AD9048KQ [ADI]
Monolithic 8-Bit Video A/D Converter; 单片8位视频A / D转换器
| 型号： | AD9048KQ |
| 厂家： | 
ADI |
| 描述： | Monolithic 8-Bit Video A/D Converter |
| 文件： | 总8页 (文件大小：111K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Monolithic 8-Bit
a
Video A/D Converter
AD9048
FUNCTIONAL BLOCK DIAGRAM
FEATURES
35 MSPS Encode Rate
16 pF Input Capacitance
550 mW Power Dissipation
Industry-Standard Pinouts
MIL-STD-883 Compliant Versions Available
12
28
23
18
NLINV
NMINV
AD9048
V
IN
1
2
R
T
R
R
1
2
APPLICATIONS
D1 (MSB)
D2
E
N
C
O
D
I
Professional Video Systems
Special Effects Generators
Electro-Optics
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
3
D3
127
128
L
A
T
C
H
4
D3
R/2
R/2
N
G
R
M
27
13
14
15
16
D5
L
O
G
I
D6
D7
C
R
R
254
255
D8 (LSB)
GENERAL DESCRIPTION
26
17
R
B
The AD9048 is an 8-bit, 35 MSPS flash converter, made on a
high speed bipolar process, which is an alternate source for the
TDC1048 unit, offers enhancements over its predecessor.
Lower power dissipation makes the AD9048 attractive for a
variety of system designs.
CONVERT
11
DGND AGND
6
10
19 25
5
8
9
7
V
V
EE
CC
Because of its wide bandwidth, it is an ideal choice for real-time
conversion of video signals. Input bandwidth is flat with no
missing codes.
Commercial versions are packaged in 28-lead DIPs; extended
temperature versions are available in ceramic DIP and ceramic
LCC packages. Both commercial units and MIL-STD-883 units
are standard products.
Clocked latching comparators, encoding logic and output buffer
registers operating at minimum rates of 35 MSPS preclude a
need for a sample-and-hold (S/H) or track-and-hold (T/H) in
most system designs using the AD9048. All digital control in-
puts and outputs are TTL compatible.
The AD9048 A/D converter is available in versions compliant
with MIL-STD-883. Refer to the Analog Devices Military Prod-
ucts Databook or current AD9048/883B data sheet for detailed
specifications.
Devices operating over two ambient temperature ranges and
with two grades of linearity are available. Linearities of either
0.5 LSB or 0.75 LSB can be ordered for a commercial range
of 0°C to +70°C or extended case temperatures of –55°C to
+125°C.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 1999
(typical with nominal supplies unless otherwise noted)
AD9048–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS1
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . 1.0 sec5
Operating Temperature Range (Ambient)
VCC to DGND . . . . . . . . . . . . . . . . . . . –0.5 V dc to +7.0 V dc
AGND to DGND . . . . . . . . . . . . . . . . –0.5 V dc to +0.5 V dc
VEE to AGND . . . . . . . . . . . . . . . . . . . +0.5 V dc to –7.0 V dc
VIN, VRT or VRB to AGND . . . . . . . . . . . . . . . . . +0.5 V to VEE
VRT to VRB . . . . . . . . . . . . . . . . . . . . . . –2.2 V dc to +2.2 V dc
CONV, NMINV or NLINV to DGND –0.5 V dc to +5.5 V dc
Applied Output Voltage to DGND . . . –0.5 V dc to +5.5 V dc2
Applied Output Current, Externally Forced
AD9048JJ/KJ/JQ/KQ . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD9048SE/SQ/TE/TQ . . . . . . . . . . . . . . –55°C to +125°C
Maximum Junction Temperature (Plastic) . . . . . . . . +150°C6
Maximum Junction Temperature (Hermetic) . . . . . . +175°C6
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 mA to +6.0 mA3, 4
(V = +5.0 V; V = –5.2 V; Differential Reference Voltage = 2.0 V, unless otherwise noted)
ELECTRICAL CHARACTERISTICS
CC
EE
Test
AD9048JJ/JQ
AD9048KJ/KQ
Min Typ Max
AD9048SE/SQ
Min Typ Max
AD9048TE/TQ
Min Typ Max
Parameter (Conditions)
Temp
Level Min Typ Max
Units
RESOLUTION
8
8
8
8
Bits
DC ACCURACY
Differential Nonlinearity
+25°C
Full
+25°C
Full
I
VI
I
VI
VI
0.4
0.6
0.75
1.0
0.75
1.0
0.3 0.5
0.75
0.4 0.5
0.75
0.4
0.6
0.75
1.0
0.75
1.0
0.3 0.5
0.75
0.4 0.5
LSB
LSB
LSB
LSB
Integral Nonlinearity
No Missing Codes
0.75
GUARANTEED
Full
GUARANTEED
GUARANTEED
GUARANTEED
INITIAL OFFSET ERROR
Top of Reference Ladder
+25°C
Full
+25°C
Full
I
VI
I
VI
V
5
12
12
8
5
12
12
8
5
12
12
8
5
12
12
8
mV
mV
mV
mV
Bottom of Reference Ladder
Offset Drift Coefficient
4
4
4
4
8
8
8
8
Full
20
20
20
20
µV/°C
ANALOG INPUT
Input Voltage Range
Full
V
–2.1;
+0.1
36
–2.1;
+0.1
36
–2.1;
+0.1
36
–2.1;
+0.1
36
V
Input Bias Current7
Input Resistance
+25°C
Full
+25°C
Full
+25°C
+25°C
I
VI
I
VI
IV
IV
60
100
60
100
60
100
60
100
µA
µA
kΩ
kΩ
pF
MHz
200
40
300
200 300
200
40
300
200 300
40
16
40
Input Capacitance
16
15
20
16
15
20
16
15
20
20
Full Power Bandwidth8
10
10
10
10
15
REFERENCE INPUT
Positive Reference Voltage9
Negative Reference Voltage9
Differential Reference Voltage
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Ladder Current
Reference Input Bandwidth
Full
Full
Full
Full
Full
Full
+25°C
V
V
V
VI
V
VI
V
0.0
–2.0
2.0
60
0.22
23
0.0
–2.0
2.0
60
0.22
23
0.0
–2.0
2.0
60
0.22
23
0.0
–2.0
2.0
60
0.22
23
V
V
V
Ω
Ω/°C
mA
MHz
30
125
40
30
125
40
30
125
40
30
125
40
10
10
10
10
DYNAMIC PERFORMANCE10
Conversion Rate
Aperture Delay
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
I
35
5
38
2.4
25
13
8
6
8
35
5
38
2.4
25
9
8
6
35
5
38
2.4
25
9
8
6
35
5
38
2.4
25
9
8
6
MHz
ns
ps
ns
ns
ns
ns
ns
ns
IV
IV
I
5
50
15
5
50
15
5
50
15
5
50
15
Aperture Uncertainty (Jitter)
Output Delay (tPD
)
11
Output Hold Time (tOH
)
I
Transient Response12
IV
V
I
I
I
20
20
20
20
Overvoltage Recovery Time13
Rise Time
8
8
8
9
14
7
9
14
7
9
14
7
9
14
7
Fall Time
Output Time Skew14
4.5
4.5
4.5
4.5
ns
NMINV and NLINV INPUTS
+0.4 V Input Current
+2.4 V Input Current
Full
Full
Full
VI
VI
VI
200
150
150
200
150
150
200
150
150
200
150
150
µA
µA
µA
+5.5 V Input Current
CONVERT INPUT
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Convert Pulsewidth (LOW)
Convert Pulsewidth (HIGH)
Full
Full
Full
Full
+25°C
+25°C
+25°C
VI
VI
VI
VI
IV
I
2.0
2.0
2.0
2.0
V
V
µA
µA
pF
ns
ns
0.8
150
500
6
0.8
150
500
6
0.8
150
500
6
0.8
150
500
6
4
4
4
4
18
10
18
10
18
10
18
10
I
–2–
REV. C
AD9048
Test
AD9048JJ/JQ
AD9048KJ/KQ
AD9048SE/SQ
Min Typ Max
AD9048TE/TQ
Min Typ Max
Parameter (Conditions)
Temp
Level Min Typ Max Min Typ Max
Units
AC LINEARITY
In-Band Harmonics
dc to 2.438 MHz15
+25°C
+25°C
I
V
47
50
48
49
55
48
47
50
48
49
55
48
dBc
dBc
dc to 9.35 MHz16
Signal-to-Noise Ratio (SNR)15
1.248 MHz Input Frequency17
2.438 MHz Input Frequency17
1.248 MHz Input Frequency18
2.438 MHz Input Frequency18
Signal-to-Noise Ratio (SNR)16
1.248 MHz Input Frequency17
9.35 MHz Input Frequency17
Noise Power Ratio (NPR)19
Differential Phase 20
+25°C
+25°C
+25°C
+25°C
I
I
I
I
43.5 44
43 44
52.5 53
52 53
45
44
54
53
46
46
55
55
43.5 44
43 44
52.5 53
52 53
45
44
54
53
46
46
55
55
dB
dB
dB
dB
+25°C
+25°C
+25°C
+25°C
+25°C
I
V
IV
IV
IV
43.5 44
40.5
36.5 39
45
46
40.5
43.5 44
40.5
36.5 39
45
46
40.5
dB
dB
dB
Degree
%
36.5 39
36.5 39
1
2
1
2
1
2
1
2
Differential Gain 20
DIGITAL OUTPUTS
Logic “1” Voltage
Full
Full
Full
VI
VI
VI
2.4
2.4
2.4
2.4
V
V
mA
Logic “0” Voltage
0.5
30
0.5
30
0.5
30
0.5
30
Short Circuit Current5
POWER SUPPLY
Positive Supply Current
+25°C
Full
+25°C
Full
+25°C
+25°C
I
VI
I
VI
V
V
34
90
56
58
110
120
34
90
56
58
110
120
34
90
56
58
110
120
34
90
56
58
110
120
mA
mA
mA
mA
mW
mW
Negative Supply Current
Nominal Power Dissipation
Reference Ladder Dissipation
550
45
550
45
550
45
550
45
NOTES
1Maximum ratings are limiting values to be applied individually, and beyond which
the serviceability of the device may be impaired. Functional operation under any of
these conditions is not necessarily implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect device reliability.
2Applied voltage must be current-limited to specified range.
3Forcing voltage must be limited to specified range.
10Outputs terminated with 40 pF and eight 10 Ω pull-up resistors.
11Interval from 50% point of leading edge CONVERT pulse to change in output
data.
12For full-scale step input, 8-bit accuracy attained in specified time.
13Recovers to 8-bit accuracy in specified time after –3 V input overvoltage.
14Output time skew includes high-to-low and low-to-high transitions as well as
bit-to-bit time skew differences.
4Current is specified as negative when flowing into the device.
5Output High; one pin to ground; one second duration.
15Measured at 20 MHz encode rate with analog input 1 dB below full scale.
16Measured at 35 MHz encode rate with analog input 1 dB below full scale.
17RMS signal to rms noise.
6Typical thermal impedances (no air flow) are as follows:
Ceramic DIP: θJA = 49°C/W; θJC = 15°C/W LCC: θJA = 69°C/W; θJC = 21°C/W
JLCC: θJA = 59°C/W; θJC = 19°C/W
18Peak signal to rms noise.
To calculate junction temperature (TJ), use power dissipation (PD) and thermal
impedance: TJ = PD (θJA) + TAMBIENT = PD (θJC) = + TCASE.
7Measured with VIN = 0 V and CONVERT low (sampling mode).
8Determined by beat frequency testing for no missing codes.
9VRT ≥ VRB under all circumstances.
19DC to 8 MHz noise bandwidth with 1.248 MHz slot; four sigma loading;
20 MHz encode.
20Clock frequency = 4 × NTSC = 14.32 MHz. Measured with 40-IRE
modulated ramp.
Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
Test Level I – 100% production tested.
Test Level II – 100% production tested at +25°C and
sample tested at specific temperatures.
Test Level III – Sample tested only.
Test Level IV – Parameter is guaranteed by design and
characterization testing.
Test Level V – Parameter is a typical value only.
Test Level VI – All devices are 100% production tested at
+25°C. 100% production tested at tempera-
ture extremes for military temperature de-
vices; sample tested at temperature extremes
for commercial/industrial devices.
REV. C
–3–
AD9048
ORDERING GUIDE
PIN DESIGNATIONS
DIP (Q Package)
Package
Option1
Model
Linearity
Temperature
(MSB) D1
D2
1
2
28 NMINV
AD9048JJ
0.75 LSB
0.5 LSB
0.75 LSB
0.5 LSB
0.75 LSB
0.5 LSB
0.75 LSB
0.5 LSB
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
J-28A
J-28A
Q-28
Q-28
E-28A
E-28A
Q-28
Q-28
R
27
26
25
24
23
22
21
20
M
B
AD9048KJ
AD9048JQ
AD9048KQ
AD9048SE2
AD9048TE2
AD9048SQ2
AD9048TQ2
D3
3
R
D4
4
AGND
NC
DGND
5
AD9048
TOP VIEW
(Not to Scale)
V
6
V
CC
IN
V
7
NC
NC
NC
EE
V
8
EE
V
9
EE
V
10
11
12
13
14
19 AGND
18
NOTES
CC
1E = Leadless Ceramic Chip Carrier; J = J-Leaded Ceramic; Q = Cerdip.
2For temperature designation only. MIL-STD-883 and Standard Military
Drawing available.
DGND
NLINV
D5
R
T
17 CONVERT
16 D8 (LSB)
D6
D7
15
NC = NO CONNECT
MECHANICAL INFORMATION
LCC (E Package)
Die Dimensions . . . . . . . . . . . . . . . . 140 × 137 × 21 (±2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic
Bond Wire . . . . . . . . . . . . . . . .1 mil Gold; Gold Ball Bonding
4
3
1
28 27 26
2
25 AGND
NC
5
6
DGND
V
24
23 V
CC
V
7
IN
EE
AD9048
TOP VIEW
(Not to Scale)
22 NC
V
8
EE
V
21 NC
9
EE
V
20 NC
10
11
CC
AGND
AIN
AGND
19 AGND
DGND
12
13 14 15 16 17 18
RLOW
RMID
RTOP
NC = NO CONNECT
NMINV
CONV
D8
J-Leaded Ceramic (J Package)
MSB
D2
D7
D3
D6
25 24 23 22 21 20 19
26
27
28
1
18
17
16
15
14
13
12
R
R
R
T
B
D4
D5
CONVERT
D8 (LSB)
D7
M
NLINV
DGND
NMINV
AD9048
(MSB) D1
DGND
TOP VIEW
(Not to Scale)
2
D6
D2
D3
D4
3
D5
VCC VCC
VEE VEE VEE
VCC VCC DGND
4
NLINV
5
6
7
8
9
10 11
Bonding Diagram
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9048 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. C
AD9048
PIN FUNCTION DESCRIPTIONS
Pin
Description
Pin
Description
RB
Most negative reference voltage for internal
reference ladder.
D1–D8
Eight digital outputs. D1 (MSB) is the most
significant bit of the digital output word;
D8 (LSB) is the least significant bit.
RM
RT
Midpoint tap on internal reference ladder.
AGND
DGND
One of two analog ground returns. Both
grounds should be connected together and to
low impedance ground plane near the AD9048.
Most positive reference voltage for internal
reference ladder.
VIN
Analog input signal pin.
One of two digital ground returns. Both
grounds should be connected together and to
low impedance ground plane near the AD9048.
NMINV
“Not Most Significant Bit Invert.” In normal
operation, this pin floats high; logic LOW at
NMINV inverts most significant bit of digital
output word [D1 (MSB)].
VCC
VEE
Positive supply terminals; nominally +5.0 V.
Negative supply terminals; nominally –5.2 V.
NLINV
“Not Least Significant Bit Invert.” In normal
operation, this pin floats high; logic LOW at
NLINV inverts the seven least significant bits
of the digital output word.
CONVERT Input for conversion signal; sample of analog
input signal taken on rising edge of this pulse.
Burn-In Diagram
REV. C
–5–
AD9048
THEORY OF OPERATION
System timing, which provides details on delays through the
AD9048 as well as the relationships of various timing events, is
shown in Figure 2.
Refer to the Functional Block Diagram of the AD9048. The
AD9048 comprises three functional sections: a comparator
array, encoding logic and output latches.
Dynamic performance of the AD9048, i.e., typical signal-to-
noise ratio, is illustrated in Figures 3 and 4.
Within the array, the analog input signal to be digitized is com-
pared with 255 reference voltages. The outputs of all compara-
tors whose references are below the input signal level will be
high; outputs whose references are above that level will be low.
The n-of-255 code that results from this comparison is applied
to the encoding logic where it is converted into binary coding.
When it is inverted with dc signals applied to the NLINV and/or
NMINV pins, it becomes twos complement.
After encoding, the signal is applied to the output latch circuits
where it is held constant between updates controlled by the
application of CONVERT pulses.
The AD9048 uses strobed latching comparators in which com-
parator outputs are either high or low, as dictated by the analog
input level. Data appearing at the output pins have a pipeline
delay of one encode cycle.
Input signal levels between the references applied to RT (Pin 18)
and RB (Pin 26) will appear at the output as binary numbers
between 0 and 255, inclusive. Signals outside that range will
show up as either full-scale positive or full-scale negative out-
puts. No damage will occur to the AD9048 as long as the input
is within the voltage range of VEE to +0.5 V.
The significantly reduced input capacitance of the AD9048
lowers the drive requirements of the input buffer/amplifier and
also induces much smaller phase shift in the analog input signal.
Applications that depend on controlled phase shift at the con-
verter input can benefit from using the AD9048 because of its
inherently lower phase shift.
The CONVERT, analog input and digital output circuits are
shown in Figure 1.
Figure 1. Input/Output Circuits
Figure 2. Timing Diagram
–6–
REV. C
AD9048
Ceramic 0.1 µF decoupling capacitors should be placed as closely
as possible to the supply pins of the AD9048. For decoupling
low frequency signals, use 10 µF tantalum capacitors, also con-
nected as closely as practical to voltage supply pins.
Within the AD9048, reference currents may vary because of
coupling between the clock and input signals. As a result, it is
important that the ends of the reference ladder, RT (Pin 18) and
RB (Pin 28), be connected to low impedances (as measured
from ground).
If the AD9048 is being used in a circuit in which the reference
is not varied, a bypass capacitor to ground is strongly recom-
mended. In applications that use varying references, they must
be driven from a low impedance source.
Figure 3. Dynamic Performance (20 MHz Encode Rate)
Figure 4. Dynamic Performance (35 MHz Encode Rate)
LAYOUT SUGGESTIONS
Designs that use the AD9048 or any other high speed device
must follow some basic layout rules to ensure optimum
performance.
The first requirement is to have a large, low impedance ground
plane under and around the converter. If the system uses sepa-
rate analog and digital grounds, both should be solidly con-
nected together, and to the ground plane, as closely to the
AD9048 as practical to avoid ground loop currents.
Figure 5. Typical Connections
REV. C
–7–
AD9048
Table I. Truth Table
Binary
Offset Twos
Complement
Step
Range
True
Inverted
True
Inverted
–2.000 V FS
7.8431 mV Step 8.000 mV Step
–2.0480 V FS
NMINV = 1
NLINV = 1
0
0
0
1
1
0
000
001
•
0.0000 V
–0.0078 V
•
•
0.0000 V
–0.0080 V
•
•
00000000
00000001
•
•
11111111
11111110
•
•
10000000
10000001
•
•
01111111
01111110
•
•
•
•
•
•
•
•
•
•
127
128
129
•
–0.9961 V
–1.0039 V
–1.0118 V
•
–1.0160 V
–1.0240 V
–1.0320 V
•
01111111
10000000
10000001
•
10000000
01111111
01111110
•
11111111
00000000
00000001
•
00000000
11111111
11111110
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
254
255
–1.9921 V
–2.0000 V
–2.0320 V
–2.0400 V
11111110
11111111
00000001
00000000
01111110
01111111
10000001
10000000
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Ceramic Side-Brazed DIP
28-Terminal Leadless Chip Carrier
0.100 (2.54)1
0.055 (1.40)
28
15
0.045 (1.14)
0.064 (1.63)
0.075 (1.91) REF
0.610 (15.24)
0.500 (14.43)
26
25
18
19
PIN 1
0.028 (0.71)
1
14
0.12 (3.05)
0.06 (1.53)
0.022 (0.56)
0.458 (11.63)
28
0.050 ±0.005
(1.27 ±0.13)
1.418 (36.02)
1.38 (35.06)
0.442 (11.23)
SQ
1
NO 1
PIN INDEX
BOTTOM
VIEW
0.225 (5.72)
MAX
12
5
4
0.015 (0.305)
11
0.175 (4.45)
0.125 (3.18)
0.008 (0.203)
0.020 (0.51) x 45°
REF 1 PLC
SEATING
PLANE
0.620 (15.4)
0.040 (1.02) x 45°
REF 3 PLCS
0.023 (0.508)
0.014 (0.381)
0.065 (1.66)
0.105 (2.67)
0.095 (2.42)
0.590 (14.74)
0.038 (0.965)
NOTES
1
LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH
THIS DIMENSION CONTROLS THE OVERALL PACKAGE THICKNESS
2
APPLIES TO ALL FOUR SIDES
LEADS ARE GOLD PLATED (50 MICROINCHES MIN) KOVAR OR ALLOY 42
ALL TERMINALS ARE GOLD PLATED
28-Lead J-Lead Package
0.171 (4.34)
MAX
0.450 ±0.006
(11.43 ±0.152)
0.039 ±0.005
SQ
(0.991 ±0.127)
25
26
19
18
0.028 ±0.002
(0.711 ±0.051)
0.050
(1.27)
PIN 1
0.300
(7.62)
TYP
TOP VIEW
(PINS DOWN)
0.420 ±0.010
(10.668 ±0.254)
BOTTOM VIEW
BSC
0.019 ±0.002
(0.483 ±0.051)
12
4
5
11
0.006 ±0.0006
(0.152 ±0.015)
0.488 ±0.010
(11.43 ±0.254)
SQ
0.022 ±0.003
(0.559 ±0.076)
0.102 ±0.010
(1.448 ±0.254)
–8–
REV. C
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