AD9082 [ADI]
MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC;
| 型号： | AD9082 |
| 厂家： | 
ADI |
| 描述： | MxFE Quad, 16-Bit, 12 GSPS RF DAC and Dual, 12-Bit, 6 GSPS RF ADC |
| 文件： | 总33页 (文件大小：717K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MxFE Quad, 16-Bit, 12 GSPS RF DAC
and Dual, 12-Bit, 6 GSPS RF ADC
AD9082
Data Sheet
Auxiliary features
FEATURES
Fast frequency hopping
Direct digital synthesis (DDS)
Flexible reconfigurable common platform design
4 DACs and 2 ADCs (4D2A)
Low latency digital loopback mode (ADC to DAC)
ADC clock driver with selectable divide ratios
Power amplifier downstream protection circuitry
On-chip temperature monitoring unit
Flexible GPIOx pins
TDD power savings option
SERDES JESD204B/JESD204C interface, 16 lanes up to 16.22 Gbps
8 lanes per DACs and ADCs
Supports single, dual, and quad band
Maximum DAC/ADC sample rate up to 12 GSPS/6 GSPS
DAC to ADC sample rate ratios of 1, 2, 3, and 4
ADC and DAC datapath bypass option
Analog bandwidth to 8 GHz
Full-scale output current range, ac coupling: 7 mA to 40 mA
On-chip PLL with multichip synchronization
External RFCLK input option
JESD204B compatible with the maximum 15.5 Gbps lane rate
JESD204C compatible with the maximum 16.22 Gbps lane rate
Sample and bit repeat mode for lane rate matching
Total power consumption: 11.45 W typical
15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch
ADC ac performance at 6 GSPS
Full-scale input voltage: 1.475 V p-p
Full-scale sine wave input power: 4.4 dBm
Noise density: −153 dBFS/Hz
Noise figure: 25.3 dB
HD2: −65.2 dBFS at 2.7 GHz
HD3: −70.8 dBFS at 2.7 GHz
APPLICATIONS
Wireless communications infrastructure
Microwave point-to-point, E-band and 5G mmWave
Broadband communications systems
DOCSIS 3.1 and 4.0 CMTS
Phased array radar and electronic warfare
Electronic test and measurement systems
Worst other (excluding HD2 and HD3): −68.5 dBFS at 2.7 GHz
DAC ac performance at 3.7 GHz output
2-tone IMD3 (−7 dBFS per tone): −78.9 dBc
NSD, single-tone, fDAC = 12 GSPS: −155.1 dBc/Hz
SFDR, single-tone, fDAC = 12 GSPS: −70 dBc
Versatile digital features
Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
Selectable interpolation and decimation filters
Configurable DDC and DUC
8 fine complex DUCs and 4 coarse complex DUCs
8 fine complex DDCs and 4 coarse complex DDCs
48-bit NCO per DUC/DDC
Option to bypass fine and coarse DUC/DDC
Programmable 192-tap PFIR filter for receive equalization
Supports 4 different profile settings loaded via GPIO
Programable delay per data path
GENERAL DESCRIPTION
The mixed signal front-end (MxFE®) is a highly integrated device
with a 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog
converter (DAC) core, and 12-bit, 6 GSPS rate, RF analog-to-
digital converter (ADC) core. The AD9082 supports four
transmitter channels and two receiver channels. The AD9082
is well suited for applications requiring both wideband ADCs
and DACs to process signal(s) having wide instantaneous
bandwidth. The device features a 16 lane, 16.22 Gbps JESD204C
or 15.5 Gbps JESD204B data transceiver port, an on-chip clock
multiplier, and a digital signal processing (DSP) capability
targeted at either wideband or multiband, direct to RF
applications. The AD9082 also features a bypass mode that
allows the full bandwidth capability of the ADC and/or DAC
cores to bypass the DSP datapaths. The device also features low
latency loopback and frequency hopping modes targeted at
phase array radar system and electronic warfare applications.
Receive AGC support
Fast detect with low latency for fast AGC control
Signal monitor for slow AGC control
Dedicated AGC support pins
Transmit DPD support
Fine DUC channel gain control and delay adjust
Coarse DDC delay adjust for DPD observation path
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice.
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Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2020 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9082
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
DAC AC Specifications................................................................9
ADC AC Specifications............................................................. 12
Timing Specifications................................................................ 13
Absolute Maximum Ratings......................................................... 15
Reflow Profile ............................................................................. 15
Thermal Resistance.................................................................... 15
ESD Caution ............................................................................... 15
Pin Configuration and Function Descriptions .......................... 16
Typical Performance Characteristics .......................................... 21
DAC ............................................................................................. 21
ADC ............................................................................................. 26
Theory of Operation ...................................................................... 32
Outline Dimensions....................................................................... 33
Ordering Guide .......................................................................... 33
Applications ...................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications .................................................................................... 4
Recommended Operating Conditions ...................................... 4
DC Specifications ......................................................................... 4
DAC and ADC Sampling Specifications................................... 5
Power Consumption.................................................................... 6
Clock Input and Phase-Locked Loop (PLL) Frequency
Specifications ................................................................................ 6
Input and Output Data Rates and Signal Bandwidth
Specifications ................................................................................ 7
JESD204B and JESD204C Interface Electrical and Speed
Specifications ................................................................................ 8
CMOS Pin Specifications............................................................ 9
REVISION HISTORY
9/2020—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 3
Changes to Figure 5........................................................................ 16
Changes to Table 14....................................................................... 17
6/2020—Revision 0: Initial Version
Rev. A | Page 2 of 33
Data Sheet
AD9082
FUNCTIONAL BLOCK DIAGRAM
AD9082
DAC0P
FINE DIGITAL
DELAY
PA
PROTECT
COARSE DIGITAL
UPCONVERSION
RAMP
UP/DOWN
DAC0
UPCONVERSION
ADJUST
SERDIN0±
SERDIN1±
SERDIN2±
SERDIN3±
SERDIN4±
SERDIN5±
SERDIN6±
SERDIN7±
DAC0N
FINE DIGITAL
UPCONVERSION
DELAY
ADJUST
DAC1P
DAC1N
ISET
FINE DIGITAL
DELAY
PA
COARSE DIGITAL
UPCONVERSION
RAMP
DAC1
UPCONVERSION
ADJUST
PROTECT
UP/DOWN
FINE DIGITAL
UPCONVERSION
DELAY
ADJUST
DAC
BIAS
FINE DIGITAL
UPCONVERSION
DELAY
ADJUST
DAC2P
DAC2N
PA
PROTECT
COARSE DIGITAL
UPCONVERSION
RAMP
UP/DOWN
FINE DIGITAL
UPCONVERSION
DELAY
ADJUST
DAC2
DAC3
FINE DIGITAL
UPCONVERSION
DELAY
ADJUST
DAC3P
DAC3N
PA
PROTECT
COARSE DIGITAL
UPCONVERSION
RAMP
UP/DOWN
FINE DIGITAL
UPCONVERSION
DELAY
ADJUST
SYNCOUTB0±
SYNCOUTB1±
DAC
CLOCK
LOOPBACK
MUX
VCM0
COARSE DIGITAL
DOWNCONVERSION
FINE DIGITAL
DOWNCONVERSION
DELAY
ADJUST
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SERDOUT4±
SERDOUT5±
SERDOUT6±
SERDOUT7±
ADC0P
ADC0N
FINE DIGITAL
DELAY
DOWNCONVERSION
ADJUST
ADC0
FINE DIGITAL
DOWNCONVERSION
DELAY
ADJUST
COARSE DIGITAL
ADCx_FD1
ADCx_FD2
ADCx_SMON1
ADCx_SMON0
DOWNCONVERSION
FINE DIGITAL
DOWNCONVERSION
DELAY
ADJUST
FAST DETECT
SIGNAL MONITOR
FINE DIGITAL
DOWNCONVERSION
DELAY
ADJUST
ADC1P
ADC1N
COARSE DIGITAL
DOWNCONVERSION
FINE DIGITAL
DOWNCONVERSION
DELAY
ADJUST
ADC1
FINE DIGITAL
DOWNCONVERSION
DELAY
ADJUST
VCM1
COARSE DIGITAL
DOWNCONVERSION
FINE DIGITAL
DOWNCONVERSION
DELAY
ADJUST
÷1, ÷2, ÷3,
OR ÷4
VDD1_NVG
NVG1_OUT
VNN1
TO DAC
CLOCK
SYNCINB0±
SYNCINB1±
PEAK VALUE
CLOCK DISTRIBUTION
AND
CONTROL LOGIC
ALIGN
DETECT
SYNCRONIZATION
RXEN0
RXEN1
LOGIC
BVNN1
BVNN2
PLL
TXEN0
TXEN1
BVDD3
MICROPROCESSOR
GPIO MUX
SPI
SYSREF
CLOCK
RECEIVER
CLOCK
RECEIVER
CLOCK
DRIVER
Figure 1.
Rev. A | Page 3 of 33
AD9082
Data Sheet
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Successful DAC calibration is required during the device initialization phase that occurs shortly after power-up to ensure long-term
reliability of the DAC core circuitry. Refer to UG-1578, the device user guide, for more information on device initialization.
Table 1.
Parameter
Min
Typ
Max
Unit
OPERATING JUNCTION TEMPERATURE (TJ)
ANALOG SUPPLY VOLTAGE RANGE
AVDD2, BVDD2, RVDD2
AVDD1, AVDD1_ADC, CLKVDD1, FVDD1, VDD1_NVG1
DIGITAL SUPPLY VOLTAGE RANGE
DVDD1, DVDD1_RT, DCLKVDD1, DAVDD1
DVDD1P8
120
°C
1.9
0.95
2.0
1.0
2.1
1.05
V
V
0.95
1.7
1.0
1.8
1.05
2.1
V
V
SERIALIZER/DESERIALIZER (SERDES) SUPPLY VOLTAGE RANGE
SVDD2_PLL
SVDD1, SVDD1_PLL
1.9
0.95
2.0
1.0
2.1
1.05
V
V
DC SPECIFICATIONS
Nominal supplies with DAC output full-scale current (IOUTFS) = 26 mA, unless otherwise noted. For the minimum and maximum values,
TJ = −40°C to +120°C, and for the typical values, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min Typ
Max Unit
DAC RESOLUTION
ADC RESOLUTION
DAC ACCURACY
Gain Error
Gain Matching
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ADC ACCURACY
No Missing Codes
Offset Error
16
12
Bit
Bit
1.5
0.1
8.0
3.5
%FSR
%FSR
LSB
Shuffling disabled
Shuffling disabled
LSB
Guaranteed
0.57
0.26
5.34
1.06
0.32
1.38
%FSR
%FSR
%FSR
%FSR
LSB
Offset Matching
Gain Error
Gain Matching
DNL
Dithering enabled
Dithering enabled
INL
LSB
DAC ANALOG OUTPUTS
Full-Scale Output Current Range
AC Coupling
DACxP and DACxN
AC coupling, setting resistance (RSET) = 5 kΩ
Output common-mode voltage (VCM) = 0 V
VCM = 0.3 V
7
26
20
40
mA
mA
DC Coupling
Full-Scale Sinewave Output Power with
AC Coupling1
Ideal 2:1 balun interface to 50 Ω
IOUTFS = 26 mA
IOUTFS = 40 mA
Common-Mode Output Voltage (VCMOUT
3.3
7
0
dBm
dBm
V
)
Differential Impedance
100
Ω
Rev. A | Page 4 of 33
Data Sheet
AD9082
Parameter
Test Conditions/Comments
Min Typ
1.475
Max Unit
ADC ANALOG INPUTS
Differential Input Voltage
Full-Scale Sine Wave Input Power
ADCxP and ADCxN
V p-p
dBm
Input power level resulting 0 dBFS tone level on fast
Fourier transform (FFT)
4.4
Common-Mode Input Voltage (VCMIN)
Differential Input
Resistance
Capacitance
Return Loss
AC-coupled, equal to voltage at VCMx for ADCx input
1
V
100
0.4
−4.3
−3.6
−2.9
Ω
pF
dB
dB
dB
<2.7 GHz
2.7 GHz to 3.8 GHz
3.8 GHz to 5.4 GHz
CLKINP and CLKINN
CLOCK INPUTS
Differential Input Power
Direct RF Clock
CLK Synchronization Enabled
Differential Input Impedance1
Common-Mode Voltage
ADC CLOCK OUTPUTS
0
0
dBm
dBm
Ω//pF
V
100//0.3
0.5
AC coupled
ADCDRVP and ADCDRVN
Differential Output Voltage Magnitude2 1.5 GHz
740
690
640
490
100
0.5
mV p-p
mV p-p
mV p-p
mV p-p
Ω
2.0 GHz
3 GHz
6 GHz
Differential Output Resistance
Common-Mode Voltage
AC coupled
V
1 The actual measured full-scale power is frequency dependent due to DAC sinc response, impedance mismatch loss, and balun insertion loss.
2 Measured with differential 100 Ω load and less than 2 mm of printed circuit board (PCB) trace from package ball.
DAC AND ADC SAMPLING SPECIFICATIONS
Nominal supplies. For the minimum and maximum values, TJ = −40°C to +120°C and 5% of nominal supply. For the typical values, TA
= 25°C, unless otherwise noted.
Table 3.
Parameter
DAC UPDATE RATE1
Minimum
Maximum
ADC SAMPLE RATE1
Minimum
Maximum
Aperture Jitter2
Min
12
6
Typ
Max
Unit
2.9
GSPS
GSPS
1.45
GSPS
GSPS
fs rms
65
1 Pertains to the update rate of the DAC and ADC cores independent of datapath and JESD mode configuration.
2 Measured using a signal-to-noise ratio (SNR) degradation method with the DAC disabled, clock divider = 1, ADC frequency (fADC) = 6 GSPS, and input frequency (fIN) = 5.55 GHz.
Rev. A | Page 5 of 33
AD9082
Data Sheet
POWER CONSUMPTION
Typical at nominal supplies and maximum at 5% supplies. DAC datapath with a complex I/Q data rate frequency (fIQ_DATA) = 375 MSPS and
DAC frequency (fDAC) of 12 GSPS with interpolate by 32× with JRx mode of 16B (L = 8, M = 16). ADC datapath with fIQ_DATA = 375 MSPS and
fADC of 6 GSPS with decimate by 16× with JTx mode of 17B (L = 8, M = 16). For the minimum and maximum values, TJ = −40°C to +120°C.
For the typical values, TA = 25°C, unless otherwise noted.
See the UG-1578 user guide for further information on the JESDB or JESDC mode configurations and detailed settings referred to
throughout this data sheet.
Table 4.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
CURRENTS
AVDD2 (IAVDD2
)
2.0 V supply
2.0 V supply
2.0 V supply
2.0 V supply total power dissipation
1.0 V supply
1.0 V supply
1.0 V supply
1.0 V supply
1.0 V supply
1.0 V supply
1.0 V supply
1.0 V supply
1.0 V supply
1.0 V supply
1.0 V supply total power dissipation
1.8 V supply
190
292
44
1.05
43
1541
1700
96
72.5
290
985
3555
461
1626
10.4
6.8
BVDD2 (IBVDD2) + RVDD2 (IRVDD2
AVDD2_PLL (IAVDD2__PLL) + SVDD2_PLL (ISVDD2__PLL
Power Dissipation for 2 V Supplies
PLLCLKVDD1 (IPLLCLKVDD1
AVDD1 (IAVDD1) + DCLKVDD1(IDCLKVDD1
AVDD1_ADC (IAVDD1_ADC
CLKVDD1 (ICLKVDD1
FVDD1 (IFVDD1
VDD1_NVG (IVDD1_NVG
DAVDD1 (IDAVDD1
DVDD1 (IDVDD1
DVDD1_RT (IDVDD1_RT
)
mA
mA
W
)
)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
W
)
)
)
)
)
)
)
)
SVDD1 (ISVDD1) + SVDD1_PLL (ISVDD1_PLL
Power Dissipation for 1 V Supplies
DVDD1P8 (IDVDD1P8
)
)
mA
W
Total Power Dissipation
Total power dissipation of 2 and 1 V supplies
11.45
CLOCK INPUT AND PHASE-LOCKED LOOP (PLL) FREQUENCY SPECIFICATIONS
For the minimum and maximum values, TJ = −40°C to +120°C and 5% of nominal supply, unless otherwise noted.
Table 5.
Parameter
Test Conditions/Comments
Min Typ Max
Unit
PLL VOLTAGE CONTROLLED OSCILLATOR (VCO) FREQUENCY RANGES
VCO Output
Divide by 1
Divide by 2
Divide by 4
6
3
1.5
25
12
6
3
GSPS
GSPS
GSPS
MHz
PHASE FREQUENCY DETECT INPUT FREQUENCY RANGES
750
CLOCK INPUTS (CLKINP, CLKINN) FREQUENCY RANGES
PLL Off
PLL On
1.45
25
50
75
100
12
750
1500 MHz
2250 MHz
3000 MHz
GHz
MHz
M divider set to divide by 1
M divider set to divide by 2
M divider set to divide by 3
M divider set to divide by 4
Rev. A | Page 6 of 33
Data Sheet
AD9082
INPUT AND OUTPUT DATA RATES AND SIGNAL BANDWIDTH SPECIFICATIONS
For the minimum and maximum values, TJ = −40°C to +120°C and 5% of nominal supply, unless otherwise noted.
Table 6.
Parameter1
Test Conditions/Comments
Min
Typ Max
Unit
DATA RATE PER INPUT CHANNEL
Channel datapaths bypassed (1× interpolation),
single DAC mode only, 16-bit resolution
(JR mode = 19C)
12,000 MSPS
Channel datapaths bypassed (1× interpolation),
dual DAC or dual ADC, 16-bit resolution
(JRxmode = 18C and JTx mode = 28C)
Channel datapaths bypassed (1× interpolation),
quad DAC mode , 12-bit resolution (JRx mode =
35C)
6000
4000
MSPS
MSPS
1 complex channel enabled, 16-bit resolution
(JRx mode = 18C and JTx mode = 19C)
2 complex channels enabled, 12-bit resolution
(JRx mode = 23C and JTx mode = 27C)
4 complex channels enabled, 12-bit resolution
(JRx mode = 24C and JTx mode = 26C)
8 complex channels enabled, 16-bit resolution
(JRx mode = 16C and JTx mode = 16C)
6000
4000
2000
750
MSPS
MSPS
MSPS
MSPS
COMPLEX SIGNAL BANDWIDTH PER CHANNEL
1 complex channel enabled (0.8 × data
frequency (fDATA))
4800
MHz
2 complex channels enabled (0.8 × fDATA
4 complex channels enabled (0.8 × fDATA
8 complex channels enabled (0.8 × fDATA
)
)
)
3200
1600
600
MHz
MHz
MHz
MAXIMUM NUMERICALLY CONTROLLED OSCILLATOR (NCO)
CLOCK RATE
Channel NCO
Main DAC NCO
Main ADC NCO
1500
12
6
MHz
GHz
GHz
MAXIMUM NCO SHIFT FREQUENCY RANGE
Channel NCO
Channel summing node = 1.5 GHz,
channel interpolation rate > 1×
−750
+750
MHz
Main DAC NCO
Main ADC NCO
fDAC = 12 GHz, main interpolation rate > 1×
fADC = 6 GHz, main decimation rate > 1×
Maximum NCO output frequency × 0.8
−6
−3
+6
+3
GHz
GHz
MHz
MAXIMUM FREQUENCY SPACING ACROSS INPUT CHANNELS
1200
1 The values listed for these parameters are the maximum possible when considering all JESD204B modes of operation. Some modes are more limiting, based on other
parameters.
Rev. A | Page 7 of 33
AD9082
Data Sheet
JESD204B AND JESD204C INTERFACE ELECTRICAL AND SPEED SPECIFICATIONS
Nominal supplies. For the minimum and maximum values, TJ = −40°C to +120°C and 5% of nominal supply, and for the typical values,
TA = 25°C, unless otherwise noted.
Table 7.
Parameter
Test Conditions/Comments
Serial lane rate (bit repeat option disabled) 8.11
168.35
Min
Typ
Max
15.5
64.5
Unit
Gbps
ps
JESD204B SERIAL INTERFACE RATE
Unit Interval
JESD204C SERIAL INTERFACE RATE
Unit Interval
Serial lane rate (bit repeat option disabled) 8.11
16.22
61.65
Gbps
ps
123.3
JESD204x DATA INPUTS
Differential Voltage, RVDIFF
Differential Impedance, ZRDIFF
Termination Voltage, VTT
JESD204x DATA OUTPUTS
Logic Compliance
Differential Output Voltage
Differential Termination Impedance
Rise Time, tR
SERDINx , where x = 0 to 7
800
98
0.97
mV p-p
Ω
V
At dc
AC-coupled
SERDOUTx , where x = 0 to 7
JESD204B/JESD204C compliant
675
Maximum strength
mV p-p
Ω
ps
ps
80
108
18
18
120
20% to 80% into 100 Ω load
20% to 80% into 100 Ω load
Fall Time, tF
SYSREFP AND SYSREFN INPUTS
Logic Compliance
LVDS/LVPECL1
Differential Input Voltage
Input Common-Mode Voltage Range DC-coupled
Input Reference, RIN (Differential)
0.7
1.9
2
V p-p
V
Ω
0.675
100
1
Input Capacitance (Differential)
pF
SYNCxOUTB OUTPUTS2
Output Differential Voltage, VOD
Output Offset Voltage, VOS
SYNCxOUTB+
Where x = 0 or1
Driving 100 Ω differential load
400
DVDD1P8/2
Refer to CMOS pin specification
mV
V
CMOS output option
Where x = 0 or1
SYNCxINB INPUT2
Logic Compliance
LVDS
Differential Input Voltage
Input Common-Mode Voltage
RIN (Differential)
0.7
0.675
18
1.9
2
mV p-p
V
kΩ
DC-coupled
18
Input Capacitance (Differential)
SYNCxINB+ INPUT
1
1
pF
CMOS input option
Refer to CMOS pin specification
1 LVDS means low voltage differential signaling and LVPECL means low voltage positive/pseudo emitter-coupled logic.
2 IEEE 1596.3 Standard LVDS compatible.
Rev. A | Page 8 of 33
Data Sheet
AD9082
CMOS PIN SPECIFICATIONS
Nominal supplies. For the minimum and maximum values, TJ = −40°C to +120°C and DVDD1P8 = 2.0 V 5%, and for the typical values,
TA = 25°C, unless otherwise noted.
Table 8.
Parameter
Symbol Test Conditions/Comments
SDIO, SCLK, CSB, RESETB, RXEN0, RXEN1,
Min
Typ
Max
Unit
INPUTS
TXEN0, TXEN1, SYNC0INB , SYNC1INB ,
and GPIOx
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
OUTPUTS
VIH
VIL
0.70 × DVDD1P8
V
V
kΩ
0.3 × DVDD1P8
30
SDIO, SDO, GPIOx, ADCx_FDx, SYNC0INB ,
and SYNC1INB , 4 mA load
Logic 1 Voltage
Logic 0 Voltage
VOH
VOL
DVDD1P8 − 0.45
1.45
V
V
0.45
0.35
INTERRUPT OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
IRQB_0 and IRQB_1, pull-up resistor of 5 kΩ
VOH
VOL
V
V
DAC AC SPECIFICATIONS
Nominal supplies with TA = 25°C. fIQ_DATA = 1500 MSPS. Specifications represent the average of all four DAC channels with the DAC
OUTFS = 26 mA and ADC powered down, unless otherwise noted.
I
Table 9.
Parameter
Test Conditions/Comments
Min Typ
Max Unit
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
Single-Tone, fDAC = 12 GSPS
Output Frequency (fOUT) = 100 MHz
fOUT = 500 MHz
−7 dBFS, shuffle enabled
−70.7
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−69.2
−69.7
−68.5
−73.1
−70
fOUT = 900 MHz
fOUT = 1900 MHz
fOUT = 2600 MHz
fOUT = 3700 MHz
fOUT = 4500 MHz
−66.5
Single-Tone, fDAC = 9 GSPS
fOUT = 100 MHz
fOUT = 500 MHz
fOUT = 900 MHz
fOUT = 1900 MHz
fOUT = 2600 MHz
fOUT = 3700 MHz
Single-Tone, fDAC = 6 GSPS
fOUT = 100 MHz
fOUT = 500 MHz
−7 dBFS, shuffle enabled
−7 dBFS, shuffle enabled
−74.4
−72.5
−72.50
−71.0
−71.5
−69.1
dBc
dBc
dBc
dBc
dBc
dBc
−77
dBc
dBc
dBc
dBc
−75.8
−75.3
−75.3
fOUT = 900 MHz
fOUT = 1900 MHz
SINGLE-BAND APPLICATION, BAND 3
Windowed SFDR Nonharmonics
In Band
fDAC =9 GSPS, 500 MHz reference clock
−7 dBFS, shuffle enabled
1842.5 MHz 37.5 MHz pass-band region
1842.5 MHz, 200 MHz pass-band region
−95.5
−80.3
dBc
dBc
DPD Band
Rev. A | Page 9 of 33
AD9082
Data Sheet
Parameter
Test Conditions/Comments
Min Typ
Max Unit
ADJACENT CHANNEL LEAKAGE RATIO
Single Carrier 20 MHz LTE Downlink Test Vector
fDAC = 12 GSPS
−1 dBFS digital back off, 256QAM
fOUT = 1840 MHz
fOUT = 2650 MHz
fOUT = 3500 MHz
fOUT = 1900 MHz
fOUT = 2650 MHz
fOUT = 750 MHz
fOUT = 1840 MHz
77.3
76.3
73.3
77.0
77.1
78.8
77.3
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fDAC = 9 GSPS
fDAC = 6 GSPS
THIRD-ORDER INTERMODULATION DISTORTION (IMD3)
fDAC = 12 GSPS
Two tone test, −6 dBFS per tone, 1 MHz spacing
fOUT = 1900 MHz
fOUT = 2600 MHz
fOUT = 3700 MHz
fOUT = 1900 MHz
fOUT = 2600 MHz
fOUT = 900 MHz
fOUT = 1900 MHz
−74.5
−75.5
−77
−83
−86
dBc
dBc
dBc
dBc
dBc
dBc
dBc
fDAC = 9 GSPS
fDAC = 6 GSPS
−88.4
−86.3
NOISE SPECTRAL DENSITY (NSD)
0 dBFS, NSD measurement taken at
10% away from fOUT, shuffle off
Single-Tone, fDAC = 12 GSPS
fOUT = 150 MHz
−168
dBc/Hz
fOUT = 500 MHz
fOUT = 950 MHz
fOUT = 1840 MHz
fOUT = 2650 MHz
fOUT = 3700 MHz
fOUT = 4500 MHz
−166.7
−164.8
−161.6
−160
−155.1
−154.2
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Single-Tone, fDAC = 9 GSPS
fOUT = 150 MHz
fOUT = 500 MHz
fOUT = 950 MHz
fOUT = 1840 MHz
−168
−166
−164
−160.2
−158.4
−153.5
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fOUT = 2650 MHz
fOUT = 3700 MHz
Single-Tone, fDAC = 6 GSPS
fOUT = 150 MHz
fOUT = 500 MHz
fOUT = 950 MHz
fOUT = 1840 MHz
−168
−165
−163
−159
−156.8
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fOUT = 2650 MHz
SINGLE SIDEBAND PHASE NOISE OFFSET (PLL DISABLED)
fOUT = 3 GHz, fDAC = 12 GSPS, CLKINx Frequency (fCLKIN) =
12 GHz
Direct RF clock input at 7 dBm
R&S SMA100B B711 option
1 kHz
−119
−129
−136
−146
−148
−150
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
10 kHz
100 kHz
600 kHz
1.2 MHz
1.8 MHz
6 MHz
Rev. A | Page 10 of 33
Data Sheet
AD9082
Parameter
Test Conditions/Comments
Min Typ
Max Unit
SINGLE SIDEBAND PHASE NOISE OFFSET (PLL ENABLED)
Loop filter component values include
C1 = 22 nF, R1 = 226 Ω, C2 = 2.2 nF,
C3 = 33 nF, and phase detector
frequency (PFD) = 500 MHz
fOUT = 1.8 GHz, fDAC = 12 GSPS, fCLKIN = 0.5 GHz
1 kHz
−103
−111
−119
−127
−132
−137
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
10 kHz
100 kHz
600 kHz
1.2 MHz
1.8 MHz
6 MHz
Rev. A | Page 11 of 33
AD9082
Data Sheet
ADC AC SPECIFICATIONS
Nominal supplies with TA = 25°C. Input amplitude (AIN) = −1 dBFS, full bandwidth (no decimation) with dual link JTx mode of 13C.
Specifications represent worst measured of any ADC channel with DACs powered down. See the AN-835 Application Note,
Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Table 10.
Parameter
Min
Typ
Max
Unit
NOISE DENSITY1
NOISE FIGURE2
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 253 MHz
fIN = 450 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2700 MHz
fIN = 3600 MHz
fIN = 4500 MHz
−153
25.3
dBFS/Hz
dB
56.7
56.9
56.2
54.7
52.4
51.8
50.4
51.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
fIN = 5400 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) RATIO
fIN = 253 MHz
fIN = 450 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2700 MHz
fIN = 3600 MHz
fIN = 4500 MHz
fIN = 5400 MHz
56.6
56.6
55.7
53.9
52.0
51.3
49.6
48.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 253 MHz
fIN = 450 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2700 MHz
fIN = 3600 MHz
fIN = 4500 MHz
fIN = 5400 MHz
9.1
9.1
9
8.7
8.3
8.2
7.9
7.8
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
WORST HD2
fIN = 253 MHz
fIN = 450 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2700 MHz
fIN = 3600 MHz
fIN = 4500 MHz
fIN = 5400 MHz
−72.1
−68.9
−67.1
−64.6
−65.2
−58.1
−65
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−54.1
Rev. A | Page 12 of 33
Data Sheet
AD9082
Parameter
Min
Typ
Max
Unit
WORST HD3
fIN = 253 MHz
fIN = 450 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2700 MHz
fIN = 3600 MHz
fIN = 4500 MHz
fIN = 5400 MHz
−80.0
−78.3
−70.8
−66
−70.8
−69.2
−64.3
−62
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
WORST OTHER, EXCLUDING HD2 OR HD3 HARMONIC
fIN = 253 MHz
fIN = 450 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2700 MHz
fIN = 3600 MHz
fIN = 4500 MHz
fIN = 5400 MHz
−85.3
−81.4
−76.5
−72.1
−68.5
−65.9
−64.2
−62.7
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
TWO-TONE IMD3, Input Amplitude 1 (AIN1) = Input Amplitude 2 (AIN2) = −7 dBFS
Input Frequency 1 (fIN1) = 890 MHz, Input Frequency 2 (fIN2) = 910 MHz
fIN1 = 1780 MHz, fIN2 = 1820 MHz
fIN1 = 2680 MHz, fIN2 = 2720 MHz
fIN1 = 3560 MHz, fIN2 = 3640 MHz
fIN1 = 5360 MHz, fIN2 = 5440 MHz
ANALOG BANDWIDTH3
−78.9
−75
−73.2
−64.2
8
dBFS
dBFS
dBFS
dBFS
GHz
1 Noise density is measured at a low analog amplitude and/or frequency where timing jitter does not degrade noise floor.
2 Noise figure is based on a nominal full-scale input power of 4.5 dBm with an input span of 1.5 V p-p and RIN = 100 Ω.
3 Analog input bandwidth is the bandwidth of operation in which the full-scale input frequency response rolls off by −3 dB based on a de-embedded model of the ADC
extracted from the measured frequency response on evaluation board. This bandwidth requires optimized matching network to achieve this upper bandwidth.
TIMING SPECIFICATIONS
For the minimum and maximum values, TJ = −40°C to +120°C and 5% of nominal supply, unless otherwise noted.
Table 11.
Parameter
Symbol
Test Conditions/Comments
Min Typ Max Unit
SERIAL PORT INTERFACE (SPI) WRITE OPERATION
Maximum SCLK Clock Rate
SCLK Clock High
fSCLK, 1/tSCLK
33
5
5
4
4
MHz
ns
ns
ns
ns
tPWH
tPWL
tDS
tDH
tS
SCLK = 33 MHz
SCLK = 33 MHz
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CSB to SCLK Setup Time
SCLK to CSB Hold Time
4
4
ns
ps
tH
Rev. A | Page 13 of 33
AD9082
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min Typ Max Unit
SPI READ OPERATION
Maximum SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CSB to SCLK Setup Time
SCLK to SDIO Data Valid Time
SCLK to SDO Data Valid Time
CSB to SDIO Output Valid to High-Z
CSB to SDO Output Valid to High-Z
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tDV
tDV_SDO
tZ
tZ_SDO
8
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
50
4
4
4
20
20
20
20
Timing Diagrams
tS
tH
tSCLK
CSB
tPWH
tPWL
SCLK
SDIO
tDS
tDH
R/W
A15 A14
A0
D7
D6 D1 D0
Figure 2. Timing Diagram for 3-Wire Write Operation
tS
tSCLK
CSB
tPWH
tPWL
SCLK
tDS
tDV
tZ
tDH
SDIO
R/W A14 A2 A1
A0
D7 D6 D1 D0
Figure 3. Timing Diagram for 3-Wire Read Operation
tS
tSCLK
CSB
tPWH
tPWL
SCLK
tDS
tDH
R/W A14 A2 A1
SDIO
SDO
A0
tZ_SDO
tDV_SDO
D7 D6 D1 D0
Figure 4. Timing Diagram for 4-Wire Read Operation
Rev. A | Page 14 of 33
Data Sheet
AD9082
ABSOLUTE MAXIMUM RATINGS
Table 12.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Parameter
Rating
ISET, DACxP, DACxN, TDP, TDN
VCO_COARSE, VCO_FINE,
VCO_VCM, VCO_VREG
ADC0P, ADC0N, ADC1P, ADC1N
VCM0, VCM1
CLKINP, CLKINN
ADCDRVN, ADCDRVP
SERDINx , SERDOUTx
SYSREFP, SYSREFN, and
SYNCxINB
−0.3 V to AVDD2 + 0.3 V
−0.3 V to AVDD2_PLL + 0.3 V
−0.3 V to BVDD2 + 0.3 V
−0.3 V to RVDD2 + 0.3 V
−0.2 V to PLLCLKVDD1 + 0.2 V
−0.2 V to CLKVDD1 + 0.2 V
−0.2 V to SVDD1 + 0.2 V
−0.2 V to +2.5 V
REFLOW PROFILE
The AD9082 reflow profile is in accordance with the JEDEC
JESD 20 criteria for Pb-free devices. The maximum reflow
temperature is 260°C.
SYNCxOUTB , SYNCxINB ,
RESETB, TXENx, RXENx, IRQB_x,
CSB, SCLK, SDIO, SDO,
TMU_REFN, TMU_REFP,
ADCx_SMON0, ADCx_SMON1,
ADCx_FD0, ADCx_FD1, GPIOx
AVDD2, AVDD2_PLL, BVDD2,
RVDD2, SVDD2_PLL, DVDD1P8
PLLCLKVDD1, AVDD1,
AVDD1_ADC, CLKVDD1,
FVDD1, DAVDD1, DVDD1_RT,
DCLKVDD1, SVDD1
−0.3 V to DVDD1P8 + 0.3 V
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. The use of appropriate thermal
management techniques is recommended to ensure that the
maximum TJ does not exceed the limits shown in Table 12.
−0.3 V to +2.2 V
−0.2 V to +1.2 V
θJA is the natural convection, junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC_TOP is the junction to case, thermal resistance.
θJB is the junction to board, thermal resistance.
VNN1
−1.1 V to +0.2 V
Table 13. Simulated Thermal Resistance1
Temperature
Junction (TJ)1
Storage Range
Airflow Velocity
(m/sec)
125°C
−40°C to +150°C
PCB Type
θJA
θJC_TOP θJB Unit
1.8 °C/W
JEDEC 2s2p
Board
0.0
14.9 0.70
1 Do not exceed this temperature for any duration of time when the device is
powered.
1 Thermal resistance values specified are simulated based on JEDEC specifications
in compliance with JESD51-12 with the device power equal to 9 W.
ESD CAUTION
Rev. A | Page 15 of 33
AD9082
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9082
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SYNC1INB– SYNC0INB– SERDOUT0– SERDOUT0+
GND
A
B
C
GND
AVDD2
GND
GND
NC
NC
GND
GND
ADC0N
ADC0P
GND
SVDD1
GND
DAC0P
DAC0N
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
GND
VCM0
GND
GND
BVNN2
GND
GND
RVDD2
GND
SYNC1INB+ SYNC0INB+
RESETB DVDD1P8
GND
GND
SVDD1
SVDD1
SVDD1
SERDOUT7– SERDOUT7+
SERDOUT1– SERDOUT1+
ADCDRVN ADCDRVP
BVDD3
GND
GND
VDD1_
NVG
SERDOUT6– SERDOUT6+
D
E
F
AVDD1
AVDD2
GND
AVDD1
AVDD1
AVDD1
GND
AVDD1
GND
GND
GND
DNC
GND
FVDD1
GND
BVDD2
BVDD2
GND
VNN1
VNN1
GND
ADC0_
SMON1
ADC0_
SMON0
RXEN1
RXEN0
SDIO
GND
GND
NVG1_
OUT
GND
DAVDD1
DAVDD1
GND
VNN1
ADC1_
SMON1
ADC1_
SMON0
SERDOUT2– SERDOUT2+ SVDD1
GND
GND
DAC1N
GND
DVDD1P8
DVDD1 ADC0_FD1 ADC0_FD0
GND
GND
SVDD1
SERDOUT5– SERDOUT5+
TMU_
REFN
TMU_
G
H
J
DAC1P
GND
GND
CLKVDD1 AVDD1_
ADC
AVDD1_
ADC
ADC1_FD1 ADC1_FD0
REFP
CSB
SERDOUT3– SERDOUT3+ SVDD1
GND
GND
SERDOUT4– SERDOUT4+
AVDD2
ISET
GND
GND
GND
GND
DVDD1
GND
DVDD1
GND
SCLK
GND
GND
GND
SVDD1
VCO_
FINE
SVDD1_
PLL
VCO_
COARSE
CLKINP
CLKINN
GND
GND
PLLCLKVDD1 DVDD1_
RT
DVDD1_
RT
GND
GND
GND
DVDD1
DVDD1
GND
GND
DVDD1
DVDD1
DVDD1
GPIO3
GND
GND
SDO
GND
GND
GND
GND
GND
GND
GND
VCO_
VREG
VCO_
VCM
DCLKVDD1 DVDD1_
RT
DVDD1_
RT
SVDD2_
PLL
SVDD1_
PLL
GPIO9
GPIO8
K
L
GND
AVDD2
GND
AVDD2_
PLL
DNC
GND
GND
GND
GND
GND
DVDD1
DVDD1
GND
GND
GND
DNC
DNC
SERDIN0– SERDIN0+
DAC2P
GND
CLKVDD1 AVDD1_
ADC
AVDD1_
ADC
GPIO1
GPIO7 SERDIN4– SERDIN4+
SVDD1
GND
GND
M
N
P
R
T
DAC2N
GND
GND
AVDD1
AVDD1
GND
GND
DAVDD1
DAVDD1
GND
GND
GND
GND
TDP
TDN
GPIO2
GPIO4
GPIO0
GPIO6
TXEN0
GND
GND
SVDD1 SERDIN1– SERDIN1+
NVG1_
OUT
IRQB_0
AVDD2
BVDD2
VNN1
VNN1
SERDIN7– SERDIN7+
SVDD1
GND
GND
VDD1_
NVG
TXEN1
GND
GND
SVDD1 SERDIN2– SERDIN2+
GND
AVDD1
GND
AVDD1
AVDD1
GND
GND
GND
FVDD1
GND
BVDD2
GND
VNN1
GND
GND
BVNN2
GND
IRQB_1
GPIO5
GND
DAC3N
DAC3P
SYSREFN SYSREFP
BVDD3
GND
GPIO10 DVDD1P8 SERDIN6– SERDIN6+
SVDD1
GND
GND
GND
GND
GND
GND
GND
GND
VCM1
GND
GND
DNC
RVDD2 SYNC1OUTB+SYNC0OUTB+
U
V
SVDD1
SVDD1
SERDIN3– SERDIN3+
SYNC1OUTB–SYNC0OUTB–
GND
SERDIN5– SERDIN5+
GND
GND
GND
AVDD2
GND
GND
GND
NC
NC
ADC1N
ADC1P
ANALOG
GROUND
DIGITAL
GROUND
SERDES
GND
GND
GROUND
Figure 5. 324-Ball Pin Configuration
Rev. A | Page 16 of 33
Data Sheet
AD9082
Table 14. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
POWER SUPPLIES
A2, E2, H2, L2, P2, V2
L3
AVDD2
AVDD2_PLL
Input
Input
Analog 2.0 V Supply Inputs for DAC.
Analog 2.0 V Supply Input for Clock PLL Linear
Dropout Regulator (LDO).
D7, E7, P7, R7
B11, U11
J5
D2 to D4, E3, F3, N3, P3, R2 to R4
G7, G8, M7, M8
G6, M6
D6, R6
D10, R10
BVDD2
RVDD2
Input
Input
Input
Input
Input
Input
Input
Input
Analog 2.0 V Supply Inputs for ADC Buffer.
Analog 2.0 V Supply Inputs for ADC Reference.
Analog 1.0 V Supply Input for Clock PLL.
Analog 1.0 V Supply Inputs for DAC Clock.
Analog 1.0 V Supply Inputs for ADC.
Analog 1.0 V Supply Inputs for ADC Clock.
Analog 1.0 V Supply Inputs for ADC Reference.
Analog 1.0 V Supply Inputs for Negative Voltage
Generator (NVG) Used to Generate −1 V Output.
PLLCLKVDD1
AVDD1
AVDD1_ADC
CLKVDD1
FVDD1
VDD1_NVG
E9, P9
NVG1_OUT
VNN1
Output
Input
Analog −1 V Supply Outputs from NVG.
Decouple NVG1_OUT to GND with a 0.1 μF
capacitor.
Analog −1 V Supply Inputs for ADC Buffer and
Reference. Connect these pins to the adjacent,
NVG1_OUT pins.
Analog −2 V Supply Outputs for ADC Buffer.
Decouple each BVNN2 pin to GND with a 0.1 μF
capacitor.
D8, E8, E10, P8, R8, P10
C9, T9,
BVNN2
Output
Output
C10, T10
BVDD3
Analog 3 V Supply Output for ADC Buffer.
Decouple BVDD3 to GND with 0.1 μF capacitor.
E5, F5, N5, P5
F10, H9, H11, J9, J11, K9, K11, L9, L11, M9
J6, J7, K6, K7
K5
A16, B16, C16, D16, E16, F16, G16, H16, M16, SVDD1
N16, P16, R16, T16, U16, V16
DAVDD1
DVDD1
DVDD1_RT
DCLKVDD1
Input
Input
Input
Input
Input
Digital Analog 1.0 V Supply Inputs.
Digital 1.0 V Supply Inputs.
Digital 1.0 Supply Inputs for Retimer Block.
Digital 1.0 V Clock Generation Supply.
Digital 1.0 V Supply Inputs for SERDES
Deserializer and Serializer.
K15
J16, K16
SVDD2_PLL
Input
Input
Digital 2.0 V Supply Input for SERDES LDO.
Digital 1.0 V Supply Inputs for SERDES Clock
Generation and PLL.
Digital Interface and Temperature Monitoring
Unit (TMU) Supply Inputs (Nominal 1.8 V).
SVDD1_PLL
DVDD1P8
GND
C13, F9, T13
Input
A1, A3, A4, A7, A8, A11, A17, A18, B2 to B6,
B9, B10, B14, B15, C2, C5 to C8, C11, C17,
C18, D1, D5, D9, D14, D15, E1, E4, E6, E17,
E18, F2, F4, F6 to F8, F14, F15, G2 to G5,
G17, G18, H1, H5 to H8, H10, H12, H14,
H15, J2, J8, J10, J12, J14, J15, J17, J18, K2,
K8, K10, K12, K14, K17, K18, L1, L5 to L8,
L10, L12, L14, M2 to M5, M10, M17, M18,
N2, N4, N6 to N8, N14, N15, P1, P4, P6,
P17, P18, R1, R5, R9, R14, R15, T2, T5 to T8,
T11, T17, T18, U2 to U6, U9, U10, U14,
U15, V1, V3, V4, V7, V8, V11, V17, V18
Input/output Ground References.
Rev. A | Page 17 of 33
AD9082
Data Sheet
Pin No.
ANALOG OUTPUTS
B1, C1
G1, F1
M1, N1
Mnemonic
Type
Description
DAC0P, DAC0N
DAC1P, DAC1N
DAC2P, DAC2N
DAC3P, DAC3N
ISET
Output
Output
Output
Output
Output
DAC0 Output Currents, Ground Referenced.
DAC1 Output Currents, Ground Referenced.
DAC2 Output Currents, Ground Referenced.
DAC3 Output Currents, Ground Referenced.
DAC Bias Current Setting Pin. Connect this pin
with a 5 kΩ resistor to GND.
U1, T1
H3
C4, C3
B8, U8
K3
ADCDRVP,
ADCDRVN
Output
Output
Output
Output
Output
ADC Clock Output Options. These pins are
disabled by default.
ADC Buffer Common-Mode Output Voltage.
Decouple this pin to GND with a 0.1 μF capacitor.
PLL LDO Regulator Output. Decouple this pin to
GND with a 2.2 μF capacitor.
TMU ADC Negative Reference. Connect this pin
to GND.
VCM0, VCM1
VCO_VREG
TMU_REFN
TMU_REFP
G9
G10
TMU ADC Positive Reference. Connect this pin
to DVDD1P8.
ANALOG INPUTS
A10, A9
ADC0P, ADC0N
ADC1P, ADC1N
VCO_FINE
Input
Input
Input
Input
Input
Input
ADC0 Differential Inputs with Internal 100 Ω
Differential Resistor.
ADC1 Differential Inputs with Internal 100 Ω
Differential Resistor.
On-Chip Clock Multiplier and PLL Fine Loop
Filter Input.
On-Chip DAC Clock Multiplier and PLL Coarse
Loop Filter Input.
On-Chip Clock Multiplier and VCO Common-
Mode Input.
Anode and Cathode of Temperature Diodes.
This feature is not supported. Tie TDP and TDN
to GND.
V10, V9
J3
J4
VCO_COARSE
VCO_VCM
K4
N9, N10
TDP, TDN
J1, K1
CLKINP, CLKINN
Input
Differential Clock Inputs with Nominal 100 Ω
Termination. Self bias input requiring ac
coupling. When the on-chip clock multiplier PLL
is enabled, this input is the reference clock
input. If the PLL is disabled, an RF clock equal to
the DAC output sample rate is required.
CMOS INPUTS AND OUTPUTS1
G13
H13
F13
J13
CSB
Input
Input
Serial Port Enable Input. Active low.
Serial Plot Clock Input.
SCLK
SDIO
SDO
Input/output Serial Port Bidirectional Data Input/Output.
Output
Input
Serial Port Data Output.
C12
RESETB
Active Low Reset Input. RESETB places digital
logic and SPI registers in a known default state.
RESETB must be connected to a digital IC that is
capable of issuing a reset signal for the first step
in the device initialization process.
E13, D13
P13, R13
RXEN0, RXEN1
TXEN0, TXEN1
Input
Input
Active High ADC and Receive Datapath Enable
Inputs. RXENx is also SPI configurable.
Active High DAC and Transmit Datapath Enable
Inputs. TXENx is also SPI configurable.
Rev. A | Page 18 of 33
Data Sheet
AD9082
Pin No.
Mnemonic
Type
Description
D12, D11
ADC0_SMON0,
ADC0_SMON1
Output
ADC0 Signal Monitoring Outputs by Default. Do
not connect if unused.
E12, E11
F12, F11
G12, G11
P12, R12
ADC1_SMON0,
ADC1_SMON1
ADC0_FD0,
ADC0_FD1
ADC1_FD0,
ADC1_FD1
IRQB_0, IRQB_1
Output
Output
Output
Outputs
ADC1 Signal Monitoring Outputs by Default. Do
not connect if unused.
ADC0 Fast Detect Outputs by Default. Do not
connect if unused.
ADC1 Fast Detect Outputs by Default. Do not
connect if unused.
Interrupt Request 0 and 1 Outputs. These pins
are an open-drain, active low output (CMOS
levels with respect to DVDD1P8). Connect a
10 kΩ pull-up resistor to DVDD1P8 to prevent
these pins from floating when unused.
K13, L13, M11 to M13, N11 to N13,
P11, R11, T12
GPIO0 to GPIO10
Input/output General-Purpose Input or Output Pins.
JESD204B or JESD204C COMPATIBLE SERDES
DATA LANES AND CONTROL SIGNALS2
L18, L17
N18, N17
R18, R17
U18, U17
M15, M14
V15, V14
T15, T14
P15, P14
U13, V13
SERDIN0+,
SERDIN0−
SERDIN1+,
SERDIN1−
SERDIN2+,
SERDIN2−
SERDIN3+,
SERDIN3−
SERDIN4+,
SERDIN4−
SERDIN5+,
SERDIN5−
SERDIN6+,
SERDIN6−
SERDIN7+,
SERDIN7−
Input
Input
Input
Input
Input
Input
Input
Input
Output
JRx Lane 0 Inputs, Data True/Complement.
JRx Lane 1 Inputs, Data True/Complement.
JRx Lane 2 Inputs, Data True/Complement.
JRx Lane 3 Inputs, Data True/Complement.
JRx Lane 4 Inputs, Data True/Complement.
JRx Lane 5 Inputs, Data True/Complement.
JRx Lane 6 Inputs, Data True/Complement.
JRx Lane 7 Inputs, Data True/Complement.
SYNC0OUTB+,
SYNC0OUTB−
JRx Link 0 Synchronization Outputs for
JESD204B interface. These pins are LVDS or
CMOS configurable. These pins can also
provide differential 100 Ω output impedance
in LVDS mode.
U12, V12
SYNC1OUTB+,
SYNC1OUTB−
Output
JRx Link 1 Synchronization Outputs for
JESD204B interface or CMOS Input for Transmit
Fast Frequency Hopping (FFH) via GPIOx pins.
For sync output function, these pins are LVDS
or CMOS output configurable and can provide
differential 100 Ω output impedance in LVDS
mode.
A15, A14
C15, C14
E15, E14
G15, G14
H18, H17
SERDOUT0+,
SERDOUT0−
SERDOUT1+,
SERDOUT1−
SERDOUT2+,
SERDOUT2−
SERDOUT3+,
SERDOUT3−
Output
Output
Output
Output
Output
JTx Lane 0 Outputs, Data True/Complement.
JTx Lane 1 Outputs, Data True/Complement.
JTx Lane 2 Outputs, Data True/Complement.
JTx Lane 3 Outputs, Data True/Complement.
JTx Lane 4 Outputs, Data True/Complement.
SERDOUT4+,
SERDOUT4−
Rev. A | Page 19 of 33
AD9082
Data Sheet
Pin No.
Mnemonic
Type
Description
F18, F17
SERDOUT5+,
SERDOUT5−
SERDOUT6+,
SERDOUT6−
SERDOUT7+,
SERDOUT7−
SYNC0INB+,
SYNC0INB−
Output
JTx Lane 5 Outputs, Data True/Complement.
JTx Lane 6 Outputs, Data True/Complement.
JTx Lane 7 Outputs, Data True/Complement.
D18, D17
B18, B17
B13, A13
Output
Output
Input
JTx Link 0 Synchronization Inputs for JESD204B
interface. These pins are LVDS or CMOS
configurable. These pins are LVDS or CMOS
configurable and have selectable internal 100 Ω
input impedance for LVDS operation
B12, A12
T4, T3
SYNC1INB+,
SYNC1INB−
Input
Input
JTx Link 1 Synchronization Inputs for JESD204B
interface or CMOS Inputs for Receive FFH via
GPIOx pins. These pins are LVDS or CMOS
configurable and have selectable internal 100 Ω
input impedance for LVDS operation.
Active High JESD204 System Reference Inputs.
These pins are configurable for differential
current mode logic (CML), PECL, and LVDS with
internal 100 Ω termination or single-ended
CMOS.
SYSREFP, SYSREFN
NO CONNECTS AND DO NOT CONNECTS
A5, A6, V5, V6
NC
No Connect. These pins can be left open or
connected.
B7, H4, L4, L15, L16, U7
DNC
DNC
Do Not Connect. The pins must be kept open.
1 CMOS inputs do not have pull-up or pull-down resistors.
2 SERDINx and SERDOUTx include 100 Ω internal termination resistors.
Rev. A | Page 20 of 33
Data Sheet
AD9082
TYPICAL PERFORMANCE CHARACTERISTICS
DAC
TA = 25°C using the AD9082-FMCA-EBZ, data curves represent average performance of all DAC outputs with harmonics (or alias
harmonics) and spurs falling in the first DAC Nyquist zone (<fDAC/2), IOUTFS = 26 mA, PLL clock multiplier enabled, and ADC powered
down, unless otherwise noted. See the UG-1578 user guide for additional information on the JESDB or JESDC mode configurations.
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
0dBFS
0dBFS
–7dBFS
–12dBFS
–17dBFS
–7dBFS
–12dBFS
–17dBFS
0
1000
2000
3000
4000
5000
6000
0
500
1000
1500
2000
2500
3000
fOUT (MHz)
fOUT (MHz)
Figure 6. HD2 vs. fOUT over Digital Scale (Mode 17B), 6 GSPS DAC Sample
Figure 9. HD2 vs. fOUT over Digital Scale (Mode 16B), 12 GSPS DAC Sample
Rate, Channel Interpolation 1×, Main Interpolation 4×
Rate, Channel Interpolation 4×, Main Interpolation 8×
–50
–50
0dBFS
–55
–55
–60
–65
–70
–75
–80
–7dBFS
–12dBFS
–17dBFS
–60
–65
–70
–75
–80
–85
–90
–95
–100
–85
–90
0dBFS
–7dBFS
–12dBFS
–17dBFS
–95
–100
0
500
1000
1500
2000
2500
3000
0
1000
2000
3000
4000
5000
6000
fOUT (MHz)
fOUT (MHz)
Figure 7. HD3 vs. fOUT over Digital Scale (Mode 17B), 6 GSPS DAC Sample
Figure 10. HD3 vs. fOUT over Digital Scale (Mode 16B), 12 GSPS DAC Sample
Rate, Channel Interpolation 1×, Main Interpolation 4×
Rate, Channel Interpolation 4×, Main Interpolation 8×
–50
–50
0dBFS
–55
–55
–60
–65
–70
–75
–80
–7dBFS
–12dBFS
–60
–65
–70
–75
–80
–85
–90
–95
–100
–17dBFS
–85
–90
0dBFS
–7dBFS
–12dBFS
–17dBFS
–95
–100
0
500
1000
1500
2000
2500
3000
0
1000
2000
3000
4000
5000
6000
fOUT (MHz)
fOUT (MHz)
Figure 8. SFDR, Worst Spurious vs. fOUT over Digital Scale (Mode 17B),
6 GSPS DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 4×
Figure 11. SFDR, Worst Spurious vs. fOUT over Digital Scale (Mode 16B), 12 GSPS
DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8×
Rev. A | Page 21 of 33
AD9082
Data Sheet
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
0dBFS
–7dBFS
–13dBFS
–17dBFS
0dBFS
–7dBFS
–12dBFS
–17dBFS
–100
0
1000
2000
3000
4000
5000
6000
0
500 1000 1500 2000 2500 3000 3500 4000 4500
fOUT (MHz)
fOUT (MHz)
Figure 12. HD2 vs. fOUT over Digital Scale (Mode 17B), 12 GHz GSPS Sample Rate,
Channel Interpolation 1×, Main Interpolation 8×
Figure 15. HD2 vs. fOUT over Digital Scale (Mode 17B), 9 GHz GSPS Sample Rate,
Channel Interpolation 1×, Main Interpolation 6×
–50
–55
–60
–65
–70
–75
–80
–50
0dBFS
–55
–7dBFS
–13dBFS
–60
–65
–70
–75
–80
–85
–90
–95
–100
–17dBFS
–85
–90
0dBFS
–7dBFS
–12dBFS
–17dBFS
–95
–100
0
1000
2000
3000
4000
5000
6000
0
500 1000 1500 2000 2500 3000 3500 4000 4500
fOUT (MHz)
fOUT (MHz)
Figure 13. HD3 vs. fOUT over Digital Scale (Mode 17B), 12 GSPS DAC Sample Rate,
Channel Interpolation 1×, Main Interpolation 8×
Figure 16. HD3 vs. fOUT over Digital Scale (Mode 17B), 9 GSPS DAC Sample Rate,
Channel Interpolation 1×, Main Interpolation 6×
–50
–55
–60
–65
–70
–75
–80
–50
0dBFS
–55
–7dBFS
–13dBFS
–60
–65
–70
–75
–80
–85
–90
–95
–100
–17dBFS
–85
–90
0dBFS
–7dBFS
–12dBFS
–17dBFS
–95
–100
0
1000
2000
3000
4000
5000
6000
0
500 1000 1500 2000 2500 3000 3500 4000 4500
fOUT (MHz)
fOUT (MHz)
Figure 14. SFDR vs. fOUT over Digital Scale (Mode 17B), 12 GSPS DAC Sample
Rate, Channel Interpolation 1×, Main Interpolation 8×
Figure 17. SFDR vs. fOUT over Digital Scale (Mode 17B), 9 GSPS DAC Sample Rate,
Channel Interpolation 1×, Main Interpolation 6×
Rev. A | Page 22 of 33
Data Sheet
AD9082
–50
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–6dBFS
–6dBFS
–13dBFS
–18dBFS
–23dBFS
–13dBFS
–18dBFS
–23dBFS
0
500
1000
1500
2000
2500
3000
0
1000
2000
3000
4000
5000
6000
7000
fOUT (MHz)
fOUT (MHz)
Figure 18. IMD3 vs. fOUT over Digital Scale (Mode 17B), 6 GSPS DAC
Sample Rate, Channel Interpolation 1×, Main Interpolation 4×
Figure 21. IMD3 vs. fOUT over Digital Scale (Mode 17B), 9 GSPS DAC Sample
Rate, Channel Interpolation 1×, Main Interpolation 6×, 1 MHz Tone Spacing
–50
–50
–6dBFS
–55
–6dBFS
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–13dBFS
–13dBFS
–18dBFS
–23dBFS
–18dBFS
–23dBFS
–60
–65
–70
–75
–80
–85
–90
–95
–100
0
1000
2000
3000
4000
5000
6000
0
1000
2000
3000
4000
5000
6000
fOUT (MHz)
fOUT (MHz)
Figure 19. IMD3 vs. fOUT over Digital Scale (Mode 16B),
Figure 22. IMD3 vs. fOUT over Digital Scale (Mode 17B),
12 GHz DAC Sample Rate, Channel Interpolation 4×, Main Interpolation 8×
12 GSPS DAC Sample Rate, Channel Interpolation 1×, Main Interpolation 8×
–50
–50
fDAC = 11796.48MSPS
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
fDAC = 11796.48MSPS
fDAC = 8847.36MSPS
fDAC = 5898.24MSPS
fDAC = 2949.12MSPS
–53
–56
–59
–62
–65
–68
–71
–74
–77
–80
fDAC = 9830.4MSPS
fDAC = 5898.24MSPS
fDAC = 2949.24MSPS
0
1000
2000
3000
4000
5000
6000
0
1000
2000
3000
4000
5000
6000
fOUT (MHz)
fOUT (MHz)
Figure 20. IMD3 vs. fOUT over fDAC (Mode 17B), 1 MHz Tone Spacing with
−12 dBFS/Tone Level
Figure 23. Worst Harmonic In-Band vs. fOUT Across fDAC with 0 dBFS Tone Level
(Mode 17B)
Rev. A | Page 23 of 33
AD9082
Data Sheet
2
1
MKR1 3.900000000GHz
–41.78dBm
1
–35
–45
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–55
fDAC = 11796.48MSPS
fDAC = 8847.36MSPS
fDAC = 5898.24MSPS
fDAC = 2949.12MSPS
–65
–75
–85
–95
–105
–115
–13
0
1000
2000
3000
4000
5000
6000
CENTER 3.9000GHz
#RES BW 100kHz
SPAN 798.3MHz
SWEEP 233ms (1001PTS)
fOUT (MHz)
Figure 24. DAC0 Fundamental Output Power vs. fOUT for
Different fDAC Sample Rates (Mode 17B), Channel Interpolation 1×,
Main Interpolation 8×, 0 dBFS Digital Back Off)
Figure 27. Adjacent Channel Leakage Ratio (ACLR) Performance for 100 MHz
5G Test Vector at fOUT = 3.9 GHz and fDAC = 11.898 GSPS, Test Vector Peak to
RMS = 11.7 dB with −1 dBFS Back Off (Mode 9C), Channel Interpolation 3×,
Main Interpolation 8×
–140
–140
SHUFFLE ON
SHUFFLE ON
–143
–146
–149
–152
–155
–158
–161
–164
–167
–170
SHUFFLE OFF
–143
–146
–149
–152
–155
–158
–161
–164
–167
–170
SHUFFLE OFF
0
1000
2000
3000
4000
5000
6000
0
1000
2000
3000
4000
5000
6000
fOUT (MHz)
fOUT (MHz)
Figure 25. Single-Tone NSD Measured at 10% Offset from fOUT vs. fOUT
,
Figure 28. Single-Tone NSD Measured at 10% Offset from fOUT vs. fOUT
,
11796.48 MSPS fDAC, 16-Bit Resolution, Shuffle Off vs. Shuffle On (Mode 17B)
11796.48 MSPSz fDAC, 12-Bit Resolution, Shuffle Off vs. Shuffle On (Mode 24C)
–140
–140
fDAC = 11796.48MSPS
fDAC = 11796.48MSPS
fDAC = 8847.36MSPS
–143
fDAC = 5898.24MSPS
–146
–143
fDAC = 8847.36MSPS
fDAC = 5898.24MSPS
–146
–149
–152
–155
–158
–161
–164
–167
–170
–149
–152
–155
–158
–161
–164
–167
–170
0
1000
2000
3000
4000
5000
6000
0
1000
2000
3000
4000
5000
6000
fOUT (MHz)
fOUT (MHz)
Figure 26. Single-Tone NSD Measured at 10% Offset from fOUT vs. fOUT over fDAC
,
Figure 29. Single-Tone NSD Measured at 10% Offset from fOUT vs. fOUT over fDAC
,
16-Bit Resolution, Shuffle On (Mode 17B)
12-Bit Resolution, Shuffle On (Mode 24C)
Rev. A | Page 24 of 33
Data Sheet
AD9082
–80
–70
–80
fREF = 125MHz
fREF = 250MHz
fREF = 375MHz
fREF = 500MHz
fREF = 750MHz
–90
–90
–100
–110
–120
–130
–140
–150
–160
CLOCK PLL DISABLED
–100
–110
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
Figure 30. Single Sideband Phase Noise vs. Frequency Offset with fDAC = 12 GSPS,
fOUT = 3 GHz, Clock PLL Disabled with External 12 GHz Clock Input Using
R&S SMA100B with B711 Option as Clock Source, Engineering Board Used
Figure 33. Single Sideband Phase Noise vs. Frequency Offset for Different PLL
Reference Clock (fREF), fOUT = 1.8 GHz, fDAC = 12 GSPS, PLL Enabled with Exception of
External 12 GHz Clock Input with Clock PLL Disabled, Engineering Board Used
MKR2 265.0MHz
–0.294dB
–40
–50
–30
1
2Δ1
–40
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–110
–120
–100
–110
CENTER 2.145GHz
#RES BW 30kHz
SPAN 140MHz
SWEEP 3.862s
CENTER 2.0125GHz
#RES BW 30kHz
SPAN 500.0MHz
SWEEP 42.87ms (1001PTS)
Figure 34. Dual Band ACLR Performance for 20 MHz LTE at fOUT = 2.145 GHz
and fDAC = 11.796 GSPS, Test Vector PAR = 7.7 dB with −1 dBFS Back Off
(Mode 9C), Channel Interpolation 3×, Main Interpolation 8×
Figure 31. Dual Band 3GPP B1 and B3 Wideband Plot for 20 MHz LTE at
fOUT = 1.88 GHz and fOUT = 2.145 GHz with fDAC = 11.796 GSPS,
Test Vector PAR = 7.7 dB with −1 dBFS Back Off (Mode 9C),
Channel Interpolation 3×, Main Interpolation 8×
–40
–50
–60
–70
–80
–90
–100
–110
–120
CENTER 1.88GHz
#RES BW 30kHz
SPAN 140MHz
SWEEP 3.862s (1001PTS)
Figure 32. Dual Band ACLR Performance for 20 MHz LTE at fOUT = 1.88 GHz
and fDAC = 11.796 GSPS, Test Vector PAR = 7.7 dB with −1 dBFS Back Off
(Mode 9C), Channel Interpolation 3×, Main Interpolation 8×
Rev. A | Page 25 of 33
AD9082
Data Sheet
ADC
Sampling rate = 6 GSPS with clock frequency (fCLK) = 6 GHz direct RF clock of 6 GHz, Nyquist mode operation (no decimation) with
JESD204 interface mode = 19B, timing calibration disabled with 100 MHz region centered on Nyquist zone transition, TA = 25°C, 128 K FFT
sample with no averaging and AIN = −1 dBFS, ADCx input, and DAC powered down, unless otherwise noted.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
93
90
87
84
81
78
75
72
69
66
63
60
62
61
60
59
58
57
56
55
54
53
52
51
SNR = 56.9dBFS
HD2 = 80.6dBFS
HD3 = 79.7dBFS
WORST OTHER SPUR = –87.4dBFS
CH0 SFDR
CH1 SFDR
CH0 SNR
CH1 SNR
0
0.5
1.0
1.5
2.0
2.5
3.0
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 35. Single-Tone FFT at fIN = 450 MHz
Figure 38. Single-Tone SFDR and SNR vs. Input Amplitude at fIN = 450 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
93
90
87
84
81
78
75
72
69
66
63
60
62
61
60
59
58
57
56
55
54
53
52
51
SNR = 56.4dBFS
HD2 = 67.4dBFS
HD3 = 71.6dBFS
WORST OTHER SPUR = –83.8dBFS
CH0 SFDR
CH1 SFDR
CH0 SNR
CH1 SNR
0
0.5
1.0
1.5
2.0
2.5
3.0
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 36. Single-Tone FFT at fIN = 900 MHz
Figure 39. Single-Tone SFDR and SNR vs. Input Amplitude at fIN = 900 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
93
90
87
84
81
78
75
72
69
66
63
60
62
61
60
59
58
57
56
55
54
53
52
51
SNR = 54.8dBFS
HD2 = 67.9dBFS
HD3 = 68.0dBFS
WORST OTHER SPUR = –80.0dBFS
CH0 SFDR
CH1 SFDR
CH0 SNR
CH1 SNR
0
0.5
1.0
1.5
2.0
2.5
3.0
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 37. Single-Tone FFT at fIN = 1.8 GHz
Figure 40. Single-Tone SFDR and SNR vs. Input Amplitude at fIN = 1.8 GHz
Rev. A | Page 26 of 33
Data Sheet
AD9082
0
93
90
87
84
81
78
75
72
69
66
63
60
62
61
60
59
58
57
56
55
54
53
52
SNR = 52.7dBFS
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
HD2 = 65.2dBFS
HD3 = 71.3dBFS
WORST OTHER SPUR = –75.5dBFS
CH0 SFDR
CH1 SFDR
CH0 SNR
CH1 SNR
51
0
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.0
3.0
–80
–70
–60
–50
–40
–30
–20
–10
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 41. Single-Tone FFT at fIN = 2.7 GHz
Figure 44. Single-Tone SFDR and SNR vs. Input Amplitude at fIN = 2.7 GHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
93
90
87
84
81
78
75
72
69
66
63
60
57
54
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SNR = 51.9dBFS
HD2 = 58.1dBFS
HD3 = 69.2dBFS
WORST OTHER SPUR = –73.7dBFS
CH0 SFDR
CH1 SFDR
CH0 SNR
CH1 SNR
0.5
1.0
1.5
2.0
2.5
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 42. Single-Tone FFT at fIN = 3.6 GHz
Figure 45. Single-Tone SFDR and SNR vs. Input Amplitude at fIN = 3.6 GHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
93
90
87
84
81
78
75
72
69
66
63
60
57
54
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SNR = 50.8dBFS
HD2 = 70.5dBFS
HD3 = 64.2dBFS
WORST OTHER SPUR =
–74.0dBFS
CH0 SFDR
CH1 SFDR
CH0 SNR
CH1 SNR
0.5
1.0
1.5
2.0
2.5
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 43. Single-Tone FFT at fIN = 4.5 GHz
Figure 46. Single-Tone SFDR and SNR vs. Input Amplitude at fIN = 4.5 GHz
Rev. A | Page 27 of 33
AD9082
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
93
90
87
84
81
78
75
72
69
66
63
60
57
54
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SNR = 51.3dBFS
HD2 = 54.1dBFS
HD3 = 61.0dBFS
WORST OTHER SPUR = –70.3dBFS
CH0 SFDR
CH1 SFDR
CH0 SNR
CH1 SNR
–110
0
0.5
1.0
1.5
2.0
2.5
3.0
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 47. Single-Tone FFT at fIN = 5.4 GHz
Figure 50. Single-Tone SFDR and SNR vs. Input Amplitude at fIN = 5.4 GHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
SNR = 50.3dBFS
HD2 = 57.0dBFS
HD3 = 61.3dBFS
WORST OTHER SPUR = –69.0dBFS
CH0 SFDR
CH1 SFDR
CH0 SNR
CH1 SNR
–110
0
0.5
1.0
1.5
2.0
2.5
3.0
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 48. Single-Tone FFT at fIN = 6.3 GHz
Figure 51. Single-Tone SNR/SFDR vs. Input Amplitude at fIN = 6.3 GHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–64
A
AND A
= –7.0dBFS
IN2
IN1
–70
–76
CH0 IMD3L
CH0 IMD3H
CH1 IMD3L
CH1 IMD3H
IMD3L = –78.1dBFS
IMD3H = –79.0dBFS
–82
–88
–94
–100
–106
–112
–118
–124
–130
1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10
–31
–28
–25
–22
–19
–16
–13
–10
–7
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 49. Two-Tone FFT, fIN1 = 1.775 GHz, fIN2 = 1.825 GHz, and
AIN1 and AIN2 = −7 dBFS (Note That IMD3L and IMD3H Are the Lower and
Higher IMD3 Product Components in dBFS.)
Figure 52. Two-Tone IMD3 vs. Input Amplitude with
fIN1 = 1.775 GHz, fIN2 = 1.825 GHz
Rev. A | Page 28 of 33
Data Sheet
AD9082
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–64
–70
A
AND A
= –7.0dBFS
IN2
IN1
CH0 IMD3L
CH0 IMD3H
CH1 IMD3L
CH1 IMD3H
IMD3L = –75.6dBFS
IMD3H = –74.8dBFS
–76
–82
–88
–94
–100
–106
–112
–118
–124
–130
2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00
–31
–28
–25
–22
–19
–16
–13
–10
–7
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 53. Two-Tone FFT, fIN1 = 2.675 GHz, fIN2 = 2.725 GHz, and
AIN1 and AIN2 = −7 dBFS
Figure 56. Two-Tone IMD3 vs. Input Amplitude with fIN1 = 2.675 GHz and
fIN2 = 2.725 GHz
0
–64
A
AND A
= –7.0dBFS
IN2
IN1
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–70
–76
CH0 IMD3L
CH0 IMD3H
CH1 IMD3L
CH1 IMD3H
IMD3L = –72.8dBFS
IMD3H = –73.1dBFS
–82
–88
–94
–100
–106
–112
–118
–124
–130
2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70
–31
–28
–25
–22
–19
–16
–13
–10
–7
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 54. Two-Tone FFT, fIN1 = 3.575 GHz, fIN2 = 3.625 GHz, and
AIN1 and AIN2 = −7 dBFS
Figure 57. Two-Tone IMD3 vs. Input Amplitude with fIN1 = 3.575 GHz and
fIN2 = 3.625 GHz
0
–64
A
AND A
= –7.0dBFS
IN2
IN1
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–70
–76
CH0 IMD3L
CH0 IMD3H
CH1 IMD3L
CH1 IMD3H
IMD3L = –64.2dBFS
IMD3H = –65.4dBFS
–82
–88
–94
–100
–106
–112
–118
–124
–130
0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90
–31
–28
–25
–22
–19
–16
–13
–10
–7
FREQUENCY (GHz)
INPUT AMPLITUDE (dBFS)
Figure 55. Two-Tone FFT, fIN1 = 5.375 GHz, fIN2 = 5.425 GHz, and
AIN1 and AIN2 = −7 dBFS
Figure 58. Two-Tone IMD3 vs. Input Amplitude with fIN1 = 5.375 GHz and
fIN2 = 5.425 GHz
Rev. A | Page 29 of 33
AD9082
Data Sheet
57
56
55
54
53
52
51
50
48
48
57
56
55
54
53
52
51
50
48
48
47
CH0 DIRECT RF
CH1 DIRECT RF
CH0 CLK_PLL
CH1 CLK_PLL
CH0 DIRECT RF, DAC OFF
CH0 DIRECT RF, DAC ON
CH0 CLK PLL, DAC OFF
CH0 CLK PLL, DAC ON
47
0
1000
2000
3000
4000
5000
6000
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 59. SNR vs. Frequency with AIN =−1 dBFS Between Direct External RF
Clock = 6 GHz and PLL Clock Multiplier Enabled with Reference Input of 125 MHz
Figure 62. SNR vs. Frequency with AIN = −1 dBFS with DAC On/Off and
PLL On/Off Between Direct External RF Clock = 6 GHz and PLL Clock
Multiplier Enabled with Reference Input of 125 MHz
86
0
CH0 DIRECT RF
–0.5
CH1 DIRECT RF
CH0 CLK_PLL
CH1 CLK_PLL
83
80
77
74
71
68
65
62
59
56
53
50
47
ADC0
ADC1
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
0
1000
2000
3000
4000
5000
6000
0
1
2
3
4
5
6
7
8
9
FREQUENCY (MHz)
FREQUENCY (GHz)
Figure 63. Measured Input Bandwidth of ADC0 and ADC1 Input Using
Marki Microwave BALH-0009 on AD9082-FMCA-EBZ (No Matching Network),
De-Embedded −3 dB ADC Bandwidth Is Equal to 8 GHz
Figure 60. SFDR vs. Frequency with AIN = −1 dBFS Between Direct External RF
Clock = 6 GHz and PLL Clock Multiplier Enabled with Reference Input of 125 MHz
–45
–45
–51
–57
–63
–69
–75
–81
–87
ADC0 HD2
ADC0 HD3
ADC1 HD2
ADC1 HD3
–51
–57
–63
–69
–75
–81
–87
–93
–99
–105
–93
ADC0 HD2
ADC0 HD3
ADC1 HD2
ADC1 HD3
–99
–105
0
1000
2000
3000
4000
5000
6000
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 64. Harmonics (HD2 and HD3) vs. Frequency with AIN = −9 dBFS
Figure 61. Harmonics (HD2 and HD3) vs. Frequency with AIN = −1 dBFS
Rev. A | Page 30 of 33
Data Sheet
AD9082
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
CH0 HD2
CH0 HD3
CH1 HD2
CH1 HD3
CH0 HD2
CH0 HD3
CH1 HD2
CH1 HD3
2000
2500
3000
3500
4000
4500
5000
5500
6000
2000
2500
3000
3500
4000
4500
5000
5500
6000
SAMPLE FREQUENCY (MHz)
SAMPLE FREQUENCY (MHz)
Figure 65. HD2 and HD3 vs. Sample Frequency (fS), fIN = 450 MHz,
AIN = −1 dBFS, fS = 2 GSPS to 6 GSPS
Figure 68. HD2 and HD3 vs. Sample Frequency, fIN = 3450 MHz, AIN = −1 dBFS,
fS = 2 GSPS to 6 GSPS
85
80
75
70
65
60
85
CH0 SNR
CH0 SFDR
CH1 SNR
80
CH1 SFDR
75
70
65
60
55
50
45
55
CH0 SNR
CH0 SFDR
CH1 SNR
CH1 SFDR
50
45
2000
2500
3000
3500
4000
4500
5000 5500 6000
2000
2500
3000
3500
4000
4500
5000
5500
6000
SAMPLE FREQUENCY (MHz)
SAMPLE FREQUENCY (MHz)
Figure 66. SNR and SFDR vs. Sample Frequency, fIN = 450 MHz, AIN = −1 dBFS,
fS = 2 GSPS to 6 GSPS
Figure 69. SNR and SFDR vs. Sample Frequency, fIN = 3450 MHz,
AIN = −1 dBFS, fS = 2 GSPS to 6 GSPS
80
75
70
65
60
55
50
250k
1.925 LSB RMS
200k
150k
100k
50k
0
45
CH0 SNR
CH0 SFDR
40
CH1 SNR
CH1 SFDR
35
30
–40
–20
0
20
40
60
80
100
120
DIE TEMPERATURE (°C)
CODE
Figure 70. Input Referred Noise Histogram
Figure 67. SFDR and SNR vs. Die Temperature, fIN= 1.85 GHz, AIN = −1 dBFS
Rev. A | Page 31 of 33
AD9082
Data Sheet
THEORY OF OPERATION
The AD9082 is a highly integrated, 28 nm, RF, MxFE featuring
four 16-bit, 12 GSPS DAC cores and two 12-bit, 6 GSPS ADC
cores (see Figure 1). The DAC core is based on a current
segmentation architecture providing a differential complementary
current output with an adjustable full-scale output (IOUTFS) range
of 7 mA to 40 mA. The ADC core is based on a proprietary
interleaved architecture that suppresses residual interleaving
spurious products into the noise floor. To enable wide bandwidth
operation, a high linearity 100 Ω differential buffer with overload
protection is used to isolate the ADC core from the RF ADC
driver source. An on-chip clock multiplier can be used to
synthesize the RF DAC and ADC clocks or, alternatively,
an external clock can be applied.
external to the device. The transmit datapath includes digital gain
control, fine delay adjust, and power amplifier protection to
simplify DPD integration in a multiband transmitter. The receive
path includes a flexible programmable 192-tap finite impulse
response (PFIR) filter. The filter can be allocated across one or
more ADCs for receive equalization with support for four
different profiles. These profiles can be selected using the
GPIOx pins. The receive datapath also includes a fast and slow
signal detection capability in support of automatic gain control
(AGC). Transmit and receive data formatting can be real or
complex with resolutions of 8, 12, 16, and 24 bits depending on
the JESD204B or the JESD204C mode. The AD9082 also allows
complete bypass of the transmit and receive DSP paths enabling
Nyquist operation.
Flexible transmit and receive DSP paths are available to up and
down sample the desired intermediate frequency (IF) or RF
signal(s) to manageable data interface rates aligned with
bandwidth requirements. The transmit and receive DSP paths are
symmetric and consist of four coarse digital upconversion (DUC)
and digital downconversion (DDC) blocks in the main datapath
along with eight fine DUC and DDC blocks in the channelizer
datapath. Each block includes a 48-bit NCO configurable for
integer or fractional mode of operation. The channelizer
datapath enables an efficient implementation to support
multiband applications where up to eight RF bands can be
supported. Each of the DUC and DDC blocks are bypassable
and offer flexible interpolating and decimation factors. The
NCO in each block also supports coherent frequency hopping.
The device also supports fast frequency hopping via GPIOx and a
low latency digital loopback capability. An on-chip TMU is also
included and can be used as part of a thermal management
solution. Power savings option in support of time division
duplex (TDD) applications are included.
A 16-lane JESD204 transceiver port is available to support the
high data throughput rates on the receive and transmit datapaths.
Eight SERDES lanes are designated for the transmit datapaths,
while the other 8 lanes are designated for the receive datapaths with
the option to support two links. The transceiver port supports
JESD204C up to 16.22 GSPS or JESD204B up to 15.5 GSPS lane
rates. The JESD204 data link layer is highly flexible allowing
optimization of the lane count (or rate) required to support a
target throughput rate. Internal synchronization for deterministic
latency and phase alignment as well as multichip synchronization
are possible via an external alignment signal (SYSREF).
Additional features are also included in the receive and
transmit datapaths as well as elsewhere to facilitate system
integration. Both datapaths include adjustable delay lines to
compensate for mismatch in channel delay paths that may occur
Rev. A | Page 32 of 33
Data Sheet
AD9082
OUTLINE DIMENSIONS
15.10
15.00 SQ
14.90
11.80
11.60 SQ
11.50
A1 BALL
CORNER
A1 BALL
CORNER
0.70
BSC
18 16 14 12 10
17 15 13 11
8
6
4
2
9
7
5
3
1
A
B
C
E
D
F
14.80
G
14.70 SQ
14.60
H
J
L
13.60 REF
SQ
K
M
P
T
12.60
12.50 SQ
12.40
N
R
U
0.80
BSC
V
R 0.5~1.5
R 1.0
TOP VIEW
BOTTOM VIEW
1.20
1.10
1.00
DETAIL A
1.72
1.58
1.44
0.87 REF
DETAIL A
SIDE VIEW
0.525
0.500
0.475
0.40
0.36
0.32
SEATING
PLANE
0.40
0.35
0.30
COPLANARITY
0.10
0.50
0.45
0.40
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-KKAB-1
Figure 71. 324-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]
(BP-324-3)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Option
Model1
Temperature Range
Package Description
AD9082BBPZ-4D2AC
AD9082BBPZRL-4D2AC −40°C to +85°C
AD9082-FMCA-EBZ
−40°C to +85°C
324-Ball Ball Grid Array, Thermally Enhanced [BGA_ED], JESD204B and JESD204C
324-Ball Ball Grid Array, Thermally Enhanced [BGA_ED], JESD204B and JESD204C
AD9082 Evaluation Board with High Performance Analog Network
BP-324-3
BP-324-3
1 Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D21496-9/20(A)
Rev. A | Page 33 of 33
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