AD9083EBZ [ADI]
16-Channel, 125 MHz Bandwidth, JESD204B Analog-to-Digital Converter;型号: | AD9083EBZ |
厂家: | ADI |
描述: | 16-Channel, 125 MHz Bandwidth, JESD204B Analog-to-Digital Converter |
文件: | 总93页 (文件大小:2837K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
16-Channel, 125 MHz Bandwidth, JESD204B
Analog-to-Digital Converter
Data Sheet
AD9083
FEATURES
APPLICATIONS
1.0 V and 1.8 V supply operation
125 MHz usable analog input bandwidth
Sample rate up to 2 GSPS
Noise spectral density in 100 MHz bandwidth =
−145 dBFS/Hz, 2.0 GSPS encode
SNR = 66 dBFS in 100 MHz bandwidth, 2.0 GSPS encode
SNR = 82 dBFS in 15.625 MHz bandwidth, 2.0 GSPS encode
SFDR = 60 dBc in 100 MHz bandwidth, 2.0 GSPS encode
SFDR = 80 dBc in 15.625 MHz bandwidth, 2.0 GSPS encode
90 mW total power per channel at 2.0 GSPS (default settings)
Flexible input range: 0.5 V p-p to 2 V p-p differential
90 dB channel crosstalk, 2.0 GSPS encode
Digital processor
Millimeter wave imaging
Electronic beam forming and phased arrays
Multichannel wideband receivers
Electronic support measures
PRODUCT HIGHLIGHTS
1. Continuous time, Σ-Δ analog-to-digital converters (ADCs)
support signal bandwidths of up to 125 MHz with low
power and minimal filtering.
2. Integrated digital processing blocks reduce data payload
and lower overall system cost.
3. Configurable JESD204B interface reduces printed circuit
board (PCB) complexity.
4. Flexible power-down options.
CIC decimation filter
5. SPI interface controls various product features and
functions to meet specific system requirements.
6. Small, 9 mm × 9 mm, 100-ball CSP_BGA package, simple
interface, and integrated digital processing save PCB space.
Programmable DDC
Data gating
JESD204B Subclass 1 encoded outputs
Supports up to 16 Gbps/lane
Flexible sample data processing
Flexible JESD204B lane configurations
Large signal dither
Serial port control
FUNCTIONAL BLOCK DIAGRAM
AVDD
(1V)
AVDD1P8
(1.8V)
DVDD
(1V)
DVDD1P8
(1.8V)
AD9083
NCO
NCO
NCO
2
0
1
DECIMATE
BY J
GAIN
VIN1+ TO
VIN16+
MIXER
AVERAGING AND
DECIMATION FILTER
ADC
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
VIN1– TO
VIN16–
CIC DECIMATOR
JESD204B
OUTPUTS
AVERAGING AND
MIXER
MIXER
GAIN
GAIN
DECIMATION FILTER
AVERAGING AND
DECIMATION FILTER
SYNCINB±
16 CHANNELS
CLK±
CSB
PLL,
SPI AND CONTROL
REGISTERS
SYSREF±
TRIG±
JESD204B SUBCLASS1 CONTROL,
AND CLOCK DISTRIBUTION
SCLK
SDIO
AGND
DGND
PD/STBY
Figure 1.
Rev. 0
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2021 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9083
Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Nonburst Mode Datapath......................................................... 37
Burst Mode Datapath ................................................................ 41
Averaging Filters ........................................................................ 42
Mixers .......................................................................................... 43
NCO FTW Description............................................................. 43
Digital Outputs ............................................................................... 45
JESD204B Overview .................................................................. 45
Functional Overview ................................................................. 46
JESD204B Link Establishment ................................................. 46
Physical Layer (Driver) Outputs.............................................. 48
Setting Up the AD9083 Digital Interface.................................... 49
JESD204B Transport Layer Settings........................................ 49
Deterministic Latency ............................................................... 51
Multichip Synchronization....................................................... 51
Sampled SYSREF Mode ............................................................ 51
Serial Port Interface (SPI) ............................................................. 53
Configuration Using the SPI .................................................... 53
Hardware Interface .................................................................... 53
Programming Guide...................................................................... 54
Programming Sequence ............................................................ 54
Memory Map .................................................................................. 60
Logic Levels................................................................................. 60
Memory Map Register Details...................................................... 61
Applications Information ............................................................. 90
Evaluation Board Information................................................. 90
Power Delivery Network........................................................... 90
Layout Guidelines ...................................................................... 90
Outline Dimensions....................................................................... 93
Ordering Guide .............................................................................. 93
Applications ...................................................................................... 1
Product Highlights........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications .................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications ......................................................................... 5
Digital Specifications ................................................................. 10
Switching Specifications............................................................ 11
Timing Specifications ................................................................ 12
Absolute Maximum Ratings ......................................................... 13
Thermal Resistance.................................................................... 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions .......................... 14
Typical Performance Characteristics........................................... 17
Equivalent Circuits......................................................................... 25
Terminology.................................................................................... 27
Theory of Operation ...................................................................... 28
ADC Architecture ...................................................................... 28
Low-Pass, CTSD ADC Overview............................................. 29
Low-Pass Σ-Δ ADC.................................................................... 29
Analog Inputs ............................................................................. 30
Clock Inputs................................................................................ 32
Power Modes .............................................................................. 33
Temperature Diode.................................................................... 33
Digital Signal Processing Overview......................................... 33
Signal Processing Tile .................................................................... 35
Cascaded Integrator Comb (CIC) Filter ................................. 36
REVISION HISTORY
1/2021—Revision 0: Initial Version
Rev. 0 | Page 2 of 93
Data Sheet
AD9083
GENERAL DESCRIPTION
response (FIR) decimation filters (decimate by J block), or up
to three quadrature DDC channels with averaging decimation
filters for data gating applications.
The AD9083 is a 16-channel, 125 MHz bandwidth, continuous
time Σ-Δ (CTSD) ADC. The device features an on-chip,
programmable, single-pole antialiasing filter and termination
resistor that is designed for low power, small size, and ease of
use.
Users can configure the Subclass 1 JESD204B based, high speed
serialized output in a variety of lane configurations (up to four),
depending on the DDC configuration and the acceptable lane rate
of the receiving logic device. Multiple device synchronization is
supported through the SYSREF , TRIG , and SYNCINB
input pins.
The 16 ADC cores features a first-order, CTSD modulator
architecture with integrated, background nonlinearity
correction logic and self cancelling dither. Each ADC features
wide bandwidth inputs supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations.
The AD9083 has flexible power-down options that allow
significant power savings when desired. All of these features
can be programmed using a 1.8 V capable 3-wire serial port
interface (SPI).
The analog input and clock signals are differential inputs. Each
ADC has a signal processing tile to filter out of band shaped
noise from the Σ-Δ ADC and reduce the sample rate. Each tile
contains a cascaded integrator comb (CIC) filter, a quadrature
digital downconverter (DDC) with multiple finite input
The AD9083 is available in a Pb-free, 100-ball CSP_BGA and is
specified over the −40°C to +85°C industrial temperature range.
This product is protected by a U.S. patent.
Rev. 0 | Page 3 of 93
AD9083
Data Sheet
SPECIFICATIONS
Table 1 shows the AD9083 wide bandwidth real output setups used to obtain the specifications. The AD9083 is a highly programmable
device and supports many use cases. Refer to the Setting Up the AD9083 Digital Interface section and the Programming Guide section
for more details.
Table 1.
JESD204B Link Setup Parameters
Number of
fSAMPLE
(GSPS)
CIC Output Data Number of
Decimation J Decimation Rate (MSPS) Lanes (L)
Number of
Octets per
Frame (F)
Number of
Converters (M)
Samples (S)
N’
K
2
1
1
1
8
4
250
250
4
4
16
16
6
6
1
1
12 32
12 32
DC SPECIFICATIONS
AVDD = 1.0 V, AVDD1P8 = 1.8 V, DVDD = 1.0 V, DVDD1P8 = 1.8 V, programmable maximum ADC input voltage range (VMAX) = 1.8 V,
analog input (AIN) = −2.0 dBFS, −40°C ≤ TJ ≤ +115°C1, mode details as shown in Table 12, backoff = 03, EN_HP = 04, unless otherwise noted.
Typical specifications represent performance at TJ = 45°C (TA = 25°C).
Table 2.
1.0 GSPS
Typ
2.0 GSPS
Typ
Parameter5
Min
Max
Min
Max
Unit
RESOLUTION
12
16
12
16
Bits
ACCURACY
Offset Error
Offset Matching
Gain Error
Gain Matching
TEMPERATURE DRIFT
Offset Stability Error
Gain Stability Error
Voltage Reference
ANALOG INPUTS
0.33
0.75
5.2
−0.86
−10
+0.33
+0.75
+5.2
+1.55
+1.66
+20
%FS
%FS
%FS
%FS
1.1
+1.1
+3.7
14.1
0.2
0.1
14.1
0.2
0.1
ppm/°C
ppm/°C
ppm/°C
Differential Input Voltage
Range
Common-Mode Voltage (VCM
0.5
0.5
1.0
2.0
1.0
0.5
0.5
1.0
2.0
1.0
V p-p
)
0.7
RIN
0.7
RIN
V
Ω
Common-Mode Input Series
6
Resistance (RIN
)
Differential Input Termination 100
Resistance (RTERM
200
2 × RIN
100
200
2 × RIN
Ω
)
Differential Input Capacitance
Analog Full-Power Bandwidth
0.35
125
0.35
125
pF
MHz
POWER SUPPLY
AVDD
AVDD1P8
DVDD
0.95
1.7
0.95
1.7
1.0
1.8
1.0
1.8
208
65
1.05
1.9
1.05
1.9
0.95
1.7
0.95
1.7
1.0
1.8
1.0
1.8
397
95
1.05
1.9
1.05
1.9
471
102
971
48
V
V
V
V
mA
mA
mA
mA
DVDD1P8
AVDD Current (IAVDD
AVDD1P8 Current (IAVDD1P8
DVDD Current (IDVDD
DVDD1P8 (IDVDD1P8
)
)
)
592
40
797
41
)
Rev. 0 | Page 4 of 93
Data Sheet
AD9083
1.0 GSPS
Typ
2.0 GSPS
Typ
Parameter5
Min
Max
Min
Max
Unit
POWER CONSUMPTION
Total Power Dissipation
1.0
1.4
W
(Including Output Drivers)7
Power-Down Dissipation
Standby8
Power per Channel
56
676
63
86
802
90
mW
mW
mW
1 The TJ range of −40°C to +115°C translates to an TA range of −40°C to +85°C.
216-channel, 125 MSPS real output mode.
3 Backoff is the reduction in front-end gain for increased linearity.
4 EN_HP increases the SNR by 2.5 dB at an increased power dissipation.
5 See the AN-835 for definitions and for details on how these tests were completed.
6 RIN = 8 kΩ/Kvti, where Kvti is proportional to the ADC front-end gain factor, RIN = 1000 Ω for fS = 1 GSPS, and RIN = 381 for fS = 2 GSPS.
7 See Table 1 for setup details. Note that power consumption varies as a function of sample rate, the decimation options selected, and the JESD204B setup.
8 Can be controlled by SPI, ADC in low power mode.
AC SPECIFICATIONS
AVDD = 1.0 V, AVDD1P8 = 1.8 V, DVDD = 1.0 V, DVDD1P8 = 1.8 V, VMAX = 1.8 V, −40°C ≤ TJ ≤ +115°C TJ range of −40°C to +115°C
translates to a TA range of −65°C to +85°C. The mode details are as shown in Table 1 (16-channel, 125 MSPS, real output mode), unless
otherwise noted. Typical specifications represent performance at TJ = 45°C (TA = 25°C).
Table 3.
1.0 GSPS
Typ
2.0 GSPS
Max Min Typ
Parameter1
Test Conditions/Comments Min
Max
Unit
NOISE SPECTRAL DENSITY (NSD)
Flicker Noise Corner
1
1
MHz
NSD at 22 MHz
AIN = −3.0 dBFS, frequency (f) = 22 MHz
Backoff = 0, EN_HP = 0
Backoff = 3, EN_HP = 0
Backoff = 6, EN_HP = 0
Backoff = 0, EN_HP = 1
−141
−138
−136
−144
−146 −144 dBFS/Hz
−145
−142
dBFS/Hz
dBFS/Hz
−149 −146 dBFS/Hz
SIGNAL-TO-NOISE RATIO (SNR)
SNR at 22 MHz
AIN = −3.0 dBFS, f = 22 MHz
Backoff = 0, EN_HP = 0
Backoff = 3, EN_HP = 0
Backoff = 6, EN_HP = 0
Backoff = 0, EN_HP = 1
60
57
55
63
62
65
65
64
61
67
dBFS
dBFS
dBFS
dBFS
SPURIOUS-FREE DYNAMIC RANGE (SFDR)/
THIRD-ORDER HARMONIC DISTORTION (HD3)
HD3 at 22 MHz
AIN = −3.0 dBFS, f = 22 MHz
Backoff = 0, EN_HP = 0
Backoff = 3, EN_HP = 0
Backoff = 6, EN_HP = 0
Backoff = 0, EN_HP = 1
−68
−76
−74
−66
−69
−71
−75
−69
−64
−63
dBc
dBc
dBc
dBc
THIRD-ORDER INTERMODULATION DISTORTION
(IMD3)
SFDR/HD3 at 22 MHz
AIN = −9.0 dBFS, f = 22 MHz
Backoff = 0, EN_HP = 0
Backoff = 3, EN_HP = 0
Backoff = 6, EN_HP = 0
Backoff = 0, EN_HP = 1
−83
−86
−93
−87
−85
−86
−86
−85
dBFS
dBFS
dBFS
dBFS
Delete blank line
In-Band Gain Flatness2
CROSSTALK3
ANALOG INPUT BANDWIDTH, FULL POWER4
25°C
25°C
25°C
0.3
90
0.5
90
dB
dB
62.5
125
MHz
1 See AN-835 for definitions and for details on how these tests were completed.
2 The gain flatness may vary depending on the digital filter selection in the datapath.
3 Crosstalk is measured at 30.3 MHz with a −2.0 dBFS analog input on one channel, and no input on the adjacent channel.
4 Full power bandwidth of fS/16 is achieved only when CIC decimation = 4 is used.
Rev. 0 | Page 5 of 93
AD9083
Data Sheet
AC Specifications for Different Variable Settings
See the AN-835 for definitions and for details on how the tests shown in this section were completed. fS is the sample clock of the converter core.
Backoff is the reduction in front-end gain for increased linearity. EN_HP increases the SNR by 2.5 dB at an increased power dissipation.
Table 4. Variable Settings: fS = 2.0 GSPS, Backoff = 0, and EN_HP = 0
Parameters
Test Conditions/Comments
Min
Typ
Max
Unit
NSD
Flicker Noise Corner
1
MHz
At 15.625 MHz (fS/128)
At 31.25 MHz (fS/64)
At 100 MHz (fS/20)
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−155
−153
−145
dBFS/Hz
dBFS/Hz
dBFS/Hz
SNR
7.8 MHz to 23.4 MHz (15.625 MHz Bandwidth)
23.4 MHz to 39 MHz (15.625 MHz Bandwidth)
92.2 MHz to 107.8 MHz (15.625 MHz Bandwidth)
DC to 15.625 MHz
DC to 31.25 MHz
DC to 100 MHz
SFDR/HD3
At fS/128
82
80
71
82
76
66
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
AIN = −2.0 dBFS
AIN = −8.0 dBFS
−80
−75
−60
dBc
dBc
dBc
At fS/64
At fS/20
IMD3
At fS/128
At fS/64
At fS/20
−80
−75
−60
dBc
dBc
dBc
Table 5. Variable Settings: fS = 2.0 GSPS, Backoff = 3, and EN_HP = 0
Parameters
Test Conditions/Comments
Min
Typ
Max
Unit
NSD
Flicker Noise Corner
1
MHz
At 15.625 MHz (fS/128)
At 31.25 MHz (fS/64)
At 100 MHz (fS/20)
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−153
−151
−143
dBFS/Hz
dBFS/Hz
dBFS/Hz
SNR
7.8 MHz to 23.4 MHz (15.625 MHz Bandwidth)
23.4 MHz to 39 MHz (15.625 MHz Bandwidth)
92.2 MHz to 107.8 MHz (15.625 MHz Bandwidth)
DC to 15.625 MHz
DC to 31.25 MHz
DC to 100 MHz
SFDR/HD3
At fS/128
80
74
64
80
74
64
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
AIN = −2.0 dBFS
AIN = −8.0 dBFS
−81
−78
−63
dBc
dBc
dBc
At fS/64
At fS/20
IMD3
At fS/128
At fS/64
At fS/20
−81
−77
−63
dBc
dBc
dBc
Rev. 0 | Page 6 of 93
Data Sheet
AD9083
Table 6. Variable Settings: fS = 2.0 GSPS, Backoff = 6, and EN_HP = 0
Parameters
Test Conditions/Comments
Min
Typ
Max
Unit
NSD
Flicker Noise Corner
1
MHz
At 15.625 MHz (fS/128)
At 31.25 MHz (fS/64)
At 100 MHz (fS/20)
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−150
−148
−140
dBFS/Hz
dBFS/Hz
dBFS/Hz
SNR
7.8 MHz to 23.4 MHz (15.625 MHz Bandwidth)
23.4 MHz to 39 MHz (15.625 MHz Bandwidth)
92.2 MHz to 107.8 MHz (15.625 MHz Bandwidth)
DC to 15.625 MHz
DC to 31.25 MHz
DC to 100 MHz
SFDR/HD3
At fS/128
77
71
61
77
71
61
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
AIN = −2.0 dBFS
AIN = −8.0 dBFS
−82
−81
−66
dBc
dBc
dBc
At fS/64
At fS/20
IMD3
At fS/128
At fS/64
At fS/20
−82
−80
−66
dBc
dBc
dBc
Table 7. Variable Settings: fS = 2.0 GSPS, Backoff = 0, and EN_HP = 1
Parameters
Test Conditions/Comments
Min
Typ
Max
Unit
NSD
Flicker Noise Corner
1
MHz
At 15.625 MHz (fS/128)
At 31.25 MHz (fS/64)
At 100 MHz (fS/20)
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−157
−155
−147
dBFS/Hz
dBFS/Hz
dBFS/Hz
SNR
7.8 MHz to 23.4 MHz (15.625 MHz Bandwidth)
23.4 MHz to 39 MHz (15.625 MHz Bandwidth)
92.2 MHz to 107.8 MHz (15.625 MHz Bandwidth)
DC to 15.625 MHz
DC to 31.25 MHz
DC to 100 MHz
SFDR/HD3
At fS/128
85
79
69
85
79
69
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
AIN = −2.0 dBFS
AIN = −8.0 dBFS
−80
−75
−60
dBc
dBc
dBc
At fS/64
At fS/20
IMD3
At fS/128
At fS/64
At fS/20
−80
−75
−60
dBc
dBc
dBc
Rev. 0 | Page 7 of 93
AD9083
Data Sheet
Table 8. Variable Settings: fS = 1.0 GSPS, Backoff = 0, and EN_HP = 0
Parameters
Test Conditions/Comments
Min
Typ
Max
Unit
NSD
Flicker Noise Corner
1
MHz
At 7.8125 MHz (fS/128)
At 15.625 MHz (fS/64)
At 50 MHz (fS/20)
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−152
−151
−144
dBFS/Hz
dBFS/Hz
dBFS/Hz
SNR
3.9 MHz to 11.7 MHz (7.8125 MHz Bandwidth)
11.7 MHz to 19.5 MHz (7.8125 MHz Bandwidth)
46.1 MHz to 53.9 MHz (7.8125 MHz Bandwidth)
DC to 7.8125 MHz
DC to 15.625 MHz
DC to 50 MHz
SFDR/HD3
82
80
71
82
76
66
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
At fS/128
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−80
−75
−60
dBc
dBc
dBc
HD3 at fS/64
HD3 at fS/20
SFDR/IMD3
At fS/128
At fS/64
At fS/20
AIN = −8.0 dBFS
AIN = −8.0 dBFS
AIN = −8.0 dBFS
−80
−75
−60
dBc
dBc
dBc
Table 9. Variable Settings: fS = 1.0 GSPS, Backoff = 3, and EN_HP = 0
Parameters
Test Conditions/Comments
Min
Typ
Max
Unit
NSD
Flicker Noise Corner
1
MHz
At 7.8125 MHz (fS/128)
At 15.625 MHz (fS/64)
At 50 MHz (fS/20)
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−150
−149
−142
dBFS/Hz
dBFS/Hz
dBFS/Hz
SNR
3.9 MHz to 11.7 MHz (7.8125 MHz Bandwidth)
11.7 MHz to 19.5 MHz (7.8125 MHz Bandwidth)
46.1 MHz to 53.9 MHz (7.8125 MHz Bandwidth)
DC to 7.8125 MHz
DC to 15.625 MHz
DC to 50 MHz
SFDR/HD3
80
74
64
80
74
64
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
At fS/128
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−81
−78
−63
dBc
dBc
dBc
HD3 at fS/64
HD3 at fS/20
SFDR/IMD3
At fS/128
At fS/64
At fS/20
AIN = −8.0 dBFS
AIN = −8.0 dBFS
AIN = −8.0 dBFS
−81
−77
−63
dBc
dBc
dBc
Rev. 0 | Page 8 of 93
Data Sheet
AD9083
Table 10. Variable Settings: fS = 1.0 GSPS, Backoff = 6, and EN_HP = 0
Parameters
Test Conditions/Comments
Min
Typ
Max
Unit
NSD
Flicker Noise Corner
1
MHz
At 7.8125 MHz (fS/128)
At 15.625 MHz (fS/64)
At 50 MHz (fS/20)
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−147
−146
−139
dBFS/Hz
dBFS/Hz
dBFS/Hz
SNR
3.9 MHz to 11.7 MHz (7.8125 MHz Bandwidth)
11.7 MHz to 19.5 MHz (7.8125 MHz Bandwidth)
46.1 MHz to 53.9 MHz (7.8125 MHz Bandwidth)
DC to 7.8125 MHz
DC to 15.625 MHz
DC to 50 MHz
SFDR/HD3
77
71
61
77
71
61
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
At fS/128
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−82
−81
−66
dBc
dBc
dBc
HD3 at fS/64
HD3 at fS/20
SFDR/IMD3
At fS/128
At fS/64
At fS/20
AIN = −8.0 dBFS
AIN = −8.0 dBFS
AIN = −8.0 dBFS
−82
−80
−66
dBc
dBc
dBc
Table 11. Variable Settings: fS = 1.0 GSPS, Backoff = 0, and EN_HP = 1
Parameters
Test Conditions/Comments
Min
Typ
Max
Unit
NSD
Flicker Noise Corner
1
MHz
At 7.8125 MHz (fS/128)
At 15.625 MHz (fS/64)
At 50 MHz (fS/20)
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−154
−153
−146
dBFS/Hz
dBFS/Hz
dBFS/Hz
SNR
3.9 MHz to 11.7 MHz (7.8125 MHz Bandwidth)
11.7 MHz to 19.5 MHz (7.8125 MHz Bandwidth)
46.1 MHz to 53.9 MHz (7.8125 MHz Bandwidth)
DC to 7.8125 MHz
DC to 15.625 MHz
DC to 50 MHz
SFDR/HD3
85
79
69
85
70
69
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
At fS/128
AIN = −2.0 dBFS
AIN = −2.0 dBFS
AIN = −2.0 dBFS
−80
−75
−60
dBc
dBc
dBc
HD3 at fS/64
HD3 at fS/20
SFDR/IMD3
At fS/128
At fS/64
At fS/20
AIN = −8.0 dBFS
AIN = −8.0 dBFS
AIN = −8.0 dBFS
−80
−75
−60
dBc
dBc
dBc
Rev. 0 | Page 9 of 93
AD9083
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.0 V, AVDD1P8= 1.8 V, DVDD = 1.0 V, DVDD1P8 = 1.8 V, VMAX = 1.8 V1, AIN = −2.0 dBFS, −40°C ≤ TJ ≤ +115°C2, mode
details as shown in Table 13, unless otherwise noted. Typical specifications represent performance at TJ = 45°C (TA = 25°C).
Table 12.
Parameter
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
300
800
0.5
100
1
1800
mV p-p
V
Ω
pF
SYSREF and TRIG INPUTS (SYSREF+, SYSREF−, TRIG+, AND TRIG−)
Logic Compliance
LVDS
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Differential)
LOGIC INPUT (SDIO, SCLK, CSB, PD/STBY, AND RSTB)
Logic Compliance
700
0.5
100
1
1100
mV p-p
V
Ω
pF
CMOS
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
0.7 × DVDD1P8
DVDD1P8 – 0.45
V
V
0.3 × DVDD1P8
High impedance
CMOS
LOGIC OUTPUT (SDIO)
Logic Compliance
Logic 1 Voltage (High Output Current (IOH) = 800 µA)
Logic 0 Voltage (Low Output Current (IOL) = 50 µA)
SYNCINB INPUT (SYNCINB+/SYNCINB−)
Logic Compliance
V
V
0.45
LVDS
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
700
0.45
100
1
1900
mV p-p
V
kΩ
pF
SYNCINB+ INPUT
Logic Compliance
CMOS
Logic 1 Voltage
Logic 0 Voltage
0.7 × DVDD1P8
V
V
0.3 × DVDD1P8
Input Resistance
High impedance
DIGITAL OUTPUTS (SERDOUTx , x = 0 TO 3)
Standards Compliance
Differential Output Voltage
Differential Termination Impedance
JESD204B
675
108
mV p-p
Ω
80
120
1 VMAX is the programmable maximum ADC input voltage range.
2 The TJ range of −40°C to +115°C translates to an TA range of −65°C to +85°C.
3 16-channel 125 MSPS real output mode.
Rev. 0 | Page 10 of 93
Data Sheet
AD9083
SWITCHING SPECIFICATIONS
AVDD = 1.0 V, AVDD1P8 = 1.8 V, DVDD = 1.0 V, DVDD1P8 = 1.8 V, VMAX = 1.8 V1, −40°C ≤ TJ ≤ +115°C2, mode details as shown in
Table 13, unless otherwise noted. Typical specifications represent performance at TJ = 45°C (TA = 25°C).
Table 13.
Parameter
Min
Typ
Max
Unit
CLOCK
Clock Rate (at CLK+/CLK− Pins)4
ADC Sample Rate5
Clock Pulse Width
50
1
1
250
500
2
10
MHz
GSPS
ns
OUTPUT PARAMETERS
Unit Interval (UI)6
62.5
0.25
4000
16
ps
ps
ps
ms
Gbps
Rise Time (tR) (20% to 80% into 100 Ω Load)
Fall Time (tF) (20% to 80% into 100 Ω Load)
Phase-Locked Loop (PLL) Lock Time7
Data Rate per Channel (NRZ)8
30
30
5
1 VMAX is the programmable maximum ADC input voltage range.
2 The TJ range of −40°C to +115°C translates to an TA range of −65°C to +85°C.
3 16-channel 125 MSPS real output mode.
4 Input clock to the on-chip PLL (Pin K3 and Pin J3).
5 ADC sample clock of the converter core.
6 Baud rate = 1/UI. A subset of this range can be supported.
7 Lock times may vary depending on the JESD204B link setup.
8 Default L = 4. This number can be changed based on the sample rate and decimation ratio.
Rev. 0 | Page 11 of 93
AD9083
Data Sheet
TIMING SPECIFICATIONS
Table 14.
Parameter
Description
Min Typ Max Unit
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tACCESS
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Maximum time delay between falling edge of SCLK and output data valid for a
read operation
4
4
10
2
2
ns
ns
ns
ns
ns
ns
ns
ns
4
4
2
4
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an input relative to
the SCLK rising edge
6
ns
t
t
t
t
t
H
DS
HIGH
CLK
ACCESS
t
LOW
t
t
DH
S
CSB
SCLK
DON’T CARE
DON’T CARE
DON’T CARE
R/W
A14
A13
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
SDIO DON’T CARE
Figure 2. Serial Port Interface Timing Diagram
Rev. 0 | Page 12 of 93
Data Sheet
AD9083
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 15.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
Electrical
AVDD to AGND
AVDD1P8 to AGND
DVDD to DGND
DVDD1P8 to DGND
AGND to DGND
VINx to AGND
CLK to AGND
1.05 V
2.0 V
1.05 V
2.0 V
Table 16. Thermal Resistance
Package Type
BC-100-81
θJA
θJC_TOP θJB
ΨJB
ΨJT
Unit
23.4 10.3
8.9
9.0
1.2
°C/W
−0.3 V to +0.3 V
1 Test Condition 1: Thermal impedance simulated values are based on JEDEC
2S2P thermal test board with 190 thermal vias. See JEDEC JESD-51.
AGND − 0.3 V to AVDD1P8 + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
DGND − 0.3 V to DVDD1P8 + 0.3 V
SCLK, SDIO, CSB, RSTB,
PD/STBY to DGND
ESD CAUTION
SYSREF , TRIG to AGND
SYNCINB to DGND
Temperature
AGND − 0.3 V to AVDD + 0.3 V
DGND − 0.3 V to DVDD1P8 + 0.3 V
Junction Range
Storage Range
(Ambient)
−40°C to +125°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Rev. 0 | Page 13 of 93
AD9083
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9083
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
DGND
SYNCINB+
SYNCINB–
CSB
VIN1+
VIN2+
VIN3+
VIN4+
VIN5+
DNC
DVDD1P8
DGND
DVDD1P8
DGND
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
CLK–
CLK+
SCLK
SDIO
VIN1–
PD/STDBY
RSTB
VIN2–
AGND
AVDD
VIN3–
AGND
AGND
AVDD
AVDD
AGND
AGND
VIN14–
VIN14+
VIN4–
AVDD1P8
AVDD1P8
AGND
VIN5–
VIN6–
TD
VIN6+
VIN7+
VIN8+
VIN9+
VIN10+
VIN11+
RBIAS
AGND
SEROUT0–
SEROUT1–
SEROUT2–
SEROUT3–
TRIG+
SEROUT0+
SEROUT1+
SEROUT2+
SEROUT3+
DGND
DGND
DGND
DGND
DGND
REF_VCO
AVDD
VIN7–
AGND
AVDD
VIN8–
AVDD
AVDD
AGND
VIN9–
G
H
J
VCOARSE_
VCO
AVDD
AVDD1P8
AVDD1P8
VIN13–
VIN10–
VIN11–
VIN12–
VIN12+
AGND
VIN16–
VIN16+
AVDD1P8
VIN15–
VIN15+
TRIG–
SYSREF–
SYSREF+
K
DNC
AGND
VIN13+
LEGEND:
1.0V SUPPLY
DIGITAL INPUT
1.8V SUPPLY
SERDES OUTPUT
DIGITAL CONTROLS
STATIC CONTROLS
GROUND RETURN
ANALOG INPUT
Figure 3. Pin Configuration
Table 17. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
Analog Power Supply (1.0 V Nominal).
Analog Power Supply for Clock (1.0 V Nominal).
Analog Power Supply for Internal PLL (1.0 V Nominal).
Analog Power Supply (1.8 V Nominal).
Power Supplies
D6, E6, E7, F6, F7, G6
F5
J4
C8, D8, G8, H6, H8
D3, E3, F3, G3
B3, C3, H3
B1
B2
AVDD
AVDD
AVDD
AVDD1P8
DVDD
DVDD
DVDD1P8
DVDD1P8
Power
Power
Power
Power
Power
Power
Power
Power
Digital Power Supply (1.0 V Nominal).
Digital Driver Power Supply (1.0 V Nominal).
Digital Driver Power Supply (1.8 V Nominal).
Digital Power Supply for I/O and SPI (1.8 V Nominal).
Rev. 0 | Page 14 of 93
Data Sheet
AD9083
Pin No.
Mnemonic
Type
Description
C6, C7, D7, E8, F8, G7, H5, H7, K10 AGND
Ground
Analog Ground. These AGND pins connect to the
analog ground plane.
E5
K4
AGND
AGND
DGND
Ground
Ground
Ground
Ground Reference for AVDD.
Ground Reference for AVDD.
Digital Ground. These DGND pins connect to the
digital ground plane.
D4, E4, F4, G4
A1, C1, C2, H2
DGND
Ground
Digital Driver Ground. These DGND pins connect to
the digital driver ground plane.
Analog
A5, B5
A6, B6
A7, B7
A8, B8
A9, B9
C9, C10
D9, D10
E9, E10
F9, F10
G9, G10
H9, H10
J9, K9
VIN1+, VIN1−
VIN2+, VIN2−
VIN3+, VIN3−
VIN4+, VIN4−
VIN5+, VIN5−
VIN6−, VIN6+
VIN7−, VIN7+
VIN8−, VIN8+
VIN9−, VIN9+
VIN10−, VIN10+
VIN11−, VIN11+
VIN12−, VIN12+
VIN13−, VIN13+
VIN14−, VIN14+
VIN15−, VIN15+
VIN16−, VIN16+
CLK−, CLK+
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
ADC 1 Analog Input True/Complement.
ADC 2 Analog Input True/Complement.
ADC 3 Analog Input True/Complement.
ADC 4 Analog Input True/Complement.
ADC 5 Analog Input True/Complement.
ADC 6 Analog Input Complement/True.
ADC 7 Analog Input Complement/True.
ADC 8 Analog Input Complement/True.
ADC 9 Analog Input Complement/True.
ADC 10 Analog Input Complement/True.
ADC 11 Analog Input Complement/True.
ADC 12 Analog Input Complement/True.
ADC 13 Analog Input Complement/True.
ADC 14 Analog Input Complement/True.
ADC 15 Analog Input Complement/True.
ADC 16 Analog Input Complement/True.
Clock Input Complement/True.
J8, K8
J7, K7
J6, K6
J5, K5
J3, K3
Digital Inputs
J2, K2
SYSREF−, SYSREF+
SYNCINB+, SYNCINB-
TRIG+, TRIG−
Input
Input
Input
Active High JESD204B LVDS/CML System Reference
Input Complement/True.
Active Low JESD204B LVDS Sync Input
True/Complement.
Trigger Input LVDS. These TRIG pins can be left
floating if disabled.
A2, A3
H1, J1
Data Outputs
D1, D2
E1, E2
F1, F2
G1, G2
SERDOUT0−, SERDOUT0+
SERDOUT1−, SERDOUT1+
SERDOUT2−, SERDOUT2+
SERDOUT3−, SERDOUT3+
Output
Output
Output
Output
Lane 0 Output Data Complement/True.
Lane 1 Output Data Complement/True.
Lane 2 Output Data Complement/True.
Lane 3 Output Data Complement/True.
Digital Controls
C5
PD/STBY
Input
Power-Down Input (Active High). The operation of
the PD/STBY pin depends on the SPI mode and can
be configured as power-down or standby.
D5
A4
B4
C4
RSTB
CSB
SCLK
SDIO
Input
Input
Input
Input/output
Active Low Input for Device Reset.
SPI Chip Select (Active Low).
SPI Serial Clock.
SPI Serial Data Input/Output.
Rev. 0 | Page 15 of 93
AD9083
Data Sheet
Pin No.
Mnemonic
Type
Description
Static Control
B10
J10
H4
TD
RBIAS
REG_VCO
Temperature Diode Pin.
Current Reference Resistor, 5 kΩ to AGND.
Clock Multiplier PLL Voltage Regulator Bypass
Capacitor. Low effective series resistance (ESR), low
effective series inductance (ESL), 2.2 µF capacitor to
AGND. Inductance between package and capacitor
< 1 nH.
G5
VCOARSE_VCO
DNC
Clock Multiplier PLL Coarse Tuning Loop Filter, 33 nF
Capacitor to AGND.
Do Not Connect. Leave the DNC pins floating.
A10, K1
Rev. 0 | Page 16 of 93
Data Sheet
AD9083
TYPICAL PERFORMANCE CHARACTERISTICS
Nominal supply voltages, AIN = −2.0 dBFS, TJ = 45°C, and 128k FFT, unless otherwise noted.
0
–12
–24
–36
–48
–60
–72
–84
–96
–108
–120
0
–12
–24
–36
–48
–60
–72
–84
–96
–108
–120
100k
1M
10M
100M
500M
500M
50M
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4. ADC Noise Floor at Backoff = 3 dB, 1 GSPS
Figure 7. ADC Noise Floor at Backoff = 3 dB, 2 GSPS
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
BACKOFF = 6dB
BACKOFF = 3dB
BACKOFF = 0dB
BACKOFF = 6dB
BACKOFF = 3dB
BACKOFF = 0dB
100k
1M
10M
100M
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 5. ADC NSD at Various Backoff Values, 1 GSPS
Figure 8. ADC NSD at Various Backoff Values, 2 GSPS
0
–12
–24
–36
–48
–60
–72
–84
–96
–108
–120
0
–12
–24
–36
–48
–60
–72
–84
–96
–108
–120
BACKOFF = 6dB
BACKOFF = 3dB
BACKOFF = 0dB
BACKOFF = 6dB
BACKOFF = 3dB
BACKOFF = 0dB
HD2
HD3
HD3
HD2
1M
10M
90M
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 9. HD2 and HD3 at Various Backoff Values, 2 GSPS
Figure 6. Harmonic Distortion 2 (HD2) and Harmonic Distortion 3 (HD3) at
Various Backoff Values, 1 GSPS
Rev. 0 | Page 17 of 93
AD9083
Data Sheet
–130
–133
–136
–139
–142
–145
–148
–151
–154
–157
–138
–140
–142
–144
–146
–148
–150
–152
–154
–156
–158
HP DISABLED
HP ENABLED
V
V
= 0.5V
= 2.0V
MAX
MAX
–160
100k
200k
1M
10M
FREQUENCY (Hz)
100M
1M
10M
FREQUENCY (Hz)
100M
100M
100M
Figure 13. ADC NSD at Minimum and Maximum VMAX Values, 2 GSPS
Figure 10. ADC NSD with and Without EN_HP, 1 GSPS
–140
–140
–142
–144
–146
–148
–150
–152
–154
–156
–158
–160
NSD (–2dBFS SIGNAL)
NSD (NO SIGNAL)
HP DISABLED
HP ENABLED
–142
–144
–146
–148
–150
–152
–154
–156
–158
–160
100k
1M
10M
FREQUENCY (Hz)
100M
100k
1M
10M
FREQUENCY (Hz)
Figure 14. ADC NSD with and Without Full-Scale Input Signal, 1 GSPS
Figure 11. ADC NSD with and Without EN_HP, 2 GSPS
–140
–135
–137
–139
–141
–143
–145
–147
–149
–151
–153
–155
NSD (–2dBFS SIGNAL)
NSD (NO SIGNAL)
V
V
= 0.5V
= 2.0V
MAX
MAX
–142
–144
–146
–148
–150
–152
–154
–156
–158
–160
100k
1M
10M
FREQUENCY (Hz)
100M
100k
1M
10M
FREQUENCY (Hz)
Figure 15. ADC NSD with and Without Full-Scale Input Signal, 2 GSPS
Figure 12. ADC NSD at Minimum and Maximum VMAX Values, 1 GSPS
Rev. 0 | Page 18 of 93
Data Sheet
AD9083
–135
100
90
80
70
60
50
40
30
20
10
0
SNR BW = 15MHz
SNR BW = 50MHz
SNR BW = 125MHz
f
f
f
= 2.3MHz
= 12MHz
= 48MHz
IN
IN
IN
–137
–139
–141
–143
–145
–147
–149
–151
–153
–155
100k
1M
10M
FREQUENCY (Hz)
100M
–65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
5
AMPLITUDE (dBFS)
Figure 16. ADC NSD at Different Input Frequencies, 1 GSPS
Figure 19. ADC SNR vs. Input Amplitude, 2 GSPS
–140
–142
–144
–146
–148
–150
–152
–154
–156
–158
–160
–50
BACKOFF = 0dB
BACKOFF = 3dB
BACKOFF = 6dB
f
f
f
= 5MHz
= 25MHz
= 100MHz
IN
IN
IN
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
200k
1M
10M
FREQUENCY (Hz)
100M
1.0
2.9
4.7
6.6
8.5 10.3 12.2 14.1 16.0 17.8 19.7
FREQUENCY (MHz)
Figure 17. ADC NSD at Different Input Frequencies, 2 GSPS
Figure 20. ADC HD2 vs. Frequency at Various Backoff Values and
AIN = −2 dB, 1 GSPS
100
–70
SNR BW = 7.5MHz
SNR BW = 25MHz
SNR BW = 62.5MHz
BACKOFF = 0dB
BACKOFF = 3dB
BACKOFF = 6dB
90
80
70
60
50
40
30
20
10
0
–72
–74
–76
–78
–80
–82
–84
–86
–88
–90
–65 –60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
5
2.3
6.1
9.8 13.6 17.4 21.1 24.9 28.7 32.5 36.2 40.0
FREQUENCY (MHz)
AMPLITUDE (dBFS)
Figure 18. ADC SNR vs. Input Amplitude, 1 GSPS
Figure 21. ADC HD2 vs. Frequency at Various Backoff Values and
AIN = −2 dB, 2 GSPS
Rev. 0 | Page 19 of 93
AD9083
Data Sheet
–65
–69
–73
–77
–81
–85
–89
–93
–97
–101
–40
–47
–54
–61
–68
–75
–82
–89
–96
–103
–110
BACKOFF = 0dB
BACKOFF = 3dB
BACKOFF = 6dB
BACKOFF = 0dB
BACKOFF = 3dB
BACKOFF = 6dB
–105
1.0
2.9
4.7
6.6
8.5 10.3 12.2 14.1 16.0 17.8 19.7
FREQUENCY (MHz)
2.3
6.1
9.8 13.6 17.4 21.1 24.9 28.7 32.5 36.2 40.0
FREQUENCY (MHz)
Figure 22. ADC HD2 vs. Frequency at Various Backoff Values and
AIN = −10 dB, 1 GSPS
Figure 25. ADC HD3 vs. Frequency at Various Backoff Values and
AIN = −2 dB, 2 GSPS
–65
–50
BACKOFF = 0dB
BACKOFF = 0dB
–69
–56
–62
–68
–74
–80
–86
–92
–98
–104
–110
BACKOFF = 3dB
BACKOFF = 6dB
BACKOFF = 3dB
BACKOFF = 6dB
–73
–77
–81
–85
–89
–93
–97
–101
–105
2.3
6.1
9.8 13.6 17.4 21.1 24.9 28.7 32.5 36.2 40.0
FREQUENCY (MHz)
1.0
2.9
4.7
6.6
8.5 10.3 12.2 14.1 16.0 17.8 19.7
FREQUENCY (MHz)
Figure 23. ADC HD2 vs. Frequency at Various Backoff Values and
AIN = −10 dB, 2 GSPS
Figure 26. ADC HD3 vs. Frequency at Various Backoff Values and
AIN = −10 dB, 1 GSPS
–50
–50
BACKOFF = 0dB
BACKOFF = 0dB
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–56
–62
–68
–74
–80
–86
–92
–98
–104
–110
BACKOFF = 3dB
BACKOFF = 6dB
BACKOFF = 3dB
BACKOFF = 6dB
1.0
2.9
4.7
6.6
8.5 10.3 12.2 14.1 16.0 17.8 19.7
FREQUENCY (MHz)
2.3
6.1
9.8 13.6 17.4 21.1 24.9 28.7 32.5 36.2 40.0
FREQUENCY (MHz)
Figure 24. ADC HD3 vs. Frequency at Various Backoff Values and
AIN = −2 dB, 1 GSPS
Figure 27. ADC HD3 vs. Frequency at Various Backoff Values and
AIN = −10 dB, 2 GSPS
Rev. 0 | Page 20 of 93
Data Sheet
AD9083
–120
100
95
90
85
80
75
70
65
60
55
50
–40°C
+25°C
+110°C
SNR BW = 15MHz
SNR BW = 50MHz
SNR BW = 125MHz
–124
–128
–132
–136
–140
–144
–148
–152
–156
–160
100k
1M
10M
100M
500M
–40 –25 –10
5
20
35
50
65
80
95
110
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 28. ADC NSD vs. Junction Temperature, 1 GSPS
Figure 31. ADC SNR vs. Junction Temperature, 2 GSPS
–110
–114
–118
–122
–126
–130
–134
–138
–142
–146
–150
506.0
505.6
505.2
504.8
504.4
504.0
503.6
503.2
502.8
502.4
502.0
–40°C
+25°C
+110°C
100k
1M
10M
100M
1G
–40
–10
20
50
80
110
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 29. ADC NSD vs. Junction Temperature, 2 GSPS
Figure 32. Reference Voltage vs. Junction Temperature
100
95
90
85
80
75
70
65
60
55
50
500
450
400
350
300
250
200
150
100
50
SNR BW = 7.5MHz
SNR BW = 25MHz
SNR BW = 62.5MHz
AVDD 1V
AVDD 1.8V
0
1.0
–40 –25 –10
5
20
35
50
65
80
95
110
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
TEMPERATURE (°C)
SAMPLE RATE (GHz)
Figure 30. ADC SNR vs. Junction Temperature, 1 GSPS
Figure 33. Supply Current vs. Sample Rate (Digital Domain Currents Vary
with the DSP and JESD204B Setup)
Rev. 0 | Page 21 of 93
AD9083
Data Sheet
90
86
82
78
74
70
66
62
58
54
50
0
–11
–22
–33
–44
–55
–66
–77
–88
–99
–110
BW = 2MHz
BW = 10MHz
BW = 25MHz
IMD3 = 83.2dBFS
5.0 16.5 28.0 39.5 51.0 62.5 74.0 85.5 97.0 108.5 120.0
37
39
41
43
45
47
49
51
53
55
57
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 34. SNR vs. Sliding IF
Figure 37. Two-Tone FFT, Backoff = 6, fIN1 = 45.4 MHz, fIN2 = 48 MHz, AIN1 and
AIN2 = −8 dBFS, 1 GSPS
0
0
–11
–11
IMD3 = 79dBFS
IMD3 = 69.4dBFS
–22
–33
–44
–55
–66
–77
–88
–99
–110
–22
–33
–44
–55
–66
–77
–88
–99
–110
37
39
41
43
45
47
49
51
53
55
57
87
89
91
93
95
97
99
101 103 105 107
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 35. Two-Tone FFT, Backoff = 0, fIN1 = 45.4 MHz, fIN2 = 48 MHz, AIN1 and
AIN2 = −8 dBFS, 1 GSPS
Figure 38. Two-Tone FFT, Backoff = 0, fIN1 = 96.6 MHz, fIN2 = 99 MHz, AIN1 and
AIN2 = −8 dBFS, 2 GSPS
0
0
–11
–11
IMD3 = 79.4dBFS
IMD3 = 74.3dBFS
–22
–22
–33
–44
–55
–66
–77
–88
–99
–110
–33
–44
–55
–66
–77
–88
–99
–110
37
39
41
43
45
47
49
51
53
55
57
87
89
91
93
95
97
99
101 103 105 107
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 36. Two-Tone FFT, Backoff = 3, fIN1 = 45.4 MHz, fIN2 = 48 MHz, AIN1 and
AIN2 = −8 dBFS, 1 GSPS
Figure 39. Two-Tone FFT, Backoff = 3, fIN1 = 96.6 MHz, fIN2 = 99 MHz, AIN1 and
AIN2 = −8 dBFS, 2 GSPS
Rev. 0 | Page 22 of 93
Data Sheet
AD9083
0
–11
–22
–33
–44
–55
–66
–77
–88
–99
–110
0
–11
–22
–33
–44
–55
–66
–77
–88
–99
–110
IMD3 = 91.6dBFS
IMD3 = 79dBFS
87
89
91
93
95
97
99
101 103 105 107
37
39
41
43
45
47
49
51
53
55
57
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 40. Two-Tone FFT, Backoff = 6, fIN1 = 96.6 MHz, fIN2 = 99 MHz, AIN1 and
AIN2 = −8 dBFS, 2 GSPS
Figure 42. Two-Tone FFT, Backoff = 3, fIN1 = 45.4 MHz, fIN2 = 48 MHz, AIN1 and
AIN2 = −16 dBFS, 1 GSPS
0
0
–11
–11
IMD3 = 92dBFS
IMD3 = 87.5dBFS
–22
–33
–44
–55
–66
–77
–88
–99
–110
–22
–33
–44
–55
–66
–77
–88
–99
–110
37
39
41
43
45
47
49
51
53
55
57
37
39
41
43
45
47
49
51
53
55
57
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 41. Two-Tone FFT, Backoff = 0, fIN1 = 45.4 MHz, fIN2 = 48 MHz, AIN1 and
AIN2 = −16 dBFS, 1 GSPS
Figure 43. Two-Tone FFT, Backoff = 6, fIN1 = 45.4 MHz, fIN2 = 48 MHz, AIN1 and
AIN2 = −16 dBFS, 1 GSPS
Rev. 0 | Page 23 of 93
AD9083
Data Sheet
0
–11
–22
–33
–44
–55
–66
–77
–88
–99
0
–11
–22
–33
–44
–55
–66
–77
–88
–99
–110
IMD3 = 88.3dBFS
IMD3 = 86.5dBFS
–110
87
89
91
93
95
97
99
101 103 105 107
87
89
91
93
95
97
99
101 103 105 107
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 44. Two-Tone FFT, Backoff = 0, fIN1 = 96.6 MHz, fIN2 = 99 MHz, AIN1 and
AIN2 = −16 dBFS, 2 GSPS
Figure 46. Two-Tone FFT, Backoff = 6, fIN1 = 96.6 MHz, fIN2 = 99 MHz, AIN1 and
AIN2 = −16 dBFS, 2 GSPS
0
–11
IMD3 = 89.4dBFS
–22
–33
–44
–55
–66
–77
–88
–99
–110
87
89
91
93
95
97
99
101 103 105 107
FREQUENCY (MHz)
Figure 45. Two-Tone FFT, Backoff = 3, fIN1 = 96.6 MHz, fIN2 = 99 MHz, AIN1 and
AIN2 = −16 dBFS, 2 GSPS
Rev. 0 | Page 24 of 93
Data Sheet
AD9083
EQUIVALENT CIRCUITS
AVDD1P8
DVDD1P8
C
DVDD1P8
VIN1+
R/2
R/2
C
AVDD1P8
400Ω
SDIO
GND
GND
= 100Ω, 200Ω, OPEN
R
R
TERM
AVDD1P8
TERM
I
GND
VIN1–
O EN
R/2
R/2
DGND
C
DGND
GND
GND
Figure 47. Analog Inputs
Figure 50. SDIO Input/Output
AVDD
DE-EMPHASIS/SWING
CONTROL (SPI)
CLK+/
SYSREF+/
TRIG+
DVDD
30Ω
172kΩ
V
CM
(0.5V)
SERDOUTx+
x = 0, 1, 2, 3
100Ω
GND
AVDD
172kΩ
DATA+
CLK–/
SYSREF–/
TRIG–
GND
DVDD
OUTPUT
DRIVER
30Ω
DATA–
GND
SERDOUTx–
x = 0, 1, 2, 3
GND
Figure 48. CLK , SYSREF , and TRIG Inputs
Figure 51. Digital Outputs
DVDD1P8
AVDD1P8
1x DIODE
VOLTAGE
TD
TEMPERATURE
DIODE
ENABLE
20x DIODE
VOLTAGE
RSTB/SCLK/
PD/STBY/CSB
TEMPERATURE
DIODE SELECT
GND GND
400Ω
GND
DGND
Figure 52. TD (Temperature Diode) Pin
Figure 49. RSTB, SCLK, PD/STBY, and CSB Inputs
Rev. 0 | Page 25 of 93
AD9083
Data Sheet
DVDD1P8
600Ω
DVDD1P8
CMOS_EN
DVDD1P8
DGND
SYNCINB+
300Ω
50Ω
DGND
DGND
EN_LVDS
DVDD1P8
LVDS
RECEIVER
DVDD1P8
50Ω
SYNCINB–
300Ω
DGND
DGND
Figure 53. SYNCINB Input
Rev. 0 | Page 26 of 93
Data Sheet
AD9083
TERMINOLOGY
Noise Spectral Density (NSD)
In-Band Noise
The NSD is the noise power normalized to 1 Hz bandwidth (at
a particular frequency) relative to the full-scale of the ADC
(dBFS). NSD is given in units of dBFS/Hz. Unlike a descrete-
time flash type ADC, a Σ-Δ ADC displays uneven NSD across
the spectrum from dc up to fS. Typical NSD at various
inflection points are reported in the specifications. The total
SNR is not always a straightforward calculation and it is often
useful to think in terms of noise density instead of SNR.
Achieving a good SNR is dependent on filtering out the
wideband CTSD ADC quantization noise.
In-band noise is the integrated noise power measured over a
user defined bandwidth relative to the full-scale of the ADC (in
dBFS). This bandwidth is typically equal to an intermediate
frequency (IF) pass-band.
Third-Order Intermodulation Distortion (IMD3)
IMD3 is a figure of merit used to quantify the linearity of a
component or system. Two equal amplitude, unmodulated
carriers at specified frequencies (f1 and f2) injected in a nonlinear
system exhibiting third-order nonlinearities produce IMD
components at 2f1 − f2 and 2f2 − f1. Note that the IMD3
performance of an ADC does not necessarily follow the 3:1 rule
that is typical of RF/IF linear devices. IMD3 performance is
dependent on dual tone frequencies, signal input levels, and the
ADC clock rate.
ADC DATA OUTPUT
1/f NOISE
THERMAL NOISE
QUANTIZATION
NOISE
ADC NOISE
Harmonic Distortion (HD2, HD3 and SFDR)
A harmonic tone that falls within the IF band of interest when a
single tone is swept across the user defined frequency range.
fs/64
fs/16
fs/2
Signal Transfer Function (STF)
BAND OF
INTEREST
STF is the frequency response of the ADC output signal relative
to a swept single tone at the ADC input. The Typical
Performance Characteristics section shows the STF over the IF
pass-band to highlight pass-band flatness. The STF also affects
aliasing of undesired signal near fS.
Figure 54. Noise Regions of a Σ-Δ ADC
Rev. 0 | Page 27 of 93
AD9083
Data Sheet
THEORY OF OPERATION
Flicker noise may be higher for this architecture, lending itself
to better performance for IF applications instead of zero IF.
Similarly, input referred offset has no effect on an IF application,
except when using the full dynamic range of the signal
converter. A low power mode is available with a noise density
increase of 3 dB for half the converter power.
ADC ARCHITECTURE
The AD9083 is a 16-channel, highly integrated and programmable
front-end digitizer for a wide range of applications.
The AD9083 ADC uses a first-order, CTSD modulator
architecture that provides first-order quantization noise shaping
and inherent first-order, sinc shaped, antialias filtering. This
oversampling, combined with the inherent antialias filtering,
eliminates thermal noise folding into the band of interest. This
feature enables a fast signal settling time when compared to the
settling time of Nyquist rate converters, which require highly
selective antialias filters to eliminate noise folding. The first-
order Σ-Δ modulator is superior to a higher order modulator
because the former requires only a second-order CIC decimation
filter to eliminate quantization noise before decimation. This
low order decimation filter features better signal settling time
compared to a higher order filter. Built into the ADC front end
is a programmable termination resistor, programmable gain
adjust, and a programmable, single-pole, low-pass filter (LPF).
The ADC in the AD9083 must be initialized and set up based
on the particular use case. Figure 55 shows the block diagram of
the ADC used in the AD9083. The ADC in the AD9083
requires a set of user-defined variables that set up the ADC in
the use case specified by the application. These variables are as
follows:
•
fS, the sample clock of the converter core (1.0 GSPS to
2.0 GSPS).
•
VMAX, the differential peak-to-peak input full scale
(0.5 V p-p, differential, to 2.0 V p-p, differential).
fC, the cutoff frequency of the LPF (125 MHz to 800 MHz).
•
•
•
•
RTERM, the differential input termination resistance.
f
INMAX, the maximum input signal frequency.
Background calibration digitally calibrates signal path gain
error and nonlinearity. The ADC noise density is shaped, not
flat, and is better at lower bandwidths. The worst case ADC
noise density at a 2 GHz sample rate and 100 MHz offset is
−147 dBFS/Hz. For a 2 GSPS sample rate and at 100 MHz
bandwidth, the input referred noise figure is only 0.1 dB with
40 dB of front-end gain.
Backoff, the reduction in front-end gain for increased
linearity.
•
EN_HP, which increases the SNR by 2.5 dB by doubling
the ADC power dissipation.
fC = 125MHz TO 800MHz
VINx+
R/2
R/2
x = 1 TO 16
C
16
Σ-Δ
MODULATOR
R
TERM
VINx–
R/2
R/2
x = 1 TO 16
VMAX
C
fS
Figure 55. AD9083 ADC Block Diagram
Rev. 0 | Page 28 of 93
Data Sheet
AD9083
LOW-PASS, CTSD ADC OVERVIEW
LOW-PASS Σ-Δ ADC
The AD9083 uses a voltage control oscillator (VCO)-based
CTSD modulator ADC to convert the analog input to a digital
word. The digital word can then be processed by a digital backend
that provides decimation filtering, rate adjustment, DDC
frequency shifting, and FIR filtering. The ADC samples at a
rate (fS) between 1 GSPS and 2 GSPS. The typical maximum
oversampling ratio (OSR) is 8 for a usable bandwidth up to fS/16.
Figure 56 shows a simplified, single-ended representation of the
low power Σ-Δ ADC modulator. The ADC is a first-order, single-
stage modulator. The NTF is first order. Therefore, a relatively
high OSR is required to reduce noise in the signal band of
interest. For a more detailed description of the modulator,
see IEEE JSSC 2010 and IEEE JSSC 2013.
SIGNAL CONVERTER
5
5
OVER-
RANGE
CORR
8
8
NON-
15
15
10x3 – ELEMENT
ICRO
RING
PHASE
–1
–1
1–z
1–z
LINEARITY
CORRECTION
SAMPLER
DECODER
v(t)
V/I
OVER-
RANGE
CORR
NON-
LINEARITY
CORRECTION
16
10x3 – ELEMENT
ICRO
RING
SAMPLER
PHASE
DECODER
–
fS
CALIBRATION UNIT
Figure 56. Simplified, Single-Ended, Low Power, Σ-Δ ADC Modulator
Rev. 0 | Page 29 of 93
AD9083
Data Sheet
At signal frequencies below fS/64, the dominant noise source is
white thermal noise. Above this frequency, the noise is dominated
by shaped quantization noise rising at 6 dB/octave. At the
maximum signal bandwidth of fS/16, quantization noise is the
dominant noise source (see Figure 54). The ac performance
tables give measurements of the NSD at various frequencies
and ADC settings.
Differential Input Considerations
The AD9083 ADC uses a first-order, CTSD modulator
architecture that provides first-order quantization noise
shaping and inherent first-order, sinc shaped, antialias filtering.
This oversampling, combined with the inherent antialias
filtering, eliminates thermal noise folding into the band of
interest. Therefore, there is no need for an antialiasing filter in
the front end. The inputs can be differentially coupled using a
balun/transformer or an amplifier. The inputs can also be
ac- or dc-coupled. Moreover, the AD9083 inputs are resistively
terminated, which makes it easier for amplifiers to drive the
AD9083 analog inputs. Figure 58, Figure 59, Figure 60, and
Figure 61 show some commonly applicable ways to provide an
input to the AD9083.
DESIRED
INPUT
fS/64 fS/16
fS/2
BAND OF
INTEREST
SIGNAL
AD9083
INPUT
R
= 100Ω
TERM
CTSD
1:2
Figure 57. Noise Shaping Characterisctic of a Σ-Δ ADC
Figure 58. AC-Coupled Inputs to the AD9083 Using a Transformer
A digital decimation filter that follows the modulator removes
the large out-of-band quantization noise (see Figure 57) while
also reducing the data rate.
SIGNAL
AD9083
INPUT
V
R
= 100Ω
ANALOG INPUTS
CM
TERM
The analog input to the AD9083 is a differential buffer. The
internal common-mode voltage of the buffer is 1.1 V when
ac coupling. When dc coupling, the allowable level is 0.5 V
to 1.0 V. The nominal VMAX level of the ADC is 1.8 V p-p,
differential. This VMAX level is programmable from 0.5 V p-p
to 2.0 V p-p.
1:2
Figure 59. DC-Coupled Inputs to the AD9083 Using a Transformer (Note the
Center Tap Connection Providing the Common-Mode Voltage)
AD9083
SIGNAL
INPUT
R
= 100Ω
TERM
OR 200Ω OR
OPEN
The inputs of the AD9083 are terminated using a programmable
differential resistor. This differential resistor can be programmed
to 100 Ω, 200 Ω, or can be left open. Following the termination
resistor is a programmable single-pole, LPF. The maximum
signal bandwidth of the AD9083 is 125 MHz (fS/16) for a 2 GHz
ADC fS. The fC of the LPF can be programmed to be between 125
MHz to 800 MHz to reduce input noise to the ADC. In particular,
this noise includes unwanted signals near fS that can alias down
to the band of interest.
Figure 60. AC-Coupled Inputs to the AD9083 Using an Amplifier
AD9083
SIGNAL
INPUT
R
= 100Ω
TERM
OR 200Ω OR
OPEN
V
OCM
For applications where unwanted signals are not present,
increasing the cutoff frequency of this filter improves the signal
flatness out to the required signal bandwidth of the ADC. For
best ADC noise performance, place the IF below fS/20, where fS
is the ADC sample rate.
Figure 61. DC-Coupled Inputs to the AD9083 Using an Amplifier (Note the
VOCM Pin Providing the Common-Mode Voltage)
Rev. 0 | Page 30 of 93
Data Sheet
AD9083
1.1V
Σ-Δ Analog Input Considerations
A discrete time ADC aliases signals around the sample clock
frequency and the corresponding multiples to the band of
interest (see Figure 62). Therefore, an external antialias filter is
needed to reject these signals.
R
IN
V
+ VIN
– VIN
CM
(1.1V – V )/R
CM
IN
V
UNDESIRED
CM
R
DESIRED
INPUT
SIGNAL
IN
1.1V
Figure 64. Input Stage of the AD9083 Showing the Common Mode Voltage
Generation
fS
fS/2
The AD9083 can also be configured for ac-coupled applications.
In this case, the output of the ac-coupling capacitor is biased to
1.1 V by the input circuit (see Figure 65).
ADC
Figure 62. Aliasing in a Discrete Time ADC
R
IN
IN
V
V
+ VIN
– VIN
CM
In contrast, the CTSD modulator used in the AD9083 has
some inherent antialiasing that lessens the antialias filtering
requirements. The antialiasing property results from the signal
processing inherent to the ADC architecture. The intrinsic STF of
the ADC is that of a first-order sinc filter.
CM
R
1.1V
1.1V
Figure 65. AC-Coupled Application Using the AD9083
Setting the device so that VCM = 0.7 V is recommended for
optimum performance. However, the device can function over a
wider range with reasonable performance.
Additionally, a single-pole, first-order, programmable LPF is
integrated in front of the ADC. This filter is SPI programmable
between the 125 MHz to 800 MHz bandwidth.
Input Termination
The STF + LPF filtering at the front end reduces aliasing of
undesired signals near the sample rate, fS (see Figure 63).
A differential input termination can be enabled via the SPI
register. This termination value can be either 100 Ω, 200 Ω, or
high impedance. On-chip foreground calibration is performed
after startup to reduce the device to device variation of resistor
and capacitor values due to tolerances associated with the
device process. This calibration improves the termination value
tolerances, as well as the LPF tolerances discussed previously
UNDESIRED
STF + LPF
SIGNAL
DESIRED
INPUT
fS
fS/2
CTSD
R
IN
Figure 63. Alias Rejection of Σ-Δ ADC
R
TERM
Input Common Mode
R
IN
The analog inputs of the AD9083 are programmable resistors
internally dc biased to 1.1 V. The device typically expects a
common-mode input of 0.5 V to 1.0 V with a nominal voltage
of 0.7 V. An internal reference loop automatically senses the
input common mode and sources a current across the input
resistor network to generate the appropriate common-mode
level shift across each RIN (see Figure 64). The circuit driving
the AD9083 must be able to sink this common-mode current.
To set the value of the current use the following equation:
Figure 66. Programmable Input Termination of the AD9083
Input Signal Overload
Unlike a traditional CTSD ADC, the AD9083 ADC saturates
much like a flash converter. The ADC does not become unstable
(as with a traditional CTSD ADC), and the recovery time is one
clock cycle.
I
SINK = (1.1 V − VCM)/(RIN)
Rev. 0 | Page 31 of 93
AD9083
Data Sheet
–85
–90
CLOCK INPUTS
INTEGRATED JITTER = 148.2fS rms
–95
The AD9083 ADC sample clock is generated by using the
on-chip, integrated, integer PLL VCO by providing a reference
clock signal to the CLK differential inputs (Pin K3 and
Pin J3). Clock multiplying employs the on-chip ADC PLL that
accepts a reference clock operating at a submultiple of the
desired ADC sample rate. The operating range of the clock
multiplier reference input is 50 MHz to 500 MHz. The PLL
then multiplies the reference clock up to the desired ADC
sample clock frequency, which generates all the clocks within
the AD9083. The block diagram of the on-chip PLL is shown in
Figure 68.
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
1k
10k
100k
1M
10M
The AD9083 contains a low jitter, differential clock receiver
that is capable of interfacing directly to a differential clock
source. The input is self biased with a nominal impedance of
100 Ω. It is recommended that the clock source be ac-coupled
to the CLK input pins. Improved phase noise performance
can be achieved with a higher clock input level. The quality of
the clock source, as well as its interface to the AD9083 clock
input, directly impacts ac performance. Select the phase noise
and spur characteristics of the clock source to meet the target
application requirements. The typical phase noise performance
of the on-chip PLL when clocking the AD9083 at a 2 GHz
sample rate is shown in Figure 67.
FREQUENCY (Hz)
Figure 67. AD9083 On-Chip PLL Phase Noise vs. Frequency Offset, 2 GHz ADC
Sample Rate, On-Chip DDC Enabled
For optimal performance of the on-chip PLL, connect a low
ESR, low ESL, X7R dielectric, 2.2 µF capacitor between the
REG_VCO pin and GND. Additionally, connect a C0G or NP0
dielectric, 33 nF capacitor between the VCOARSE_VCO pin
and GND. Place these capacitors as close to the AD9083 chip as
possible to avoid any external noise coupling.
33nF
2.2µF
PCB
VCOARSE VCO
REG VCO
CHIP
PCB
CHIP
REGULATOR
AVDD1P8
CLK+
30Ω
30Ω
172kΩ
ADC_CLK
1GHz TO 2GHz
÷R
PFD
÷N
FILTER
÷D
V
100Ω
CM
172kΩ
8.8GHz TO 12.4GHz
CLK–
÷P
OUTPUT
DIVIDER
CONTROL
V
CM
CAL
Figure 68. AD9083 Clock Path Block Diagram
Rev. 0 | Page 32 of 93
Data Sheet
AD9083
POWER MODES
DIGITAL SIGNAL PROCESSING OVERVIEW
The AD9083 features low power modes that enable powering
down certain blocks of the AD9083, or the entire chip, based on
trade-offs between power saving achieved and wake-up time to full
power on. These sections discuss the power-down modes available
within the AD9083. All modes are controlled via the SPI.
The CTSD ADC includes a digital processing block between the
CTSD ADC output and the JESD204 transmitter core. The
digital signal processing block can filter and translate IF to zero
IF signals suitable for post processing by the host without any
loss of dynamic range. This block includes a programmable
CIC decimation filter, a mixer with NCO, and a highly
programmable, multistage decimation FIR filter. Figure 70
shows a simplified diagram of the digital functional block. For
clarity, Figure 70 does not show the digital datapath routing
options, which are described in the Signal Processing Tile
section.
Full Power-Down Mode
In full power-down mode, almost all of the blocks within the
AD9083 are held in low power mode, resulting in the highest
power saving. However, this power saving results in slow wake-
up times. The ADC internal reference, on-chip clock PLL, and
the JESD204B PLL are powered on. On release of this mode, the
ADC must undergo recalibration. The on-chip clock PLL and
the JESD204B PLL must undergo relocking to achieve normal
performance.
CIC
DDC
FIR
LOW-PASS
CTSD
Nx
Mx
NCO
Standby Mode
Figure 70. Simplified Diagram of the Digital Functional Block
In standby mode, some of the blocks are kept running while
others are held in a clock gated mode, resulting in medium
power saving, but faster wake-up time compared to full power-
down mode. The ADC cores, on-chip clock PLL, JESD204B
PLL, and digital outputs are kept powered on. The digital and
JESD204B framer blocks are clock gated. The JESD204B link
must be reinitialized on release of this mode.
The CTSD ADC provides a highly oversampled digital output
representing the desired IF signal pass band and the out-of-
band shaped noise. Figure 71 shows the spectrum of the raw
ADC output.
ADC DATA OUTPUT
DESIRED
INPUT
Power-On Mode
fIN
Power-on mode is the normal operation mode for the AD9083.
All blocks within the AD9083 are powered up and running at
rated frequency. However, to further reduce power during
normal operation, digital portions that do not need to be
running can be selectively clock gated. For example, if the
application only requires one numerically controlled oscillator
(NCO)/mixer, the other two NCOs/mixers can be disabled. The
same principle applies to the JESD204B lanes. The unused lanes
can be powered down.
ADC NOISE
fS/64 fS/16
fS/2
BAND OF
INTEREST
Figure 71. Spectrum of the Raw ADC Output
The digital signal path first filters and decimates the ADC
output data by Nx. It is necessary to remove the majority of the
out of band quantization noise before any clock rate reduction
or frequency translation. Figure 72 shows the decimator output
frequency spectrum.
TEMPERATURE DIODE
The AD9083 contains diode-based temperature sensors. The
output voltages of these diodes correspond to the temperature
of the silicon. There is a pair of diodes, one of which is 20× the
size of the other. It is recommended to use both diodes to
obtain an accurate estimate of the die temperature. For more
information, see the AN-1432 Application Note, Practical
Thermal Modeling and Measurements in High Power ICs. The
temperature diode voltages can be exported to the TD pin using
the SPI (see Figure 69).
DECIMATED DATA OUTPUT
fIN
fS/64
fS/16
fS/2N
Figure 72. Frequency Spectrum of the Decimator Output
AVDD1P8
Next, the DDC can be enabled to perform a frequency
translation. Typically, this frequency translation is from a
middle IF down to zero IF or very low IF. Figure 73 shows a
representative of the output spectrum of the DDC output.
1x DIODE
VOLTAGE
TD
TEMPERATURE
DIODE
ENABLE
20x DIODE
VOLTAGE
TEMPERATURE
DIODE SELECT
GND GND
GND
Figure 69. TD Pin Using the SPI
Rev. 0 | Page 33 of 93
AD9083
Data Sheet
DDC DATA OUTPUT
The following equation shows the quantization noise density
for truncation errors:
NSDTRUNCATION = 20log10(2BITS) + 10log10(BWBASEBAND
)
fIN – fNCO
For example, with 12-bit JESD204B data and a 2 MHz baseband
bandwidth, the truncation error NSD is only −135 dBFS, which is
well above the ADC noise floor. In this narrow-band example,
16 bits are required to reduce the truncation error to −159 dBFS,
which is well below the ADC noise level under all IF conditions.
fS/2N
Figure 73. Output Spectrum of the DDC Output
OUTPUT DATA
Finally, the FIR can filter and downsample the baseband signal
to a much lower data rate suitable for transfer via the JESD204B
interface. Figure 74 shows a representative of the output
spectrum of the FIR filter output of a baseband signal.
fIN
–
fNCO
ADC NOISE
TRUNCATION
NOISE
DDC DATA OUTPUT
fS/2(N + M)
fIN – fNCO
Figure 75. Example Showing ADC Noise Unaffected by Truncation Error
Truncation error that is well above the ADC noise floor may not
only add to the noise floor but may also add spurious content
when the truncation noise is correlated with the input signal.
OUTPUT DATA
fS/2(N + M)
Figure 74. Output Spectrum of the FIR Filter Output of a Baseband Signal
fIN – fNCO
TRUNCATION SPUR
TRUNCATION NOISE
> ADC NOISE
Care must be taken when selecting the JESD204B output data
format. Both 12- and 16-bit data modes are available, and the
user must be careful to select a word length that does not add
significant truncation noise to the baseband signal. Very
narrow-band baseband applications may see high SNR values
in the FIR output data. In all cases, the truncation noise density
is well below the baseband NSD.
fS/2(N + M)
Figure 76. Example Showing ADC Noise Affected by Truncation Error
Rev. 0 | Page 34 of 93
Data Sheet
AD9083
SIGNAL PROCESSING TILE
Each ADC has a signal processing tile to filter out of band
shaped noise from the Σ-Δ ADC and to reduce the sample rate,
resulting in 16 total tiles (see Figure 77).
stream. To enable this operation, the converter number of bits,
N, is set to a default value of 16.
For typical high performance RF applications, the ADC can
provide either a real output for zero IF inputs, or a quadrature
output for low IF inputs. The datapath through the signal
processing tile uses the multiple FIR decimate by J filters with
optional frequency translation using the mixer/NCO0 block.
This datapath is referred to as the nonburst mode datapath.
Each tile contains a CIC filter and a DDC with multiple FIR
decimation filters, known as the decimate by J filter block. The
decimate by J filter block can be used with or without the
quadrature mixer/NCO. For data gating applications, there are
up to three quadrature DDC channels using an averaging filter,
G, that selects and decimates the data.
For applications using stepped frequency modulation bursts
(SFCW), time must be allowed for settling. Data gating is used
to select the number valid samples (G) of the pulse burst for
averaging prior to decimation. Decimation reduces the data
samples by 1/H. This datapath is referred to as the burst mode.
In burst mode, each input channel is provided with three
quadrature DDCs. All channels are programmed the same, but
the individual DDCs and averaging FIR filters within a channel
can be configured for a different frequency.
Each processing block has control lines that allow the block to
be independently enabled and disabled to provide the desired
processing function. Multiplexers are enabled within the
processing tile to send the data appropriate to the application
use case. The register bits responsible for datapath selection by
the multiplexors are shown in Figure 67.
There are three NCOs (NCO0 to NCO2) available for the signal
processing tile, one for each mixer. NCO2 and NCO3 are only
used when the device is configured for data gating. The same
three NCOs are used for all 16 signal processing tiles.
Due to the JESD204B output line rate limitation (16 Gbps/lane)
and the number of lanes available (four), care must be taken to
ensure that the total throughput from all 16 signal processing
tiles does not exceed the maximum allowable line rate.
Therefore, not all combinations of CIC filter decimation, J
decimation, or averaging (H) decimation are supported.
The signal processing tile can be configured to output either
real data or complex output data. The output is complex when
using the mixer. The signal processing tile outputs a 16-bit
NCO
NCO
NCO
2
0
1
SIGNAL PROCESSING TILE 1 OF 16
BURST_MODE
DECI_ADC_DATA/
NO_DDC_MODE
DECIMATE
BY J
I
0
Q
0
NCO
0
AVERAGE
FILTER G
DECIMATE
BY H
GAIN
ADJUST
NCO
NCO
1
2
AVERAGE
FILTER G
DECIMATE
BY H
CIC
DECIMATOR
BY N
CIC OUTPUT
DATA AT fS/N
I
Q
1
ADC OUTPUT
DATA AT fS
1
2
GAIN
ADJUST
AVERAGE
FILTER G
DECIMATE
BY H
I
Q
2
GAIN
ADJUST
Figure 77. Signal Processing Tile Following Each ADC Channel (1 of 16)
Rev. 0 | Page 35 of 93
AD9083
Data Sheet
Adjust the CIC droop with a programmable gain adjustment.
For each sample frequency, the tones are at different frequency
values and the value of droop correction required is different.
Figure 79 shows the droop characteristics to a finer detail.
CASCADED INTEGRATOR COMB (CIC) FILTER
Data from each ADC is sent to the CIC filter. The CIC filter can
be bypassed, and the ADC data sent to the DDCs to decimate
the data. This is enabled by writing a 1 to the DECI_ADC_
DATA bit (Bit DB4) in the DP_CTRL register. In this mode,
the mixer is bypassed. Therefore, there is no frequency shifting
available.
0
16× DECIMATION
8× DECIMATION
4× DECIMATION
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
The frequency response of the CIC filter built in to the AD9083
is identical to that of a second-order moving average filter of
Length N, where N is the decimation rate. The decimation rates
allowed are 4×, 8×, or 16×, based on the setting. The output of
the CIC filter is a single 16-bit data sample at a rate of fS/N
where fS is the ADC sample rate and N is the CIC decimation
ratio setting.
The response of the CIC filter under different decimation
settings is shown in Figure 78. The response is normalized to
the ADC sample frequency (fS). This normalization helps the
end user with frequency planning. For example, if the ADC fS is
2 GSPS, a fundamental frequency placed at 100 MHz incurs CIC
losses of 1.09 dB, 4.77 dB, and 25.17 dB for CIC decimation ratios
of 4×, 8×, and 16×, respectively. Therefore, for this application
use case, it is best to select a CIC decimation ratio of 4× and
rely on the DDC decimation to further decimate the data.
0
0.015 0.030 0.045 0.060 0.075 0.090 0.105 0.120 0.135 0.150
NORMALIZED FREQUENCY (×fS
)
Figure 79. Zoomed in Image of the CIC Filter Response Shown in Figure 78;
Normalized to fS
The AD9083 digital datapath has a block that can be used to
program the gain to compensate for the droop. Based on the
application and the input frequency, the user can program the
appropriate gain to compensate for the loss through the CIC
filter. The gain setting to compensate for the loss is calculated
as follows
0
16× DECIMATION
8× DECIMATION
4× DECIMATION
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Fractional Bit Calculation ≥ frac(10(−Droop/20)) × 210
For example, if the input frequency is 25 MHz, Table 18 shows
the gain setting needed to compensate for the droop for the
various CIC decimation ratios for various frequencies. As
shown in Figure 79, the CIC roll-off must be considered when
designing the AD9083 in a system. As a general rule, keep the
IF to within 20% of the output data rate. For example, if the
highest frequency in the system is 100 MHz, then a CIC
decimation of 4× is recommended. Conversely, if a CIC
decimation of 16× is chosen, keep the IF below 25 MHz.
0
0.05
0.10
0.15
0.20
0.25
NORMALIZED FREQUENCY (×fS
)
The CIC gain is programmed as an unsigned 4.10 word. The
first four bits represent the integer portion of the gain, and the
following 10 bits represent the fraction portion of the gain.
Figure 78. CIC Filter Response for Decimation Ratio = 4×, 8×, and 16×;
Normalized to fS
Table 18. Example Gain Compensation Settings for various CIC filter Roll-Off Values; fS = 2 GHz
4× Decimation
8× Decimation
Frequency
(MHz)
CIC Droop (dB)
−0.0669177
−0.2687053
Gain Compensation (Unsigned 4.10)
0001_00_0000_1000
0001_00_0010_0000
CIC Droop (dB)
−0.28
−1.14
Gain Compensation (Unsigned 4.10)
0001_00_0010_0010
0001_00_1001_0000
25
50
Rev. 0 | Page 36 of 93
Data Sheet
AD9083
•
•
The NO_DDC_MODE bit (Register 0x0116, Bit 1) of the
DP_CTRL register bypasses the NCO/mixer where
frequency translation is not required.
The BURST_MODE bit (Register 0x0116, Bit 2]) of the
DP_CTRL register) selects the decimate by J filter block.
NONBURST MODE DATAPATH
Figure 80 shows the signal processing configuration in the
nonburst mode datapath. The input data can be direct from the
ADC or via the output of the CIC filter. The datapath uses
multiplexers configurable by the DP_CTRL register
(Register 0x116) to appropriately route the data. The
multiplexer control bits are shown in Figure 80.
NCO
0
SIGNAL PROCESSING TILE 1 OF 16
BURST_MODE
DECI_ADC_DATA/
NO_DDC_MODE
DECIMATE
BY J
ADC OUTPUT
DATA AT fS
I
Q
GAIN
ADJUST
CIC OUTPUT
DATA AT fS/N
DDC OUTPUT DATA
AT fS/(N × J);
J = 1 IF DDC BYPASSED
NCO
0
Figure 80. Nonburst Mode Datapath Within the Signal Processing Tile Following Each ADC Channel (1 of 16)
Rev. 0 | Page 37 of 93
AD9083
Data Sheet
The decimate by J block supports decimation ratios of 1, 4, 8, 10,
12, 16, 20, 24, 30, 40, and 60, as shown in Table 19.
Decimate by J Filters
After the frequency translation stage, there are multiple
decimation filter stages that reduce the output data rate. After
the carrier of interest is tuned down to dc (carrier frequency =
0 Hz), these filters efficiently lower the sample rate, while
providing sufficient alias rejection from unwanted adjacent
carriers around the bandwidth of interest.
Decimation rates of 1, 4, 10, and 30 are valid only when CIC is
not bypassed (for example, DECI_ADC_DATA is equal to 0).
Figure 81 shows the detailed block diagram of the Decimate by
J filters.
Table 12 describes the filter characteristics of the different FIR filter
blocks.
When the decimate by J block is supplied with direct data from
the ADC, there is no mixing option. Only decimation occurs.
The valid J decimation options are determined by the path
before the decimate by J block. Table 19 lists the available J
decimation options determined by the input data path.
Table 21 shows the different filter configurations selectable by
including different filters. In all cases, the decimate by J filtering
stage provides 81.4% of the available output bandwidth,
< 0.005 dB of pass-band ripple, and >100 dB of stop band alias
rejection. Table 22 shows the coefficients for the various finite
impulse response (FIR) filters used in the AD9083.
HB3
HB2
HB1
PB2
FROM MIXER/CIC
HB4
DIRECT FROM ADC
TB3
Figure 81. Decimate by J Filters Block Diagram
Table 19. J Decimation Rate
CIC Filter and NCO0/Mixer Bypassed
(DECI_ADC_DATA = 1 and
NO_DDC_MODE = 1)
CIC Filter Enabled and NCO0/Mixer
Bypassed (DECI_ADC_DATA = 0 and
NO_DDC_MODE = 1)
CIC Filter and NCO0/Mixer Enabled
(DECI_ADC_DATA = 0 and
NO_DDC_MODE = 0)
Invalid
Invalid
8
1 (bypass mode)
4
8
1 (bypass mode)
4
8
Invalid
12
16
20
24
40
Invalid
60
10
12
16
20
24
40
30
60
Invalid
Invalid
16
Invalid
Invalid
Invalid
Invalid
Invalid
Table 20. Decimation Filter Characteristics
Pass Band
Filter Name
Decimation Ratio
(rad/sec)
0.1 × π/2
0.2 × π/2
0.4 × π/2
0.8 × π/2
0.3 × π/3
0.4 × π/5
Stop Band (rad/sec)
π/2 × 1.9
π/2 × 1.8
π/2 × 1.6
π/2 × 1.2
Pass-Band Ripple (dB)
Stop Band Rejection (dB)
HB4
HB3
HB2
HB1
TB3
PB2
2
2
2
2
3
5
< 0.001
< 0.001
< 0.001
< 0.001
< 0.001
< 0.001
>100
>100
>100
>100
>100
>100
π/3 × 1.8
π/5 × 1.6
Rev. 0 | Page 38 of 93
Data Sheet
AD9083
Table 21. DDC Filter Configurations
DDC Input Sample Rate1
DDC Filter Configuration
Decimation Ratio
Output Bandwidth
−fIN to +fIN
fIN
Not applicable
1
HB1 + HB2
HB1 + HB2 + HB3
HB1 + PB2
HB1 + HB2 + TB3
HB1 + HB2 + HB3 + HB4
HB1 + PB2 + HB3
HB1 + HB2 + TB3 + HB4
HB1 + PB2 + TB3
HB1 + PB2 + HB3 + HB4
HB1 + PB2 + TB3 + HB4
4
8
0.814 × (−fIN/4 to +fIN/4)
0.814 × (−fIN/8 to +fIN/8)
10
12
16
20
24
30
40
60
0.814 × (−fIN/10 to +fIN/10)
0.814 × (−fIN/12 to +fIN/12)
0.814 × (−fIN/16 to +fIN/16)
0.814 × (−fIN/20 to +fIN/20)
0.814 × (−fIN/24 to +fIN/24)
0.814 × (−fIN/30 to +fIN/30)
0.814 × (−fIN/40 to +fIN/40)
0.814 × (−fIN/60 to +fIN/60)
1 fIN = fS/CIC_DEC_RATIO, where fS is the ADC sample rate.
Table 22. DDC Filter Coefficients for Various FIR Filters in the AD9083
Coefficient
Number
HB1
HB2
HB3
HB4
TB3
PB2
1
2
3
4
5
6
7
8
21'h1FFFF4
21'h00000
21'h00002C
21'h00000
21'h1FFF8C
21'h00000
21'h000102
21'h00000
21'h1FFDFC
21'h00000
21'h0003B4
21'h00000
21'h1FF9A0
21'h00000
21'h000A6E
21'h00000
21'h1FEFA7
21'h00000
21'h0018C0
21'h00000
21'h1FDB90
21'h00000
21'h003492
21'h00000
21'h1FB50C
21'h00000
21'h006AD4
21'h00000
21'h1F64EC
21'h00000
21'h00ED96
21'h00000
21'h1E5BAE
21'h00000
21'h0512F9
19'h000B4
19'h00000
19'h7FA7E
19'h00000
19'h01766
19'h00000
19'h7B3EB
19'h00000
19'h1397E
19'h20000
19'h1397E
19'h00000
19'h7B3EB
19'h00000
19'h01766
19'h00000
19'h7FA7E
19'h00000
19'h000B4
17'h1FF91
17'h00000
17'h0039C
17'h00000
17'h1EFC4
17'h00000
17'h04D0F
17'h08000
17'h04D0F
17'h00000
17'h1EFC4
17'h00000
17'h0039C
17'h00000
17'h1FF91
19'h006D2
19'h00000
19'h7CBA8
19'h00000
19'h12D86
19'h20000
19'h12D86
19'h00000
19'h7CBA8
19'h00000
19'h006D2
17'h00000
17'h00000
17'h1FFE4
17'h1FFA8
17'h00000
17'h001F8
17'h003F0
17'h00000
17'h1F352
17'h1EAB6
17'h00000
17'h03E55
17'h088D8
17'h0AAAA
17'h088D8
17'h03E55
17'h00000
17'h1EAB6
17'h1F352
17'h00000
17'h003F0
17'h001F8
17'h00000
17'h1FFA8
17'h1FFE4
17'h00000
17'h00000
20'h00000
20'hFFFF9
20'hFFFEE
20'hFFFE6
20'h00000
20'h0005A
20'h000F6
20'h0018A
20'h00178
20'h00000
20'hFFCD0
20'hFF8B0
20'hFF5DC
20'hFF77C
20'h00000
20'h00F00
20'h01F90
20'h02894
20'h01FF2
20'h00000
20'hFCD26
20'hF98A4
20'hF7DEE
20'hF9A1E
20'h00000
20'h0AD60
20'h186CA
20'h25CC0
20'h2F99B
20'h33330
20'h2F99B
20'h25CC0
20'h186CA
20'h0AD60
20'h00000
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Rev. 0 | Page 39 of 93
AD9083
Data Sheet
Coefficient
Number
HB1
HB2
HB3
HB4
TB3
PB2
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
21'h080000
21'h0512F9
21'h00000
21'h1E5BAE
21'h00000
21'h00ED96
21'h00000
21'h1F64EC
21'h00000
21'h006AD4
21'h00000
21'h1FB50C
21'h00000
21'h003492
21'h00000
21'h1FDB90
21'h00000
21'h0018C0
21'h00000
21'h1FEFA7
21'h00000
21'h000A6E
21'h00000
21'h1FF9A0
21'h00000
21'h0003B4
21'h00000
21'h1FFDFC
21'h00000
21'h000102
21'h00000
21'h1FFF8C
21'h00000
21'h00002C
21'h00000
21'h1FFFF4
20'hF9A1E
20'hF7DEE
20'hF98A4
20'hFCD26
20'h00000
20'h01FF2
20'h02894
20'h01F90
20'h00F00
20'h00000
20'hFF77C
20'hFF5DC
20'hFF8B0
20'hFFCD0
20'h00000
20'h00178
20'h0018A
20'h000F6
20'h0005A
20'h00000
20'hFFFE6
20'hFFFEE
20'hFFFF9
20'h00000
Rev. 0 | Page 40 of 93
Data Sheet
AD9083
NUM_TONES bits (Bits[DB6:5]) in the DP_CTRL register
BURST MODE DATAPATH
(Register 0x116). The averaging filter uses a programmable
number of last valid samples of the pulse burst equal to G and a
programmable decimation value equal to H. The timing of the
burst is derived from either the TRIG input or the SYSREF.
Figure 82 shows the block diagram for the burst mode datapath
of one signal processing tile of the AD9083. The data from the
CIC filter can be sent to three DDCs channels simultaneously at a
rate of fS/N (N = 4, 8, 16). Each DDC has a mixer fed with a 7-bit
NCO that can be used to tune the outputs to dc. The number of
DDCs used is programmable. The NCOs can be programmed
to different frequencies, enabling frequency translations for up
to three tones. The number of tones is defined in the
In burst mode, the decimate by J filter block is bypassed. This
bypass is enabled by the BURST_MODE bit (Bit DB2) in the
DP_CTRL register.
NO_DDC
BURST
NCO
0
I
Q
AVERAGE
FILTER
DECIMATE
BY H
0
K
0fS/(N × R)
0
NCO
1
AVERAGE
FILTER
DECIMATE
BY H
K1fS/(N × R)
CIC
DECIMATOR
BY N
I
Q
1
ADC
1
2
NCO
2
AVERAGE
FILTER
DECIMATE
BY H
K
2fS/(N × R)
I
Q
2
fS = 1 – 2Gsps
fS/N
fS/(N × H)
Figure 82. Averaging Filter Example Showing the Datapath
Rev. 0 | Page 41 of 93
AD9083
Data Sheet
The supported values for G are 8 and 16. If G is 8, the
supported H values are 12, 14, 16, 18. For a G value of 16, the
supported H values are 24, 28, 32, 36.
AVERAGING FILTERS
The averaging filters are used in the burst mode datapath. In
contrast to traditional decimation filters, the averaging filters
are designed for determining the phase and amplitude of a
single continuous wave (CW) tone of a known frequency. The
filters average G samples when the data is stable within every H
window.
Averaging Filter Example
In this example, the sample rate is 1.6 GSPS, N decimation = 4,
and G = 16:
•
•
•
f
f
f
NCO1 = 1 × (1.6e9 / (4 × 16)) = 25 MHz.
NCO2 = 2 × (1.6e9 / (4 × 16)) = 50 MHz.
NCO3 = 3 × (1.6e9 / (4 × 16)) = 75 MHz.
NCO
SAMPLE
CLOCK
Placing the frequencies like this is necessary to ensure that the
two unwanted frequencies are located at the filter nulls of the
selected NCO frequency and are removed. In the example
shown, NCO0 only allows the 25 MHz tone through, while
nulling out the 50 MHz and 75 MHz tones. Similarly, NCO1
only allows the 50 MHz tone through, while nulling out the
25 MHz and 75 MHz tones. See Figure 84 for the averaging filter
frequency response at each stage of the datapath.
G
H
DOWN-MIXED
DATA
SETTLING
VALID
DECIMATED
DATA
•
fS = 1.6 GSPS, CIC decimation = 8, G = 16,
H decimation = 24.
Figure 83. Averaging Filter
With the averaging filters, the user has the option to provide up to
three different CW tones. The filters in each signal processing tile
can use up to three NCOs. The three NCOs are shared by each of
the channels. For example, Channel 15 must use the same three
frequencies as Channel 2.
In each case, the input frequency being observed must be
identical to the NCO frequency, meaning that the output of the
ADC appears to be dc. By looking at the dc values of the I and
Q outputs, the phase and amplitude of the original CW tone
can be determined.
When using the burst mode datapath along with multiple CW
tones, the frequencies of the tones (fK) must be calculated per
the following equation:
fS
fK = K ×
N × G
where:
fS is the sample frequency.
N is the CIC N decimation.
G is the G value.
K = 1, 2, or 3 for Frequency 1, Frequency 2, or Frequency 3,
respectively.
Rev. 0 | Page 42 of 93
Data Sheet
AD9083
VCO ADC OUTPUT (fSADC = 1.6Gsps)
–75M –25M +25M +75M
–800M
fSADC/2
+800M
fSADC/2
–50M
+50M
–
+
CIC DECIMATOR OUTPUT (N = 4, fNCO = 400M)
–75M –25M +25M +75M
–50M +50M
–200M
fNCO/2
+200M
+fNCO/2
–
FIRST MIXER COMPLEX OUTPUT (k0 = 4, G = 16)
–100M –50M
–75M
0
+50M
+25M
–200M
fNCO/2
+200M
+fNCO/2
–
AVERAGING FILTER NULLS (k0 = 1, G = 16)
–100M –50M
–75M
0
+50M
+25M
–200M
fNCO/2
+200M
+fNCO/2
–
DATA-GATING (BY H = 24, fDATA = 16.66M)
0
–8.33M
fDATA/2
+8.33M
+fDATA/2
–
Figure 84. Averaging Filter Example Frequency Response
where:
MIXERS
NCO_FTW is the 7-bit twos complement number representing
the NCO FTW.
fC is the desired carrier frequency.
For nonburst mode RF applications, DDC0 using NCO0/mixer
for frequency translation can be selected. In applications where
real data outputs are required, the mixer can be bypassed.
f
IN is the input frequency to the DDC.
For data gating applications using burst mode, there are three
mixers available. These mixers are supplied by NCOs that can be
set to three different frequencies, enabling multiple frequency
translations (see the Averaging Filters section).
fS
fIN
=
CIC _ DEC _ RATIO
where CIC_DEC_RATIO is the CIC decimation ratio and can
be 1, 4, 8, or 16.
NCO FTW DESCRIPTION
mod(x) is a remainder function. For example mod(110,100) =
10 and for negative numbers, mod(−32,10) = −2.
There are three identical NCOs in the AD9083: NCO0 to NCO2.
Each NCO enables the frequency translation process by
creating a complex exponential frequency (e-jωt), which can be
mixed with the input spectrum to translate the desired
frequency band of interest to dc, where it can be filtered by the
subsequent LPF blocks to prevent aliasing. The NCO frequency
tuning word (FTW) is 7-bits wide. The NCO output is 12-bits.
All 16 signal processing tiles use the outputs from the same
three NCOs (NCO0 to NCO2).
floor(x) is defined as the largest integer less than or equal to x.
For example, floor(3.6) = 3.
Example FTW Calculation
In this example, the ADC sample rate (fS) is 2 GHz.
CIC_DEC_RATIO is set to 4. The desired fC is 100 MHz.
Plugging in the following values to the equation above yields an
NCO_FTW value of 26.
The NCO FTW can be calculated by the following equation:
mod( fC , fIN
)
NCO_ FTW = floor 27
fIN
Rev. 0 | Page 43 of 93
AD9083
Data Sheet
designer be aware of this phenomenon and adjust the
fC Calculation from FTW
frequency plan of the logic device. One way to increase this
resolution is to increase the CIC decimation ratio. In the
previous example, if the CIC decimation ratio is increased to 8
(instead of 4), the NCO_FTW results in a value of 51, which
calculates to 99.6094 MHz. This frequency only varies from the
actual requested frequency of 100 MHz by ~0.4%. However,
choosing this frequency plan results in an increased CIC filter
droop, as shown in Figure 78. Therefore, care must be taken to
choose the appropriate ADC sample rates, CIC decimation
ratio, and the NCO frequency tuning word.
The actual fC from the example above can be calculated as
follows:
NCO _ FTW × fIN
Actual _ fC =
27
For the example listed above, the actual tuning frequency is
2 GHz
26×
4
Actual _ fC
=
= 101.5625 MHz
27
The example in this section shows that, even though the
requested frequency is 100 MHz, the actual tuning frequency is
about 1.5% off the actual value. It is important that the system
Rev. 0 | Page 44 of 93
Data Sheet
AD9083
DIGITAL OUTPUTS
The AD9083 digital outputs are designed to the JEDEC standard
JESD204B, serial interface for data converters. JESD204B is a
protocol to link the AD9083 to a digital processing device over
a serial interface with lane rates of up to 16 Gbps. The benefits
of the JESD204B interface over LVDS include a reduction in
required board area for data interface routing, and an ability to
enable smaller packages for converter and logic devices.
•
•
•
•
K is the number of frames per multiframe
(AD9083 value = 8, 16, or 32 )
S is the samples transmitted/single converter/frame cycle
(AD9083 value = set automatically based on L, M, F, and N΄)
HD is the high density mode (AD9083 = set automatically
based on L, M, F, and N΄)
CF is the number of control words/frame clock
cycle/converter device (AD9083 value = 0)
JESD204B OVERVIEW
The JESD204B data transmit block assembles the parallel data
from the ADC into frames and uses 8-bit/10-bit encoding as
well as optional scrambling to form serial output data. Lane
synchronization is supported through the use of special control
characters during the initial establishment of the link. Additional
control characters are embedded in the data stream to maintain
synchronization thereafter. A JESD204B receiver is required to
complete the serial link. For additional details on the JESD204B
interface, refer to the JESD204B standard.
Figure 85 shows a simplified block diagram of the AD9083
JESD204B link. The AD9083 can be configured to use
sixteen converters and four lanes. Data from all sixteen
converters is output to SERDOUT0 , SERDOUT1 ,
SERDOUT2 and SERDOUT3 . The AD9083 allows other
configurations, such as combining the outputs of all converters
onto a single lane. These modes are customizable, and can be
set up via the SPI.
In the AD9083, if N’ = 16, the N-bit converter word from each
converter is broken into two octets (eight bits of data). Bit N − 1
(MSB) through Bit N-8 are in the first octet. The second octet
contains Bit N − 9 through Bit 0 (LSB), CS control bits (the CS
parameter defines the number of control bits), and tail bits, if
necessary, are appended to the LSB’s to achieve N’ number of
bits in the JESD word. If tail bits are needed, they can be
configured as zeros or a pseudorandom number sequence.
Control bits can be used to indicate overrange, SYSREF , or
fast detect output.
The AD9083 JESD204B data transmit block maps up to sixteen
physical ADCs or up to 96 virtual converters (when all the
DDCs are enabled) over a link. A link can be configured to use
one, two, or four JESD204B lanes. The JESD204B specification
refers to a number of parameters to define the link, and these
parameters must match between the JESD204B transmitter (the
AD9083 output) and the JESD204B receiver (the logic device
input).
The JESD204B link is described according to the following
parameters:
For modes where N’ = 12, each of the M/L samples on a lane
are concatenated starting with sample 0 on lane 0 to create the
F octets in each lane. If control bits are required, then N must
equal N’ – CS.
•
•
•
•
L is the number of lanes per converter device (lanes per
link); (AD9083 value = 1, 2, 3, or 4)
M is the number of converters per converter device
(virtual converters per link) (AD9083 value = 16, 32, 96)
F is the octets/frame (AD9083 value = 2, 3, 4, 6, 8, 12, 16,
24, 32, 48, 64, 72 or 96)
The resulting octets can be scrambled. Scrambling is optional;
however, it is recommended to avoid spectral peaks when
transmitting similar digital data patterns. The scrambler uses a
self-synchronizing, polynomial-based algorithm defined by the
N΄ is the number of bits per sample (JESD204B word size)
(AD9083 value = 12 or 16)
14 + x15. The descrambler in the receiver is a self-
equation 1 + x
synchronizing version of the scrambler polynomial.
•
•
N is the converter resolution
CS is the number of control bits/sample
(AD9083 value = 0, 1, 2, or 3)
The octets are then encoded with an 8-bit/10-bit encoder. The
8-bit/10-bit encoder works by taking eight bits of data (an
octet) and encoding them into a 10-bit symbol.
INPUT 1
ADC 1
SERDOUT0±
DSP BLOCK/
FORMAT
JESD204B
LINK
CONTROL
LANE MUX
AND
MAPPING
SERDOUT1±
SERDOUT2±
SERDOUT3±
INPUT 15
ADC 15
SYSREF±
SYNCINB±
Figure 85. Transmit Link Simplified Block Diagram
Rev. 0 | Page 45 of 93
AD9083
Data Sheet
TRANSPORT
LAYER
DATA LINK
LAYER
PHYSICAL
LAYER
PROCESSED
SAMPLES
FROM ADC
ALIGNMENT
CHARACTER
GENERATION
SAMPLE
FRAME
8-BIT/10-BIT
ENCODER
CROSSBAR
MUX
SCRAMBLER
SERIALIZER
Tx
OUTPUT
CONSTRUCTION CONSTRUCTION
SYSREF_x
SYNCINB_x
Figure 86. Data Flow
Physical Layer
FUNCTIONAL OVERVIEW
The physical layer consists of the high speed circuitry clocked at
the serial clock rate. In this layer, parallel data is converted into
one, two, or four lanes of high speed differential serial data. The
implementation of the Physical Layer is covered in the Physical
Layer (Driver) Outputs section.
The block diagram in Figure 86 shows the flow of data through
the JESD204B hardware from the sample input to the physical
output. The processing can be divided into layers that are
derived from the open source initiative (OSI) model, widely
used to describe the abstraction layers of communications
systems. These layers are the transport layer, data link layer,
and physical layer (serializer and output driver).
JESD204B LINK ESTABLISHMENT
The AD9083 JESD204B transmitter (Tx) interface operates in
Subclass 0 or Subclass 1 as defined in the JEDEC Standard
JESD204B (July 2011 specification). The link establishment
process is divided into the following steps: code group synchro-
nization, initial lane alignment sequence, and user data and error
correction.
Transport Layer
The transport layer handles packing the data (consisting of
samples and optional control bits) into JESD204B frames that
are mapped to 8-bit octets. The packing of samples into frames
are determined by the JESD204B configuration parameters for
number of lanes (L), number of converters (M), the number of
octets per lane per frame (F), the number of samples per
converter per frame (S), and the number of bits in a nibble
group (sometimes called the JESD204 word size − N’).
Code Group Synchronization (CGS)
CGS is the process by which the JESD204B receiver finds the
boundaries between the 10-bit symbols in the stream of data.
During the CGS phase, the JESD204B transmit block transmits
/K/ characters (/K28.5/ symbols). The receiver must locate the
/K/ characters in its input data stream using clock and data
recovery (CDR) techniques.
Samples are mapped in order starting from Converter 0, then
Converter 1, and so on until Converter M − 1. If S > 1, each
sample from the converter is mapped before mapping the
samples from the next converter. Each sample is mapped into
words formed by appending converter control bits, if enabled,
to the LSBs of each sample. The words are then padded with tail
bits, if necessary, to form nibble groups (NGs) of the appropriate
size as determined by the N’ parameter. The following equation
can be used to determine the number of tail bits within a nibble
group (JESD204B word):
The receiver issues a synchronization request by asserting the
SYNCINB pin of the AD9083 low. The JESD204B Tx then begins
sending /K/ characters. After the receiver has synchronized, it waits
for the correct reception of at least four consecutive /K/ symbols. It
then de-asserts SYNCINB . The AD9083 then transmits an ILAS
on the following local multiframe clock (LMFC) boundary.
For more information on the code group synchronization
phase, refer to the JEDEC Standard JESD204B, July 2011,
Section 5.3.3.1.
T = N΄ − N – CS
Data Link Layer
The data link layer is responsible for the low level functions
of passing data across the link. These include optionally
scrambling the data, inserting control characters during the
initial lane alignment sequence (ILAS) and for frame and
multiframe synchronization monitoring, and encoding 8-bit
octets into 10-bit symbols. The data link layer is also responsible
for sending the ILAS, which contains the link configuration
data used by the receiver to verify the settings in the transport
layer.
The SYNCINB pin operation can also be controlled by the
SPI. The SYNCINB signal is a differential dc-coupled LVDS
mode signal by default, but it can also be driven single-ended.
The SYNCINB pins can also be configured to run in CMOS
(single-ended) mode by setting Bit 0 in Register 0x447. When
running SYNCINB in CMOS mode, connect the CMOS
SYNCINB signal to Pin 21 (SYNCINB+) and leave Pin 20
(SYNCINB−) disconnected.
The implementation of the data link layer is discussed in the
JESD204B Link Establishment section.
Rev. 0 | Page 46 of 93
Data Sheet
AD9083
These conditions are different for unscrambled and scrambled
data. The scrambling operation is enabled by default, but it can
be disabled using the SPI.
Initial Lane Alignment Sequence (ILAS)
The ILAS phase follows the CGS phase and begins on the next
LMFC boundary after SYNCINB deassertion. The ILAS
consists of four mulitframes, with an /R/ character marking the
beginning and an /A/ character marking the end. The ILAS
begins by sending an /R/ character followed by 0 to 255 ramp
data for one multiframe. On the second multiframe, the link
configuration data is sent, starting with the third character. The
second character is a /Q/ character to confirm that the link
configuration data follows. All undefined data slots are filled
with ramp data. The ILAS sequence is never scrambled.
For scrambled data, any 0xFC character at the end of a frame
is replaced by an /F/, and any 0x7C character at the end of a
multiframe is replaced with an /A/. The JESD204B receiver
(Rx) checks for /F/ and /A/ characters in the received data
stream and verifies that they only occur in the expected
locations. If an unexpected /F/ or /A/ character is found, the
receiver handles the situation by using dynamic realignment or
asserting the SYNCINB signal for more than four frames to
initiate a resynchronization. For unscrambled data, if the final
octet of two subsequent frames are equal, the second octet is
replaced with an /F/ symbol if it is at the end of a frame, and an
/A/ symbol if it is at the end of a multiframe.
The ILAS sequence construction is shown in Figure 87. The
four multiframes include the following:
•
Multiframe 1 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
Insertion of alignment characters can be modified using SPI. The
frame alignment character insertion (FACI) is enabled by default.
•
Multiframe 2 begins with an /R/ character followed by a
/Q/ character (/K28.4/), followed by link configuration
parameters over 14 configuration octets (see Table 23) and
ends with an /A/ character. Many of the parameter values
are of the value – 1 notation.
8-Bit/10-Bit Encoder
The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols
and inserts control characters into the stream when needed. The
control characters used in JESD204B are shown in Table 23.
The 8-bit/10-bit encoding ensures that the signal is dc balanced by
using the same number of ones and zeros across multiple symbols.
•
•
Multiframe 3 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
Multiframe 4 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
The 8-bit/10-bit interface has options that can be controlled via
the SPI. These operations include bypass and invert. These options
are troubleshooting tools for the verification of the digital front
end (DFE). Refer to the Memory Map section, Register 0x2A3
(JTX_DL_204B_CONFIG0) for information on configuring the
8-bit/10-bit encoder.
User Data and Error Detection
After the initial lane alignment sequence is complete, the user
data (ADC samples) is sent. During transmission of the user data,
a mechanism called character replacement monitors the frame
clock and multiframe clock alignment. This mechanism replaces
the last octet of a frame or multiframe with an /F/ or /A/
alignment characters when the data meets certain conditions.
K
K
R
D
D
A
R
Q
C
C
D
D
A
R
D
D
A
R
D
D
A
D
END OF
MULTIFRAME
START OF
ILAS
START OF LINK
CONFIGURATION DATA
START OF
USER DATA
Figure 87. Initial Lane Alignment Sequence
Table 23. AD9083 Control Characters Used in JESD204B
10-Bit Value,
RD1 = −1
10-Bit Value,
RD1 = +1
Abbreviation
Control Symbol
/K28.0/
/K28.3/
/K28.4/
/K28.5/
8-Bit Value
000 11100
011 11100
100 11100
101 11100
111 11100
Description
/R/
/A/
/Q/
/K/
/F/
001111 0100
001111 0011
001111 0100
001111 1010
001111 1000
110000 1011
110000 1100
110000 1101
110000 0101
110000 0111
Start of multiframe
Lane alignment
Start of link configuration data
Group synchronization
Frame alignment
/K28.7/
1 RD means running disparity.
Rev. 0 | Page 47 of 93
AD9083
Data Sheet
DVDD
100Ω
DIFFERENTIAL
TRACE PAIR
0.1µF
0.1µF
SERDOUTx+
SERDOUTx–
100Ω
RECEIVER
OUTPUT SWING = 675mV p-p DIFFERENTIAL
ADJUSTABLE
Figure 88. AC-Coupled Digital Output Termination Example
The format of the output data is twos complement by default.
To change the output data format, see the Memory Map section
Register 0x18A (OUT_FORMAT_SEL ).
PHYSICAL LAYER (DRIVER) OUTPUTS
Digital Outputs, Timing, and Controls
The AD9083 physical layer consists of drivers that are defined in
the JEDEC Standard JESD204B, July 2011. The differential digital
outputs are powered up by default. The drivers use a dynamic
100 Ω internal termination to reduce unwanted reflections.
Deemphasis
Deemphasis enables the receiver eye diagram mask to be met in
conditions where the interconnect insertion loss does not meet
the JESD204B specification. Use the deemphasis feature only
when the receiver is unable to recover the clock due to excessive
insertion loss. Under normal conditions, it is disabled to conserve
power. Additionally, enabling and setting too high a deemphasis
value on a short link can cause the receiver eye diagram to fail.
Use the deemphasis setting with caution because it can increase
electromagnetic interference (EMI). See the Memory Map section
(Register 0x413 to Register 0x422 in Memory Map) for more
details.
Place a 100 Ω differential termination resistor at each receiver
input to result in a nominal 0.85 × DVDD V p-p swing at the
receiver (see Figure 88). The swing is adjustable through the
SPI registers. AC coupling is recommended to connect to the
receiver. See the Memory Map section (Register 0x402 to
Register 0x409) for more details.
The AD9083 digital outputs can interface with custom ASICs
and field programmable gate array (FPGA) receivers, providing
superior switching performance in noisy environments. Single
point-to-point network topologies are recommended with a
single differential 100 Ω termination resistor placed as close to
the receiver inputs as possible.
JTX PLL
The JTX PLL generates the serializer clock (fLR), which operates
at the JESD204B lane rate. The status of the PLL lock can be
checked in the PLL_STATUS register (Register 0x301), Bit 7
(JTX_PLL_LOCKED). This read only bit lets the user know if
the PLL has achieved lock for the specific setup.
If there is no far end receiver termination, or if there is poor
differential trace routing, timing errors can result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches, and that the differential output traces be
close together and at equal lengths.
Rev. 0 | Page 48 of 93
Data Sheet
AD9083
SETTING UP THE AD9083 DIGITAL INTERFACE
where:
OUT = fS/DECTOTAL.
fS is the ADC sample rate.
DECTOTAL is the total decimation rate of the signal processing
tile.
The AD9083 has one JESD204B link. The serial outputs
(SERDOUT0 to SERDOUT3 ) or lanes are considered to be
part of one JESD204B link. The maximum lane rate allowed by
the AD9083 is 16 Gbps.
f
The basic parameters that determine the link setup are
Table 24 shows the JESD204B output configurations supported
for the non-burst mode data path. Table 25 shows the
JESD204B output configurations supported for burst mode
data path. Take care to ensure that the serial line rate for a
given configuration is within the supported range of 0.25 Gbps
to 16 Gbps.
•
•
•
•
AD9083 datapath (nonburst or burst mode)
Number of converters per link (M).
Number of lanes per link (L).
N΄ is the number of bits per sample (JESD204B word size),
(AD9083 value = 12 or 16).
The lane line rate is related to the JESD204B parameters using
the following equation:
JESD204B TRANSPORT LAYER SETTINGS
See the JESD204B Overview section for details regarding the
transport layer information listed in Table 24 and Table 25.
10
8
M × N ' ×
× fOUT
Lane Rate =
L
Table 24. JESD2048 Output Configuration in Nonburst Mode Data
No. of Virtual Converters
Supported (Same Value as M)
JESD2048 Serial
Lane Rate
CIC N
4
8
16
4,
8
16
4
8
16
4
8
16
4
NCO/Mixer Decimate by J
L
M
F
S
N'
K
8
160 × fOUT
120 × fOUT
80 × fOUT
60 × fOUT
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
4, 8, 16
4, 8, 16
1, 4, 8, 16
4, 8, 16
4, 8, 16
1, 4, 8, 16
4
1
1
4
1
1
1
1
1
1
1
8
16
1
16 32
12 32
16 32
12 32
1
2
2
8
8
8
12
8
1
1
1
6
40 × fOUT
30 × fOUT
4
4
8
8
4
3
1
1
16 32
12 32
8
4
8
16
320 × fOUT
4
8
Bypassed
8, 12, 16, 20, 24, 30, 40, 60
4, 8, 10, 12, 16, 20, 24, 30, 40,
60
1
16 32
1
16 32
16
4, 8, 10, 12, 16, 20, 24, 30, 40,
60
1
20, 40, 60
240 × fOUT
4
8
16
Bypassed
Bypassed
10, 12, 20, 24, 30, 40, 60
10, 12, 16, 20, 24, 30, 40, 60
8, 10, 12, 16, 20, 24, 30, 40,
60
16, 20, 40, 60
4, 8,
4
1
2
16 24
1
1
12 32
1
4
8
160 × fOUT
16 16
16 32
16
1
Rev. 0 | Page 49 of 93
AD9083
Data Sheet
No. of Virtual Converters
Supported (Same Value as M)
JESD2048 Serial
Lane Rate
CIC N
1
NCO/Mixer Decimate by J
L
M
F
S
N'
K
20
120 × fOUT
80 × fOUT
1
4
8
16
1
4
8
16
1
8
Bypassed
Bypassed
16, 20
4
1
1
8, 12, 16, 24
4
1
1
2
3
16 12
1
1
12 32
12 32
16
16
16
8
8
6
80 × fOUT
Bypassed
4
1
16 32
8, 12, 16, 24
1
4, 8, 12, 16, 24
60 × fOUT
Bypassed
Enabled
4
1
1
1
12 32
16 16
1
32
640 × fOUT
4
16
32 64
8
8, 16
16
16
4
4, 8, 16,
16
8, 16
480 × fOUT
320 × fOUT
Enabled
Enabled
1
2
32 48
32 32
1
1
12 16
16 32
8
4, 8
16
4
8
16
4
8
4
160 × fOUT
160 × fOUT
120 × fOUT
Enabled
Enabled
Enabled
4, 8, 16,
4, 8, 16,
1, 4, 8, 16
4, 8
4
3
4
4
32 16
32 16
32 12
1
1
1
12 32
16 32
12 32
16
4
1
4
16
1
Table 25. JESD2048 Output Configuration Burst Mode Datapath .
No. of Virtual Converters Supported
(Same Value as M)
JESD2048 Lane Rate
640 × fOUT
640 × fOUT
480 × fOUT
480 × fOUT
640 × fOUT
640 × fOUT
480 × fOUT
480 × fOUT
640 × fOUT
640 × fOUT
480 × fOUT
480 × fOUT
480 × fOUT
480
CIC N NCO/Mixer
Dec H
L
1
1
1
1
2
2
2
2
3
3
3
3
4
4
M
F
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N’
K
32
4
8
4
8
4
8
4
8
4
8
4
8
4
8
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
24, 28, 32, 36
12, 14, 16, 18
24
32 64
32 64
32 48
32 48
64 64
64 64
64 48
64 48
96 64
96 64
96 48
96 48
96 48
96 48
16 16
16 16
12 16
12 16
16 16
16 16
12 16
12 16
16 16
16 16
12 16
12 16
16 16
16 16
12, 16
64
96
24, 28, 32
12, 14, 16
24
12
32, 36
18
24, 28, 32, 36
14, 18
24, 28
12, 14
Rev. 0 | Page 50 of 93
Data Sheet
AD9083
•
SYSREF jitter must be much less than one sample clock
DETERMINISTIC LATENCY
period. A SYSREF coming from an ASIC or an FPGA may
have significant jitter.
Both ends of the JESD204B link contain various clock domains
distributed throughout each system. Data traversing from one
clock domain to a different clock domain can lead to ambiguous
delays in the JESD204B link. These ambiguities lead to non-
repeatable latencies across the link from one power cycle or link
reset to the next. The AD9083 supports JESD204B Subclass 0
and Subclass 1 operation. If deterministic latency is not a
system requirement, Subclass 0 operation is recommended and
the SYSREF signal may not be required. Even in Subclass 0
mode, the SYSREF signal can required in an application where
multiple AD9083 devices must be synchronized with each other.
SYSREF Related Functionality
The AD9083 supports resynchronization of internal clocks and
NCOs, as well as across multiple AD9083 devices. The SYSREF
and trigger signal inputs to the AD9083 are used to provide a
synchronization triggering mechanism that supports
•
•
Deterministic latency in JESD Subclass 1 mode.
Multichip synchronization for NCO reset.
In resynchronization mode with the SYSREF_RESYNC_
MODE bit (Register 0x1C0, Bit 2 =1), the AD9083 aligns all
internal clocks to the SYSREF signal (for Subclass 1
synchronization and deterministic latency). In the case of
periodic SYSREF, after alignment is achieved, further periodic
SYSREF inputs are automatically aligned to the internal clocks.
A change in the SYSREF input phase initiates a re-alignment of
the datapath clocks to the new SYSREF input phase.
Subclass 0
If there is no requirement for multichip synchronization while
operating in Subclass 0 mode, the SYSREF input can be left
disconnected. In this mode, the relationship of the JESD204B
clocks between the JESD204B transmitter and receiver are
arbitrary but does not affect the ability of the receiver to
capture and align the lanes within the link
The NCORESET_ALL_SYSREF bit field set to 0 (default) in
Register 0x1C0, Bit 3 ensures that the NCOs only receive a reset
pulse in response to a SYSREF pulse that has resynchronized
the clocks. Program the NCOs to continuous synchronization
mode by programming DDC_SYNC_NEXT = 0 and
Subclass 1
The JESD204B protocol organizes data samples into octets,
frames, and multiframes, as described in the Transport Layer
section of this data sheet. The LMFC is synchronous with the
beginnings of these multiframes. In Subclass 1 operation, the
SYSREF signal is used to synchronize the LMFCs for each
device in a link or across multiple links (within the AD9083,
SYSREF signal also synchronizes the internal sample dividers).
The JESD204B receiver uses the multiframe boundaries and
buffering to achieve consistent latency across lanes (or even
multiple devices), and also to achieve a fixed latency between
power cycles and link reset conditions. The AD9083 features
sampled SYSREF modes for JESD204B Subclass 1 operation.
See the Multichip Synchronization (MCS) section for details.
DDC_SYNC_EN = 1 in Register 0x1C4, Bits[1:0].
The DDCs are programmed to reset the NCOs in response to
the periodic SYSREF pulse or the Nth SYSREF pulse received
using Register 0x284 (JTX_TPL_SYSREF_N_SHOT).
Multichip Synchronization and NCO Reset Options
There are two aspects of multichip synchronization:
•
•
Aligning the clocks across multiple devices.
Aligning the NCOs across multiple devices.
MULTICHIP SYNCHRONIZATION
Aligning Clocks Across Multiple Devices
The AD9083 has a JESD204B Subclass 1 compatible SYSREF
input, which provides flexible options for synchronizing the
internal blocks of the AD9083. The SYSREF input is a source
synchronous system reference signal used to align the AD9083
LMFCs that enables multichip synchronization between
multiple AD9083s. The input clock divider, the signal
processing tile, signal monitor block, and JESD204B link can be
synchronized using the SYSREF input.
Aligning the clocks across multiple devices is provided by the
SYSREF signal in resynchronization mode. The SYSREF signal
is used to align all the clocks in the AD9083. When SYSREF is
deterministically sampled by multiple devices, it implies that
the clocks are aligned across multiple devices.
Aligning NCOs Across Multiple Devices
NCO reset is handled by the reset of the NCO accumulators in
the AD9083 signal processing tiles. To ensure that the NCOs
are reset deterministically across devices, it is important to use
resynchronization mode.
SAMPLED SYSREF MODE
In sampled SYSREF mode, SYSREF operates as a standard
JESD204B Subclass 1 signal.
An external controller (for example, a clock generator chip )
generates periodic SYSREF pulses or a one-shot SYSREF pulse
to the SYSREF input.
The following are some characteristics of sampled SYSREF
synchronization:
•
•
Synchronous sampling of SYSREF.
Must meet setup/hold time requirements for reliable
synchronization. This is increasingly difficult to achieve as
the sample rate increases.
Rev. 0 | Page 51 of 93
AD9083
Data Sheet
The latency numbers, such as SYSREF LMFC delay, SYSREF to
NCO reset delay, and so on, depend on the configuration used.
Key Features and Notes Regarding Resynchronization
Mode
The latency of the NCO reset from SYSREF is constant for all
periodic SYSREF pulses. If the SYSREF period is altered, a
resynchronization followed by an NCO reset is triggered.
In SYSREF resynchronization mode, all clocks shut down and
restart in-phase to the SYSREF pulse.
The JESD LMFC aligns at a deterministic phase/delay from the
SYSREF pulse.
The SYSREF period for any mode must be a multiple of the
multiframe clock period. Additional restriction may be
required due to decimation modes.
The NCOs reset at a deterministic time after the SYSREF pulse
is received. The NCO reset occurs after the datapath clocks are
aligned to the new SYSREF.
An LMFC settling period of 8 LMFCs is expected for the
internal LMFC to stabilize after a SYSREF input initiates
realignment.
Rev. 0 | Page 52 of 93
Data Sheet
AD9083
SERIAL PORT INTERFACE (SPI)
The AD9083 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields. These fields are documented
in the Memory Map section. For detailed operational information,
see the Serial Control Interface Standard (Rev. 1.0).
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a
readback operation, performing a readback causes the SDIO
pin to change direction from an input to an output at the
appropriate point in the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB first
is the default on power-up and can be changed via the SPI port
configuration register. For more information about this and other
features, see the Serial Control Interface Standard (Rev. 1.0).
CONFIGURATION USING THE SPI
Three pins define the SPI of the AD9083 ADC: the SCLK pin,
the SDIO pin, and the CSB pin (see Table 26). The SCLK (serial
clock) pin is used to synchronize the read and write data
presented to and from the ADC. The SDIO (serial data input/
output) pin is a dual-purpose pin that allows data to be sent and
read from the internal ADC memory map registers. The CSB
(chip select bar) pin is an active low control that enables or
disables the read and write cycles. The falling edge of CSB, in
conjunction with the rising edge of SCLK, determines the start
of the framing. An example of the serial timing and its
definitions can be found in Figure 2 and Table 14.
HARDWARE INTERFACE
The pins described in Table 26 comprise the physical interface
between the user programming device and the serial port of the
AD9083. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Other modes involving the CSB pin are available. The CSB pin
can be held low indefinitely, which permanently enables the
device; this is called streaming. The CSB can stall high between
bytes to allow additional external timing. When CSB is tied
high, SPI functions are placed in a high impedance mode. This
mode turns on any SPI pin secondary functions.
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
Do not activate the SPI port during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is
used for other devices, it may be necessary to provide buffers
between this bus and the AD9083 to prevent these signals from
transitioning at the converter inputs during critical sampling
periods.
All data is composed of 8-bit words. The first bit of each
individual byte of serial data indicates whether a read or write
command is issued, which allows the SDIO pin to change
direction from an input to an output.
Table 26. Serial Port Interface Pins
Pin
Function
SCLK
SDIO
Serial clock. The serial shift clock input that is used to synchronize serial interface, reads, and writes.
Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction
being sent and the relative position in the timing frame.
CSB
Chip select bar. An active low control that gates the read and write cycles.
Rev. 0 | Page 53 of 93
AD9083
Data Sheet
PROGRAMMING GUIDE
The AD9083 is highly reconfigurable and programmable via
the SPI interface.
3. Delay = minimum 200 µs. Otherwise, wait for POR circuit
to deassert. The PORB_STAT register (Register 0x0020)
can be read back to verify the state of the PORb signals.
Register 0x0020 = 7Fh means the AD9083 is ready to be
programmed and the power supplies are at the optimal
level.
4. Configure any supporting circuitry to the AD9083. For
example, set up any necessary clock components so that
the reference clock to the AD9083 on-chip PLL is stable
before beginning to set up the AD9083.
The AD9083 product page contains instructions in the
Software and Systems Requirements section to request device
application programming interface (API) C code drivers. These
drivers are reference code that allows the user to quickly
configure the AD90803 using high level function calls, known
as application APIs. Analog Devices provides the full source
code for these high level function calls.
PROGRAMMING SEQUENCE
5. Configure any necessary setup for the FPGA in the system
to receive the JESD204B data after the AD9083 is fully
configured.
When powered on, the various blocks inside AD9083 power up
in a disabled state. To set up the AD9083 in a specific mode, a
set of SPI operations are required. Before beginning the full
programming of the device, ensure that the following sequence
is completed:
After the platform and system-dependent setup is complete and
stable, the AD9083 can be programmed to a desired configuration.
To simplify the programming details needed to configure the
AD9083, a short list of high level API function calls are
provided. These high level API calls completely configure the
device in any desired supported state. The programming
sequence for proper AD9083 setup is shown in Table 27.
1. Ramp up the supplies. There is no requirement for any
power supply sequencing. The POR circuitry holds the
AD9083 in reset until all the supplies reach the correct
threshold.
2. Issue a soft reset through SPI Register 0x000 = 81h, or by
toggling the RSTB pin.
Table 27. Programming Sequence to Set Up the AD9083
Step
No.
API Function
Input Parameters
Description
1
adi_ad9083_device_reset() &ad9083_dev: (device structure pointer) Performs a soft reset of the AD9083.
ad9083_soft_reset
2
adi_ad9083_device_init()
&ad9083_dev: (device structure pointer) Prints the API revision, retrieves the host CPU endian
mode, retrieves the host CPU type, configures the SPI
mode, executes a SPI read/write test, and checks the
power status.
3
4
adi_ad9083_device_
clock_config_set()
&ad9083_dev: (device structure pointer) Configures the on-chip PLL with the correct settings based
on the user input of the desired ADC sample rate and the PLL
reference clock that is provided to the CLK pins.
adc_clk_hz: ADC Sample Rate
ref_clk_hz: PLL Reference Clock
adi_ad9083_rx_
adc_config_set()
&ad9083_dev (device structure pointer) Configures the VCO ADC settings according to the desired
input settings for each parameter.
fc: -3dB LPF cutoff frequency
vmax: differential peak-to-peak input
full-scale
rterm: termination resistance
en_hp: enable high performance mode
backoff: dB backoff in terms of noise (dB
value × 100)
finmax: maximum input frequency,
should be set to fADC/20
Rev. 0 | Page 54 of 93
Data Sheet
AD9083
Step
No.
API Function
Input Parameters
Description
5
adi_ad9083_rx_
&ad9083_dev: (device structure pointer) Configures the digital datapath of the ADC based on the
datapath_config_set()
desired signal path flow (determined by the mode input
parameter), the decimation rates chosen, and the NCO
frequency shift (if used). The valid adi_ad9083_datapath_
mode_e enumeration values are as follows:
mode: determines datapath flow, refer
to enumeration
adi_ad9083_datapath_mode_e for
exact details
dec: array of decimation value choices
including CIC decimation, J decimation,
G averaging value and H decimation
nco_freq_hz: NCO shift frequency
desired
AD9083_DATAPATH_ADC_CIC: ADC → CIC → JESD204B
Output
AD9083_DATAPATH_ADC_CIC_NCO_J: ADC → CIC →
NCO → J Decimation → JESD204B Output
AD9083_DATAPATH_ADC_CIC_J: ADC → CIC → NCO → J
Decimation → JESD204B Output
AD9083_DATAPATH_ADC_J: ADC → J Decimation →
JESD204B Output
AD9083_DATAPATH_ADC_CIC_NCO_G: ADC → CIC →
NCO → G average samples → JESD204B Output
AD9083_DATAPATH_ADC_CIC_NCO_G_H: ADC → CIC →
NCO → G average samples → H Decimation → JESD204B
Output
6
adi_ad9083_jtx_startup()
&ad9083_dev: (device structure pointer) Configures the JESD204B interface with the SERDES
parameters for the desired configuration. Array inputs are:
{L, F, M, S, HD, K, N, NP, CF, CS, DID, BID, LID, SC, SCR},
where SC = subclass
&jtx_param: pointer to array of
JESD204B parameter settings for
desired mode operation
These API function calls are all that are needed to set up the
device. All lower level SPI writes are handled by the API
function calls underneath these high level calls and are
abstracted to make configuration easier for the user. More
detailed information about each of these API function calls and
the lower level SPI configuration included in the source code
can be found in the AD9083 API specification document,
which is provided with the API source code. This source code
package can be requested through the instructions provided at
the AD9083 product page.
Rev. 0 | Page 55 of 93
AD9083
Data Sheet
Example 1: Wide Bandwidth Real Output Mode
•
•
•
•
•
•
•
•
•
•
•
Low pass filter cut-off frequency (fC) = 800 MHz.
MAX = 2.0 V.
TERM = 100 Ω.
EN_HP = 0.
Backoff = 0 dB.
Mixer bypassed (real data).
CIC decimator bypassed.
Decimate by J = 8.
Output bandwidth = 100 MHz.
Transport parameters L, M, F, S, N’, K = 4, 16, 6, 1, 12, 32.
Each lane = 15 Gbps.
V
R
After powering up the device, execute the API sequence
according to the target application requirements listed in this
section. This sequence configures the AD9083 to operate in wide
bandwidth mode without frequency translation in the datapath.
The total power consumption in this mode is about 1.42 W. This is
the mode of operation used to measure the data sheet parameters
listed in the specification tables. (see Table 1).
•
•
•
Sample rate = 2 GSPS.
On-chip PLL reference = 250 MHz.
f
INMAX = 100 MHz (sample rate/20).
The following API sequence with specific input parameters is needed to fully configure the device in the wide bandwidth mode of operation:
// Define device structure and instantiate
adi_ad9083_device_t ad9083_dev;
// Perform soft reset
adi_ad9083_device_reset(&ad9083_dev, 0);
// Get API revision, CPU info etc
adi_ad9083_device_init(&ad9083_dev);
// Set up clocking configuration, lock on-chip PLL
//ADC Sample Rate = 2GSPS (adc_clk_hz in units of Hz)
//PLL Reference Clock = 250MHz (ref_clk_hz in units of Hz)
adi_ad9083_device_clock_config_set(&ad9083_dev, adc_clk_hz = 2000000000, ref_clk_hz =
250000000);
// Setup VCO ADC settings
//LPF bandwidth Fc = 800MHz (fc in units of Hz), Vmax = 2.0V (vmax in mV units)
//Rterm = 100 ohm (rterm bitfield = 2 for 100 ohm), Enhp = 0
//Backoff = 0dB (backoff in terms of noise, dB * 100)
//Finmax = 100MHz (finmax in units of Hz)
adi_ad9083_adc_term_res_e rterm = AD9083_ADC_TERM_RES_100; // (enum value = 2)
adi_ad9083_rx_adc_config_set(&ad9083_dev, fc = 800000000, vmax = 2000, rterm = term, en_hp
= 0, backoff = 0, finmax = 100000000);
// Setup Datapath
//Datapath: ADC -> J -> JESD204B output
//Decimation: CIC bypassed (/1), J Decimation = 8, G value bypassed, H value bypassed
//NCO frequency shifts: NCO0, NCO1 & NCO2 bypassed
adi_ad9083_datapath_mode_e datapath_mode = AD9083_DATAPATH_ADC_J;
uint8_t dec[] = {0, AD9083_J_DEC_8, 0, 0};
uint64_t nco_freq_hz = { 0, 0, 0};
adi_ad9083_rx_datapath_config_set(&ad9083_dev, datapath_mode, dec, nco_freq_hz);
Rev. 0 | Page 56 of 93
Data Sheet
AD9083
// Setup JESD204B
// L, M, F, S, N’, K = 4,16,6,1,12,32
adi_cms_jesd_param_t jtx_param[] =
/*L
F
M
S
HD
K
N
'
CF CS DID BID LID SC SCR */
0, 0, 0, 0, 0, 0, 1 };
{ 4, 6, 16, 1,
1, 32, 12, 12,
adi_ad9083_jtx_startup(&ad9083_dev, &jtx_param);
0
–20
SNR = 64.5dBFS
SFDR = 65dBFS
–40
–60
–80
HD3
–100
–120
0
12.50 25 37.50 50 62.50 75 87.50 100 112.50 125
FREQUENCY (MHz)
Figure 89. FFT Wide Bandwidth Real Output Mode
Table 28. Power Consumption Wide Bandwidth
Domain
Voltage (V)
Current (A)
0.397
Power (W)
0.397
AVDD
1
AVDD1P8
DVDD
1.8
1
0.096
0.774
0.1728
0.774
DVDD1P8
1.8
0.041
Total
0.0738
1.4176
0.089
Power per Channel (W)
1 OF 16 CHANNELS SHOWN
ADC
15Gbps/
LANE
J
JESD204B
Tx
I
19.7MHz
8
2GHz ADC
SAMPLE CLOCK
L = 4
M = 16
F = 6
S = 1
K = 32
NP = 12
CLOCK GENERATION
AND
250MHz
REF IN
DISTRIBUTION
Figure 90. Wide Bandwidth Real Output Mode Block Diagram, See Table 1
Rev. 0 | Page 57 of 93
AD9083
Data Sheet
Example 2 : Narrow Bandwidth Complex Output Mode
•
•
•
•
•
•
•
Backoff = 0
NCO0/mixer (complex data), FTW = 70.3125 MHz.
CIC decimator = 4.
Decimate by J = 16.
Output bandwidth = 12.7187 MHz.
Transport parameters L, M, F, S, N’, K = 2, 32, 32, 1, 16, 32.
Each lane = 10 Gbps.
After powering up the device, execute the API sequence
according to the target application requirements listed in this
section. This sequence configures the AD9083 to operate in narrow
bandwidth mode using frequency translation in the datapath. The
total power consumption in this mode is about1.17 W.
•
•
•
•
•
•
•
Sample rate = 2 GSPS.
On-chip PLL reference = 250 MHz.
f
INMAX = 100 MHz (sample rate/20).
fC = 800 MHz.
MAX = 2.0 V.
TERM = 100 Ω.
EN_HP = 0
V
R
The following API sequence with specific input parameters is needed to fully configure the part in the wide bandwidth mode of operation:
// Define device structure and instantiate
adi_ad9083_device_t ad9083_dev;
// Perform soft reset
adi_ad9083_device_reset(&ad9083_dev, 0);
// Get API revision, CPU info etc
adi_ad9083_device_init(&ad9083_dev);
// Set up clocking configuration, lock on-chip PLL
//ADC Sample Rate = 2GSPS (adc_clk_hz in units of Hz)
//PLL Reference Clock = 250MHz (ref_clk_hz in units of Hz)
adi_ad9083_device_clock_config_set(&ad9083_dev, adc_clk_hz = 2000000000, ref_clk_hz =
250000000);
// Setup VCO ADC settings
//LPF bandwidth Fc = 800MHz (fc in units of Hz), Vmax = 2.0V (vmax in mV units)
//Rterm = 100 ohm (rterm bitfield = 2 for 100 ohm), Enhp = 0
//Backoff = 0dB (backoff in terms of noise, dB * 100)
//Finmax = 100MHz (finmax in units of Hz)
adi_ad9083_adc_term_res_e rterm = AD9083_ADC_TERM_RES_100; // (enum value = 2)
adi_ad9083_rx_adc_config_set(&ad9083_dev, fc = 800000000, vmax = 2000, rterm = term, en_hp
= 0, backoff = 0, finmax = 100000000);
// Setup Datapath
//Datapath: ADC -> CIC -> NCO -> J -> JESD204B output
//Decimation: CIC =4, J Decimation = 16, G value bypassed, H value bypassed
//NCO frequency shifts: NCO0 = 70.3125MHz, NCO1 & NCO2 bypassed
adi_ad9083_datapath_mode_e datapath_mode = AD9083_DATAPATH_ADC_CIC_NCO_J;
uint8_t dec[] = {AD9083_CIC_DEC_4, AD9083_J_DEC_16, 0, 0};
uint64_t nco_freq_hz = { 70312500, 0, 0};
adi_ad9083_rx_datapath_config_set(&ad9083_dev, datapath_mode, dec, nco_freq_hz);
Rev. 0 | Page 58 of 93
Data Sheet
AD9083
// Setup JESD204B
// L, M, F, S, N’, K = 2,32,32,1,16,32
adi_cms_jesd_param_t jtx_param[] =
/*L
F
M
S
HD
K
N
'
CF CS DID BID LID SC SCR */
{ 2, 32, 32, 1,
1, 32, 16, 16,
0, 0, 0,
0,
0,
0, 1 };
adi_ad9083_jtx_startup(&ad9083_dev, &jtx_param);
0
–20
SNR = 70.2dBFS
SFDR = 86.8dBFS
–40
–60
–80
–100
–120
–140
–16
–11
–7
–2
2
7
11
16
FREQUENCY (MHz)
Figure 91. FFT Narrow Bandwidth Complex Output Mode
Table 29. Power Consumption Narrow Bandwidth
Domain
Voltage (V)
Current (A)
Power (W)
0.396
0.1728
0.532
0.0738
1.1746
0.073
AVDD
AVDD1P8
DVDD
1
1.8
1
0.396
0.096
0.532
0.041
Total
DVDD1P8
1.8
Power per Channel (W)
1 OF 16 CHANNELS SHOWN
I
I
70.3125MHz
NCO
cos(wt)
10Gbps/
LANE
CIC
J DECIMATOR
16
90°
0°
JESD204B
Tx
70.5MHz
ADC
4
CORR = 1.0×
–sin(wt)
2GHz ADC
SAMPLE CLOCK
Q
Q
L = 2
M = 32
F = 32
S = 1
K = 32
NP = 16
CLOCK GENERATION
AND
250MHz
REF IN
DISTRIBUTION
Figure 92. Narrow Bandwidth Complex Output Mode Block Diagram
Rev. 0 | Page 59 of 93
AD9083
Data Sheet
MEMORY MAP
All address locations that are not included in the memory map
are not currently supported for this device and must not be
written.
LOGIC LEVELS
An explanation of logic level terminology follows:
•
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
X denotes a don’t care bit.
Rev. 0 | Page 60 of 93
Data Sheet
AD9083
MEMORY MAP REGISTER DETAILS
Table 30. AD9083 Memory Map Register Details
Addr. Name
Bits
Bit Name
Description
Reset Access
Analog Devices SPI Registers
0x000 SPI_INTERFACE_
CONFIG_A
7
SOFT_RESET_7
Initiates a Reset Equivalent to a Hard Reset.
Whenever a soft reset is issued, the user must
wait at least 200 µs before writing to any other
register, to provide sufficient time for the device
reset to complete.
0x0
R/W
0: Do nothing.
1: Reset the SPI and registers (self clearing).
6
5
LSB_FIRST_6
LSB/MSB Bit Shift First.
1: Least significant bit shifted first for all SPI
operations.
0: Most significant bit shifted first for all SPI
operations.
Multibyte SPI Operations Address Increment.
0: Multibyte SPI operations cause addresses to
auto-decrement.
0x0
0x0
R/W
R/W
ADDR_ASCENSION_5
1: Multibyte SPI operations cause addresses to
auto-increment.
[4:3]
2
RESERVED
Reserved.
0x0
0x0
R/W
R/W
ADDR_ASCENSION_2
Mirror of 0x000[5].
0: Multibyte SPI operations cause addresses to
auto-decrement.
1: Multibyte SPI operations cause addresses to
auto-increment.
1
LSB_FIRST_1
Mirror of 0x000[6].
0x0
R/W
1: Least significant bit shifted first for all SPI
operations.
0: Most significant bit shifted first for all SPI
operations.
0
7
SOFT_RESET_0
Mirror of 0x000[7].
0: Do nothing.
1: Reset the SPI and registers (self clearing).
SPI Streaming Mode.
0x0
0x0
R/W
R/W
0x01
0x02
SPI_INTERFACE_
CONFIG_B
SINGLE_INSTRUCTION
0: Streaming is enabled.
1: Streaming is disabled. Only one read or write
operation is performed regardless of the state of
the CSB line.
[6:0]
[7:2]
[1:0]
RESERVED
RESERVED
OP_MODE
Reserved.
Reserved.
0x0
0x0
0x0
R/W
R
DEVICE_CONFIG
Operating Mode.
00: Normal Operation.
01: Normal Operation with Reduced Power.
10: Standby.
R/W
11: Sleep.
0x03
0x04
0x05
0x06
CHIP_TYPE
[7:0]
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
CHIP_TYPE
High Speed ADCs.
Chip ID. AD9083
Chip ID. AD9083
Chip Speed Grade.
Reserved.
Offset Pointer or LSB of the Device Index
Register.
Offset Pointer or LSB of the Device Index
Register.
0x3
0xEA
0x0
0x0
0x0
0x0
R
R
R
PROD_ID_LSB
PROD_ID_MSB
CHIP_GRADE
PROD_ID[7:0]
PROD_ID[15:8]
CHIP_SPEED_GRADE
RESERVED
R
R
R/W
0x08
0x09
DEVICE_INDEX1
DEVICE_INDEX2
DEV_INDEX1
[7:0]
DEV_INDEX2
0x0
R/W
Rev. 0 | Page 61 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
Reset Access
0x0A CHIP_SCRATCH
[7:0]
CHIP_SCRATCH
Chip Scratchpad Register. This register is used to 0x0
provide a consistent memory location for
software debug.
R/W
0x0C
VENDOR_ID_LSB
[7:0]
[7:0]
7
CHIP_VENDOR_ID[7:0]
CHIP_VENDOR_ID[15:8]
RESERVED
PORB_VDDSYNTH_JTX_PLL_1 PORb Status of JESD PLL 1.0 V VDD.
P0
Vendor ID.
Vendor ID.
Reserved.
0x56
R
R
R
R
0x0D VENDOR_ID_MSB
0x20
0x4
0x0
0x0
PORB_STAT
6
5
4
PORB_VDDPHY_SER_1P0
PORB_VDDLDO_JTX_PLL_
1P8
PORb Status of JESD SER PHY 1.0 V VDD.
PORb Status of JESD PLL (LDO) 1.8 V VDD.
0x0
0x0
R
R
3
2
1
PORB_VDDCP_JTX_PLL_1P0 PORb Status of JESD PLL 1.0 V VDD.
0x0
0x0
0x0
R
R
R
PORB_VDD_SYNCRX_1P8
PORB_VDD_DIG_1P0
PORb Status for SYNCRX I/O VDD 1.8V.
PORb Status of Digital 1.0 V VDD and Digital I/O
1.8 V VDD.
0
PORB_VDD_ANA
Status of VDD Domains in ADC, CLKTOP, on-chip 0x0
PLL, and TOPREF.
R
0x21
0x24
PORB_MASK_RESET
BLOCK_RESET
[7:1]
0
RESERVED
PORB_IGNORE
Reserved.
0x0
R
R/W
Controls Whether or Not to Gate Internal Resets 0x0
with PORb.
Reserved.
Resets the DIG Datapath and JTX.
1: Assert Reset.
[7:6]
5
RESERVED
DIG_DP_JTX_RESET
0x0
0x0
R
R/W
0: De-Assert Reset
4
3
2
1
0
JTX_PLL_RESET
JTXPHY_RESET
TOPREF_RESET
CLKTOP_RESET
ADC_RESET
Reset the JTX_PLL.
1: Assert Reset.
0: De-Assert Reset.
Reset the SER PHY.
1: Assert Reset.
0: De-Assert Reset.
Reset the TOP REF.
1: Assert Reset.
0: De-Assert Reset.
Reset the CLK TOP.
1: Assert Reset.
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
0: De-Assert Reset.
Reset the ADCs.
1: Assert Reset.
0: De-Assert Reset.
0x30
LOW_PWR_PIN_CTRL
[7:6]
5
RESERVED
JTXPHY_PIN_CTRL
Reserved.
For JTXPHY.
0x0
0x0
R
R/W
1: PD Pin and MASK Bit Control
0: CONFIG Bit Programming Control
For JTX.
1: PD Pin and MASK Bit Control
0: CONFIG Bit Programming Control
For DIG DP.
4
3
JTX_PIN_CTRL
0x0
0x0
R/W
R/W
DIG_DP_PIN_CTRL
1: PD Pin and MASK Bit Control
0: CONFIG Bit Programming Control
Rev. 0 | Page 62 of 93
Data Sheet
AD9083
Addr. Name
Bits
Bit Name
Description
Reset Access
2
TOPREF_PIN_CTRL
For TOP REF.
0x0
0x0
0x0
R/W
R/W
R/W
1: PD Pin and MASK Bit Control
0: CONFIG Bit Programming Control
Power Down for CLKTOP.
1: PD Pin and MASK Bit Control
0: CONFIG Bit Programming Control
For All 16 ADCs.
1
0
CLKTOP_PIN_CTRL
ADC_PIN_CTRL
1: PD Pin and MASK Bit Control
0: CONFIG Bit Programming Control
Reserved.
0x31
0x32
LOW_PWR_PIN_
POLARITY
[7:2]
[1:0]
RESERVED
POL
0x0
0x0
R
Polarity of PD Pin.
0: Active High.
1: Active Low.
Reserved.
Low Power Mode for JTXPHY.
0 : Normal Mode.
R/W
LOW_PWR_CONFIG
[7:6]
5
RESERVED
JTXPHY_LP_MODE
0x0
0x0
R
R/W
1 : Low Power Mode.
Low Power Mode for JTX.
0: Normal Mode
1: Low Power Mode
Low Power Mode for Digital Datapath.
0: Normal Mode
4
3
2
JTX_LP_MODE
0x0
0x0
0x0
R/W
R/W
R/W
DIG_DP_LP_MODE
TOPREF_LP_MODE
1: Low Power Mode
Low Power Mode for Top Ref. If 1 then bias
currents to on-chip PLL, ADC, clock buffer and
monitor mux from master bias are disabled. BG is
still active.
0: Normal Mode
1: Low Power Mode
1
0
CLKTOP_LP_MODE
ADC_LP_MODE
Low Power Mode for Clock Top.
0: Normal Mode
1: Low Power Mode
Low Power Mode for All 16 ADCs.
0: Normal Mode
1: Low Power Mode
Reserved.
0x0
0x0
R/W
R/W
0x33
LOW_PWR_PIN_MASK [7:6]
5
RESERVED
JTXPHY_LP_PIN_MASK
0x0
0x0
R
R/W
Mask the PD to JTXPHY.
0: Mask
1: Unmask
4
3
2
1
0
JTX_LP_PIN_MASK
Mask the PD to JTX.
0: Mask
1: Unmask
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
DIG_DP_LP_PIN_MASK
TOPREF_LP_PIN_MASK
CLKTOP_LP_PIN_MASK
ADC_LP_PIN_MASK
Mask the PD to DIG_DP.
0: Mask
1: Unmask
Mask the PD to TOP REF.
0: Mask
1: Unmask
Mask the PD to CLKTOP.
0: Mask
1: Unmask
Mask the PD to ADC
0: Mask
1: Unmask.
Rev. 0 | Page 63 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
Reset Access
Digital Datapath Setup Registers
0x100 NCO0_CONTROL
[7:1]
0
RESERVED
ADITHER_EN0
Reserved.
0x0
0x1
R
R/W
Amplitude Dither Enable for NCO0.
1: Enables amplitude dither.
0: Disables amplitude dither.
Reserved.
NCO Frequency Tuning Word for NCO0. Specifies
the frequency tuning word for NCO0. Only Bits[6:0]
are valid.
0x105 NCO0_FTW
7
[6:0]
RESERVED
NCO0_FTW
0x0
0x0
R
R/W
0x106 NCO0_PHOFF
7
RESERVED
Reserved.
0x0
R
[6:0]
NCO0_PHOFF
NCO Phase Offset for NCO0. Specifies the phase 0x0
offset for NCO0. Only Bits[6:0] are valid
R/W
0x107 NCO1_CONTROL
[7:1]
0
RESERVED
ADITHER_EN1
Reserved.
0x0
0x1
R
R/W
Amplitude Dither Enable for NCO1.
1: Enables amplitude dither.
0: Disables amplitude dither.
Reserved.
0x10C NCO1_FTW
7
RESERVED
0x0
R
[6:0]
NCO1_FTW
NCO Frequency Tuning Word for NCO1. Specifies 0x0
the frequency tuning word for NCO0. Only
Bits[6:0] are valid
R/W
0x10D NCO1_PHOFF
7
RESERVED
Reserved.
0x0
R
[6:0]
NCO1_PHOFF
NCO Phase Offset for NCO1. Specifies the phase 0x0
offset for NCO0. Only Bits[6:0] are valid
R/W
0x10E NCO2_CONTROL
[7:1]
0
RESERVED
ADITHER_EN2
Reserved.
0x0
0x1
R
R/W
Amplitude Dither Enable for NCO2.
1: Enables amplitude dither.
0: Disables amplitude dither.
Reserved.
0x113 NCO2_FTW
7
RESERVED
0x0
R
[6:0]
NCO2_FTW
NCO Frequency Tuning Word for NCO2. Specifies 0x0
the frequency tuning word for NCO0. Only
Bits[6:0] are valid
R/W
0x114 NCO2_PHOFF
0x115 MIXER_CTRL
7
[6:0]
RESERVED
NCO2_PHOFF
Reserved.
0x0
R
R/W
NCO Phase Offset for NCO2. Specifies the phase 0x0
offset for NCO0. Only Bits[6:0] are valid
Reserved.
[7:2]
[1:0]
RESERVED
MIXER_MODE
0x0
0x0
R
R/W
Mixer Mode.
00: Normal Mode: Output is input multiplied by
NCO data.
01: NCO Bypass Mode: Output is same as input.
10: Reserved.
11: NCO Test Mode : Output is constant times
NCO Data.
0x116 DP_CTRL
7
RESERVED
Reserved.
0x0
R
[6:5]
NUM_TONES
Number of Tones. Defines number of Tones per 0x3
ADC in Burst mode. This field is valid only for
BURST_MODE = 1 case.
R/W
00: Invalid.
01: 1 Tone.
10: 2 Tone.
11: 3 Tones.
4
DECI_ADC_DATA
ADC Output as input to J decimator.
1: ADC output to J decimator.
0: CIC output to J decimator.
0x0
R/W
Rev. 0 | Page 64 of 93
Data Sheet
AD9083
Addr. Name
Bits
Bit Name
Description
Reset Access
3
NCO_6DB_GAIN
Enable Gain 6 db.
0x0
R/W
1: Enables the 6 dB gain when NCO is used in
datapath
0: Disables 6 dB gain for all modes
2
1
BURST_MODE
Burst Mode.
0x1
0x0
R/W
R/W
1: Burst mode is selected. Selects the G/H path.
0: Non-burst Mode. Selects the Decimate by J path.
NCO Bypass. Note that this bit is valid only for
non-burst mode.
NO_DDC_MODE
1: Bypasses the NCO/MIXER( Real Data).
0: NCO/MIXER Enabled.
Datapath Enable.
0
DATAPATH_EN
0x0
R/W
1: Enables all the 16 datapaths.
0: Disables all the 16 datapaths.
Reserved.
CIC Accumulator Clear.
1: Clears the CIC accumulators in all the 16
datapaths
0x117 CIC_CTRL
[7:3]
2
RESERVED
CIC_ACC_CLR
0x0
0x0
R
R/W
0: No Action
[1:0]
CIC_DEC_RATE
CIC Decimation Rate.
00-Decimate by 4
0x0
R/W
01: Decimate by 8
10: Decimate by 16
This is common for all the 16 datapaths
00: Decimate by 4.
01: Decimate by 8.
10: Decimate by 16.
0x118 DECIMATE_H
[7:0]
H_VALUE
"H" Value. Specifies the "H" value for decimation 0x10 R/W
in burst mode. (G/H)
Eg: 'h04 ==> Decimate by 4
000001: 1.
001100: 12.
001110: 14.
010000: 16.
010010: 18.
011000: 24.
011100: 28.
100000: 32.
100100: 36.
0x119 DECIMATE_G
[7:0]
G_VALUE
"G" Value. Specifies the "G" value in burst mode. 0x8
R/W
(G/H)
It is for these many samples averaging has to be
done.
00000: N/A.
01000: 8.
10000: 16.
0x11A DECIMATE_J
[7:4]
[3:0]
RESERVED
DEC_J
Reserved.
0x0
0x0
R
R/W
Bits for J Decimator.
0000: Bypass (No Decimation).
0001: Decimate by 4.
0010: Decimate by 8.
0011: Decimate by 16.
0100: Not Valid.
0101: Not Valid.
0110: Decimate by 12.
Rev. 0 | Page 65 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
Reset Access
0111: Decimate by 24.
1000: Not Valid.
1001: Decimate By 10 (Valid only for CIC Data
Not valid for Decimation of ADC Data).
1010: Decimate by 20.
1011: Decimate by 40.
1100: Not Valid.
1101: Not Valid.
1110: Not Valid.
1111: Decimate by 60.
0x11B DECIMATE_H_EFF
[7:0]
H_EFF_VALUE
"H_EFF" Value. Specifies the "H" value for
decimation in burst mode. (G/H)
Eg: 'h04 ==> Decimate by 4
0x10
R
0x152 CIC_GAIN_ADJ_
VALUE_0
0x153 CIC_GAIN_ADJ_
VALUE_1
[7:0]
[7:2]
CIC_GAIN_ADJ_VAL_0[7:0]
RESERVED
CIC Gain Adj 0. integer-4. fraction-10
0x7
0x0
R/W
R
Reserved.
[1:0]
[7:4]
CIC_GAIN_ADJ_VAL_0[9:8]
RESERVED
CIC Gain Adj 0. integer-4. fraction-10
Reserved.
0x0
0x0
R/W
R
0x154 CIC_GAIN_ADJ_
VALUE_2
[3:0]
[7:0]
CIC_GAIN_ADJ_VAL_0[13:10] CIC Gain Adj 0. integer-4. fraction-10
0x1
0x20 R/W
R/W
0x155 CIC_GAIN_ADJ_
VALUE_3
CIC_GAIN_ADJ_VAL_1[7:0]
CIC Gain Adj 1. integer-4. fraction-10
0x156 CIC_GAIN_ADJ_
VALUE_4
[7:2]
RESERVED
Reserved.
0x0
R
[1:0]
[7:4]
CIC_GAIN_ADJ_VAL_1[9:8]
RESERVED
CIC Gain Adj 1. integer-4. fraction-10
Reserved.
0x0
0x0
R/W
R
0x157 CIC_GAIN_ADJ_
VALUE_5
[3:0]
[7:0]
CIC_GAIN_ADJ_VAL_1[13:10] CIC Gain Adj 1. integer-4. fraction-10
0x1
0x4A R/W
R/W
0x158 CIC_GAIN_ADJ_
VALUE_6
CIC_GAIN_ADJ_VAL_2[7:0]
CIC Gain Adj 2. integer-4. fraction-10
0x159 CIC_GAIN_ADJ_
VALUE_7
[7:2]
RESERVED
Reserved.
0x0
R
[1:0]
[7:4]
CIC_GAIN_ADJ_VAL_2[9:8]
RESERVED
CIC Gain Adj 2. integer-4. fraction-10
Reserved.
0x0
0x0
R/W
R
0x170 CIC_GAIN_ADJ_
VALUE_8
[3:0]
[7:6]
5
CIC_GAIN_ADJ_VAL_2[13:10] CIC Gain Adj 2. integer-4. fraction-10
RESERVED Reserved.
DFORMAT_DDC_DITHER_EN 0: Disable
1: Enable
0x1
0x0
0x0
R/W
R
R/W
0x189 OUT_RES
4
[3:0]
RESERVED
DFORMAT_RES
Reserved.
0x0
0x0
R/W
R/W
Data Output Resolution.
0000: 16-bit resolution.
0001: 15-bit resolution.
0010: 14-bit resolution.
0011: 13-bit resolution.
0100: 12-bit resolution.
0101: 11-bit resolution.
0110: 10-bit resolution.
0111: 9-bit resolution.
1000: 8-bit resolution.
Rev. 0 | Page 66 of 93
Data Sheet
AD9083
Addr. Name
0x18A OUT_FORMAT_SEL
Bits
[7:3]
2
Bit Name
RESERVED
DFORMAT_INV
Description
Reserved.
Output Data Inversion Enable. Digital ADC
Sample Invert
Reset Access
0x0
0x0
R
R/W
0: ADC sample data is NOT inverted
1: ADC sample data is inverted
[1:0]
DFORMAT_SEL
Output Data Format Selection.
00: 2'Complement.
01: Offset Binary.
0x0
R/W
10: Gray Code.
0x18B CTRL_0_1_SEL
[7:4]
[3:0]
DFORMAT_CTRL_BIT_1_SEL
DFORMAT_CTRL_BIT_0_SEL
Control Bit 1 Mux Selection.
00: Overrange Bit.
01: SYSREF.
Control Bit 0 Mux Selection.
00: Overrange Bit.
01: SYSREF.
0x0
0x0
R/W
R/W
0x18C CTRL_2_SEL
0x18D OVR_CLR_0
[7:4]
[3:0]
RESERVED
DFORMAT_CTRL_BIT_2_SEL
Reserved.
0x0
0x0
R
R/W
Control Bit 2 Mux Selection.
00: Overrange Bit.
01: SYSREF.
Overrange Status Clear. Converter overrange
clear bit (active high).
[7:0]
[7:0]
[7:0]
DFORMAT_OVR_CLR[7:0]
DFORMAT_OVR_CLR[15:8]
DFORMAT_OVR_CLR[23:16]
0x0
0x0
0x0
R/W
R/W
R/W
After an overrange sticky bit is set,
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
0x18E OVR_CLR_1
Overrange Status Clear. Converter overrange
clear bit (active high).
After an overrange sticky bit is set,
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
0x18F OVR_CLR_2
Overrange Status Clear. Converter overrange
clear bit (active high).
After an overrange sticky bit is set,
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
Rev. 0 | Page 67 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
Reset Access
0x190 OVR_CLR_3
[7:0]
DFORMAT_OVR_CLR[31:24]
Overrange Status Clear. Converter overrange
clear bit (active high).
After an overrange sticky bit is set,
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
0x191 OVR_CLR_4
0x192 OVR_CLR_5
0x193 OVR_CLR_6
0x194 OVR_CLR_7
[7:0]
[7:0]
[7:0]
[7:0]
DFORMAT_OVR_CLR[39:32]
DFORMAT_OVR_CLR[47:40]
DFORMAT_OVR_CLR[55:48]
DFORMAT_OVR_CLR[63:56]
Overrange Status Clear. Converter overrange
clear bit (active high).
After an overrange sticky bit is set,
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
Overrange Status Clear. Converter overrange
clear bit (active high).
After an overrange sticky bit is set,
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
Overrange Status Clear. Converter overrange
clear bit (active high).
After an overrange sticky bit is set,
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
Overrange Status Clear. Converter overrange
clear bit (active high).
After an overrange sticky bit is set,
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
Rev. 0 | Page 68 of 93
Data Sheet
AD9083
Addr. Name
Bits
Bit Name
Description
Reset Access
0x195 OVR_CLR_8
[7:0]
DFORMAT_OVR_CLR[71:64]
Overrange Status Clear. Converter overrange
clear bit (active high).
After an overrange sticky bit is set,
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
0x196 OVR_CLR_9
0x197 OVR_CLR_10
0x198 OVR_CLR_11
[7:0]
[7:0]
[7:0]
DFORMAT_OVR_CLR[79:72]
DFORMAT_OVR_CLR[87:80]
DFORMAT_OVR_CLR[95:88]
Overrange Status Clear. Converter overrange
clear bit (active high).
After an overrange sticky bit is set,
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
Overrange Status Clear. Converter overrange
clear bit (active high).
After an overrange sticky bit is set,
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
Overrange Status Clear. Converter overrange
clear bit (active high).
After an overrange sticky bit is set,
it remains set until explicitly cleared by writing a
1 to the corresponding DFORMAT_OVR_CLR bit.
The DFORMAT_OVR_CLEAR[95:0] bits must be
cleared for further overrange to be reported .
[0] = Overrange sticky bit clear for Converter 0
[1] = Overrange sticky bit clear for Converter 1
[2] = Overrange sticky bit clear for Converter 2
and so on.
Rev. 0 | Page 69 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
Reset Access
0x199 OVR_STATUS_0
[7:0]
DFORMAT_OVR_STATUS[7:0] Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high).
One bit for each virtual converter
0x0
0x0
0x0
R
R
R
0: No overrange occurred.
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits. The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
0x19A OVR_STATUS_1
[7:0]
DFORMAT_OVR_
STATUS[15:8]
Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high).
One bit for each virtual converter
0: No overrange occurred.
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits. The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
0x19B OVR_STATUS_2
[7:0]
DFORMAT_OVR_
STATUS[23:16]
Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high).
One bit for each virtual converter
0: No overrange occurred.
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits. The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
Rev. 0 | Page 70 of 93
Data Sheet
AD9083
Addr. Name
Bits
Bit Name
Description
Reset Access
0x19C OVR_STATUS_3
[7:0]
DFORMAT_OVR_
STATUS[31:24]
Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high).
One bit for each virtual converter
0: No overrange occurred.
0x0
0x0
0x0
R
R
R
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits. The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high).
One bit for each virtual converter
0: No overrange occurred.
0x19D OVR_STATUS_4
[7:0]
DFORMAT_OVR_
STATUS[39:32]
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits. The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
0x19E OVR_STATUS_5
[7:0]
DFORMAT_OVR_
STATUS[47:40]
Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high).
One bit for each virtual converter
0: No overrange occurred.
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits. The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
Rev. 0 | Page 71 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
Reset Access
0x19F OVR_STATUS_6
[7:0]
DFORMAT_OVR_
STATUS[55:48]
Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high).
One bit for each virtual converter
0: No overrange occurred.
0x0
0x0
0x0
R
R
R
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits. The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high).
One bit for each virtual converter
0: No overrange occurred.
0x1A0 OVR_STATUS_7
[7:0]
DFORMAT_OVR_
STATUS[63:56]
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits. The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
0x1A1 OVR_STATUS_8
[7:0]
DFORMAT_OVR_
STATUS[71:64]
Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high) .
One bit for each virtual converter
0: No overrange occurred.
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits . The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
Rev. 0 | Page 72 of 93
Data Sheet
AD9083
Addr. Name
Bits
Bit Name
Description
Reset Access
0x1A2 OVR_STATUS_9
[7:0]
DFORMAT_OVR_
STATUS[79:72]
Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high) .
One bit for each virtual converter
0: No overrange occurred.
0x0
0x0
0x0
R
R
R
R
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits . The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high) .
One bit for each virtual converter
0: No overrange occurred.
0x1A3 OVR_STATUS_10
[7:0]
DFORMAT_OVR_
STATUS[87:80]
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits . The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
0x1A4 OVR_STATUS_11
[7:0]
DFORMAT_OVR_
STATUS[95:88]
Output Overrange Status Indicator. Converter
overrange indication sticky bits (active high) .
One bit for each virtual converter
0: No overrange occurred.
1: Overrange occurred.
This bit is set to 1 if converter is driven beyond
the specified input range. It is sticky, meaning it
remains set until explicitly cleared by writing a 1
to the corresponding
DFORMAT_OVR_CLEAR[15:0] bits . The
corresponding DFORMAT_OVR_CLEAR[15:0] bits
must be cleared for further overflows to be
reported.
[0] = Overrange sticky bit for Converter 0
[1] = Overrange sticky bit for Converter 1
[2] = Overrange sticky bit for Converter 2
and so on.
0x1B0 DATA_PATTERN_OVERR [7:4]
IDE
RESERVED
Reserved.
0x0
0x0
[3:2]
1
RESERVED
DATA_PATTERN_OVERRIDE
Reserved.
R
R/W
This Bit Overrides the Dformat_tmode_sel[*] in 0x0
the Dformat.
0: Don't override data-pattern (Default).
1: Override data-pattern.
0
RESERVED
Reserved.
0x0
R
Rev. 0 | Page 73 of 93
AD9083
Data Sheet
Addr. Name
0x1C0 SYNC_CTRL1
Bits
[7:4]
3
Bit Name
RESERVED
NCORESET_ALL_SYSREF
Description
Reserved.
Reset Access
0x1
R
NCO Reset Control by SYSREF. Applicable only in 0x1
resynchronization mode.
R/W
0: NCO reset happens only with a SYSREF which
caused resynchronization of clocks.
1: NCO reset happens with all SYSREF pulses (not
recommended unless SYSREF period is much
greater LMFC periods).
2
1
SYSREF_RESYNC_MODE
RISEDGE_SYSREF
SYSREF Resync Mode.
0: SYSREF is not used for resync
1: SYSREF is used for resync
0x0
0x0
R/W
R/W
Risedge SYSREF.
0: No rise edge detection on SYSREF pin. Input
SYSREF used as such
1: Rise edge detection done on input SYSREF and
used.
0
[7:0]
DP_CLK_FORCEN
TRIG_PROG_DELAY
Reserved.
0x0
0x0
R/W
R/W
0x1C1 TRIG_PROG_DELAY
Programmable delay for input trig in terms of
fS/4 clock cycles.
0x1C2 SYSREF_PROG_DELAY [7:0]
SYSREF_PROG_DELAY
TRIG_EDGE_CTRL
Programmable delay for input SYSREF terms of 0x0
fS/2 clock cycles.
R/W
R/W
0x1C3 TRIG_CTRL
[7:6]
Control for Trig Edge Detection.
00: No Edge Detection.
01: Positive Edge.
10: Negative Edge.
Reserved.
0x0
[5:0]
[7:5]
4
RESERVED
RESERVED
DDC_SOFT_RESET
0x10 R/W
0x1C4 DDC_SYNC_CTRL
Reserved.
0x0
R/W
R/W
Digital Down Converter Soft Reset. Digital Down 0x0
Converter Soft Reset
0: Normal Operation
1: DDC Held in Reset.
Note: this bit can be used to synchronize all the
NCOs inside the DDC blocks.
[3:2]
1
RESERVED
Reserved.
0x0
0x1
R
DDC_SYNC_NEXT
DDC Next Synchronization Mode. DDC Next
Synchronization Mode
R/W
0: Continuous mode
1: Next Synchronization mode - only the next
valid edge of SYSREF pin will be used to
synchronize the NCO in the DDC block.
Subsequent edges of the SYSREF pin will be
ignored.
Note: The SYSREF pin must an integer multiple of
the NCO frequency in order for this function to
operate correctly in continuous mode.
0
DDC_SYNC_EN
DDC Synchronization Enable. DDC
0x0
R/W
Synchronization Enable
0: Synchronization Disabled
1: Synchronization Enabled. If DDC_SYNC_
NEXT = 1, only the next valid edge of the SYSREF
pin will be used to synchronize the NCO in the
DDC block. Subsequent edges of the SYSREF pin
are ignored. After the next SYSREF is received,
this must be cleared for any subsequent use of
next SYSREF.
Note: the SYSREF input pin must be enabled in
order to synchronize the DDCs.
Rev. 0 | Page 74 of 93
Data Sheet
AD9083
Addr. Name
0x1C5 DDC_SYNC_STATUS
Bits
[7:1]
0
Bit Name
RESERVED
DDC_SYNC_EN_CLEAR
Description
Reserved.
Reset Access
0x0
R
R
DDC Sync Enable Clear Status. DDC Sync Enable 0x0
Clear Status
JESD204B Transmitter (JTX) Control Registers
0x200 JTX_CORE_SAMPLE_
7
JTX_CONV_DISABLE
Converter sample mask to 0.
0x0
R/W
to
XBARn
0x25F
by 1
[6:0]
7
JTX_CONV_SEL
Converter sample crossbar selection.
0x0
0x0
R/W
R/W
0x260 JTX_CORE_CONFIG
JTX_SYSREF_FOR_RELINK
Will mask lane data to 0 until another SYSREF
pulse is received if SYNC~ is asserted. Applies to
JESD204B operation only.
6
JTX_SYSREF_FOR_STARTUP
Will mask lane data to 0 until the first SYSREF
pulse is received after reset.
0x0
0x0
R/W
[5:4]
3
RESERVED
Reserved.
R
JTX_CHKSUM_LSB_ALG
0: Sum whole octets of L0 config for checksum 1: 0x0
Sum individual fields for checksum.
R/W
2
[1:0]
7
JTX_CHKSUM_DISABLE
JTX_LINK_TYPE
JTX_LANE_PD
Checksum is always 0.
Link layer type selection: 0: 204B 1: 204C 2: 204H. 0x0
Physical lane in use based on link and crossbar
configuration.
0x0
R/W
R/W
R
0x261 JTX_CORE_LANE_
0x0
to
XBARn
0x264
by 1
6
5
JTX_FORCE_LANE_PD
JTX_LANE_INV
Send 0s and activate jtx_lane_pd.
Invert logical lane data (before crossbar).
Lane crossbar selection. Setting here selects
which logical lane should feed the physical lane.
0x0
0x0
0x0
R/W
R/W
R/W
[4:0]
JTX_LANE_SEL
0x271 JTX_CORE_TEST_
CONFIG
7
JTX_TEST_USER_GO
Activate USER_SINGLE test mode.
0x0
R/W
6
[5:4]
[3:0]
JTX_TEST_MIRROR
JTX_TEST_GEN_SEL
JTX_TEST_GEN_MODE
Reverse bit order of test data.
Test insertion point.
0x0
0x0
0x0
R/W
R/W
R/W
Test mode selection.
0: Disabled for TEST_GEN_SEL = 0, lane loopback
for TEST_GEN_SEL = 1.
1: CHECKER_BOARD
2: WORD_TOGGLE
3: PN31
5: PN15
7: PN7
8: RAMP
14: USER_REPEAT
15: USER_SINGLE.
0x272 JTX_TEST_USER_DATA0 [7:0]
0x273 JTX_TEST_USER_DATA1 [7:0]
0x274 JTX_TEST_USER_DATA2 [7:0]
0x275 JTX_TEST_USER_DATA3 [7:0]
0x276 JTX_TEST_USER_DATA4 [7:0]
0x277 JTX_TEST_USER_DATA5 [7:0]
0x278 JTX_TEST_USER_DATA6 [7:0]
0x279 JTX_TEST_USER_DATA7 [7:0]
0x27A JTX_TEST_USER_DATA8 [7:2]
[1:0]
JTX_TEST_USER_DATA[7:0]
User defined test data in LSBs.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
JTX_TEST_USER_DATA[15:8] User defined test data in LSBs.
JTX_TEST_USER_DATA[23:16] User defined test data in LSBs.
JTX_TEST_USER_DATA[31:24] User defined test data in LSBs.
JTX_TEST_USER_DATA[39:32] User defined test data in LSBs.
JTX_TEST_USER_DATA[47:40] User defined test data in LSBs.
JTX_TEST_USER_DATA[55:48] User defined test data in LSBs.
JTX_TEST_USER_DATA[63:56] User defined test data in LSBs.
RESERVED
Reserved.
JTX_TEST_USER_DATA[65:64] User defined test data in LSBs.
R/W
Rev. 0 | Page 75 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
Reset Access
0x27B JTX_CORE_SYNC_N_
SEL
[7:3]
RESERVED
Reserved.
0x0
R
[2:0]
JTX_SYNC_N_SEL
Decimal value to select the physical sync_n
source pin. Ignored when JTX_NUM_LINKS = 1.
0x0
R/W
0x27C JTX_CORE_13
[7:1]
0
[7:3]
RESERVED
JTX_LINK_EN
JTX_NS_CFG
Reserved.
See JTX documentation.
Number of unique samples per converter in
conv_sample.
0x0
0x0
0x0
R
R/W
R/W
0x27D JTX_TPL_CONFIG0
2
JTX_TPL_CONV_
ASYNCHRONOUS
Expect link_pclk asynchronous to conv_clk. This 0x0
will increase the delay for the domain handoff
buffer in fixed latency mode. The increased delay
may require setting the
R/W
JTX_TPL_ASYNC_SUPPORT parameter.
1
0
JTX_TPL_TEST_ENABLE
JTX_TPL_ADAPTIVE_LATENCY Enable adaptive latency mode. Default should be 0x0
0.
Enable long transport layer test.
0x0
R/W
R/W
0x27E JTX_TPL_CONFIG1
7
6
JTX_TPL_SYSREF_IGNORE_
WHEN_LINKED
JTX_TPL_SYSREF_CLR_
PHASE_ERR
Mask incoming SYSREF when SYNC~ is de-
asserted. Applies to 204B operation only.
0x0
R/W
R/W
Clear jtx_tpl_SYSREF_phase_err.
0x0
5
[4:3]
2
JTX_TPL_SYSREF_MASK
RESERVED
JTX_TPL_SYSREF_PHASE_ERR Incoming SYSREF has been registered at an
unexpected time from the previously established
SYSREF phase.
Mask any incoming SYSREF to 0.
Reserved.
0x0
0x0
0x0
R/W
R
R
1
0
JTX_TPL_SYSREF_RCVD
RESERVED
SYSREF phase has been established.
Reserved
Add additional conv_clk cycles of latency (for
both latency modes). Useful in adaptive latency
mode to get a wider adaptable range.
0x0
0x0
0x0
R
R
0x27F JTX_TPL_LATENCY_
ADJUST
[7:0]
JTX_TPL_LATENCY_ADJUST
R/W
0x280 JTX_TPL_PHASE_
ADJUST0
0x281 JTX_TPL_PHASE_
ADJUST1
0x282 JTX_TPL_TEST_NUM_
FRAMES0
0x283 JTX_TPL_TEST_NUM_
FRAMES1
[7:0]
[7:0]
[7:0]
[7:0]
[7:5]
4
JTX_TPL_PHASE_ADJUST[7:0] Output LMFC phase adjustment in conv_clk
cycles. Maximum value is k*s/ns-1.
0x0
0x0
R/W
R/W
R/W
R/W
R
JTX_TPL_PHASE_
ADJUST[15:8]
Output LMFC phase adjustment in conv_clk
cycles. Maximum value is k*s/ns-1.
JTX_TPL_TEST_NUM_
FRAMES_M1[7:0]
Number of frames (minus 1) in the long transport 0x0
layer test pattern.
JTX_TPL_TEST_NUM_
FRAMES_M1[15:8]
Number of frames (minus 1) in the long transport 0x0
layer test pattern.
0x284 JTX_TPL_SYSREF_N_
SHOT
RESERVED
Reserved.
0x0
JTX_TPL_SYSREF_N_SHOT_EN Mask all incoming SYSREF pulses except the Nth 0x0
R/W
ABLE
pulse specified by the n_shot_count. Disabling
this will cause all SYSREF pulses to be sampled
(continuous mode) and reset the n_shot counter.
[3:0]
JTX_TPL_SYSREF_N_SHOT_C Mask all incoming SYSREF pulses except the Nth 0x0
R/W
OUNT
pulse where N is the value programmed + 1.
Only used when n_shot_enable is high.
0x285 JTX_TPL_BUF_FRAMES [7:0]
JTX_TPL_BUF_FRAMES
JTX_DID_CFG
JTX_ADJCNT_CFG
Frame delay through transport layer buffer.
Device (= link) identification no.
Number of adjustment resolution steps to adjust 0x0
DAC LMFC. Applies to Subclass 2 operation only.
0x0
0x0
R
R/W
R/W
0x286 JTX_L0_DID
[7:0]
[7:4]
0x287 JTX_L0_ADJCNT_BID
[3:0]
[4:0]
JTX_BID_CFG
RESERVED
Bank ID Extension to DID.
Reserved.
0x0
0x0
R/W
R
Rev. 0 | Page 76 of 93
Data Sheet
AD9083
Addr. Name
Bits
Bit Name
Description
Reset Access
0x289 JTX_L0_SCR_L
7
JTX_SCR_CFG
JTx Scrambler
0 = Disabled
1 = Enabled
0x0
R/W
[6:5]
[4:0]
RESERVED
JTX_L_CFG
Reserved.
0x0
0x0
R
R/W
Number of lanes per converter device (link).
0 : L = 1
1 : L = 2
2 : L = 3
3 : L = 4
Values > 3 are not supported
0x28A JTX_L0_F
[7:0]
JTX_F_CFG
Number of octets per frame per lane.
F = N/16 × M × N / L.
0x0
R/W
0x28B JTX_L0_K
0x28C JTX_L0_M
[7:0]
[7:0]
JTX_K_CFG
JTX_M_CFG
Number of frames in a multi-frame/block.
Number of converters per device.
0x0
0x0
R/W
R/W
JTx number of virtual converters per link (M=JTX
M configuration + 1). 0 = 1 virtual converter 1 = 2
virtual converters 2 = 3 virtual converters 3 = 4
virtual converters 5 = 6 virtual converters 7 = 8
virtual converters 11 = 12 virtual converters 15 =
16 virtual converters All other values are invalid.
0x28D JTX_L0_CS_N
[7:6]
5
[4:0]
JTX_CS_CFG
RESERVED
JTX_N_CFG
Number of control bits per sample.
Reserved.
Converter resolution.
Device Subclass Version 2: align transmission
and LMFC boundaries to SYNC~ 1: align
0x0
0x0
0x0
0x0
R/W
R
R/W
R/W
0x28E JTX_L0_SUBCLASSV_NP [7:5]
JTX_SUBCLASSV_CFG
transmission and LMFC boundaries to SYSREF 0:
transmission and LMFC boundaries are arbitrary.
[4:0]
[7:5]
JTX_NP_CFG
JTX_JESDV_CFG
Total number of bits per sample.
JESD204 version
001: JESD204B
0x0
0x0
R/W
R/W
0x28F JTX_L0_JESDV_S
0x290 JTX_L0_HD
[4:0]
7
[6:0]
[7:0]
JTX_S_CFG
JTX_HD_CFG
RESERVED
Samples per converter per frame.
High Density format enabled.
Reserved.
0x0
0x0
0x0
0x0
R/W
R/W
R
0x293 JTX_L0_CHKSUMn
JTX_CHKSUM_CFG
Checksum calculation output (per lane).
R
to
0x296
by 1
0x297 JTX_L0_LIDn
[7:5]
RESERVED
Reserved.
0x0
R
to
0x29A
by 1
[4:0]
JTX_LID_CFG
Lane identification number (within link).
0x0
0x0
R/W
R/W
0x2A3 JTX_DL_204B_CONFIG0 [7:4]
JTX_DL_204B_ILAS_DELAY_C Delays ILAS Start by 0 to 15 LMFC Periods.
FG
3
2
JTX_DL_204B_BYP_ILAS_CFG bypass initial lane alignment sequence.
0x0
0x0
R/W
R/W
JTX_DL_204B_ILAS_TEST_
EN_CFG
Enable ilas test mode that sends repeated ILAS
pattern. If sync_n not active then 16 Kchars sent
followed by repeated ILAS.
1
0
JTX_DL_204B_BYP_8B10B_
CFG
Bypass 8-bit/10-bit encoder.
0x0
0x0
R/W
R/W
JTX_DL_204B_BYP_ACG_CFG bypass alignment character generation.
Rev. 0 | Page 77 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
Reset Access
0x2A4 JTX_DL_204B_CONFIG1 [7:3]
2
RESERVED
JTX_DL_204B_LSYNC_EN_
CFG
Reserved.
Lane sync on both sides enabled.
0x0
0x0
R
R/W
1
JTX_DL_204B_DEL_SCR_CFG Alternative scrambler enable (see JESD204B
section 5.2.4) 1 = scrambling begins at octet 2 of
user data 0 = scrambling begins at octet 0 of user
data This is the common usage.
0x0
R/W
R/W
0
JTX_DL_204B_10B_MIRROR
Reverse order of 10 bit symbols from 204B link
layer data.
0x0
0x2A5 JTX_DL_204B_CONFIG2 [7:6]
5
RESERVED
Reserved.
0x0
0x0
R
JTX_DL_204B_TESTMODE_IG ignore sync_n input during D21.5 and RPAT
NORE_SYNCN_CFG modes.
R/W
4
JTX_DL_204B_TPL_TEST_EN_ Turn on JESD Pattern Sequence test mode.
CFG
0x0
R/W
3
[2:1]
RESERVED
Reserved.
0x0
0x0
R
R/W
JTX_DL_204B_RJSPAT_SEL_C High Frequency Patterns Test Modes 11 =
FG
Unused 10 = JTSPAT Sequence 01 = JSPAT
Sequence 00 = RPAT Sequence.
0
JTX_DL_204B_RJSPAT_EN_CF Enable RPAT/JSPAT/JTSPAT Generator 1 = on
(Note: Must also set phy_data_sel[n] = 1) 0 = off.
JTX_DL_204B_KF_ILAS_CFG Number of multiframes to transmit during
initialization sequence = 4*(kf_ilas_cfg+1).
0x0
0x0
0x0
R/W
R/W
R
G
0x2A6 JTX_DL_204B_KF_ILAS [7:0]
0x2A8 JTX_DL_204B_SYNC_N
7
JTX_DL_204B_SYNC_N
JESD204 Frame Sync. Active low. Synchronous
upon rising edge pclk. 0=transmit code group
sync (K characters). Subclass 1: Internal LMFC
reset for 1-pclk by falling edge sync_n Subclass 0:
Internal lmfc held in reset by sync_n=0.
[6:2]
1
RESERVED
JTX_DL_204B_SYNC_N_
FORCE_EN
Reserved.
Force SYNC~ signal to value specified.
0x0
0x0
R
R/W
0
JTX_DL_204B_SYNC_N_
FORCE_VAL
Value to force SYNC~ if force enabled.
Reserved.
0x0
0x0
0x0
0x0
0x0
R/W
R
0x2A9 JTX_DL_204B_CLEAR_ [7:1]
SYNC_NE_COUNT
RESERVED
0
JTX_DL_204B_CLEAR_SYNC_ Clear counter of SYNC~ falling edges.
NE_COUNT
JTX_DL_204B_SYNC_NE_COU Count of falling SYNC~ edges.
NT
R/W
R
0x2AA JTX_DL_204B_SYNC_
NE_COUNT
0x2AB JTX_DL_204B_LANE_
[7:0]
[7:5]
RESERVED
Reserved.
R
to
CONFIGn
0x2AE
by 1
4
3
JTX_DL_204B_SCR_IN_CTRL_ connect test_data[39:0] to scrambler input for
0x0
0x0
R/W
R/W
CFG
lane n.
JTX_DL_204B_SCR_DATA_
SEL_CFG
Scrambler Input JESD Data on Lane Boundary
scr_data_sel_cfg [n]: 1 = Continuous D21.5 Data
for Lane [n] scr_data_sel_cfg [n]: 0 = JESD Frame
Memory or ILAS Data for Lane[n].
2
JTX_DL_204B_PHY_DATA_
SEL_CFG
JESD Data to PHY on a Lane Boundary [n]:
1 = RPAT/JSPAT/JTSPAT Generator Data [n]:
0 = 8-bit/10-bit Encoder Output Data.
Reserved.
0x0
R/W
1
0
[7:4]
RESERVED
RESERVED
0x0
0x0
0x0
R
R/W
R
Reserved
0x2C9 JTX_PHY_IFX_LANE_
JTX_LANE_FIFO_WR_ENTRIES Number of entries in the FIFO synchronized to
the write pointer.
to
CONFIGn
0x2CC
by 1
[3:0]
JTX_BR_LOG2_RATIO
Log(bit repeat ratio)/Log(2), per lane.
0x0
R/W
Rev. 0 | Page 78 of 93
Data Sheet
AD9083
Addr. Name
0x301 PLL_STATUS
Bits
7
[6:0]
7
Bit Name
JTX_PLL_LOCKED
RESERVED
SYSREF_PULSE_DELAY_
ENABLE
SYSREF_PULSE_DELAY_CYCLES Force link reset from Regmap.
FORCE_JTX_PLL_RST_
RELEASE_EN
FORCE_JTX_PLL_RST_
RELEASE
Description
PLL Locked Status Bit.
Reserved.
Reset Access
0x0
0x0
0x0
R
R
R/W
0x309 SYSREF_DELAY_REG
0x30A RESET_CTRL_REG
Force link reset from Regmap.
[6:0]
7
0x0
0x0
R/W
R/W
Enable Force JTX_PLL Reset Release.
Force JTX_PLL reset release.
Reserved.
6
0x0
R/W
5
4
RESERVED
0x0
0x0
R
R/W
FORCE_JTX_DIGITAL_RESET_ Enable SYSREF to Force link reset.
ON_SYSREF
[3:1]
0
RESERVED
Reserved.
0x0
R
R/W
FORCE_JTX_DIGITAL_RESET_ Enable Early Detection of SYSREF to Force link reset. 0x0
ON_RSTEN_FORCE_EN
0x30B SER_PARITY_RESET_EN1 [7:0]
SER_PARITY_RESET_EN
RESERVED
LCM_DIV_FORCE_EN
LCM_DIV[7:0]
parity reset enable.
Reserved.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R
0x30C LCM_DIV_FORCE_EN
[7:1]
0
LCM Divider Value Force Enable.
LCM Divider Value.
LCM Divider Value.
To select the lmfc or divided lmfc'.
Reserved.
which edge of LMFC. which edge of LMFC is used 0x0
for division before sending out of GPIO. 0for
posedge
R/W
R/W
R/W
R/W
R
0x30D LCM_DIV1
0x30E LCM_DIV2
0x30F LMFC_CTL
[7:0]
[7:0]
7
LCM_DIV[15:8]
LMFC_OUT_SEL
RESERVED
[6:5]
4
LMFC_DIV_EDGE
R/W
3
RESERVED
Reserved.
0x0
R
[2:0]
LMFC_OUT_DIV
RESERVED
FORCE_LINK_DIGITAL_RESET Force link reset from Regmap.
RESERVED
FORCE_LINK_RESET
RESERVED
Divider value before passing LMFC out of GPIO. 0x0
R/W
R
R/W
R
R/W
R
0x310 FORCE_LINK_RESET_REG [7:5]
Reserved.
0x0
0x0
0x0
0x1
0x0
4
[3:1]
0
Reserved.
Force link reset from Regmap.
Reserved.
0x313 PHASE_ESTABLISH_
STATUS
[7:1]
0
JTX_PHASE_ESTABLISHED
RESERVED
phase established readback.
Reserved.
0x0
0x0
R
R
0x315 CLKGEN_ALIGN_FALL_R [7:1]
ST_DEASSERT
0
CLKGEN_ALIGN_FALL_FOR_R To use clkgen_align for rst de-assert.
ST_DEASSERT
0x0
R/W
0x317 PLL_REF_CLK_DIV1_REG [7:4]
[3:0]
RESERVED
DIVM_JTX_PLL_RC_RX
Reserved.
0x0
0x2
R
R/W
Selects output division rate;. Selects output
division rate;
0: pd
1: no divider
2: divide by 2
3: divide by 4
0x319 PCLK_SYNC_DIV_REG1 [7:0]
0x31A PCLK_SYNC_DIV_REG2 [7:1]
0
0x31B PCLK_ASYNC_DIV_REG1 [7:0]
0x31C PCLK_ASYNC_DIV_REG2 [7:1]
0
0x31D CONV_CLK_DIV_REG1 [7:0]
0x31E CONV_CLK_DIV_REG2 [7:2]
[1:0]
PCLK_SYNC_DIV_VAL[7:0]
RESERVED
PCLK_SYNC_DIV_VAL[8]
PCLK_ASYNC_DIV_VAL[7:0]
RESERVED
PCLK_ASYNC_DIV_VAL[8]
CONV_CLK_DIV_VAL[7:0]
RESERVED
JESD Synchronous PCLK Divider Value.
Reserved.
JESD Synchronous PCLK Divider Value.
JESD Asynchronous PCLK Divider Value.
Reserved.
JESD Asynchronous PCLK Divider Value.
JESD Conv Clock Divider Value.
Reserved.
0x4
0x0
0x0
0x4
0x0
0x0
0x4
0x0
0x0
R/W
R
R/W
R/W
R
R/W
R/W
R
CONV_CLK_DIV_VAL[9:8]
JESD Conv Clock Divider Value.
R/W
Rev. 0 | Page 79 of 93
AD9083
Data Sheet
Addr. Name
0x31F JTX_CLK_CTRL_REG
Bits
[7:4]
3
2
1
0
[7:4]
3
Bit Name
RESERVED
Description
Reserved.
Reset Access
0x0
0x1
0x1
0x1
0x1
0x0
0x0
R
JTX_ASYNC_PCLK_EN
JTX_IFX_CLK_EN
JTX_CONV_CLK_EN
JTX_SYNC_PCLK_EN
RESERVED
Enable to the Async Conv Clk Divider.
Enable to the IFX Clock Divider.
Enable to the Conv Clk Divider.
Enable to the Sync PCLK Divider.
Reserved.
R/W
R/W
R/W
R/W
R
0x320 JTX_CLK_CTRL_REG2
JTX_CONV_CLK_DIV_
OVERRIDE
Override the Async Conv Clk Div Val with the
Regmap Val.
R/W
2
1
0
JTX_IFX_CLK_DIV_OVERRIDE Override the Async Conv Clk Div Val with the
Regmap Val.
0x0
0x0
0x0
R/W
R/W
R/W
JTX_SYNC_PCLK_DIV_
OVERRIDE
Override the Async Conv Clk Div Val with the
Regmap Val.
JTX_ASYNC_PCLK_DIV_
OVERRIDE
Override the Async Conv Clk DivVal with the
Regmap Val.
0x321 IFX_CLK_DIV_REG1
0x322 IFX_CLK_DIV_REG2
[7:0]
[7:1]
0
7
6
[5:4]
3
2
1
0
IFX_CLK_DIV_VAL[7:0]
RESERVED
IFX_CLK_DIV_VAL[8]
TESTMUX_CLK_SEL
TESTMUX_CLK_EN
RESERVED
JESD IFX Clock Divider Value.
Reserved.
JESD IFX Clock Divider Value.
Select Testmux_clk[0] as the asynchronous clock. 0x0
Enable Testmux_clk[0] Select.
Reserved.
0x4
0x0
0x0
R/W
R
R/W
R/W
R/W
R
0x323 ASYNC_PCLK_CTRL
0x0
0x0
0x0
0x0
0x0
0x0
0x0
ASYNC_LANE_DOUT_SEL
ASYNC_LINK_PCLK_SEL
ASYNC_LANE_CLK_SEL
ASYNC_IFX_PCLK_SEL
Select Asynchronous Lane Data.
Select Asynchronous Link PCLK.
Select Asynchronous Lane Clock.
Select Asynchronous IFX PCLK.
R/W
R/W
R/W
R/W
R/W
0x325 JTX_PCLK_DIV_
INTEGER1
[7:0]
JTX_PCLK_DIV_INTEGER[7:0] Integer Part for PCLK Divider.
0x326 JTX_PCLK_DIV_
INTEGER2
[7:1]
RESERVED
Reserved.
0x0
R
0
JTX_PCLK_DIV_INTEGER[8]
RESERVED
Integer Part for PCLK Divider.
Reserved.
0x0
0x0
R/W
R
0x327 JTX_PCLK_DIV_FRAC_ [7:5]
NUM
[4:0]
JTX_PCLK_DIV_FRAC_NUM
RESERVED
Fractional Numerator for PCLK Divider.
Reserved.
0x0
0x0
R/W
R
0x328 JTX_PCLK_DIV_FRAC_ [7:5]
DEN
[4:0]
JTX_PCLK_DIV_FRAC_DEN
JTX_IFX_PCLK_DIV_
INTEGER[7:0]
Fractional Denominator for PCLK Divider.
Integer Part for PCLK Divider.
0x0
0x0
R/W
R/W
0x329 JTX_IFX_PCLK_DIV_
INTEGER1
0x32A JTX_IFX_PCLK_DIV_
INTEGER2
[7:0]
[7:1]
0
RESERVED
Reserved.
0x0
0x0
0x0
0x0
0x0
0x0
R
JTX_IFX_PCLK_DIV_
INTEGER[8]
RESERVED
Integer Part for PCLK Divider.
Reserved.
R/W
R
0x32B JTX_IFX_PCLK_DIV_
FRAC_NUM
[7:5]
[4:0]
[7:5]
[4:0]
JTX_IFX_PCLK_DIV_FRAC_
NUM
Fractional Numerator for PCLK Divider.
Reserved.
R/W
R
0x32C JTX_IFX_PCLK_DIV_
FRAC_DEN
RESERVED
JTX_IFX_PCLK_DIV_FRAC_
DEN
Fractional Denominator for PCLK Divider.
R/W
Rev. 0 | Page 80 of 93
Data Sheet
AD9083
Addr. Name
0x402 JTX_SWING
Bits
7
[6:4]
Bit Name
RESERVED
DRVSWING_CH1_SER_RC
Description
Reserved.
SERDOUT1 output swing level.
0 = 1.00 × DVDD
Reset Access
0x0
0x1
R
R/W
1 = 0.85 × DVDD
2 = 0.75 × DVDD
3 = 0.50 × DVDD
3
[2:0]
RESERVED
DRVSWING_CH0_SER_RC
Reserved.
SERDOUT0 output swing level.
0 = 1.00 × DVDD
0x0
0x1
R
R/W
1 = 0.85 × DVDD
2 = 0.75 × DVDD
3 = 0.50 × DVDD
0x403 JTX_SWING2
7
[6:4]
RESERVED
DRVSWING_CH3_SER_RC
Reserved.
SERDOUT3 output swing level.
0 = 1.00 × DVDD
0x0
0x1
R
R/W
1 = 0.85 × DVDD
2 = 0.75 × DVDD
3 = 0.50 × DVDD
3
[2:0]
RESERVED
DRVSWING_CH2_SER_RC
Reserved.
SERDOUT2 output swing level.
0 = 1.00 × DVDD
0x0
0x1
R
R/W
1 = 0.85 × DVDD
2 = 0.75 × DVDD
3 = 0.50 × DVDD
0x40A POST_TAP_LEVEL1
7
[6:4]
RESERVED
DRVPOSTEM_CH1_SER_RC
Reserved.
Sets Post Tap Level for SERDOUT1.
0 = 0 dB.
0x0
0x0
R
R/W
1 = 3 dB.
2 = 6 dB.
3 = 9 dB.
4 = 12 dB.
5 to 7 = not applicable.
3
[2:0]
RESERVED
DRVPOSTEM_CH0_SER_RC
Reserved.
Sets Post Tap Level for SERDOUT0.
0 = 0 dB.
0x0
0x0
R
R/W
1 = 3 dB.
2 = 6 dB.
3 = 9 dB.
4 = 12 dB.
5 to 7 = not applicable.
0x40B POST_TAP_LEVEL2
7
[6:4]
RESERVED
DRVPOSTEM_CH3_SER_RC
Reserved.
Sets Post Tap Level for SERDOUT3.
0 = 0 dB.
0x0
0x0
R
R/W
1 = 3 dB.
2 = 6 dB.
3 = 9 dB.
4 = 12 dB.
5 to 7 = not applicable.
3
[2:0]
RESERVED
DRVPOSTEM_CH2_SER_RC
Reserved.
Sets Post Tap Level for SERDOUT2.
0 = 0 dB.
0x0
0x0
R
R/W
1 = 3 dB.
2 = 6 dB.
3 = 9 dB.
4 = 12 dB.
5 to 7 = not applicable.
Rev. 0 | Page 81 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
Reset Access
0x413 PRE_TAP_LEVEL_CH0
[7:0]
DRVPREEM_CH0_SER_RC
Sets Pre Tap Level for SERDOUT0.
0 = 0 dB.
1 = 3 dB.
2 = 6 dB.
3 = not applicable.
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
0x414 PRE_TAP_LEVEL_CH1
0x415 PRE_TAP_LEVEL_CH2
0x416 PRE_TAP_LEVEL_CH3
[7:0]
[7:0]
[7:0]
DRVPREEM_CH1_SER_RC
DRVPREEM_CH2_SER_RC
DRVPREEM_CH3_SER_RC
Sets Pre Tap Level for SERDOUT1.
0 = 0 dB.
1 = 3 dB.
2 = 6 dB.
3 = not applicable.
Sets Pre Tap Level for SERDOUT2.
0 = 0 dB.
1 = 3 dB.
2 = 6 dB.
3 = not applicable.
Sets Pre Tap Level for SERDOUT3.
0 = 0 dB.
1 = 3 dB.
2 = 6 dB.
3 = not applicable.
0x425 PARITY_ERROR
0x426 PARITY_ERROR2
0x427 PARITY_RST_N
[7:0]
[7:0]
[7:0]
PARITY_ERROR_SER[7:0]
PARITY_ERROR_SER[15:8]
SER_PARITY_RST_N[7:0]
JTx Parity Output Error flag, <0>=ch0, <1>=ch1 0x0
JTx Parity Output Error flag, <0>=ch0, <1>=ch1 0x0
R
R
R/W
JTx Parity Clear bit each bit is a channel. JTx
Parity Clear bit each bit is a channel ==> <3> =
chan_3, <2> = chan_2
0x0
0x428 PARITY_RST_N2
0x439 MAIN_DATA_INV
[7:0]
SER_PARITY_RST_N[15:8]
JTx Parity Clear bit each bit is a channel. JTx
Parity Clear bit each bit is a channel ==> <3> =
chan_3, <2> = chan_2
0x0
R/W
[7:4]
3
RESERVED
Reserved
0x0
0x0
R/W
R/W
OUTPUTDATAINVERT_CH3
JTx, Invert SERDOUT3 data.
0 = normal.
1 = invert.
2
1
0
OUTPUTDATAINVERT_CH2
OUTPUTDATAINVERT_CH1
OUTPUTDATAINVERT_CH0
JTx, Invert SERDOUT2 data.
0 = normal.
1 = invert.
JTx, Invert SERDOUT1 data.
0 = normal.
1 = invert.
0x0
0x0
0x0
R/W
R/W
R/W
JTx, Invert SERDOUT0 data.
0 = normal.
1 = invert.
0x447 SYNCINB_CTRL
[7:4]
3
RESERVED
PD_SYNCINB_RX_RC
Reserved.
0x0
0x1
R
R/W
SYNCINB receiver power control bit.
0 = Normal Operation
1 = Power Down
2
1
0
SYNCINB_RX_PN_INV_RC
SYNCINB Polarity control bit.
0 = Normal polarity
1 = Invert polarity
0x0
0x0
0x0
R/W
R/W
R/W
SYNCINB_RX_ONCHIP_TERM_R SYNCINB onchip termination control bit.
C
0 = Disabled (Use if 0x447[0] = 0)
1 = Enabled (100Ω differential)
SYNCINB Mode control bit.
0 = CMOS mode (Single Ended)
1 = LVDS mode (Differential)
Reserved.
SYNCINB_RX_MODE_RC
0x449 JTX_CTRL
[7:1]
0
RESERVED
0x0
0x0
R
R/W
JTAG_EN_SER_TESTMODE_RC SYNC control bit.
Rev. 0 | Page 82 of 93
Data Sheet
AD9083
Addr. Name
0x500 JTX_PLL_RST
Bits
[7:1]
0
Bit Name
RESERVED
RSTB_JTX_PLL_RC
PLL_LOCKED_BYPASS_VAL
Description
Reserved.
Force link reset from REGMAP.
Bypass value for PLL_LOCKED output when
PLL_LOCKED_BYPASS is 1. Select between PLL
lock signal and timer based lock signal
generation
Reset Access
0x0
0x0
0x0
R
R/W
R/W
0x501 PLL_ENABLE_CTRL
7
6
PLL_LOCKED_BYPASS
Bypass control for PLL_LOCKED output.
0: use state machine value
0x0
R/W
1: use PLL_LOCKED_BYPASS_VAL). Select
between PLL lock signal and timer based lock
signal generation
5
4
3
JTX_PLL_BYPASS_LOCK
RESERVED
LOLSTICKYCLEAR_FORCE_
JTX_PLL_RC
Bypass PLL lock input.
Reserved.
Clears out loss of lock bit.
0x0
0x0
0x0
R/W
R
R/W
2
1
RESERVED
Reserved.
0x0
R
R/W
LDSYNTH_FORCE_JTX_PLL_A to start calibration. A short "1" pulse starts VCO 0x0
DC
calibration, the pulse width should be at least 1
reference clock period. Allows for user to do a
calibration at will.
0
PWRUP_JTX_PLL
Power up PLL. Power up PLL, starts LDO, Starts
Calibration, sends out PLL locked when done .
"Big green button", forces power up, will not
read back correctly if PLL is powered up
internally
0x0
R/W
0x502 PLL_STATUS
[7:5]
4
RESERVED
LOSSLOCK_JTX_PLL_RS
Reserved.
0x0
0x0
R
R
PLL went out-of-lock. Bit to indicate PLL went
out-of-lock at any time between frequency
acquisitions.
3
2
RFPLLLOCK_JTX_PLL_RS
VCOCALINPROG_JTX_PLL_RS 0: when the last ALC is done (VCO cal. state
machine is in ALC_CAL_LSB state). 1: when
PLL is locked when this bit is HIGH.
0x0
0x0
R
R
init_cal_redge=1 initiated by ld_synth
1
REGULATORRDY_JTX_PLL_RS High = indicates regulator voltage is above
threshold for at least cnt conversions
0x0
R
0
[7:5]
4
JTX_PLLLOCK_JTX_PLL_RS
RESERVED
PD_TXCLK_DIST_RC
PLL is locked when this bit is high.
Reserved.
txclk dist rc. Enable output clocks to serializer1
SER
0x0
0x0
0x0
R
R
R/W
0x506 PLL_ENCAL
3
PD_RXCLK_DIST_RC
rxclk dist rc. Enable output clocks to serializer1
SER
0x0
R/W
2
1
RESERVED
EN_TX_ONLY_JTX_PLL_RC
Reserved.
Enable output clocks to serializer
0x0
0x0
R
R/W
1
SER only
0
7
6
EN_OCTAVECAL_JTX_PLL_RC Determines whether to enable PLL octave
calibration.
REFCK_DIV40BDIV120_JTX_PLL Ref clock output (1/40 or 1/120).
0x0
0x0
R/W
R/W
R/W
0x507 JTX_PLL_REF_CLK_
DIV1_REG
DIVP_JTX_PLL_RC
DIVM_JTX_PLL_RC
Selects whether B is multiplied by 6 or 8. Selects 0x0
output division rate; 0->pd, 1->no divider, 2-
>divide by 2, 3->divide by 4
Selects output division rate;. Selects output
division rate; 0->/1, 1->/2. Bit [1] is not used.
[5:4]
0x2
R/W
3
RESERVED
Reserved.
0x0
R
[2:0]
REFINDIV_JTX_PLL_RC
Sets division rate on input:. Sets division rate on 0x2
input: 0->1, 1->2, 2->4, 3->8, 4 and above div 16
R/W
Rev. 0 | Page 83 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
Reset Access
0x508 PLL_DIV2
[7:0]
B_JTX_PLL_RC
Selects PLL feedback divider. Sets integer
division rate as N=8*B, where B=5 is its minimum
value. (divb)
0x5
R/W
0x50A PLL_DIVOVD
[7:4]
3
2
RESERVED
Reserved.
0x0
0x0
0x1
0x1
0x1
0x0
R
RXDIVRATEOVD_JTX_PLL_RC Override rxdivrate.
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
REFINDIVOVD_JTX_PLL_RC
DIVMOVD_JTX_PLL_RC
BOVD_JTX_PLL_RC
RESERVED
RXDIVRATE_JTX_PLL_RC
RESERVED
VCORTRIM_JTX_PLL_RC
RESERVED
SEL_REFINDIV3_JTX_PLL_RC Enables additional /3 on input reference clock to 0x0
PLL.
Override refindiv.
1
Override divm control.
Bypass from octave cal (use b_JTX_PLL_rc).
Reserved.
When refindivovd is 1, sets value for rx_divrate. 0x8
Reserved.
0
0x50B PLL_RXDIVRATE
0x50C PLL_VCO_TRIM
0x50D PLL_REFCLK_CPL
[7:4]
[3:0]
[7:6]
[5:0]
[7:2]
1
0x0
0x0
0x0
Trim code slaved to 6-bits in the bandgap.
Reserved.
R/W
0
SEL_REFCKDCACB_JTX_PLL_RC Determines whether the reference clock input
should be DC-coupled (1) or AC coupled (0)
0x1
R/W
0x50E CBUS_REN_JTX_PLL
[7:1]
0
RESERVED
CBUS_REN_JTX_PLL_RC
RESERVED
Reserved.
Read enable for JTX_PLL registers.
Reserved.
0x0
0x0
0x0
R
R/W
R
0x50F CBUS_WSTROBE_JTX_ [7:1]
PLL
0
[7:2]
1
CBUS_WSTROBE_JTX_PLL_RC Write Strobe for JTX_PLL registers.
0x0
0x0
0x0
R/W
R
R/W
0x510 CKDIST_PD
RESERVED
Reserved.
IDIST_PD_RC
Enable output clocks to serializer.
1 : Enable
0
PD_PPF_DES_RC
Enable output clocks to serializer
1 : Enable
0x0
R/W
0x511 POLYPHASE_CTRL
[7:0]
TRIM_POLYPHASE_DES_RC
DESIGNER DEBUG: Polyphase control. DESIGNER 0x2F R/W
DEBUG: Polyphase control: <6:5>:
ppf_divm_od<1:0>, <4>: en_ppf_divm_od,
<3:1>: inv_str_od<2:0>, <0>: en_inv_str_od.
0x512 PLL_READ_FREQ4
0x513 PLL_READ_FREQ5
[7:0]
VCOFREQBAND_JTX_PLL_
RS[7:0]
VCO frequency control word that sets VCO
frequency, 00: max. VCO frequency, 7FF: min.
VCO frequency
0x0
R
[7:3]
[2:0]
RESERVED
Reserved.
0x0
0x0
R
R
VCOFREQBAND_JTX_PLL_RS[ VCO frequency control word that sets VCO
10:8]
frequency, 00: max. VCO frequency, 7FF: min.
VCO frequency
0x514 PLL_PTAT_STARTUP
0x515 PLL_PTAT_STARTUP_
STATUS1
[7:0]
[7:1]
PTAT_STARTUP_JTX_PLL_RC PTAT startup control.
RESERVED Reserved.
0x0
0x0
R/W
R
0
[7:1]
PTAT_STARTUP_STATUS_RS1 PTAT startup status.
RESERVED Reserved.
0x0
0x0
R
R
0x516 PLL_PTAT_STARTUP_
STATUS2
0
[7:1]
0
PTAT_STARTUP_STATUS_RS2 PTAT startup status.
0x0
0x0
0x0
R
R
R/W
0x517 PLL_TEMP
RESERVED
Reserved.
TDEGCINIT_JTX_PLL_RC
Low-to-High transition activates on-chip
temperature measurement.
0x51E PLL_LOCK_CTL1
[7:4]
[3:1]
0
JTX_PLL_LOCK_DIVIDER[3:0] PLL Lock counter.
0x0
0x0
0x0
R/W
R
R/W
RESERVED
Reserved.
JTX_PLL_LOCK_SEL
PLL lock and timer based lock select. Select
between PLL lock signal and timer based lock
signal generation
0x51F PLL_LOCK_CTL2
0x520 CBUS_ADDR
[7:6]
[5:0]
[7:0]
RESERVED
Reserved.
0x0
0x0
0x0
R
R/W
R/W
JTX_PLL_LOCK_DIVIDER[9:4] PLL Lock counter.
CBUS_ADDR_JTX_PLL_RC Control bus address select.
Rev. 0 | Page 84 of 93
Data Sheet
AD9083
Addr. Name
Bits
Bit Name
Description
Reset Access
0x521 CBUS_WDATA
[7:0]
CBUS_WDATA_JTX_PLL_RC
Control Bus data,. Control Bus data, channel
selected with cbus_wstrobe_ser signal
0x0
R/W
0x522 CBUS_RDATA
0x523 REFCLK_CTRL
[7:0]
CBUS_RDATA_JTX_PLL_RS
RESERVED
Read back bus, channel selected bwith
cbus_ren_ser.
0x0
R
7
[6:3]
2
Reserved.
0x0
0x0
0x0
R
R/W
R/W
SEL_REFCLK_RCVR_CM_CTRL Synca for refclk.
SEL_REFCLK_RCVR_LP_MODE Synca for refclk.
_RC
1
0
[7:0]
SEL_SYNCA_FOR_REFCLK_RC Synca for refclk.
0x0
0x1
0x0
R/W
R/W
R
EN_REFCLK_RCVR_RC
JTX_PLL_REV_ID_RS
Synca for refclk.
Read back bus, channel selected bwith
cbus_ren_ser.
0x524 JTX_PLL_REV_ID_RS
0xB90 POWER_DOWN_REG
7
EN_CAL_ANA
EN_CAL_CLK
EN_34
Enable Calibration Analog Blocks, Set to 0 for
Power-down.
Enable Calibration Clock and Digital Blocks, Set 0x0
to 0 for Power-down.
Enable Additional Two Signal Channels for 3dB 0x0
Noise Improvement.
Power down mode.
0x0
R/W
R/W
R/W
R/W
6
5
[4:3]
PIN_PD_MODE
0x0
00: power down pin disabled.
01: power down pin disables clock path only.
10: power down pin disables adc clock and vti
bias.
11: power down pin disables adc clock, vti bias
and adc masterbias block.
2
1
0
EN_BIAS
EN_ADCCLK
EN_VTI
Enable for Adc Bias Block, Set to 0 for Power-
down.
Enable Channel I Adc Clock, Set to 0 for Power- 0x0
down.
Enable Channel I Analog Front End, Set to 0 for 0x0
Power-down.
0x0
R/W
R/W
R/W
0xB91 ENABLE_CH7_0_REG
7
6
5
EN_ADC7
EN_ADC6
EN_ADC5
EN_ADC4
EN_ADC3
EN_ADC2
EN_ADC1
EN_ADC0
EN_ADC15
EN_ADC14
EN_ADC13
EN_ADC12
EN_ADC11
EN_ADC10
EN_ADC9
EN_ADC8
RESERVED
BGAIN
Enable for Channel 7 Adc Clock.
Enable for Channel 6 Adc Clock.
Enable for Channel 5 Adc Clock.
Enable for Channel 4 Adc Clock.
Enable for Channel 3 Adc Clock.
Enable for Channel 2 Adc Clock.
Enable for Channel 1 Adc Clock.
Enable for Channel 0 Adc Clock.
Enable for Channel 15 Adc Clock.
Enable for Channel 14 Adc Clock.
Enable for Channel 13 Adc Clock.
Enable for Channel 12 Adc Clock.
Enable for Channel 11 Adc Clock.
Enable for Channel 10 Adc Clock.
Enable for Channel 9 Adc Clock.
Enable for Channel 8 Adc Clock.
Reserved
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
4
3
2
1
0
7
6
0xB92 ENABLE_CH15_8_REG
5
4
3
2
1
0
0xB94 VTI_GAIN_REG
[7:6]
[5:0]
[7:6]
[5:0]
[7:0]
Bgain Adjustment.
Reserved
Bcap Adjustment.
Bdither DAC1.
R/W
R
R/W
R/W
0xB95 VTI_LPF_CAP_REG
RESERVED
BCAP
BDITHDAC1
0xB99 DITHER_DAC_
CURRENT1_REG
0xB9A DITHER_DAC_
CURRENT2_REG
[7:0]
BDITHDAC2
Bdither DAC2.
0x0
R/W
Rev. 0 | Page 85 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
Reset Access
0xBA2 VTI_SHIFT_CURRENT_
MSB_REG
7
SPARE_REG_12_7
(vti_force_cm): 0 = vti normal mode, 1= vti input 0x0
common-mode is forced by input.
R/W
R/W
R/W
6
SPARE_REG_12_6
RTERM
(vti_high_imp): 0 = vti normal mode, 1= vti
input common-mode is high impedance.
0x0
[5:4]
Termination Resistance.
00: Open.
0x0
01: 200 Ohm.
10: 100 Ohm.
[3:0]
7
RESERVED
ENABLE_CLOCK
RESERVED
KGAIN_VAL[7:0]
KGAIN_VAL[15:8]
RESERVED
KGAIN_VAL[21:16]
BCENTER_OFFSET
RESERVED[9:8]
DIVM_RC
Reserved.
Clock Enable for the VCO ADC Digital.
Reserved.
floor(kgain) – (2^8)*Kgain1 – (2^16)*Kgain2
floor(kgain/2^8) – (2^8)*Kgain2
Reserved.
floor(kgain/2^16)
Offset Value for Bcenter.
Reserved.
Wait Time for C Measurement. Valid range is 125- 0x0
255. This multiplied by the fs/8 clock period
determines the time between falling edge of
C_RESET to falling edge of C_CLK for C ramp.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R
0xBB3 CAL_EN
[6:0]
[7:0]
[7:0]
[7:6]
[5:0]
[7:2]
[1:0]
[7:0]
0xBBA KGAIN_VAL0
0xBBB KGAIN_VAL1
0xBBC KGAIN_VAL2
0xBC3 BCENTER_1
0xBC8 DIVM_RC
R/W
Temperature Diode Control Registers
0xC01 TRM_TEMP_DIODE
[7:0]
TRM_TEMP_DIODE
0x0
R/W
00: Default.
11: Temp sensor: Enable sense 1x and 20x diode
voltages.
0xC04 TOP_REF_MONITOR
[7:4]
[3:2]
RESERVED
SPI_SEL_MON_TEMP
Reserved.
0x0
0x0
R
R/W
00: Default.
01: Temp Sensor: measure 1x diode (also set
trm_temp_diode[7:0] = 3).
10: Temp sensor: measure 20x diode (also set
trm_temp_diode[7:0] = 3).
11: Temp sensor: measure GND.
Reserved.
[1:0]
RESERVED
0x0
R/W
On-Chip PLL Configuration Registers
0xD02 RESET_REG
[7:2]
RESERVED
Reserved.
0x0
0x0
R
1
D_CAL_RESET
Resets Vco Calibration. Rising edge starts VCO
momcap calibration.
R/W
0
[7:2]
[1:0]
RESERVED
RESERVED
D_REFIN_DIV
Reserved.
Reserved.
0x0
0x4
0x0
R/W
R
0xD03 INPUT_MISC_REG
Programmable Predivider Value (1,2,3,4) (Also
called /R in some documentation).
R/W
00: /1.
01: /2.
10: /3.
11: /4.
0xD04 CHARGEPUMP_REG_0 [7:6]
[5:0]
RESERVED
Reserved.
0x0
R/W
D_CP_CURRENT
RESERVED
D_DIVIDE_CONTROL
Charge Pump Current
Reserved.
Programmable Divide by N Value (2-50)
0x13 R/W
0x0
0x6
0xD09 DIVIDER_REG
[7:6]
[5:0]
R/W
R/W
Rev. 0 | Page 86 of 93
Data Sheet
AD9083
Addr. Name
0xD0C VCO_CAL_LOCK_REG
Bits
[7:6]
[5:4]
Bit Name
RESERVED
D_CONTROL_HS_FB_DIV
Description
Reserved.
Hs Feedback Divider (/P)
00: /5.
Reset Access
0x0
0x2
R
R/W
01: /7.
10: /8.
11: /11.
[3:0]
[7:6]
[5:0]
RESERVED
RESERVED
D_FILT_CBIG
Reserved.
Reserved.
0x6
0x0
0x20 R/W
R
R
0xD21 FILT_MAIN_0
0xD22 FILT_MAIN_1
the large capacitor in filter: .5pF + 9.5pF*N
(0<N<63).
the resistor control for filter: nonlinear. R = 31k 0xFA R/W
ohm/(1+!<0>+2*!<1>+4*!<2>+8*!<3>+16*!<4>
+32*!<5>+64*!<6>+128*!<7>, or Resistor_code
= 256 - 31k/R (123 < R <31k).
[7:0]
D_FILT_R
0xD23 FILT_MAIN_2
0xD40 CLOCK_PD
[7:6]
[5:0]
RESERVED
D_FILT_CSMALL
Reserved.
0x0
0x22 R/W
R
the small capacitor in filter. .83pF+.87pF*M
(0<M<63).
[7:4]
3
[2:0]
RESERVED
SPI_PLL_BYP
RESERVED
RESERVED
Reserved.
Bypass On-chip PLL.
Reserved.
0x0
0x0
0x0
0x0
R
R/W
R/W
R
0xD41 CLOCK_DIVIDER_CNTR [7:5]
L
Reserved.
[4:3]
SPI_CNTRL_HS_DIV
Select Divider for Vco Outputs.
0x0
R/W
00: /6.
01: /8.
10: /10.
11: Not supported.
Reserved.
Reserved.
[2:0]
[7:5]
RESERVED
RESERVED
0x7
0x0
R/W
R
0xD44 Clock_PLL_READY_
CNTRL
4
3
2
SPI_OUTOFLOCK_RST
SPI_LOCK_VALID_RST
PLL_OUTOFLOCK
Reset F/F for Slow Lock Coming Out of Lock.
Reset F/F for Slow Lock Valid Signal.
1: Lock Slow Transitioned Low (PLL Out of Lock); 0x0
Once the PLL is in lock, if the PLL goes out of
lock (output "pll_lock_slow" transitions low),
pll_outoflock will transition high and stay high
until spi_outoflock_rst is set high then low.
0x0
0x0
R/W
R/W
R
1
PLL_LOCK_VALID
1: Lock Slow Transitioned High (PLL in Lock);
Once the PLL achieves lock (output
0x0
R
"pll_lock_slow" transitions high), pll_lock_valid
will transition high and stay high until
spi_lock_valid_rst is set high then low.
0
[7:6]
[5:0]
RESERVED
RESERVED
SPI_DIV_JTX_PLL
Reserved.
Reserved.
Adjust Divider for Refclk to JTX_PLL.
00000: NC.
0x0
0x0
0x2
R
R
R/W
0xD4A JTX_PLL_REFCLK_DIV
00001: NC.
00010: /2.
00011: /3.
00100: /4.
00101: /5.
00110: /6.
00111: /7.
01000: /8.
01001: /9.
Rev. 0 | Page 87 of 93
AD9083
Data Sheet
Addr. Name
Bits
Bit Name
Description
01010: /10.
01011: /11.
01100: /12.
01101: /13.
01110: /14.
01111: /15.
10000: /16.
10001: /17.
10010: /18.
10011: /19.
10100: /20.
10101: /21.
10110: /22.
10111: /23.
11000: /24.
11001: /25.
11010: /26.
11011: /27.
11100: /28.
11101: /29.
11110: /30.
11111: /31.
Reserved.
Reset Access
0xD4D SYSREF_IGNORE
7
6
RESERVED
0x0
R
SPI_SYSREF_IGNORE_START Start ignoring sysrefs. This bit will self clear once 0x0
count expires. The first posedge of sysref after
R/W
the start is passed through, thereafter they are
masked until ignore count expires. The bit will
self-clear once masking is over.
5
SPI_SYSREF_IGNORE_ENABLE Master enable for sysref_ignore block. This also 0x0
R/W
R/W
R/W
acts as a clock gating signal for the FFs in the
block.
[4:1]
0
SPI_SYSREF_IGNORE_COUNT Number of sysrefs to ignore. Value to be
programmed is N-1, e.g. 0 will ignore 1 sysref,
0xF will ignore 16 sysrefs.
0x0
0x0
SPI_SYSREF_DISABLE
Master disable for sysref, asynchronous – can
affect duty cycle of sysref edge closest to bit
transition.
G/H Sync Mode Control Registers
0xE20 TRIGGER_DELAY_VAL_0 [7:0]
TRIGGER_DELAY
Delay in Trigger Pulse in terms of cic_clk cycles. 0x0
This delay is a common delay for all path.
R/W
R
0xE21 TRIGGER_DELAY_VAL_1 [7:0]
I_TRIGGER_DELAY
Hardware computed value of Delay in Trigger
Pulse in terms of cic_clk cycles. This delay is a
common delay for all path.
0x0
0xE24 G_H_SYNC_MODE_VAL [7:5]
4
RESERVED
TRIG_NCO_RESET_EN
Reserved.
0x0
R
R/W
Enable/Disable for NCO Reset Based on G/H Trig. 0x0
1-Enables periodic reset of NCO based on G/H
Trig. Upon the arrival of G/H Trig NCO resets are
periodically generated at the period of "H".
0-Disables NCO reset based on G/H Trig.
3
2
RESERVED
DELAY_AUTO_INCR
Reserved.
0x0
R
R/W
Auto Increment Trigger Delay after each trigger 0x0
out for calibration purpose.
Rev. 0 | Page 88 of 93
Data Sheet
AD9083
Addr. Name
Bits
Bit Name
Description
Reset Access
[1:0]
G_H_SYNC_MODE
Mode Selection for G H Sync.
00: Sysref Based Synchronization.
0x0
R/W
01: Trigger Based Synchronization with exclusive
trigger.
10: Trigger Based Synchronization with sysref
repurposed.
11: Direct Pulse Mode.
Reserved.
0xE25 G_H_SYNC_SYSREF_
FUNC_VAL
[7:1]
0
RESERVED
0x0
0x0
0xE
R
SYSREF_FUNC
AVERAGER_DELAY
Flag for Sysref Function for Mode 2 with sysref
repurposed.
Moving Averager Strobe Delay in terms of
number of clock cycles of cic_clk. Indicates the
amount of delay to be incurred on the strobe for
moving averager.
R/W
R/W
0xE26 TRIG_AVG_DELAY_VAL [7:0]
Strobe is initiated by G/H trig, and this register
indicates the amount of delay on that strobe.
0xE27 TRIG_AVG_DELAY_G_V [7:0]
AL
0xE28 TRIG_NCO_DELAY_VAL [7:0]
AVERAGER_G_DELAY
NCO_DELAY
Moving Averager Strobe Delay to account for G 0x0
value in terms of cic_clk cycles.
R/W
R/W
NCO Strobe/Reset Delay in terms of cic_clk
cycles. Indicates the amount of delay to be
incurred on the strobe/Reset for NCO.
Strobe is initiated by G/H trig, and this register
indicates the amount of delay on that strobe for
NCO.
0x0
0xE30 TRIG_DELAY_OVERWRI [7:4]
TE
RESERVED
Reserved.
0x0
0x0
0x0
0x0
0x0
R
3
2
1
0
OVERWRITE_TRIGGER_DELAY 1: Overwrite the TRIGGER delay 0 : Don't
overwrite the delay value.
R/W
R/W
R/W
R/W
OVERWRITE_NCO_DELAY
1: Overwrite the NCO delay 0 : Don't overwrite
the delay value.
1: Overwrite the Averager delay 0 : Don't
overwrite the delay value.
1: Overwrite the Averager G delay 0 : Don't
overwrite the delay value.
OVERWRITE_AVERAGER_
DELAY
OVERWRITE_AVERAGER_G_
DELAY
Rev. 0 | Page 89 of 93
AD9083
Data Sheet
APPLICATIONS INFORMATION
EVALUATION BOARD INFORMATION
LTM8074
VOUT
5V TO 40V
1.0V
DVDD
AVDD
For information regarding the AD9083 evaluation board, visit
https://wiki.analog.com/resources/eval/ad9083.
AVDD1P8
POWER DELIVERY NETWORK
The power supplies needed to power the AD9083 are shown in
Table 31.
LTM8074
VOUT
1.8V
DVDD1P8
Table 31. Typical Power Supplies for AD9083
Figure 93. Simplified Power Solution for the AD9083
Domain
Voltage (V)
Tolerance (%)
The user can employ several different decoupling capacitors to
cover both high and low frequencies. These capacitors must be
located close to the point of entry at the PCB level and close to
the devices, with minimal trace lengths.
AVDD
AVDD1P8
DVDD
1.0
1.8
1.0
1.8
5
5
5
5
DVDD1P8
LAYOUT GUIDELINES
The evaluation board uses the power delivery network shown
in Figure 93. Ferrite beads are used to isolate each of the supply
domains. The ferrite beads are sized to limit the IR drop across
it such that the 5% regulation specification can still be
maintained. The DVDD supply does not use a ferrite due to its
high current draw.
The ADC evaluation board can be used as a guide to follow
good layout practices. The evaluation board layout is done in
such a way as to
•
•
•
Minimize coupling between the analog inputs.
Minimize clock coupling to the analog inputs.
Provide enough power and ground planes for the various
supply domains while reducing cross coupling.
Provide adequate thermal relief to the ADC.
The AD9083 can be driven directly from the dc-to-dc
converter. Note that this approach has risks in that more power
supply noise could be injected into the power supply domains
of the ADC. To minimize noise, follow the layout guidelines of
the dc-to-dc converter.
•
Figure 94 shows the overall layout scheme used for the AD9083
evaluation board.
Rev. 0 | Page 90 of 93
Data Sheet
AD9083
Figure 94. AD9083EBZ Layout Showing AVDD Plane (Layer 3)
Figure 95. AD9083EBZ Layout Showing AVDD1P8 Plane (Layer 4)
Rev. 0 | Page 91 of 93
AD9083
Data Sheet
Figure 96. AD9083EBZ Layout Showing DVDD and DVDD1P8 Planes (Layer 6)
Rev. 0 | Page 92 of 93
Data Sheet
AD9083
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
A1 BALL
CORNER
A1 BALL
INDICATORꢀ
AREA
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
7.20 REF
SQ
G
H
J
0.80
BSC
K
0.90
BSC
TOP VIEW
BOTTOM VIEW
1.076
1.006
0.946
DETAIL A
DETAIL A
1.400
1.346
1.236
0.34 NOM
0.29 MIN
SIDE VIEW
0.53
0.48
0.43
SEATING
PLANE
COPLANARITY
0.12
Ø
Figure 97. 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-100-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range2
Package Description
Package Option
AD9083BBCZ
AD9083BBCZ-RL7
AD9083EBZ
−40°C to +115°C
−40°C to +115°C
100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation board for AD9083
BC–100–8
BC–100–8
1 Z = RoHS Compliant Part
2 Specified TJ start-up at TJ = 40°C is guaranteed.
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registered trademarks are the property of their respective owners.
D22923-1/21(0)
Rev. 0 | Page 93 of 93
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