AD9101 [ADI]
125 MSPS Monolithic Sampling Amplifier; 125 MSPS单芯片采样放大器
| 型号： | AD9101 |
| 厂家： | 
ADI |
| 描述： | 125 MSPS Monolithic Sampling Amplifier |
| 文件： | 总12页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
125 MSPS Monolithic
Sampling Amplifier
a
AD9101
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
350 MHz Sam pling Bandw idth
125 MHz Sam pling Rate
Excellent Hold Mode Distortion
AD9101
–75 dB @ 50 MSPS (25 MHz VIN
)
–
–57 dB @ 125 MSPS (50 MHz VIN
7 ns Acquisition Tim e to 0.1%
<1 ps Aperture J itter
)
SAMPLER
+
4X
AMP
C
V
HOLD
V
IN
+
OUT
–
66 dB Feedthrough Rejection @ 50 MHz
3.3 nV/ √Hz Spectral Noise Density
3R
APPLICATIONS
R
Direct IF Sam pling
Digital Sam pling Oscilloscopes
HDTV Cam eras
RTN
CLOCK CLOCK
Peak Detectors
Radar/ EW/ ECM
Spectrum Analysis
Test Equipm ent/ CCD Testers
DDS DAC Deglitcher
T he benefits of using a track-and-hold ahead of a flash converter
have been well known for many years. However, before the
AD9101, there was no track-and-hold amplifier with sufficient
bandwidth and linearity to markedly increase the dynamic per-
formance of such flashes as the AD9002, AD9012, AD9020,
and AD9060.
GENERAL D ESCRIP TIO N
T he AD9101 is an extremely accurate, general purpose, high
speed sampling amplifier. Its fast and accurate acquisition speed
allows for a wide range of frequency vs. resolution performance.
T he AD9101 is capable of 8 to 12 bits of accuracy at clock rates
of 125 MSPS or 50 MSPS, respectively. T his level of perfor-
mance makes it an ideal driver for almost all 8- to 12-bit A/D
encoders on the market today.
A new application made possible by the AD9101 is direct IF-
to-digital conversion. Utilizing the Nyquist principle, the IF
frequency can be rejected, and the baseband signal can be
recovered. As an example, a 40 MH z IF is modulated by a
10 MHz bandwidth signal. By sampling at 25 MSPS, the signal
of interest is detected.
In effect, the AD9101 is a track-and-hold with a post amplifier.
T his configuration allows the front end sampler to operate at
relatively low signal amplitudes. T his results in dramatic im-
provement in both track and hold mode distortion while keeping
power low.
T he AD9101 is offered in commercial and military temperature
ranges. Commercial versions include the AD9101AR in plastic
SOIC and AD9101AE in ceramic LCC. Military devices are
available in ceramic LCC. Contact the factory for availability of
versions in DIP and/or military versions.
T he gain-of-four output amplifier has been optimized for fast
and accurate large signal step settling characteristics even when
heavily loaded. T his amplifier’s fast Settling T ime Linearity
(ST L) characteristic causes the amplifier to be transparent to
the low signal level distortion of the sampler. When sampled,
output distortion levels reflect only the distortion performance
of the sampler.
P RO D UCT H IGH LIGH TS
1. Guaranteed Hold-Mode Distortion
2. 125 MHz Sampling Rate to 8 Bits; 50 MHz to 12 Bits
3. 350 MHz Sampling Bandwidth
4. Super-Nyquist Sampling Capability
5. Output Offset Adjustable
Dramatic SNR and distortion improvements can be realized
when using the AD9101 with high speed flash converters. Flash
converters generally have excellent linearity at dc and low fre-
quencies. However, as signal slew rate increases, their perfor-
mance degrades due to the internal comparators’ aperture delay
variations and finite gain bandwidth product.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD9101–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+V = +5 V, –V = –5.2 V, RLOAD = 100 ⍀, R = 50 ⍀ unless otherwise noted)
S
S
lN
Test
Level
AD 9101
Typ
P aram eter
Conditions
Tem p
Min
Max
Units
DC ACCURACY
Gain
∆VIN = 0.5 V
∆VIN = 0.5 V
VIN = 0 V
25°C
Full
25°C
Full
25°C
Full
25°C
Full
Full
I
VI
I
VI
V
VI
VI
V
V
3.93
3.9
4
4.07
4.1
±10
±15
V/V
V/V
mV
mV
Ω
mA
dB
mV/V
mV/V
Offset
±3
VIN = 0 V
Output Resistance
Output Drive Capability
PSRR
Pedestal Sensitivity to Positive Supply
Pedestal Sensitivity to Negative Supply
0.4
±70
43
4
±60
37
∆VS = 0.5 V p-p
∆VS = 0.5 V p-p
∆VS = 0.5 V p-p
8
ANALOG INPUT /OUT PUT
Output Voltage Range
Input Bias Current
Full
25°C
Full
25°C
25°C–T MAX
T MIN
VI
I
VI
V
VI
VI
±2.4
±2.7
±5
V
±15
±20
µA
µA
pF
kΩ
kΩ
Input Capacitance
Input Resistance
2
125
30
25
CLOCK/CLOCK INPUT S
Input Bias Current
CL/CL = –1.0 V
VIN = 0.5 V p-p
VIN = 0.5 V p-p
Full
Full
Full
VI
VI
VI
3
3.6
–1.5
–0.8
mA
V
V
Input Low Voltage (VIL)1
–1.8
–1.0
1
Input High Voltage (VIH
)
T RACK MODE DYNAMICS
Bandwidth (–3 dB)
VOUT = 1 V p-p
Full
IV
IV
V
V
V
160
1300
250
1800
55
210
3.3
MHz
V/µs
ns
µV
µV/√Hz
Slew Rate
4 Volt Output Step Full
VIN = ±1 V to 0 V 25°C
(5 MHz–200 MHz) 25°C
25°C
Overdrive Recovery T ime2 (to 0.1%)
Integrated Output Noise
Input RMS Spectral Noise @ 10 MHz
HOLD MODE DYNAMICS
Worst Harmonic (23 MHz, 50 MSPS)
VOUT = 2 V p-p
25°C
25°C
Full (Ind.)
Full (Mil.)
25°C
25°C
Full
25°C
Full
V
–75
–62
dBFS
dBFS
dBFS
dBFS
dBFS
MHz
mV/s
mV/µs
mV/µs
dB
Worst Harmonic (48 MHz, 100 MSPS) VOUT = 2 V p-p
Worst Harmonic (48 MHz, 100 MSPS) VOUT = 2 V p-p
Worst Harmonic (48 MHz, 100 MSPS) VOUT = 2 V p-p
Worst Harmonic (48 MHz, 125 MSPS) VOUT = 2 V p-p
IV
IV
IV
V
V
V
I
VI
V
–57
–53
–51
–57
350
150 × tH
±5
Sampling Bandwidth (–3 dB)3
Hold Noise4 (RMS)
Droop Rate
VIN = 0.5 V p-p
±18
±40
Feedthrough Rejection (50 MHz)
VOUT = 2 V p-p
Full
–66
T RACK-T O-HOLD SWIT CHING
Aperture Delay
Aperture Jitter
25°C
25°C
25°C
Full
Full
Full
V
V
I
VI
V
V
V
–250
<1
±5
ps
ps rms
mV
mV
mV
ns
Pedestal Offset
VIN = 0 V
VIN = 0 V
VIN = 0 V
VIN = 0 V
VIN = 0 V
±20
±35
T ransient Amplitude
Settling T ime to 4 mV
Glitch Product5
8
4
20
25°C
pV-s
HOLD-T O-T RACK SWIT CHING
Acquisition T ime to 0.1%
Acquisition T ime to 0.01%
2 V Output Step
2 V Output Step
2 V Output Step
25°C
25°C
Full
V
IV
IV
7
11
ns
ns
ns
14
16
POWER SUPPLY
+VS Current
–VS Current
Full
Full
Full
VI
VI
VI
55
59
570
70
73
715
mA
mA
mW
Power Dissipation
–2–
REV. 0
AD9101
NOT ES
1If the analog input exceeds ±300 mV, the clock levels should be shifted as shown in the T heory of Operation section entitled “Driving the Encode Clock.”
2T ime to recover within rated error band from 160% overdrive.
3Sampling bandwidth is defined as the –3 dB frequency response of the input sampler to the hold capacitor when operating in the sampling mode. It is greater than
tracking bandwidth because it does not include the bandwidth of the output amplifier.
4Hold mode noise is proportional to the length of time a signal is held. For example, if the hold time (t H ) is 20 ns, the accumulated noise is typically 3 µV
(150 mV/s × 20 ns). T his value must be combined with the track mode noise to obtain total noise.
5T otal energy of worst case track-to-hold or hold-to-track glitch.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS1
P in D escr iption
Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . –0.5 V to +6 V
P in
D escription
Connection
Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . –6 V to +0.5 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 V
CLOCK/CLOCK Input . . . . . . . . . . . . . . . . . –5 V to +0.5 V
Continuous Output Current4 . . . . . . . . . . . . . . . . . . . . 70 mA
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating T emperature Range
AE, AR . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Junction T emperature (Ceramic)2 . . . . . . . . . . . . . . . +175°C
Junction T emperature (Plastic)2 . . . . . . . . . . . . . . . . +150°C
Soldering T emperature (1 minute)3 . . . . . . . . . . . . . . +220°C
1
2
3
4
5
6
7
8
RT N
RT N
CB+
Gain Set Resistor Return*
Gain Set Resistor Return*
Bootstrap Capacitor (Positive Bias)
+5 V Power Supply (Analog)
+5 V Power Supply (Analog)
Hold Capacitor Ground
+VS
+VS
GND
GND
+VS
+VS
CLK
CLK
–VS
–VS
N/C
VIN
GND
–VS
–VS
Hold Capacitor Ground
+5 V Power Supply (Digital)
+5 V Power Supply (Digital)
T rue ECL T /H Clock
Complement ECL T /H Clock
–5.2 V Power Supply (Digital)
–5.2 V Power Supply (Digital)
No Connection
Analog Signal Input
Ground (Signal Return)
–5.2 V Power Supply (Analog)
–5.2 V Power Supply (Analog)
Bootstrap Capacitor (Negative Bias)
Analog Signal Output
9
10
11
12
13
14
15
16
17
18
19
20
NOT ES
1Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2T ypical thermal impedances (no air flow, soldered to PC board) are as follows:
Ceramic LCC: θJA = 48°C/W; θJC = 9.9°C/W; Plastic SOIC: θJA = 54°C/W;
θJC = 7.3°C/W.
3For surface mount devices, mounted by vapor phase soldering. Prior to vapor phase
soldering, plastic units should receive a minimum eight hour bakeout at 110 °C to
drive off any moisture absorbed in plastic during shipping or storage. T hrough-hole
devices can be soldered at +300°C for 10 seconds.
CB–
VOUT
4Output is short circuit protected to ground. Continuous short circuit may affect
device reliability.
*See “Matching the AD9101 to A/D Encoders.” Both pins should either be
grounded or connected to voltage source for offset.
EXP LANATIO N O F TEST LEVELS
Test Level
P IN CO NFIGURATIO NS
I
– 100% production tested.
20-P in SO IC
20-Contact Cer am ic LCC
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Periodically sample tested.
IV – Parameter is guaranteed by design and characterization
testing.
1
2
3
20 VOUT
RTN
CB–
19
19
20
1
2
3
RTN
CB+
–V
–V
+V
+V
18
17
16
15
14
4
5
6
7
8
V
– Parameter is a typical value only.
S
S
–VS
18
VI – All devices are 100% production tested at +25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
S
S
–VS
17
+VS
+VS
4
5
BOTTOM VIEW
GND
GND
GND
AD9101
V
GND
16
IN
TOP VIEW
+V
S
NC
(Not to Scale)
GND
15
6
VIN
13
10 9
12 11
7
GND
+VS
+VS
14
13
12
NC
O RD ERING INFO RMATIO N
–VS
8
Tem perature
Range
P ackage
D escription
P ackage
O ption
–VS
9
Model
10
CLK
11
CLK
AD9101AR
AD9101AE
AD9101SE
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
Plastic SOIC
LCC
LCC
R-20
E-20A
E-20A
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9101 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–3–
REV. 0
AD9101
H old-to-Tr ack Switch D elay is the time delay from the track
command to the point when the output starts to change to ac-
quire a new signal level.
Acquisition Tim e is the amount of time it takes the AD9101
to reacquire the analog input when switching from hold to track
mode. T he interval starts at the 50% clock transition point and
ends when the input signal is reacquired to within a specified
error band at the hold capacitor.
P edestal O ffset is the offset voltage measured immediately af-
ter the AD9101 is switched from track to hold with the input
held at zero volts. It manifests itself as a dc offset during the
hold time.
Aper tur e D elay establishes when the input signal is actually
sampled. It is the time difference between the analog propaga-
tion delay of the front-end buffer and the control switch delay
time (the time from the hold command transition to when the
switch is opened). For the AD9101, this is a negative value,
meaning that the analog delay is longer than the switch delay.
Sam pling Bandwidth is the –3 dB frequency response from
the input to the hold capacitor under sampling conditions. It is
greater than the tracking bandwidth because it does not include
the bandwidth of the output amplifier which is optimized for
settling time rather than bandwidth.
Aper tur e Jitter is the random variation in the aperture delay.
T his is measured in ps-rms and is manifested as phase noise on
the held signal.
Tr ack-to-H old Settling Tim e is the time necessary for the
track to hold switching transient to settle to within 4 mV of its
final value.
D r oop Rate is the change in output voltage as a function of
time (dV/dt). It is measured at the AD9101 output with the de-
vice in hold mode and the input held at a specified dc value; the
measurement starts immediately after the T /H switches from
track to hold.
Tr ack-to-H old Switching Tr ansient is the maximum peak
switch induced transient voltage which appears at the AD9101
output when it is switched from track to hold.
Feedthr ough Rejection is the ratio of the output signal to the
input signal when in hold mode. T his is a measure of how well
the switch isolates the input signal from feeding through to the
output.
APERTURE
DELAY
(–0.25 ns)
+2V
VOLTAGE
LEVEL HELD
ANALOG
0V
INPUT (x 4)
ACQUISITION
TIME (SEE
TEXT)
-2V
+2V
HOLD TO TRACK
OBSERVED AT
SWITCH DELAY
TIME (1.5 ns)
HOLD CAPACITOR
OBSERVED AT
AMPLIFIER OUTPUT
SAMPLER OUTPUT SIGNAL (x 4)
0V
AND AMPLIFIER OUTPUT SIGNAL
TRACK TO
HOLD
SETTLING
(4 ns)
-2V
"1"
CLOCK
CLOCK
"HOLD"
CLOCK
"HOLD"
"TRACK"
CLOCK
INPUTS
"0"
Tim ing Diagram (500 ps/div)
REV. 0
–4–
AD9101
TH EO RY O F O P ERATIO N
V
HC
V
T he AD9101 employs a new and unique track-and-hold archi-
tecture. Previous commercially available high speed track-and-
holds used an open loop input buffer, followed by a diode
bridge, hold capacitor, and output buffer (closed or open loop)
with a FET device usually connected to the hold capacitor. T his
architecture required mixed device technology and, usually, hy-
brid construction. T he sampling rate of these hybrids has been
limited to 20 MSPS for 12-bit accuracy. Distortion generated in
the front-end amplifier/bridge limited the dynamic range perfor-
mance to the “mid –70 dBFS” for analog input signals of less
than 10 MHz. Broadband and switch-generated noise limited
the SNR of previous track-and-holds to about 70 dB.
OUT
AMP
SAMPLER
HC
TRACK-TO-HOLD
INDUCED GLITCH
V
HC
V
OUT
ACQUISITION TIME
AT HC TO X%
t
DHT
1.5ns
T he AD9101 is a monolithic device using a high frequency
complementary bipolar process to achieve new levels of high
speed precision. Its architecture completely breaks from the tra-
ditional architecture described above. T he hold switch has been
integrated into the first stage closed-loop buffer. T his innova-
tion provides error (distortion) correction for both the switch
and buffer while still achieving slew rates representative of an
open-loop design. In addition, acquisition slew current for the
hold capacitor is higher than the traditional diode bridge switch
configurations, removing a main contributor to the limits of
maximum sampling rate, input frequency, and distortion.
TS
TRACK
HOLD
Figure 1. Acquisition Tim e at Hold Capacitor
during the track time. However, since the output amplifier al-
ways “tracks” the front end circuitry, it “catches up” and di-
rectly superimposes itself (less about 500 ps of analog delay) to
V
HC. Since the small signal settling time of the output amplifier
can be about 1.2 ns to ±1 mV, and is significantly less than the
hold time, acquisition time should be referenced to the hold
capacitor.
T he closed-loop output amplifier includes zero voltage bias cur-
rent cancellation, which results in high-temperature droop rates
close to those found in FET type inputs. T his closed-loop am-
plifier inherently provides high speed loop correction and has
extremely low distortion even when heavily loaded.
Most of the hold settling time and output acquisition time are
due to the sampler and the switch network. (Output acquisition
time is as seen on a scope at the output. T his is typically 1.7 ns
longer than actual acquisition time.) For track time, the output
amplifier contributes only about 5 ns of the total; in hold mode,
it contributes 1.7 ns (as stated above).
Extremely fast time constant linearity (7 ns to 0.01% for a 4 V
output step) ensures that the output amplifier does not limit the
AD9101 sampling rate or analog input frequency. (T he acquisi-
tion and settling time are primarily limited only by the input
sampler.) T he output is transparent to the overall AD9101 hold
mode distortion levels for loads as low as 50 Ω.
A stricter definition of acquisition would actually include both
the acquisition and track-to-hold settling times to a defined ac-
curacy. T o obtain 12-bit+ distortion levels and 50 MSPS opera-
tion, the minimum recommended track and hold times are
12 ns and 8 ns, respectively. T o drive an 8-bit flash converter
(such as the AD9002) with a 2 V p-p full-scale input, hold time
to 1 LSB accuracy will be limited primarily by the aperture time
of the encoder, rather than by the AD9101. T his makes it pos-
sible to reduce track time to as little as 5 ns, with hold time cho-
sen to optimize the encoder’s performance.
Full-scale track and acquisition slew rates achieved by the
AD9101 are 1800 V/µs and 1700 V/µs, respectively. When com-
bined with excellent phase margin (typically 5% overshoot),
wide bandwidth, and dc gain accuracy, acquisition time to
0.01% is only 11 ns.
Acquisition Tim e
Acquisition time is the amount of time it takes the AD9101 to
reacquire the analog input when switching from hold-to-track
mode. T he interval starts at the 50% clock transition point and
ends when the input signal is reacquired to within a specified er-
ror band at the hold capacitor.
T hough acquisition time and track-to-hold settling time to
1/2 LSB (0.4%) accuracy are 6 ns and 4 ns respectively, it is still
possible to achieve –45 dB SNR performance at clock speeds to
125 MSPS. T his is because the settling error is roughly propor-
tional to the signal level and is partially cancelled due to the
high phase margin of the input sampler.
T he hold-to-track switch delay (tDHT ) cannot be subtracted
from this acquisition time for 12-bit performance because it is a
charging time and analog output delay that occurs when moving
from hold to track; this delay is typically 1.5 ns. T herefore, the
track time required for the AD9101 is the acquisition time
which includes tDHT . Note that the acquisition time is defined as
the settled voltage at the hold capacitor and does not include the
delay and settling time of the output amplifier. T he example in
Figure 1 illustrates why the output amplifier does not contribute
to the overall acquisition time.
H old vs. Tr ack Mode D istor tion
In many traditional high speed, open-loop track-and-holds,
track mode distortion is often much better than hold mode dis-
tortion. T rack mode distortion does not include nonlinearities
due to the switch network, and does not correlate to the relevant
hold mode distortion. But since hold mode distortion has tradi-
tionally been omitted from manufacturer’s specification tables,
users have had to discover for themselves the effective overall
hold mode distortion of the combined T /H and encoder.
T he exaggerated illustration in Figure 1 shows that VHC has
settled to within x% of its final value, but VOUT (due to slew rate
limitations, finite BW, power supply ringing, etc.) has not settled
REV. 0
–5–
AD9101
T he architecture of the AD9101 minimizes hold mode distor-
tion over its specified frequency range. As an example, in track
mode the worst harmonic generated for a 20 MHz input tone is
typically –65 dBFS. In hold mode, under the same conditions
and sampling at 50 MSPS, the worst harmonic generated is
–75 dBFS. T he reason is the output amplifier in hold mode has
only a dc distortion relevancy. With its inherent linearity (7 ns
settling to 0.01%), the output amplifier has essentially settled to
its dc distortion level even for track plus hold times as short as
20 ns. For a traditional open-loop output buffer, the ac (track
mode) and dc (hold mode) distortion levels are often the same.
should be removed from around the VIN and VOUT pins to mini-
mize coupling onto the analog signal path.
While a single ground plane is recommended, the analog signal
and differential ECL clock ground currents follow a narrow path
directly under their common voltage signal line. T o reduce re-
flections, especially when terminations are used for transmission
line efficiency, the clock, VIN, and VOUT signals and respective
ground paths should not cross each other; if they do, unwanted
coupling can result. Analog terminations should be kept as far as
possible from the power supply decoupling capacitors to mini-
mize supply current spike feedthrough.
D r oop Rate
D r iving the Encode Clock
Droop rate does not necessarily affect a track-and-hold’s distor-
tion characteristics. If the droop rate is constant versus the input
voltage for a given hold time, it manifests itself as a dc offset
to the encoder. For the AD9101, the droop rate is typically
3 mV/µs. If a signal is held for 1 µs, a subsequent encoder will
see a 3 mV offset voltage. If there is no droop sensitivity to the
held voltage value, the offset would be constant and “ride” on
the input signal and introduce no hold-mode nonlinearities.
T he AD9101 requires a differential ECL clock command. Due
to the high gain bandwidth of the AD9101 internal switch, the
input clock should have a slew rate of at least 400 V/µs.
T o obtain maximum signal to noise performance, especially at
high analog input frequencies, a low jitter clock source is re-
quired. T he AD9101 clock can be driven by an AD96685, an
ultrahigh speed ECL comparator with very low jitter.
Figure 2 illustrates a recommended termination for the differen-
tial encode clock inputs of the AD9101. T he 40 Ω RLS is re-
quired to level shift the ECL voltages more negative. T his
increases the linear signal range of the sampler. When the input
is less than 600 mV (2.4 V p-p output), these level shift resistors
are not required.
When droop rate varies proportionately to the level of the held
voltage signal level, only a gain error is introduced to the A/D
encoder. T he AD9101 has a droop sensitivity to the input level
of 20 mV/V µs. For a 2 V p-p output signal, this translates to a
1%/µs gain error and does not cause additional distortion errors.
However, hold times longer than about 500 ns can cause distor-
tion due to the R × HC time constant at the hold capacitor. In
addition, hold mode noise will increase linearly vs. hold time
and thus degrade SNR performance.
R
R
LS
LS
CLK
10
CLK
11
40
40
Layout Consider ations
510
510
For best performance results, good high speed design tech-
niques must be applied. T he component (top) side ground
plane should be as large as possible; two-ounce copper cladding
is preferable. All runs should be as short as possible, and de-
coupling capacitors must be used.
–5.2 V
–5.2 V
Figure 2. Recom m ended Encode Clock Term ination
T he schematic of a recommended AD9101 evaluation board is
shown. (Contact factory concerning availability of assembled
boards.) All 0.01 µF decoupling capacitors should be low induc-
tance surface mount devices (P/N 05085C103MT 050 from
AVX) and connected with short lead lengths to minimize stray
inductance.
When driving the encode clock from a remote circuit via
transmission lines, or where stray capacitance exceeds 2 pF,
T hevenin equivalent terminations should be used (270 Ω to
–5.2 V and 160 Ω to ground). For this 100 Ω equivalent termi-
nation, RLS should be 20 Ω.
D r iving the Analog Input
T he 10 µF, low frequency tantalum power supply decoupling
capacitors should be located within 1.5 inches of the AD9101.
T he common 0.01 µF supply capacitors can be wired together.
T he common power supply bus (connected to the 10 µF capaci-
tor and power supply source) can be routed to the underside of
the board to the daisy chain wired 0.01 µF supply capacitors.
Special care must be taken to ensure that the analog input signal
is not compromised before it reaches the AD9101. T o obtain
maximum signal to noise performance, a very low phase noise
analog source is required. In addition, input filtering and/or a
low harmonic signal source is necessary to maximize the spuri-
ous free dynamic range. Any required filtering should be located
close to the AD9101 and away from digital lines.
For remote input and/or output drive applications, controlled
impedances are required to minimize line reflections which will
reduce signal fidelity. When capacitive and/or high impedance
levels are present, the load and/or source should be physically
located within approximately one inch of the AD9101. Note
that a series resistance, RS, is required if the load is greater than
6 pF. (T he Recommended RS vs. CL chart in the “T ypical Per-
formance Section” shows values of RS for various capacitive
loads which result in no more than a 20% increase in settling
time for loads up to 80 pF.) For best results when driving
heavily capacitive or low resistance loads, the AD9630 buffer is
strongly suggested. As much of the ground plane as possible
Matching the AD 9101 to A/D Encoder s
T he AD9101’s analog output level may have to be offset or am-
plified to match the full-scale range of a given A/D converter.
T his can generally be accomplished by inserting an amplifier af-
ter the AD9101. For example, the AD671 is a 12-bit 500 ns
monolithic ADC encoder that requires a 0 V to +5 V full-scale
analog input. An AD84X series amplifier could be used to con-
dition the AD9101 output to match the full-scale range of the
AD671.
The AD9101 can perform a dc level shift function when its input
is bipolar and the ADC requires a unipolar signal. The AD9002
REV. 0
–6–
AD9101
–70
–65
–60
–55
–50
provides a good example. It operates on a single negative supply
with the input range from 0 V to –2 V. By connecting Pins 1
and 2 (RT N) to a +0.33 V level, rather than its usual ground
connection, a bipolar ±0.25 V input is shifted to 0 V to –2 V at
the AD9101’s output (see Figure 3 in the Applications section.)
WORST HARMONIC
SNR W/HARMONICS
WITH AD9101
WITH AD9101
AP P LICATIO NS
Because of its rapid acquisition and low distortion, the AD9101
is useful in a wide range of signal processing.
–45
–40
–35
–30
Choosing Between the AD 9100 and AD 9101
T he first obvious difference between the AD9100 and AD9101
is sample rate. Simplistically, any high resolution system (12–16
bits) operating below 25 MSPS will use the AD9100 and 8–12
bit systems operating above 25 MSPS will use the AD9101.
T here are, however, some subtle characteristics of these high
performance track-and-hold amplifiers that create some excep-
tions to these guidelines. T he typical curve entitled “Dynamic
Range vs. Analog Frequency” should be considered when
choosing between these two high performance track-and-holds.
ENCODE = 125 MSPS
1
10
100
MHz
Figure 4. AD9002 Dynam ic Range With and Without
AD9101
27Ω
When speed is critical, the AD9101 should receive strong con-
sideration, even in high resolution systems. Using a reduced sig-
nal amplitude through the AD9100 greatly reduces slew limiting
effects and should also be considered when converting high fre-
quency (up to 70 MHz) analog signals with encode rates below
25 MSPS.
AD9060
AD9630
AD9101
CLOCK 2
CLOCK 1
"HOLD"
8 ns
"HOLD"
8 ns
CLOCK 1
8.5 ns
8.5 ns
8.5 ns
Sam pler for Flash AD C
Flash ADCs typically suffer degradation of dynamic range as
signal frequency increases. T he AD9101 was designed specifi-
cally for the purpose of boosting this performance and allowing
users to obtain maximum performance with flash ADCs. Figure
3 shows the block diagram and timing relationship for an 8-bit,
125 MSPS converter.
"TRACK"
"TRACK"
"TRACK"
2.5 ns
"HOLD"
8.25 ns
"HOLD"
8.25 ns
"HOLD"
8.25 ns
8.25 ns
"TRACK"
8.25 ns
"TRACK"
CLOCK 2
+5V
Figure 5. AD9101 with 10-Bit, 75 MSPS ADC
1k
0.33V
3k
–70
+
WORST
HARMONIC
SNR W/
WITH AD9101
–
1k
0.1µF
–65
HARMONICS
RTN
–60
–55
–50
WITH AD9101
40Ω
AC
AD9002
AD9101
CLOCK 1
CLOCK 2
HOLD
4.4 ns
HOLD
44 ns
–45
–40
–35
–30
CLOCK 1
(AD9101)
3.6 ns
3.6 ns
3.6 ns
TRACK
TRACK
TRACK
ENCODE = 60 MSPS
1.6 ns
HOLD
3.5 ns
HOLD
3.5 ns
HOLD
3.5 ns
CLOCK 2
(AD9002)
4.5 ns
TRACK
4.5 ns
TRACK
1
10
100
MHz
Figure 6. AD9060 Dynam ic Perform ance With and With-
out AD9101
Figure 3. AD9101 with 8-Bit, 125 MSPS Flash
Figure 4 contrasts performance of the flash converter alone vs.
the circuit of Figure 3.
Figures 5 and 6 show the block diagrams and dynamic range
improvement when the AD9101 is used ahead of an 10-bit, 75
MSPS flash converter. T he AD9630 is not required if the input
frequency is limited to 40 MHz.
REV. 0
–7–
AD9101
D eglitcher
T hus, the final IF signal was mixed with quadrature signals
from the final LO. T he two resultant baseband signals repre-
senting I and Q were digitized by independent converters.
Many recently announced video-speed digital-to-analog con-
verters feature very low glitch impulse. T his is the result of de-
sign emphasis on spurious free dynamic range (SFDR), a key
spec for the emerging direct digital synthesis (DDS) market.
T hese DACs have extremely low spurs and often do not require
deglitching.
Q
ADC
90°
Although their specs are impressive, these DACs may suffer har-
monic distortion, especially at higher clock rates. T herefore, a
deglitcher using the AD9101 can improve SFDR in some cases.
Figure 7 illustrates the block diagram for deglitching an
AD9713, 12-bit DAC.
IF
BPF
ANALOG
INPUT
DSP
LOCAL
OSC.
I
ADC
QUADRATURE
DEMODULATOR
32
12
DDS
ACCUMULATOR
(AD9955)
SAMPLING
AMPLIFIER
(AD9101)
TUNING
WORD
DAC
(AD9713)
LOW
DISTORTION
OUTPUT
Figure 8. Traditional l-Q Dem odulation
T his method, shown in block form in Figure 8, relies heavily on
accuracy of the phase of the analog I and Q signals applied to
the ADCs. As little as 0.5° of phase error can reduce system dy-
namic range by 6 dB or more.
CLK1
CLK2
CLK3
Figure 7. Deglitcher Block Diagram
IF-to-D igital Conver sion
T raditional receivers with information encoded with in phase (I)
and quadrature (Q) signals comprise extensive analog signal
processing ahead of the pair of ADCs.
Using the bandwidth and low distortion of the AD9101 greatly
simplifies the analog front end and allows signal processing to
be done in the digital domain which is more predictable and less
susceptible to environmental changes. T he simplified front end
is illustrated in Figure 9.
T his I-Q demodulation in the analog domain requires precise
gain and phase matching as well as close matching of the ADCs.
T his leads to high cost both in materials and labor to attain the
desired performance. Digital front end designers have paid the
cost for these components because ADCs have limited the dy-
namic range at higher signal frequencies.
T his configuration removes the burden from the analog section.
T he AD9101 expands the dynamic range of the ADC into the
IF bandwidth, allowing straightforward digital algorithms to de-
modulate the I and Q data.
Q
H (z)
NUMERICALLY
CONTROLLED
OSCILLATOR
(NCO)
12
ANALOG
IF
DSP
AD9101
ADC
INPUT
BPF
I
H (z)
Figure 9. Direct IF-to-Digital
REV. 0
–8–
AD9101
–V
+V
S
S
3.0 (76.2)
GND
C6
10 µF
+
C1
C2
10 µF
+
H2
+5V
H3
–5.2V
V
OUT
R1
27
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
V
RTN
RTN
OUT
J3
V
C
OUT
B–
C6
C2
AD9101
–V
S
AD9101
EVALUATION
BOARD
C
B+
C7
C3
C1
R1
–V
S
+V
S
S
C9
R2
C3
+V
GND
J2
C7
R4 C4
R5
6
CLOCK IN
V
IN
GND
GND
OUT
U1
J1
R7
V
7
8
9
C5
IN
NC
R3
–V
S
+V
S
C9
C8
C4
–V
S
H1
H4
+V
S
10
CLK
CLK
AD9101 Layout
J1
V
IN
R2
51
R6,160
U1
R4,160
AD96685BR
J2
3
R7, 270
R5, 270
CLOCK
INPUT
11
+
–
Q
Q
R3
51
4
12
6
LE
–5.2 V
NOTES
1. ALL CAPACITORS ARE 0.01 F UNLESS OTHERWISE
DESIGNATED. SURFACE-MOUNT CAPS PREFERRED.
2. R1 SHOULD BE SELECTED BASED ON CL AND MAY BE
SHORTED FOR CAPACITIVE LOADS OF LESS THAN 6 pF.
3. C1 SHOULD A LOW INDUCTANCE 0.01 F WITH
CIRCUIT LEADS AS SHORT AS POSSIBLE.
4. PINOUTS FOR AD9101 AND AD96685 ARE FOR SOIC.
Evaluation Circuit
Com ponent Side
EVALUATIO N BO ARD O RD ERING GUID E
P art Num ber
D escription
AD9101/PCB
AD9101/PWB
Fully Populated and T ested Evaluation Board
Printed Circuit Board without Components
Ground Plane Bottom
REV. 0
–9–
AD9101 – Typical Performance Curves
Gain vs. Frequency (Track Mode)
Hold Mode Distortion vs. Analog
Input Frequency
Recom m ended RS vs. CL for Optim al
Settling Tim e
Droop Rate vs. Tem perature
Track-to-Hold-to-Track Transients
Feedthrough vs. Input Frequency
Settling Tolerance vs. Acquisition
Tim e
Power Supply Rejection Ratio vs.
Frequency
REV. 0
–10–
AD9101
O UTLINE D IMENSIO NS
D imensions are shown in inches and (mm).
20-P in SO IC
20-Contact LCC
0.055 (1.40)
0.045 (1.14)
0.512 (13.00)
0.496 (12.60)
0.075
(1.91)
REF.
19 20
1
2
3
20
11
0.028 (0.71)
0.022 (0.56)
18
17
4
5
6
0.299 (7.60)
0.291 (7.40)
NO. 1 PIN
INDEX
TOP VIEW
16
BOTTOM VIEW
0.419 (10.65)
0.394 (10.00)
0.050
(1.27)
BSC
15
14
7
8
10
1
13
12 11 10
9
0.019 (0.49)
0.014 (0.35)
0.50 (1.27) BSC
0.358 (9.09)
0.342 (8.69)
0.104 (2.65)
0.093 (2.35)
0.100 (2.54)
0.064 (1.63)
0.012 (0.30)
0.004 (0.10)
0.0125 (0.32)
0.0091 (0.23)
0.050 (1.27)
0.016 (0.40)
REV. 0
–11–
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