AD9228ABCPZRL7-40 [ADI]
Serial LVDS 1.8 V A/D Converter;型号: | AD9228ABCPZRL7-40 |
厂家: | ADI |
描述: | Serial LVDS 1.8 V A/D Converter 转换器 |
文件: | 总57页 (文件大小:1554K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Quad, 12-Bit, 40/65 MSPS
Serial LVDS 1.8 V A/D Converter
Data Sheet
AD9228
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
DRGND
4 ADCs integrated into 1 package
119 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
AD9228
12
VIN + A
VIN – A
SERIAL
LVDS
D + A
D – A
PIPELINE
ADC
ENOB = 11.3 bits
SFDR = 82 dBc (to Nyquist)
Excellent linearity
DNL = 0.3 LSB (typical)
12
12
VIN + B
VIN – B
PIPELINE
ADC
SERIAL
LVDS
D + B
D – B
VIN + C
VIN – C
SERIAL
LVDS
D + C
D – C
INL = 0.4 LSB (typical)
PIPELINE
ADC
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
315 MHz full-power analog bandwidth
2 V p-p input voltage range
12
VIN + D
VIN – D
SERIAL
LVDS
D + D
D – D
PIPELINE
ADC
VREF
FCO+
FCO–
SENSE
+
0.5V
–
DATA RATE
MULTIPLIER
1.8 V supply operation
Serial port control
REFT
REFB
REF
SELECT
SERIAL PORT
INTERFACE
DCO+
DCO–
Full-chip and individual-channel power-down modes
Flexible bit orientation
SCLK/DTP
RBIASAGND CSB SDIO/ODM
CLK+ CLK–
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
Figure 1.
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-
channel power-down is supported and typically consumes less
than 2 mW when all channels are disabled.
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI).
Test equipment
GENERAL DESCRIPTION
The AD9228 is available in an RoHS compliant, 48-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital con-
verter (ADC) with an on-chip sample-and-hold circuit designed
for low cost, low power, small size, and ease of use. The product
operates at a conversion rate of up to 65 MSPS and is optimized for
outstanding dynamic performance and low power in applications
where a small package size is critical.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-
saving package.
2. Low power of 119 mW/channel at 65 MSPS.
3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 390 MHz and supports
double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of flexible
features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9259 (14-bit).
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
AD9228* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
TOOLS AND SIMULATIONS
• Visual Analog
• AD9228 IBIS Model
EVALUATION KITS
REFERENCE MATERIALS
• AD9228 Evaluation Board
Technical Articles
DOCUMENTATION
Application Notes
• Matching An ADC To A Transformer
• MS-2210: Designing Power Supplies for High Speed ADC
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
DESIGN RESOURCES
• AD9228 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AN-501: Aperture Uncertainty and ADC System
Performance
• AN-586: LVDS Outputs for High Speed A/D Converters
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
DISCUSSIONS
View all AD9228 EngineerZone Discussions.
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
SAMPLE AND BUY
Visit the product page to see pricing options.
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
• AN-835: Understanding High Speed ADC Testing and
Evaluation
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
• AD9228: Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D
Converter Data Sheet
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
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AD9228
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Input Considerations ................................................... 20
Clock Input Considerations...................................................... 23
Serial Port Interface (SPI).............................................................. 31
Hardware Interface..................................................................... 31
Memory Map .................................................................................. 33
Reading the Memory Map Table.............................................. 33
Reserved Locations .................................................................... 33
Default Values............................................................................. 33
Logic Levels................................................................................. 33
Evaluation Board ............................................................................ 37
Power Supplies............................................................................ 37
Input Signals................................................................................ 37
Output Signals ............................................................................ 37
Default Operation and Jumper Selection Settings................. 38
Alternative Analog Input Drive Configuration...................... 39
Outline Dimensions....................................................................... 53
Ordering Guide .......................................................................... 53
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Diagrams.............................................................................. 8
Absolute Maximum Ratings.......................................................... 10
Thermal Impedance................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Equivalent Circuits......................................................................... 13
Typical Performance Characteristics ........................................... 15
Theory of Operation ...................................................................... 20
Rev. E | Page 2 of 56
Data Sheet
AD9228
REVISION HISTORY
Changes to Figure 23 to Figure 26 Captions ...............................15
Change to Figure 35 Caption.........................................................17
Added Figure 46 and Figure 47.....................................................20
Changes to Figure 51 ......................................................................21
Changes to Clock Duty Cycle Considerations Section..............22
Changes to Power Dissipation and Power-Down Mode Section...23
Changes to Figure 61 to Figure 63 Captions ...............................25
Changes to Table 9 Endnote ..........................................................26
Changes to Digital Outputs and Timing Section........................27
Added Table 10................................................................................27
Changes to RBIAS Pin Section......................................................28
Deleted Figure 62 and Figure 63 ...................................................27
Changes to Figure 67 ......................................................................29
Changes to Hardware Interface Section.......................................30
Added Figure 68..............................................................................31
Changes to Table 15 ........................................................................31
Changes to Reading the Memory Map Table Section................32
Change to Input Signals Section ...................................................36
Changes to Output Signals Section...............................................36
Changes to Figure 71 ......................................................................36
Changes to Default Operation and
12/11—Rev. D to Rev. E
Changes to Output Signals Section and Figure 71......................37
Change to Default Operation and Jumper Selection Settings
Section ..............................................................................................38
Change to Figure 74........................................................................41
Added Endnote 3 in Ordering Guide...........................................53
4/10—Rev. C to Rev. D
Changes to Table 16 ........................................................................35
Updated Outline Dimensions........................................................53
Changes to Ordering Guide...........................................................53
12/09—Rev. B to Rev. C
Updated Outline Dimensions........................................................53
Changes to Ordering Guide...........................................................54
7/07—Rev. A to Rev. B
Changes to Figure 3...........................................................................7
Change to Table 7............................................................................10
5/07—Rev. 0 to Rev. A
Jumper Selection Settings Section ...........................................37
Changes to Alternative Analog Input
Drive Configuration Section ....................................................38
Changes to Figure 74 ......................................................................40
Changes to Table 17 ........................................................................48
Changes to Ordering Guide...........................................................52
Changes to Features ..........................................................................1
Change to Effective Number of Bits (ENOB)................................4
Changes to Logic Output (SDIO/ODM) Section..........................5
Added Endnote 3 to Table 3.............................................................5
Changes to Pipeline Latency............................................................6
Added Endnote 2 to Table 4.............................................................6
Changes to Figure 2 to Figure 4.......................................................7
Changes to Figure 10 ......................................................................12
Changes to Figure 15, Figure 17 to Figure 19, Figure 37, and
Figure 39......................................................................................14
4/06—Revision 0: Initial Version
Rev. E | Page 3 of 56
AD9228
Data Sheet
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
AD9228-40
Min Typ
AD9228-65
Max Min Typ
Parameter1
Temperature
Max
Unit
RESOLUTION
12
12
Bits
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Full
Full
Full
Full
Full
Full
Full
Guaranteed
±1
±2
±ꢀ.4
±ꢀ.ꢁ
Guaranteed
±1
±2
±±
±±
±1.2
±ꢀ.ꢂ
±ꢀ.5
±1
±±
mV
±±
mV
±2
±ꢁ.5
±ꢀ.ꢂ
% FS
% FS
Gain Matching
±ꢀ.ꢁ
±ꢀ.ꢁ
±ꢀ.4
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Voltage (1 V Mode)
REFERENCE
±ꢀ.25
±ꢀ.4
±ꢀ.65 LSB
±1
LSB
Full
Full
Full
±2
±1ꢂ
±21
±2
±1ꢂ
±21
ppm/°C
ppm/°C
ppm/°C
Output Voltage Error (VREF = 1 V)
Load Regulation at 1.ꢀ mA (VREF = 1 V)
Input Resistance
Full
Full
Full
±2
ꢁ
6
±ꢁꢀ
±2
ꢁ
6
±ꢁꢀ
mV
mV
kΩ
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V)
Common-Mode Voltage
Differential Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
Full
Full
Full
Full
2
2
V p-p
V
pF
AVDD/2
ꢂ
ꢁ15
AVDD/2
ꢂ
ꢁ15
MHz
AVDD
DRVDD
IAVDD
IDRVDD
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.ꢂ
1.ꢂ
1.±
1.±
155
ꢁ1
ꢁꢁ5
2
1.9
1.9
1ꢂꢀ
ꢁ4
ꢁ6ꢂ
5.±
1.ꢂ
1.ꢂ
1.±
1.±
2ꢁ2
ꢁ4
4ꢂ±
2
1.9
1.9
245
ꢁ±
51ꢀ
5.±
V
V
mA
mA
mW
mW
mW
dB
Total Power Dissipation (Including Output Drivers)
Power-Down Dissipation
Standby Dissipation2
CROSSTALK
ꢂ2
ꢂ2
−1ꢀꢀ
−1ꢀꢀ
−1ꢀꢀ
−1ꢀꢀ
CROSSTALK (Overrange Condition)ꢁ
dB
1 See the AN-±ꢁ5 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Can be controlled via the SPI.
ꢁ Overrange condition is specific with 6 dB of the full-scale input range.
Rev. E | Page 4 of 56
Data Sheet
AD9228
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2.
AD9228-40
Typ
AD9228-65
Typ
Parameter1
Temperature
Min
Max
Min
Max
Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 19.ꢂ MHz
fIN = ꢁ5 MHz
fIN = ꢂꢀ MHz
Full
Full
Full
Full
ꢂꢀ.5
ꢂꢀ.2
ꢂꢀ.2
ꢂꢀ.ꢀ
ꢂꢀ.2
ꢂꢀ.ꢀ
ꢂꢀ.ꢀ
69.5
dB
dB
dB
dB
6±.5
6±.5
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 2.4 MHz
fIN = 19.ꢂ MHz
fIN = ꢁ5 MHz
fIN = ꢂꢀ MHz
Full
Full
Full
Full
ꢂꢀ.ꢁ
69.±
69.ꢂ
69.5
ꢂꢀ.ꢀ
ꢂꢀ.ꢀ
69.±
69.ꢀ
dB
dB
dB
dB
6±.ꢀ
11.1
ꢂ2
6±.ꢀ
11.1
ꢂꢁ
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 19.ꢂ MHz
fIN = ꢁ5 MHz
fIN = ꢂꢀ MHz
Full
Full
Full
Full
11.42
11.ꢁꢂ
11.ꢁꢂ
11.ꢁꢁ
11.ꢁꢂ
11.ꢁꢁ
11.ꢁꢁ
11.25
Bits
Bits
Bits
Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 19.ꢂ MHz
fIN = ꢁ5 MHz
fIN = ꢂꢀ MHz
Full
Full
Full
Full
±5
±2
±ꢀ
±ꢀ
±5
±5
±4
ꢂ4
dBc
dBc
dBc
dBc
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz
fIN = 19.ꢂ MHz
fIN = ꢁ5 MHz
fIN = ꢂꢀ MHz
Full
Full
Full
Full
−±5
−±2
−±ꢀ
−±ꢀ
−±5
−±5
−±4
−ꢂ4
dBc
dBc
dBc
dBc
−ꢂ2
−±ꢀ
−ꢂꢁ
−ꢂ9
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz
fIN = 19.ꢂ MHz
fIN = ꢁ5 MHz
fIN = ꢂꢀ MHz
Full
Full
Full
Full
−9ꢀ
−9ꢀ
−9ꢀ
−9ꢀ
−9ꢀ
−9ꢀ
−9ꢀ
−±±
dBc
dBc
dBc
dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)—
AIN1 AND AIN2 = −ꢂ.ꢀ dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz
fIN1 = ꢂꢀ MHz, fIN2 = ꢂ1 MHz
25°C
25°C
±ꢀ.±
ꢂ5.ꢀ
ꢂꢂ.±
ꢂꢂ.ꢀ
dBc
dBc
1 See the AN-±ꢁ5 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Rev. E | Page 5 of 56
AD9228
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
AD9228-40
Typ Max
AD9228-65
Typ Max
Parameter1
Temperature
Min
Min
Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
CMOS/LVDS/LVPECL
CMOS/LVDS/LVPECL
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Full
Full
25°C
25°C
25ꢀ
25ꢀ
mV p-p
V
kΩ
pF
1.2
2ꢀ
1.5
1.2
2ꢀ
1.5
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic ꢀ Voltage
Input Resistance
Input Capacitance
Full
Full
25°C
25°C
1.2
ꢀ
ꢁ.6
ꢀ.ꢁ
1.2
1.2
ꢁ.6
ꢀ.ꢁ
V
V
kΩ
pF
ꢁꢀ
ꢀ.5
ꢁꢀ
ꢀ.5
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic ꢀ Voltage
Full
Full
1.2
ꢀ
ꢁ.6
ꢀ.ꢁ
ꢁ.6
ꢀ.ꢁ
V
V
Input Resistance
Input Capacitance
25°C
25°C
ꢂꢀ
ꢀ.5
ꢂꢀ
ꢀ.5
kΩ
pF
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic ꢀ Voltage
Full
Full
1.2
ꢀ
DRVDD + ꢀ.ꢁ 1.2
DRVDD + ꢀ.ꢁ
ꢀ.ꢁ
V
V
ꢀ.ꢁ
ꢀ
Input Resistance
Input Capacitance
25°C
25°C
ꢁꢀ
2
ꢁꢀ
2
kΩ
pF
LOGIC OUTPUT (SDIO/ODM)ꢁ
Logic 1 Voltage (IOH = ±ꢀꢀ μA)
Logic ꢀ Voltage (IOL = 5ꢀ μA)
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance
Full
Full
1.ꢂ9
ꢀ.ꢀ5
1.ꢂ9
V
V
ꢀ.ꢀ5
LVDS
LVDS
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Full
Full
24ꢂ
1.125
454
1.ꢁꢂ5
Offset binary
24ꢂ
1.125
454
1.ꢁꢂ5
Offset binary
mV
V
DIGITAL OUTPUTS (D + x, D − x),
(Low Power, Reduced Signal Option)
Logic Compliance
LVDS
LVDS
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Full
Full
15ꢀ
1.1ꢀ
25ꢀ
1.ꢁꢀ
Offset binary
15ꢀ
1.1ꢀ
25ꢀ
1.ꢁꢀ
Offset binary
mV
V
1 See the AN-±ꢁ5 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 This is specified for LVDS and LVPECL only.
ꢁ This is specified for 1ꢁ SDIO pins sharing the same connection.
Rev. E | Page 6 of 56
Data Sheet
AD9228
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
AD9228-40
Typ
AD9228-65
Typ
Parameter1, 2
Temp
Min
Max
Min
Max
Unit
CLOCKꢁ
Maximum Clock Rate
Minimum Clock Rate
Full
Full
Full
Full
4ꢀ
65
MSPS
MSPS
ns
1ꢀ
1ꢀ
Clock Pulse Width High (tEH
)
12.5
12.5
ꢂ.ꢂ
ꢂ.ꢂ
Clock Pulse Width Low (tEL)
ns
OUTPUT PARAMETERSꢁ
Propagation Delay (tPD
)
Full
Full
Full
Full
Full
2.ꢀ
2.ꢀ
2.ꢂ
ꢁ.5
ꢁ.5
2.ꢀ
2.ꢀ
2.ꢂ
ꢁ.5
ꢁ.5
ns
ps
ps
ns
ns
Rise Time (tR) (2ꢀ% to ±ꢀ%)
Fall Time (tF) (2ꢀ% to ±ꢀ%)
FCO Propagation Delay (tFCO
ꢁꢀꢀ
ꢁꢀꢀ
2.ꢂ
ꢁꢀꢀ
ꢁꢀꢀ
2.ꢂ
)
4
DCO Propagation Delay (tCPD
)
tFCO
+
tFCO
+
(tSAMPLE/24)
(tSAMPLE/24)
4
Full
Full
Full
(tSAMPLE/24) − ꢁꢀꢀ (tSAMPLE/24) (tSAMPLE/24) + ꢁꢀꢀ (tSAMPLE/24) − ꢁꢀꢀ (tSAMPLE/24) (tSAMPLE/24) + ꢁꢀꢀ ps
(tSAMPLE/24) − ꢁꢀꢀ (tSAMPLE/24) (tSAMPLE/24) + ꢁꢀꢀ (tSAMPLE/24) − ꢁꢀꢀ (tSAMPLE/24) (tSAMPLE/24) + ꢁꢀꢀ ps
DCO to Data Delay (tDATA
)
4
DCO to FCO Delay (tFRAME
Data to Data Skew
)
±5ꢀ
±15ꢀ
±5ꢀ
±15ꢀ
ps
(tDATA-MAX − tDATA-MIN
)
Wake-Up Time (Standby)
25°C
25°C
Full
6ꢀꢀ
ꢁꢂ5
±
6ꢀꢀ
ꢁꢂ5
±
ns
μs
Wake-Up Time (Power-Down)
Pipeline Latency
CLK
cycles
APERTURE
Aperture Delay (tA)
25°C
25°C
25°C
5ꢀꢀ
<1
1
5ꢀꢀ
<1
2
ps
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
ps rms
CLK
cycles
1 See the AN-±ꢁ5 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Measured on standard FR-4 material.
ꢁ Can be adjusted via the SPI.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
Rev. E | Page ꢂ of 56
AD9228
Data Sheet
TIMING DIAGRAMS
N – 1
VIN ± x
tA
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFRAME
tFCO
FCO–
FCO+
tPD
tDATA
D – x
D + x
MSB
N – 9
D10
N – 9
D9
N – 9
D8
N – 9
D7
N – 9
D6
N – 9
D5
N – 9
D4
N – 9
D3
N – 9
D2
N – 9
D1
N – 9
D0
N – 9
MSB
N – 8
D10
N – 8
Figure 2. 12-Bit Data Serial Stream, MSB First (Default)
N – 1
VIN ± x
tA
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFRAME
tFCO
FCO–
FCO+
D – x
tPD
tDATA
MSB
N – 9
D8
N – 9
D7
D6
D5
D4
D3
D2
D1
D0
MSB
D8
D7
D6
D5
N – 8
N – 9 N – 9
N – 9 N – 9 N – 9 N – 9
N – 9 N – 9 N – 8 N – 8
N – 8 N – 8
D + x
Figure 3. 10-Bit Data Serial Stream, MSB First
Rev. E | Page ± of 56
Data Sheet
AD9228
N – 1
VIN ± x
tA
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFRAME
tFCO
FCO–
FCO+
tPD
tDATA
D – x
D + x
LSB
N – 9
D0
N – 9
D1
N – 9
D2
N – 9
D3
N – 9
D4
N – 9
D5
N – 9
D6
N – 9
D7
N – 9
D8
N – 9
D9
N – 9
D10
N – 9
LSB
N – 8
D0
N – 8
Figure 4. 12-Bit Data Serial Stream, LSB First
Rev. E | Page 9 of 56
AD9228
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
With
Respect To
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
ELECTRICAL
AVDD
DRVDD
AGND
Rating
AGND
−ꢀ.ꢁ V to +2.ꢀ V
−ꢀ.ꢁ V to +2.ꢀ V
−ꢀ.ꢁ V to +ꢀ.ꢁ V
−2.ꢀ V to +2.ꢀ V
−ꢀ.ꢁ V to +2.ꢀ V
DRGND
DRGND
DRVDD
DRGND
AVDD
Digital Outputs
(D + x, D − x, DCO+,
DCO−, FCO+, FCO−)
THERMAL IMPEDANCE
Table 6.
Air Flow Velocity (m/sec)
CLK+, CLK−
VIN + x, VIN − x
SDIO/ODM
PDWN, SCLK/DTP, CSB
REFT, REFB, RBIAS
VREF, SENSE
AGND
AGND
AGND
AGND
AGND
AGND
−ꢀ.ꢁ V to +ꢁ.9 V
−ꢀ.ꢁ V to +2.ꢀ V
−ꢀ.ꢁ V to +2.ꢀ V
−ꢀ.ꢁ V to +ꢁ.9 V
−ꢀ.ꢁ V to +2.ꢀ V
−ꢀ.ꢁ V to +2.ꢀ V
1
θJA
24
21
19
θJB
θJC
Unit
°C/W
°C/W
°C/W
ꢀ.ꢀ
1.ꢀ
2.5
12.6
1.2
1 θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad
soldered to PCB.
ENVIRONMENTAL
Operating Temperature
Range (Ambient)
Maximum Junction
Temperature
−4ꢀ°C to +±5°C
15ꢀ°C
ESD CAUTION
Lead Temperature
(Soldering, 1ꢀ sec)
ꢁꢀꢀ°C
Storage Temperature
Range (Ambient)
−65°C to +15ꢀ°C
Rev. E | Page 1ꢀ of 56
Data Sheet
AD9228
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
2
AVDD
AVDD
VIN – D
VIN + D
AVDD
AVDD
CLK–
36
35
34
33
AVDD
AVDD
3
VIN – A
VIN + A
AVDD
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
4
5
32
31
30
29
28
27
26
25
6
PDWN
AD9228
TOP VIEW
7
CSB
8
CLK+
SDIO/ODM
SCLK/DTP
AVDD
9
AVDD
AVDD
DRGND
DRVDD
10
11
12
DRGND
DRVDD
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
Figure 5. 48-Lead LFCSP Pin Configuration, Top View
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
ꢀ
AGND
AVDD
Analog Ground (Exposed Paddle)
1.± V Analog Supply
1, 2, 5, 6, 9, 1ꢀ, 2ꢂ, ꢁ2,
ꢁ5, ꢁ6, ꢁ9, 45, 46
11, 26
12, 25
ꢁ
4
ꢂ
DRGND
DRVDD
VIN − D
VIN + D
CLK−
Digital Output Driver Ground
1.± V Digital Output Driver Supply
ADC D Analog Input Complement
ADC D Analog Input True
Input Clock Complement
±
CLK+
Input Clock True
1ꢁ
14
15
16
1ꢂ
1±
19
2ꢀ
21
22
2ꢁ
24
2±
29
ꢁꢀ
ꢁ1
D − D
D + D
D − C
D + C
D − B
D + B
D − A
D + A
ADC D Digital Output Complement
ADC D Digital Output True
ADC C Digital Output Complement
ADC C Digital Output True
ADC B Digital Output Complement
ADC B Digital Output True
ADC A Digital Output Complement
ADC A Digital Output True
Frame Clock Output Complement
Frame Clock Output True
Data Clock Output Complement
Data Clock Output True
Serial Clock/Digital Test Pattern
Serial Data IO/Output Driver Mode
Chip Select Bar
FCO−
FCO+
DCO−
DCO+
SCLK/DTP
SDIO/ODM
CSB
PDWN
Power-Down
Rev. E | Page 11 of 56
AD9228
Data Sheet
Pin No.
ꢁꢁ
ꢁ4
ꢁꢂ
ꢁ±
4ꢀ
41
42
4ꢁ
Mnemonic
VIN + A
VIN − A
VIN − B
VIN + B
RBIAS
SENSE
VREF
REFB
Description
ADC A Analog Input True
ADC A Analog Input Complement
ADC B Analog Input Complement
ADC B Analog Input True
External resistor sets the internal ADC core bias current
Reference Mode Selection
Voltage Reference Input/Output
Differential Reference (Negative)
Differential Reference (Positive)
ADC C Analog Input True
44
4ꢂ
4±
REFT
VIN + C
VIN − C
ADC C Analog Input Complement
Rev. E | Page 12 of 56
Data Sheet
AD9228
EQUIVALENT CIRCUITS
DRVDD
V
V
D–
D+
VIN ± x
V
V
DRGND
Figure 9. Equivalent Digital Output Circuit
Figure 6. Equivalent Analog Input Circuit
10Ω
CLK+
10kΩ
10kΩ
1.25V
SCLK/DTP
1kΩ
AND
10Ω
PDWN
30kΩ
CLK–
Figure 7. Equivalent Clock Input Circuit
Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit
100Ω
RBIAS
350Ω
SDIO/ODM
30kΩ
Figure 11. Equivalent RBIAS Circuit
Figure 8. Equivalent SDIO/ODM Input Circuit
Rev. E | Page 1ꢁ of 56
AD9228
Data Sheet
AVDD
70kΩ
1kΩ
CSB
VREF
6kΩ
Figure 12. Equivalent CSB Input Circuit
Figure 14. Equivalent VREF Circuit
1kΩ
SENSE
Figure 13. Equivalent SENSE Circuit
Rev. E | Page 14 of 56
Data Sheet
AD9228
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–20
–40
–60
–80
AIN = –0.5dBFS
SNR = 70.51dB
AIN = –0.5dBFS
SNR = 69.62dB
ENOB = 11.27 BITS
SFDR = 72.48dBc
ENOB = 11.42 BITS
SFDR = 86.00dBc
–20
–40
–60
–80
–100
–120
–100
–120
0
2
4
6
8
10
12
14
16
18
20
0
5
10
15
20
25
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 40 MSPS
Figure 18. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 65 MSPS
0
0
AIN = –0.5dBFS
SNR = 68.74dB
ENOB = 11.12 BITS
SFDR = 72.99dBc
AIN = –0.5dBFS
SNR = 70.38dB
ENOB = 11.40 BITS
SFDR = 81.13dBc
–20
–40
–20
–40
–60
–80
–60
–80
–100
–120
–100
–120
0
2
4
6
8
10
12
14
16
18
20
0
5
10
15
20
25
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. Single-Tone 32k FFT with fIN = 35 MHz, fSAMPLE = 40 MSPS
Figure 19. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 65 MSPS
0
0
AIN = –0.5dBFS
AIN = –0.5dBFS
SNR = 70.53dB
SNR = 67.68dB
ENOB = 11.42 BITS
SFDR = 86.04dBc
ENOB = 10.95 BITS
SFDR = 62.23dBc
–20
–20
–40
–60
–80
–40
–60
–80
–100
–120
–100
–120
0
5
10
15
20
25
30
0
5
10
15
20
25
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 20. Single-Tone 32k FFT with fIN = 170 MHz, fSAMPLE = 65 MSPS
Figure 17. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 65 MSPS
Rev. E | Page 15 of 56
AD9228
Data Sheet
84
82
80
78
76
74
72
70
68
0
AIN = –0.5dBFS
SNR = 67.58dB
ENOB = 10.93 BITS
SFDR = 68.39dBc
–20
2V p-p, SFDR
–40
–60
–80
–100
2V p-p, SNR
–120
0
10
15
20
25
30
35
40
5
10
15
20
25
30
ENCODE (MSPS)
FREQUENCY (MHz)
Figure 21. Single-Tone 32k FFT with fIN = 190 MHz, fSAMPLE = 65 MSPS
Figure 24. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 40 MSPS
0
90
85
AIN = –0.5dBFS
SNR = 65.56dB
ENOB = 10.6 BITS
SFDR = 62.72dBc
–20
2V p-p, SFDR
–40
–60
80
75
70
–80
–100
–120
65
2V p-p, SNR
60
10
0
5
10
15
20
25
30
20
30
40
50
60
FREQUENCY (MHz)
ENCODE (MSPS)
Figure 22. Single-Tone 32k FFT with fIN = 250 MHz, fSAMPLE = 65 MSPS
Figure 25. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
90
84
2V p-p, SFDR
82
85
2V p-p, SFDR
80
78
76
74
72
80
75
70
2V p-p, SNR
65
60
70
2V p-p, SNR
68
10
10
15
20
25
30
35
40
20
30
40
50
60
ENCODE (MSPS)
ENCODE (MSPS)
Figure 23. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 40 MSPS
Figure 26. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 65 MSPS
Rev. E | Page 16 of 56
Data Sheet
AD9228
100
100
90
80
70
60
50
40
30
20
10
0
fIN = 35MHz
fSAMPLE = 65MSPS
fIN = 10.3MHz
fSAMPLE = 40MSPS
90
80
70
60
50
40
30
20
10
0
2V p-p, SFDR
2V p-p, SFDR
80dB
REFERENCE
2V p-p, SNR
2V p-p, SNR
80dB
REFERENCE
–60
–50
–40
–30
–20
–10
0
–60
–50
–40
–30
–20
–10
0
ANALOG INPUT LEVEL (dBFS)
ANALOG INPUT LEVEL (dBFS)
Figure 30. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 65 MSPS
Figure 27. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 40 MSPS
100
0
AIN1 AND AIN2 = –7dBFS
SFDR = 80.75dBc
IMD2 = 85.53dBc
fIN = 35MHz
90
fSAMPLE = 40MSPS
–20
IMD3 = 80.83dBc
80
2V p-p, SFDR
70
–40
–60
–80
60
50
80dB
REFERENCE
2V p-p, SNR
40
30
20
10
0
–100
–120
–60
–50
–40
–30
–20
–10
0
0
2
4
6
8
10
12
14
16
18
20
ANALOG INPUT LEVEL (dBFS)
FREQUENCY (MHz)
Figure 28. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 40 MSPS
Figure 31. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz,
fSAMPLE = 40 MSPS
100
0
AIN1 AND AIN2 = –7dBFS
SFDR = 74.76dBc
IMD2 = 81.03dBc
fIN = 10.3MHz
90
fSAMPLE = 65MSPS
2V p-p, SFDR
–20
80
70
60
IMD3 = 75.00dBc
–40
–60
–80
50
40
30
20
10
0
80dB
REFERENCE
2V p-p, SNR
–100
–120
–60
–50
–40
–30
–20
–10
0
0
2
4
6
8
10
12
14
16
18
20
ANALOG INPUT LEVEL (dBFS)
FREQUENCY (MHz)
Figure 29. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
Figure 32. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz,
fSAMPLE = 40 MSPS
Rev. E | Page 1ꢂ of 56
AD9228
Data Sheet
0
90
85
80
75
70
65
60
AIN1 AND AIN2 = –7dBFS
SFDR = 78.15dBc
IMD2 = 77.84dBc
–20
IMD3 = 88.94dBc
2V p-p, SFDR
–40
–60
–80
2V p-p, SINAD
–100
–120
0
5
10
15
20
25
30
–40
–20
0
20
40
60
80
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 33. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz,
fSAMPLE = 65 MSPS
Figure 36. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
0
1.0
0.8
AIN1 AND AIN2 = –7dBFS
SFDR = 76.75dBc
IMD2 = 77.56dBc
IMD3 = 77.01dBc
–20
0.6
0.4
–40
–60
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–80
–100
–120
0
5
10
15
20
25
30
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
FREQUENCY (MHz)
Figure 34. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz,
fSAMPLE = 65 MSPS
Figure 37. INL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
90
0.5
0.4
85
2V p-p, SFDR
0.3
80
0.2
75
0.1
70
0
2V p-p, SNR
–0.1
–0.2
–0.3
–0.4
–0.5
65
60
55
50
1
10
100
1000
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
FREQUENCY (MHz)
Figure 35. SNR/SFDR vs. Frequency, fSAMPLE = 65 MSPS
Figure 38. DNL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
Rev. E | Page 1± of 56
Data Sheet
AD9228
0
–20
–45.0
–45.5
–46.0
–46.5
–47.0
–47.5
–48.0
NPR = 60.83dB
NOTCH = 18.0MHz
NOTCH WIDTH = 3.0MHz
–40
–60
–80
–100
–120
0
5
10
15
20
25
30
10
15
20
25
30
35
40
45
50
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 39. CMRR vs. Frequency, fSAMPLE = 65 MSPS
Figure 41. Noise Power Ratio (NPR), fSAMPLE = 65 MSPS
1.2
1.0
0.8
0.6
0.4
0.2
0
0
–1
–2
–3
–4
–5
–6
–7
0.26 LSB rms
–3dB CUTOFF = 315MHz
–8
–9
–10
N – 3
N – 2
N – 1
N
N + 1
N + 2
N + 3
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
CODE
Figure 40. Input-Referred Noise Histogram, fSAMPLE = 65 MSPS
Figure 42. Full-Power Bandwidth vs. Frequency, fSAMPLE = 65 MSPS
Rev. E | Page 19 of 56
AD9228
Data Sheet
THEORY OF OPERATION
The AD9228 architecture consists of a pipelined ADC divided into
three sections: a 4-bit first stage followed by eight 1.5-bit stages and
a final 3-bit flash. Each stage provides sufficient overlap to correct
for flash errors in the preceding stage. The quantized outputs from
each stage are combined into a final 12-bit result in the digital
correction logic. The pipelined architecture permits the first stage
to operate with a new input sample while the remaining stages
operate with preceding samples. Sampling occurs on the rising
edge of the clock.
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 43). When the input
circuit is switched to sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
input can help reduce the peak transient current injected from
the output stage of the driving source. In addition, low-Q inductors
or ferrite beads can be placed on each leg of the input to reduce
high differential capacitance at the analog inputs and therefore
achieve the maximum bandwidth of the ADC. Such use of low-
Q inductors or ferrite beads is required when driving the converter
front end at high IF frequencies. Either a shunt capacitor or two
single-ended capacitors can be placed on the inputs to provide a
matching passive network. This ultimately creates a low-pass
filter at the input to limit unwanted broadband noise. See the
AN-742 Application Note, the AN-827 Application Note, and the
Analog Dialogue article “Transformer-Coupled Front-End for
Wideband A/D Converters” (Volume 39, April 2005) for more
information. In general, the precise values depend on the
application.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction of
flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and data clocks.
The analog inputs of the AD9228 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
this bias externally. Setting the device so that VCM = AVDD/2 is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 44 to Figure 47.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9228 is a differential switched-
capacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
H
CPAR
H
VIN + x
CSAMPLE
S
S
S
S
CSAMPLE
VIN – x
H
CPAR
H
Figure 43. Switched-Capacitor Input Circuit
Rev. E | Page 2ꢀ of 56
Data Sheet
AD9228
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
55
SFDR (dBc)
SFDR (dBc)
SNR (dB)
SNR (dB)
50
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
ANALOG INPUT COMMON-MODE VOLTAGE (V)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
Figure 44. SNR/SFDR vs. Common-Mode Voltage,
fIN = 2.4 MHz, fSAMPLE = 65 MSPS
Figure 46. SNR/SFDR vs. Common-Mode Voltage,
fIN = 2.4 MHz, fSAMPLE = 40 MSPS
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
55
50
SFDR (dBc)
SFDR (dBc)
SNR (dB)
SNR (dB)
0.8
0.2
0.4
0.6
1.0
1.2
1.4
1.6
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
ANALOG INPUT COMMON-MODE VOLTAGE (V)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
Figure 45. SNR/SFDR vs. Common-Mode Voltage,
fIN = 30 MHz, fSAMPLE = 65 MSPS
Figure 47. SNR/SFDR vs. Common-Mode Voltage,
fIN = 30 MHz, fSAMPLE = 40 MSPS
Rev. E | Page 21 of 56
AD9228
Data Sheet
ADT1-1WT
1:1 Z RATIO
For best dynamic performance, the source impedances driving
VIN + x and VIN − x should be matched such that common-
mode settling errors are symmetrical. These errors are reduced
by the common-mode rejection of the ADC. An internal
reference buffer creates the positive and negative reference
voltages, REFT and REFB, respectively, that define the span of
the ADC core. The output common-mode of the reference buffer
is set to midsupply, and the REFT and REFB voltages and span
are defined as
C
R
VIN + x
ADC
AD9228
2Vp-p
49.9ꢀ
*C
R
DIFF
AVDD
1kꢀ
VIN – x
AGND
C
*C
DIFF IS OPTIONAL
1kꢀ
0.1μF
Figure 48. Differential Transformer-Coupled Configuration
for Baseband Applications
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
ADT1-1WT
2Vp-p
16nH
16nH 0.1μF
1:1 Z RATIO
33ꢀ
VIN + x
65ꢀ
ADC
AD9228
499ꢀ
16nH
2.2pF
1kꢀ
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
33ꢀ
VIN – x
AVDD
1kꢀ
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9228, the largest input span available is 2 V p-p.
0.1μF
1kꢀ
Figure 49. Differential Transformer-Coupled Configuration
for IF Applications
Differential Input Configurations
Single-Ended Input Configuration
There are several ways to drive the AD9228 either actively or
passively; however, optimum performance is achieved by driving
the analog input differentially. For example, using the AD8332
differential driver to drive the AD9228 provides excellent perfor-
mance and a flexible interface to the ADC (see Figure 51) for
baseband applications. This configuration is commonly used
for medical ultrasound systems.
A single-ended input may provide adequate performance in cost-
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the application requires a single-ended input configuration,
ensure that the source impedances on each input are well matched
in order to achieve the best possible performance. A full-scale
input of 2 V p-p can be applied to the ADC’s VIN + x pin while
the VIN − x pin is terminated. Figure 50 details a typical single-
ended input configuration.
For applications where SNR is a key parameter, differential
transformer coupling is the recommended input configuration
(see Figure 48 and Figure 49), because the noise performance of
most amplifiers is not adequate to achieve the true performance
of the AD9228.
AVDD
C
R
VIN + x
0.1µF
AVDD
1kꢀ
25ꢀ
2V p-p
49.9ꢀ
Regardless of the configuration, the value of the shunt capacitor,
C, is dependent on the input frequency and may need to be
reduced or removed.
ADC
*C
DIFF
AD9228
1kꢀ
R
C
VIN – x
0.1µF
1kꢀ
*C
DIFF IS OPTIONAL
Figure 50. Single-Ended Input Configuration
0.1μF
LOP
VIP
AVDD
10kꢀ
33ꢀ
680nH
68pF
187ꢀ
187ꢀ
VOH
VOL
0.1μF 120nH
INH
VIN + x
1V p-p
AD8332
10kꢀ
AVDD
1kꢀ
22pF
+
ADC
AD9228
LNA
VGA
10kꢀ
10kꢀ
33ꢀ
LMD
VIN – x
0.1μF
680nH
LPF
LON
VIN
274ꢀ
18nF
0.1μF
Figure 51. Differential Input Configuration Using the AD8332 with Two-Pole, 16 MHz Low-Pass Filter
Rev. E | Page 22 of 56
Data Sheet
AD9228
CLOCK INPUT CONSIDERATIONS
in parallel with a 39 kΩ resistor (see Figure 55). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V and
therefore offers several selections for the drive logic voltage.
For optimum performance, the AD9228 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled to the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional biasing.
AD9510/AD9511/
AD9512/AD9513/
0.1µF
AD9514/AD9515
CLK+
CLK
OPTIONAL
100ꢀ
Figure 52 shows a preferred method for clocking the AD9228. The
low jitter clock source is converted from a single-ended signal
to a differential signal using an RF transformer. The back-to-
back Schottky diodes across the secondary transformer limit
clock excursions into the AD9228 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9228,
and it preserves the fast rise and fall times of the signal, which
are critical to low jitter performance.
50ꢀ*
CMOS DRIVER
CLK+
0.1µF
ADC
AD9228
CLK
0.1µF
CLK–
0.1µF
39kꢀ
*50ꢀ RESISTOR IS OPTIONAL
Figure 55. Single-Ended 1.8 V CMOS Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
50ꢀ*
CLK+
CLK
OPTIONAL
®
Mini-Circuits
100ꢀ
ADT1-1WT, 1:1Z
CMOS DRIVER
CLK
CLK+
0.1µF
0.1µF
0.1µF
0.1µF
XFMR
ADC
AD9228
CLK+
CLK+
100ꢀ
ADC
AD9228
CLK–
0.1µF
50ꢀ
CLK–
0.1µF
*50ꢀ RESISTOR IS OPTIONAL
SCHOTTKY
DIODES:
0.1µF
HSM2812
Figure 56. Single-Ended 3.3 V CMOS Sample Clock
Figure 52. Transformer-Coupled Differential Clock
Clock Duty Cycle Considerations
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 53. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock
drivers offers excellent jitter performance.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9228 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9228. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
0.1µF
CLK+
CLK
CLK+
ADC
AD9228
100ꢀ
PECL DRIVER
0.1µF
0.1µF
CLK–
CLK–
CLK
240ꢀ
240ꢀ
50ꢀ*
50ꢀ*
*50ꢀ RESISTORS ARE OPTIONAL
Figure 53. Differential PECL Sample Clock
AD9510/AD9511/
AD9512/AD9513/
Jitter in the rising edge of the input is an important concern, and it
is not reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates of less than
20 MHz nominal. The loop has a time constant associated with
it that must be considered in applications where the clock rate
can change dynamically. This requires a wait time of 1.5 ꢀs to
5 ꢀs after a dynamic clock frequency increase (or decrease)
before the DCS loop is relocked to the input signal. During the
period that the loop is not locked, the DCS loop is bypassed and
the internal device timing is dependent on the duty cycle of the
input clock signal. In such applications, it may be appropriate to
disable the duty cycle stabilizer. In all other applications,
enabling the DCS circuit is recommended to maximize ac
performance.
AD9514/AD9515
0.1µF
0.1µF
CLK+
CLK–
CLK
CLK+
ADC
AD9228
100ꢀ
LVDS DRIVER
CLK
0.1µF
0.1µF
CLK–
50ꢀ*
50ꢀ*
*50ꢀ RESISTORS ARE OPTIONAL
Figure 54. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
Rev. E | Page 2ꢁ of 56
AD9228
Data Sheet
Clock Jitter Considerations
Power Dissipation and Power-Down Mode
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
As shown in Figure 58 and Figure 59, the power dissipated by
the AD9228 is proportional to its sample rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 57).
180
160
140
120
100
80
360
340
320
300
280
260
240
220
200
180
AVDD CURRENT
TOTAL POWER
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9228.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
60
40
DRVDD CURRENT
20
0
10
15
20
25
30
35
40
ENCODE (MSPS)
Refer to the AN-501 Application Note and to the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
Figure 58. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 40 MSPS
250
480
460
440
420
400
380
360
340
320
300
130
RMS CLOCK JITTER REQUIREMENT
AVDD CURRENT
120
110
200
TOTAL POWER
16 BITS
100
90
80
70
60
50
40
150
100
14 BITS
12 BITS
10 BITS
50
0
DRVDD CURRENT
0.125 ps
0.25 ps
0.5 ps
1.0 ps
10
20
30
40
50
60
2.0 ps
ENCODE (MSPS)
30
1
10
100
1000
ANALOG INPUT FREQUENCY (MHz)
Figure 59. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS
Figure 57. Ideal SNR vs. Input Frequency and Jitter
Rev. E | Page 24 of 56
Data Sheet
AD9228
By asserting the PDWN pin high, the AD9228 is placed into
power-down mode. In this state, the ADC typically dissipates
3 mW. During power-down, the LVDS output drivers are placed
into a high impedance state. If any of the SPI features are changed
before the power-down feature is enabled, the chip continues to
function after PDWN is pulled low without requiring a reset. The
AD9228 returns to normal operating mode when the PDWN pin
is pulled low. This pin is both 1.8 V and 3.3 V tolerant.
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be less than 24 inches and
that the differential output traces be close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position is shown in Figure 60.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode: shorter cycles result in proportionally shorter wake-up
times. With the recommended 0.1 ꢀF and 2.2 ꢀF decoupling
capacitors on REFT and REFB, approximately 1 sec is required
to fully discharge the reference buffer decoupling capacitors and
approximately 375 ꢀs is required to restore full operation.
2.5ns/DIV
CH1 200mV/DIV = DCO
CH2 200mV/DIV = DATA
CH3 500mV/DIV = FCO
There are several other power-down options available when
using the SPI. The user can individually power down each
channel or put the entire device into standby mode. The latter
option allows the user to keep the internal PLL powered when
fast wake-up times (~600 ns) are required. See the Memory
Map section for more details on using these features.
Figure 60. AD9228-65, LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on standard FR-4 material is
shown in Figure 61. Figure 62 shows an example of trace lengths
exceeding 24 inches on standard FR-4 material. Notice that the
TIE jitter histogram reflects the decrease of the data eye opening
as the edge deviates from the ideal position. It is the user’s respon-
sibility to determine if the waveforms meet the timing budget of
the design when the trace lengths exceed 24 inches. Additional SPI
options allow the user to further increase the internal termination
(increasing the current) of all four outputs in order to drive longer
trace lengths (see Figure 63). Even though this produces sharper
rise and fall times on the data edges and is less prone to bit errors,
the power dissipation of the DRVDD supply increases when this
option is used. In addition, notice in Figure 63 that the histogram
is improved compared with that shown in Figure 62. See the
Memory Map section for more details.
Digital Outputs and Timing
The AD9228 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SDIO/ODM pin or SPI. The LVDS standard can further reduce the
overall power dissipation of the device by approximately 15 mW.
See the SDIO/ODM Pin section or Table 16 in the Memory Map
section for more information. The LVDS driver current is derived
on-chip and sets the output current at each output equal to a
nominal 3.5 mA. A 100 Ω differential termination resistor placed at
the LVDS receiver inputs results in a nominal 350 mV swing at
the receiver.
The AD9228 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
Rev. E | Page 25 of 56
AD9228
Data Sheet
EYE: ALL BITS
EYE: ALL BITS
ULS: 9599/15599
ULS: 10000/15600
400
200
500
0
0
–200
–400
–500
–1ns
–0.5ns
0ns
0.5ns
1ns
–1ns
–0.5ns
0ns
0.5ns
1ns
100
100
50
0
50
0
–150ps –100ps
–50ps
0ps
50ps
100ps
150ps
–100ps
0ps
100ps
Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Internal
Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4,
External 100 Ω Far Termination Only
ULS: 9600/15600
EYE: ALL BITS
200
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
0
Table 8. Digital Output Coding
(VIN + x) − (VIN − x),
Code Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D11 ... D0)
4ꢀ95
2ꢀ4±
2ꢀ4ꢂ
ꢀ
+1.ꢀꢀ
1111 1111 1111
1ꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ111 1111 1111
ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
–200
100
ꢀ.ꢀꢀ
−ꢀ.ꢀꢀꢀ4±±
−1.ꢀꢀ
–1ns
–0.5ns
0ns
0.5ns
1ns
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 780 Mbps
(12 bits × 65 MSPS = 780 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section for
details on enabling this feature.
50
0
–150ps –100ps
–50ps
0ps
50ps
100ps
150ps
Figure 62. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
Rev. E | Page 26 of 56
Data Sheet
AD9228
capturing. The FCO is used to signal the start of a new output
byte and is equal to the sample clock rate. See the timing
diagram shown in Figure 2 for more information.
Two output clocks are provided to assist in capturing data from
the AD9228. The DCO is used to clock the output data and is
equal to six times the sample clock (CLK) rate. Data is clocked
out of the AD9228 and must be captured on the rising and
falling edges of the DCO that supports double data rate (DDR)
Table 9. Flexible Output Test Modes
Output Test Mode
Bit Sequence
Subject to Data
Format Select
Pattern Name
Off (default)
Midscale short
Digital Output Word 1
Digital Output Word 2
ꢀꢀꢀꢀ
ꢀꢀꢀ1
N/A
N/A
Same
N/A
Yes
1ꢀꢀꢀ ꢀꢀꢀꢀ (±-bit)
1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (1ꢀ-bit)
1ꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (12-bit)
1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (14-bit)
ꢀꢀ1ꢀ
ꢀꢀ11
ꢀ1ꢀꢀ
+Full-scale short
−Full-scale short
Checkerboard
1111 1111 (±-bit)
Same
Same
Yes
Yes
No
11 1111 1111 (1ꢀ-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
ꢀꢀꢀꢀ ꢀꢀꢀꢀ (±-bit)
ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (1ꢀ-bit)
ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (12-bit)
ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (14-bit)
1ꢀ1ꢀ 1ꢀ1ꢀ (±-bit)
ꢀ1ꢀ1 ꢀ1ꢀ1 (±-bit)
1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ (1ꢀ-bit)
1ꢀ1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ (12-bit)
1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ (14-bit)
N/A
N/A
ꢀ1 ꢀ1ꢀ1 ꢀ1ꢀ1 (1ꢀ-bit)
ꢀ1ꢀ1 ꢀ1ꢀ1 ꢀ1ꢀ1 (12-bit)
ꢀ1 ꢀ1ꢀ1 ꢀ1ꢀ1 ꢀ1ꢀ1 (14-bit)
N/A
N/A
ꢀ1ꢀ1
ꢀ11ꢀ
ꢀ111
PN sequence long1
PN sequence short1
One-/zero-word toggle
Yes
Yes
No
1111 1111 (±-bit)
ꢀꢀꢀꢀ ꢀꢀꢀꢀ (±-bit)
11 1111 1111 (1ꢀ-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (1ꢀ-bit)
ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (12-bit)
ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (14-bit)
1ꢀꢀꢀ
1ꢀꢀ1
User input
1-/ꢀ-bit toggle
Register ꢀx19 to Register ꢀx1A
1ꢀ1ꢀ 1ꢀ1ꢀ (±-bit)
Register ꢀx1B to Register ꢀx1C
N/A
No
No
1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ (1ꢀ-bit)
1ꢀ1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ (12-bit)
1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ (14-bit)
1ꢀ1ꢀ
1ꢀ11
11ꢀꢀ
1× sync
ꢀꢀꢀꢀ 1111 (±-bit)
N/A
N/A
N/A
No
No
No
ꢀꢀ ꢀꢀꢀ1 1111 (1ꢀ-bit)
ꢀꢀꢀꢀ ꢀꢀ11 1111 (12-bit)
ꢀꢀ ꢀꢀꢀꢀ ꢀ111 1111 (14-bit)
One bit high
Mixed frequency
1ꢀꢀꢀ ꢀꢀꢀꢀ (±-bit)
1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (1ꢀ-bit)
1ꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (12-bit)
1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ (14-bit)
1ꢀ1ꢀ ꢀꢀ11 (±-bit)
1ꢀ ꢀ11ꢀ ꢀꢀ11 (1ꢀ-bit)
1ꢀ1ꢀ ꢀꢀ11 ꢀꢀ11 (12-bit)
1ꢀ 1ꢀꢀꢀ ꢀ11ꢀ ꢀ111 (14-bit)
1 All test mode options except PN sequence short and PN sequence long can support ±- to 14-bit word lengths in order to verify data capture to the receiver.
Rev. E | Page 2ꢂ of 56
AD9228
Data Sheet
Table 10. PN Sequence
When the SPI is used, the DCO phase can be adjusted in 60°
increments relative to the data edge. This enables the user to
refine system timing margins if required. The default DCO+
and DCO− timing, as shown in Figure 2, is 90° relative to the
output data edge.
Initial
Value
First Three Output Samples
(MSB First)
Sequence
PN Sequence Short
PN Sequence Long
ꢀxꢀdf
ꢀxdf9, ꢀxꢁ5ꢁ, ꢀxꢁꢀ1
ꢀx591, ꢀxfdꢂ, ꢀxꢀaꢁ
ꢀx29b±ꢀa
Consult the Memory Map section for information on how to
change these additional digital output timing features through
the SPI.
An 8-, 10-, or 14-bit serial stream can also be initiated from the
SPI. This allows the user to implement and test compatibility to
lower and higher resolution systems. When changing the
resolution to an 8- or 10-bit serial stream, the data stream is
shortened. See Figure 3 for the 10-bit example. However, when
using the 14-bit option, the data stream stuffs two 0s at the end
of the 14-bit serial data.
SDIO/ODM Pin
The SDIO/ODM pin is for use in applications that do not require
SPI mode operation. This pin can enable a low power, reduced
signal option (similar to the IEEE 1596.3 reduced range link
output standard) if it and the CSB pin are tied to AVDD during
device power-up. This option should only be used when the
digital output trace lengths are less than 2 inches from the LVDS
receiver. When this option is used, the FCO, DCO, and outputs
function normally, but the LVDS signal swing of all channels is
reduced from 350 mV p-p to 200 mV p-p, allowing the user to
further reduce the power on the DRVDD supply.
When the SPI is used, all of the data outputs can also be
inverted from their nominal state. This is not to be confused
with inverting the serial stream to an LSB-first mode. In default
mode, as shown in Figure 2, the MSB is first in the data output
serial stream. However, this can be inverted so that the LSB is
first in the data output serial stream (see Figure 4).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Table 9 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns do not adhere to the data format select option. In
addition, custom user-defined test patterns can be assigned in
the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode
options except PN sequence short and PN sequence long can
support 8- to 14-bit word lengths in order to verify data capture
to the receiver.
For applications where this pin is not used, it should be tied low.
In this case, the device pin can be left open, and the 30 kΩ internal
pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant.
If applications require this pin to be driven from a 3.3 V logic level,
insert a 1 kΩ resistor in series with this pin to limit the current.
Table 11. Output Driver Mode Pin Settings
Resulting
Output Standard FCO and DCO
Resulting
Selected ODM ODM Voltage
Normal
1ꢀ kΩ to AGND ANSI-644
ANSI-644
Operation
(default)
(default)
ODM
AVDD
Low power,
reduced
Low power,
reduced
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 − 1 or 511 bits. A
signal option
signal option
description of the PN sequence and how it is generated can be
found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The
only difference is that the starting value must be a specific value
instead of all 1s (see Table 10 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 − 1 or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value must be a specific
value instead of all 1s (see Table 10 for the initial values) and the
AD9228 inverts the bit stream with relation to the ITU standard.
Rev. E | Page 2± of 56
Data Sheet
AD9228
SCLK/DTP Pin
RBIAS Pin
The SCLK/DTP pin is for use in applications that do not require
SPI mode operation. This pin can enable a single digital test
pattern if it and the CSB pin are held high during device power-
up. When SCLK/DTP is tied to AVDD, the ADC channel
outputs shift out the following pattern: 1000 0000 0000. The
FCO and DCO function normally while all channels shift out the
repeatable test pattern. This pattern allows the user to perform
timing alignment adjustments among the FCO, DCO, and output
data. For normal operation, this pin should be tied to AGND
through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant.
To set the internal core bias current of the ADC, place a resistor
(nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The
resistor current is derived on-chip and sets the AVDD current of
the ADC to a nominal 232 mA at 65 MSPS. Therefore, it is
imperative that at least a 1% tolerance on this resistor be used to
achieve consistent performance.
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the
AD9228. It is gained up internally by a factor of 2, setting VREF
to 1.0 V, which results in a full-scale differential input span of
2 V p-p. The VREF is set internally by default; however, the VREF
pin can be driven externally with a 1.0 V reference to improve
accuracy.
Table 12. Digital Test Pattern Pin Settings
Resulting
Resulting
Selected DTP DTP Voltage
D + x and D − x FCO and DCO
Normal
1ꢀ kΩ to AGND Normal
Normal operation
Operation
operation
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9228. The recommended capacitor values and
configurations for the AD9228 reference pin are shown in
Figure 64.
DTP
AVDD
1ꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ Normal operation
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map
section for information about the options available.
CSB Pin
Table 13. Reference Settings
The CSB pin should be tied to AVDD for applications that do
not require SPI mode operation. By tying CSB high, all SCLK
and SDIO information is ignored. This pin is both 1.8 V and
3.3 V tolerant.
Resulting
Differential
Selected Mode SENSE Voltage Resulting VREF (V) Span (V p-p)
External
AVDD
N/A
2 × external
reference
Reference
Internal,
AGND to ꢀ.2 V
1.ꢀ
2.ꢀ
2 V p-p FSR
Rev. E | Page 29 of 56
AD9228
Data Sheet
External Reference Operation
Internal Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. Figure 67 shows the typical drift characteristics
of the internal reference in 1 V mode.
A comparator within the AD9228 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 64), setting VREF to 1 V.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. The external
reference is loaded with an equivalent 6 kΩ load. An internal
reference buffer generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. Therefore, the
external reference must be limited to a nominal 1.0 V.
The REFT and REFB pins establish the input span of the ADC
core from the reference configuration. The analog input full-
scale range of the ADC equals twice the voltage of the reference
pin for either an internal or an external reference configuration.
If the reference of the AD9228 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 66
depicts how the internal reference voltage is affected by loading.
5
0
–5
VIN + x
VIN – x
REFT
–10
–15
–20
–25
–30
0.1µF
+
ADC
CORE
0.1µF
2.2µF
REFB
0.1µF
VREF
0.1µF
1µF
0.5V
SELECT
LOGIC
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
SENSE
CURRENT LOAD (mA)
Figure 66. VREF Accuracy vs. Load
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.16
–0.18
Figure 64. Internal Reference Configuration
VIN + x
VIN – x
REFT
0.1µF
0.1µF
REFB
+
ADC
CORE
2.2µF
0.1µF
VREF
1µF
0.1µF
AVDD
0.5V
–40
–20
0
20
40
60
80
SELECT
LOGIC
TEMPERATURE (°C)
SENSE
Figure 67. Typical VREF Drift
Figure 65. External Reference Operation
Rev. E | Page ꢁꢀ of 56
Data Sheet
AD9228
SERIAL PORT INTERFACE (SPI)
The AD9228 serial port interface allows the user to configure the
converter for specific functions or operations through a structured
register space provided in the ADC. This may provide the user
with additional flexibility and customization, depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, as documented
in the Memory Map section. Detailed operational information
can be found in the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
In addition to the operation modes, the SPI port configuration
influences how the AD9228 operates. For applications that do
not require a control port, the CSB line can be tied and held high.
This places the remainder of the SPI pins into their secondary
modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin
sections. CSB can also be tied low to enable 2-wire mode. When
CSB is tied low, SCLK and SDIO are the only pins required for
communication. Although the device is synchronized during
power-up, the user should ensure that the serial port remains
synchronized with the CSB line when using this mode. When
operating in 2-wire mode, it is recommended to use a 1-, 2-,
or 3-byte transfer exclusively. Without an active CSB line,
streaming mode can be entered but not exited.
There are three pins that define the SPI: SCLK, SDIO, and CSB
(see Table 14). The SCLK pin is used to synchronize the read
and write data presented to the ADC. The SDIO pin is a dual-
purpose pin that allows data to be sent to and read from the
internal ADC memory map registers. The CSB pin is an active
low control that enables or disables the read and write cycles.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the SDIO pin to change from an
input to an output at the appropriate point in the serial frame.
Table 14. Serial Port Pins
Pin
Function
SCLK
Serial Clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
Serial Data Input/Output. A dual-purpose pin. The typical
role for this pin is as an input or output, depending on
the instruction sent and the relative position in the
timing frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
SDIO
CSB
Chip Select Bar (Active Low). This control gates the read
and write cycles.
HARDWARE INTERFACE
The pins described in Table 14 compose the physical interface
between the user’s programming device and the serial port of
the AD9228. The SCLK and CSB pins function as inputs when
using the SPI. The SDIO pin is bidirectional, functioning as an
input during write phases and as an output during readback.
The falling edge of the CSB in conjunction with the rising edge of
the SCLK determines the start of the framing sequence. During an
instruction phase, a 16-bit instruction is transmitted followed by
one or more data bytes, which is determined by Bit Field W0 and
Bit Field W1. An example of the serial timing and its definitions
can be found in Figure 69 and Table 15. During normal operation,
CSB is used to signal to the device that SPI commands are to be
received and processed. When CSB is brought low, the device
processes SCLK and SDIO to obtain instructions. Normally,
CSB remains low until the communication cycle is complete.
However, if connected to a slow device, CSB can be brought
high between bytes, allowing older microcontrollers enough
time to transfer data into shift registers. CSB can be stalled
when transferring one, two, or three bytes of data. When W0
and W1 are set to 11, the device enters streaming mode and
continues to process data, either reading or writing, until
CSB is taken high to end the communication cycle. This allows
complete memory transfers without requiring additional instruc-
tions. Regardless of the mode, if CSB is taken high in the middle
of a byte transfer, the SPI state machine is reset and the device
waits for a new instruction.
If multiple SDIO pins share a common connection, care should
be taken to ensure that proper VOH levels are met. Assuming the
same load for each AD9228, Figure 68 shows the number of
SDIO pins that can be connected together and the resulting VOH
level. This interface is flexible enough to be controlled by either
serial PROMS or PIC microcontrollers, providing the user with
an alternative method, other than a full SPI controller, to
program the ADC (see the AN-812 Application Note).
Rev. E | Page ꢁ1 of 56
AD9228
Data Sheet
1.800
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
1.745
1.740
1.735
1.730
1.725
1.720
If the user chooses not to use the SPI, these dual-function pins
serve their secondary functions when the CSB is strapped to
AVDD during device power-up. See the Theory of Operation
section for details on which pin-strappable functions are
supported on the SPI pins.
For users who wish to operate the ADC without using the
SPI, remove any connections from the CSB, SCLK/DTP, and
SDIO/ODM pins. By disconnecting these pins from the control
bus, the ADC can function in its most basic operation. Each
of these pins has an internal termination that floats to its
respective level.
1.715
0
10
20
30
40
50
60
70
80
90
100
NUMBER OF SDIO PINS CONNECTED TOGETHER
Figure 68. SDIO Pin Loading
tDS
tHI
tCLK
tH
tS
tDH
tLO
CSB
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
Figure 69. Serial Timing Details
Table 15. Serial Timing Definitions
Parameter
Timing (Minimum, ns)
Description
tDS
5
2
4ꢀ
5
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
tDH
tCLK
tS
Setup time between CSB and SCLK
tH
2
Hold time between CSB and SCLK
tHI
tLO
tEN_SDIO
16
16
1ꢀ
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 69)
tDIS_SDIO
1ꢀ
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 69)
Rev. E | Page ꢁ2 of 56
Data Sheet
AD9228
MEMORY MAP
READING THE MEMORY MAP TABLE
RESERVED LOCATIONS
Each row in the memory map register table (Table 16) has eight
address locations. The memory map is divided into three sections:
the chip configuration register map (Address 0x00 to Address 0x02),
the device index and transfer register map (Address 0x05 and
Address 0xFF), and the ADC functions register map (Address 0x08
to Address 0x22).
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES
When the AD9228 comes out of a reset, critical registers are
preloaded with default values. These values are indicated in
Table 16, where an X refers to an undefined feature.
The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second
rightmost column. The (MSB) Bit 7 column is the start of the
default hexadecimal value given. For example, Address 0x09, the
clock register, has a default value of 0x01, meaning that Bit 7 = 0,
Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and
Bit 0 = 1, or 0000 0001 in binary. This setting is the default for
the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6
of this address followed by a 0x01 in Register 0xFF (transfer bit),
the duty cycle stabilizer turns off. It is important to follow each
writing sequence with a transfer bit to update the SPI registers. For
more information on this and other functions, consult the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
Rev. E | Page ꢁꢁ of 56
AD9228
Data Sheet
Table 16. Memory Map Register
Default
Value
(Hex)
Addr.
(Hex)
(MSB)
Bit 7
(LSB)
Bit 0
Default Notes/
Comments
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Chip Configuration Registers
ꢀꢀ
chip_port_config
ꢀ
LSB first
1 = on
Soft
reset
1
1
Soft
reset
LSB first
1 = on
ꢀ
ꢀx1±
The nibbles
should be
ꢀ = off
(default)
1 = on
ꢀ = off
(default)
1 = on
ꢀ = off
(default)
ꢀ = off
(default)
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless
of shift mode.
ꢀ1
ꢀ2
chip_id
±-bit Chip ID Bits [ꢂ:ꢀ]
(AD922± = ꢀxꢀ2), (default)
ꢀxꢀ2
Default is unique
chip ID, different
for each device.
This is a read-
only register.
chip_grade
X
Child ID [6:4]
X
X
X
X
Read
only
Child ID used to
differentiate
graded devices.
(identify device variants of Chip ID)
ꢀꢀꢀ = 65 MSPS
ꢀꢀ1 = 4ꢀ MSPS
Device Index and Transfer Registers
ꢀ5
device_index_A
X
X
X
Clock
Channel
DCO
1 = on
ꢀ = off
Clock
Channel
FCO
1 = on
ꢀ = off
Data
Channel
D
Data
Channel
C
Data
Channel
B
Data
Channel
A
ꢀxꢀF
ꢀxꢀꢀ
Bits are set to
determine which
on-chip device
receives the next
write command.
1 = on
1 = on
1 = on
1 = on
(default) (default) (default) (default)
(default) (default) ꢀ = off
ꢀ = off
ꢀ = off
ꢀ = off
FF
device_update
X
X
X
X
X
X
SW
Synchronously
transfers data
from the master
shift register to
the slave.
transfer
1 = on
ꢀ = off
(default)
ADC Functions
ꢀ±
modes
X
X
X
X
X
X
X
X
X
X
Internal power-down mode
ꢀꢀꢀ = chip run (default)
ꢀꢀ1 = full power-down
ꢀ1ꢀ = standby
ꢀxꢀꢀ
ꢀxꢀ1
Determines
various generic
modes of chip
operation.
ꢀ11 = reset
ꢀ9
clock
X
X
Duty
Turns the
cycle
internal duty
cycle stabilizer
on and off.
stabilizer
1 = on
(default)
ꢀ = off
ꢀD
test_io
User test mode
ꢀꢀ = off (default)
ꢀ1 = on, single alternate 1 = on
1ꢀ = on, single once
11 = on, alternate once
Reset PN Reset
long gen PN short
ꢀxꢀꢀ
When this reg-
ister is set, the
test data is placed
on the output
pins in place of
normal data.
Output test mode—see Table 9 in the
Digital Outputs and Timing section
ꢀꢀꢀꢀ = off (default)
ꢀꢀꢀ1 = midscale short
ꢀꢀ1ꢀ = +FS short
gen
ꢀ = off
1 = on
(default) ꢀ = off
(default)
ꢀꢀ11 = −FS short
ꢀ1ꢀꢀ = checkerboard output
ꢀ1ꢀ1 = PN 2ꢁ sequence
ꢀ11ꢀ = PN 9 sequence
ꢀ111 = one-/zero-word toggle
1ꢀꢀꢀ = user input
1ꢀꢀ1 = 1-/ꢀ-bit toggle
1ꢀ1ꢀ = 1× sync
1ꢀ11 = one bit high
11ꢀꢀ = mixed bit frequency
(format determined by output_mode)
Rev. E | Page ꢁ4 of 56
Data Sheet
AD9228
Default
Value
(Hex)
Addr.
(Hex)
(MSB)
Bit 7
(LSB)
Bit 0
Default Notes/
Comments
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
14
output_mode
X
ꢀ = LVDS
ANSI-644
(default)
1 = LVDS
low power
(IEEE
X
X
X
Output
invert
1 = on
ꢀ = off
(default)
ꢀꢀ = offset binary
(default)
ꢀ1 = twos
ꢀxꢀꢀ
Configures the
outputs and the
format of the
data.
complement
1596.ꢁ
similar)
15
output_adjust
X
X
Output driver
termination
ꢀꢀ = none (default)
ꢀ1 = 2ꢀꢀ Ω
1ꢀ = 1ꢀꢀ Ω
11 = 1ꢀꢀ Ω
X
X
X
X
ꢀxꢀꢀ
Determines
LVDS or other
output properties.
Primarily func-
tions to set the
LVDS span and
common-mode
levels in place of
an external
resistor.
16
output_phase
X
X
X
X
ꢀꢀ11 = output clock phase adjust
(ꢀꢀꢀꢀ through 1ꢀ1ꢀ)
ꢀꢀꢀꢀ = ꢀ° relative to data edge
ꢀꢀꢀ1 = 6ꢀ° relative to data edge
ꢀꢀ1ꢀ = 12ꢀ° relative to data edge
ꢀꢀ11 = 1±ꢀ° relative to data edge (default)
ꢀ1ꢀ1 = ꢁꢀꢀ° relative to data edge
ꢀ11ꢀ = ꢁ6ꢀ° relative to data edge
1ꢀꢀꢀ = 4±ꢀ° relative to data edge
1ꢀꢀ1 = 54ꢀ° relative to data edge
1ꢀ1ꢀ = 6ꢀꢀ° relative to data edge
1ꢀ11 to 1111 = 66ꢀ° relative to data edge
ꢀxꢀꢁ
On devices that
utilize global
clock divide,
determines
which phase of
the divider
output is used to
supply the
output clock.
Internal latching
is unaffected.
19
1A
1B
1C
21
user_patt1_lsb
user_patt1_msb
user_patt2_lsb
user_patt2_msb
serial_control
Bꢂ
B6
B14
B6
B5
B1ꢁ
B5
B4
B12
B4
Bꢁ
B2
B1
B9
B1
B9
Bꢀ
B±
Bꢀ
B±
ꢀxꢀꢀ
ꢀxꢀꢀ
ꢀxꢀꢀ
ꢀxꢀꢀ
ꢀxꢀꢀ
User-defined
pattern, 1 LSB.
B15
Bꢂ
B11
Bꢁ
B1ꢀ
B2
User-defined
pattern, 1 MSB.
User-defined
pattern, 2 LSB.
B15
B14
X
B1ꢁ
X
B12
X
B11
B1ꢀ
User-defined
pattern, 2 MSB.
LSB first
1 = on
ꢀ = off
<1ꢀ
MSPS,
low
encode
rate
ꢀꢀꢀ = 12 bits (default, normal bit
stream)
ꢀꢀ1 = ± bits
ꢀ1ꢀ = 1ꢀ bits
ꢀ11 = 12 bits
Serial stream
control. Default
causes MSB first
and the native
bit stream
(default)
mode
1 = on
ꢀ = off
(default)
1ꢀꢀ = 14 bits
(global).
22
serial_ch_stat
X
X
X
X
X
X
Channel
output
reset
Channel
power-
down
ꢀxꢀꢀ
Used to power
down individual
sections of a
1 = on
ꢀ = off
1 = on
ꢀ = off
converter (local).
(default) (default)
Rev. E | Page ꢁ5 of 56
AD9228
Data Sheet
Power and Ground Recommendations
Exposed Paddle Thermal Heat Slug Recommendations
When connecting power to the AD9228, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These should be located close to the point of
entry at the PC board level and close to the parts, with minimal
trace lengths.
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9228. An
exposed continuous copper plane on the PCB should mate to
the AD9228 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
only guarantees one tie point. See Figure 70 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the AN-772 Application Note,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP).
A single PC board ground plane should be sufficient when
using the AD9228. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance can be easily achieved.
SILKSCREEN PARTITION
PIN 1 INDICATOR
Figure 70. Typical PCB Layout
Rev. E | Page ꢁ6 of 56
Data Sheet
AD9228
EVALUATION BOARD
board individually. Use P501 to connect a different supply for
each section. At least one 1.8 V supply is needed for AVDD_DUT
and DRVDD_DUT; however, it is recommended that separate
supplies be used for analog and digital signals and that each
supply have a current capability of 1 A. To operate the evaluation
board using the VGA option, a separate 5.0 V analog supply
(AVDD_5 V) is needed. To operate the evaluation board using
the SPI and alternate clock options, a separate 3.3 V analog
supply (AVDD_3.3 V) is needed in addition to the other
supplies.
The AD9228 evaluation board provides all of the support cir-
cuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially using a
transformer (default) or an AD8332 driver. The ADC can also be
driven in a single-ended fashion. Separate power pins are provided
to isolate the DUT from the drive circuitry of the AD8332. Each
input configuration can be selected by changing the connection
of various jumpers (see Figure 73 to Figure 77). Figure 71 shows
the typical bench characterization setup used to evaluate the ac
performance of the AD9228. It is critical that the signal sources
used for the analog input and clock have very low phase noise
(<1 ps rms jitter) to realize the optimum performance of the
converter. Proper filtering of the analog input signal to remove
harmonics and lower the integrated or broadband noise at the
input is also necessary to achieve the specified noise performance.
INPUT SIGNALS
When connecting the clock and analog sources to the evaluation
board, use clean signal generators with low phase noise, such as
Rohde & Schwarz SMHU or HP8644B signal generators or the
equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial cable.
Enter the desired frequency and amplitude from the ADC speci-
fications tables. Typically, most Analog Devices evaluation boards
can accept approximately 2.8 V p-p or 13 dBm sine wave input
for the clock. When connecting the analog input source, it is
recommended to use a multipole, narrow-band, band-pass filter
with 50 Ω terminations. Good choices of such band-pass filters are
available from TTE, Allen Avionics, and K&L Microwave, Inc.
The filter should be connected directly to the evaluation board
if possible.
See Figure 73 to Figure 81 for the complete schematics and
layout diagrams demonstrating the routing and grounding
techniques that should be applied at the system level.
POWER SUPPLIES
This evaluation board has a wall-mountable switching power
supply that provides a 6 V, 2 A maximum output. Connect the
supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to
63 Hz. The other end of the supply is a 2.1 mm inner diameter
jack that connects to the PCB at P503. Once on the PC board,
the 6 V supply is fused and conditioned before connecting to
three low dropout linear regulators that supply the proper bias
to each of the various sections on the board.
OUTPUT SIGNALS
The default setup uses the Analog Devices HSC-ADC-FIFO5-
INTZ to interface with the Analog Devices standard dual-channel
FIFO data capture board (HCS-ADC-EVALCZ). Two of the
eight channels can be evaluated at the same time. For more
information on the channel settings and optional settings of
these boards, visit www.analog.com/FIFO.
When operating the evaluation board in a nondefault condition,
L504 to L507 can be removed to disconnect the switching
power supply. This enables the user to bias each section of the
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
6V DC
2A MAX
5.0V
1.8V
1.8V
3.3V
3.3V
–
+
–
+
–
+
–
+
–
+
SWITCHING
POWER
SUPPLY
PC
RUNNING
ADC
ROHDE & SCHWARZ,
ANALYZER
AND SPI
USER
INTERPOSER
BOARD
HSC-ADC-EVALCZ
FIFO DATA
CAPTURE
SMHU,
2V p-p SIGNAL
SYNTHESIZER
BAND-PASS
FILTER
XFMR
INPUT
AD9228
EVALUATION BOARD
SOFTWARE
BOARD
CH A TO CH D
12-BIT
USB
CONNECTION
ROHDE & SCHWARZ,
SMHU,
SERIAL
CLK
LVDS
2V p-p SIGNAL
SYNTHESIZER
SPI
SPI
SPI
SPI
Figure 71. Evaluation Board Connection
Rev. E | Page ꢁꢂ of 56
AD9228
Data Sheet
A differential LVPECL clock can also be used to clock the
ADC input using the AD9515 (U202). Populate R225 and
R227 with 0 Ω resistors and remove R217 and R218 to
disconnect the default clock path inputs. In addition, populate
C207 and C208 with a 0.1 μF capacitor and remove C210 and
C211 to disconnect the default clock path outputs. The
AD9515 has many pin-strappable options that are set to a
default mode of operation. Consult the AD9515 data sheet
for more information about these and other options.
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
The following is a list of the default and optional settings or
modes allowed on the AD9228 Rev. A evaluation board.
POWER: Connect the switching power supply that is
provided with the evaluation kit between a rated 100 V
ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P503.
AIN: The evaluation board is set up for a transformer-
coupled analog input with an optimum 50 Ω impedance
match of 200 MHz of bandwidth (see Figure 72). For more
bandwidth response, the differential capacitor across the
analog inputs can be changed or removed. The common
mode of the analog inputs is developed from the center tap
of the transformer or AVDD_DUT/2.
In addition, an on-board oscillator is available on the OSC201
and can act as the primary clock source. The setup is quick
and involves installing R212 with a 0 Ω resistor and setting
the enable jumper (J205) to the on position. If the user wishes
to employ a different oscillator, two oscillator footprint options
are available (OSC201) to check the ADC performance.
0
PDWN: To enable the power-down feature, short J201 to
AVDD on the PDWN pin.
–2
–3dB CUTOFF = 200MHz
–4
–6
SCLK/DTP: To enable the digital test pattern on the digital
outputs of the ADC, use J204. If J204 is tied to AVDD during
device power-up, Test Pattern 1000 0000 0000 is enabled. See
the SCLK/DTP Pin section for details.
–8
–10
–12
–14
–16
SDIO/ODM: To enable the low power, reduced signal option
(similar to the IEEE 1595.3 reduced range link LVDS output
standard), use J203. If J203 is tied to AVDD during device
power-up, it enables the LVDS outputs in a low power,
reduced signal option from the default ANSI-644 standard.
This option changes the signal swing from 350 mV p-p to
200 mV p-p, reducing the power of the DRVDD supply. See
the SDIO/ODM Pin section for more details.
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
Figure 72. Evaluation Board Full-Power Bandwidth
VREF: VREF is set to 1.0 V by tying the SENSE pin to
ground, R237. This causes the ADC to operate in 2.0 V p-p
full-scale range. A separate external reference option using
the ADR510 is also included on the evaluation board.
Populate R231 and R235 and remove C214. Proper use of the
VREF options is noted in the Voltage Reference section.
CSB: To enable processing of the SPI information on the
SDIO and SCLK pins, tie J202 low in the always enable
mode. To ignore the SDIO and SCLK information, tie J202
to AVDD.
Non-SPI Mode: For users who wish to operate the DUT
without using SPI, remove Jumpers J302, J303, and J304.
This disconnects the CSB, SCLK/DTP, and SDIO/ODM pins
from the control bus, allowing the DUT to operate in its
simplest mode. Each of these pins has internal termination
and will float to its respective level.
RBIAS: RBIAS has a default setting of 10 kΩ (R201) to
ground and is used to set the ADC core bias current.
CLOCK: The default clock input circuitry is derived from a
simple transformer-coupled circuit using a high bandwidth
1:1 impedance ratio transformer (T201) that adds a very
low amount of jitter to the clock path. The clock input is
50 Ω terminated and ac-coupled to handle single-ended
sine wave types of inputs. The transformer converts the
single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.
D + x, D − x: If an alternative data capture method to the setup
shown in Figure 73 is used, optional receiver terminations,
R206 to R211, can be installed next to the high speed back-
plane connector.
Rev. E | Page ꢁ± of 56
Data Sheet
AD9228
ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
Populate R101, R114, R127, and R140 with 0 Ω resistors in
the analog input path.
The following is a brief description of the alternative analog input
drive configuration using the AD8332 dual VGA. If this drive
option is in use, some components may need to be populated, in
which case all the necessary components are listed in Table 17. For
more details on the AD8332 dual VGA, including how it works
and its optional pin settings, consult the AD8332 data sheet.
Populate R105, R113, R118, R124, R131, R137, R151, and
R160 with 0 Ω resistors in the analog input path to connect
the AD8332.
Populate R152, R153, R154, R155, R156, R157, R158, R159,
C103, C105, C110, C112, C117, C119, C124, and C126
with 10 kΩ resistors to provide an input common-mode
level to the ADC analog inputs.
To configure the analog input to drive the VGA instead of the
default transformer option, the following components need to
be removed and/or changed.
Remove R305, R306, R313, R314, R405, R406, R412, and
R424 to configure the AD8332.
Remove R102, R115, R128, R141, R161, R162, R163, R164,
T101, T102, T103, and T104 in the default analog input path.
In this configuration, L301 to L308 and L401 to L408 are
populated with 0 Ω resistors to allow signal connection and use
of a filter if additional requirements are necessary.
Rev. E | Page ꢁ9 of 56
AD9228
Data Sheet
AVDD_DUT
R105
DNP
R152
DNP
CH_A
C101
FB102 R108
R104
0ꢀ
P102
DNP
T101
0.1µF
10ꢀ 33ꢀ
VGA INPUT CONNECTION
INH1
1
6
VIN_A
AIN
R106
DNP
CHANNEL A
P101
R101
DNP
R161
2
3
5
4
R109
1kꢀ
C103
C104
2.2pF
CM1
CM1
499ꢀ
DNP
AIN
R107
DNP
R113
DNP
FB101
10ꢀ
R103
0ꢀ
C102
0.1µF
R102
64.9ꢀ
VIN_A
CH_A
CM1
FB103 R110
C105
DNP
R156
DNP
10ꢀ
33ꢀ
E101
AVDD_DUT
C106
DNP
R111
1kꢀ
C107
0.1µF
R112
1kꢀ
AVDD_DUT
AVDD_DUT
R118
DNP
VGA INPUT CONNECTION
INH2
R153
DNP
CH_B
CHANNEL B
P103
FB105 R121
R114
DNP
T102
10ꢀ 33ꢀ
1
6
AIN
VIN_B
FB104
10ꢀ
R119
DNP
R115
64.9ꢀ
C108
0.1µF
R162
2
3
5
4
R123
1kꢀ
P104
DNP
C110
C111
2.2pF
CM2
CM2
499ꢀ
DNP
R120
DNP
R124
DNP
R116
0ꢀ
AIN
C109
0.1µF
E102
VIN_B
CH_B
CM2
R117
0ꢀ
FB106 R122
C112
DNP
R157
DNP
10ꢀ
33ꢀ
AVDD_DUT
C113
DNP
R125
1kꢀ
C114
0.1µF
R126
1kꢀ
AVDD_DUT
AVDD_DUT
R131
DNP
R154
DNP
CH_C
C115
FB108 R134
P106
DNP
R130
0ꢀ
T103
0.1µF
10ꢀ 33ꢀ
VGA INPUT CONNECTION
INH3
1
6
VIN_C
AIN
R132
DNP
CHANNEL C
P105
R127
DNP
R163
2
3
5
4
R135
1kꢀ
C117
C118
2.2pF
CM3
CM3
499ꢀ
DNP
AIN
R133
DNP
R137
DNP
FB107
10ꢀ
R129
0ꢀ
C116
0.1µF
R128
64.9ꢀ
VIN_C
CH_C
CM3
FB109 R136
C119
DNP
R158
DNP
10ꢀ
33ꢀ
E103
AVDD_DUT
C120
DNP
R138
1kꢀ
C121
0.1µF
R139
1kꢀ
AVDD_DUT
AVDD_DUT
R151
DNP
VGA INPUT CONNECTION
INH4
R155
DNP
CH_D
CHANNEL D
P107
FB111 R146
R140
DNP
T104
10ꢀ 33ꢀ
1
6
AIN
VIN_D
FB110
R144
DNP
R141
64.9ꢀ
C122
10ꢀ
0.1µF
R164
499ꢀ
2
3
5
4
R148
1kꢀ
C124
DNP
C125
CM4
P108
CM4
2.2pF
DNP
R145
DNP
R160
DNP
R143
0ꢀ
AIN
C123
0.1µF
R142
VIN_D
CH_D
CM4
0ꢀ
FB112 R147
C126
DNP
R159
DNP
10ꢀ
33ꢀ
E104
AVDD_DUT
C127
DNP
R149
1kꢀ
C128
0.1µF
R150
1kꢀ
AVDD_DUT
DNP: DO NOT POPULATE
Figure 73. Evaluation Board Schematic, DUT Analog Inputs
Rev. E | Page 4ꢀ of 56
Data Sheet
AD9228
0 1 6 0 5 7 2 7 -
AVDD_DUT
CW
S 0
S 1
S 2
S 3
S 4
S 5
S 6
S 7
S 8
2 5
1 6
1 5
1 4
1 3
1 2
1 1
1 0
2
2
2
2
1
2
Ω k 1 0
3 3
3 1
1
0 5 R 2
3
V –
D
G N
V S
T E R S
Ω 0 k 1 0
0 4 R 2
P N - Ω D 0 1 0 k
6 7 R 2
9
D - N Ω P k 1 0 0
Ω 0 k 1 0
0 3 R 2
S 9
8
6 6 R 2
0
S 1
3 2
7
F E V R
6
B – V I N
+ N B V I
B _ V I N
B _ N V I
3 7
3 8
3 9
4 0
4 1
O
O
D C
D C
+ O D C
2 4
– O D C
O + F C
2 3
2 2
2 1
2 0
D D A V
D U T D D A _ V
O
O
A
A
B
B
C
C
F C
F C
C H
C H
C H
C H
C H
C H
S A I R B
S E N S E
F E V R
B F R E
O – F C
T U D E S _ S V E N
T U _ D V R E F
A
B
C
D
D +
4 2
D – A
1 9
4 3
4 4
4 5
4 6
4 7
4 8
D +
1 8
D – B
1
T
R E F
D D A V
D D A V
+ N C V I
3
1 7
D U T D D A _ V
D U T D D A _ V
C _ N V I
D +
1 6
D – C
1 5
D
D
C H
C H
D +
1 4
D – D
C _ V I N
C – V I N
1 3
Figure 74. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface
Rev. E | Page 41 of 56
AD9228
Data Sheet
POPULATE L301-L308 WITH 0ꢀ
RESISTORS OR DESIGN YOUR
OWN FILTER.
R301
DNP
R302
DNP
EXTERNAL VARIABLE GAIN DRIVE
VG
C302
DNP
C301
DNP
VARIABLE GAIN CIRCUIT
L301
0ꢀ
L302 L303
L304
0ꢀ
(0-1.0V DC)
VG
0ꢀ
0ꢀ
GND
CW
AVDD_5V
C303
C304
L307
0ꢀ
L306
0ꢀ
L305 DNP
DNP L308
R320
39kꢀ
R319
10kꢀ
0ꢀ
0ꢀ
R303
DNP
R304
DNP
C305
0.1µF
C306 C307
0.1µF 0.1µF
C308
0.1µF
R306
374ꢀ
R305
374ꢀ
R311
C309
1000pF
10kꢀ
DNP
C310
0.1µF
R307
187ꢀ
R308
187ꢀ
R309
187ꢀ
R310
187ꢀ
R312
10kꢀ
U301
25
R313
10kꢀ
DNP
R314
ENBV
ENBL
HILO
VCM1
VIN1
VIP1
COM1
LOP1
RCLMP
16
26
27
28
29
30
31
32
10kꢀ
VG
GAIN
MODE
VCM2
VIN2
VIP2
COM2
LOP2
15
14
13
12
11
10
9
DNP
AD8332
C311
0.1µF
C313
0.1µF
C312
0.1µF
C314
0.1µF
R316
C320
0.1µF
R317
274ꢀ
C321
0.1µF
274ꢀ
R315 C315
10kꢀ 10µF
C316
0.1µF
C325
0.1µF
C326
10µF
R318
10kꢀ
C317
0.018µF
C322
0.018µF
C318
22pF
C323
22pF
L309
120nH
L310
120nH
C319
0.1µF
C324
0.1µF
DNP: DO NOT POPULATE
INH4
INH3
Figure 75. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit
Rev. E | Page 42 of 56
Data Sheet
AD9228
C _ H A D S O
ꢀ 0
7
R 4 2
C _ H A D S I
ꢀ 0
ꢀ 0
0
8
R 4 2
R 4 2
A H C _ K L S C
C H A B 1 _ C S
ꢀ 0
6
R 4 2
J401
PICVCC
1
2
PICVCC
GP1
GP0
3
5
4
6
GP1
GP0
MCLR/GP3
7
9
8
10
MCLR/GP3
ꢀ k 7 5 4 .
R 4 1 8
OPTIONAL
PIC PROGRAMMING HEADER
V
7 ± 5 m = = H N I P O L H I
V 0 . 5 V 5 - 2 .
V 0 . 1 -
2
0
P E O = S L N I A
P E O = S N L I A
V I E T A G E G N
V I E T G S I P O
V m 0 5 ± = O L N I P = O L H I
N
P M P A I L C R
_ 5 V D D A V
N
E D P I M O
. R I L F T E O W N
R U Y O N G E S D I R O S R O S T E S R I
ꢀ 0 T H W 8 I 0 L - 4 1 0 4 L T E L A U O P P
A _ C H
F
2 7 4
8 µ 0 1 0 .
C 4 2
ꢀ
0
6
R 4 1
2 N L O
M M C O
2 H V O
2 L V O
8
1 7
1 8
1 9
V P S 2
7
_ 5 V D D A V
N I H 2
6
A _ C H
B _ C H
N C
2 0
2 D L M
5
4
1 D L M
V P S V
1 L V O
V
D V D A _ 5
2 1
2 2
N I H 1
V P S 1
1 N L O
1 H V O
M M C O
3
2
1
2 3
2 4
_ 5 V D D A V
B _ C H
)
E R W E L P B O S I A D V 1 = – ( 0
N A E B N L W R E D W O O P
E
_ 5 V D D A V
0 V 1 . 0 - = E N G N A R I A G O L
0 V 5 - . V 5 2 . 2 = E
R N I A A N G G H I
N I P O L H I
B L N E
D C H A A N L A N A N N E R O C H F T
R C U C E I I V
A G D R V I N A O I L T P O
Figure 76. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit (Continued)
Rev. E | Page 4ꢁ of 56
AD9228
Data Sheet
1 9 0 7 - 7 2 0 5
D
G N
D
G N
1
1
D
G N
D
G N
1
1
Figure 77. Evaluation Board Schematic, Power Supply Inputs
Rev. E | Page 44 of 56
Data Sheet
AD9228
Figure 78. Evaluation Board Layout, Primary Side
Rev. E | Page 45 of 56
AD9228
Data Sheet
Figure 79. Evaluation Board Layout, Ground Plane
Rev. E | Page 46 of 56
Data Sheet
AD9228
Figure 80. Evaluation Board Layout, Power Plane
Rev. E | Page 4ꢂ of 56
AD9228
Data Sheet
Figure 81. Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. E | Page 4± of 56
Data Sheet
AD9228
Table 17. Evaluation Board Bill of Materials (BOM)1
Manufacturer’s
Manufacturer Part Number
Item
Qty.
1
ꢂ5
Reference Designator
Device
PCB
Capacitor
Package
PCB
4ꢀ2
Value
1
2
AD922±LFCSP_REVA
PCB
ꢀ.1 μF, ceramic,
C1ꢀ1, C1ꢀ2, C1ꢀꢂ,
C1ꢀ±, C1ꢀ9, C114,
C115, C116, C121,
C122, C12ꢁ, C12±,
C2ꢀ1, C2ꢀꢁ, C2ꢀ4,
C2ꢀ5, C2ꢀ6, C21ꢀ,
C211, C212, C21ꢁ,
C216, C21ꢂ, C21±,
C219, C22ꢀ, C221,
C222, C22ꢁ, C224,
Cꢁ1ꢀ, Cꢁ11, Cꢁ12,
Cꢁ1ꢁ, Cꢁ14, Cꢁ16,
Cꢁ19, Cꢁ2ꢀ, Cꢁ21,
Cꢁ24, Cꢁ25, C4ꢀ9,
C41ꢀ, C412, C414,
C416, C41ꢂ, C419,
C422, C42ꢁ, C424,
C425, C42ꢂ, C42±,
C429, C5ꢀꢁ, C5ꢀ5,
C5ꢀꢂ, C5ꢀ9, C516,
C51ꢂ, C51±, C519,
C52ꢀ, C521, C522,
C52ꢁ, C524, C525,
C526, C52ꢂ, C52±,
C529, C5ꢁꢀ, C5ꢁ1
Murata
GRM155Rꢂ1C1ꢀ4KA±±D
X5R, 1ꢀ V, 1ꢀ% tol
ꢁ
4
C1ꢀ4, C111, C11±,
C125
Capacitor
4ꢀ2
2.2 pF, ceramic,
COG, ꢀ.25 pF tol,
5ꢀ V
Murata
GRM1555C1H2R2GZꢀ1B
4
4
1
2
4
4
1
9
Cꢁ15, Cꢁ26, C41ꢁ,
C426
C2ꢀ2
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
±ꢀ5
6ꢀꢁ
4ꢀ2
4ꢀ2
4ꢀ2
12ꢀ6
6ꢀꢁ
1ꢀ μF, 6.ꢁ V ±1ꢀ%
ceramic, X5R
2.2 μF, ceramic,
X5R, 6.ꢁ V, 1ꢀ% tol
1ꢀꢀꢀ pF, ceramic,
XꢂR, 25 V, 1ꢀ% tol
ꢀ.ꢀ1± μF, ceramic,
XꢂR, 16 V, 1ꢀ% tol
22 pF, ceramic,
NPO, 5% tol, 5ꢀ V
1ꢀ μF, tantalum,
16 V, 2ꢀ% tol
Murata
Murata
Murata
AVX
GRM219R6ꢀJ1ꢀ6KE19D
GRM1±±CꢂꢀJ225KE2ꢀD
GRM155Rꢂ1H1ꢀ2KAꢀ1D
ꢀ4ꢀ2YC1±ꢁKAT2A
5
6
Cꢁꢀ9, C411
ꢂ
Cꢁ1ꢂ, Cꢁ22, C415,
C42ꢀ
Cꢁ1±, Cꢁ2ꢁ, C41±,
C421
±
Murata
Rohm
GRM1555C1H22ꢀJZꢀ1D
TCA1C1ꢀ6M±R
9
C5ꢀ1
1ꢀ
C214, C512, C51ꢁ,
C514, C515, C5ꢁ2,
C5ꢁꢁ, C5ꢁ4, C5ꢁ5
1 μF, ceramic, X5R, Murata
6.ꢁ V, 1ꢀ% tol
GRM1±±R61C1ꢀ5KA9ꢁD
11
±
Cꢁꢀ5, Cꢁꢀ6, Cꢁꢀꢂ,
Cꢁꢀ±, C4ꢀ5, C4ꢀ6,
C4ꢀꢂ, C4ꢀ±
C5ꢀ2, C5ꢀ4, C5ꢀ6,
C5ꢀ±
Capacitor
±ꢀ5
ꢀ.1 μF, ceramic,
XꢂR, 5ꢀ V, 1ꢀ% tol
Murata
Murata
GRM21BRꢂ1H1ꢀ4KAꢀ1L
12
1ꢁ
14
15
16
4
1
2
1
1
Capacitor
Diode
LED
6ꢀꢁ
1ꢀ μF, ceramic,
X5R, 6.ꢁ V, 2ꢀ% tol
ꢁꢀ V, 2ꢀ mA, dual
Schottky
Green, 4 V, 5 m
candela
GRM1±±R6ꢀJ1ꢀ6M
HSMS2±12-TRIG
LNJꢁ14G±TRA
SKꢁꢁ-TP
CR2ꢀ1
SOT-2ꢁ
6ꢀꢁ
Agilent
Technologies
Panasonic
CR4ꢀ1, CR5ꢀ1
D5ꢀ2
Diode
Diode
DO-214AB ꢁ A, ꢁꢀ V, SMC
DO-214AA 2 A, 5ꢀ V, SMC
Micro
Commercial Co.
Micro
D5ꢀ1
S2A-TP
Commercial Co.
Rev. E | Page 49 of 56
AD9228
Data Sheet
Manufacturer’s
Manufacturer Part Number
Item
Qty.
Reference Designator
Device
Package
Value
1ꢂ
1
F5ꢀ1
Fuse
121ꢀ
6.ꢀ V, 2.2 A trip-
current resettable
fuse
Tyco/Raychem NANOSMDC11ꢀF-2
1±
19
1
FER5ꢀ1
Choke coil
2ꢀ2ꢀ
6ꢀꢁ
1ꢀ μH, 5 A, 5ꢀ V,
19ꢀ Ω @ 1ꢀꢀ MHz
1ꢀ Ω, test freq
1ꢀꢀ MHz, 25% tol,
5ꢀꢀ mA
Murata
Murata
DLW5BSN191SQ2L
BLM1±BA1ꢀꢀSN1B
12
FB1ꢀ1, FB1ꢀ2, FB1ꢀꢁ,
FB1ꢀ4, FB1ꢀ5, FB1ꢀ6,
FB1ꢀꢂ, FB1ꢀ±, FB1ꢀ9,
FB11ꢀ, FB111, FB112
Ferrite bead
2ꢀ
21
22
1
2
1
JPꢁꢀ1
Connector
Connector
Connector
2-pin
ꢁ-pin
12-pin
1ꢀꢀ mil header
jumper, 2-pin
1ꢀꢀ mil header
jumper, ꢁ-pin
1ꢀꢀ mil header
male, 4 × ꢁ triple
row straight
Samtec
Samtec
Samtec
TSW-1ꢀ2-ꢀꢂ-G-S
TSW-1ꢀꢁ-ꢀꢂ-G-S
TSW-1ꢀ4-ꢀ±-G-T
J2ꢀ5, J4ꢀ2
J2ꢀ1 to J2ꢀ4
2ꢁ
24
25
26
1
J4ꢀ1
Connector
1ꢀ-pin
121ꢀ
4ꢀ2
1ꢀꢀ mil header,
male, 2 × 5 double
row straight
1ꢀ μH, bead core
ꢁ.2 × 2.5 × 1.6
SMD, 2 A
12ꢀ nH, test freq
1ꢀꢀ MHz, 5% tol,
15ꢀ mA
Samtec
Murata
Murata
TSW-1ꢀ5-ꢀ±-G-D
BLMꢁ1PG5ꢀꢀSN1L
LQG15HNR12Jꢀ2B
NRC1ꢀZOTRF
±
L5ꢀ1, L5ꢀ2, L5ꢀꢁ, L5ꢀ4, Ferrite bead
L5ꢀ5, L5ꢀ6, L5ꢀꢂ, L5ꢀ±
4
Lꢁꢀ9, Lꢁ1ꢀ, L4ꢀ9, L41ꢀ Inductor
16
Lꢁꢀ1, Lꢁꢀ2, Lꢁꢀꢁ, Lꢁꢀ4, Resistor
Lꢁꢀ5, Lꢁꢀ6, Lꢁꢀꢂ, Lꢁꢀ±,
±ꢀ5
ꢀ Ω, 1/± W, 5% tol
NIC
Components
L4ꢀ1, L4ꢀ2, L4ꢀꢁ, L4ꢀ4,
L4ꢀ5, L4ꢀ6, L4ꢀꢂ, L4ꢀ±
2ꢂ
2±
1
5
OSC2ꢀ1
Oscillator
SMT
SMA
Clock oscillator,
65.ꢀꢀ MHz, ꢁ.ꢁ V
Side-mount SMA
for ꢀ.ꢀ6ꢁ" board
thickness
Valpey Fisher
VFACꢁH-L-65MHz
142-ꢀꢂ1ꢀ-±51
P1ꢀ1, P1ꢀꢁ, P1ꢀ5,
P1ꢀꢂ, P2ꢀ1
Connector
Johnson
Components
29
1
P2ꢀ2
Connector
Header
1469169-1, right
angle 2-pair,
25 mm, header
assembly
Tyco
6469169-1
ꢁꢀ
ꢁ1
1
P5ꢀꢁ
Connector
Resistor
ꢀ.1", PCMT SC115ꢁ, power
supply connector
Switchcraft
RAPCꢂ22X
15
R2ꢀ1, R2ꢀ5, R214,
R215, R221, R2ꢁ9,
Rꢁ12, Rꢁ15, Rꢁ1±,
R411, R414, R41ꢂ,
R425, R429, R4ꢁꢀ
4ꢀ2
1ꢀ kΩ, 1/16 W,
5% tol
NIC
Components
NRCꢀ4J1ꢀꢁTRF
ꢁ2
14
R1ꢀꢁ, R11ꢂ, R129,
R142, R216, R21ꢂ,
R21±, R22ꢁ, R224,
R2ꢁꢂ, R42ꢀ, R426,
R42ꢂ, R42±
Resistor
4ꢀ2
ꢀ Ω, 1/16 W,
5% tol
NIC
Components
NRCꢀ4ZꢀTRF
ꢁꢁ
ꢁ4
4
4
R1ꢀ2, R115, R12±,
R141
R1ꢀ4, R116, R1ꢁꢀ,
R14ꢁ
Resistor
Resistor
4ꢀ2
6ꢀꢁ
64.9 Ω, 1/16 W,
1% tol
ꢀ Ω, 1/1ꢀ W,
5% tol
NIC
Components
NIC
Components
NRCꢀ4F64R9TRF
NRCꢀ6ZꢀTRF
Rev. E | Page 5ꢀ of 56
Data Sheet
AD9228
Manufacturer’s
Manufacturer Part Number
Item
Qty.
Reference Designator
Device
Package
Value
ꢁ5
15
R1ꢀ9, R111, R112,
R12ꢁ, R125, R126,
R1ꢁ5, R1ꢁ±, R1ꢁ9,
R14±, R149, R15ꢀ,
R4ꢁ1, R4ꢁ2, R4ꢁꢁ
Resistor
4ꢀ2
1 kΩ, 1/16 W,
1% tol
NIC
Components
NRCꢀ4F1ꢀꢀ1TRF
ꢁ6
±
R1ꢀ±, R11ꢀ, R121,
R122, R1ꢁ4, R1ꢁ6,
R146, R14ꢂ
Resistor
4ꢀ2
ꢁꢁ Ω, 1/16 W, 5%
tol
NIC
Components
NRCꢀ4JꢁꢁꢀTRF
ꢁꢂ
ꢁ±
ꢁ9
4ꢀ
41
42
4
ꢁ
1
1
1
2
R161, R162, R16ꢁ,
R164
R2ꢀ2, R2ꢀꢁ, R2ꢀ4
Resistor
4ꢀ2
499 Ω, 1/16 W,
1% tol
1ꢀꢀ kΩ, 1/16 W,
1% tol
4.12 kΩ, 1/16 W,
1% tol
49.9 Ω, 1/16 W,
ꢀ.5% tol
4.99 kΩ, 1/16 W,
5% tol
1ꢀ kΩ, cermet
trimmer
NIC
Components
NIC
Components
NIC
Components
Susumu
NRCꢀ4F499ꢀTRF
NRCꢀ4F1ꢀꢀꢁTRF
NRCꢀ4F4121TRF
RRꢀ51ꢀR-49R9-D
NRCꢀ4F4991TRF
CT94EW1ꢀꢁ
Resistor
4ꢀ2
R222
Resistor
4ꢀ2
R21ꢁ
Resistor
4ꢀ2
R229
Resistor
4ꢀ2
NIC
Components
BC
R2ꢁꢀ, Rꢁ19
Potentiometer
ꢁ-lead
Components
potentiometer,
1±-turn top adjust,
1ꢀ%, 1/2 W
4ꢁ
44
45
1
1
±
R22±
Rꢁ2ꢀ
Resistor
Resistor
Resistor
4ꢀ2
4ꢀ2
4ꢀ2
4ꢂꢀ kΩ, 1/16 W,
5% tol
ꢁ9 kΩ, 1/16 W,
5% tol
1±ꢂ Ω, 1/16 W,
1% tol
NIC
Components
NIC
Components
NIC
Components
NRCꢀ4J4ꢂ4TRF
NRCꢀ4Jꢁ9ꢁTRF
NRCꢀ4F1±ꢂꢀTRF
Rꢁꢀꢂ, Rꢁꢀ±, Rꢁꢀ9,
Rꢁ1ꢀ, R4ꢀꢂ, R4ꢀ±,
R4ꢀ9, R41ꢀ
46
4ꢂ
4±
4
Rꢁꢀ5, Rꢁꢀ6, R4ꢀ5,
R4ꢀ6
Rꢁ16, Rꢁ1ꢂ, R415,
R416
R245, R24ꢂ, R249,
R251, R25ꢁ, R255,
R25ꢂ, R259, R261,
R26ꢁ, R265
Resistor
Resistor
Resistor
4ꢀ2
4ꢀ2
2ꢀ1
ꢁꢂ4 Ω, 1/16 W,
1% tol
2ꢂ4 Ω, 1/16 W,
1% tol
NIC
Components
NIC
Components
NRCꢀ4Fꢁꢂ4ꢀTRF
NRCꢀ4F2ꢂ4ꢀTRF
ERJ-1GEꢀRꢀꢀC
4
11
ꢀ Ω, 1/2ꢀ W, 5% tol
Panasonic
49
5ꢀ
51
52
5ꢁ
54
55
1
1
1
2
2
1
5
R41±
Resistor
Resistor
Resistor
Resistor
Resistor
Switch
4ꢀ2
4.ꢂ5 kΩ, 1/16 W,
1% tol
261 Ω, 1/16 W,
1% tol
261 Ω, 1/16 W,
1% tol
24ꢁ Ω, 1/16 W,
1% tol
1ꢀꢀ Ω, 1/16 W,
1% tol
Light touch,
1ꢀꢀGE, 5 mm
ADT1-1WT, 1:1
impedance ratio
transformer
NIC
Components
NIC
Components
NIC
Components
NIC
Components
NRCꢀ4J4ꢂ2TRF
NRCꢀ4F261ꢀTRF
NRCꢀ6F261ꢀTRF
NRCꢀ4F24ꢁꢀTRF
NRCꢀ4F1ꢀꢀꢀTRF
EVQ-PLDA15
R419
4ꢀ2
R5ꢀ1
6ꢀꢁ
R24ꢀ, R241
R242, R24ꢁ
S4ꢀ1
4ꢀ2
4ꢀ2
NIC
Components
Panasonic
SMD
CD542
T1ꢀ1, T1ꢀ2, T1ꢀꢁ, T1ꢀ4, Transformer
T2ꢀ1
Mini-Circuits
ADT1-1WT+
56
2
U5ꢀ1, U5ꢀꢁ
IC
SOT-22ꢁ
ADPꢁꢁꢁꢁ9AKC-1.±, Analog Devices ADPꢁꢁꢁꢁ9AKCZ-1.±
1.5 A, 1.± V LDO
regulator
Rev. E | Page 51 of 56
AD9228
Data Sheet
Manufacturer’s
Manufacturer Part Number
Item
Qty.
Reference Designator
Device
Package
Value
5ꢂ
2
Uꢁꢀ1, U4ꢀ1
IC
LFCSP,
CP-ꢁ2
AD±ꢁꢁ2ACP,
ultralow noise
precision dual
VGA
Analog Devices AD±ꢁꢁ2ACPZ
5±
59
6ꢀ
1
1
1
U5ꢀ4
U5ꢀ2
U2ꢀ1
IC
IC
IC
SOT-22ꢁ
SOT-22ꢁ
LFCSP,
ADPꢁꢁꢁ9AKC-5
ADPꢁꢁꢁ9AKC-ꢁ.ꢁ
AD922±BCPZ-65,
quad, 12-bit, 65
MSPS serial LVDS
1.± V ADC
Analog Devices ADPꢁꢁꢁ9AKCZ-5
Analog Devices ADPꢁꢁꢁ9AKCZ-ꢁ.ꢁ
Analog Devices AD922±BCPZ-65
CP-4±-1
61
1
U2ꢀꢁ
IC
SOT-2ꢁ
ADR51ꢀARTZ, 1.ꢀ V, Analog Devices ADR51ꢀARTZ
precision low
noise shunt
voltage reference
62
6ꢁ
64
65
1
1
1
1
U2ꢀ2
U4ꢀꢁ
U4ꢀ4
U4ꢀ2
IC
IC
IC
IC
LFCSP
CP-ꢁ2-2
SCꢂꢀ,
MAAꢀ6A
SCꢂꢀ,
MAAꢀ6A
±-SOIC
AD9515BCPZ
Analog Devices AD9515BCPZ
NCꢂWZꢀꢂ
Fairchild
Fairchild
Microchip
NCꢂWZꢀꢂP6X_NL
NCꢂWZ16
NCꢂWZ16P6X_NL
PIC12F629-I/SN
Flash prog
mem 1k × 14,
RAM size 64 × ±,
2ꢀ MHz speed,
PIC12F controller
series
1 This BOM is RoHS compliant.
Rev. E | Page 52 of 56
Data Sheet
AD9228
OUTLINE DIMENSIONS
7.10
7.00 SQ
6.90
0.30
0.23
0.18
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
37
36
48
1
PIN 1
INDICATOR
0.50
REF
6.85
*
5.55
5.50 SQ
5.45
6.75 SQ
6.65
EXPOSED
PAD
(BOTTOM VIEW)
25
24
12
13
0.50
0.40
0.30
0.22 MIN
TOP VIEW
5.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.08
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 82. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-8)
Dimensions shown in millimeters
ORDERING GUIDE
Package
Model1, 2
Notes
Temperature Range Package Description
Option
CP-4±-±
CP-4±-±
CP-4±-±
CP-4±-±
AD922±ABCPZ-4ꢀ
AD922±ABCPZRLꢂ-4ꢀ
AD922±ABCPZ-65
AD922±ABCPZRLꢂ-65
AD922±-65EBZ
−4ꢀ°C to +±5°C
−4ꢀ°C to +±5°C
−4ꢀ°C to +±5°C
−4ꢀ°C to +±5°C
4±-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4±-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4±-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4±-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
ꢁ
1 Z = RoHS Compliant Part.
2 Reference PCN ꢀ9_ꢀ156.
ꢁ Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board.
Rev. E | Page 5ꢁ of 56
AD9228
NOTES
Data Sheet
Rev. E | Page 54 of 56
Data Sheet
NOTES
AD9228
Rev. E | Page 55 of 56
AD9228
NOTES
Data Sheet
©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05727-0-12/11(E)
Rev. E | Page 56 of 56
相关型号:
AD9228BCPZ-65
4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48
ROCHESTER
AD9228BCPZRL7-40
4-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, QCC48, 7 X 7 MM, ROHS COMPLIANT, MO-220VKKD-2, LFCSP-48
ROCHESTER
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