AD9228BCPZRL-40_技术文档

Quad, 12-bit, 40/65 MSPS

Serial LVDS 1.8 V A/D Converter

AD9228

FUNCTIONAL BLOCK DIAGRAM

FEATURES

AVDD

PDWN

Four ADCs integrated into 1 package

119 mW ADC power per channel at 65 MSPS

SNR = 70 dB (to Nyquist)

DRVDD

DRGND

AD9228

12

VIN+A

VIN–A

SERIAL

LVDS

D+A

D–A

PIPELINE

ADC

Excellent linearity

DNL = 0.3 LSB (typical)

INL = 0.4 LSB (typical)

12

VIN+B

VIN–B

PIPELINE

ADC

SERIAL

LVDS

D+B

D–B

Serial LVDS (ANSI-644, default)

Low power reduced signal option, IEEE 1596.3 similar

Data and frame clock outputs

315 MHz full power analog bandwidth

2 V p-p input voltage range

VIN+C

VIN–C

SERIAL

LVDS

D+C

D–C

PIPELINE

ADC

12

VIN+D

VIN–D

SERIAL

LVDS

D+D

D–D

PIPELINE

ADC

VREF

1.8 V supply operation

Serial port control

FCO+

FCO–

SENSE

+

0.5V

–

DATA RATE

REFT

REFB

REF

SELECT

MULTIPLIER

Full-chip and individual-channel power-down modes

Flexible bit orientation

SERIAL PORT

INTERFACE

DCO+

DCO–

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

SCLK/DTP

RBIASAGND CSB SDIO/ODM

CLK+ CLK–

Figure 1.

capturing data on the output and a frame clock (FCO) for

APPLICATIONS

signaling a new output byte are provided. Individual channel

power-down is supported and typically consumes less than

2 mW when all channels are disabled.

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam forming systems

Quadrature radio receivers

Diversity radio receivers

Tape drives

Optical networking

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-

defined test patterns entered via the serial port interface (SPI®).

Test equipment

GENERAL DESCRIPTION

The AD9228 is available in a Pb-free, 48-lead LFCSP package. It is

specified over the industrial temperature range of −40°C to +85°C.

The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital

converter (ADC) with an on-chip sample-and-hold circuit that

is designed for low cost, low power, small size, and ease of use.

The product operates at a conversion rate of up to 65 MSPS and

is optimized for outstanding dynamic performance and low

power in applications where a small package size is critical.

PRODUCT HIGHLIGHTS

1. Small Footprint. Four ADCs are contained in a small, space-

saving package; low power of 119 mW/channel at 65 MSPS.

2. Ease of Use. A data clock output (DCO) is provided that

operates up to 390 MHz and supports double data rate

operation (DDR).

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

3. User Flexibility. Serial port interface (SPI) control offers a wide

range of flexible features to meet specific system requirements.

The ADC automatically multiplies the sample rate clock for the

appropriate LVDS serial data rate. A data clock (DCO) for

4. Pin-Compatible Family. This includes the AD9287 (8-bit),

AD9219 (10-bit), and AD9259 (14-bit).

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9228

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagrams.............................................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Impedance..................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Equivalent Circuits......................................................................... 12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 19

Analog Input Considerations ................................................... 19

Clock Input Considerations...................................................... 21

Serial Port Interface (SPI).............................................................. 29

Hardware Interface..................................................................... 29

Memory Map .................................................................................. 31

Reading the Memory Map Table.............................................. 31

Reserved Locations .................................................................... 31

Default Values............................................................................. 31

Logic Levels................................................................................. 31

Evaluation Board ............................................................................ 35

Power Supplies............................................................................ 35

Input Signals................................................................................ 35

Output Signals ............................................................................ 35

Default Operation and Jumper Selection Settings................. 36

Alternative Analog Input Drive Configuration...................... 37

Outline Dimensions....................................................................... 51

Ordering Guide .......................................................................... 51

REVISION HISTORY

4/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 52

AD9228

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 1.

AD9228-40

Min Typ

AD9228-65

Max Min Typ

Parameter¹

Temperature

Max

Unit

RESOLUTION

12

Bits

ACCURACY

No Missing Codes

Offset Error

Offset Matching

Gain Error

Full

Guaranteed

1

2

0.3

0.ꢁ

1

2

0.ꢁ

0.3

0.25

0.ꢁ

ꢀ

1.2

0.ꢂ

0.5

1

ꢀ

mV

ꢀ

mV

3.5

0.ꢂ

% FS

Gain Matching

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

TEMPERATURE DRIFT

Offset Error

Gain Error

Reference Voltage (1 V Mode)

REFERENCE

0.ꢃ5 LSB

1

LSB

Full

2

1ꢂ

21

2

1ꢂ

21

ppm/°C

Output Voltage Error (VREF = 1 V)

Load Regulation @ 1.0 mA (VREF = 1 V)

Input Resistance

Full

2

3

ꢃ

30

2

3

ꢃ

30

mV

kΩ

ANALOG INPUTS

Differential Input Voltage Range (VREF = 1 V)

Common-Mode Voltage

Differential Input Capacitance

Analog Bandwidth, Full Power

POWER SUPPLY

Full

2

V p-p

V

pF

AVDD/2

ꢂ

315

AVDD/2

ꢂ

315

MHz

AVDD

DRVDD

IAVDD

IDRVDD

Full

1.ꢂ

1.ꢀ

155

31

335

2

1.9

1.ꢂ

1.ꢀ

232

3ꢁ

ꢁꢂꢀ

2

1.9

2ꢁ5

3ꢀ

510

5.ꢀ

V

1.9

1ꢂ0

3ꢁ

3ꢃꢂ

5.ꢀ

mA

mW

dB

Total Power Dissipation (Including Output Drivers)

Power-Down Dissipation

Standby Dissipation²

CROSSTALK

ꢂ2

−100

CROSSTALK (Overrange Condition)³

dB

¹See the AN-ꢀ35 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.

²Can be controlled via SPI.

³Overrange condition is specific with ꢃ dB of the full-scale input range.

Rev. 0 | Page 3 of 52

AD9228

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 2.

AD9228-40

AD9228-65

Parameter¹

Temperature Min Typ Max Min Typ

Max Unit

dB

SIGNAL-TO-NOISE RATIO (SNR)

f_IN= 2.ꢁ MHz

f_IN= 19.ꢂ MHz Full

f_IN= 35 MHz

f_IN= ꢂ0 MHz

f_IN= 2.ꢁ MHz

Full

ꢂ0.5

ꢃꢀ.5 ꢂ0.2

ꢂ0.2

ꢂ0.0

ꢃꢀ.5 ꢂ0.0

ꢃ9.5

dB

Full

ꢂ0.0

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

EFFECTIVE NUMBER OF BITS (ENOB)

ꢂ0.3

ꢃꢀ.0 ꢃ9.ꢀ

ꢃ9.ꢂ

ꢂ0.0

ꢃꢀ.0 ꢃ9.ꢀ

ꢃ9.0

dB

f_IN= 19.ꢂ MHz Full

f_IN= 35 MHz

f_IN= ꢂ0 MHz

f_IN= 2.ꢁ MHz

Full

ꢃ9.5

11.ꢁ

11.3ꢂ

Bits

f_IN= 19.ꢂ MHz Full

11.1 11.3ꢂ

11.3ꢂ

11.33

11.1 11.33

11.25

Bits

f_IN= 35 MHz

f_IN= ꢂ0 MHz

f_IN= 2.ꢁ MHz

Full

11.33

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

WORST HARMONIC (Second or Third)

ꢀ5

dBc

f_IN= 19.ꢂ MHz Full

ꢂ2

ꢀ2

ꢀ0

ꢀ5

ꢀꢁ

ꢂꢁ

dBc

f_IN= 35 MHz

f_IN= ꢂ0 MHz

f_IN= 2.ꢁ MHz

Full

ꢂ3

−ꢀ5

−ꢀ2

−ꢀ0

−90

ꢀ0.ꢀ

−ꢀ5

−ꢀꢁ

−ꢂꢁ

−90

−ꢀꢀ

ꢂꢂ.ꢀ

dBc

−ꢂ3 dBc

dBc

f_IN= 19.ꢂ MHz Full

−ꢂ2

−ꢀ0

f_IN= 35 MHz

f_IN= ꢂ0 MHz

f_IN= 2.ꢁ MHz

Full

WORST OTHER (Excluding Second or Third)

dBc

−ꢂ9 dBc

dBc

f_IN= 19.ꢂ MHz Full

f_IN= 35 MHz

f_IN= ꢂ0 MHz

Full

TWO-TONE INTERMODULATION DISTORTION (IMD)—

AIN1 AND AIN2 = −ꢂ.0 dBFS

f_IN1= 15 MHz, 25°C

_IN2= 1ꢃ MHz

f_IN1= ꢂ0 MHz, 25°C

_IN2= ꢂ1 MHz

dBc

f

ꢂ5.0

ꢂꢂ.0

dBc

f

¹See the AN-ꢀ35 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.

Rev. 0 | Page ꢁ of 52

AD9228

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 3.

AD9228-40

Typ Max

AD9228-65

Typ Max

Parameter¹

Temperature

Min

Unit

CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage²

Input Common-Mode Voltage

Input Resistance (Differential)

Input Capacitance

Full

25°C

250

mV p-p

V

kΩ

pF

1.2

20

1.5

1.2

20

1.5

LOGIC INPUTS (PDWN, SCLK/DTP)

Logic 1 Voltage

Logic 0 Voltage

Input Resistance

Input Capacitance

Full

25°C

1.2

0

3.ꢃ

0.3

1.2

3.ꢃ

0.3

V

kΩ

pF

30

0.5

30

0.5

LOGIC INPUT (CSB)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

0

3.ꢃ

0.3

3.ꢃ

0.3

V

Input Resistance

Input Capacitance

25°C

ꢂ0

0.5

ꢂ0

0.5

kΩ

pF

LOGIC INPUT (SDIO/ODM)

Logic 1 Voltage

Logic 0 Voltage

Full

1.2

0

DRVDD + 0.3 1.2

DRVDD + 0.3

0.3

V

0.3

0

Input Resistance

Input Capacitance

25°C

30

2

30

2

kΩ

pF

LOGIC OUTPUT (SDIO/ODM)

Logic 1 Voltage (I_OH= 50 μA)

Logic 0 Voltage (I_OL= 50 μA)

DIGITAL OUTPUTS (D+, D−), (ANSI-ꢃꢁꢁ)¹

Logic Compliance

Full

1.ꢂ9

V

0.05

LVDS

Differential Output Voltage (V_OD

)

Full

2ꢁꢂ

1.125

ꢁ5ꢁ

1.3ꢂ5

2ꢁꢂ

1.125

ꢁ5ꢁ

1.3ꢂ5

mV

V

Output Offset Voltage (V_OS

)

Output Coding (Default)

Offset binary

DIGITAL OUTPUTS (D+, D−),

(Low Power, Reduced Signal Option)¹

Logic Compliance

LVDS

Differential Output Voltage (V_OD

)

Full

150

1.10

250

1.30

150

1.10

250

1.30

mV

V

Output Offset Voltage (V_OS

)

Output Coding (Default)

Offset binary

¹See the AN-ꢀ35 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.

²This is specified for LVDS and LVPECL only.

Rev. 0 | Page 5 of 52

AD9228

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.

Table 4.

AD9228-40

Typ

AD9228-65

Typ

Parameter¹

CLOCK²

Temp

Min

Max

Min

Max

Unit

Maximum Clock Rate

Minimum Clock Rate

Full

ꢁ0

ꢃ5

MSPS

ns

10

Clock Pulse Width High (t_EH

)

12.5

ꢂ.ꢂ

Clock Pulse Width Low (t_EL)

ns

OUTPUT PARAMETERS²

Propagation Delay (t_PD

)

Full

2.0

2.ꢂ

3.5

2.0

2.ꢂ

3.5

ns

ps

ns

Rise Time (t_R) (20% to ꢀ0%)

Fall Time (t_F) (20% to ꢀ0%)

FCO Propagation Delay (t_FCO

300

2.ꢂ

300

2.ꢂ

)

3

DCO Propagation Delay (t_CPD

)

t_FCO

+

t_FCO

+

(t_SAMPLE/2ꢁ)

3

Full

(t_SAMPLE/2ꢁ) − 300 (t_SAMPLE/2ꢁ) (t_SAMPLE/2ꢁ) + 300 (t_SAMPLE/2ꢁ) − 300 (t_SAMPLE/2ꢁ) (t_SAMPLE/2ꢁ) + 300 ps

DCO to Data Delay (t_DATA

)

3

DCO to FCO Delay (t_FRAME

Data to Data Skew

)

50

150

50

150

ps

(t_DATA-MAX− t_DATA-MIN

)

Wake-Up Time (Standby)

25°C

Full

ꢃ00

3ꢂ5

10

ꢃ00

3ꢂ5

10

ns

μs

Wake-Up Time (Power Down)

Pipeline Latency

CLK

cycles

APERTURE

Aperture Delay (t_A)

25°C

500

<1

1

500

<1

2

ps

Aperture Uncertainty (Jitter)

Out-of-Range Recovery Time

ps rms

CLK

cycles

¹See the AN-ꢀ35 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.

²Can be adjusted via the SPI interface.

³t_SAMPLE/2ꢁ is based on the number of bits divided by 2 because the delays are based on half duty cycles.

Rev. 0 | Page ꢃ of 52

AD9228

TIMING DIAGRAMS

N-1

AIN

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

D6

D–

D+

MSB

D10

D9

D8

D7

D5

D4

D3

D2

D1

D0

MSB

N – 9

D10

N – 9

N – 10 N – 10 N – 10 N – 10 N – 10 N – 10 N – 10 N – 10 N – 10 N – 10 N – 10 N – 10

Figure 2. 12-Bit Data Serial Stream (Default)

N-1

AIN

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

D–

t_PD

t_DATA

MSB

N–10

D8

N–10

D7

D6

D5

N–10

D4

D3

D2

D1

D0

MSB

N–9

D8

N–9

D7

N–9

D6

N–9

D5

N–9

N–10 N–10

N–10 N–10 N–10

N–10 N–10

D+

Figure 3. 10-Bit Data Serial Stream

Rev. 0 | Page ꢂ of 52

AD9228

N-1

AIN

t_A

N

t_EH

t_EL

CLK–

CLK+

t_CPD

DCO–

DCO+

t_FRAME

t_FCO

FCO–

FCO+

t_PD

t_DATA

D4

D–

D+

LSB

D0

D1

D2

D3

D5

D6

D7

D8

D9

D10

LSB

D0

(N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 9) (N – 9)

Figure 4. 12-Bit Data Serial Stream, LSB First

Rev. 0 | Page ꢀ of 52

AD9228

ABSOLUTE MAXIMUM RATINGS

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

With

Respect To

Parameter

ELECTRICAL

AVDD

DRVDD

AGND

AVDD

Digital Outputs

(D+, D−, DCO+,

DCO−, FCO+, FCO−)

CLK+, CLK−

VIN+, VIN−

SDIO/ODM

PDWN, SCLK/DTP, CSB

REFT, REFB, RBIAS

VREF, SENSE

Rating

AGND

−0.3 V to +2.0 V

−0.3 V to +0.3 V

−2.0 V to +2.0 V

−0.3 V to +2.0 V

DRGND

DRVDD

DRGND

THERMAL IMPEDANCE

Table 6.

Air Flow Velocity (m/s)

1

θ_JA

θ_JB

θ_JC

AGND

−0.3 V to +3.9 V

−0.3 V to +2.0 V

−0.3 V to +3.9 V

−0.3 V to +2.0 V

0.0

1.0

2.5

2ꢁ°C/W

21°C/W

19°C/W

12.ꢃ°C/W

1.2°C/W

¹θ_JAfor a ꢁ-layer PCB with solid ground plane (simulated). Exposed pad

soldered to PCB.

ENVIRONMENTAL

Operating Temperature

Range (Ambient)

Maximum Junction

Temperature

−ꢁ0°C to +ꢀ5°C

150°C

Lead Temperature

(Soldering, 10 sec)

300°C

Storage Temperature

Range (Ambient)

−ꢃ5°C to +150°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as ꢁ000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. 0 | Page 9 of 52

AD9228

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

AVDD

VIN – D

VIN + D

AVDD

CLK–

1

2

36

35

34

33

32

31

30

29

28

27

26

25

AVDD

3

VIN – A

VIN + A

AVDD

EXPOSED PADDLE, PIN 0

(BOTTOM OF PACKAGE)

4

5

6

PDWN

AD9228

TOP VIEW

7

CSB

8

CLK+

SDIO/ODM

SCLK/DTP

AVDD

9

AVDD

DRGND

DRVDD

10

11

12

DRGND

DRVDD

Figure 5. 48-Lead LFCSP Top View

Table 7. Pin Function Descriptions

Pin No.

Name

Description

0

AGND

AVDD

Analog Ground (Exposed Paddle)

1.ꢀ V Analog Supply

1, 2, 5, ꢃ, 9, 10, 2ꢂ, 32,

35, 3ꢃ, 39, ꢁ5, ꢁꢃ

11, 2ꢃ

12, 25

3

ꢁ

ꢂ

DRGND

DRVDD

VIN − D

VIN + D

CLK−

Digital Output Driver Ground

1.ꢀ V Digital Output Driver Supply

ADC D Analog Input—Complement

ADC D Analog Input—True

Input Clock—Complement

Input Clock—True

ꢀ

CLK+

13

1ꢁ

15

1ꢃ

1ꢂ

1ꢀ

19

20

21

22

23

2ꢁ

2ꢀ

29

30

31

33

3ꢁ

D − D

D + D

D − C

D + C

D − B

D + B

D − A

D + A

ADC D Complement Digital Output

ADC D True Digital Output

ADC C Complement Digital Output

ADC C True Digital Output

ADC B Complement Digital Output

ADC B True Digital Output

ADC A Complement Digital Output

ADC A True Digital Output

Frame Clock Output—Complement

Frame Clock Output—True

Data Clock Output—Complement

Data Clock Output—True

Serial Clock/Digital Test Pattern

Serial Data Input-Output/Output Driver Mode

CSB

Power-Down

ADC A Analog Input—True

ADC A Analog Input—Complement

FCO−

FCO+

DCO−

DCO+

SCLK/DTP

SDIO/ODM

CSB

PDWN

VIN + A

VIN − A

Rev. 0 | Page 10 of 52

AD9228

Pin No.

3ꢂ

3ꢀ

ꢁ0

ꢁ1

ꢁ2

ꢁ3

ꢁꢁ

ꢁꢂ

Name

VIN − B

VIN + B

RBIAS

SENSE

VREF

REFB

REFT

VIN + C

VIN − C

Description

ADC B Analog Input—Complement

ADC B Analog Input—True

External Resistor Sets the Internal ADC Core Bias Current

Reference Mode Selection

Voltage Reference Input/Output

Differential Reference (Negative)

Differential Reference (Positive)

ADC C Analog Input—True

ꢁꢀ

ADC C Analog Input—Complement

Rev. 0 | Page 11 of 52

AD9228

EQUIVALENT CIRCUITS

DRVDD

V

D–

D+

VIN

V

DRGND

Figure 9. Equivalent Digital Output Circuit

Figure 6. Equivalent Analog Input Circuit

10Ω

CLK

10kΩ

1.25V

1kΩ

SCLK/PDWN

10Ω

30kΩ

CLK

Figure 7. Equivalent Clock Input Circuit

Figure 10. Equivalent SCLK/PDWN Input Circuit

100Ω

RBIAS

350Ω

SDIO/ODM

30kΩ

Figure 11. Equivalent RBIAS Circuit

Figure 8. Equivalent SDIO/ODM Input Circuit

Rev. 0 | Page 12 of 52

AD9228

AVDD

70kΩ

1kΩ

CSB

VREF

6kΩ

Figure 12. Equivalent CSB Input Circuit

Figure 14. Equivalent VREF Circuit

1kΩ

SENSE

Figure 13. Equivalent SENSE Circuit

Rev. 0 | Page 13 of 52

AD9228

TYPICAL PERFORMANCE CHARACTERISTICS

0

–20

–40

–60

–80

AIN = –0.5dBFS

SNR = 70.51dB

ENOB = 11.38 BITS

AIN = –0.5dBFS

SNR = 69.62dB

ENOB = 10.96 BITS

SFDR = 72.48dBc

–20

SFDR = 86.00dBc

–40

–60

–80

–100

–120

–100

–120

0

2

4

6

8

10

12

14

16

18

20

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 15. Single-Tone 32k FFT with f_IN= 2.3 MHz, f_SAMPLE= 40 MSPS

Figure 18. Single-Tone 32k FFT with f_IN= 70 MHz, f_SAMPLE= 65 MSPS

0

AIN = –0.5dBFS

SNR = 68.74dB

ENOB = 10.88 BITS

SFDR = 72.99dBc

AIN = –0.5dBFS

SNR = 70.38dB

ENOB = 11.40 BITS

SFDR = 81.13dBc

–20

–40

–20

–40

–60

–80

–60

–80

–100

–120

–100

–120

0

2

4

6

8

10

12

14

16

18

20

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 16. Single-Tone 32k FFT with f_IN= 35 MHz, f_SAMPLE= 40 MSPS

Figure 19. Single-Tone 32k FFT with f_IN= 120 MHz, f_SAMPLE= 65 MSPS

0

AIN = –0.5dBFS

SNR = 70.53dB

SNR = 67.68dB

ENOB = 11.38 BITS

SFDR = 86.04dBc

ENOB = 10.95 BITS

SFDR = 62.23dBc

–20

–40

–60

–80

–40

–60

–80

–100

–120

–100

–120

0

5

10

15

20

25

30

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 20. Single-Tone 32k FFT with f_IN= 170 MHz, f_SAMPLE= 65 MSPS

Figure 17. Single-Tone 32k FFT with f_IN= 2.3 MHz, f_SAMPLE= 65 MSPS

Rev. 0 | Page 1ꢁ of 52

AD9228

84

82

80

78

76

74

72

70

68

0

–20

AIN = –0.5dBFS

SNR = 67.58dB

ENOB = 10.93 BITS

SFDR = 68.39dBc

2V p-p, SFDR

–40

–60

–80

–100

–120

2V p-p, SNR

10

15

20

25

30

35

40

0

5

10

15

20

25

30

ENCODE (MSPS)

FREQUENCY (MHz)

Figure 21. Single-Tone 32k FFT with f_IN= 190 MHz, f_SAMPLE= 65 MSPS

Figure 24. SNR/SFDR vs. f_SAMPLE, f_IN= 35 MHz, f_SAMPLE= 40 MSPS

0

90

85

AIN = –0.5dBFS

SNR = 65.56dB

ENOB = 10.6 BITS

SFDR = 62.72dBc

–20

2V p-p, SFDR

–40

–60

80

75

70

–80

–100

–120

65

2V p-p, SNR

60

10

0

5

10

15

20

25

30

20

30

40

50

60

FREQUENCY (MHz)

ENCODE (MSPS)

Figure 22. Single-Tone 32k FFT with f_IN= 250 MHz, f_SAMPLE= 65 MSPS

Figure 25. SNR/SFDR vs. f_SAMPLE, f_IN= 10.3 MHz, f_SAMPLE= 65 MSPS

90

84

2V p-p, SFDR

82

85

2V p-p, SFDR

80

78

76

74

72

80

75

70

2V p-p, SNR

65

60

70

2V p-p, SNR

68

10

15

20

25

30

35

40

20

30

40

50

60

ENCODE (MSPS)

Figure 23. SNR/SFDR vs. f_SAMPLE, f_IN= 10.3 MHz, f_SAMPLE= 40 MSPS

Figure 26. SNR/SFDR vs. f_SAMPLE, f_IN= 35 MHz, f_SAMPLE= 65 MSPS

Rev. 0 | Page 15 of 52

AD9228

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

F

= 35MHz

F

= 10.3MHz

IN

SAMPLE

IN

SAMPLE

= 65MSPS

= 40MSPS

2V p-p, SFDR

80dB

REFERENCE

2V p-p, SNR

80dB

REFERENCE

0

–60

–50

–40

–30

–20

–10

0

–50

–40

–30

–20

–10

0

ANALOG INPUT LEVEL (dBFS)

Figure 30. SNR/SFDR vs. Analog Input Level, f_IN= 35 MHz, f_SAMPLE= 65 MSPS

Figure 27. SNR/SFDR vs. Analog Input Level, f_IN= 10.3 MHz, f_SAMPLE= 40 MSPS

0

100

AIN1 AND AIN2 = –7dBFS

SFDR = 80.75dBc

IMD2 = 85.53dBc

F

= 35MHz

IN

SAMPLE

90

80

70

60

50

40

30

20

10

0

= 40MSPS

–20

IMD3 = 80.83dBc

2V p-p, SFDR

–40

–60

–80

80dB

REFERENCE

2V p-p, SNR

–100

–120

0

2

4

6

8

10

12

14

16

18

20

–60

–50

–40

–30

–20

–10

0

FREQUENCY (MHz)

ANALOG INPUT LEVEL (dBFS)

Figure 31. Two-Tone 32k FFT with f_IN1= 15 MHz and f_IN2= 16 MHz,

f_SAMPLE= 40 MSPS

Figure 28. SNR/SFDR vs. Analog Input Level, f_IN= 35 MHz, f_SAMPLE= 40 MSPS

100

0

AIN1 AND AIN2 = –7dBFS

SFDR = 74.76dBc

IMD2 = 81.03dBc

F

= 10.3MHz

IN

SAMPLE

90

80

70

60

50

40

30

20

10

0

= 65MSPS

2V p-p, SFDR

–20

IMD3 = 75.00dBc

–40

–60

–80

80dB

REFERENCE

2V p-p, SNR

–100

–120

–60

–50

–40

–30

–20

–10

0

2

4

6

8

10

12

14

16

18

20

ANALOG INPUT LEVEL (dBFS)

FREQUENCY (MHz)

Figure 29. SNR/SFDR vs. Analog Input Level, f_IN= 10.3 MHz, f_SAMPLE= 65 MSPS

Figure 32. Two-Tone 32k FFT with f_IN1= 70 MHz and f_IN2= 71 MHz,

f_SAMPLE= 40 MSPS

Rev. 0 | Page 1ꢃ of 52

AD9228

0

–20

–40

–60

90

85

80

75

70

65

60

AIN1 AND AIN2 = –7dBFS

SFDR = 78.15dBc

IMD2 = 77.84dBc

IMD3 = 88.94dBc

2V p-p, SFDR

–80

–100

–120

2V p-p, SINAD

0

5

10

15

20

25

30

–40

–20

0

20

40

60

80

FREQUENCY (MHz)

TEMPERATURE (°C)

Figure 33. Two-Tone 32k FFT with f_IN1= 15 MHz and

f_IN2= 16 MHz, f_SAMPLE= 65 MSPS

Figure 36. SINAD/SFDR vs. Temperature, f_IN= 10.3 MHz, f_SAMPLE= 65 MSPS

0.5

0.4

0

–20

–40

–60

AIN1 AND AIN2 = –7dBFS

SFDR = 76.75dBc

IMD2 = 77.56dBc

IMD3 = 77.01dBc

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–80

–100

–120

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 34. Two-Tone 32k FFT with f_IN1= 70 MHz and

f_IN2= 71 MHz, f_SAMPLE= 65 MSPS

Figure 37. INL, f_IN= 2.4 MHz, f_SAMPLE= 65 MSPS

0.5

0.4

90

85

80

75

70

65

60

55

50

2Vp-p, SFDR

2Vp-p, SNR

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

1

10

100

1000

ANALOG INPUT LEVEL (dBFS)

Figure 38. DNL, f_IN= 2.4 MHz, f_SAMPLE= 65 MSPS

Figure 35. SNR/SFDR vs. f_IN, f_SAMPLE= 65 MSPS

Rev. 0 | Page 1ꢂ of 52

AD9228

0

–20

–30

–35

–40

–45

–50

–55

–60

–65

NPR = 60.83dB

NOTCH = 18.0MHz

NOTCH WIDTH = 3.0MHz

–40

–60

–80

–100

–120

–70

0

5

10

15

20

25

30

5

10

15

20

25

30

35

FREQUENCY (MHz)

Figure 39. CMRR vs. Frequency, f_SAMPLE= 65 MSPS

Figure 41. Noise Power Ratio (NPR), f_SAMPLE= 65 MSPS

1.2

1.0

0.8

0.6

0.4

0.2

0

–1

–2

–3

–4

–5

–6

–7

0.26 LSB rms

–3dB CUTOFF = 315MHz

–8

–9

–10

N–3

N–2

N–1

N

N+1

N+2

N+3

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

CODE

Figure 40. Input Referred Noise Histogram, f_SAMPLE= 65 MSPS

Figure 42. Full Power Bandwidth vs. Frequency, f_SAMPLE= 65 MSPS

Rev. 0 | Page 1ꢀ of 52

AD9228

THEORY OF OPERATION

realizing the maximum bandwidth of the ADC. Such use of

The AD9228 architecture consists of a pipelined ADC that is

divided into three sections: a 4-bit first stage followed by eight

1.5-bit stages and a final 3-bit flash. Each stage provides

sufficient overlap to correct for flash errors in the preceding

stages. The quantized outputs from each stage are combined

into a final 12-bit result in the digital correction logic. The

pipelined architecture permits the first stage to operate on a

new input sample while the remaining stages operate on preceding

samples. Sampling occurs on the rising edge of the clock.

low-Q inductors or ferrite beads is required when driving the

converter front end at high IF frequencies. Either a shunt capacitor

or two single-ended capacitors can be placed on the inputs to

provide a matching passive network. This ultimately creates a

low-pass filter at the input to limit any unwanted broadband

noise. See the AN-742 Application Note, the AN-827 Application

Note, and the Analog Dialogue article “Transformer-Coupled

Front-End for Wideband A/D Converters” for more information

on this subject. In general, the precise values depend on the

application.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The analog inputs of the AD9228 are not internally dc-biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that V_CM= AVDD/2 is recom-

mended for optimum performance, but the device can function

over a wider range with reasonable performance, as shown in

Figure 44 and Figure 45.

The output staging block aligns the data, carries out the error

correction, and passes the data to the output buffers. The data is

then serialized and aligned to the frame and output clock.

90

SFDR (dBc)

85

80

ANALOG INPUT CONSIDERATIONS

75

The analog input to the AD9228 is a differential switched-capacitor

circuit designed for processing differential input signals. The input

can support a wide common-mode range and maintain excellent

performance. An input common-mode voltage of midsupply

minimizes signal-dependent errors and provides optimum

performance.

SNR (dB)

70

65

60

55

50

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

H

ANALOG INPUT COMMON MODE VOLTAGE (V)

Figure 44. SNR/SFDR vs. Common-Mode Voltage,

f_IN= 2.4 MHz, f_SAMPLE= 65 MSPS

C_PAR

H

VIN+

C_SAMPLE

90

S

SFDR (dBc)

85

80

75

70

65

60

55

50

C_SAMPLE

VIN–

H

C_PAR

H

SNR (dB)

Figure 43. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample mode and hold mode (see Figure 43). When the input

circuit is switched into sample mode, the signal source must be

capable of charging the sample capacitors and settling within

one-half of a clock cycle. A small resistor in series with each

input can help reduce the peak transient current injected from

the output stage of the driving source. In addition, low-Q inductors

or ferrite beads can be placed on each leg of the input to reduce

the high differential capacitance seen at the analog inputs, thus

0.8

0.2

0.4

0.6

1.0

1.2

1.4

1.6

ANALOG INPUT COMMON MODE VOLTAGE (V)

Figure 45. SNR/SFDR vs. Common-Mode Voltage,

f

_IN= 30 MHz, f_SAMPLE= 65 MSPS

Rev. 0 | Page 19 of 52

AD9228

ADT1–1WT

1:1 Z RATIO

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference

buffer creates the positive and negative reference voltages, REFT

and REFB, respectively, that define the span of the ADC core.

The output common-mode of the reference buffer is set to

midsupply, and the REFT and REFB voltages and span are

defined as

C

R

VIN+

VIN–

ADC

2Vp-p

49.9ꢀ

*C

R

DIFF

AD9228

AVDD

1kꢀ

AGND

C

*C

DIFF IS OPTIONAL

1kꢀ

0.1μF

Figure 46. Differential Transformer Coupled Configuration

for Baseband Applications

REFT = 1/2 (AVDD + VREF)

REFB = 1/2 (AVDD − VREF)

Span = 2 × (REFT − REFB) = 2 × VREF

ADT1–1WT

1:1 Z RATIO

2Vp-p

16nH

16nH 0.1μF

33ꢀ

VIN+

65ꢀ

ADC

AD9228

499ꢀ

16nH

2.2pF

1kꢀ

It can be seen from these equations that the REFT and REFB

voltages are symmetrical about the midsupply voltage and, by

definition, the input span is twice the value of the VREF voltage.

33ꢀ

VIN–

AVDD

1kꢀ

Maximum SNR performance is always achieved by setting the

ADC to the largest span in a differential configuration. In the

case of the AD9228, the largest input span available is 2 V p-p.

0.1μF

1kꢀ

Figure 47. Differential Transformer Coupled Configuration for IF Applications

Differential Input Configurations

Single-Ended Input Configuration

There are several ways in which to drive the AD9228 either

actively or passively. In either case, the optimum performance is

achieved by driving the analog input differentially. One example

is by using the AD8332 differential driver. It provides excellent

performance and a flexible interface to the ADC (see Figure 49)

for baseband applications. This configuration is common for

medical ultrasound systems.

A single-ended input may provide adequate performance in

cost-sensitive applications. In this configuration, SFDR and

distortion performance degrade due to the large input common-

mode swing. If the application requires a single-ended input

configuration, ensure that the source impedances on each input

are well matched in order to achieve the best possible performance.

A full-scale input of 2 V p-p can still be applied to the ADC’s VIN+

pin while the VIN− pin is terminated. Figure 48 details a typical

single-ended input configuration.

However, the noise performance of most amplifiers is not

adequate to achieve the true performance of the AD9228. For

applications where SNR is a key parameter, differential transfor-

mer coupling is the recommended input configuration. Two

examples are shown in Figure 46 and Figure 47.

AVDD

C

R

VIN+

0.1µF

AVDD

1kꢀ

25ꢀ

2V p-p

49.9ꢀ

ADC

AD9228

*C

In any configuration, the value of the shunt capacitor, C, is

dependent on the input frequency and may need to be reduced

or removed.

DIFF

1kꢀ

R

C

VIN–

0.1µF

1kꢀ

*C

DIFF IS OPTIONAL

Figure 48. Single-Ended Input Configuration

0.1μF

LOP

VIP

0.1μF

187ꢀ

374ꢀ

R

VOH

VOL

0.1μF 120nH

INH

VIN+

1V p-p

AD8332

1.0kꢀ

22pF

LNA

ADC

AD9228

VGA

C

1.0kꢀ

R

LMD

VIN–

VREF

0.1μF

187ꢀ

0.1μF

10μF

LON

VIN

274ꢀ

18nF

0.1μF

Figure 49. Differential Input Configuration Using the AD8332

Rev. 0 | Page 20 of 52

AD9228

CLOCK INPUT CONSIDERATIONS

In some applications, it is acceptable to drive the sample clock

inputs with a single-ended CMOS signal. In such applications,

CLK+ should be directly driven from a CMOS gate, and the

CLK− pin should be bypassed to ground with a 0.1 μF capacitor

in parallel with a 39 kΩ resistor (see Figure 53). Although the

CLK+ input circuit supply is AVDD (1.8 V), this input is

designed to withstand input voltages up to 3.3 V, making the

selection of the drive logic voltage very flexible.

For optimum performance, the AD9228 sample clock inputs

(CLK+ and CLK−) should be clocked with a differential signal.

This signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or capacitors. These pins are biased internally

and require no additional bias.

Figure 50 shows one preferred method for clocking the AD9228.

The low jitter clock source is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the secondary transformer limit clock excursions

into the AD9228 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD9228 and preserves the fast

rise and fall times of the signal, which are critical to low jitter

performance.

0.1µF

CLOCK

CLK

INPUT

OPTIONAL

100ꢀ

0.1µF

50ꢀ*

AD9510/1/2/3/4/5

CMOS DRIVER

CLK+

ADC

AD9228

CLK

0.1µF

CLK–

0.1µF

39kꢀ

*50ꢀ RESISTOR IS OPTIONAL

Figure 53. Single-Ended 1.8 V CMOS Sample Clock

MIN-CIRCUITS

ADT1–1WT, 1:1Z

0.1µF

CLK

0.1µF

CLOCK

INPUT

XFMR

CLOCK

INPUT

CLK+

OPTIONAL

0.1µF

50ꢀ*

100ꢀ

ADC

AD9228

CLK–

AD9510/1/2/3/4/5

CMOS DRIVER

50ꢀ

CLK+

0.1µF

ADC

AD9228

CLK

SCHOTTKY

DIODES:

0.1µF

CLK–

HSM2812

*50ꢀ RESISTOR IS OPTIONAL

Figure 50. Transformer Coupled Differential Clock

Figure 54. Single-Ended 3.3 V CMOS Sample Clock

If a low jitter clock is available, another option is to ac-couple a

differential PECL signal to the sample clock input pins as shown

in Figure 51. The AD9510/AD9511/AD9512/AD9513/AD9514/

AD9515 family of clock drivers offers excellent jitter performance.

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals. As a result, these ADCs may

be sensitive to clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic performance

characteristics. The AD9228 contains a duty cycle stabilizer (DCS)

that retimes the nonsampling edge, providing an internal clock

signal with a nominal 50% duty cycle. This allows a wide range

of clock input duty cycles without affecting the performance of

the AD9228. When the DCS is on, noise and distortion perfor-

mance are nearly flat for a wide range of duty cycles. The DCS

function cannot be turned off.

0.1µF

CLOCK

INPUT

CLK

CLK+

ADC

AD9228

100ꢀ

AD9510/1/2/3/4/5

PECL DRIVER

0.1µF

CLOCK

INPUT

CLK–

CLK

240ꢀ

50ꢀ*

*50ꢀ RESISTORS ARE OPTIONAL

Figure 51. Differential PECL Sample Clock

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately 10 clock cycles

to allow the DLL to acquire and lock to the new rate.

0.1µF

CLOCK

INPUT

CLK+

CLK

ADC

AD9228

100ꢀ

AD9510/1/2/3/4/5

LVDS DRIVER

0.1µF

CLOCK

INPUT

CLK–

CLK

50ꢀ*

*50ꢀ RESISTORS ARE OPTIONAL

Figure 52. Differential LVDS Sample Clock

Rev. 0 | Page 21 of 52

AD9228

Clock Jitter Considerations

Power Dissipation and Power-Down Mode

High speed, high resolution ADCs are sensitive to the quality of the

clock input. The degradation in SNR at a given input frequency

(f_A) due only to aperture jitter (t_J) can be calculated by

As shown in Figure 56 and Figure 57, the power dissipated by

the AD9228 is proportional to its sample rate. The digital power

dissipation does not vary much because it is determined primarily

by the DRVDD supply and bias current of the LVDS output drivers.

SNR degradation = 20 × log 10 [1/2 × π × f_A× t_J]

180

160

140

120

100

80

360

340

320

300

280

260

240

220

200

180

In this equation, the rms aperture jitter represents the root mean

square of all jitter sources, including the clock input, analog input

signal, and ADC aperture jitter specifications. IF undersampling

applications are particularly sensitive to jitter (see Figure 55).

AVDD CURRENT

TOTAL POWER

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the AD9228.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another

type of source (by gating, dividing, or other methods), it should

be retimed by the original clock at the last step.

60

40

DRVDD CURRENT

20

0

10

15

20

25

30

35

40

ENCODE (MSPS)

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs (visit www.analog.com).

Figure 56. Supply Current vs. f_SAMPLEfor f_IN= 10.3 MHz, f_SAMPLE= 40 MSPS

250

480

460

440

420

400

380

360

340

320

300

130

AVDD CURRENT

200

RMS CLOCK JITTER REQUIREMENT

120

110

TOTAL POWER

150

100

16 BITS

100

90

80

70

60

50

40

14 BITS

12 BITS

50

0

10 BITS

DRVDD CURRENT

0.125 ps

0.25 ps

0.5 ps

10

20

30

40

50

60

1.0 ps

ENCODE (MSPS)

2.0 ps

30

1

Figure 57. Supply Current vs. f_SAMPLEfor f_IN= 10.3 MHz, f_SAMPLE= 65 MSPS

10

100

1000

ANALOG INPUT FREQUENCY (MHz)

Figure 55. Ideal SNR vs. Input Frequency and Jitter

Rev. 0 | Page 22 of 52

AD9228

By asserting the PDWN pin high, the AD9228 is placed in

power-down mode. In this state, the ADC typically dissipates

3 mW. During power-down, the LVDS output drivers are placed in

a high impedance state. The AD9228 returns to normal operating

mode when the PDWN pin is pulled low. This pin is both 1.8 V

and 3.3 V tolerant.

100 Ω termination resistor placed as close to the receiver as

possible. No far-end receiver termination and poor differential

trace routing may result in timing errors. It is recommended

that the trace length is no longer than 24 inches and that the

differential output traces are kept close together and at equal

lengths. An example of the FCO and data stream with proper

trace length and position can be found in Figure 58.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on REFT and REFB are

discharged when entering power-down mode and must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in the power-down

mode; shorter cycles result in proportionally shorter wake-up

times. With the recommended 0.1 ꢀF and 2.2 ꢀF decoupling

capacitors on REFT and REFB, it takes approximately 1 sec to

fully discharge the reference buffer decoupling capacitors and

375 ꢀs to restore full operation.

There are a number of other power-down options available

when using the SPI port interface. The user can individually

power down each channel or put the entire device into standby

mode. This allows the user to keep the internal PLL powered

when fast wake-up times (~600 ns) are required. See the

Memory Map section for more details on using these features.

2.5ns/DIV

CH1 200mV/DIV = DCO

CH2 200mV/DIV = DATA

CH3 500mV/DIV = FCO

Figure 58. LVDS Output Timing Example in ANSI Mode (Default)

An example of the LVDS output using the ANSI standard (default)

data eye and a time interval error (TIE) jitter histogram with

trace lengths less than 24 inches on regular FR-4 material is

shown in Figure 59. Figure 60 shows an example of when the

trace lengths exceed 24 inches on regular FR-4 material. Notice

that the TIE jitter histogram reflects the decrease of the data eye

opening as the edge deviates from the ideal position. It is up to

the user to determine if the waveforms meet the timing budget

of the design when the trace lengths exceed 24 inches. Additional

SPI options allow the user to further increase the internal ter-

mination (increasing the current) of all four outputs in order to

drive longer trace lengths (see Figure 61). Even though this

produces sharper rise and fall times on the data edges and is less

prone to bit errors, the power dissipation of the DRVDD supply

increases when this option is used. Also notice in Figure 61 that

the histogram has improved. See the Memory Map section for

more details.

Digital Outputs and Timing

The AD9228 differential outputs conform to the ANSI-644

LVDS standard on default power-up. This can be changed to a

low power, reduced signal option similar to the IEEE 1596.3

standard using the SDIO/ODM pin or via the SPI. This LVDS

standard can further reduce the overall power dissipation of the

device by roughly 15 mW. See the SDIO/ODM Pin section or

Table 15 in the Memory Map section for more information. The

LVDS driver current is derived on-chip and sets the output

current at each output equal to a nominal 3.5 mA. A 100 Ω

differential termination resistor placed at the LVDS receiver

inputs results in a nominal 350 mV swing at the receiver.

The AD9228 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs that have LVDS capability

for superior switching performance in noisy environments.

Single point-to-point net topologies are recommended with a

Rev. 0 | Page 23 of 52

AD9228

EYE: ALL BITS

ULS: 9599/15599

ULS: 10000/15600

400

200

500

0

–200

–400

–500

–1ns

–0.5ns

0ns

0.5ns

1ns

–1ns

–0.5ns

0ns

0.5ns

1ns

100

50

0

50

0

–150ps –100ps

–50ps

–0ps

50ps

100ps

150ps

–100ps

–0ps

100ps

Figure 59. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less

than 24 Inches on Standard FR-4

Figure 61. Data Eye for LVDS Outputs in ANSI Mode with 100 Ω Termination

on and Trace Lengths Greater than 24 Inches on Standard FR-4

The format of the output data is offset binary by default. An

example of the output coding format can be found in Table 8.

If it is desired to change the output data format to twos

complement, see the Memory Map section.

EYE: ALL BITS

ULS: 9600/15600

200

Table 8. Digital Output Coding

(VIN+) − (VIN−), Input

Code Span = 2 V p-p (V)

0

Digital Output Offset Binary

(D11 ... D0)

ꢁ095

20ꢁꢀ

20ꢁꢂ

0

+1.00

1111 1111 1111

1000 0000 0000

0111 1111 1111

0000 0000 0000

0.00

−0.000ꢁꢀꢀ

−1.00

–200

100

–1ns

–0.5ns

0ns

0.5ns

1ns

Data from each ADC is serialized and provided on a separate

channel. The data rate for each serial stream is equal to 12 bits

times the sample clock rate, with a maximum of 780 Mbps

(12 bits × 65 MSPS = 780 Mbps). The lowest typical conversion

rate is 10 MSPS. However, if lower sample rates are required for

a specific application, the PLL can be set up for encode rates

lower than 10 MSPS via the SPI. This allows encode rates as low

as 5 MSPS. See the Memory Map section to enable this feature.

50

0

–150ps –100ps

–50ps

–0ps

50ps

100ps

150ps

Figure 60. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths

Greater than 24 Inches on Standard FR-4

Rev. 0 | Page 2ꢁ of 52

AD9228

Two output clocks are provided to assist in capturing data from

the AD9228. The DCO is used to clock the output data and is

equal to six times the sampling clock (CLK) rate. Data is

clocked out of the AD9228 and must be captured on the rising

and falling edges of the DCO that supports double data rate

(DDR) capturing. The frame clock out (FCO) is used to signal

the start of a new output byte and is equal to the sampling clock

rate. See the timing diagram shown in Figure 2 for more

information.

Table 9. Flex Output Test Modes

Subject

to Data

Format

Output Test

Mode Bit

Sequence

Pattern Name

OFF (default)

Midscale Short

Digital Output Word 1

Digital Output Word 2

Select

0000

0001

N/A

Same

N/A

Yes

1000 0000 (ꢀ-bit)

10 0000 0000 (10-bit)

1000 0000 0000 (12-bit)

10 0000 0000 0000 (1ꢁ-bit)

0010

0011

0100

+Full-Scale Short

−Full-Scale Short

Checker Board

1111 1111 (ꢀ-bit)

Same

Yes

No

11 1111 1111 (10-bit)

1111 1111 1111 (12-bit)

11 1111 1111 1111 (1ꢁ-bit)

0000 0000 (ꢀ-bit)

00 0000 0000 (10-bit)

0000 0000 0000 (12-bit)

00 0000 0000 0000 (1ꢁ-bit)

1010 1010 (ꢀ-bit)

0101 0101 (ꢀ-bit)

10 1010 1010 (10-bit)

1010 1010 1010 (12-bit)

10 1010 1010 1010 (1ꢁ-bit)

N/A

01 0101 0101 (10-bit)

0101 0101 0101 (12-bit)

01 0101 0101 0101 (1ꢁ-bit)

N/A

0101

0110

0111

PN Sequence Long¹

PN Sequence Short¹

One/Zero Word Toggle

Yes

No

1111 1111 (ꢀ-bit)

0000 0000 (ꢀ-bit)

11 1111 1111 (10-bit)

1111 1111 1111 (12-bit)

11 1111 1111 1111 (1ꢁ-bit)

00 0000 0000 (10-bit)

0000 0000 0000 (12-bit)

00 0000 0000 0000 (1ꢁ-bit)

1000

1001

User Input

One/Zero Bit Toggle

Register 0x19 to Register 0x1A

1010 1010 (ꢀ-bit)

Register 0x1B to Register 0x1C

N/A

No

10 1010 1010 (10-bit)

1010 1010 1010 (12-bit)

10 1010 1010 1010 (1ꢁ-bit)

1010

1011

1100

1× Sync

0000 1111 (ꢀ-bit)

N/A

No

00 0001 1111 (10-bit)

0000 0011 1111 (12-bit)

00 0000 0111 1111 (1ꢁ-bit)

One Bit High

Mixed Frequency

1000 0000 (ꢀ-bit)

10 0000 0000 (10-bit)

1000 0000 0000 (12-bit)

10 0000 0000 0000 (1ꢁ-bit)

1010 0011 (ꢀ-bit)

10 0110 0011 (10-bit)

1010 0011 0011 (12-bit)

10 1000 0110 0111 (1ꢁ-bit)

¹PN, or pseudorandom number, sequence is determined by the number of bits in the shift register. The long sequence is 23 bits and the short sequence is

9 bits. How the sequence is generated and utilized is described in the ITU O.150 standard. In general, the polynomial, X23 + X1ꢀ + 1 (long) and X9 + X5 + 1

(short), defines the pseudorandom sequence.

Rev. 0 | Page 25 of 52

AD9228

Table 10. Output Driver Mode Pin Settings

When using the serial port interface (SPI), the DCO phase can

be adjusted in 60° increments relative to the data edge. This

enables the user to refine system timing margins if required.

The default DCO timing, as shown in Figure 2, is 90° relative to

the output data edge.

Resulting

Selected ODM ODM Voltage

Normal

operation

Output Standard FCO and DCO

10 kΩ to AGND ANSI-ꢃꢁꢁ

ANSI-ꢃꢁꢁ

(default)

ODM

AVDD

Low power,

reduced signal

option

Low power,

reduced

signal

An 8-, 10-, and 14-bit serial stream can also be initiated from

the SPI. This allows the user to implement and test compatibility

to lower and higher resolution systems. When changing the

resolution to an 8- or 10-bit serial stream, the data stream is

shortened. See Figure 3 for the 10-bit example. However, when

using the 14-bit option, the data stream stuffs two 0s at the end

of the normal 14-bit serial data.

option

SCLK/DTP Pin

This pin is for applications that do not require SPI mode operation.

The serial clock/digital test pattern (SCLK/DTP) pin can enable

a single digital test pattern if this pin and the CSB pin are held

high during device power-up. When the DTP is tied to AVDD,

all the ADC channel outputs shift out the following pattern:

1000 0000 0000. The FCO and DCO outputs still work as usual

while all channels shift out the repeatable test pattern. This pattern

allows the user to perform timing alignment adjustments among

the FCO, DCO, and output data. For normal operation, this pin

should be tied to AGND through a 10 kΩ resistor. This pin is

both 1.8 V and 3.3 V tolerant.

When using the SPI, all of the data outputs can also be inverted

from their nominal state. This is not to be confused with

inverting the serial stream to an LSB-first mode. In default

mode, as shown in Figure 2, the MSB is represented first in the

data output serial stream. However, this can be inverted so that

the LSB is represented first in the data output serial stream (see

Figure 4).

There are 12 digital output test pattern options available that

can be initiated through the SPI. This is a useful feature when

validating receiver capture and timing. Refer to Table 9 for the

output bit sequencing options available. Some test patterns have

two serial sequential words and can be alternated in various

ways, depending on the test pattern chosen. It should be noted

that some patterns may not adhere to the data format select

option. In addition, customer user patterns can be assigned in

the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode

options can support 8- to 14-bit word lengths in order to verify

data capture to the receiver.

Table 11. Digital Test Pattern Pin Settings

Resulting

FCO and DCO

Selected DTP DTP Voltage

Normal

operation

DTP

D+ and D−

10 kΩ to AGND Normal

Normal operation

operation

AVDD

1000 0000 0000 Normal operation

Additional and custom test patterns can also be observed when

commanded from the SPI port. Consult the Memory Map

section to choose from the different options available.

CSB Pin

Please consult the Memory Map section for information on how

to change these additional digital output timing features through

the serial port interface or SPI.

The chip select bar (CSB) pin should be tied to AVDD for

applications that do not require SPI mode operation. By tying

CSB high, all SCLK and SDIO information is ignored. This pin

is both 1.8 V and 3.3 V tolerant.

SDIO/ODM Pin

RBIAS Pin

This pin is for applications that do not require SPI mode operation.

The SDIO/ODM pin can enable a low power, reduced signal option

similar to the IEEE 1596.3 reduced range link output standard if

this pin and the CSB pin are tied to AVDD during device power-

up. This option should only be used when the digital output trace

lengths are less than 2 inches in length to the LVDS receiver. The

FCO, DCO, and outputs still work as usual, but the LVDS signal

swing of all channels is reduced from 350 mV p-p to 200 mV p-p.

This output mode allows the user to further lower the power on

the DRVDD supply. For applications where this pin is not used,

it should be tied low. In this case, the device pin can be left open,

and the 30 kΩ internal pull-down resistor pulls this pin low. This

pin is only 1.8 V tolerant. If applications require this pin to be

driven from a 3.3 V logic level, insert a 1 kΩ resistor in series

with this pin to limit the current.

To set the internal core bias current of the ADC, place a resistor

(nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The

resistor current is derived on-chip and sets the ADC’s AVDD

current to a nominal 232 mA at 65 MSPS. Therefore, it is

imperative that at least a 1% tolerance on this resistor be used to

achieve consistent performance. If SFDR performance is not as

critical as power, simply adjust the ADC core current to achieve

a lower power. Figure 62 and Figure 63 show the relationship

between the dynamic range and power as the RBIAS resistance

is changed. Nominally, we use a 10.0 kΩ value, as indicated by

the dashed line.

Rev. 0 | Page 2ꢃ of 52

AD9228

90

85

80

75

70

65

75

70

65

60

55

50

Internal Reference Operation

A comparator within the AD9228 detects the potential at the

SENSE pin and configures the reference. If SENSE is grounded,

the reference amplifier switch is connected to the internal

resistor divider (see Figure 64), setting VREF to 1 V.

SNR

SFDR

The REFT and REFB pins establish their input span of the ADC

core from the reference configuration. The analog input full-

scale range of the ADC equals twice the voltage at the reference

pin for either an internal or an external reference configuration.

If the reference of the AD9228 is used to drive multiple

converters to improve gain matching, the loading of the refer-

ence by the other converters must be considered. Figure 66

depicts how the internal reference voltage is affected by loading.

2

4

6

8

10

12

14

16

18

20

22

24

RESISTANCE (kꢀ)

Figure 62. SFDR vs. RBIAS

600

500

400

300

200

100

0

VIN+

VIN–

REFT

0.1µF

+

ADC

CORE

0.1µF

2.2µF

REFB

0.1µF

V

REF

1µF

0.1µF

0.5V

SELECT

LOGIC

SENSE

3

8

13

18

23

RESISTANCE (kꢀ)

Figure 63. IAVDD vs. RBIAS

Figure 64. Internal Reference Configuration

Voltage Reference

VIN+

VIN–

A stable and accurate 0.5 V voltage reference is built into the

AD9228. This is gained up by a factor of 2 internally, setting

REFT

V

_REFto 1.0 V, which results in a full-scale differential input span

0.1µF

REFB

+

ADC

CORE

of 2 V p-p. The V_REFis set internally by default; however, the

VREF pin can be driven externally with a 1.0 V reference to

achieve more accuracy.

2.2µF

0.1µF

V

REF

When applying the decoupling capacitors to the VREF, REFT,

and REFB pins, use ceramic low ESR capacitors. These capacitors

should be close to the ADC pins and on the same layer of the

PCB as the AD9228. The recommended capacitor values and

configurations for the AD9228 reference pin can be found in

Figure 64.

1µF

0.1µF

AVDD

0.5V

SELECT

LOGIC

SENSE

Table 12. Reference Settings

Figure 65. External Reference Operation

Resulting

Selected

Mode

SENSE

Voltage

Resulting

VREF (V)

Differential

Span (V p-p)

External

AVDD

N/A

2 × external

reference

Reference

Internal,

2 V p-p FSR

AGND to 0.2 V

1.0

2.0

Rev. 0 | Page 2ꢂ of 52

AD9228

0.20

0.15

0.10

0.05

0

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 67 shows the typical drift characteristics of the

internal reference in 1 V mode.

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. The external

reference is loaded with an equivalent 6 kΩ load. An internal

reference buffer generates the positive and negative full-scale

references, REFT and REFB, for the ADC core. Therefore, the

external reference must be limited to a nominal of 1.0 V.

–0.05

–0.10

–0.15

–0.20

–40

–20

0

20

40

60

80

5

TEMPERATURE (°C)

Figure 67. Typical V_REFDrift

0

–5

–10

–15

–20

–25

–30

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

CURRENT LOAD (mA)

Figure 66. V_REFAccuracy vs. Load

Rev. 0 | Page 2ꢀ of 52

AD9228

SERIAL PORT INTERFACE (SPI)

middle of any byte transfer, the SPI state machine is reset and

the device waits for a new instruction.

The AD9228 serial port interface allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. This gives

the user added flexibility and customization depending on the

application. Addresses are accessed via the serial port and can

be written to or read from via the port. Memory is organized

into bytes that can be further divided down into fields, as doc-

umented in the Memory Map section. Detailed operational

information can be found in the Analog Devices user manual

Interfacing to High Speed ADCs via SPI.

In addition to the operation modes, the SPI port can be

configured to operate in different manners. For applications

that do not require a control port, the CSB line can be tied and

held high. This places the remainder of the SPI pins in their

secondary mode as defined in the Serial Port Interface (SPI)

section. CSB can also be tied low to enable 2-wire mode. When

CSB is tied low, SCLK and SDIO are the only pins required for

communication. Although the device is synchronized during

power-up, caution must be exercised when using this mode to

ensure that the serial port remains synchronized with the CSB

line. When operating in 2-wire mode, it is recommended to use

a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB

line, streaming mode can be entered but not exited.

There are three pins that define the serial port interface or SPI

to this particular ADC. They are the SCLK, SDIO, and CSB

pins. The SCLK (serial clock) is used to synchronize the read

and write data presented to the ADC. The SDIO (serial data

input/output) is a dual-purpose pin that allows data to be sent

to and read from the internal ADC memory map registers. The

CSB (chip select bar) is an active low control that enables or

disables the read and write cycles (see Table 13).

In addition to word length, the instruction phase determines if

the serial frame is a read or write operation, allowing the serial

port to be used to both program the chip and read the contents

of the on-chip memory. If the instruction is a readback operation,

performing a readback causes the serial data input/output (SDIO)

pin to change direction from an input to an output at the

appropriate point in the serial frame.

Table 13. Serial Port Pins

Function

SCLK

Serial Clock. The serial shift clock in. SCLK is used to

synchronize serial interface reads and writes.

Serial Data Input/Output. A dual-purpose pin. The

typical role for this pin is an input or output, depending

on the instruction sent and the relative position in the

timing frame.

SDIO

CSB

Data can be sent in MSB- or LSB-first mode. MSB-first mode

is the default at power-up and can be changed by adjusting the

configuration register. For more information about this and

other features, see the user manual Interfacing to High Speed

ADCs via SPI.

Chip Select Bar (Active Low). This control gates the read

and write cycles.

HARDWARE INTERFACE

The falling edge of the CSB in conjunction with the rising edge

of the SCLK determines the start of the framing sequence. During

an instruction phase, a 16-bit instruction is transmitted followed

by one or more data bytes, which is determined by Bit Fields

W0 and W1. An example of the serial timing and its definitions

can be found in Figure 68 and Table 14. In normal operation,

CSB is used to signal to the device that SPI commands are to be

received and processed. When CSB is brought low, the device

processes SCLK and SDIO to process instructions. Normally,

CSB remains low until the communication cycle is complete.

However, if connected to a slow device, CSB can be brought

high between bytes, allowing old microcontrollers enough time

to transfer data into shift registers. CSB can be stalled when

transferring one, two, or three bytes of data. When W0 and W1

are set to 11, the device enters streaming mode and continues

to process data, either reading or writing, until the CSB is taken

high to end the communication cycle. This allows complete

memory transfers without having to provide additional instruc-

tions. Regardless of the mode, if CSB is taken high in the

The pins described in Table 13 compose the physical interface

between the user’s programming device and the serial port of

the AD9228. The SCLK and CSB pins function as inputs when

using the SPI interface. The SDIO pin is bidirectional, functioning

as an input during write phases and as an output during readback.

This interface is flexible enough to be controlled by either serial

PROMS or PIC mirocontrollers. This provides the user an

alternative method, other than a full SPI controller, to program

the ADC (see the AN-812 Application Note).

If the user chooses not to use the SPI interface, these pins serve

a dual function and are associated with secondary functions

when the CSB is strapped to AVDD during device power-up.

See the Theory of Operation section for details on which pin-

strappable functions are supported on the SPI pins.

Rev. 0 | Page 29 of 52

AD9228

t_DS

t_HI

t_CLK

t_H

t_S

t_DH

t_LO

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

DON’T CARE

Figure 68. Serial Timing Details

Table 14. Serial Timing Definitions

Parameter

Timing (minimum, ns)

Description

t_DS

t_DH

t_CLK

t_S

5

2

ꢁ0

5

Set-up time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the clock

Set-up time between CSB and SCLK

t_H

2

Hold time between CSB and SCLK

t_HI

t_LO

1ꢃ

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

Rev. 0 | Page 30 of 52

AD9228

MEMORY MAP

READING THE MEMORY MAP TABLE

RESERVED LOCATIONS

Each row in the memory map table has eight address locations.

The memory map is roughly divided into three sections: chip

configuration register map (Address 0x00 to Address 0x02), device

index and transfer register map (Address 0x05 and Address 0xFF),

and program register map (Address 0x08 to Address 0x25).

Undefined memory locations should not be written to except

when writing the default values suggested in this data sheet.

Addresses that have values marked as 0 should be considered

reserved and have a 0 written into their registers during power-up.

DEFAULT VALUES

The left-hand column of the memory map indicates the register

address number in hexadecimal. The default value of this address is

shown in hexadecimal in the right-hand column. The Bit 7 (MSB)

column is the start of the default hexadecimal value given. For

example, Hexadecimal Address 0x09, Clock, has a hexadecimal

default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0,

Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001

in binary. This setting is the default for the duty cycle stabilizer in

the on condition. By writing a 0 to Bit 6 at this address, the duty

cycle stabilizer turns off. For more information on this and other

functions, consult the user manual Interfacing to High Speed

ADCs via SPI.

Coming out of reset, critical registers are preloaded with default

values. These values are indicated in Table 15, where an X refers

to an undefined feature.

LOGIC LEVELS

An explanation of various registers follows: “Bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly, “clear a bit” is synonymous with “bit is set to

Logic 0” or “writing Logic 0 for the bit.”

Rev. 0 | Page 31 of 52

AD9228

Table 15. Memory Map Register

Default

Value

(Hex)

Addr.

(Hex)

Bit 7

Bit 0

(LSB)

Default Notes/

Comments

Parameter Name (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Chip Configuration Registers

00

chip_port_config

0

LSB first

1 = on

Soft

reset

1

Soft

reset

LSB first

1 = on

0

0x1ꢀ

The nibbles

should be

0 = off

(default)

1 = on

0 = off

(default)

1 = on

0 = off

(default)

0 = off

(default)

mirrored so that

LSB- or MSB-first

mode registers

correctly

regardless of

shift mode.

01

02

chip_id

ꢀ-bit Chip ID Bits ꢂ:0

(AD922ꢀ = 0x02), (default)

0x02

Default is unique

chip ID, different

for each device.

This is a read-

only register.

chip_grade

X

Child ID ꢃ:ꢁ

X

Read

only

Child ID used to

differentiate

graded devices.

(identify device variants of Chip ID)

000 = ꢃ5 MSPS,

001 = ꢁ0 MSPS

Device Index and Transfer Registers

05

device_index_A

X

Clock

Channel

DCO

1 = on

0 = off

Clock

Channel

FCO

1 = on

0 = off

Data

Channel

D

Data

Channel

C

Data

Channel

B

Data

Channel

A

0x0F

0x00

Bits are set to

determine which

on-chip device

receives the next

write command.

1 = on

(default) (default) (default) (default)

(default) (default) 0 = off

0 = off

FF

device_update

X

SW

Synchronously

transfers data

from the master

shift register to

the slave.

transfer

1 = on

0 = off

(default)

ADC Functions

0ꢀ

modes

X

Internal power-down mode

000 = chip run (default)

001 = full power-down

010 = standby

0x00

0x01

Determines

various generic

modes of chip

operation.

011 = reset

09

clock

X

Duty

Turns the

cycle

internal duty

cycle stabilizer

on and off.

stabilizer

1 = on

(default)

0 = off

0D

test_io

User test mode

00 = off (default)

01 = on, single alternate 1 = on

10 = on, single once

11 = on, alternate once

Reset PN Reset

long gen PN short

0x00

When set, the

test data is

placed on the

output pins in

place of normal

data.

Output test mode—see Table 9 in the

Digital Outputs and Timing section

0000 = off (default)

0001 = midscale short

0010 = +FS short

0011 = −FS short

gen

0 = off

1 = on

(default) 0 = off

(default)

0100 = checker board output

0101 = PN 23 sequence

0110 = PN 9

0111 = one/zero word toggle

1000 = user input

1001 = one/zero bit toggle

1010 = 1× sync

1011 = one bit high

1100 = mixed bit frequency

(format determined by output_mode)

Rev. 0 | Page 32 of 52

AD9228

Default

Value

(Hex)

Addr.

(Hex)

Bit 7

Bit 0

(LSB)

Default Notes/

Comments

Parameter Name (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

1ꢁ

output_mode

X

0 = LVDS

ANSI

(default)

1 = LVDS

low

X

Output

invert

1 = on

0 = off

(default)

00 = offset binary

(default)

01 = twos

0x00

Configures the

outputs and the

format of the

data.

complement

power,

(IEEE

159ꢃ.3

similar)

15

output_adjust

X

Output driver

termination

00 = none (default)

01 = 200 Ω

10 = 100 Ω

11 = 100 Ω

X

0x00

Determines

LVDS or other

output properties.

Primarily func-

tions to set the

LVDS span and

common-mode

levels in place of

an external

resistor.

1ꢃ

output_phase

X

0011 = output clock phase adjust

(0000 through 1010)

0x03

On devices that

utilize global

clock divide,

determines

which phase of

the divider

output is used to

supply the

output clock.

Internal latching

is unaffected.

(Default: 1ꢀ0° relative to DATA edge)

0000 = 0° relative to DATA edge

0001 = ꢃ0° relative to DATA edge

0010 = 120° relative to DATA edge

0011 = 1ꢀ0° relative to DATA edge

0100 = 2ꢁ0° relative to DATA edge

0101 = 300° relative to DATA edge

0110 = 3ꢃ0° relative to DATA edge

0111 = ꢁ20° relative to DATA edge

1000 = ꢁꢀ0° relative to DATA edge

1001 = 5ꢁ0° relative to DATA edge

1010 = ꢃ00° relative to DATA edge

1011 to 1111 = ꢃꢃ0° relative to DATA edge

19

1A

1B

1C

21

user_patt1_lsb

user_patt1_msb

user_patt2_lsb

user_patt2_msb

serial_control

Bꢂ

Bꢃ

B1ꢁ

Bꢃ

B5

B13

B5

Bꢁ

B12

Bꢁ

B3

B2

B1

B9

B1

B9

B0

Bꢀ

B0

Bꢀ

0x00

User-defined

pattern, 1 LSB.

B15

Bꢂ

B11

B3

B10

B2

User-defined

pattern, 1 MSB.

User-defined

pattern, 2 LSB.

B15

B1ꢁ

X

B13

X

B12

X

B11

B10

User-defined

pattern, 2 MSB.

LSB first

1 = on

0 = off

<10

MSPS,

low

encode

rate

000 = 12 bits (default, normal bit

stream)

001 = ꢀ bits

010 = 10 bits

011 = 12 bits

Serial stream

control. Default

causes MSB first

and the native

bit stream

(default)

mode

1 = on

0 = off

(default)

100 = 1ꢁ bits

(global).

22

serial_ch_stat

X

Channel

output

reset

Channel

power-

down

0x00

Used to power

down individual

sections of a

1 = on

0 = off

1 = on

0 = off

converter (local).

(default) (default)

Rev. 0 | Page 33 of 52

AD9228

Power and Ground Recommendations

Exposed Paddle Thermal Heat Slug Recommendations

When connecting power to the AD9228, it is recommended

that two separate 1.8 V supplies be used: one for analog (AVDD)

and one for digital (DRVDD). If only one supply is available, it

should be routed to the AVDD first and then tapped off and

isolated with a ferrite bead or a filter choke preceded by

decoupling capacitors for the DRVDD. The user can employ

several different decoupling capacitors to cover both high and

low frequencies. These should be located close to the point of

entry at the PC board level and close to the parts with minimal

trace length.

It is required that the exposed paddle on the underside of the

ADC is connected to analog ground (AGND) to achieve the

best electrical and thermal performance of the AD9228. An

exposed continuous copper plane on the PCB should mate to

the AD9228 exposed paddle, Pin 0. The copper plane should

have several vias to achieve the lowest possible resistive thermal

path for heat dissipation to flow through the bottom of the PCB.

These vias should be solder filled or plugged.

To maximize the coverage and adhesion between the ADC and

PCB, partition the continuous copper plane by overlaying a

silkscreen on the PCB into several uniform sections. This provides

several tie points between the two during the reflow process.

Using one continuous plane with no partitions only guarantees

one tie point between the ADC and PCB. See Figure 69 for a

PCB layout example. For detailed information on packaging

and the PCB layout of chip scale packages, see the AN-772

Application Note, “A Design and Manufacturing Guide for the

Lead Frame Chip Scale Package (LFCSP),” at www.analog.com.

A single PC board ground plane should be sufficient when

using the AD9228. With proper decoupling and smart parti-

tioning of the PC board’s analog, digital, and clock sections,

optimum performance is easily achieved.

SILKSCREEN PARTITION

PIN 1 INDICATOR

Figure 69. Typical PCB Layout

Rev. 0 | Page 3ꢁ of 52

AD9228

EVALUATION BOARD

each section. At least one 1.8 V supply is needed with a 1 A current

capability for AVDD_DUT and DRVDD_DUT; however, it is

recommended that separate supplies be used for both analog

and digital. To operate the evaluation board using the VGA

option, a separate 5.0 V analog supply is needed. The 5.0 V

supply, or AVDD_5 V, should have a 1 A current capability. To

operate the evaluation board using the SPI and alternate clock

options, a separate 3.3 V analog supply is needed in addition to

the other supplies. The 3.3 V supply, or AVDD_3.3 V, should

have a 1 A current capability as well.

The AD9228 evaluation board provides all of the support cir-

cuitry required to operate the ADC in its various modes and

configurations. The converter can be driven differentially through a

transformer (default) or through the AD8332 driver. The ADC

can also be driven in a single-ended fashion. Separate power pins

are provided to isolate the DUT from the AD8332 drive circuitry.

Each input configuration can be selected by proper connection

of various jumpers (see Figure 72 to Figure 76). Figure 70 shows

the typical bench characterization setup used to evaluate the ac

performance of the AD9228. It is critical that the signal sources

used for the analog input and clock have very low phase noise

(<1 ps rms jitter) to realize the optimum performance of the

converter. Proper filtering of the analog input signal to remove

harmonics and lower the integrated or broadband noise at the

input is also necessary to achieve the specified noise performance.

INPUT SIGNALS

When connecting the clock and analog source, use clean signal

generators with low phase noise, such as Rohde & Schwarz SMHU

or HP8644 signal generators or the equivalent. Use a 1 m, shielded,

RG-58, 50 Ω coaxial cable for making connections to the evalu-

ation board. Enter the desired frequency and amplitude from the

ADC specifications tables. Typically, most ADI evaluation boards

can accept ~2.8 V p-p or 13 dBm sine wave input for the clock.

When connecting the analog input source, it is recommended

to use a multipole, narrow-band, band-pass filter with 50 Ω

terminations. ADI uses TTE, Allen Avionics, and K&L types of

band-pass filters. The filter should be connected directly to the

evaluation board if possible.

See Figure 72 to Figure 80 for the complete schematics and

layout diagrams that demonstrate the routing and grounding

techniques that should be applied at the system level.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching

power supply that provides a 6 V, 2 A maximum output. Simply

connect the supply to the rated 100 V ac to 240 V ac wall outlet

at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter

jack that connects to the PCB at P503. Once on the PC board,

the 6 V supply is fused and conditioned before connecting to

three low dropout linear regulators that supply the proper bias

to each of the various sections on the board.

OUTPUT SIGNALS

The default setup uses the HSC-ADC-FPGA high speed

deserialization board to deserialize the digital output data and

convert it to parallel CMOS. These two channels interface

directly with the ADI standard dual-channel FIFO data capture

board (HSC-ADC-EVALA-DC). Two of the four channels can

then be evaluated at the same time. For more information on

channel settings on these boards and their optional settings,

visit www.analog.com/FIFO.

When operating the evaluation board in a nondefault condition,

L504 to L507 can be removed to disconnect the switching

power supply. This enables the user to bias each section of the

board individually. Use P501 to connect a different supply for

WALL OUTLET

100V TO 240V AC

47Hz TO 63Hz

6V DC

2A MAX

5.0V

1.8V

3.3V

1.5V

3.3V

–

+

–

+

–

+

–

+

–

+

–

+

–

+

SWITCHING

POWER

SUPPLY

PC

RUNNING

ADC

ANALYZER

AND SPI

USER

ROHDE & SCHWARZ,

HSC-ADC-FPGA

HIGH SPEED

DESERIALIZATION

HSC-ADC-EVALA-DC

FIFO DATA

SMHU,

2V p-p SIGNAL

SYNTHESIZER

BAND-PASS

FILTER

XFMR

INPUT

CAPTURE

BOARD

AD9228

EVALUATION BOARD

BOARD

CHA–CHD

12-BIT

SERIAL

LVDS

SOFTWARE

2 CH

USB

CONNECTION

ROHDE & SCHWARZ,

SMHU,

12-BIT

PARALLEL

CMOS

CLK

2V p-p SIGNAL

SYNTHESIZER

SPI

Figure 70. Evaluation Board Connection

Rev. 0 | Page 35 of 52

AD9228

50 Ω terminated and ac-coupled to handle single-ended

sine wave types of inputs. The transformer converts the

single-ended input to a differential signal that is clipped

before entering the ADC clock inputs.

DEFAULT OPERATION AND JUMPER SELECTION

SETTINGS

The following is a list of the default and optional settings or

modes allowed on the AD9228 Rev. A evaluation board.

A differential LVPECL clock can also be used to clock the

ADC input using the AD9515 (U202). Simply populate

R225 and R227 with 0 Ω resistors and remove R217 and

R218 to disconnect the default clock path inputs. In addition,

populate C207 and C208 with a 0.1 μF capacitor and remove

C210 and C211 to disconnect the default cloth path outputs.

The AD9515 has many pin-strappable options that are set

to a default working condition. Consult the AD9515 data

sheet for more information about these and other options.

•

POWER: Connect the switching power supply that is

supplied in the evaluation kit between a rated 100 V ac

to 240 V ac wall outlet at 47 Hz to 63 Hz and P503.

AIN: The evaluation board is set up for a transformer-

coupled analog input with optimum 50 Ω impedance

matching out to 200 MHz (see Figure 71). For more

bandwidth response, the differential capacitor across the

analog inputs can be changed or removed. The common

mode of the analog inputs is developed from the center

tap of the transformer or AVDD_DUT/2.

If using an oscillator, two oscillator footprint options are

also available (OSC201) to check the ADC performance.

J205 gives the user flexibility in using the enable pin, which

is common on most oscillators.

0

–2

–3dB CUTOFF = 200MHz

–4

–6

•

PDWN: To enable the power-down feature, simply short

J201 to the on position (AVDD) on the PDWN pin.

SCLK/DTP: To enable one of the two digital test patterns

on the digital outputs of the ADC, use J204. If J204 is tied to

AVDD during device power-up, Test Pattern 1000 0000 0000

will be enabled. See the SCLK/DTP Pin section for details.

–8

–10

–12

–14

–16

•

SDIO/ODM: To enable the low power, reduced signal option

similar to the IEEE 1595.3 reduced range link LVDS output

standard, use J203. If J203 is tied to AVDD during device

power-up, it enables the LVDS outputs in a low power,

reduced signal option from the default ANSI standard.

This option changes the signal swing from 350 mV p-p to

200 mV p-p, which reduces the power of the DRVDD supply.

See the SDIO/ODM Pin section for more details.

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (MHz)

Figure 71. Evaluation Board Full Power Bandwidth

•

VREF: VREF is set to 1.0 V by tying the SENSE pin to

ground, R237. This causes the ADC to operate in 2.0 V p-p

full-scale range. A separate external reference option using

the ADR510 or ADR520 is also included on the evaluation

board. Simply populate R231 and R235 and remove C214.

Proper use of the VREF options is noted in the Voltage

Reference section.

•

CSB: To enable the SPI information on the SDIO and

SCLK pins that is to be processed, simply tie J202 low in

the always enable mode. To ignore the SDIO and SCLK

information, tie J202 to AVDD.

•

RBIAS: RBIAS has a default setting of 10 kΩ (R201) to

ground and is used to set the ADC core bias current. To

further lower the core power (excluding the LVDS driver

supply), simply change the resistor setting. However,

performance of the ADC will degrade depending on the

resistor chosen. See RBIAS section for more information.

D+, D−: If an alternative data capture method to the setup

described in Figure 72 is used, optional receiver terminations,

R206 to R211, can be installed next to the high speed back-

plane connector.

CLOCK: The default clock input circuitry is derived from a

simple transformer-coupled circuit using a high bandwidth

1:1 impedance ratio transformer (T201) that adds a very

low amount of jitter to the clock path. The clock input is

Rev. 0 | Page 3ꢃ of 52

AD9228

•

Remove R102, R115, R128, R141, T101, T102, T103, and

T104 in the default analog input path.

ALTERNATIVE ANALOG INPUT DRIVE

CONFIGURATION

The following is a brief description of the alternative analog

input drive configuration using the AD8332 dual VGA. If this

particular drive option is in use, some components may need to

be populated, in which case all the necessary components are

listed in Table 16. For more details on the AD8332 dual VGA,

including how it works and its optional pin settings, consult the

AD8332 data sheet.

Populate R101, R114, R127, and R140 with 0 Ω resistors in

the analog input path.

Populate R106, R107, R119, R120, R132, R133, R144, and

R145 with 10 kΩ resistors to provide an input common-

mode level to the analog input.

•

Populate R105, R113, R118, R124, R131, R137, R151, and

R160 with 0 Ω resistors in the analog input path.

To configure the analog input to drive the VGA instead of the

default transformer option, the following components need to

be removed and/or changed.

Currently, L301 to L308 and L401 to L408 are populated with 0 Ω

resistors to allow signal connection. This area allows the user to

design a filter if additional requirements are necessary.

Rev. 0 | Page 3ꢂ of 52

AD9228

AVDD_DUT

R105

DNP

R152

DNP

CH_A

C101

FB102 R108

R104

0ꢀ

P102

DNP

T101

0.1µF

10ꢀ 33ꢀ

VGA INPUT CONNECTION

INH1

1

6

VIN_A

AIN

R106

DNP

CHANNEL A

P101

R101

DNP

R161

2

3

5

4

R109

1kꢀ

C103

C104

2.2pF

CM1

499ꢀ

DNP

AIN

R107

DNP

R113

DNP

FB101

10ꢀ

R103

0ꢀ

C102

0.1µF

R102

64.9ꢀ

VIN_A

CH_A

CM1

FB103 R110

C105

DNP

R156

DNP

10ꢀ

33ꢀ

E101

AVDD_DUT

C106

DNP

R111

1kꢀ

C107

0.1µF

R112

1kꢀ

AVDD_DUT

R118

DNP

VGA INPUT CONNECTION

INH2

R153

DNP

CH_B

CHANNEL B

P103

FB105 R121

R114

DNP

T102

10ꢀ 33ꢀ

1

6

AIN

VIN_B

FB104

10ꢀ

R119

DNP

R115

64.9ꢀ

C108

0.1µF

R162

2

3

5

4

R123

1kꢀ

P104

DNP

C110

C111

2.2pF

CM2

499ꢀ

DNP

R120

DNP

R124

DNP

R116

0ꢀ

AIN

C109

0.1µF

E102

VIN_B

CH_B

CM2

R117

0ꢀ

FB106 R122

C112

DNP

R157

DNP

10ꢀ

33ꢀ

AVDD_DUT

C113

DNP

R125

1kꢀ

C114

0.1µF

R126

1kꢀ

AVDD_DUT

R131

DNP

R154

DNP

CH_C

C115

FB108 R134

P106

DNP

R130

0ꢀ

T103

0.1µF

10ꢀ 33ꢀ

VGA INPUT CONNECTION

INH3

1

6

VIN_C

AIN

R132

DNP

CHANNEL C

P105

R127

DNP

R163

2

3

5

4

R135

1kꢀ

C117

C118

2.2pF

CM3

499ꢀ

DNP

AIN

R133

DNP

R137

DNP

FB107

10ꢀ

R129

0ꢀ

C116

0.1µF

R128

64.9ꢀ

VIN_C

CH_C

CM3

FB109 R136

C119

DNP

R158

DNP

10ꢀ

33ꢀ

E103

AVDD_DUT

C120

DNP

R138

1kꢀ

C121

0.1µF

R139

1kꢀ

AVDD_DUT

R151

DNP

VGA INPUT CONNECTION

INH4

R155

DNP

CH_D

CHANNEL D

P107

FB111 R146

R140

DNP

T104

10ꢀ 33ꢀ

1

6

AIN

VIN_D

FB110

R144

DNP

R141

64.9ꢀ

C122

10ꢀ

0.1µF

R164

499ꢀ

2

3

5

4

R148

1kꢀ

C124

DNP

C125

CM4

P108

CM4

2.2pF

DNP

R145

DNP

R160

DNP

R143

0ꢀ

AIN

C123

0.1µF

R142

VIN_D

CH_D

CM4

0ꢀ

FB112 R147

C126

DNP

R159

DNP

10ꢀ

33ꢀ

E104

AVDD_DUT

C127

DNP

R149

1kꢀ

C128

0.1µF

R150

1kꢀ

AVDD_DUT

DNP: DO NOT POPULATE

Figure 72. Evaluation Board Schematic, DUT Analog Inputs

Rev. 0 | Page 3ꢀ of 52

AD9228

6

0 1 7 - 5 7 0 2

AVDD_DUT

CW

S 0

S 1

S 2

S 3

S 4

S 5

S 6

S 7

S 8

2 5

1 6

1 5

1 4

1 3

1 2

1 1

1 0

2

1

2

ꢀ k 1 0

R 2 0

3 3

3 1

1

5

3

D

G N

V S

S E R T

GND

ꢀ 0 k 1 0

R 2 0

P N - ꢀ D 1 0 0 k

R 2 6

4

7

9

P N - ꢀ D k 1 0 0

R 2 6 6

ꢀ 0 k 1 0

S 9

8

3

R 2 0

S 1 0

3 2

7

F E V R

6

B – N V I

B _ N V I

3 7

3 8

3 9

4 0

4 1

4 2

4 3

4 4

4 5

4 6

4 7

4 8

D C O

+

–

D C O

2 4

B + N V I

D D A V

D C O

2 3

2 2

2 1

2 0

T

D _ U D D A V

O

F C

O + F C

O – F C

A I S R B

S E N S E

F E V R

B F R E

F C

T U _ D E S E N V S

T U D _ F E V R

C H A

C H B

C H C

A

B

C

D

D +

D – A

1 9

D +

1 8

D – B

1

T

R E F

D D A V

3

1 7

T

D _ U D D A V

D +

1 6

D – C

1 5

C + N V I

C – N V I

C _ N V I

C H D

D +

1 4

D – D

1 3

Figure 73. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface

Rev. 0 | Page 39 of 52

AD9228

POPULATE L301-L308 WITH 0ꢀ

RESISTORS OR DESIGN YOUR

OWN FILTER.

R301

DNP

R302

DNP

EXTERNAL VARIABLE GAIN DRIVE

VG

C302

DNP

C301

DNP

VARIABLE GAIN CIRCUIT

L301

0ꢀ

L302 L303

L304

0ꢀ

(0-1.0V DC)

VG

0ꢀ

GND

CW

AVDD_5V

C303

C304

L307

0ꢀ

L306

0ꢀ

L305 DNP

DNP L308

R320

39kꢀ

R319

10kꢀ

0ꢀ

R303

DNP

R304

DNP

C305

0.1µF

C306 C307

0.1µF 0.1µF

C308

0.1µF

R306

374ꢀ

R305

374ꢀ

R311

C309

1000pF

10kꢀ

DNP

C310

0.1µF

R307

187ꢀ

R308

187ꢀ

R309

187ꢀ

R310

187ꢀ

R312

10kꢀ

U301

25

R313

10kꢀ

DNP

R314

ENBV

ENBL

HILO

VCM1

VIN1

VIP1

COM1

LOP1

RCLMP

16

26

27

28

29

30

31

32

10kꢀ

VG

GAIN

MODE

VCM2

VIN2

VIP2

COM2

LOP2

15

14

13

12

11

10

9

DNP

AD8332

C311

0.1µF

C313

0.1µF

C312

0.1µF

C314

0.1µF

R316

C320

0.1µF

R317

274ꢀ

C321

0.1µF

274ꢀ

R315 C315

10kꢀ 10µF

C316

0.1µF

C325

0.1µF

C326

10µF

R318

10kꢀ

C317

0.018µF

C322

0.018µF

C318

22pF

C323

22pF

L309

120nH

L310

120nH

C319

0.1µF

C324

0.1µF

DNP: DO NOT POPULATE

INH4

INH3

Figure 74. Evaluation Board Schematic, Optional DUT Analog Input Drive

Rev. 0 | Page ꢁ0 of 52

AD9228

A H C _ O S D

ꢀ 0

4 2 R 7

A H C _ I S D

ꢀ 0

4 2 R 0

A H C _ K L S C

ꢀ 0

4 2 R 8

A

_ C B H 1 C S

ꢀ 0

4 2 R 6

J401

PICVCC

1

2

PICVCC

GP1

GP0

3

5

4

6

GP1

GP0

MCLR/GP3

7

9

8

10

MCLR/GP3

ꢀ k 7 5 4 .

4 1 R 8

OPTIONAL

PIC PROGRAMMING HEADER

V

± 7 5 m = H N I = P O L H I

V 0 . V 5 - 5 2 .

2

P E O = S N L I A

V I E T G A E G N

V I E T G S I P O

V m 0 5 ± = L = O N I

L I O H P

V 0 . - 1 0 P E O = S N L I A

N I P P M A L R C

N

P E I D M O

_ 5 V D D A V

. R E

F I L T O W N

R U Y O N G E S D I R O S R O S T S E I R

ꢀ 0 H T I W 8 0 4 L - 1 0 4 L E T A L P U P O

_ A C H

F µ 0 1 0 8 .

ꢀ 4 2 7

R 4 1

4 2 C 0

6

2 N L O

8

M M C O

2 H V O

2 L V O

1 7

1 8

1 9

V P S 2

7

_ 5 V D D A V

2 H I N

6

_ A C H

_ B C H

N C

2 0

2 D L M

5

1 D L M

4

V P S V

1 L V O

_ 5 V D D A V

2 1

2 2

1 H I N

3

1 H V O

M M C O

2 3

2 4

V P S 1

_ 5 V D D A V

2

1 N L O

1

_ B C H

)

E R W E L P B O S I A D = V 1 – ( 0

B L A N E N W R E D W O O P

E

V

D D _ 5 A V

V . 0 1 - 0 = G N E A R I N

L O G A

V . 0 5 - V 5 2 . 2 = G N E A R I N G I H A

N I P O L H I

B

A A N S D L E A N N R O C H F T U I R C C E I V R D I A G V L N A O I T P O

Figure 75. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface (Continued)

Rev. 0 | Page ꢁ1 of 52

AD9228

1 9 0 7 - 7 2 0 5

D

G N

D

G N

1

D

G N

D

G N

1

Figure 76. Evaluation Board Schematic, Power Supply Inputs

Rev. 0 | Page ꢁ2 of 52

AD9228

Figure 77. Evaluation Board Layout, Primary Side

Rev. 0 | Page ꢁ3 of 52

AD9228

Figure 78. Evaluation Board Layout, Ground Plane

Rev. 0 | Page ꢁꢁ of 52

AD9228

Figure 79. Evaluation Board Layout, Power Plane

Rev. 0 | Page ꢁ5 of 52

AD9228

Figure 80. Evaluation Board Layout, Secondary Side (Mirrored Image)

Rev. 0 | Page ꢁꢃ of 52

AD9228

Table 16. Evaluation Board Bill of Materials (BOM)

Qnty.

per

Board REFDES

Item

Device

PCB

Capacitor

Pkg.

PCB

ꢁ02

Value

Mfg.

Mfg. Part Number

1

2

1

ꢂ5

AD922ꢀLFCSP_REVA

PCB

0.1 μF, ceramic,

C101, C102, C10ꢂ,

C10ꢀ, C109, C11ꢁ,

C115, C11ꢃ, C121,

C122, C123, C12ꢀ,

C201, C203, C20ꢁ,

C205, C20ꢃ, C210,

C211, C212, C213,

C21ꢃ, C21ꢂ, C21ꢀ,

C219, C220, C221,

C222, C223, C22ꢁ,

C310, C311, C312,

C313, C31ꢁ, C31ꢃ,

C319, C320, C321,

C32ꢁ, C325, Cꢁ09,

Cꢁ10, Cꢁ12, Cꢁ1ꢁ,

Cꢁ1ꢃ, Cꢁ1ꢂ, Cꢁ19,

Cꢁ22, Cꢁ23, Cꢁ2ꢁ,

Cꢁ25, Cꢁ2ꢂ, Cꢁ2ꢀ,

Cꢁ29, C503, C505,

C50ꢂ, C509, C51ꢃ,

C51ꢂ, C51ꢀ, C519,

C520, C521, C522,

C523, C52ꢁ, C525,

C52ꢃ, C52ꢂ, C52ꢀ,

C529, C530, C531

Panasonic

ECJ-0EB1A10ꢁK

X5R, 10 V, 10% tol

3

ꢁ

C10ꢁ, C111, C11ꢀ,

C125

Capacitor

ꢁ02

2.2 pF, ceramic,

COG, 0.25 pF tol,

50 V

Murata

GRM1555C1H2R2GZ01B

ꢁ

1

2

ꢁ

1

9

C315, C32ꢃ, Cꢁ13,

Cꢁ2ꢃ

C202

Capacitor

ꢀ05

ꢃ03

ꢁ02

120ꢃ

ꢃ03

10 μF, ꢃ.3 V 10%

ceramic, X5R

2.2 μF, ceramic,

X5R, ꢃ.3 V, 10% tol

1000 pF, ceramic,

XꢂR, 25 V, 10% tol

0.01ꢀ μF, ceramic,

XꢂR, 1ꢃ V, 10% tol

22 pF, ceramic,

NPO, 5% tol, 50 V

10 μF, tantalum,

1ꢃ V, 20% tol

AVX

0ꢀ05ꢃD10ꢃKAT2A

ECJ-1VB0J225K

5

Panasonic

Kemet

AVX

ꢃ

C309, Cꢁ11

C0ꢁ02C102K3RACTU

0ꢁ02YC1ꢀ3KAT2A

C0ꢁ02C220J5GACTU

TCA1C10ꢃMꢀR

ꢂ

C31ꢂ, C322, Cꢁ15,

Cꢁ20

C31ꢀ, C323, Cꢁ1ꢀ,

Cꢁ21

ꢀ

Kemet

Rohm

9

C501

10

C21ꢁ, C512, C513,

C51ꢁ, C515, C532,

C533, C53ꢁ, C535

1 μF, ceramic, X5R, Panasonic

ꢃ.3 V, 10% tol

ECJ-1VB0J105K

11

ꢀ

C305, C30ꢃ, C30ꢂ,

C30ꢀ, Cꢁ05, Cꢁ0ꢃ,

Cꢁ0ꢂ, Cꢁ0ꢀ

Capacitor

ꢀ05

0.1 μF, ceramic,

XꢂR, 50 V, 10% tol

AVX

0ꢀ055C10ꢁKAT2A

12

13

1ꢁ

15

1ꢃ

ꢁ

1

2

1

C502, C50ꢁ, C50ꢃ,

C50ꢀ

CR201

Capacitor

Diode

LED

ꢃ03

10 μF, ceramic,

X5R, ꢃ.3 V, 20% tol

30 V, 20 mA, dual

Schottky

Green, ꢁ V, 5 m

candela

Panasonic

ECJ-1VB0J10ꢃM

HSMS2ꢀ12

LNJ30ꢃGꢀTRA

SK33MSCT

S2A

SOT-23

ꢃ03

Agilent

Technologies

Panasonic

CRꢁ01, CR501

D502

Diode

DO-21ꢁAB 3 A, 30 V, SMC

DO-21ꢁAA 2 A, 50 V, SMC

Micro

Commercial Co.

Micro

D501

Commercial Co.

Rev. 0 | Page ꢁꢂ of 52

AD9228

Qnty.

per

Item

Board REFDES

Device

Pkg.

Value

Mfg.

Mfg. Part Number

1ꢂ

1

F501

Fuse

1210

ꢃ.0 V, 2.2 A trip-

current resettable

fuse

Tyco/Raychem NANOSMDC110F-2

1ꢀ

19

1

FER501

Choke Coil

2020

ꢃ03

10 μH, 5 A, 50 V,

190 Ω @ 100 MHz

10 Ω, test freq

100 MHz, 25% tol,

500 mA

Murata

DLW5BSN191SQ2L

BLM1ꢀBA100SN1

12

FB101, FB102, FB103,

FB10ꢁ, FB105, FB10ꢃ,

FB10ꢂ, FB10ꢀ, FB109,

FB110, FB111, FB112

Ferrite bead

20

21

22

1

2

1

JP301

Connector

2-pin

3-pin

12-pin

100 mil header

jumper, 2-pin

100 mil header

jumper, 3-pin

100 mil header

male, ꢁ × 3 triple

row straight

Samtec

TSW-102-0ꢂ-G-S

TSW-103-0ꢂ-G-S

TSW-10ꢁ-0ꢀ-G-T

J205, Jꢁ02

J201 to J20ꢁ

23

2ꢁ

25

2ꢃ

1

Jꢁ01

Connector

10-pin

1210

ꢁ02

100 mil header,

male, 2 × 5 double

row straight

10 μH, bead core

3.2 × 2.5 × 1.ꢃ

SMD, 2 A

120 nH, test freq

100 MHz, 5% tol,

150 mA

Samtec

TSW-105-0ꢀ-G-D

ꢀ

L501, L502, L503, L50ꢁ, Ferrite bead

L505, L50ꢃ, L50ꢂ, L50ꢀ

Panasonic-ECG EXC-CL3225U1

ꢁ

L309, L310, Lꢁ09, Lꢁ10 Inductor

Murata

LQG15HNR12J02B

ERJ-ꢃGEY0R00V

1ꢃ

L301, L302, L303, L30ꢁ, Resistor

L305, L30ꢃ, L30ꢂ, L30ꢀ,

ꢀ05

0 Ω, 1/ꢀ W, 5% tol

Panasonic

Lꢁ01, Lꢁ02, Lꢁ03, Lꢁ0ꢁ,

Lꢁ05, Lꢁ0ꢃ, Lꢁ0ꢂ, Lꢁ0ꢀ

2ꢂ

2ꢀ

1

5

OSC201

Oscillator

SMT

SMA

Clock oscillator,

ꢃ5.00 MHz, 3.3 V

Side-mount SMA

for 0.0ꢃ3" board

thickness

CTS REEVES

CB3LV-3C-ꢃ5M0000-T

1ꢁ2-0ꢂ11-ꢀ21

P101, P103, P105,

P10ꢂ, P201

Connector

Johnson

Components

29

1

P202

Connector

HEADER

1ꢁꢃ91ꢃ9-1, right

angle 2-pair,

25 mm, header

assembly

Tyco

1ꢁꢃ91ꢃ9-1

30

31

1

P503

Connector

Resistor

0.1", PCMT RAPCꢂ22, power

supply connector

Switchcraft

Panasonic

SC1153

15

R201, R205, R21ꢁ,

R215, R221, R239,

R312, R315, R31ꢀ,

Rꢁ11, Rꢁ1ꢁ, Rꢁ1ꢂ,

Rꢁ25, Rꢁ29, Rꢁ30

ꢁ02

10 kΩ, 1/1ꢃ W,

5% tol

ERJ-2GEJ103X

32

1ꢁ

R103, R11ꢂ, R129,

R1ꢁ2, R21ꢃ, R21ꢂ,

R21ꢀ, R223, R22ꢁ,

R23ꢂ, Rꢁ20, Rꢁ2ꢃ,

Rꢁ2ꢂ, Rꢁ2ꢀ

Resistor

ꢁ02

0 Ω, 1/1ꢃ W,

5% tol

Panasonic

ERJ-2GE0R00X

33

3ꢁ

ꢁ

R102, R115, R12ꢀ,

R1ꢁ1

R10ꢁ, R11ꢃ, R130,

R1ꢁ3

Resistor

ꢁ02

ꢃ03

ꢃꢁ.9 Ω, 1/1ꢃ W,

1% tol

0 Ω, 1/10 W,

5% tol

Panasonic

ERJ-2RKFꢃꢁR9X

ERJ-3GEY0R00V

Rev. 0 | Page ꢁꢀ of 52

AD9228

Qnty.

per

Item

Board REFDES

Device

Pkg.

Value

Mfg.

Mfg. Part Number

35

15

R109, R111, R112,

Resistor

ꢁ02

1 kΩ, 1/1ꢃ W,

1% tol

Panasonic

ERJ-2RKF1001X

R123, R125, R12ꢃ,

R135, R13ꢀ, R139,

R1ꢁꢀ, R1ꢁ9, R150,

Rꢁ31, Rꢁ32, Rꢁ33

3ꢃ

ꢀ

R10ꢀ, R110, R121,

R122, R13ꢁ, R13ꢃ,

R1ꢁꢃ, R1ꢁꢂ

Resistor

ꢁ02

33 Ω, 1/1ꢃ W, 5%

tol

Panasonic

ERJ-2GEJ330X

3ꢂ

3ꢀ

39

ꢁ0

ꢁ1

ꢁ2

ꢁ

3

1

2

R1ꢃ1, R1ꢃ2, R1ꢃ3,

R1ꢃꢁ

R202, R203, R20ꢁ

Resistor

ꢁ02

ꢁ99 Ω, 1/1ꢃ W,

1% tol

100 kΩ, 1/1ꢃ W,

1% tol

ꢁ.02 kΩ, 1/1ꢃ W,

1% tol

ꢁ9.9 Ω, 1/1ꢃ W,

0.5% tol

ꢁ.99 kΩ, 1/1ꢃ W,

5% tol

10 kΩ, Cermet

trimmer

Panasonic

Susumu

ERJ-2RKFꢁ990X

ERJ-2RKF1003X

ERJ-2RKFꢁ021X

RR0510R-ꢁ9R9-D

ERJ-2RKFꢁ991X

CT-9ꢁW-103

Resistor

ꢁ02

R222

Resistor

ꢁ02

R213

Resistor

ꢁ02

R229

Resistor

ꢁ02

Panasonic

R230, R319

Potentiometer

3-lead

BC

Components

potentiometer,

1ꢀ turn top adjust,

10%, 1/2 W

ꢁ3

ꢁꢁ

ꢁ5

1

ꢀ

R22ꢀ

R320

Resistor

ꢁ02

ꢁꢂ0 kΩ, 1/1ꢃ W,

5% tol

39 kΩ, 1/1ꢃ W,

5% tol

1ꢀꢂ Ω, 1/1ꢃ W,

1% tol

Yageo America 9C0ꢁ021Aꢁꢂ03JLHF3

Susumu

RR0510P-393-D

ERJ-2RKF1ꢀꢂ0X

R30ꢂ, R30ꢀ, R309,

R310, Rꢁ0ꢂ, Rꢁ0ꢀ,

Rꢁ09, Rꢁ10

Panasonic

ꢁꢃ

ꢁꢂ

ꢁꢀ

ꢁ

R305, R30ꢃ, Rꢁ05,

Rꢁ0ꢃ

R31ꢃ, R31ꢂ, Rꢁ15,

Rꢁ1ꢃ

R2ꢁ5, R2ꢁꢂ, R2ꢁ9,

R251, R253, R255,

R25ꢂ, R259, R2ꢃ1,

R2ꢃ3, R2ꢃ5

Resistor

ꢁ02

201

3ꢂꢁ Ω, 1/1ꢃ W,

1% tol

2ꢂꢁ Ω, 1/1ꢃ W,

1% tol

Panasonic

ERJ-2RKF3ꢂꢁ0X

ERJ-2RKF2ꢂꢁ0X

ERJ-1GE0R00C

ꢁ

11

0 Ω, 1/20 W, 5% tol

ꢁ9

50

51

52

53

5ꢁ

55

ꢁ

1

2

1

5

Rꢁ1ꢀ

Resistor

Switch

ꢁ02

ꢁ.ꢂ5 kΩ, 1/1ꢃ W,

1% tol

2ꢃ1 Ω, 1/1ꢃ W,

1% tol

2ꢃ1 Ω, 1/1ꢃ W,

1% tol

2ꢁ3 Ω, 1/1ꢃ W,

1% tol

100 Ω, 1/1ꢃ W,

1% tol

LIGHT TOUCH,

100GE, 5 mm

ADT1-1WT, 1:1

impedance ratio

transformer

Panasonic

Mini-Circuits

ERJ-2RKFꢁꢂ51X

ERJ-2RKF2ꢃ10X

ERJ-3EKF2ꢃ10V

ERJ-2RKF2ꢁ30X

ERJ-2RKF1000X

EVQ-PLDA15

Rꢁ19

ꢁ02

R501

ꢃ03

R2ꢁ0, R2ꢁ1

R2ꢁ2, R2ꢁ3

Sꢁ01

ꢁ02

SMD

CD5ꢁ2

T101, T102, T103, T10ꢁ, Transformer

T201

ADT1-1WT

5ꢃ

2

U501, U503

IC

SOT-223

ADP33339AKC-1.ꢀ, ADI

1.5 A, 1.ꢀ V LDO

regulator

ADP33339AKC-1.ꢀ

Rev. 0 | Page ꢁ9 of 52

AD9228

Qnty.

per

Item

Board REFDES

Device

Pkg.

Value

Mfg.

Mfg. Part Number

5ꢂ

2

U301, Uꢁ01

IC

LFCSP,

CP-32

ADꢀ332ACP,

ultralow noise

precision dual

VGA

ADI

ADꢀ332ACP

5ꢀ

59

ꢃ0

1

U50ꢁ

U502

U201

IC

SOT-223

LFCSP,

ADP33339AKC-5

ADP33339AKC-3.3 ADI

AD922ꢀ-ꢃ5, quad,

12-bit, ꢃ5 MSPS

serial LVDS 1.ꢀ V

ADC

ADI

ADP33339AKC-5

ADP33339AKC-3.3

AD922ꢀBCPZ-ꢃ5

ADI

CP-ꢁꢀ-1

ꢃ1

1

U203

IC

SOT-23

ADR510AR, 1.0 V,

precision low

ADI

ADR510AR

noise shunt

voltage reference

ꢃ2

ꢃ3

ꢃꢁ

ꢃ5

1

U202

Uꢁ03

Uꢁ0ꢁ

Uꢁ02

IC

LFCSP

CP-32-2

SCꢂ0,

MAA0ꢃA

SCꢂ0,

MAA0ꢃA

ꢀ-SOIC

AD9515

ADI

AD9515BCPZ

NCꢂWZ0ꢂPꢃX

NCꢂWZ1ꢃPꢃX

PIC12Fꢃ29-I/SN

NCꢂWZ0ꢂ

NCꢂWZ1ꢃ

Fairchild

Microchip

Flash prog

mem 1kx1ꢁ,

RAM size ꢃꢁ × ꢀ,

20 MHz speed,

PIC12F controller

series

Rev. 0 | Page 50 of 52

AD9228

OUTLINE DIMENSIONS

0.30

0.23

0.18

7.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

37

36

48

1

PIN 1

INDICATOR

EXPOSED

5.25

5.10 SQ

4.95

TOP

VIEW

6.75

BSC SQ

PAD

(BOTTOM VIEW)

0.50

0.40

0.30

25

24

12

13

0.25 MIN

5.50

REF

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.50 BSC

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

Figure 81. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

7 mm × 7 mm Body, Very Thin Quad

(CP-48-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

−ꢁ0°C to +ꢀ5°C

Package Description

ꢁꢀ-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

ꢁꢀ-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel

ꢁꢀ-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

ꢁꢀ-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel

Evaluation Board

Package Option

CP-ꢁꢀ-1

AD922ꢀBCPZ-ꢁ0¹

AD922ꢀBCPZRL-ꢁ0¹

AD922ꢀBCPZ-ꢃ5¹

AD922ꢀBCPZRL-ꢃ5¹

AD922ꢀ-ꢃ5EB

¹Z = Pb-free part.

Rev. 0 | Page 51 of 52

AD9228

NOTES

registered trademarks are the property of their respective owners.

D05727–0–4/06(0)

Rev. 0 | Page 52 of 52


型号：	AD9228BCPZRL-40
厂家：	ADI
描述：	Quad, 12-bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter 四通道，12位，六十五分之四十○ MSPS串行LVDS 1.8 VA / D转换器转换器
文件：	总52页 (文件大小：1699K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9228BCPZRL-40 [ADI]

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