AD9235BRU-40 [ADI]
12-Bit, 20/40/65 MSPS 3 V A/D Converter; 12位20/40/65 MSPS 3 V A / D转换器
| 型号： | AD9235BRU-40 |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 20/40/65 MSPS 3 V A/D Converter |
| 文件： | 总32页 (文件大小：1129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 20/40/65 MSPS
3 V A/D Converter
a
AD9235
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
DRVDD
Single 3 V Supply Operation (2.7 V to 3.6 V)
SNR = 70 dBc to Nyquist at 65 MSPS
SFDR = 85 dBc to Nyquist at 65 MSPS
Low Power: 300 mW at 65 MSPS
Differential Input with 500 MHz Bandwidth
On-Chip Reference and SHA
VIN+
VIN–
8-STAGE
SHA
MDAC1
A/D
1 1/2-BIT PIPELINE
3
4
16
REFT
REFB
A/D
DNL = ꢀ0.4 LSB
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
CORRECTION LOGIC
12
OTR
OUTPUT BUFFERS
D11
D0
APPLICATIONS
Ultrasound Equipment
AD9235
VREF
IF Sampling in Communications Receivers:
IS-95, CDMA-One, IMT-2000
Battery-Powered Instruments
Hand-Held Scopemeters
CLOCK
DUTY CYCLE
STABLIZER
MODE
SELECT
SENSE
REF
SELECT
0.5V
Low Cost Digital Oscilloscopes
CLK
PDWN
DGND
AGND
MODE
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9235 is a family of monolithic, single 3 V supply, 12-bit,
20/40/65 MSPS analog-to-digital converters. This family
features a high performance sample-and-hold amplifier (SHA)
and voltage reference. The AD9235 uses a multistage differential
pipelined architecture with output error correction logic to provide
12-bit accuracy at 20/40/65 MSPS data rates and guarantee
no missing codes over the full operating temperature range.
1. The AD9235 operates from a single 3 V power supply and
features a separate digital output driver supply to accommodate
2.5 V and 3.3 V logic families.
2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW.
3. The patented SHA input maintains excellent performance
for input frequencies up to 100 MHz and can be configured
for single-ended or differential operation.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
analog-to-digital converters, the AD9235 is suitable for applica-
tions in communications, imaging, and medical ultrasound.
4. The AD9235 pinout is similar to the AD9214-65, a 10-bit,
65 MSPS ADC. This allows a simplified upgrade path from
10 bits to 12 bits for 65 MSPS systems.
5. The clock DCS maintains overall ADC performance over a
wide range of clock pulsewidths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
A single-ended clock input is used to control all internal conversion
cycles. A duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance. The digital output data is presented
in straight binary or twos complement formats. An out-of-range
(OTR) signal indicates an overflow condition that can be used
with the most significant bit to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9235 is available
in a 28-lead thin shrink small outline package (TSSOP) and a
32-lead chip scale package (LFCSP) and is specified over the
industrial temperature range (–40°C to +85°C).
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD9235–SPECIFICATIONS
(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, 2 V p-p Differential Input,
DC SPECIFICATIONS 1.0 V internal reference, TMIN to TMAX, unless otherwise noted.)
Test
AD9235BRU-20
Max
AD9235BRU-40
AD9235BRU/BCP-65
Parameter
Temp Level Min Typ
Min Typ
Max
Min Typ
Max
Unit
RESOLUTION
Full
VI
12
12
12
Bits
ACCURACY
No Missing Codes Guaranteed
Offset Error
Full
Full
Full
Full
25°C
Full
25°C
VI
VI
VI
IV
I
12
12
12
Bits
0.30
0.30
0.35
0.35
0.45
0.40
1.20
2.40
0.65
0.50
1.20
2.50
0.75
0.50
1.20
2.60
0.80
% FSR
% FSR
LSB
LSB
LSB
Gain Error1
0.50
0.35
0.35
0.50
0.40
0.50
0.40
0.35
0.70
0.45
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
IV
I
0.80
0.90
1.30
LSB
TEMPERATURE DRIFT
Offset Error
Full
Full
V
V
2
12
2
12
3
12
ppm/°C
ppm/°C
Gain Error1
INTERNAL VOLTAGE
REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
Full
Full
Full
Full
VI
V
V
5
35
5
35
5
35
mV
mV
mV
mV
0.8
2.5
0.1
0.8
2.5
0.1
0.8
2.5
0.1
V
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
25°C
25°C
V
V
0.54
0.27
0.54
0.27
0.54
0.27
LSB rms
LSB rms
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance3
Full
Full
Full
IV
IV
V
1
2
7
1
2
7
1
2
7
V p-p
V p-p
pF
REFERENCE INPUT
RESISTANCE
Full
V
7
7
7
kΩ
POWER SUPPLIES
Supply Voltages
AVDD
Full
Full
IV
IV
2.7 3.0
2.25 3.0
3.6
3.6
2.7 3.0
2.25 3.0
3.6
3.6
2.7 3.0
2.25 3.0
3.6
3.6
V
V
DRVDD
Supply Current
IAVDD2
Full
Full
Full
V
V
V
30
2
0.01
55
5
0.01
100
7
0.01
mA
mA
% FSR
IDRVDD2
PSRR
POWER CONSUMPTION
DC Input4
Full
Full
Full
V
VI
V
90
95
1.0
165
180
1.0
300
320
1.0
mW
mW
mW
Sine Wave Input2
Standby Power5
110
205
350
NOTES
1Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
2Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2 for the equivalent analog input structure.
4Measured with dc input at maximum clock rate.
5Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
Specifications subject to change without notice.
–2–
REV. B
AD9235
DIGITAL SPECIFICATIONS
Test
AD9235BRU-20
AD9235BRU-40
AD9235BRU/BCP-65
Parameter
Temp Level Min
Typ
Max Min
Typ
Max Min
Typ
Max Unit
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
2.0
2.0
2.0
V
V
µA
µA
pF
0.8
+10
+10
0.8
+10
+10
0.8
+10
+10
–10
–10
–10
–10
–10
–10
2
2
2
LOGIC OUTPUTS*
DRVDD = 3.3 V
High-Level Output Voltage
(IOH = 50 µA)
High-Level Output Voltage
(IOH = 0.5 mA)
Low-Level Output Voltage
(IOL = 1.6 mA)
Low-Level Output Voltage
(IOL = 50 µA)
DRVDD = 2.5 V
Full
Full
Full
Full
IV
IV
IV
IV
3.29
3.25
3.29
3.25
3.29
3.25
V
V
V
V
0.2
0.2
0.2
0.05
0.05
0.05
High-Level Output Voltage
(IOH = 50 µA)
Full
Full
Full
Full
IV
IV
IV
IV
2.49
2.45
2.49
2.45
2.49
2.45
V
V
V
V
High-Level Output Voltage
(IOH = 0.5 mA)
Low-Level Output Voltage
(IOL = 1.6 mA)
Low-Level Output Voltage
(IOL = 50 µA)
0.2
0.2
0.2
0.05
0.05
0.05
*Output voltage levels measured with 5 pF load on each output.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Test
AD9235BRU-20
AD9235BRU-40
AD9235BRU/BCP-65
Parameter
Temp Level Min
Typ
Max Min
Typ
Max Min
Typ
Max Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
Full
Full
Full
Full
Full
VI
V
V
V
V
20
40
65
MSPS
MSPS
ns
ns
ns
1
1
1
50.0
15.0
15.0
25.0
8.8
8.8
15.4
6.2
6.2
CLK Pulsewidth High1
CLK Pulsewidth Low1
DATA OUTPUT PARAMETERS
Output Delay2 (tPD
)
Full
Full
Full
Full
Full
V
V
V
V
V
3.5
7
1.0
0.5
3.0
3.5
7
1.0
0.5
3.0
3.5
7
1.0
0.5
3.0
ns
Cycles
ns
ps rms
ms
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty Jitter (tJ)
Wake-Up Time3
OUT-OF-RANGE RECOVERY
TIME
Full
V
1
1
2
Cycles
NOTES
1For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.
2Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
3Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Specifications subject to change without notice.
N+1
N
N+2
N+8
N–1
N+3
t
A
ANALOG
INPUT
N+7
N+4
N+6
N+5
CLK
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
tPD = 6.0ns MAX
2.0ns MIN
Figure 1. Timing Diagram
–3–
REV. B
AD9235–SPECIFICATIONS
(AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, 2 V p-p Differential Input, AIN = –0.5 dBFS,
1.0 V internal reference, TMIN to TMAX, unless otherwise noted.)
AC SPECIFICATIONS
Test
AD9235BRU-20
AD9235BRU-40
AD9235BRU/BCP-65
Parameter
Temp Level Min
Typ
Max Min
Typ
Max Min
Typ
Max Unit
SIGNAL-TO-NOISE RATIO
fINPUT = 2.4 MHz
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
70.8
70.4
70.6
70.6
70.5
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
f
INPUT = 9.7 MHz
70.0
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
69.9
70.3
70.4
68.7 69.7
70.1
68.7
68.5
70.5
68.3
SIGNAL-TO-NOISE RATIO
AND DISTORTION
fINPUT = 2.4 MHz
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
70.6
70.3
70.5
70.4
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
f
INPUT = 9.7 MHz
69.9
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
69.7
70.2
70.3
68.3 69.5
69.9
68.6
68.3
67.8
TOTAL HARMONIC
DISTORTION
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
–88.0
–86.0 –79.0
–87.4
–89.0
–87.5
dBc
dBc
dBc
dBc
dBc
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
–85.5 –79.0
–86.0
–81.8 –74.0 dBc
–82.0
–78.0
dBc
dBc
–84.0
–82.5
WORST HARMONIC
(Second or Third)
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
Full
Full
Full
IV
IV
IV
–90.0 –80.0
dBc
dBc
–90.0 –80.0
–83.5 –74.0 dBc
SPURIOUS FREE DYNAMIC
RANGE
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
92.0
88.5
91.0
92.0
92.0
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
80.0
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
80.0
89.0
90.0
74.0 83.0
85.0
84.0
85.0
80.5
Specifications subject to change without notice.
–4–
REV. B
AD9235
ABSOLUTE MAXIMUM RATINGS1
With
EXPLANATION OF TEST LEVELS
100% production tested.
I
Pin Name
Respect to Min Max
Unit
II 100% production tested at 25°C and sample tested at
specified temperatures.
ELECTRICAL
AVDD
DRVDD
AGND
AVDD
Digital Outputs
CLK, MODE
VIN+, VIN–
VREF
SENSE
REFB, REFT
PDWN
III Sample tested only.
AGND
DGND
DGND
DRVDD
DGND
AGND
AGND
AGND
AGND
AGND
AGND
–0.3 +3.9
–0.3 +3.9
–0.3 +0.3
–3.9 +3.9
–0.3 DRVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
V
V
V
V
V
V
V
V
V
V
V
IV Parameter is guaranteed by design and characterization testing.
V
Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range;
100% production tested at temperature extremes for military
devices.
ENVIRONMENTAL2
Operating Temperature
Junction Temperature
Lead Temperature (10 sec)
Storage Temperature
–40 +85
150
300
–65 +150
°C
°C
°C
°C
NOTES
1Absolute maximum ratings are limiting values to be applied individually and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2Typical thermal impedances (28-lead TSSOP), θJA = 67.7°C/W; (32-lead LFCSP),
θ
JA = 32.5°C/W, θJC = 32.71°C/W. These measurements were taken on a 4-layer
board in still air, in accordance with EIA/JESD51-1.
ORDERING GUIDE
Temperature Range Package Description
Model
Package Option
AD9235BRU-20
AD9235BRU-40
AD9235BRU-65
AD9235BCP-20*
AD9235BCP-40*
AD9235BCP-65*
AD9235-20PCB
AD9235-40PCB
AD9235-65PCB
AD9235BCP-20EB
AD9235BCP-40EB
AD9235BCP-65EB
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
28-Lead Thin Shrink Small Outline Package (TSSOP)
32-Lead Lead Frame Chip Scale Package (LFCSP) (Contact Factory) CP-32
32-Lead Lead Frame Chip Scale Package (LFCSP) (Contact Factory) CP-32
32-Lead Lead Frame Chip Scale Package (LFCSP)
TSSOP Evaluation Board
TSSOP Evaluation Board
RU-28
RU-28
RU-28
CP-32
TSSOP Evaluation Board
LFCSP Evaluation Board (Contact Factory)
LFCSP Evaluation Board (Contact Factory)
LFCSP Evaluation Board
*It is recommended that the exposed paddle be soldered to the ground plane. There is an increased reliability of the solder joints and maximum thermal capability of
the package is achieved with exposed paddle soldered to the customer board.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9235 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–5–
AD9235
PIN CONFIGURATION
28-Lead TSSOP
32-Lead LFCSP
OTR
MODE
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+
D11 (MSB)
D10
1
2
3
4
5
6
7
8
9
28
27
26
25
24
D9
D8
DNC 1
CLK 2
DNC 3
PDWN 4
DNC 5
DNC 6
24 VREF
23 SENSE
22 MODE
21 OTR
20 D11(MSB)
19 D10
PIN 1
INDICATOR
DRVDD
AD9235
TOP VIEW
(Not to Scale)
23 DGND
AD9235
22
D7
TOP VIEW
(Not to Scale)
21 D6
20 D5
(LSB)D0 7
D1 8
18 D9
17 D8
VIN– 10
D4
D3
D2
19
18
17
AGND
AVDD
11
12
CLK 13
14
16 D1
PDWN
15 D0 (LSB)
PIN FUNCTION DESCRIPTIONS
Description
Pin Number
Mnemonic
28-Lead
TSSOP
32-Lead
LFCSP
1
21
OTR
Out-of-Range Indicator.
2
3
4
5
22
23
24
25
MODE
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+
Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.
Reference Mode Selection.
Voltage Reference Input/Output.
Differential Reference (–).
Differential Reference (+).
Analog Power Supply.
6
26
7, 12
8, 11
9
27, 32
28, 31
29
Analog Ground.
Analog Input Pin (+).
10
30
VIN–
Analog Input Pin (–).
13
2
CLK
Clock Input Pin.
14
4
PDWN
Power-Down Function Selection (Active High).
15–22,
25–28
23
7-14,
17-20
15
D0 (LSB)–D11(MSB) Data Output Bits.
DGND
Digital Output Ground.
24
16
DRVDD
Digital Output Driver Supply. Must be decoupled to DGND with a minimum
0.1 µF capacitor. Recommended decoupling is 0.1 µF in parallel with 10 µF.
Do Not Connect.
1, 3, 5, 6
DNC
–6–
REV. B
AD9235
DEFINITIONS OF SPECIFICATIONS
Signal-to-Noise and Distortion (SINAD)*
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
The ratio of the rms signal amplitude (set 0.5 dB below full scale)
to the rms value of the sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
Effective Number of Bits (ENOB)
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
The effective number of bits for a device for sine wave inputs at
a given input frequency can be calculated directly from its mea-
sured SINAD using the following formula
Aperture Jitter (tJ)
The sample-to-sample variation in aperture delay.
N = SINAD − 1.76 6.02
(
)
Signal-to-Noise Ratio (SNR)*
Integral Nonlinearity (INL)
The ratio of the rms signal amplitude (set at 0.5 dB below
full scale) to the rms value of the sum of all other spectral
components below the Nyquist frequency, excluding the first six
harmonics and dc.
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs 1/2 LSB before the first code transi-
tion. Positive full scale is defined as a level 1 1/2 LSBs beyond
the last code transition. The deviation is measured from the
middle of each particular code to the true straight line.
Spurious Free Dynamic Range (SFDR)*
The difference in dB between the rms amplitude of the input signal
and the peak spurious signal.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096 codes
must be present over all operating ranges.
Two-Tone SFDR*
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Clock Pulsewidth and Duty Cycle
Offset Error
Pulsewidth high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated perfor-
mance. Pulsewidth low is the minimum time the clock pulse
should be left in the low state. At a given clock rate, these speci-
fications define an acceptable clock duty cycle.
The major carry transition should occur for an analog value 1/2 LSB
below VIN+ = VIN–. Offset error is defined as the deviation of
the actual transition from that point.
Gain Error
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur
at an analog value 1 1/2 LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay (tPD
)
Temperature Drift
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
The temperature drift for offset error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX
.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input after
a transition from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
Power Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at its maximum
limit.
Total Harmonic Distortion (THD)*
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
*AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
REV. B
–7–
AD9235
Equivalent Circuits
DRVDD
AVDD
D11–D0,
OTR
VIN+, VIN–
Figure 4. Equivalent Digital Output Circuit
Figure 2. Equivalent Analog Input Circuit
AVDD
AVDD
MODE
CLK,
PDWN
20k⍀
Figure 3. Equivalent MODE Input Circuit
Figure 5. Equivalent Digital Input Circuit
–8–
REV. B
AD9235
Typical Performance Characteristics
(AVDD = 3.0 V, DRVDD = 2.5 V, fSAMPLE = 65 MSPS with DCS Disabled, TA = 25ꢁC, 2 V Differential Input, AIN = –0.5 dBFS, VREF = 1.0 V,
unless otherwise noted.)
0
–20
100
95
90
85
80
75
70
65
60
55
50
SNR = 70.3dBc
SFDR (2V DIFF)
SINAD = 70.2dBc
ENOB = 11.4 BITS
THD = –86.3dBc
SFDR = 89.9dBc
–40
SNR (2V SE)
–60
–80
SNR (2V DIFF)
–100
SFDR (2V SE)
45
–120
0.0
6.5
13.0
19.5
26.0
32.5
40
50
55
SAMPLE RATE MSPS)
60
65
FREQUENCY (MHz)
(
TPC 1. Single Tone 8K FFT with fIN = 10 MHz
TPC 4. AD9235-65: Single Tone SNR/SFDR vs. fCLK with
fIN = Nyquist (32.5 MHz)
100
95
0
SNR = 69.4dBc
SINAD = 69.1dBc
ENOB = 11.2 BITS
–20
–40
THD = –81.0dBc
SFDR = 83.8dBc
90
85
SFDR (2V DIFF)
80
SNR (2V SE)
SNR (2V DIFF)
75
70
65
–60
–80
60
SFDR (2V SE)
–100
55
50
–120
20
25
30
35
40
65.0
71.5
78.0
84.5
91.0
SAMPLE RATE (MSPS)
FREQUENCY (MHz)
TPC 5. AD9235-40: Single Tone SNR/SFDR vs. fCLK with
fIN = Nyquist (20 MHz)
TPC 2. Single Tone 8K FFT with fIN = 70 MHz
0
100
SNR = 68.5dBc
SINAD = 66.5dBc
ENOB = 10.8 BITS
THD = –71.0dBc
SFDR = 71.2dBc
SFDR (2V DIFF)
95
–20
–40
90
85
SFDR (2V SE)
80
–60
75
70
65
60
55
50
SNR (2V SE)
–80
SNR (2V DIFF)
–100
–120
97.5
104.0
110.5
117.0
123.5
130.0
0
5
10
15
20
FREQUENCY (MHz)
SAMPLE RATE (MSPS)
TPC 6. AD9235-20: Single Tone SNR/SFDR vs. fCLK with
fIN = Nyquist (10 MHz)
TPC 3. Single Tone 8K FFT with fIN = 100 MHz
REV. B
–9–
AD9235
95
90
85
80
75
100
90
80
70
60
50
40
SFDR
SFDR
SINGLE-ENDED (dBFS)
DIFFERENTIAL (dBFS)
SFDR
SFDR
DIFFERENTIAL (dBc)
SNR
DIFFERENTIAL (dBFS)
SNR
SINGLE-ENDED (dBFS)
SFDR
SINGLE-ENDED (dBc)
SNR
25
SNR
SINGLE-ENDED (dBc)
70
65
SNR
DIFFERENTIAL (dBc)
0
50
75
100
125
–30
–25
–20
–15
–10
–5
20
Input Frequency (MHz)
A
(dBFS)
IN
TPC 10. AD9235-65: SNR/SFDR vs. fIN
TPC 7. AD9235-65: Single Tone SNR/SFDR vs. AIN with
fIN = Nyquist (32.5 MHz)
95
90
85
80
75
100
SFDR
DIFFERENTIAL (dBFS)
SFDR
90
SFDR
SFDR
SINGLE-ENDED
DIFFERENTIAL
SNR
DIFFERENTIAL
(dBFS)
(dBFS)
(dBc)
80
70
60
50
40
SNR
SINGLE-ENDED
(dBFS)
SFDR
SINGLE-ENDED
(dBc)
SNR
DIFFERENTIAL (dBc)
SNR
70
65
SNR
SINGLE-ENDED (dBc)
0
50
75
100
125
25
–30
–25
–20
–15
–10
–5
0
Input Frequency (MHz)
A
(dBFS)
IN
TPC 11. AD9235-40: SNR/SFDR vs. fIN
TPC 8. AD9235-40: Single Tone SNR/SFDR vs. AIN with
fIN = Nyquist (20 MHz)
95
90
85
80
75
100
SFDR DIFFERENTIAL (dBFS)
SFDR
SFDR
90
80
70
60
50
40
DIFFERENTIAL (dBc)
SFDR
SINGLE-ENDED (dBFS)
SFDR
SINGLE-ENDED
(dBc)
SNR
DIFFERENTIAL (dBFS)
SNR
SINGLE-ENDED (dBFS)
SNR
DIFFERENTIAL
(dBc)
SNR
70
65
SNR
SINGLE-ENDED (dBc)
0
50
75
100
125
25
–30
–25
–20
–15
(dBFS)
–10
–5
0
A
Input Frequency (MHz)
IN
TPC 12. AD9235-20: SNR/SFDR vs. fIN
TPC 9. AD9235-20: Single Tone SNR/SFDR vs. AIN with
fIN = Nyquist (10 MHz)
–10–
REV. B
AD9235
95
90
0
SNR = 64.6dBFS
SFDR = 81.6dBFS
2V SFDR
1V SFDR
–20
85
80
75
70
–40
–60
–80
2V SNR
1V SNR
–100
65
60
–120
–24
–21
–18
–15
(dBFS)
–12
–9
–6
32.5
39.0
45.5
52.0
58.5
65.0
A
IN
FREQUENCY (MHz)
TPC 13. Dual Tone 8K FFT with fIN1 = 45 MHz and
TPC 16. Dual Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz
and fIN2 = 46 MHz
f
IN2 = 46 MHz
95
0
–20
2V SFDR
SNR = 64.3dBFS
SFDR = 81.1dBFS
90
1V SFDR
85
80
75
–40
–60
–80
2V SNR
1V SNR
70
–100
65
60
–24
–120
65.0
–21
–18
–15
(dBFS)
–12
–9
–6
71.5
78.0
84.5
91.0
97.5
A
FREQUENCY (MHz)
IN
TPC 14. Dual Tone 8K FFT with fIN1 = 69 MHz and
fIN2 = 70 MHz
TPC 17. Dual Tone SNR/SFDR vs. AIN with fIN1 = 69 MHz
and fIN2 = 70 MHz
0
95
SNR = 62.5dBFS
SFDR = 75.6dBFS
2V SFDR
90
–20
–40
1V SFDR
85
80
75
–60
–80
2V SNR
1V SNR
70
–100
65
–120
60
–24
–21
–18
–15
–12
–9
–6
130.0
136.5
143.0
149.5
156.0
162.5
FREQUENCY (MHz)
A
(dBFS)
IN
TPC 18. Dual Tone SNR/SFDR vs. AIN with fIN1 = 144 MHz
and fIN2 = 145 MHz
TPC 15. Dual Tone 8K FFT with fIN1 = 144 MHz and
fIN2 = 145 MHz
REV. B
–11–
AD9235
20
15
12.2
11.7
11.2
10.7
10.2
9.7
75
AD9235-40:
2V SINAD
AD9235-20:
2V SINAD
72
69
66
63
60
AD9235-65: 2V SINAD
AD9235-40: 1V SINAD
10
5
AD9235-20: 1V SINAD
AD9235-65: 1V SINAD
0
–5
–10
–15
–20
0
10
20
30
40
50
60
–40
–20
0
20
40
60
80
SAMPLE RATE (MSPS)
TEMPERATURE (ꢁC)
TPC 19. SINAD vs. fCLK with fIN = Nyquist
TPC 22. A/D Gain vs. Temperature Using an
External Reference
1.0
90
SFDR: DCS ON
0.8
0.6
80
SFDR: DCS OFF
SINAD: DCS ON
0.4
70
60
50
40
30
0.2
0.0
SINAD: DCS OFF
–0.2
–0.4
–0.6
–0.8
–1.0
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
35
40
45
50
55
60
65
DUTY CYCLE (%)
TPC 20. SINAD/SFDR vs. Clock Duty Cycle
TPC 23. Typical INL
90
1.0
0.8
0.6
0.4
SFDR 2V DIFF
85
80
SFDR 1V DIFF
75
0.2
0.0
SINAD 2V DIFF
70
65
60
55
50
–0.2
–0.4
–0.6
–0.8
–1.0
SINAD 1V DIFF
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
SAMPLE RATE (MSPS)
TPC 21. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz
TPC 24. Typical DNL
–12–
REV. B
AD9235
APPLYING THE AD9235
H
THEORY OF OPERATION
The AD9235 architecture consists of a front-end sample and
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The pipelined ADC is divided into three sections, consisting
of a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit
flash. Each stage provides sufficient overlap to correct for flash
errors in the preceding stages. The quantized outputs from each
stage are combined into a final 12-bit result in the digital correction
logic. The pipelined architecture permits the first stage to operate
on a new input sample while the remaining stages operate on pre-
ceding samples. Sampling occurs on the rising edge of the clock.
T
T
T
5pF
5pF
VIN+
VIN–
C
PAR
C
PAR
T
H
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output and
the flash input for the next stage in the pipeline. One bit of redun-
dancy is used in each stage to facilitate digital correction of flash
errors. The last stage simply consists of a flash ADC.
Figure 6. Switched-Capacitor SHA Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as follows:
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output-
staging block aligns the data, carries out the error correction, and
passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
REFT = 1 2 AVDD +VREF
(
)
REFB = 1 2 AVDD −VREF
(
)
Span = 2 × REFT − REFB = 2 ×VREF
(
)
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the
VREF voltage.
ANALOG INPUT
The analog input to the AD9235 is a differential switched
capacitor SHA that has been designed for optimum performance
while processing a differential input signal. The SHA input can
support a wide common-mode range and maintain excellent
performance, as shown in Figure 7. An input common-mode
voltage of midsupply will minimize signal-dependant errors and
provide optimum performance.
–90
–85
–80
–75
–70
–65
–60
–55
–50
90
85
80
75
70
65
60
55
50
THD 2.5MHz 2V DIFF
THD 35MHz 2V DIFF
SNR 2.5MHz 2V DIFF
Referring to Figure 6, the clock signal alternatively switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half of
a clock cycle. A small resistor in series with each input can help
reduce the peak transient current required from the output stage
of the driving source. Also, a small shunt capacitor can be placed
across the inputs to provide dynamic charging currents. This
passive network will create a low-pass filter at the ADC’s input;
therefore, the precise values are dependant upon the application.
In IF undersampling applications, any shunt capacitors should
be removed. In combination with the driving source impedance,
they would limit the input bandwidth.
SNR 35MHz 2V DIFF
0.0
0.5
1.0
1.5
2.0
2.5
3.0
COMMON-MODE LEVEL (V)
Figure 7. AD9235-65: SNR, THD vs. Common-Mode Level
The internal voltage reference can be pin-strapped to fixed values
of 0.5 V or 1.0 V, or adjusted within the same range as discussed
in the Internal Reference Connection section. Maximum SNR
performance will be achieved with the AD9235 set to the largest
input span of 2 V p-p. The relative SNR degradation will be 3 dB
when changing from 2 V p-p mode to 1 V p-p mode.
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors will be reduced by
the common-mode rejection of the ADC.
REV. B
–13–
AD9235
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference volt-
age. The minimum and maximum common-mode input levels
are defined as follows:
The signal characteristics must be considered when selecting a
transformer. Most RF transformers will saturate at frequencies
below a few MHz, and excessive signal power can also cause core
saturation, which leads to distortion.
Single-Ended Input Configuration
VCMMIN =VREF /2
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there will be a
degradation in SFDR and in distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little effect
on SNR performance. Figure 10 details a typical single-ended
input configuration.
VCMMAX = (AVDD +VREF)/2
The minimum common-mode input level allows the AD9235 to
accommodate ground-referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source may be driven into VIN+ or VIN–.
In this configuration, one input will accept the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9235 will then accept an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance may
degrade significantly as compared to the differential case. However,
the effect will be less noticeable at lower input frequencies and
in the lower speed grade models (AD9235-40 and AD9235-20).
AVDD
1k⍀
22⍀
VIN+
0.33F
2Vp-p
49.9⍀
1k⍀
15pF
AD9235
1k⍀
1k⍀
22⍀
+
VIN–
AGND
10F
0.1F
15pF
Differential Input Configurations
Figure 10. Single-Ended Input Configuration
As previously detailed, optimum performance will be achieved
while driving the AD9235 in a differential input configuration.
For baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen Key filter
topology to provide band limiting of the input signal.
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be sensitive to
clock duty cycle. Commonly a 5% tolerance is required on the
clock duty cycle to maintain dynamic performance character-
istics. The AD9235 contains a clock duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of the
AD9235. As shown in TPC 20, noise and distortion perfor-
mance are nearly flat over a 30% range of duty cycle.
1Vp-p
49.9⍀
499⍀
AVDD
VIN+
22⍀
499⍀
523⍀
15pF
AD9235
AD8138
499⍀
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency will require approximately 100 clock cycles
to allow the DLL to acquire and lock to the new rate.
1k⍀
22⍀
VIN–
AGND
1k⍀
0.1F
15pF
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated with the following equation.
Figure 8. Differential Input Configuration Using
the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers will not be adequate to achieve
the true performance of the AD9235. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 9.
SNR Degradation = 20 × log10 1 2 × π × f
× tJ
[
]
INPUT
In the equation, the rms aperture jitter, tJ, represents the root-
sum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. Under-
sampling applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9235.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
AVDD
22⍀
VIN+
15pF
2V p-p
49.9⍀
AD9235
22⍀
VIN–
AGND
15pF
1k⍀
1k⍀
0.1F
Figure 9. Differential Transformer-Coupled Configuration
–14–
REV. B
AD9235
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 11, the power dissipated by the AD9235 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode, and then must be recharged when returning
to normal operation. As a result, the wake-up time is related to the
time spent in standby mode and shorter standby cycles will result
in proportionally shorter wake-up times. With the recommended
0.1 µF and 10 µF decoupling capacitors on REFT and REFB, it
takes approximately 1 sec to fully discharge the reference buffer
decoupling capacitors and 3 ms to restore full operation.
IDRVDD =VDRVDD × CLOAD × fCLK × N
where N is the number of output bits, 12 in the case of the
AD9235. This maximum current occurs when every output bit
switches on every clock cycle, i.e., a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current will
be established by the average number of output bits switching,
which will be determined by the encode rate and the characteris-
tics of the analog input signal.
DIGITAL OUTPUTS
The AD9235 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
325
300
AD9235-65
275
250
225
200
As detailed in Table II, the data format can be selected for
either offset binary or twos complement.
Timing
The AD9235 provides latched data outputs with a pipeline delay of
seven clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal. Refer to
Figure 1 for a detailed timing diagram.
175
AD9235-40
150
125
100
AD9235-20
The length of the output data lines and loads placed on them should
be minimized to reduce transients within the AD9235; these
transients can detract from the converter’s dynamic performance.
75
50
0.0
10
20
30
40
50
60
SAMPLE RATE (MSPS)
The lowest typical conversion rate of the AD9235 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
Figure 11. Total Power vs. Sample Rate with fIN = 10 MHz
VOLTAGE REFERENCE
For the AD9235-20 speed grade, the digital power consumption
can represent as much as 10% of the total dissipation. Digital
power consumption can be minimized by reducing the capacitive
load presented to the output drivers. The data in Figure 11 was
taken with a 5 pF load on each output driver.
A stable and accurate 0.5 V voltage reference is built into the
AD9235. The input range can be adjusted by varying the reference
voltage applied to the AD9235, using either the internal reference
or an externally applied reference voltage. The input span of the
ADC tracks reference voltage changes linearly.
The analog circuitry is optimally biased so that each speed grade
provides excellent performance while affording reduced power
consumption. Each speed grade dissipates a baseline power at
low sample rates that increases linearly with the clock frequency.
If the ADC is being driven differentially through a transformer, the
reference voltage can be used to bias the center tap (common-
mode voltage).
Internal Reference Connection
By asserting the PDWN pin high, the AD9235 is placed in
standby mode. In this state, the ADC will typically dissipate 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reassert-
ing the PDWN pin low returns the AD9235 into its normal
operational mode.
A comparator within the AD9235 detects the potential at the
SENSE pin and configures the reference into one of four possible
states, which are summarized in Table I. If SENSE is grounded,
Table I. Reference Configuration Summary
Selected
Mode
SENSE
Voltage
Internal Switch
Position
Resulting
VREF (V)
Resulting Differential
Span (V p-p)
External Reference
AVDD
VREF
0.2 V to VREF
AGND to 0.2 V
N/A
SENSE
SENSE
Internal Divider
N/A
0.5
2 × External Reference
Internal Fixed Reference
Programmable Reference
Internal Fixed Reference
1.0
0.5 × (1 + R2/R1)
1.0
2 × VREF (See Figure 13)
2.0
REV. B
–15–
AD9235
reference amplifier switch is connected to the internal resistor
divider (see Figure 12), setting VREF to 1 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a 0.5 V
reference output. If a resistor divider is connected as shown in
Figure 13, the switch will again be set to the SENSE pin. This
will put the reference amplifier in a noninverting mode with the
VREF output defined as follows.
External Reference Operation
The use of an external reference may be necessary to enhance the
gain accuracy of the ADC or improve thermal drift characteristics.
When multiple ADCs track one another, a single reference
(internal or external) may be necessary to reduce gain matching
errors to an acceptable level. A high precision external reference
may also be selected to provide lower gain and offset temperature
drift. Figure 14 shows the typical drift characteristics of the
internal reference in both 1 V and 0.5 V modes.
VREF = 0.5 × 1+ R2 R1
(
)
1.2
VIN+
VIN–
1.0
REFT
0.1ꢂF
VREF= 1.0V
0.8
ADC
CORE
10ꢂF
VREF= 0.5V
0.1ꢂF
REFB
0.6
0.4
0.2
0.0
0.1ꢂF
VREF
0.5V
10ꢂF
0.1ꢂF
SELECT
LOGIC
SENSE
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (ꢁC)
AD9235
Figure 14. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference
will be disabled, allowing the use of an external reference. An
internal reference buffer will load the external reference with an
equivalent 7 kΩ load. The internal buffer will still generate the
positive and negative full-scale references, REFT and REFB, for
the ADC core. The input span will always be twice the value of
the reference voltage; therefore, the external reference must be
limited to a maximum of 1 V.
Figure 12. Internal Reference Configuration
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
VIN+
If the internal reference of the AD9235 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 15 depicts
how the internal reference voltage is affected by loading.
VIN–
REFT
0.1ꢂF
ADC
CORE
10ꢂF
0.1ꢂF
REFB
0.05
0.00
0.1ꢂF
VREF
0.5V
10ꢂF
0.1ꢂF
–0.05
SELECT
LOGIC
0.5V ERROR (%)
R2
SENSE
R1
–0.10
1V ERROR (%)
–0.15
AD9235
–0.20
Figure 13. Programmable Reference Configuration
–0.25
0.0
0.5
1.0
1.5
2.0
2.5
3.0
LOAD (mA)
Figure 15. VREF Accuracy vs. Load
–16–
REV. B
AD9235
OPERATIONAL MODE SELECTION
The AUXCLK input should be selected in applications requiring
the lowest jitter and SNR performance (i.e., IF undersampling
characterization). It allows the user to apply a clock input signal that
is 4× the target sample rate of the AD9235. A low-jitter, differential
divide-by-4 counter, the MC100LVEL33D, provides a 1× clock
output that is subsequently returned back to the CLK input via
JP9. For example, a 260 MHz signal (sinusoid) will be divided
down to a 65 MHz signal for clocking the ADC. Note that R1 must
be removed with the AUXCLK interface. Lower jitter is often
achieved with this interface since many RF signal generators
display improved phase noise at higher output frequencies and the
slew rate of the sinusoidal output signal is 4× that of a 1× signal
of equal amplitude.
As discussed earlier, the AD9235 can output data in either
offset binary or twos complement format. There is also a provision
for enabling or disabling the clock duty cycle stabilizer (DCS).
The MODE pin is a multilevel input that controls the data format
and DCS state. The input threshold values and corresponding
mode selections are outlined below.
Table II. Mode Selection
MODE
Voltage
Data
Format
Duty Cycle
Stabilizer
AVDD
Twos Complement
Twos Complement
Offset Binary
Disabled
Enabled
Enabled
Disabled
2/3 AVDD
1/3 AVDD
AGND (Default)
Complete schematics and layout plots follow and demonstrate the
proper routing and grounding techniques that should be applied
at the system level.
Offset Binary
The MODE pin is internally pulled down to AGND by a
20 kΩ resistor.
LFCSP EVALUATION BOARD
The typical bench setup used to evaluate the ac performance
of the AD9235 is similar to the TSSOP Evaluation Board
connections (refer to the schematics for connection details).
The AD9235 can be driven single-ended or differentially
through a transformer. Separate power pins are provided to
isolate the DUT from the support circuitry. Each input con-
figuration can be selected by proper connection of various
jumpers (refer to the schematics).
TSSOP EVALUATION BOARD
The AD9235 evaluation board provides all of the support
circuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially,
through an AD8138 driver or a transformer, or single-ended.
Separate power pins are provided to isolate the DUT from the
support circuitry. Each input configuration can be selected by
proper connection of various jumpers (refer to the schematics).
Figure 16 shows the typical bench characterization setup used to
evaluate the ac performance of the AD9235. It is critical that
signal sources with very low phase noise (<1 ps rms jitter) be used
to realize the ultimate performance of the converter. Proper
filtering of the input signal, to remove harmonics and lower the
integrated noise at the input, is also necessary to achieve the
specified noise performance.
An alternative differential analog input path using an AD8351
op amp is included in the layout but is not populated in pro-
duction. Designers interested in evaluating the op amp with
the ADC should remove C15, R12, and R3 and populate the
op amp circuit. The passive network between the AD8351
outputs and the AD9235 allows the user to optimize the fre-
quency response of the op amp for the application.
3V
3V
3V
3V
–
+
–
+
–
+
–
+
AVDD GND DUT GND DUT
AVDD DRVDD
DVDD
J1
S4
XFMR
INPUT
HP8644, 2V p-p
SIGNAL SYNTHESIZER
BAND-PASS
FILTER
REFIN
DATA
CAPTURE
AND
AD9235
TSSOP EVALUATION BOARD
PROCESSING
CLOCK
DIVIDER
10MHz
REFOUT
S1
HP8644, 2V p-p
CLOCK SYNTHESIZER
CLOCK
Figure 16. TSSOP Evaluation Board Connections
REV. B
–17–
AD9235
Figure 17. TSSOP Evaluation Board Schematic, DUT
–18–
REV. B
AD9235
O R S
H E A D E R R I G H T A N G L E M A L E N O E J E C T
1N5712
1 N 5 7 1 2
Figure 18. TSSOP Evaluation Board Schematic, Clock Inputs and Output Buffering
REV. B
–19–
AD9235
Figure 19. TSSOP Evaluation Board Schematic, Analog Inputs
–20–
REV. B
AD9235
DACLK
DVDD
1
2
28
C30
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
MSB–DB11
DB10
CLOCK
DVDD
C31
27
26
25
24
23
22
21
20
19
18
17
16
15
0.1ꢂF
0.01ꢂF
3
C29
DB19
DCOM
NC3
C46
4
DB8
AD9762
0.1ꢂF
0.01ꢂF
5
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC1
NC2
AVDD
TP18
WHT
S6
6
COMP2
IOUTA
IOUTB
ACOM
COMP1
FSADJ
REFIO
REFLO
SLEEP
7
U4
8
9
49.9ꢃ
R29
0.1ꢂF
C56
10
11
12
13
14
C55
22pF
C51
R30
2kꢃ
0.1ꢂF
49.9ꢃ
R28
C49
0.1ꢂF
C54
22pF
Figure 20. TSSOP Evaluation Board Schematic, Optional D/A Converter
Figure 21. TSSOP Evaluation Board Layout, Primary Side
REV. B
–21–
AD9235
Figure 22. TSSOP Evaluation Board Layout, Secondary Side
Figure 23. TSSOP Evaluation Board Layout, Ground Plane
–22–
REV. B
AD9235
_
Figure 24. TSSOP Evaluation Board Power Plane
Figure 25. TSSOP Evaluation Board Layout, Primary Silkscreen
–23–
REV. B
AD9235
Figure 26. TSSOP Evaluation Board Layout, Secondary Silkscreen
–24–
REV. B
AD9235
P 2
5 . 0 V
2 . 5 V
P M V A
V D L
G N D
2 . 5 V
3 . 0 V
V D D R
G N D
D D A V
D 8
D 9
D 1
1 7
1 8
8
D 0 7
D 1 0
D N C
6
1 9
2 0
2 1
2 2
2 3
D N C
D 1 1
O T
5
R
W N P D
4
D N C
M O D E
S E N S E
V R E F
3
C L K
2
D N C
1
2 4
Figure 27. LFCSP Evaluation Board Schematic, Analog Inputs and DUT
–25–
REV. B
AD9235
Figure 28. LFCSP Evaluation Board Schematic, Digital Path
–26–
REV. B
AD9235
Figure 29. LFCSP Evaluation Board Schematic, Clock Input
–27–
REV. B
AD9235
Figure 30. LFCSP Evaluation Board Layout, Primary Side
Figure 32. LFCSP Evaluation Board Layout, Ground Plane
Figure 31. LFCSP Evaluation Board Layout, Secondary Side
Figure 33. LFCSP Evaluation Board Layout, Power Plane
–28–
REV. B
AD9235
Figure 34. LFCSP Evaluation Board Layout,
Primary Silkscreen
Figure 35. LFCSP Evaluation Board Layout,
Secondary Silkscreen
REV. B
–29–
AD9235
Table III. LFCSP Evaluation Board Bill of Materials
Item
Qty.
Omit1
Reference Designator
Device
Package
Value
Recommended
Vendor/Part Number
Supplied
by ADI
1
18
C1, C5, C7, C8, C9, C11,
C12, C13, C15, C16, C31,
C33, C34, C36, C37, C41,
C43, C47
Chip Capacitor
0603
0.1 µF
8
2
C6, C18, C27, C17, C28,
C35, C45, C44
2
3
8
8
C2, C3, C4, C10, C20,
C22, C25, C29
C46, C24
Tantalum Capacitor
Chip Capacitor
TAJD
0603
10 µF
C14, C30, C32, C38, C39,
C40, C48, C49
0.001 µF
4
5
6
3
1
9
C19, C21, C23
C26
Chip Capacitor
Chip Capacitor
Header
0603
10 pF
10 pF
0603
E31, E35, E43, E44, E50,
E51, E52, E53
EHOLE
Jumper Blocks
2
1
E1, E45
7
8
2
J1, J2
L1
SMA Connector/50 Ω
SMA
0603
Inductor
10 nH
Coilcraft/0603CS-
10NXGBU
9
1
1
5
P2
Terminal Block
TB6
Wieland/25.602.2653.0,
z5-530-0625-0
10
11
P12
Header Dual 20-Pin
RT Angle
HEADER40
0603
Digi-Key S2131-20-ND
R3, R12, R23, R28, RX
R37, R22, R42, R16, R17,
R27
Chip Resistor
0 Ω
6
12
13
2
R4, R15
Chip Resistor
Chip Resistor
0603
0603
33 Ω
1 kΩ
14
R5, R6, R7, R8, R13, R20,
R21, R24, R25, R26, R30,
R31, R32, R36
14
15
2
1
R10, R11
Chip Resistor
Chip Resistor
0603
0603
36 Ω
50 Ω
R29
R19
1
16
2
RP1, RP2
Resistor Pack
ADT1-1WT
R_742
220 Ω
Digi-Key
CTS/742C163220JTR
17
18
1
1
T1
U1
AWT1-1T
TSSOP-48
Mini-Circuits
74LVTH162374
CMOS Register
19
20
21
22
23
24
25
1
1
1
U4
AD9235BCP ADC (DUT) CSP-32
Analog Devices, Inc.
Fairchild
X
U5
74VCX86M
SOIC-14
PCB
PCB
AD92XXBCP/PCB
AD8351 Op Amp
MACOM Transformer
Chip Resistor
Analog Devices, Inc.
Analog Devices, Inc.
MACOM/ETC1-1-13
X
X
1
1
5
3
U3
MSOP-8
ETC1-1-13
0603
T2
1-1 TX
SELECT
25 Ω
R9, R1, R2, R38, R39
R18, R14, R35
Chip Resistor
0603
–30–
REV. B
AD9235
Table III. LFCSP Evaluation Board Bill of Materials (continued)
Item
Qty.
Omit1
Reference Designator
Device
Package
Value
Recommended
Vendor/Part Number
Supplied
by ADI
26
2
R40, R41
R34
Chip Resistor
Chip Resistor
Chip Resistor
0603
10 kΩ
1.2 kΩ
100 Ω
27
1
28
1
R33
Total
82
34
1These items are included in the PCB design but are omitted at assembly.
OUTLINE DIMENSIONS
28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
9.80
9.70
9.60
28
15
14
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8ꢁ
0ꢁ
0.30
0.19
0.20
0.09
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AE
32-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-32)
Dimensions shown in millimeters
5.00
BSC SQ
0.60 MAX
PIN 1
0.60 MAX
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
3.25
3.10
2.95
4.75
BSC SQ
TOP
VIEW
BOTTOM
VIEW
SQ
0.50
0.40
0.30
17
16
8
9
3.50
REF
0.80 MAX
0.65 NOM
12ꢁ MAX
0.05 MAX
0.02 NOM
1.00
0.90
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
REV. B
–31–
AD9235
Revision History
Location
Page
5/03—Data Sheet changed from REV. A to REV. B.
Added CP-32 Package (LFCSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UNIVERSAL
Changes to Several Pin Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UNIVERSAL
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to PRODUCT HIGHLIGHTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Replaced Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
New DEFINITIONS OF SPECIFICATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to TPCs 1–12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes to THEORY OF OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Changes to ANALOG INPUT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Changes to Single-ended Input Configuration section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Replaced Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Changes to CLOCK INPUT CONSIDERATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to POWER DISSIPATION AND STANDBY MODE section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to DIGITAL OUTPUTS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Timing section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Changes to Figures 16–26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Added LFCSP Evaluation Board section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Inserted Figures 27–35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Added Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8/02—Data Sheet changed from REV. 0 to REV. A.
Updated RU-28 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
–32–
REV. B
相关型号：
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