AD9244BSTRL-65 [ADI]
14-Bit, 40/65 MSPS Monolithic A/D Converter; 14位，六十五分之四十MSPS单片A / D转换器
| 型号： | AD9244BSTRL-65 |
| 厂家： | 
ADI |
| 描述： | 14-Bit, 40/65 MSPS Monolithic A/D Converter |
| 文件： | 总36页 (文件大小：1762K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
14-Bit, 40/65 MSPS A/D Converter
AD9244
FEATURES
FUNCTIONAL BLOCK DIAGRAM
14-Bit, 40/65 MSPS ADC
Low Power:
REFT REFB
DRVDD
AVDD
550 mW at 65 MSPS
300 mW at 40 MSPS
AD9244
On-Chip Reference and Sample-and-Hold
750 MHz Analog Input Bandwidth
SNR > 73 dBc to Nyquist @ 65 MSPS
SFDR > 86 dBc to Nyquist @ 65 MSPS
Differential Nonlinearity Error = ؎0.7 LSB
Guaranteed No Missing Codes over Full Temperature Range
1 V to 2 V p-p Differential Full-Scale Analog Input Range
Single 5 V Analog Supply, 3.3 V/5 V Driver Supply
Out-of-Range Indicator
TEN
STAGE
PIPELINE
ADC
VIN+
VIN–
DFS
OTR
SHA
14
CLK+
CLK–
OUTPUT
REGISTER
TIMING
DCS
D13–D0
OEB
Straight Binary or Twos Complement Output Data
Clock Duty Cycle Stabilizer
Output Enable Function
14
REFERENCE
48-Lead LQFP Package
APPLICATIONS
AGND CML VR
VREF SENSE
REF
GND
DGND
Communications Subsystems (Microcell, Picocell)
Medical and High End Imaging Equipment
Ultrasound Equipment
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9244 is a monolithic, single 5 V supply, 14-bit,
40 MSPS/65 MSPS analog-to-digital converter with an on-chip,
high performance sample-and-hold amplifier and voltage reference.
The AD9244 uses a multistage differential pipelined architecture
with output error correction logic to provide 14-bit accuracy at
40 MSPS/65 MSPS data rates and guarantees no missing codes
over the full operating temperature range.
Low Power—The AD9244, at 550 mW, consumes a frac-
tion of the power of presently available ADCs in existing
high speed solutions.
IF Sampling—The AD9244 delivers outstanding perfor-
mance at input frequencies beyond the first Nyquist zone.
Sampling at 65 MSPS with an input frequency of 100 MHz,
the AD9244 delivers 71 dB SNR and 86 dB SFDR.
The AD9244 has an on-board, programmable voltage reference.
An external reference can also be used to suit the dc accuracy
and temperature drift requirements of the application.
Pin Compatibility—The AD9244 offers a seamless
migration from the 12-bit, 65 MSPS AD9226.
On-Board Sample-and-Hold (SHA)—The versatile SHA
input can be configured for either single-ended or differ-
ential inputs.
A differential or single-ended clock input is used to control all
internal conversion cycles. The digital output data can be pre-
sented in straight binary or in twos complement format. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow.
Out-of-Range (OTR)—The OTR output bit indicates
when the input signal is beyond the AD9244’s input range.
Single Supply—The AD9244 uses a single 5 V power
supply, simplifying system power supply design. It also
features a separate digital output driver supply to accom-
modate 3.3 V and 5 V logic families.
Fabricated on an advanced CMOS process, the AD9244 is
available in a 48-lead low profile quad flatpack package (LQFP)
and is specified for operation over the industrial temperature
range (–40°C to +85°C).
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD9244–SPECIFICATIONS
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), Differential Clock Inputs, VREF = 2 V,
DC SPECIFICATIONS External Reference, Differential Analog Inputs, unless otherwise noted.)
Test
Level Min
AD9244BST-65
AD9244BST-40
Parameter
Temp
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
Full
VI
14
14
Bits
DC ACCURACY
No Missing Codes
Offset Error
Full
Full
Full
Full
25°C
Full
VI
VI
VI
VI
V
Guaranteed
Guaranteed
Bits
0.3
0.6
1.4
2.0
1.0
0.3
0.6
1.4
2.0
1.0
% FSR
% FSR
LSB
LSB
LSB
Gain Error1
Differential Nonlinearity (DNL)2
0.7
1.4
0.6
1.3
Integral Nonlinearity (INL)2
V
TEMPERATURE DRIFT
Offset Error
Full
Full
Full
V
V
V
2.0
2.3
25
2.0
2.3
25
ppm/°C
ppm/°C
ppm/°C
Gain Error (EXT VREF)1
Gain Error (INT VREF)3
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (2 VREF)
Load Regulation @ 1 mA
Output Voltage Error (1 VREF)
Load Regulation @ 0.5 mA
Input Resistance
Full
Full
Full
Full
Full
VI
V
IV
V
V
29
15
29
15
mV
mV
mV
mV
kΩ
0.5
0.5
0.25
5
0.25
5
INPUT REFERRED NOISE
VREF = 2 V
VREF = 1 V
25°C
25°C
V
V
0.8
1.5
0.8
1.5
LSB rms
LSB rms
ANALOG INPUT
Input Voltage Range (Differential)
VREF = 2 V
VREF = 1 V
Full
Full
Full
25°C
25°C
25°C
V
V
V
V
V
V
2
1
2
1
V p-p
V p-p
V
pF
µA
MHz
Common-Mode Voltage
0.5
4
0.5
4
Input Capacitance4
10
500
750
10
500
750
Input Bias Current5
Analog Bandwidth (Full Power)
POWER SUPPLIES
Supply Voltages
AVDD
Full
Full
IV
IV
4.75
2.7
5
5.25
5.25
4.75
2.7
5
5.25
5.25
V
V
DRVDD
Supply Current
IAVDD
IDRVDD
Full
Full
Full
V
V
V
109
12
0.05
64
8
0.05
mA
mA
% FSR
PSRR
POWER CONSUMPTION
DC Input6
Sine Wave Input
Full
Full
V
VI
550
590
300
345
mW
mW
640
370
NOTES
1Gain error is based on the ADC only (with a fixed 2.0 V external reference).
2Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3Includes internal voltage reference error.
4Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 2d for the equivalent analog input structure.
5Input bias current is due to the inputs looking like a resistor that is dependent on the clock rate.
6Measured with dc input at maximum clock rate.
Specifications subject to change without notice.
–2–
REV. A
AD9244
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), Differential Clock Inputs, VREF = 2 V,
External Reference, AIN = –0.5 dBFS, Differential Analog Inputs, unless otherwise noted.)
AC SPECIFICATIONS
Test
Level
AD9244BST-65
Typ
AD9244BST-40
Typ
Parameter
Temp
Min
Max
Min
Max
Unit
SNR
fIN = 2.4 MHz
Full
25°C
VI
I
IV
V
VI
I
IV
I
72.4
72.0
73.4
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
74.8
73.7
75.3
74.7
f
IN = 15.5 MHz (–1 dBFS) Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
fIN = 20 MHz
72.1
fIN = 32.5 MHz
70.8
69.9
73.0
f
IN = 70 MHz
IV
V
V
72.2
71.2
67.2
fIN = 100 MHz
fIN = 200 MHz
72.8
68.3
V
SINAD
fIN = 2.4 MHz
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
IV
I
IV
V
V
V
72.2
73.2
72
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
74.7
75.1
74.4
70.6
69.7
72.6
71.9
71
59.8
fIN = 100 MHz
fIN = 200 MHz
72.4
56.3
ENOB
fIN = 2.4 MHz
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
IV
I
IV
V
V
V
11.7
11.9
11.7
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
12.1
12.2
12.1
11.4
11.3
11.8
11.7
11.5
9.6
fIN = 100 MHz
fIN = 200 MHz
11.7
9.1
THD
fIN = 2.4 MHz
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
IV
I
IV
V
V
V
–78.4
–80.7
–80.4
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
–90.0
–89.7
–89.4
–79.2
–78.7
–84.6
–84.1
–83.0
–60.7
fIN = 100 MHz
fIN = 200 MHz
–83.2
–56.6
WORST 2 or 3
fIN = 2.4 MHz
fIN = 20 MHz
25°C
25°C
25°C
25°C
25°C
25°C
V
V
V
V
V
V
–94.5
–93.7
–92.8
dBc
dBc
dBc
dBc
dBc
dBc
f
IN = 32.5 MHz
–86.5
–86.1
–86.2
–60.7
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
–84.5
–56.6
REV. A
–3–
AD9244
AC SPECIFICATIONS (continued)
Test
AD9244BST-65
Typ
AD9244BST-40
Typ
Parameter
Temp
Level
Min
Max
Min
Max
Unit
SFDR
f
IN = 2.4 MHz
Full
25°C
VI
I
IV
V
IV
I
IV
I
IV
V
V
V
78.6
83
82.5
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
94.5
90
93.7
91.8
fIN = 15.5 MHz (–1 dBFS) Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
fIN = 20 MHz
IN = 32.5 MHz
81.4
f
80.0
79.5
86.4
fIN = 70 MHz
86.1
86.2
60.7
fIN = 100 MHz
fIN = 200 MHz
84.5
56.6
(AVDD = 5 V, DRVDD = 3 V, VREF = 2 V, External Reference, unless otherwise noted.)
DIGITAL SPECIFICATIONS
Test
AD9244BST-65
AD9244BST-40
Parameter
Temp
Level Min
Typ
Max
Min
Typ
Max Unit
DIGITAL INPUTS
Logic 1 Voltage (OEB, DRVDD = 3 V)
Logic 1 Voltage (OEB, DRVDD = 5 V)
Logic 0 Voltage (OEB)
Logic 1 Voltage (DFS, DCS)
Logic 0 Voltage (DFS, DCS)
Input Current
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
V
2
3.5
2
3.5
V
V
V
V
V
µA
pF
0.8
0.8
3.5
3.5
0.8
10
0.8
10
Input Capacitance
5
5
CLOCK INPUT PARAMETERS
Differential Input Voltage
CLK–Voltage1
Internal Clock Common-Mode
Single-Ended Input Voltage
Logic 1 Voltage
Logic 0 Voltage
Input Capacitance
Input Resistance
Full
Full
Full
IV
IV
V
0.4
0.25
0.4
0.25
V p-p
V
V
1.6
1.6
Full
Full
Full
Full
IV
IV
V
2
2
V
V
pF
kΩ
0.8
0.8
5
100
5
100
V
DIGITAL OUTPUTS (DRVDD = 5 V)2
Logic 1 Voltage (IOH = 50 µA)
Logic 0 Voltage (IOL = 50 µA)
Logic 1 Voltage (IOH = 0.5 mA)
Logic 0 Voltage (IOL = 1.6 mA)
Full
Full
Full
Full
IV
IV
IV
IV
4.5
2.4
4.5
2.4
V
V
V
V
0.1
0.4
0.1
0.4
DIGITAL OUTPUTS (DRVDD = 3 V)2
Logic 1 Voltage (IOH = 50 µA)
Logic 0 Voltage (IOL = 50 µA)
Logic 1 Voltage (IOH = 0.5 mA)
Logic 0 Voltage (IOL = 1.6 mA)
Full
Full
Full
Full
IV
IV
IV
IV
2.95
2.8
2.95
2.8
V
V
V
V
0.05
0.4
0.05
0.4
NOTES
1See Clock section of Theory of Operation for more details.
2Output voltage levels measured with 5 pF load on each output.
Specifications subject to change without notice.
–4–
REV. A
AD9244
SWITCHING SPECIFICATIONS
(AVDD = 5 V, DRVDD = 3 V, unless otherwise noted.)
Test
Level Min
AD9244BST-65
AD9244BST-40
Parameter
Temp
Typ
Max
Min
Typ
Max Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
Clock Period1
Full
Full
Full
Full
Full
Full
Full
VI
V
V
V
V
V
V
65
40
MHz
kHz
ns
ns
ns
ns
ns
500
500
15.4
4
4
6.9
6.9
25
4
4
11.3
11.3
Clock Pulsewidth High2
Clock Pulsewidth Low2
Clock Pulsewidth High3
Clock Pulsewidth Low3
DATA OUTPUT PARAMETERS
4
Output Delay (tPD
)
Full
Full
Full
Full
Full
V
V
V
V
V
3.5
7
3.5
7
ns
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Enable Delay
8
8
Clock Cycles
ns
ps rms
ns
1.5
0.3
15
1.5
0.3
15
OUT-OF-RANGE RECOVERY TIME
Full
V
2
1
Clock Cycles
NOTES
1The clock period may be extended to 2 µs with no degradation in specified performance at 25°C.
2With duty cycle stabilizer enabled.
3With duty cycle stabilizer disabled.
4Measured from clock 50% transition to data 50% transition with 5 pF load on each output.
Specifications subject to change without notice
N+3
N+2
N+1
N+4
N
N+5
ANALOG
INPUT
N+6
N+9
N+7
N+8
tA
CLOCK
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
tPD
Figure 1. Input Timing
REV. A
–5–
AD9244
ABSOLUTE MAXIMUM RATINGS1
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
With
Mnemonic
Respect to Min Max
Unit
II. 100% production tested at 25°C and sample tested at
ELECTRICAL
AVDD
DRVDD
AGND
AVDD
REFGND
specified temperatures.
AGND
DGND
DGND
DRVDD
AGND
–0.3 +6.5
–0.3 +6.5
–0.3 +0.3
–6.5 +6.5
V
V
V
V
V
V
V
V
V
V
V
V
V
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range;
100% production tested at temperature extremes for
military devices.
–0.3 +0.3
CLK+, CLK–, DCS AGND
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
–0.3 AVDD + 0.3
DFS
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DGND
DGND
DGND
VIN+, VIN–
VREF
SENSE
REFB, REFT
CML
VR
OTR
–0.3 DRVDD + 0.3 V
–0.3 DRVDD + 0.3 V
–0.3 DRVDD + 0.3 V
D0–D13
OEB
ENVIRONMENTAL2
Junction Temperature
Storage Temperature
Operating Temperature
Lead Temperature (10 sec)
150
–65 +150
–40 +85
300
°C
°C
°C
°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
2Typical thermal impedances; JA = 50.0°C/W; JC = 17.0°C/W. These measure-
ments were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7.
ORDERING GUIDE
Temperature Range Package Description
Model
Package Option
48-Lead Low Profile Quad Flatpack Package ST-48
AD9244BST-65
AD9244BST-40
–40°C to +85°C
–40°C to +85°C
48-Lead Low Profile Quad Flatpack Package ST-48
48-Lead Low Profile Quad Flatpack Package ST-48
48-Lead Low Profile Quad Flatpack Package ST-48
Evaluation Board
AD9244BSTRL-65 –40°C to +85°C
AD9244BSTRL-40 –40°C to +85°C
AD9244-65PCB
AD9244-40PCB
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9244 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–6–
REV. A
AD9244
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
SENSE
DFS
AGND
1
2
36
35
34
33
32
31
AGND
AVDD
AVDD
AGND
AGND
AVDD
3
AVDD
AGND
CLK–
CLK+
NIC
4
5
AD9244
TOP VIEW
(NOT TO SCALE)
6
7
30 DGND
29
28
27
26
25
DRVDD
OTR
8
OEB
9
10
11
12
D13 (MSB)
D12
D0 (LSB)
D1
D11
D2
13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1, 2, 5, 32, 33
3, 4, 31, 34
6, 7
8, 44
9
10
11–13, 16–21,
24–26
14, 22, 30
AGND
AVDD
CLK–, CLK+
NIC
OEB
D0 (LSB)
D1–D3, D4–D9,
D10–D12
DGND
Analog Ground.
Analog Supply Voltage.
Differential Clock Inputs.
No Internal Connection.
Digital Output Enable (Active Low).
Least Significant Bit, Digital Output.
Digital Outputs.
Digital Ground.
15, 23, 29
27
28
DRVDD
D13 (MSB)
OTR
Digital Supply Voltage.
Most Significant Bit, Digital Output.
Out-of-Range Indicator (Logic 1 indicates OTR).
35
36
DFS
SENSE
Data Format Select. Connect to AGND for straight binary, AVDD for twos complement.
Internal Reference Control.
37
VREF
Internal Reference.
38
39–42
43
REFGND
REFB, REFT
DCS
Reference Ground.
Internal Reference Decoupling.
50% Duty Cycle Stabilizer. Connect to AVDD to activate 50% duty cycle stabilizer, AGND
for external control of both clock edges.
Common-Mode Reference (0.5 × AVDD).
Differential Analog Inputs.
45
46, 47
48
CML
VIN+, VIN–
VR
Internal Bias Decoupling.
REV. A
–7–
AD9244
TERMINOLOGY
sampled signal does not overlap Nyquist zones and alias onto
itself. Nyquist sampling performance is limited by the band-
width of the input SHA and clock jitter (noise caused by jitter
increases as the input frequency increases).
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Integral Nonlinearity (INL)
Aperture Delay
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs 1/2 LSB before the first
code transition. Positive full scale is defined as a level 1 1/2 LSB
beyond the last code transition. The deviation is measured from
the middle of each particular code to the true straight line.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Voltage Range
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
The peak-to-peak differential voltage must be applied to the
converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180 degrees
out of phase. Peak-to-peak differential is computed by rotating
the input phase 180° and taking the peak measurement again.
Then the difference is found between the two peak measurements.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2), this is often referred to as
Nyquist sampling.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16384
codes must be present over all operating ranges.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Dual Tone SFDR*
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Power Supply Rejection Ratio
The change in full scale from the value with the supply at its
minimum limit to the value with the supply at its maximum limit.
Effective Number of Bits (ENOB)
The effective number of bits for a device for sine wave inputs at
a given input frequency can be calculated directly from its mea-
sured SINAD using the following formula:
Signal-to-Noise-and-Distortion (SINAD)*
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist fre-
quency, including harmonics but excluding dc.
N = SINAD – 1.76 / 6.02
(
)
Signal-to-Noise Ratio (SNR)*
Gain Error
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist fre-
quency, excluding the first six harmonics and dc.
The first code transition should occur at an analog value 1/2 LSB
above negative full scale. The last code transition should occur
at an analog value 1 1/2 LSB below the nominal full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Spurious-Free Dynamic Range (SFDR)*
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Temperature Drift
Common-Mode Rejection Ratio (CMRR)
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
Common-mode (CM) signals appearing on VIN+ and VIN– are
ideally rejected by the differential front end of the ADC. With a
full-scale CM signal driving both VIN+ and VIN–, CMRR is the
ratio of the amplitude of the full-scale input CM signal to the
amplitude of signal that is not rejected, expressed in dBFS.
at TMIN or TMAX
.
Total Harmonic Distortion (THD)*
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
IF Sampling
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Higher sampled frequencies will be aliased
down into the first Nyquist zone (DC–fCLOCK/2) on the output
of the ADC. Care must be taken that the bandwidth of the
Offset Error
The major carry transition should occur for an analog value
1/2 LSB below VIN+ = VIN–. Offset error is defined as the
deviation of the actual transition from that point.
*AC specifications may be reported in dBc (degrades as signal levels are lowered) or
in dBFS (always related back to converter full scale).
–8–
REV. A
AD9244
DRVDD
AVDD
DRVDD
DRVDD
CLK
BUFFER
200⍀
200⍀
DGND
DGND
AGND
a. D0–D13, OTR
b. Three-State (OEB)
c. CLK+, CLK–
AVDD
AVDD
AVDD
200⍀
AGND
AGND
AGND
d. VIN+, VIN–
e. DFS, DCS, SENSE
f. VREF, REFT, REFB, VR, CML
Figure 2. Equivalent Circuits
REV. A
–9–
AD9244–Typical Performance Characteristics
(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Duty Cycle Stabilizer Enabled, TA = 25؇C, Differential Analog Input, Common-Mode Voltage (VCM) =
2.5 V, Input Amplitude (AIN) = –0.5 dBFS, VREF = 2.0 V External, FFT length = 8 K, unless otherwise noted.)
0
–20
–40
–60
100
90
SNR = 74.8dBc
SFDR = 93.6dBc
SFDR – dBFS
SFDR – dBc
80
SNR – dBFS
70
SFDR = 90dBc
REFERENCE LINE
–80
60
SNR – dBc
–100
–120
50
40
0
5
10
15
20
25
30 32.5
–30
–25
–20
–15
– dBFS
–10
–5
0
FREQUENCY – MHz
A
IN
TPC 1. Single-Tone FFT, fIN = 5 MHz
TPC 4. Single-Tone SNR/SFDR vs. AIN, fIN = 5 MHz
0
100
SNR = 74.0dBc
SFDR = 87.0dBc
SFDR – dBFS
90
–20
–40
–60
80
SNR – dBFS
70
60
50
40
SFDR – dBc
SFDR = 90dBc
REFERENCE LINE
–80
–100
–120
SNR – dBc
0
5
10
15
20
25
30 32.5
–30
–25
–20
–15
–10
–5
0
FREQUENCY – MHz
A
– dBFS
IN
TPC 2. Single-Tone FFT, fIN = 31 MHz
TPC 5. Single-Tone SNR/SFDR vs AIN, fIN = 31 MHz
0
–20
–40
–60
100
SNR = 68.0dBc
SFDR = 59.5dBc
90
SFDR – dBFS
80
SNR – dBFS
SFDR – dBc
70
SFDR = 90dBc
–80
60
50
REFERENCE LINE
SNR – dBc
–100
–120
40
–30
0
5
10
15
20
25
30
30.72
–25
–20
–15
–10
–5
0
FREQUENCY – MHz
A
– dBFS
IN
TPC 3. Single-Tone FFT, fIN = 190 MHz, fSAMPLE
61.44 MSPS
=
TPC 6. Single-Tone SNR/SFDR vs. AIN,
fIN = 190 MHz, fSAMPLE = 61.44 MSPS
–10–
REV. A
AD9244
75
73
71
12.2
11.8
11.5
11.2
75
73
71
2V SPAN
1V SPAN
2V SPAN
69
67
65
69
67
65
1V SPAN
10.8
10.5
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
TPC 7. SINAD/ENOB vs. Input Frequency
TPC 10. SNR vs. Input Frequency
–100
–95
–90
–85
–80
–75
100
95
90
85
80
75
1V SPAN
1V SPAN
2V SPAN
100
2V SPAN
0
20
40
60
80
100
120
140
0
20
40
60
80
120
140
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
TPC 8. THD vs. Input Frequency
TPC 11. SFDR vs. Input Frequency
–92
–90
–88
–86
–84
–82
–80
–78
–76
–74
77
75
73
71
–40؇C
+25؇C
+25؇C
–40؇C
+85؇C
69
67
+85؇C
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
INPUT FREQUENCY – MHz
INPUT FREQUENCY – MHz
TPC 9. SNR vs. Temperature and Input Frequency
TPC 12. THD vs. Temperature and Input Frequency
REV. A
–11–
AD9244
–100
100
95
90
85
80
75
70
65
60
FOURTH
–95
–90
–85
–80
HARMONIC
SFDR, DCS ON
THIRD
HARMONIC
SFDR, DCS OFF
SNR, DCS ON
SECOND
HARMONIC
SNR, DCS OFF
–75
0
30
35
40
45
50
55
60
65
70
20
40
60
80
100
120
140
DUTY CYCLE – %
INPUT FREQUENCY – MHz
TPC 16. SNR/SFDR vs. Duty Cycle, fIN = 2.5 MHz
TPC 13. Harmonics vs. Input Frequency
100
76
75
12.33
f
= 2MHz
IN
f
= 2MHz
IN
12.17
12.00
11.83
11.67
96
92
88
84
80
74
73
f
= 10MHz
IN
f
= 10MHz
IN
f
= 20MHz
IN
72
71
70
f
= 20MHz
IN
11.50
11.34
0
20
40
60
80
100
0
20
40
60
80
100
SAMPLE RATE – MSPS
SAMPLE RATE – MSPS
TPC 17. SFDR vs. Sample Rate
TPC 14. SINAD vs. Sample Rate
1.5
1.0
0.5
1.0
0.8
0.6
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
0
4096
8192
12288
16384
0
4096
8192
12288
16384
CODES – 14-Bit
CODES – 14-Bit
TPC 15. Typical INL
TPC 18. Typical DNL
–12–
REV. A
AD9244
TYPICAL IF SAMPLING PERFORMANCE
0
100
90
80
70
60
50
40
SFDR – dBFS
SNR = 67.5dBc
SFDR = 79.4dBc
–20
–40
SFDR – dBc
SNR – dBFS
–60
SFDR = 90dBc
–80
REFERENCE LINE
SNR – dBc
–100
–120
0
5
10
15
20
25
30 32.5
–30
–25
–20
–15
– dBFS
–10
–6
FREQUENCY – MHz
A
IN
TPC 19. Dual-Tone FFT with fIN–1 = 44.2 MHz and
fIN–2 = 45.6 MHz (AIN1 = AIN2 = –6.5 dBFS)
TPC 22. Dual-Tone SNR/SFDR vs. AIN with fIN–1
44.2 MHz and fIN–2 = 45.6 MHz
=
0
100
SNR = 67.0dBc
SFDR = 78.2dBc
–20
–40
SFDR – dBFS
90
80
70
60
50
40
SNR – dBFS
SFDR – dBc
–60
SFDR = 90dBc
REFERENCE LINE
–80
–100
–120
SNR – dBc
–25
0
5
10
15
20
25
30 32.5
–30
–20
A
–15
– dBFS
–10
–6
FREQUENCY – MHz
IN
TPC 20. Dual-Tone FFT with fIN–1 = 69.2 MHz and
fIN–2 = 70.6 MHz (AIN1 = AIN2 = –6.5 dBFS)
TPC 23. Dual-Tone SNR/SFDR vs. AIN with fIN–1
69.2 MHz and fIN–2 = 70.6 MHz
=
0
100
SNR = 65.0dBc
SFDR = 69.1dBc
SFDR – dBFS
90
–20
–40
80
SNR – dBFS
–60
70
SFDR – dBc
–80
60
50
40
SFDR = 90dBc
REFERENCE LINE
–100
–120
SNR – dBc
–30
–25
–20
–15
– dBFS
–10
–6
0
5
10
15
20
25
30 32.5
A
FREQUENCY – MHz
IN
TPC 21. Dual-Tone FFT with fIN–1 = 139.2 MHz and
fIN–2 = 140.7 MHz (AIN1 = AIN2 = –6.5 dBFS)
TPC 24. Dual-Tone SNR/SFDR vs. AIN with fIN–1
139.2 MHz and fIN–2 = 140.7 MHz
=
REV. A
–13–
AD9244
0
100
90
80
70
60
50
40
SNR = 62.6dBc
SFDR = 60.7dBc
SFDR – dBFS
–20
–40
SNR – dBFS
–60
SFDR – dBc
–80
SFDR = 90dBc
REFERENCE LINE
–100
SNR – dBc
–25
–120
0
5
10
15
20
25
30 32.5
–30
–20
A
–15
– dBFS
–10
–6
FREQUENCY – MHz
IN
T
PC 28.
Dual-Tone SNR/SFDR vs. AIN with fIN–1
TPC 25. Dual-Tone FFT with fIN–1 = 239.1 MHz and
fIN–2 = 240.7 MHz (AIN–1 = AIN2 = –6.5 dBFS)
=
239.1 MHz and fIN–2 = 240.7 MHz
95
0
SFDR – dBFS
SNR = 73.0dBFS
THD = –89.5dBFS
90
–20
–40
SFDR – dBc
85
80
NOTE: SPUR FLOOR
SNR – dBFS
75
BELOW 90dBFS @ 240MHz
–60
–80
70
65
60
55
SFDR = 90dBc
REFERENCE LINE
–100
–120
SNR – dBc
–21
–18
–15
–12
–9
– dBFS
–6
–3
0
0
5
10
15
20
25
30 32.5
FREQUENCY – MHz
A
IN
TPC 29. Driving ADC Inputs with Transformer
and Balun SNR/SFDR vs. AIN, fIN = 240 MHz
TPC 26. Driving ADC Inputs with Transformer
and Balun, fIN = 240 MHz, AIN = –8.5 dBFS
95
105
100
95
SFDR – dBFS
90
85
SFDR – dBc
90
80
75
SNR – dBFS
85
80
70
SFDR = 90dBc
REFERENCE LINE
75
65
SNR – dBc
70
60
55
65
0
50
100
150
200
250
–21
–18
–15
–12
–9
–6
–3
0
INPUT FREQUENCY – MHz
A
– dBFS
IN
TPC 30. Driving ADC Inputs with Transformer
and Balun SNR/SFDR vs. AIN, fIN = 190 MHz
TPC 27. CMRR vs. Input Frequency (AIN = 0 dBFS
and CML = 2.5 V)
–14–
REV. A
AD9244
2.5V
1.5V
THEORY OF OPERATION
The AD9244 is a high performance, single-supply 14-bit ADC. In
addition to high dynamic range Nyquist sampling, it is designed for
excellent IF undersampling performance with an analog input as
high as 240 MHz.
AD9244
33⍀
VIN+
0.1F
20pF
50⍀
REFT
REFB
VIN–
33⍀
+
10F
0.1F
0.1F
2V
The AD9244 uses a calibrated 10-stage pipeline architecture
with a patented wideband, input sample-and-hold amplifier
(SHA) implemented on a cost-effective CMOS process. Each stage
of the pipeline, excluding the last, consists of a low resolution flash
ADC along with a switched capacitor DAC and interstage residue
amplifier (MDAC). The MDAC amplifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each of the
stages to facilitate digital correction of flash errors. The last stage
simply consists of a flash ADC.
VREF
2.5V
1.5V
+
0.1F
10F
SENSE
REFGND
Figure 3a. 2 V p-p Differential Input, Common-Mode
Voltage = 2 V
3.0V
1.0V
AD9244
33⍀
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. While the converter captures a
new input sample every clock cycle, it takes eight clock cycles
for the conversion to be fully processed and appear at the out-
put as illustrated in Figure 1. This latency is not a concern in
many applications. The digital output, together with the OTR
indicator, is latched into an output buffer to drive the output
pins. The output drivers of the AD9244 can be configured to
interface with 5 V or 3.3 V logic families.
VIN+
20pF
33⍀
0.1F
VIN–
REFT
REFB
2V
0.1F
+
VREF
0.1F
0.1F
10F
+
10F
SENSE
REFGND
Figure 3b. 2 V p-p Single-Ended Input, Common-Mode
Voltage = 2 V
The AD9244 has a duty clock stabilizer (DCS) that generates
its own internal falling edge to create an internal 50% duty cycle
clock, independent of the externally applied duty cycle. Control
of straight binary or twos complement output format is accom-
plished with the DFS pin.
AD9244
2.5V
0.1F
CML
3.0V
2.0V
The ADC samples the analog input on the rising edge of the
clock. While the clock is low, the input SHA is in sample mode.
When the clock transitions to a high logic level, the SHA goes
into the hold mode. System disturbances just prior to or imme-
diately after the rising edge of the clock and/or excessive clock
jitter may cause the SHA to acquire the wrong input value and
should be minimized.
33⍀
VIN+
VIN–
VREF
50⍀
0.1F
20pF
REFT
REFB
33⍀
+
0.1F
0.1F
10F
2V
3.0V
3.0V
+
2.5V
10F
0.1F
2.0V
2.0V
SENSE
REFGND
ANALOG INPUT AND REFERENCE OVERVIEW
The differential input span of the AD9244 is equal to the potential
at the VREF pin. The VREF potential may be obtained from the
internal AD9244 reference or an external source.
Figure 3c. 2 V p-p Differential Input, Common-Mode
Voltage = 2.5 V
In differential applications, the center point of the input span is
the common-mode level of the input signals. In single-ended
applications, the center point is the dc potential applied to one
input pin while the signal is applied to the opposite input pin.
Figures 3a to 3c show various system configurations.
Figure 4 is a simplified model of the AD9244 analog input,
showing the relationship between the analog inputs, VIN+, VIN–,
and the reference voltage, VREF. Note that this is only a sym-
bolic model and that no actual negative voltages exist inside the
AD9244. Similar to the voltages applied to the top and bottom
of the resistor ladder in a flash ADC, the value VREF/2 defines
the minimum and maximum input voltages to the ADC core.
AD9244
VIN+
+VREF/2
14
V
+
–
CORE
ADC
CORE
⌺
–VREF/2
VIN–
Figure 4. Equivalent Analog Input of AD9244
REV. A
–15–
AD9244
A differential input structure allows the user to easily configure
the inputs for either single-ended or differential operation. The
ADC’s input structure allows the dc offset of the input signal to
be varied independent of the input span of the converter. Specifi-
cally, the input to the ADC core can be defined as the difference
of the voltages applied at the VIN+ and VIN– input pins.
Therefore, the equation
For additional information showing the relationship between
VIN+, VIN–, VREF, and the analog input range of the AD9244,
see Tables I and II.
ANALOG INPUT OPERATION
Figure 5 shows the equivalent analog input of the AD9244,
which consists of a 750 MHz differential SHA. The differential
input structure of the SHA is flexible, allowing the device to be
configured for either a differential or single-ended input. The
analog inputs VIN+ and VIN– are interchangeable, with the
exception that reversing the inputs to the VIN+ and VIN– pins
results in a data inversion (complementing the output word).
VCORE = VIN+ – VIN–
(1)
defines the output of the differential input stage and provides
the input to the ADC core. The voltage, VCORE, must satisfy the
condition
–VREF/2 < VCORE < VREF/2
(2)
S
where VREF is the voltage at the VREF pin.
C
H
In addition to the limitations placed on the input voltages VIN+
and VIN– by Equations 1 and 2, boundaries on the inputs
also exist based on the power supply voltages according to the
conditions
S
C
S
VIN+
–
C
PIN, PAR
S
H
VIN–
+
AGND – 0.3 V < VIN + < AVDD + 0.3 V
C
C
S
PIN, PAR
C
H
(3)
AGND – 0.3 V < VIN – < AVDD + 0.3 V
S
where AGND is nominally 0 V and AVDD is nominally 5 V. The
range of valid inputs for VIN+ and VIN– is any combination that
satisfies both Equations 2 and 3.
Figure 5. Analog Input of AD9244 SHA
Table I. Analog Input Configuration Summary
Input Range (V)
Input
Connection
Input
Coupling Span (V) VIN+*
Input CM
Voltage
VIN–
Comments
*
Single-Ended
DC or AC 1.0
2.0
0.5 to 1.5
1 to 3
1.0
1.0
2.0
Best for stepped input response applications.
2.0
Optimum noise performance for single-ended
mode, often requires low distortion op amp with
VCC > 5 V due to its headroom issues.
Differential
DC or AC 1.0
2.0
2.25 to 2.75 2.75 to 2.25 2.5
2.0 to 3.0 3.0 to 2.0 2.5
Optimum full-scale THD and SFDR performance
well beyond the ADC’s Nyquist frequency.
Optimum noise performance for differential mode
Preferred mode for applications.
*
VIN+ and VIN– can be interchanged if data inversion is required.
Table II. Reference Configuration Summary
Reference
Operating Mode
Input Span (VIN+ – VIN–)
(V p-p)
Connect
To
Resulting VREF (V)
Internal
Internal
Internal
SENSE
SENSE
R1
R2
SENSE
VREF
VREF
AGND
VREF and SENSE
SENSE and REFGND
AVDD
1
2
1
2
1 Յ VREF Յ 2.0
VREF = (1 + R1/R2)
1 Յ VREF Յ 2.0
1 Յ SPAN Յ 2
(SPAN = VREF)
SPAN = EXTERNAL REF
External
EXTERNAL REF
–16–
REV. A
AD9244
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (i.e., 2 V input span) and matched
input impedance for VIN+ and VIN–. Only a slight degradation
in dc linearity performance exists between the 2 V and 1 V input
spans; however, the SNR is lower in the 1 V input span.
Since not all applications have a signal precondition for differential
operation, there is often a need to perform a single-ended-to-
differential conversion. In systems that do not require dc coupling,
an RF transformer with a center tap is the best method for
generating differential input signals for the AD9244. This provides
the benefit of operating the ADC in the differential mode without
contributing additional noise or distortion. An RF transformer
also has the added benefit of providing electrical isolation between
the signal source and the ADC.
When the ADC is driven by an op amp and a capacitive load is
switched onto the output of the op amp, the output will momen-
tarily drop due to its effective output impedance. As the output
recovers, ringing may occur. To remedy the situation, a series
resistor, RS, can be inserted between the op amp and the SHA
input as shown in Figure 6. A shunt capacitance also acts like
a charge reservoir, sinking or sourcing the additional charge
required by the sampling capacitor, CS, further reducing current
transients seen at the op amp’s output.
The differential input characterization for this data sheet was
performed using the configuration in Figure 7. The circuit uses
a Mini-Circuits® RF transformer, model T1–1T, which has an
impedance ratio of 1:1. This circuit assumes that the signal source
has a 50 Ω source impedance. The secondary center tap of the
transformer allows a dc common-mode voltage to be added to
the differential input signal. In Figure 7, the center tap is con-
nected to a resistor divider providing a half supply voltage. It could
also be connected to the CML pin of the AD9244. It is recom-
mended for IF sampling applications (70 MHz < fIN < 200 MHz)
that the 20 pF differential capacitor between VIN+ and VIN–
be reduced or removed.
V
CC
R
S
33⍀
AD9244
VIN+
R
20pF
S
33⍀
V
EE
VIN–
VREF
AVDD
+
10F
0.1F
R
33⍀
S
1k⍀
SENSE
0.1F
VIN+
REFCOM
REFT
+
0.1F
0.1F
50⍀
20pF
0.1F
10F
AD9244
1k⍀
REFB
Figure 6. Resistors Isolating SHA Input from Op Amp
VIN–
MINI-CIRCUITS
T1–1T
R
S
33⍀
The optimum size of this resistor is dependent on several factors,
including the ADC sampling rate, the selected op amp, and the
particular application. In most applications, a 30 Ω to 100 Ω
resistor is sufficient.
Figure 7. Transformer-Coupled Input
The circuit shown in Figure 8 shows a method for applying a
differential direct-coupled signal to the AD9244. An AD8138
amplifier is used to derive a differential signal from a single-
ended signal.
For noise sensitive applications, the very high bandwidth of the
AD9244 may be detrimental and the addition of a series resistor
and/or shunt capacitor can help limit the wideband noise at the
ADC’s input by forming a low-pass filter. The source impedance
driving VIN+ and VIN– should be matched. Failure to provide
matching may result in degradation of the SNR, THD, and
SFDR performance.
10F
+
5V
10F
0.1F
1k⍀
+
0.1F
0.1F
1k⍀
Differentially Driving the Analog Inputs
The AD9244 has a very flexible input structure, allowing it to
interface with single-ended or differential inputs.
0.1F
AVDD
VIN+
1V p-p
33⍀
499⍀
0V
475⍀
499⍀
REFT
The optimum mode of operation, analog input range, and
associated interface circuitry will be determined by the particular
application’s performance requirements as well as power supply
options.
0.1F
10F
+
20pF
AD9244
REFB
AD8138
50⍀
0.1F
VIN–
499⍀
33⍀
Differential operation requires that VIN+ and VIN– be simulta-
neously driven with two equal signals that are 180° out of phase
with each other.
Figure 8. Direct-Coupled Drive Circuit with AD8138
Differential Op Amp
Differential modes of operation (ac-coupled or dc-coupled input)
provide the best SFDR performance over a wide frequency range.
They should be considered for the most demanding spectral-based
applications (i.e., direct IF conversion to digital).
REV. A
–17–
AD9244
REFERENCE OPERATION
Pin Programmable Reference
The AD9244 contains a band gap reference that provides a pin-
strappable option to generate either a 1 V or 2 V output. With the
addition of two external resistors, the user can generate reference
voltages between 1 V and 2 V. Another alternative is to use an
external reference for designs requiring enhanced accuracy and/or
drift performance as described later in this section. Figure 9a
shows a simplified model of the internal voltage reference of the
AD9244. A reference amplifier buffers a 1 V fixed reference. The
output from the reference amplifier, A1, appears on the VREF pin.
As stated earlier, the voltage on the VREF pin determines the
full-scale differential input span of the ADC.
By shorting the VREF pin directly to the SENSE pin, the internal
reference amplifier is placed in a unity gain mode and the resulting
VREF output is 1 V. By shorting the SENSE pin directly to the
REFGND pin, the internal reference amplifier is configured for a
gain of 2.0 and the resulting VREF output is 2.0 V.
Resistor Programmable Reference
Figure 10 shows an example of how to generate a reference voltage
other than 1.0 V or 2.0 V with the addition of two external
resistors. Use the equation
VREF = 1 V × 1+ R1/R2
(
)
to determine the appropriate values for R1 and R2. These resistors
should be in the 2 kΩ to 10 kΩ range. For the example shown,
R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation above,
the resulting reference voltage on the VREF pin is 1.5 V. This
sets the differential input span to 1.5 V p-p. The midscale voltage
can also be set to VREF by connecting VIN– to VREF.
AD9244
TO
ADC
REFT
A2
2.5V
REFB
VREF
AD9244
VIN+
3.25V
1.75V
33⍀
20pF
0.1F
2.5V
VIN–
33⍀
A1
REFT
REFB
1.5V
1V
VREF
R
R
R1
2.5k⍀
0.1F
0.1F
10F
10F
0.1F
SENSE
SENSE
R2
5k⍀
DISABLE
A1
LOGIC
REFGND
REFGND
Figure 10. Resistor Programmable Reference (1.5 V p-p
Input Span, Differential Input with VCM = 2.5 V)
Figure 9a. Equivalent Reference Circuit
Using an External Reference
The voltage appearing at the VREF pin and the state of the internal
reference amplifier, A1, are determined by the voltage present at
the SENSE pin. The logic circuitry contains comparators that
monitor the voltage at the SENSE pin. The various reference
modes are summarized in Table II and are described in the next
few sections.
To use an external reference, the internal reference must be
disabled by connecting the SENSE pin to AVDD. The AD9244
contains an internal reference buffer, A2 (see Figure 9a), that
simplifies the drive requirements of an external reference. The
external reference must be able to drive a 5 kΩ ( 20%) load. The
bandwidth of the reference is deliberately left small to minimize
the reference noise contribution. As a result, it is not possible to
drive VREF externally with high frequencies.
The actual reference voltages used by the internal circuitry of the
AD9244 appear on the REFT and REFB pins. The voltages on
these pins are symmetrical about midsupply or CML. For proper
operation, it is necessary to add a capacitor network to decouple
these pins. Figure 9b shows the recommended decoupling network.
The turn-on time of the reference voltage appearing between
REFT and REFB is approximately 10 ms and should be taken
into consideration in any power-down mode of operation. The
VREF pin should be bypassed to the REFGND pin with a 10 µF
tantalum capacitor in parallel with a low inductance 0.1 µF
ceramic capacitor.
Figure 11 shows an example of an external reference driving both
VIN– and VREF. In this case, both the common-mode voltage
and input span are directly dependent on the value of VREF.
Both the input span and the center of the input span are equal
to the external VREF. Thus the valid input range extends from
(VREF + VREF/2) to (VREF – VREF/2). For example, if the
precision reference part, REF191, a 2.048 V external reference,
is used, the input span is 2.048 V. In this case, 1 LSB of the
AD9244 corresponds to 0.125 mV. It is essential that a minimum
of a 10 µF capacitor, in parallel with a 0.1 µF low inductance
ceramic capacitor, decouple the reference output to AGND.
0.1F
VREF
REFT
+
+
*
10F
0.1F
0.1F
10F
AD9244
AD9244
REFGND REFB
VREF + VREF/2
VREF – VREF/2
33⍀
20pF
33⍀
0.1F
AVDD
0.1F
VIN+
0.1F
*LOCATE AS CLOSE AS POSSIBLETO REFT/REFB PINS
REFT
REFB
5V
VIN–
VREF
+
0.1F
0.1F
10F
0.1F
Figure 9b. Reference Decoupling
10F
VREF
SENSE
Figure 11. Using an External Reference
–18–
REV. A
AD9244
Table III. Output Data Format
Binary
Twos
Complement
Mode
Input (V)
Condition (V)
Output Mode
OTR
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
<
–VREF – 0.5 LSB
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
1
0
0
0
1
= –VREF
= 0
= +VREF – 1.0 LSB
> +VREF – 0.5 LSB
+FS – 1 LSB
DIGITAL INPUTS AND OUTPUTS
Digital Outputs
Table III details the relationship among the ADC input, OTR,
and digital output format.
OTR DATA OUTPUTS
OTR
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
–FS + 1/2 LSB
Data Format Select (DFS)
The AD9244 may be programmed for straight binary or twos
complement data on the digital outputs. Connect the DFS pin to
AGND for straight binary and to AVDD for twos complement.
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
–FS
–FS – 1/2 LSB
+FS
+FS – 1/2 LSB
Digital Output Driver Considerations
Figure 12. OTR Relation to Input Voltage and Output Data
The AD9244 output drivers can be configured to interface with
5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V,
respectively. The output drivers are sized to provide sufficient
output current to drive a wide variety of logic families. How-
ever, large drive currents tend to cause glitches on the supplies
and may affect converter performance. Applications requiring
the ADC to drive large capacitive loads or large fanouts may
require external buffers or latches.
Table IV. Output Data Format
OTR
MSB
Analog Input Is
0
0
1
1
0
1
0
1
Within Range
Within Range
Underrange
Overrange
Out-of-Range (OTR)
An out-of-range condition exists when the analog input voltage is
beyond the input range of the ADC. OTR is a digital output that
is updated along with the data output corresponding to the par-
ticular sampled input voltage. Thus, OTR has the same pipeline
latency as the digital data. OTR is low when the analog input
voltage is within the analog input range and high when the analog
input voltage exceeds the input range as shown in Figure 12.
OTR will remain high until the analog input returns to within the
input range and another conversion is completed. By logically
AND-ing OTR with the MSB and its complement, overrange
high or underrange low conditions can be detected. Table IV is a
truth table for the overrange/underrange range circuit in Figure 13,
which uses NAND gates. Systems requiring programmable gain
conditioning of the AD9244 can, after eight clock cycles, detect an
out-of-range condition, thus eliminating gain selection iterations.
Also, OTR can be used for digital offset and gain calibration.
MSB
OTR
MSB
OVER = 1
UNDER = 1
Figure 13. Overrange/Underrange Logic
Digital Output Enable Function (OEB)
The AD9244 has three-state ability. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the
output data drivers are placed in a high impedance state. It is
not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
REV. A
–19–
AD9244
CLOCK OVERVIEW
Clock Input Considerations
The AD9244 has a flexible clock interface that accepts either a
single-ended or differential clock. An internal bias voltage facilitates
ac coupling using two external capacitors. To remain backward
compatible with the single-pin clock scheme of the AD9226, the
AD9244 can be operated with a dc-coupled, single-pin clock by
grounding the CLK– pin and driving CLK+.
The analog input is sampled on the rising edge of the clock.
Timing variations, or jitter, on this edge causes the sampled
input voltage to be in error by an amount proportional to the
slew rate of the input signal and to the amount of the timing
variation. Thus, to maintain the excellent high frequency SFDR
and SNR characteristics of the AD9244, it is essential that the
clock edge be kept as clean as possible.
When the CLK– pin is not grounded, the CLK+ and CLK– pins
function as a differential clock receiver. When CLK+ is greater
than CLK–, the SHA is in hold mode; when CLK+ is less than
CLK–, the SHA is in track mode (see timing in Figure 14). The
rising edge of the clock (CLK+ – CLK–) switches the SHA from
track to hold and timing jitter on this transition should be mini-
mized, especially for high frequency analog inputs.
The clock should be treated like an analog signal. Clock drivers
should not share supplies with digital logic or noisy circuits. The
clock traces should not run parallel to noisy traces. Using a pair
of symmetrically routed, differential clock signals can help to
provide immunity from common-mode noise coupled from the
environment.
It is often difficult to maintain a 50% duty cycle to the ADC,
especially when driving the clock with a single-ended or sine
wave input. To ease the constraint of providing an accurate
50% clock, the ADC has an optional internal duty cycle stabilizer
(DCS) that allows the rising clock edge to pass through with
minimal jitter and interpolates the falling edge, independent of
the input clock falling edge. The DCS is described in greater
detail in a later section.
The clock receiver functions like a differential comparator. At
the CLK inputs, a slowly changing clock signal will result in
more jitter than a rapidly changing one. Driving the clock with
a low amplitude sine wave input is not recommended. Running
a high speed clock through a divider circuit will provide a fast
rise/fall time, resulting in the lowest jitter in most systems.
Clock Input Modes
Figures 15a to 15e illustrate the modes of operation of the clock
receiver. Figure 15a shows a differential clock directly coupled to
CLK+ and CLK–. In this mode, the common mode of the CLK+
and CLK– signals should be close to 1.6 V. Figure 15b illustrates
a single-ended clock input. The capacitor decouples the internal
bias voltage on the CLK– pin (about 1.6 V), establishing a threshold
for the CLK+ pin. Figure 15c provides backward compatibility
with the AD9226. In this mode, CLK– is grounded and the
threshold for CLK+ is 1.5 V. Figure 15d shows a differential clock
ac-coupled by connecting through two capacitors. AC coupling
a single-ended clock can also be accomplished using the circuit
in Figure 15e.
CLK+
AD9244
CLK–
Figure 15a. Differential Clock Input—DC-Coupled
When using the differential clock circuits of Figure 15a or
Figure 15d, if CLK– drops below 250 mV, the mode of the clock
receiver may change, causing conversion errors. It is essential
that CLK– remain above 250 mV when the clock is ac-coupled
or dc-coupled.
CLK+
AD9244
1.6V
CLK–
0.1F
AGND
CLK–
CLK+
Figure 15b. Single-Ended Clock Input
—DC-Coupled
SHA IN
HOLD
SHA IN
TRACK
CLK+
AD9244
CLK–
CLK–
CLK+
AGND
Figure 14. SHA Timing
Figure 15c. Single-Ended Input
Compatibility with AD9226
—
Retains Pin
–20–
REV. A
AD9244
speed. When the stabilizer is disabled, the internal switching will
be directly affected by the clock state. If CLK+ is high, the SHA
will be in hold mode; if CLK+ is low, the SHA will be in track
mode. TPC 16 shows the benefits of using the clock stabilizer.
Connecting the DCS pin to AVDD implements the internal clock
stabilization function in the AD9244. If the DCS pin is connected
to ground, the AD9244 will use both edges of the external clock
in its internal timing circuitry (see Specifications for timing
requirements).
CLK+
CLK–
AD9244
100pF – 0.1F
Figure 15d. Differential Clock Input
—
AC-Coupled
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in high speed, high resolution sys-
tems. Multilayer printed circuit boards (PCBs) are recommended
to provide optimal grounding and power distribution. The use of
power and ground planes offers distinct advantages, including:
0.1F
CLK+
AD9244
1.6V
•
•
•
The minimization of the loop area encompassed by a signal
and its return path.
CLK–
0.1F
The minimization of the impedance associated with ground
and power paths.
AGND
The inherent distributed capacitor formed by the power
plane, PCB material, and ground plane.
Figure 15e. Single-Ended Clock Input
—AC-Coupled
Clock Power Dissipation
It is important to design a layout that minimizes noise from
coupling onto the input signal. Digital input signals should not be
run in parallel with input signal traces and should be routed away
from the input circuitry. While the AD9244 features separate
analog and digital ground pins, it should be treated as an analog
component. The AGND and DGND pins must be joined together
directly under the AD9244. A solid ground plane under the
ADC is acceptable if the power and ground return currents are
carefully managed.
Most of the power dissipated by the AD9244 is from the analog
power supplies. However, lower clock speeds will reduce digital
supply current. Figure 16 shows the relationship between power
and clock rate.
600
550
AD9244-65
500
Analog Supply Decoupling
450
400
350
The AD9244 features separate analog and digital supply and
ground circuits, helping to minimize digital corruption of sensitive
analog signals. In general, AVDD (analog power) should be
decoupled to AGND (analog ground). The AVDD and AGND
pins are adjacent to one another. Figure 17 shows the recom-
mended decoupling for each pair of analog supplies; 0.1 µF
ceramic chip and 10 µF tantalum capacitors should provide
adequately low impedance over a wide frequency range. The
decoupling capacitors (especially 0.1 µF) should be located as
close to the pins as possible.
AD9244-40
300
250
200
0
10
20
30
40
50
60
70
SAMPLE RATE – MHz
Figure 16. Power Consumption vs. Sample Rate
AVDD
+
*
0.1F
10F
AD9244
AGND
Clock Stabilizer (DCS)
The clock stabilizer circuit in the AD9244 desensitizes the ADC
from clock duty cycle variations. System clock constraints are
eased by internally restoring the clock duty cycle to 50%, inde-
pendent of the clock input duty cycle. Low jitter on the rising
edge (sampling edge) of the clock is preserved while the falling
edge is generated on-chip.
*LOCATE AS CLOSE AS POSSIBLE TO SUPPLY PINS
Figure 17. Analog Supply Decoupling
Digital Supply Decoupling
The digital activity on the AD9244 falls into two categories:
correction logic and output drivers. The internal correction
logic draws relatively small surges of current, mainly during the
clock transitions. The output drivers draw large current impulses
when the output bits change state. The size and duration of
these currents are a function of the load on the output bits; large
capacitive loads should be avoided.
It may be desirable to disable the clock stabilizer and may be
necessary when the clock frequency is varied or completely stopped.
Note that stopping the clock is not recommended with ac-coupled
clocks. Once the clock frequency is changed, over 100 clock cycles
may be required for the clock stabilizer to settle to the new
REV. A
–21–
AD9244
For the digital decoupling shown in Figure 18, 0.1 µF ceramic
chip and 10 µF tantalum capacitors are appropriate. The decou-
pling capacitors (especially 0.1 µF) should be located as close to
the pins as possible. Reasonable capacitive loads on the data
pins are less than 20 pF per bit. Applications involving greater
digital loads should consider increasing the digital decoupling
and/or using external buffers/latches.
from single-ended signals to differential. Optimal AD9244 perfor-
mance is achieved above 500 kHz by using the input transformer. To
drive the AD9244 via the transformer, connect solderable Jumpers
JP45 and JP46. DC bias is provided by the Resistors R8 and R28.
The evaluation board has positions for through-hole and surface-
mount transformers. For applications requiring lower frequencies
or dc applications, the AD8138 can be used. The AD8138 will
provide good distortion and noise performance, as well as input
buffering, up to 30 MHz. For more information, refer to the
AD8138 data sheet. To use the AD8138 to drive the AD9244,
remove the transformer (T1 or T4) and connect solderable
Jumpers JP42 and JP43. The AD9244 can be driven single-ended
directly via S3 and can be ac-coupled or dc-coupled by removing
or inserting JP5. To run the evaluation board in this way, remove
the transformer (T1 or T4) and connect solderable Jumpers
JP40 and JP41. The Resistors R40, R41, R8, and R28 are used
to bias the AD9244 inputs to the correct common-mode levels
in this application.
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the power supply connector to reduce
low frequency ripple to insignificant levels.
DRVDD
+
*
0.1F
10F
AD9244
DGND
*LOCATE AS CLOSE AS POSSIBLE TO SUPPLY PINS
Figure 18. Digital Supply Decoupling
CML
Reference Configuration
The AD9244 has a midsupply reference point. This is used within
the internal architecture of the AD9244 and must be decoupled
with a 0.1 µF capacitor. It will source or sink a load of up to
300 µA. If more current is required, the CML pin should be
buffered with an amplifier.
As described in the Analog Input and Reference Overview section
earlier in this data sheet, the AD9244 can be configured to use its
own internal or an external reference. An external reference, D3,
and reference buffer, U5, are included on the AD9244 evaluation
board. Jumpers JP8 and JP22–JP24 can be used to select the
desired reference configuration (Table VI).
VR
VR is an internal bias point on the AD9244. It must be decoupled
to AGND with a 0.1 µF capacitor.
Clock Configuration
The AD9244 evaluation board was designed to achieve optimal
performance as well as to be easily configurable by the user. To
configure the clock input, begin by connecting the correct com-
bination of solderable Jumpers JP11–JP15 (Table VII). The
specific jumper configuration is dependent on the application and
can be determined by referring to the clock input modes section.
If the differential clock input mode is selected, an external sine
wave generator applied to S5 can be used as the clock source.
The clock buffer/drive MC10EL16 from ON Semiconductor is
used on the evaluation board to buffer and square the clock input.
If the single-ended clock configuration is used, an external clock
source can be applied to S1.
CML
VR
AD9244
0.1F
0.1F
Figure 19. CML/VR Decoupling
EVALUATION BOARD
Analog Input Configuration
Table V provides a summary of the analog input configuration.
The analog inputs of the AD9244 on the evaluation board can be
driven differentially through a transformer via Connector S4, or
the AD8138 amplifier via Connector S2, or driven single-ended
directly via Connector S3. When using the transformer or AD8138
amplifier, a single-ended source may be used as both of these
devices are configured on the AD9244 evaluation board to convert
The AD9244 evaluation board generates a buffered clock at
TTL/CMOS levels for use with a data capture system, such as the
HSC-ADC-EVAL-SC system. The clock buffering is provided
by U4 and U7 and is configured by Jumpers JP3, JP4, JP9, and
JP18 (Table VII).
–22–
REV. A
AD9244
Table V. Analog Input Jumper Configuration
Input
Connector
Jumpers
Notes
Differential: Transformer
Differential: Amplifier
Single-Ended
S4
S2
S3
45, 46
42, 43
5, 40, 41
R8, R28 Provide DC Bias. Optimal for 500 kHz+.
Remove T1 or T4. Used for low input frequencies.
Remove T1 or T4. JP5: connected for dc-coupled, not connected
for ac-coupling.
Table VI. Reference Jumper Configuration
Reference
Voltage
Jumpers
Notes
Internal
Internal
Internal
External
2 V
1 V
23
24
25
8, 22
JP8 Not Connected.
JP8 Not Connected.
JP8 Not Connected. VREF = 1 + R1/R2.
Set VREF with R26.
1 V ≤ VREF ≤ 2 V
1 V ≤ VREF ≤ 2 V
Table VII. Clock Jumper Configuration
Input Connector
Jumpers
DUT Clock
Differential
Single-Ended
S5
S1
11, 13
12, 15
Data Capture Clock
Internal
Diff DUT Clock
SE DUT Clock
External
NA
NA
S6
9, 18A
9, 18B
3 or 4
5V
5V
3V
3V
+
–
–
+
–
+
–
+
AVDD
GND DUT GND DUT
DVDD
SIGNAL SYNTHESIZER
AVDD
DVDD
2.5MHz
BAND-PASS FILTER
S4
INPUT
xFMR
REFIN
2.5MHz, 0.8V p-p
HP8644
AD9244
OUTPUT
BUSS
J1
DSP
EQUIPMENT
EVALUATION BOARD
S1/S5
INPUT
CLOCK
CLK SYNTHESIZER
65MHz, 1V p-p
HP8644
10MHz
REFOUT
CLOCK
DIVIDER
Figure 20. Evaluation Board Connections
REV. A
–23–
AD9244
C W
Figure 21. AD9244 Evaluation Board, ADC, External Reference, and Power Supply Circuitry
–24–
REV. A
AD9244
HEADER RIGHT ANGLE MALE NO EJECTORS
Figure 22. AD9244 Evaluation Board, Clock Input, and Digital Output Buffer Circuitry
REV. A
–25–
AD9244
AVDD
JP5
C7
0.1F
R40
1k⍀
SINGLE
INPUT
S3
C9
0.33F
R5
49.9⍀
R41
1k⍀
JP42
JP40
JP45
C15
10F
10V
C44
DNP
R21
33⍀
AVDD
AVDD
R32
VIN+
10k⍀
C24
20pF
SHEET 1
VIN–
R22
33⍀
JP45
JP41
JP43
C69
0.1F
C8
0.1F
R33
10k⍀
C43
DNP
R37
499⍀
3
R46
33⍀
4
V+
1
8
–IN
OUT+
R34
U2
AD8138
2
523⍀
V
AMP INPUT
OCM
OUT–
S2
+IN
R47
33⍀
V–
6
R35
499⍀
5
R31
49.9⍀
ADT4-6T
T4
1
3
P
S
6
5
4
R36
499⍀
AVDD
NC= 2
XFMRINPUT
S4
CW
T1-1TX65
NC = 5
T1
5
4
1
2
3
R28
2k⍀
P
S
R24
49.9⍀
C25
0.33F
C16
0.1F
R8
500⍀
Figure 23. AD9244 Evaluation Board, Analog Input Circuitry
–26–
REV. A
AD9244
Figure 24. AD9244 Evaluation Board, PCB Assembly, Top
REV. A
–27–
AD9244
Figure 25. AD9244 Evaluation Board, PCB Assembly, Bottom
–28–
REV. A
AD9244
Figure 26. AD9244 Evaluation Board, PCB Layer 1 (Top)
REV. A
–29–
AD9244
Figure 27. AD9244 Evaluation Board, PCB Layer 2 (Ground Plane)
–30–
REV. A
AD9244
Figure 28. AD9244 Evaluation Board, PCB Layer 3 (Power Plane)
REV. A
–31–
AD9244
Figure 29. AD9244 Evaluation Board, PCB Layer 4 (Bottom)
–32–
REV. A
AD9244
OUTLINE DIMENSIONS
8-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
0.75
0.60
0.45
9.00 BSC
SQ
1.60
MAX
37
48
36
1
PIN 1
SEATING
PLANE
10؇
6؇
2؇
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
VIEW A
7؇
3.5؇
0؇
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90؇ CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
REV. A
–33–
AD9244
Revision History
Location
Page
6/03—Data Sheet changed from REV. 0 to REV. A
Changes to AC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
–34–
REV. A
–35–
–36–
相关型号：
©2020 ICPDF网 联系我们和版权申明