AD9244_17 [ADI]
14-Bit, 40 MSPS/65 MSPS A/D Converter;
| 型号： | AD9244_17 |
| 厂家： | 
ADI |
| 描述： | 14-Bit, 40 MSPS/65 MSPS A/D Converter |
| 文件： | 总37页 (文件大小：996K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit, 40 MSPS/65 MSPS A/D Converter
AD9244
FUNCTIONAL BLOCK DIAGRAM
FEATURES
AVDD
REFT REFB
DRVDD
14-bit, 40 MSPS/65 MSPS ADC
Low power
550 mW at 65 MSPS
AD9244
VIN+
VIN–
DFS
OTR
300 mW at 40 MSPS
14
10-STAGE
PIPELINE ADC
SHA
On-chip reference and sample-and-hold
750 MHz analog input bandwidth
SNR > 73 dBc to Nyquist @ 65 MSPS
SFDR > 86 dBc to Nyquist @ 65 MSPS
Differential nonlinearity error = 0.7 LSB
Guaranteed no missing codes over full temperature range
1 V to 2 V p-p differential full-scale analog input range
Single 5 V analog supply, 3.3 V/5 V driver supply
Out-of-range indicator
CLK+
CLK–
DCS
OUTPUT
REGISTER
TIMING
14
D13 TO D0
OEB
REFERENCE
Straight binary or twos complement output data
Clock duty cycle stabilizer
Output-enable function
48-lead LQFP package
AGND CML
VR VREF SENSE REF DGND
GND
Figure 1.
APPLICATIONS
Fabricated on an advanced CMOS process, the AD9244 is
available in a 48-lead LQFP and is specified for operation over
the industrial temperature range (–40°C to +85°C).
Communication subsystems (microcell, picocell)
Medical and high-end imaging equipment
Test and measurement equipment
PRODUCT HIGHLIGHTS
1. Low Power—The AD9244, at 550 mW, consumes a fraction
of the power of currently available ADCs in existing high
speed solutions.
GENERAL DESCRIPTION
The AD9244 is a monolithic, single 5 V supply, 14-bit,
40 MSPS/65 MSPS ADC with an on-chip, high performance
sample-and-hold amplifier (SHA) and voltage reference.
2. IF Sampling—The AD9244 delivers outstanding
performance at input frequencies beyond the first Nyquist
zone. Sampling at 65 MSPS with an input frequency of
100 MHz, the AD9244 delivers 71 dB SNR and 86 dB SFDR.
3. Pin Compatibility—The AD9244 offers a seamless
migration from the 12-bit, 65 MSPS AD9226.
4. On-Board Sample-and-Hold (SHA)—The versatile SHA
input can be configured for either single-ended or
differential inputs.
5. Out-of-Range (OTR) Indicator—The OTR output bit
indicates when the input signal is beyond the AD9244’s
input range.
6. Single Supply—The AD9244 uses a single 5 V power
supply, simplifying system power supply design. It also
features a separate digital output driver supply to
accommodate 3.3 V and 5 V logic families.
The AD9244 uses a multistage differential pipelined architec-
ture with output error correction logic to provide 14-bit
accuracy at 40 MSPS/65 MSPS data rates, and guarantees no
missing codes over the full operating temperature range.
The AD9244 has an on-board, programmable voltage reference.
An external reference can also be used to suit the dc accuracy
and temperature drift requirements of the application.
A differential or single-ended clock input controls all internal
conversion cycles. The digital output data can be presented in
straight binary or in twos complement format. An out-of-range
(OTR) signal indicates an overflow condition that can be used
with the most significant bit to determine low or high overflow.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD9244* PRODUCT PAGE QUICK LINKS
Last Content Update: 09/27/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
TOOLS AND SIMULATIONS
• Visual Analog
• AD9244 IBIS Models
EVALUATION KITS
REFERENCE MATERIALS
• AD9244 Evaluation Board
Technical Articles
DOCUMENTATION
• Buffer Adapts Single-ended Signals for Differential Inputs
Application Notes
• Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• AN-345: Grounding for Low-and-High-Frequency Circuits
• DNL and Some of its Effects on Converter Performance
• Matching An ADC To A Transformer
• MS-2210: Designing Power Supplies for High Speed ADC
• AN-501: Aperture Uncertainty and ADC System
Performance
DESIGN RESOURCES
• AD9244 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• AN-737: How ADIsimADC Models an ADC
• AN-741: Little Known Characteristics of Phase Noise
• AN-742: Frequency Domain Response of Switched-
Capacitor ADCs
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
DISCUSSIONS
View all AD9244 EngineerZone Discussions.
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
SAMPLE AND BUY
Visit the product page to see pricing options.
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
• AN-835: Understanding High Speed ADC Testing and
Evaluation
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
Data Sheet
• AD9244: 14-Bit, 40/65 MSPS A/D Converter Data Sheet
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AD9244
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .......................................................................................9
Typical Application Circuits ......................................................... 11
Typical Performance Characteristics ........................................... 12
Theory of Operation ...................................................................... 17
Analog Input and Reference Overview................................... 17
Analog Input Operation............................................................ 18
Reference Operation .................................................................. 20
Digital Inputs and Outputs ....................................................... 21
Evaluation Board ............................................................................ 26
Analog Input Configuration..................................................... 26
Reference Configuration ........................................................... 26
Clock Configuration.................................................................. 26
Outline Dimensions....................................................................... 36
Ordering Guide .......................................................................... 36
Functional Block Diagram .............................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Absolute Maximum Ratings............................................................ 7
Explanation of Test Levels........................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
REVISION HISTORY
12/05—Rev. B to Rev. C
2/05—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Figure 45...................................................................... 19
Added Single-Ended Input Configuration Section.................... 19
Added Reference Decoupling Section ......................................... 25
Changes to Figure 65...................................................................... 28
Changes to Figure 66...................................................................... 29
Changes to Figure 67...................................................................... 30
Added Table 15 ............................................................................... 34
Updated Format..................................................................Universal
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Reformatted Table 5 ..........................................................................7
Changes to Table 6.............................................................................8
Changes to Figure 12...................................................................... 12
Changed Captions on Figure 18 and Figure 21.......................... 13
Changes to Figure 35, Figure 38, Figure 39................................. 16
Changes to Table 9.......................................................................... 18
Changes to Table 13 ....................................................................... 26
Changes to Ordering Guide.......................................................... 36
6/03—Rev. 0 to Rev. A
Changes to AC Specifications..........................................................3
Updated Ordering Guide .................................................................6
Updated Outline Dimensions....................................................... 33
6/02—Revision 0: Initial Version
Rev. C | Page 2 of 36
AD9244
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), differential clock inputs, VREF = 2 V, external reference,
differential analog inputs, unless otherwise noted.
Table 1.
Test
AD9244BST-65
Typ
AD9244BST-40
Min Typ
14
Parameter
Temp Level Min
Max
Max Unit
RESOLUTION
Full
VI
14
Bits
DC ACCURACY
No Missing Codes
Offset Error
Full
Full
Full
Full
25°C
Full
Full
VI
VI
VI
VI
V
Guaranteed
0.3
0.6
Guaranteed
0.3
0.6
Bits
1.4 % FSR
2.0 % FSR
1.0 LSB
LSB
1.4
2.0
1.0
Gain Error1
Differential Nonlinearity (DNL)2
0.7
1.4
0.6
1.3
Integral Nonlinearity (INL)2
V
LSB
VI
−4
+4
−4
+4
LSB
TEMPERATURE DRIFT
Offset Error
Full
Full
Full
V
V
V
2.0
2.3
25
2.0
2.3
25
ppm/°C
ppm/°C
ppm/°C
Gain Error (EXT VREF)1
Gain Error (INT VREF)3
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (2 VREF)
Load Regulation @ 1 mA
Output Voltage Error (1 VREF)
Load Regulation @ 0.5 mA
Input Resistance
INPUT REFERRED NOISE
VREF = 2 V
Full
Full
Full
Full
Full
VI
V
IV
V
2ꢀ
15
2ꢀ
15
mV
mV
mV
mV
kΩ
0.5
0.5
0.25
5
0.25
5
V
25°C
25°C
V
V
0.8
1.5
0.8
1.5
LSB rms
LSB rms
VREF = 1 V
ANALOG INPUT
Input Voltage Range (Differential)
VREF = 2 V
VREF = 1 V
Common-Mode Voltage
Input Capacitance4
Input Bias Current5
Analog Bandwidth (Full Power)
POWER SUPPLIES
Supply Voltages
Full
Full
Full
25°C
25°C
25°C
V
V
V
V
V
V
2
1
2
1
V p-p
V p-p
V
pF
μA
0.5
4
0.5
4
10
500
750
10
500
750
MHz
AVDD
DRVDD
Full
Full
IV
IV
4.75
2.7
5
5.25
5.25
4.75
2.7
5
5.25
5.25
V
V
Supply Current
IAVDD
IDRVDD
PSRR
Full
Full
Full
V
V
V
10ꢀ
12
0.05
64
8
0.05
mA
mA
% FSR
POWER CONSUMPTION
DC Input6
Sine Wave Input
Full
Full
V
VI
550
5ꢀ0
300
345
mW
mW
640
370
1 Gain error is based on the ADC only (with a fixed 2.0 V external reference).
2 Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Includes internal voltage reference error.
4 Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 7 for the equivalent analog input structure.
5 Input bias current is due to the input looking like a resistor that is dependent on the clock rate.
6 Measured with dc input at maximum clock rate.
Rev. C | Page 3 of 36
AD9244
AC SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), differential clock inputs, VREF = 2 V, external reference,
AIN = –0.5 dBFS, differential analog inputs, unless otherwise noted.
Table 2.
Test
AD9244BST-65
AD9244BST-40
Parameter
SNR1
fIN = 2.4 MHz
Temp
Level
Min
72.4
72.0
Typ
Max
Min
Typ
Max
Unit
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
IV
V
VI
I
IV
I
IV
V
V
V
73.4
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
74.8
73.7
75.3
fIN = 15.5 MHz (–1 dBFS)
fIN = 20 MHz
72.1
74.7
fIN = 32.5 MHz
70.8
6ꢀ.ꢀ
73.0
fIN = 70 MHz
72.2
71.2
67.2
fIN = 100 MHz
fIN = 200 MHz
SINAD1
72.8
68.3
fIN = 2.4 MHz
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
IV
I
IV
V
V
V
72.2
73.2
72
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
74.7
72.6
75.1
74.4
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
70.6
6ꢀ.7
71.ꢀ
71
5ꢀ.8
fIN = 100 MHz
fIN = 200 MHz
ENOB
72.4
56.3
fIN = 2.4 MHz
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
IV
I
IV
V
V
V
11.7
11.ꢀ
11.7
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
12.1
12.2
12.1
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
11.4
11.3
11.8
11.7
11.5
ꢀ.6
fIN = 100 MHz
fIN = 200 MHz
THD1
11.7
ꢀ.1
fIN = 2.4 MHz
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
IV
I
IV
V
V
V
−78.4
−80.7
−80.4
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−ꢀ0.0
−8ꢀ.7
−8ꢀ.4
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
−7ꢀ.2
−78.7
−84.6
−84.1
−83.0
−60.7
fIN = 100 MHz
fIN = 200 MHz
−83.2
−56.6
Rev. C | Page 4 of 36
AD9244
Test
AD9244BST-65
AD9244BST-40
Parameter
WORST HARMONIC (SECOND or THIRD)1
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
fIN = 2.4 MHz
fIN = 20 MHz
fIN = 32.5 MHz
fIN = 70 MHz
fIN = 100 MHz
25°C
25°C
25°C
25°C
25°C
25°C
V
V
V
V
V
V
−ꢀ4.5
−ꢀ3.7
−ꢀ2.8
dBc
dBc
dBc
dBc
dBc
dBc
−86.5
−86.1
−86.2
−60.7
−84.5
−56.6
fIN = 200 MHz
SFDR1
fIN = 2.4 MHz
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
25°C
VI
I
IV
V
IV
I
IV
I
IV
V
V
V
78.6
83
82.5
81.4
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
ꢀ4.5
ꢀ0
ꢀ3.7
ꢀ1.8
fIN = 15.5 MHz (–1 dBFS)
fIN = 20 MHz
fIN = 32.5 MHz
80.0
7ꢀ.5
86.4
fIN = 70 MHz
86.1
86.2
60.7
fIN = 100 MHz
fIN = 200 MHz
84.5
56.6
1 AC specifications can be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale).
DIGITAL SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, VREF = 2 V, external reference, unless otherwise noted.
Table 3.
Test
AD9244BST-65
AD9244BST-40
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic 1 Voltage (OEB, DRVDD = 3 V)
Logic 1 Voltage (OEB, DRVDD = 5 V)
Logic 0 Voltage (OEB)
Logic 1 Voltage (DFS, DCS)
Logic 0 Voltage (DFS, DCS)
Input Current
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
V
2
3.5
2
3.5
V
V
V
V
V
μA
pF
0.8
0.8
3.5
3.5
0.8
10
0.8
10
Input Capacitance
5
5
CLOCK INPUT PARAMETERS
Differential Input Voltage
CLK− Voltage1
Internal Clock Common-Mode
Single-Ended Input Voltage
Logic 1 Voltage
Logic 0 Voltage
Input Capacitance
Input Resistance
Full
Full
Full
IV
IV
V
0.4
0.25
0.4
0.25
V p-p
V
V
1.6
1.6
Full
Full
Full
Full
IV
IV
V
2
2
V
V
pF
kΩ
0.8
0.8
5
100
5
100
V
DIGITAL OUTPUTS (DRVDD = 5 V)
Logic 1 Voltage (IOH = 50 μA)
Logic 0 Voltage (IOL = 50 μA)
Logic 1 Voltage (IOH = 0.5 mA)
Logic 0 Voltage (IOL = 1.6 mA)
Full
Full
Full
Full
IV
IV
IV
IV
4.5
2.4
4.5
2.4
V
V
V
V
0.1
0.4
0.1
0.4
Rev. C | Page 5 of 36
AD9244
Test
Level
AD9244BST-65
Typ Max
AD9244BST-40
Typ Max
Parameter
Temp
Min
2.ꢀ5
2.8
Min
2.ꢀ5
2.8
Unit
DIGITAL OUTPUTS (DRVDD = 3 V)2
Logic 1 Voltage (IOH = 50 μA)
Logic 0 Voltage (IOL = 50 μA)
Logic 1 Voltage (IOH = 0.5 mA)
Logic 0 Voltage (IOL = 1.6 mA)
Full
Full
Full
Full
IV
IV
IV
IV
V
V
V
V
0.05
0.4
0.05
0.4
1 See the Clock Overview section for more details.
2 Output voltage levels measured with 5 pF load on each output.
SWITCHING SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, unless otherwise noted.
Table 4.
Test
AD9244BST-65
AD9244BST-40
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
Clock Period1
Clock Pulse Width High2
Clock Pulse Width Low2
Clock Pulse Width High3
Clock Pulse Width Low3
Full
Full
Full
Full
Full
Full
Full
VI
V
V
V
V
V
V
65
40
MHz
kHz
ns
ns
ns
500
500
15.4
4
4
6.ꢀ
6.ꢀ
25
4
4
11.3
11.3
ns
ns
DATA OUTPUT PARAMETERS
4
Output Delay (tPD
)
Full
Full
Full
Full
Full
Full
V
V
V
V
V
V
3.5
7
3.5
7
ns
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Output Enable Delay
8
8
Clock cycles
ns
ps rms
ns
1.5
0.3
15
2
1.5
0.3
15
1
OUT-OF-RANGE RECOVERY TIME
Clock cycles
1 The clock period can be extended to 2 μs with no degradation in specified performance at 25°C.
2 With duty cycle stabilizer enabled.
3 With duty cycle stabilizer disabled.
4 Measured from clock 50% transition to data 50% transition with 5 pF load on each output.
N + 3
N + 2
N + 1
N + 4
N
N + 5
ANALOG INPUT
N + 6
N + 9
N + 7
N + 8
tA
CLOCK
DATA OUT N – 9
N – 8
N – 7
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
N + 1
tPD
Figure 2. Input Timing
Rev. C | Page 6 of 36
AD9244
ABSOLUTE MAXIMUM RATINGS
Table 5.
With
Respect to
Parameter
ELECTRICAL
AVDD
DRVDD
AGND
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
AGND
DGND
DGND
DRVDD
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DGND
DGND
DGND
–0.3 V to +6.5 V
−0.3 V to +6.5 V
–0.3 V to +0.3 V
–6.5 V to +6.5 V
AVDD
REFGND
CLK+, CLK–, DCS
DFS
VIN+, VIN–
VREF
SENSE
REFB, REFT
CML
VR
OTR
D0 to D13
OEB
–0.3 V to +0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to AVDD + 0.3 V
–0.3 V to DRVDD + 0.3 V
–0.3 V to DRVDD + 0.3 V
–0.3 V to DRVDD + 0.3 V
EXPLANATION OF TEST LEVELS
Table 6.
Test
Level Description
I
100% production tested.
II
100% production tested at 25°C and sample tested at
specified temperatures.
III
Sample tested only.
IV
Parameter is guaranteed by design and characterization
testing.
ENVIRONMENTAL1
V
Parameter is a typical value only.
Junction Temperature
Storage Temperature
Operating Temperature
Lead Temperature (10 sec)
150°C
VI
100% production tested at 25°C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature extremes
for military devices.
−65°C to +150°C
−40°C to +85°C
300°C
1 Typical thermal impedances; θJA = 50.0°C/W; θJC = 17.0°C/W. These
measurements were taken on a 4-layer board in still air, in accordance with
EIA/JESD51-7.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 7 of 36
AD9244
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
AGND
SENSE
DFS
PIN 1
2
AGND
3
4
AVDD
AVDD
AGND
CLK–
CLK+
NIC
AVDD
AGND
AGND
AVDD
DGND
DRVDD
OTR
5
AD9244
TOP VIEW
(Not to Scale)
6
7
8
9
OEB
10
11
12
D0 (LSB)
D1
D13 (MSB)
D12
D2
D11
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 5, 32, 33
AGND
Analog Ground.
3, 4, 31, 34
AVDD
CLK–, CLK+
NIC
OEB
D0 (LSB)
D1 to D3,
D4 to Dꢀ,
D10 to D12
Analog Supply Voltage.
Differential Clock Inputs.
No Internal Connection.
Digital Output Enable (Active Low).
Least Significant Bit, Digital Output.
Digital Outputs.
6, 7
8, 44
ꢀ
10
11 to 13,
16 to 21,
24 to 26
14, 22, 30
15, 23, 2ꢀ
27
28
35
36
37
DGND
DRVDD
D13 (MSB)
OTR
DFS
SENSE
VREF
Digital Ground.
Digital Supply Voltage.
Most Significant Bit, Digital Output.
Out-of-Range Indicator (Logic 1 Indicates OTR).
Data Format Select. Connect to AGND for straight binary, AVDD for twos complement.
Internal Reference Control.
Internal Reference.
38
3ꢀ to 42
43
REFGND
REFB, REFT
DCS
Reference Ground.
Internal Reference Decoupling.
50% Duty Cycle Stabilizer. Connect to AVDD to activate 50% duty cycle stabilizer, AGND for
external control of both clock edges.
45
46, 47
48
CML
VIN+, VIN–
VR
Common-Mode Reference (0.5 × AVDD).
Differential Analog Inputs.
Internal Bias Decoupling.
Rev. C | Page 8 of 36
AD9244
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
IF Sampling
Due to the effects of aliasing, an ADC is not necessarily limited
to Nyquist sampling. Higher sampled frequencies are aliased
down into the first Nyquist zone (DC − fCLOCK/2) on the output
of the ADC. Care must be taken that the bandwidth of the sam-
pled signal does not overlap Nyquist zones and alias onto itself.
Nyquist sampling performance is limited by the bandwidth of
the input SHA and clock jitter (noise caused by jitter increases
as the input frequency increases).
Aperture Delay
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Integral Nonlinearity (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each particular code to the true straight line.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage must be applied to the
converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the input phase 180° and taking the peak measurement again. The
difference is then found between the two peak measurements.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Nyquist Sampling
When the frequency components of the analog input are below
the Nyquist frequency (fCLOCK/2).
Dual-Tone SFDR1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Effective Number of Bits (ENOB)
The ENOB for a device for sine wave inputs at a given input
frequency can be calculated directly from its measured SINAD by
Power Supply Rejection Ratio (PSRR)
The change in full scale from the value with the supply at its
minimum limit to the value with the supply at its maximum limit.
N = (SINAD − 1.76)/6.02
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last code transition should occur
at an analog value 1½ LSB below the nominal full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Signal-to-Noise-and-Distortion (SINAD)1
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist
frequency, including harmonics, but excluding dc.
Signal-to-Noise Ratio (SNR)1
Common-Mode Rejection Ratio (CMRR)
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Common-mode (CM) signals appearing on VIN+ and VIN–
are ideally rejected by the differential front end of the ADC.
With a full-scale CM signal driving both VIN+ and VIN–,
CMRR is the ratio of the amplitude of the full-scale input CM
signal to the amplitude of signal that is not rejected, expressed
in dBFS.1
Rev. C | Page ꢀ of 36
AD9244
Spurious-Free Dynamic Range (SFDR)1
Total Harmonic Distortion (THD)1
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
Temperature Drift
Offset Error
The temperature drift for offset error and gain error specifies
the maximum change from initial (25°C) value to the value at
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
TMIN or TMAX.
1 AC specifications can be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. C | Page 10 of 36
AD9244
TYPICAL APPLICATION CIRCUITS
DRVDD DRVDD
AVDD
DGND
AGND
Figure 4. D0 to D13, OTR
Figure 7. VIN+, VIN−
AVDD
DRVDD
200Ω
200Ω
DGND
AGND
Figure 5. Three-State (OEB)
Figure 8. DFS, DCS, SENSE
AVDD
AVDD
200Ω
CLK
BUFFER
AGND
AGND
Figure 6. CLK+, CLK−
Figure 9. VREF, REFT, REFB, VR, CML
Rev. C | Page 11 of 36
AD9244
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK duty cycle stabilizer enabled, TA = 25°C, differential analog input, common-
mode voltage (VCM) = 2.5 V, input amplitude (AIN) = −0.5 dBFS, VREF = 2.0 V external, FFT length = 8K, unless otherwise noted.
0
100
90
80
70
60
50
40
SNR = 74.8dBc
SFDR = 93.6dBc
–20
SFDR (dBFS)
SFDR (dBc)
–40
SNR (dBFS)
–60
SFDR = 90dBc
REFERENCE LINE
SNR (dBc)
–80
–100
–120
0
5
10
15
20
25
30 32.5
–30
–25
–20
–15
–10
–5
0
0
0
FREQUENCY (MHz)
A
(dBFS)
IN
Figure 13. Single-Tone SNR/SFDR vs. AIN, fIN = 5 MHz
Figure 10. Single-Tone FFT, fIN = 5 MHz
100
90
80
70
60
50
40
0
–20
SNR = 74.0dBc
SFDR = 87.0dBc
SFDR (dBFS)
–40
SNR (dBFS)
SFDR (dBc)
–60
SFDR = 90dBc
REFERENCE LINE
–80
–100
–120
SNR (dBc)
30
–25
–20
–15
–10
–5
0
5.0
10.0
15.0
20.0
25.0
30.0 32.5
A
(dBFS)
FREQUENCY (MHz)
IN
Figure 11. Single-Tone FFT, fIN = 31 MHz
Figure 14. Single-Tone SNR/SFDR vs. AIN, fIN = 31 MHz
0
–20
100
90
80
70
60
50
40
SNR = 66.5dBc
SFDR = 74.0dBc
SFDR (dBFS)
–40
SNR (dBFS)
SFDR (dBc)
–60
SFDR = 90dBc
REFERENCE LINE
–80
SNR (dBc)
–100
–120
0
5
10
15
20
25
30
–30
–25
–20
–15
–10
–5
FREQUENCY (MHz)
A
(dBFS)
IN
Figure 15. Single-Tone SNR/SFDR vs. AIN, fIN = 190 MHz, fSAMPLE = 61.44 MSPS
Figure 12. Single-Tone FFT, fIN = 190 MHz, fSAMPLE = 61.44 MSPS
Rev. C | Page 12 of 36
AD9244
75
73
71
69
67
65
75
73
71
69
67
65
12.2
11.9
11.5
11.2
10.8
10.5
2V SPAN
2V SPAN
1V SPAN
1V SPAN
0
20
40
60
80
100
120
140
0
0
0
20
20
20
40
60
80
100
120
140
140
140
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 16. SINAD/ENOB vs. Input Frequency
Figure 19. SNR vs. Input Frequency
–100
–95
–90
–85
–80
–75
100
95
90
85
80
75
1V SPAN
1V SPAN
2V SPAN
2V SPAN
100
0
20
40
60
80
120
140
40
60
80
100
120
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 20. SFDR vs. Input Frequency
Figure 17. THD vs. Input Frequency
–92
–90
–88
–86
–84
–82
–80
–78
–76
–74
77
75
73
71
69
67
+25°C
–40°C
+25°C
–40°C
+85°C
+85°C
40
60
80
100
120
0
20
40
60
80
100
120
140
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure 21. THD vs. Temperature and Input Frequency, DCS Disabled
Figure 18. SNR vs. Temperature and Input Frequency, DCS Disabled
Rev. C | Page 13 of 36
AD9244
–100
–95
–90
–85
–80
100
95
90
85
80
75
60
65
60
FOURTH
HARMONIC
SFDR, DCS ON
THIRD
HARMONIC
SFDR, DCS OFF
SNR, DCS ON
SECOND
HARMONIC
SNR, DCS OFF
–75
0
20
40
60
80
100
120
140
30
35
40
45
50
55
60
65
70
INPUT FREQUENCY (MHz)
DUTY CYCLE (%)
Figure 22. Harmonics vs. Input Frequency
Figure 25. SNR/SFDR vs. Duty Cycle, fIN = 2.5 MHz
76
75
74
73
72
71
12.33
12.17
12.00
11.83
11.67
11.50
11.34
100
96
92
88
84
80
fIN = 2MHz
fIN = 2MHz
fIN = 10MHz
fIN = 10MHz
fIN = 20MHz
fIN = 20MHz
70
0
20
40
60
80
100
0
20
40
60
80
100
SAMPE RATE (MSPS)
SAMPLE RATE (MSPS)
Figure 23. SINAD/ENOB vs. Sample Rate
Figure 26. SFDR vs. Sample Rate
1.5
1.0
1.0
0.8
0.6
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
0
4096
8192
12288
16384
0
4096
8192
12288
16384
CODES (14-Bit)
CODES (14-Bit)
Figure 24. Typical INL
Figure 27. Typical DNL
Rev. C | Page 14 of 36
AD9244
0
–20
100
90
80
70
60
50
40
SNR = 67.5dBc
SFDR = 93.2dBc
SFDR (dBFS)
SFDR (dBc)
–40
SNR (dBFS)
–60
SFDR = 90dBc
REFERENCE LINE
–80
SNR (dBc)
–100
–120
0
5.0
10.0
15.0
20.0
25.0
30.0 32.5
–30
–25
–20
–15
(dBFS)
–10
–5
–5
–5
FREQUENCY (MHz)
A
IN
Figure 28. Dual-Tone FFT with fIN−1 = 44.2 MHz and
fIN−2 = 45.6 MHz (AIN1 = AIN2 = –6.5 dBFS)
Figure 31. Dual-Tone SNR/SFDR vs. AIN with
fIN−1 = 44.2 MHz and fIN−2 = 45.6 MHz
0
20
100
90
80
70
60
50
40
SNR = 67.0dBc
SFDR = 78.2dBc
SFDR (dBFS)
40
SNR (dBFS)
SFDR (dBc)
60
SFDR = 90dBc
REFERENCE LINE
80
100
120
SNR (dBc)
0
5.0
10.0
15.0
20.0
25.0
30.0 32.5
–30
–25
–20
–15
(dBFS)
–10
FREQUENCY (MHz)
A
IN
Figure 29. Dual-Tone FFT with fiN−1 = 69.2 MHz and
fIN−2 = 70.6 MHz (AIN1 = AIN2 = –6.5 dBFS)
Figure 32. Dual-Tone SNR/SFDR vs. AIN with
fIN−1 = 69.2 MHz and= fIN−2 = 70.6 MHz
0
–20
100
90
80
70
60
50
40
SNR = 65.0dBc
SFDR = 69.1dBc
SFDR (dBFS)
–40
SNR (dBFS)
–60
SFDR (dBc)
SFDR = 90dBc
REFERENCE LINE
–80
–100
–120
SNR (dBc)
0
5.0
10.0
15.0
20.0
25.0
30.0 32.5
–30
–25
–20
–15
(dBFS)
–10
FREQUENCY (MHz)
A
IN
Figure 30. Dual-Tone FFT with fIN−1 = 139.2 MHz and
fIN−2 = 140.7 MHz (AIN1 = AIN2 = –6.5 dBFS)
Figure 33. Dual-Tone SNR/SFDR vs. AIN with
fIN−1 = 139.2 MHz and fIN−2 = 140.7 MHz
Rev. C | Page 15 of 36
AD9244
0
100
90
80
70
60
50
40
SNR = 62.6dBc
SFDR = 60.7dBc
–20
SFDR (dBFS)
–40
SNR (dBFS)
–60
SFDR (dBc)
–80
SFDR = 90dBc
REFERENCE LINE
–100
SNR (dBc)
–25
–120
0
5
10
15
20
25
30.0 32.5
–30
–20
–15
(dBFS)
–10
–5
FREQUENCY (MHz)
A
IN
Figure 34. Dual-Tone with fIN−1 = 239.1 MHz and
fIN−2 = 240.7 MHz (AIN−1 = AIN−2 = –6.5 dBFS)
Figure 37. Dual-Tone SNR/SFDR vs. AIN with
fIN−1 = 239.1 MHz and fIN−2 = 240.7 MHz
0
–10
–20
–30
–40
–50
–60
100
95
90
85
80
75
70
65
60
55
50
SNR = 71.3dBc
THD = –90.8dBc
SFDR (dBFS)
SNR (dBFS)
SFDR = 90dBc
REFERENCE LINE
SFDR (dBc)
NOTE: SPUR FLOOR
BELOW 90dBFS @ 240MHz
–70
–80
–90
–100
–110
–120
SNR (dBc)
0
5
10
15
20
25
30
–21
–18
–15
–12
–9
(dBFS)
–6
–3
0
FREQUENCY (MHz)
A
IN
Figure 35. Driving ADC Inputs with Transformer and Balun,
fIN = 240 MHz, AIN = –8.5 dBFS
Figure 38. Driving ADC Inputs with Transformer and
Balun SNR/SFDR vs. AIN, fIN = 240 MHz
105
95
90
85
80
75
70
65
60
55
SFDR (dBFS)
SFDR (dBc)
100
95
90
85
80
75
70
65
SFDR = 90dBc
REFERENCE LINE
SNR (dBFS)
SNR (dBc)
0
50
100
150
200
250
–21
–18
–15
–12
–9
–6
–3
0
INPUT FREQUENCY (MHz)
A
(dBFS)
IN
Figure 39. Driving ADC Inputs with Transformer and
Balun SNR/SFDR vs. AIN, fIN = 190 MHz
Figure 36. CMRR vs. Input Frequency (AIN = 0 dBFS and CML = 2.5 V)
Rev. C | Page 16 of 36
AD9244
THEORY OF OPERATION
2.5V
1.5V
The AD9244 is a high performance, single-supply 14-bit ADC.
In addition to high dynamic range Nyquist sampling, it is
designed for excellent IF undersampling performance with an
analog input as high as 240 MHz.
AD9244
VIN+
33Ω
50V
20pF
0.1μF
REFT
REFB
VIN–
33Ω
+
0.1μF
0.1μF
10μF
The AD9244 uses a calibrated 10-stage pipeline architecture
with a patented, wideband, input sample-and-hold amplifier
(SHA) implemented on a cost-effective CMOS process. Each
stage of the pipeline, excluding the last, consists of a low resolu-
tion flash ADC along with a switched capacitor DAC and
interstage residue amplifier (MDAC). The MDAC amplifies the
difference between the reconstructed DAC output and the flash
input for the next stage in the pipeline. One bit of redundancy is
used in each of the stages to facilitate digital correction of flash
errors. The last stage simply consists of a flash ADC.
2V
VREF
2.5V
1.5V
+
10μF
0.1μF
SENSE
REFGND
Figure 40. 2 V p-p Differential Input, Common-Mode Voltage = 2 V
3.0V
AD9244
2.0V
33Ω
VIN+
20pF
0.1μF
REFT
REFB
VIN–
33Ω
+
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. While the converter cap-
tures a new input sample every clock cycle, it takes eight clock
cycles for the conversion to be fully processed and appear at the
output, as illustrated in Figure 2. This latency is not a concern
in many applications. The digital output, together with the OTR
indicator, is latched into an output buffer to drive the output
pins. The output drivers of the AD9244 can be configured to
interface with 5 V or 3.3 V logic families.
0.1μF
0.1μF
10μF
2V
VREF
+
10μF
0.1μF
SENSE
REFGND
Figure 41. 2 V p-p Single-Ended Input, Common-Mode Voltage = 2 V
AD9244
2.5V
0.1pF
3.0V
2.0V
33Ω
33Ω
VIN+
The AD9244 has a duty clock stabilizer (DCS) that generates its
own internal falling edge to create an internal 50% duty cycle
clock, independent of the externally applied duty cycle. Control
of straight binary or twos complement output format is accom-
plished with the DFS pin.
50Ω
20pF
0.1μF
0.1μF
0.1μF
REFT
REFB
VIN–
+
10μF
2V
VREF
3.0V
2.0V
+
10μF
0.1μF
SENSE
The ADC samples the analog input on the rising edge of the
clock. While the clock is low, the input SHA is in sample mode.
When the clock transitions to a high logic level, the SHA goes
into the hold mode. System disturbances just prior to or imme-
diately after the rising edge of the clock and/or excessive clock
jitter can cause the SHA to acquire the wrong input value and
should be minimized.
REFGND
Figure 42. 2 V p-p Differential Input, Common-Mode Voltage = 2.5 V
Figure 43 is a simplified model of the AD9244 analog input,
showing the relationship between the analog inputs, VIN+,
VIN–, and the reference voltage, VREF. Note that this is only a
symbolic model and that no actual negative voltages exist inside
the AD9244. Similar to the voltages applied to the top and bot-
tom of the resistor ladder in a flash ADC, the value VREF/2
defines the minimum and maximum input voltages to the
ADC core.
ANALOG INPUT AND REFERENCE OVERVIEW
The differential input span of the AD9244 is equal to the poten-
tial at the VREF pin. The VREF potential can be obtained from
the internal AD9244 reference or an external source.
AD9244
In differential applications, the center point of the input span is
the common-mode level of the input signals. In single-ended
applications, the center point is the dc potential applied to one
input pin while the signal is applied to the opposite input pin.
Figure 40 to Figure 42 show various system configurations.
+VREF/2
VIN+
V
14
CORE
ADC
CORE
+
–
VIN–
–VREF/2
Figure 43. Equivalent Analog Input of AD9244
Rev. C | Page 17 of 36
AD9244
The range of valid inputs for VIN+ and VIN− is any combination
that satisfies Equation 2, Equation 3, and Equation 4.
A differential input structure allows the user to easily configure the
inputs for either single-ended or differential operation. The ADC’s
input structure allows the dc offset of the input signal to be varied
independent of the input span of the converter. Specifically, the
input to the ADC core can be defined as the difference of the
voltages applied at the VIN+ and VIN– input pins.
For additional information showing the relationship between
VIN+, VIN–, VREF, and the analog input range of the AD9244,
see Table 8 and Table 9.
ANALOG INPUT OPERATION
Therefore, the equation
Figure 44 shows the equivalent analog input of the AD9244,
which consists of a 750 MHz differential SHA. The differential
input structure of the SHA is flexible, allowing the device to be
configured for either a differential or single-ended input. The
analog inputs VIN+ and VIN– are interchangeable, with the
exception that reversing the inputs to the VIN+ and VIN– pins
results in a data inversion (complementing the output word).
V
CORE = (VIN+) – (VIN−)
(1)
defines the output of the differential input stage and provides
the input to the ADC core. The voltage, VCORE, must satisfy the
condition
−VREF/2 < VCORE < VREF/2
(2)
where VREF is the voltage at the VREF pin.
S
In addition to the limitations placed on the input voltages VIN+
and VIN– by Equation 1 and Equation 2, boundaries on the
inputs also exist based on the power supply voltages according
to the conditions
S
C
C
C
C
S
H
H
VIN+
VIN–
C
C
S
PIN, PAR
H
S
AGND − 0.3 V < VIN+ < AVDD + 0.3 V
AGND − 0.3 V < VIN− < AVDD + 0.3 V
(3)
(4)
PIN, PAR
where:
S
AGND is nominally 0 V.
AVDD is nominally 5 V.
Figure 44. Analog Input of AD9244 SHA
Table 8. Analog Input Configuration Summary
Input
Input
Input Range (V)
Input CM
Voltage (V)
1.0
Connection
Single-Ended
Coupling Span (V) VIN+1
VIN−1
Comments
DC or AC
1.0
2.0
0.5 to 1.5
1 to 3
1.0
2.0
Best for stepped input response applications.
2.0
Optimum noise performance for single-ended
mode often requires low distortion op amp
with VCC > 5 V due to its headroom issues.
Differential
DC or AC
1.0
2.0
2.25 to 2.75
2.0 to 3.0
2.75 to 2.25
3.0 to 2.0
2.5
2.5
Optimum full-scale THD and SFDR performance
well beyond the ADC’s Nyquist frequency.
Optimum noise performance for differential
mode. Preferred mode for applications.
1VIN+ and VIN− can be interchanged if data inversion is required.
Table 9. Reference Configuration Summary
Reference Operating Mode
Connect
SENSE
SENSE
R1
R2
SENSE
VREF
To
Resulting VREF (V)
Input Span (VIN+ − VIN−) (V p-p)
Internal
Internal
Internal
VREF
AGND
VREF and SENSE
SENSE and REFGND
AVDD
1
2
1
2
1 ≤ VREF ≤ 2.0
VREF = (1 + R1/R2)
1 ≤ VREF ≤ 2.0
1 ≤ SPAN ≤ 2
(SPAN = VREF)
SPAN = EXTERNAL REF
External
EXTERNAL REF
Rev. C | Page 18 of 36
AD9244
Differentially Driving the Analog Inputs
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (that is, 2 V input span) and matched
input impedance for VIN+ and VIN–. Only a slight degradation
in dc linearity performance exists between the 2 V and 1 V
input spans; however, the SNR is lower in the 1 V input span.
The AD9244 has a very flexible input structure, allowing it to
interface with single-ended or differential inputs.
The optimum mode of operation, analog input range, and associ-
ated interface circuitry is determined by the particular application’s
performance requirements as well as power supply options.
When the ADC is driven by an op amp and a capacitive load is
switched onto the output of the op amp, the output momentar-
ily drops due to its effective output impedance. As the output
recovers, ringing can occur. To remedy the situation, a series
resistor, RS, can be inserted between the op amp and the SHA
input, as shown in Figure 45. A shunt capacitance also acts like
a charge reservoir, sinking or sourcing the additional charge
required by the sampling capacitor, CS, further reducing current
transients seen at the op amp’s output.
Differential operation requires that VIN+ and VIN− be
simultaneously driven with two equal signals that are 180°out of
phase with each other.
Differential modes of operation (ac-coupled or dc-coupled input)
provide the best SFDR performance over a wide frequency range.
They should be considered for the most demanding spectral-
based applications; that is, direct IF conversion to digital.
Because not all applications have a signal precondition for
differential operation, there is often a need to perform a single-
ended-to-differential conversion. In systems that do not require
dc coupling, an RF transformer with a center tap is the best
method for generating differential input signals for the AD9244.
This provides the benefit of operating the ADC in the differen-
tial mode without contributing additional noise or distortion.
An RF transformer also has the added benefit of providing
electrical isolation between the signal source and the ADC.
V
CC
R
33Ω
S
AD9244
VIN+
C
S
20pF
VIN–
V
EE
R
33Ω
S
0.1μF
5Ω
VREF
+
10μF
0.1μF
SENSE
REFCOM
The differential input characterization was performed using the
configuration in Figure 46. The circuit uses a Mini-Circuits® RF
transformer, model T1-1T, which has an impedance ratio of 1:1.
This circuit assumes that the signal source has a 50 Ω source
impedance. The secondary center tap of the transformer allows
a dc common-mode voltage to be added to the differential input
signal. In Figure 46, the center tap is connected to a resistor
divider providing a half supply voltage. It could also be
connected to the CML pin of the AD9244. For IF sampling
applications (70 MHz < fIN < 200 MHz), it is recommended that
the 20 pF differential capacitor between VIN+ and VIN− be
reduced or removed.
Figure 45. Resistors Isolating SHA Input from Op Amp
The optimum size of this resistor is dependent on several
factors, including the ADC sampling rate, the selected op amp,
and the particular application. In most applications, a 30 Ω to
100 Ω resistor is sufficient.
For noise-sensitive applications, the very high bandwidth of the
AD9244 can be detrimental, and the addition of a series resistor
and/or shunt capacitor can help limit the wideband noise at the
ADC’s input by forming a low-pass filter. The source impedance
driving VIN+ and VIN− should be matched. Failure to provide
matching can result in degradation of the SNR, THD, and SFDR
performance.
AVDD
R
33Ω
S
1kΩ
AD9244
VIN+
Single-Ended Input Configuration
0.1μF
0.1μF
0.1μF
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, there is
degradation in distortion performance due to large input
common-mode swing. However, if the source impedances on
each input are matched, there should be little effect on SNR
performance.
REFT
+
50Ω
20pF
10μF
0.1μF
1kΩ
REFB
VIN–
MINI-CIRCUITS
T1–1T
R
S
33Ω
Figure 46. Transformer-Coupled Input
The internal reference can be used to drive the inputs. Figure 45
shows an example of VREF driving VIN−. In this operating
mode, a 5 Ω resistor and a 0.1 μF capacitor must be connected
between VREF and VIN−, as shown in Figure 45, to limit the
reference noise sampled by the analog input.
Rev. C | Page 1ꢀ of 36
AD9244
The actual reference voltages used by the internal circuitry of
the AD9244 appear on the REFT and REFB pins. The voltages
on these pins are symmetrical about midsupply or CML. For
proper operation, it is necessary to add a capacitor network to
decouple these pins. Figure 49 shows the recommended
decoupling network. The turn-on time of the reference voltage
appearing between REFT and REFB is approximately 10 ms and
should be taken into consideration in any power-down mode of
operation. The VREF pin should be bypassed to the REFGND
pin with a 10 μF tantalum capacitor in parallel with a low
inductance 0.1 μF ceramic capacitor.
The circuit in Figure 47 shows a method for applying a differential,
direct-coupled signal to the AD9244. An AD8138 amplifier is used
to derive a differential signal from a single-ended signal.
10μF
+
5V
10
μ
F
F
0.1μF
0.1μF
+
10μ
1kΩ 1kΩ
AVDD
VIN+
499Ω
33Ω
1V p-p
0V
0.1μF
475Ω
499Ω
REFT
+
0.1μF
0.1μF
10μF
0.1μF
AD8138
499Ω
AD9244
20pF
VREF
REFT
50Ω
REFB
+
+
1
10μF
0.1μF
0.1μF
10μF
AD9244
VIN–
33Ω
REFGND REFB
0.1μF
1
LOCATE AS CLOSE AS POSSIBLE TO REFT/REFB PINS.
Figure 47. Direct-Coupled Drive Circuit with AD8138 Differential Op Amp
Figure 49. Reference Decoupling
REFERENCE OPERATION
Pin-Programmable Reference
The AD9244 contains a band gap reference that provides a pin-
strappable option to generate either a 1 V or 2 V output. With
the addition of two external resistors, the user can generate
reference voltages between 1 V and 2 V. Another alternative is
to use an external reference for designs requiring enhanced
accuracy and/or drift performance, as described later in this
section. Figure 48 shows a simplified model of the internal
voltage reference of the AD9244. A reference amplifier buffers a
1 V fixed reference. The output from the reference amplifier,
A1, appears on the VREF pin. As stated earlier, the voltage on
the VREF pin determines the full-scale differential input span
of the ADC.
By shorting the VREF pin directly to the SENSE pin, the inter-
nal reference amplifier is placed in a unity gain mode, and the
resulting VREF output is 1 V. By shorting the SENSE pin directly to
the REFGND pin, the internal reference amplifier is configured
for a gain of 2, and the resulting VREF output is 2 V.
Resistor-Programmable Reference
Figure 50 shows an example of how to generate a reference
voltage other than 1.0 V or 2.0 V with the addition of two
external resistors. Use the equation
VREF = 1 V × (1 + R1/R2)
(5)
AD9244
TO
to determine the appropriate values for R1 and R2. These resistors
should be in the 2 kΩ to 10 kΩ range. For the example shown, R1
equals 2.5 kΩ and R2 equals 5 kΩ. From the previous equation, the
resulting reference voltage on the VREF pin is 1.5 V. This sets the
differential input span to 1.5 V p-p. The midscale voltage can also
be set to VREF by connecting VIN− to VREF.
ADC
REFT
A2
2.5V
REFB
VREF
AD9244
VIN+
A1
3.25V
1.75V
33Ω
1V
R
R
20pF
0.1μF
2.5V
VIN–
REFT
REFB
33Ω
SENSE
1.5V
+
VREF
0.1μF
0.1μF
10μF
DISABLE
A1
+
R1
2.5kΩ
R2
5kΩ
10μF
0.1μF
LOGIC
SENSE
REFGND
REFGND
Figure 48. Equivalent Reference Circuit
Figure 50. Resistor-Programmable Reference
(1.5 V p-p Input Span, Differential Input with VCM = 2.5 V)
The voltage appearing at the VREF pin and the state of the
internal reference amplifier, A1, are determined by the voltage
present at the SENSE pin. The logic circuitry contains compara-
tors that monitor the voltage at the SENSE pin. The various
reference modes are summarized in Table 9 and are described
in the next few sections.
Rev. C | Page 20 of 36
AD9244
Using an External Reference
Digital Outputs
To use an external reference, the internal reference must be dis-
abled by connecting the SENSE pin to AVDD. The AD9244
contains an internal reference buffer, A2 (see Figure 48), that
simplifies the drive requirements of an external reference. The
external reference must be able to drive a 5 kΩ ( 20%) load.
The bandwidth of the reference is deliberately left small to
minimize the reference noise contribution. As a result, it is not
possible to drive VREF externally with high frequencies.
Table 10 details the relationship among the ADC input, OTR,
and digital output format.
Data Format Select (DFS)
The AD9244 can be programmed for straight binary or twos
complement data on the digital outputs. Connect the DFS pin to
AGND for straight binary and to AVDD for twos complement.
Digital Output Driver Considerations
Figure 51 shows an example of an external reference driving
both VIN– and VREF. In this case, both the common-mode
voltage and input span are directly dependent on the value of
VREF. Both the input span and the center of the input span are
equal to the external VREF. Thus, the valid input range extends
from (VREF + VREF/2) to (VREF − VREF/2). For example, if
the Precision Reference Part REF191, a 2.048 V external refer-
ence, is used, the input span is 2.048 V. In this case, 1 LSB of the
AD9244 corresponds to 0.125 mV.
The AD9244 output drivers can be configured to interface with
5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V,
respectively. The output drivers are sized to provide sufficient
output current to drive a wide variety of logic families.
However, large drive currents tend to cause glitches on the
supplies and can affect converter performance. Applications
requiring the ADC to drive large capacitive loads or large
fanouts can require external buffers or latches.
It is essential that a minimum of a 10 μF capacitor, in parallel
with a 0.1 μF low inductance ceramic capacitor, decouple the
reference output to AGND.
AD9244
VIN+
VREF + VREF/2
33Ω
VREF – VREF/2
20pF
0.1μF
VREF
5V
REFT
REFB
VIN–
+
33Ω
+
0.1μF
10μF
0.1μF
0.1μF
10μF
VREF
0.1μF
AVDD
SENSE
Figure 51. Using an External Reference
DIGITAL INPUTS AND OUTPUTS
Table 10. Output Data Format
Input (V)
Condition (V)
< –VREF/2 − 0.5 LSB
= −VREF/2
Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
OTR
VIN+ – VIN−
VIN+ – VIN−
VIN+ – VIN−
VIN+ – VIN−
VIN+ – VIN−
1
0
0
0
1
= 0
= +VREF/2 − 1.0 LSB
> +VREF/2 − 0.5 LSB
Rev. C | Page 21 of 36
AD9244
Out of Range (OTR)
Digital Output Enable Function (OEB)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OTR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OTR has the same pipe-
line latency as the digital data. OTR is low when the analog
input voltage is within the analog input range and high when
the analog input voltage exceeds the input range, as shown in
Figure 52. OTR remains high until the analog input returns to
within the input range and another conversion is completed.
The AD9244 has three-state ability. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the out-
put data drivers are placed in a high impedance state. The
three-state ability is not intended for rapid access to the data
bus. Note that OEB is referenced to the digital supplies
(DRVDD) and should not exceed that supply voltage.
Clock Overview
The AD9244 has a flexible clock interface that accepts either a
single-ended or differential clock. An internal bias voltage
facilitates ac coupling using two external capacitors. To remain
backward compatible with the single-pin clock scheme of the
AD9226, the AD9244 can be operated with a dc-coupled,
single-pin clock by grounding the CLK− pin and driving CLK+.
By logically AND’ing OTR with the MSB and its complement,
overrange high or underrange low conditions can be detected.
Table 11 is a truth table for the overrange/underrange circuit in
Figure 53, which uses NAND gates. Systems requiring
programmable gain conditioning of the AD9244 can after eight
clock cycles detect an OTR condition, thus eliminating gain
selection iterations. In addition, OTR can be used for digital
offset and gain calibration.
When the CLK− pin is not grounded, the CLK+ and CLK– pins
function as a differential clock receiver. When CLK+ is greater
than CLK–, the SHA is in hold mode; when CLK+ is less than
CLK–, the SHA is in track mode (see Figure 54 for timing). The
rising edge of the clock (CLK+ – CLK–) switches the SHA from
track to hold, and timing jitter on this transition should be mini-
mized, especially for high frequency analog inputs.
+FS – 1 LSB
OTR DATA OUTPUTS
1
0
0
1111 1111 1111 OTR
1111 1111 1111
1111 1111 1110
–FS + 1/2 LSB
CLK–
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
–FS
–FS – 1/2 LSB
+FS
CLK+
+FS – 1/2 LSB
SHA IN
HOLD
SHA IN
TRACK
Figure 52. OTR Relation to Input Voltage and Output Data
Table 11. Output Data Format
OTR
MSB
Analog Input Is
Within range
Within range
Underrange
Overrange
CLK–
CLK+
0
0
1
1
0
1
0
1
Figure 54. SHA Timing
It is often difficult to maintain a 50% duty cycle to the ADC,
especially when driving the clock with a single-ended or sine
wave input. To ease the constraint of providing an accurate 50%
clock, the ADC has an optional internal duty cycle stabilizer
(DCS) that allows the rising clock edge to pass through with
minimal jitter, and interpolates the falling edge, independent of
the input clock falling edge. The DCS is described in greater
detail in the Clock Stabilizer (DCS) section.
MSB
OTR
MSB
OVER = 1
UNDER = 1
Figure 53. Overrange/Underrange Logic
Rev. C | Page 22 of 36
AD9244
Clock Input Modes
CLK+
CLK–
Figure 55 to Figure 59 illustrate the modes of operation of the
clock receiver. Figure 55 shows a differential clock directly
coupled to CLK+ and CLK–. In this mode, the common mode
of the CLK+ and CLK– signals should be close to 1.6 V. Figure 56
illustrates a single-ended clock input. The capacitor decouples
the internal bias voltage on the CLK– pin (about 1.6 V), estab-
lishing a threshold for the CLK+ pin. Figure 57 provides
backward compatibility with the AD9226. In this mode, CLK−
is grounded, and the threshold for CLK+ is 1.5 V. Figure 58
shows a differential clock ac-coupled by connecting through
two capacitors. AC coupling a single-ended clock can also be
accomplished using the circuit in Figure 59.
AD9244
1.6V
0.1μF
AGND
Figure 56. Single-Ended Clock Input, DC-Coupled
CLK+
AD9244
CLK–
AGND
Figure 57. Single-Ended Input, Retains Pin Compatibility with AD9226
When using the differential clock circuits of Figure 55 or Figure 58,
if CLK− drops below 250 mV, the mode of the clock receiver
may change, causing conversion errors. It is essential that CLK−
remains above 250 mV when the clock is ac-coupled or dc-coupled.
CLK+
AD9244
CLK–
100pF
TO 0.1μF
Clock Input Considerations
Figure 58. Differential Clock Input, AC-Coupled
The analog input is sampled on the rising edge of the clock.
Timing variations, or jitter, on this edge causes the sampled
input voltage to be in error by an amount proportional to the
slew rate of the input signal and to the amount of the timing
variation. Thus, to maintain the excellent high frequency SFDR
and SNR characteristics of the AD9244, it is essential that the
clock edge be kept as clean as possible.
0.1μF
CLK+
AD9244
1.6V
CLK–
0.1μF
AGND
The clock should be treated like an analog signal. Clock drivers
should not share supplies with digital logic or noisy circuits.
The clock traces should not run parallel to noisy traces. Using a
pair of symmetrically routed, differential clock signals can help
to provide immunity from common-mode noise coupled from
the environment.
Figure 59. Single-Ended Clock Input, AC-Coupled
Clock Power Dissipation
Most of the power dissipated by the AD9244 is from the analog
power supplies. However, lower clock speeds reduce digital
supply current. Figure 60 shows the relationship between power
and clock rate.
The clock receiver functions like a differential comparator. At
the CLK inputs, a slowly changing clock signal results in more
jitter than a rapidly changing one. Driving the clock with a low
amplitude sine wave input is not recommended. Running a high
speed clock through a divider circuit provides a fast rise/fall
time, resulting in the lowest jitter in most systems.
600
550
AD9244-65
500
450
400
350
CLK+
AD9244
CLK–
AD9244-40
300
250
200
Figure 55. Differential Clock Input, DC-Coupled
0
10
20
30
40
50
60
70
SAMPLE RATE (MHz)
Figure 60. Power Consumption vs. Sample Rate
Rev. C | Page 23 of 36
AD9244
Clock Stabilizer (DCS)
Analog Supply Decoupling
The clock stabilizer circuit in the AD9244 desensitizes the ADC
from clock duty cycle variations. System clock constraints are
eased by internally restoring the clock duty cycle to 50%,
independent of the clock input duty cycle. Low jitter on the
rising edge (sampling edge) of the clock is preserved while the
falling edge is generated on-chip.
The AD9244 features separate analog and digital supply and
ground circuits, helping to minimize digital corruption of
sensitive analog signals. In general, AVDD (analog power)
should be decoupled to AGND (analog ground). The AVDD
and AGND pins are adjacent to one another. Figure 61 shows
the recommended decoupling for each pair of analog supplies;
0.1 μF ceramic chip and 10 μF tantalum capacitors should pro-
vide adequately low impedance over a wide frequency range.
The decoupling capacitors (especially 0.1 μF) should be located
as close to the pins as possible.
It may be desirable to disable the clock stabilizer, or necessary
when the clock frequency is varied or completely stopped. Note
that stopping the clock is not recommended with ac-coupled
clocks. Once the clock frequency is changed, more than 100
clock cycles may be required for the clock stabilizer to settle to
the new speed. When the stabilizer is disabled, the internal
switching is directly affected by the clock state. If CLK+ is high,
the SHA is in hold mode; if CLK+ is low, the SHA is in track
mode. Figure 25 shows the benefits of using the clock stabilizer.
Connecting DCS to AVDD implements the internal clock
stabilization function in the AD9244. If the DCS pin is
connected to ground, the AD9244 uses both edges of the
external clock in its internal timing circuitry (see the
AVDD
+
1
0.1μF
10μF
AD9244
AGND
1
LOCATE AS CLOSE AS POSSIBLE TO SUPPLY PINS.
Figure 61. Analog Supply Decoupling
Digital Supply Decoupling
The digital activity on the AD9244 falls into two categories:
correction logic and output drivers. The internal correction
logic draws relatively small surges of current, mainly during
the clock transitions. The output drivers draw large current
impulses when the output bits change state. The size and
duration of these currents are a function of the load on the
output bits; large capacitive loads should be avoided.
Specifications section for timing requirements).
Grounding and Decoupling
Analog and Digital Grounding
Proper grounding is essential in high speed, high resolution
systems. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power distribution.
For the digital decoupling shown in Figure 62, 0.1 μF ceramic
chip and 10 μF tantalum capacitors are appropriate. The
decoupling capacitors (especially 0.1 μF) should be located as
close to the pins as possible. Reasonable capacitive loads on the
data pins are less than 20 pF per bit. Applications involving
greater digital loads should consider increasing the digital
decoupling and/or using external buffers/latches.
The use of power and ground planes offers distinct advantages,
including:
•
•
•
The minimization of the loop area encompassed by a signal
and its return path
The minimization of the impedance associated with ground
and power paths
A complete decoupling scheme also includes large tantalum or
electrolytic capacitors on the power supply connector to reduce
low frequency ripple to insignificant levels.
The inherent distributed capacitor formed by the power
plane, PCB material, and ground plane
It is important to design a layout that minimizes noise from
coupling onto the input signal. Digital input signals should not
be run in parallel with input signal traces and should be routed
away from the input circuitry. While the AD9244 features sepa-
rate analog and digital ground pins, it should be treated as an
analog component. The AGND and DGND pins must be joined
together directly under the AD9244. A solid ground plane
under the ADC is acceptable if the power and ground return
currents are carefully managed.
DRVDD
+
1
10μF
0.1μF
AD9244
DGND
1
LOCATE AS CLOSE AS POSSIBLE TO SUPPLY PINS.
Figure 62. Digital Supply Decoupling
Rev. C | Page 24 of 36
AD9244
Reference Decoupling
VR
The VREF pin should be bypassed to the REFGND pin with a
10 μF tantalum capacitor in parallel with a low inductance
0.1 μF ceramic capacitor. It is also necessary to add a capacitor
network to decouple the REFT and REFB pins. Figure 49 shows
the recommended decoupling networks.
VR is an internal bias point on the AD9244. It must be
decoupled to AGND with a 0.1 μF capacitor.
CML
VR
AD9244
0.1μF
0.1μF
CML
Figure 63. CML/VR Decoupling
The AD9244 has a midsupply reference point. This is used
within the internal architecture of the AD9244 and must be
decoupled with a 0.1 μF capacitor. It sources or sinks a load of
up to 300 μA. If more current is required, the CML pin should
be buffered with an amplifier.
Rev. C | Page 25 of 36
AD9244
EVALUATION BOARD
ANALOG INPUT CONFIGURATION
REFERENCE CONFIGURATION
Table 12 provides a summary of the analog input configuration.
The analog inputs of the AD9244 on the evaluation board can
be driven differentially through a transformer via Connector S4,
or through the AD8138 amplifier via Connector S2, or they can
be driven single-ended directly via Connector S3. When using
the transformer or AD8138 amplifier, a single-ended source can
be used, as both of these devices are configured on the AD9244
evaluation board to convert single-ended signals to differential
signels.
As described in the Analog Input and Reference Overview
section, the AD9244 can be configured to use its own internal
or an external reference. An external reference, D3, and refer-
ence buffer, U5, are included on the AD9244 evaluation board.
Jumper JP8 and Jumper JP22 to Jumper JP24 can be used to
select the desired reference configuration (see Table 13).
CLOCK CONFIGURATION
The AD9244 evaluation board was designed to achieve optimal
performance as well as to be easily configurable by the user. To
configure the clock input, begin by connecting the correct com-
bination of solderable jumpers (see Table 14). The specific
jumper configuration is dependent on the application and can
be determined by referring to the Clock Input Modes section. If
the differential clock input mode is selected, an external sine
wave generator applied to S5 can be used as the clock source.
The clock buffer/drive MC10EL16 from ON Semiconductor® is
used on the evaluation board to buffer and square the clock
input. If the single-ended clock configuration is used, an exter-
nal clock source can be applied to S1.
Optimal AD9244 performance is achieved above 500 kHz by
using the input transformer. To drive the AD9244 via the trans-
former, connect solderable Jumper JP45 and Jumper JP46. DC
bias is provided by Resistor R8 and Resistor R28. The evaluation
board has positions for through-hole and surface-mount
transformers.
For applications requiring lower frequencies or dc applications,
the AD8138 can be used. The AD8138 provides good distortion
and noise performance, as well as input buffering up to 30 MHz.
For more information, refer to the AD8138 data sheet. To use
the AD8138 to drive the AD9244, remove the transformer (T1
or T4) and connect solderable Jumper JP42 and Jumper JP43.
The AD9244 evaluation board generates a buffered clock at
TTL/CMOS levels for use with a data capture system, such as
the HSC-ADC-EVAL-SC system. The clock buffering is pro-
vided by U4 and U7 and is configured by Jumper JP3,
Jumper JP4, Jumper JP9, and Jumper JP18 (see Table 14).
The AD9244 can be driven single-ended directly via S3 and can
be ac-coupled or dc-coupled by removing or inserting JP5. To
run the evaluation board in this way, remove the transformer
(T1 or T4) and connect solderable Jumper JP40 and Jumper JP41.
Resistor R40, Resistor R41, Resistor R8, and Resistor R28 are
used to bias the AD9244 inputs to the correct common-mode
levels in this application.
Table 12. Analog Input Jumper Configuration
Analog Input
Input Connector Jumpers Notes
Differential: Transformer S4
45, 46
R8, R28 provide dc bias; optimal for 500 kHz.
Differential: Amplifier
Single-Ended
S2
S3
42, 43
5, 40, 41
Remove T1 or T4; used for low input frequencies.
Remove T1 or T4. JP5: connected for dc-coupled, not connected for ac-coupling.
Table 13. Reference Jumper Configuration
Reference
Internal
Internal
Internal
External
Voltage
Jumpers
23
24
25
8, 22
Notes
2 V
1 V
JP8 not connected
JP8 not connected
JP8 not connected; VREF = 1 + R1/R2
Set VREF with R26
1 V ≤ VREF ≤ 2 V
1 V ≤ VREF ≤ 2 V
Rev. C | Page 26 of 36
AD9244
Table 14. Clock Jumper Configuration
Clock Input
Input Connector
Jumpers
DUT CLOCK
Differential
Single-Ended
ADꢀ226-Compatible
DATA CAPTURE CLOCK
Internal
S5
S1
S1
11, 13
12, 15
12, 14
Differential DUT Clock
Single-Ended DUT Clock
External
N/A
N/A
S6
ꢀ, 18A
ꢀ, 18B
3 or 4
5V
5V
3V
3V
+
–
+
–
+
–
+
–
AVDD
GND DUT GND DUT
AVDD DVDD
DVDD
SIGNAL SYNTHESIZER
S4
2.5MHz
BAND-PASS FILTER
REFIN
2.5MHz, 0.8V p-p
HP8644
INPUT
xFMR
AD9244
OUTPUT
BUSS
J1
DSP
EQUIPMENT
EVALUATION BOARD
CLK SYNTHESIZER
65MHz, 1V p-p
HP8644
S1/S5
INPUT
CLOCK
10MHz
REFOUT
CLOCK
DIVIDER
Figure 64. Evaluation Board Connections
Rev. C | Page 27 of 36
AD9244
C W
Figure 65. AD9244 Evaluation Board, ADC, External Reference, and Power Supply Circuitry
Rev. C | Page 28 of 36
AD9244
R S T O C E J
E
N E O A L M E L N A G H T G R R I A D H E E
Figure 66. AD9244 Evaluation Board, Clock Input, and Digital Output Buffer Circuitry
Rev. C | Page 2ꢀ of 36
AD9244
AVDD
C7
R40
1kΩ
JP5
C9
SINGLE
INPUT
0.1μF
S3
JP42
JP40
JP45
R5
R41
1kΩ
49.9Ω 0.33μF
C15
10μF
10V
C44
DNP
R21
33Ω
AVDD
R32
AVDD
VIN+
VIN–
+
C24
20pF
10kΩ
R22
33Ω
JP46
JP41
JP43
C69
0.1μF
R33
10kΩ
C8
0.1μF
C43
DNP
R37
499Ω
3
R46
33Ω
V+
4
1
8
–IN
OUT+
R34
U2
2
V
OCM
523Ω
AD8138
AMP INPUT
S2
OUT–
+IN
R47
33Ω
R35
5
V–
6
499Ω
R31
49.9Ω
ADT4-6T
T4
1
3
P
S
6
5
4
R36
499Ω
AVDD
NC= 2
XFMRINPUT
S4
CW
T1-1TX65
NC = 5
R28
2kΩ
5
4
1
P
S
2
R24
49.9Ω
3
C25
0.33μF
C16
0.1μF
R8
500Ω
T1
Figure 67. AD9244 Evaluation Board, Analog Input Circuitry
Rev. C | Page 30 of 36
AD9244
Figure 68. AD9244 Evaluation Board, PCB Assembly, Top
Figure 69. AD9244 Evaluation Board, PCB Assembly, Bottom
Rev. C | Page 31 of 36
AD9244
Figure 70. AD9244 Evaluation Board, PCB Layer 1 (Top)
Figure 71. AD9244 Evaluation Board, PCB Layer 2 (Ground Plane)
Rev. C | Page 32 of 36
AD9244
Figure 72. AD9244 Evaluation Board, PCB Layer 3 (Power Plane)
Figure 73. AD9244 Evaluation Board, PCB Layer 4 (Bottom)
Rev. C | Page 33 of 36
AD9244
Table 15. Evaluation Board Bill of Materials
Item Qty. Reference Designator
Description
Tantalum capacitors BCASE
Chip capacitors 1206
Package
Value
10 ꢁF
0.1 ꢁF
1
2
11
28
C1, C3, C4, C5, C15, C20, C21, C22, C23, C26, C27
C2, C7, C8, C10, C11, C12, C13, C14, C16, C17, C18, C1ꢀ, C28, C2ꢀ,
C31, C32, C33, C34, C35, C36, C37, C38, C50, C52, C53, C5ꢀ, C61, C6ꢀ
3
4
5
6
7
8
ꢀ
4
2
1
3
5
2
1
1
1
12
11
1
4
6
1
2
5
2
1
2
2
1
2
2
6
3
4
1
3
1
2
1
2
4
6
1
1
1
1
4
2
4
1
1
1
1
1
2
C6, C47, C48, C58
Cꢀ, C25
C24
C30, C46, C4ꢀ
C3ꢀ, C40, C41, C42, C45
C43, C44
C60
D3
Tantalum capacitors DCASE
22 ꢁF
0.33 ꢁF
20 pF
0.1 ꢁF
0.001 ꢁF
DNP1
0.01 μF
1.2 V
Chip capacitors
Chip capacitor
Chip capacitors
Chip capacitors
DNP1
1206
0805
0805
0805
0805
Chip capacitor
Diode
Header male
Headers
1206
10
11
12
13
14
15
16
17
18
1ꢀ
20
21
22
23
24
25
26
27
28
2ꢀ
30
31
32
33
34
35
36
37
38
3ꢀ
40
40a
41
42
43
44
45
46
47
48
4ꢀ
SOT-23 Can
40 PIN RA
JPRBLK02
J1
Header
JP1, JP2, JP3, JP4, JP5, JP6, JP8, JPꢀ, JP22, JP23, JP24, JP25
JP11, JP12, JP13, JP14, JP15, JP40, JP41, JP42, JP43, JP45, JP46
JP18
L1, L2, L3, L4
R1, R5, R11, R24, R2ꢀ, R31
R2
R3, R4
R6, R10, R40, R41, R42
R7, Rꢀ
R8
R12, R13
R14, R15
R16
R17, R20
R18, R1ꢀ
R21, R22, R23, R25, R46, R47
R26, R27, R28
R30, R32, R33, R38
R34
R35, R36, R37
R3ꢀ
R43, R44
R45
RP1, RP2
RP3, RP4, RP5, RP6
S1, S2, S3, S4, S5, S6
T1
T4
TB1
TB1a
TP1, TP2, TP3, TP4
TP5, TP7
Solder jumpers
Header
Chip inductors
Chip resistors
Potentiometer
DNP1
JPRBLK03
LC1210
RC07CUP
RV32ꢀꢀUP
RC07CUP
1206
FBEAD
4ꢀ.ꢀ Ω
5 kΩ
DNP1
1 kΩ
Chip resistors
Chip resistors
Chip resistor
Chip resistors
Chip resistors
Chip resistor
Chip resistors
Chip resistors
Chip resistors
Potentiometers
Chip resistors
Chip resistor
Chip resistors
Chip resistor
Chip resistors
Potentiometer
Resistor packs
Resistor packs
1206
1206
1206
1206
1206
1206
1206
1206
RV32ꢀꢀUP
1206
1206
1206
1206
22 Ω
500 Ω
113 Ω
ꢀ0 Ω
2.55 kΩ
2 kΩ
4 kΩ
33 Ω
2 kΩ
10 kΩ
523 Ω
4ꢀꢀ Ω
4ꢀ.ꢀ Ω
100 Ω
10 kΩ
22 Ω
1206
RV32ꢀꢀUP
RCTS766
RCA74204
22 Ω
SMA connectors 50 Ω SMA200UP
Transformer
Transformer
Header
DIP06RCUP
MINI_CD637 ADT4-6T
TBLK06REM
T1-1TX65
Header
Test points
Test points
Test points
ADꢀ244
AD8138 amplifier
ECL divider
Hex inverter
AD822 op amp
Octal registers
LOOPTP
LOOPMINI
LOOPTP
LQFP-48
R-8
RED
WHT
BLK
ADꢀ244
AD8138
MC10EL16
74VHC04MTC
AD822
TP11, TP12, TP13, TP14
U1
U2
U3
U4
U5
U6, U7
SO8
TSSOP14
SOIC-8
SOL20
74VHC541
Rev. C | Page 34 of 36
AD9244
Item Qty. Reference Designator
Description
Package
Value
50
51
14
2
Sockets for through resistors
C56, C57
Solder sockets
DNP1
Total 183
1 Do not place.
Rev. C | Page 35 of 36
AD9244
OUTLINE DIMENSIONS
0.75
0.60
0.45
9.00
BSC SQ
1.60
MAX
37
48
36
1
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
12
0.15
0.05
13
24
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 74. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADꢀ244BST-65
Temperature Range
Package Description
Package Option
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
48-Lead Low Profile Quad Flat Package (LQFP)
Evaluation Board
ADꢀ244BSTRL-65
ADꢀ244BSTZ-651
ADꢀ244BSTZRL-651
ADꢀ244BST-40
ADꢀ244BSTRL-40
ADꢀ244BSTZ-401
ADꢀ244BSTZRL-401
ADꢀ244-65PCB
ADꢀ244-40PCB
Evaluation Board
1 Z = Pb-free part.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02404-0-12/05(C)
Rev. C | Page 36 of 36
相关型号：
AD9245BCPZ-40
1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC32, ROHS COMPLIANT, EXPOSED PAD, MO-220-VHHD-2, LFCSP-32
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