AD9279BBCZ [ADI]
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| 型号： | AD9279BBCZ |
| 厂家： | 
ADI |
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Octal LNA/VGA/AAF/ADC
and CW I/Q Demodulator
AD9279
FEATURES
GENERAL DESCRIPTION
8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
Low power: 141 mW per channel, TGC mode, 40 MSPS;
60 mW per channel, CW mode
10 mm × 10 mm, 144-ball CSP-BGA
TGC channel input-referred noise: 0.8 nV/√Hz, max gain
Flexible power-down modes
The AD9279 is designed for low cost, low power, small size,
and ease of use for medical ultrasound and automotive radar. It
contains eight channels of a variable gain amplifier (VGA) with
a low noise preamplifier (LNA), an antialiasing filter (AAF), an
analog-to-digital converter (ADC), and an I/Q demodulator
with programmable phase rotation.
Fast recovery from low power standby mode: <2 μs
Overload recovery: <10 ns
Low noise preamplifier (LNA)
Input-referred noise: 0.75 nV/√Hz, gain = 21.3 dB
Programmable gain: 15.6 dB/17.9 dB/21.3 dB
0.1 dB compression: 1000 mV p-p/
Each channel features a variable gain range of 45 dB, a fully
differential signal path, an active input preamplifier termination,
and a maximum gain of up to 52 dB. The channel is optimized
for high dynamic performance and low power in applications
where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. Assuming a 15 MHz noise bandwidth (NBW)
and a 21.3 dB LNA gain, the LNA input SNR is roughly 94 dB.
In CW Doppler mode, each LNA output drives an I/Q demod-
ulator that has independently programmable phase rotation
with 16 phase settings.
750 mV p-p/450 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW): >100 MHz
Variable gain amplifier (VGA)
Attenuator range: −45 dB to 0 dB
Postamp gain (PGA): 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable second-order LPF from 8 MHz to 18 MHz
Programmable HPF
Analog-to-digital converter (ADC)
SNR: 70 dB, 12 bits up to 80 MSPS
Serial LVDS (ANSI-644, low power/reduced signal)
CW mode I/Q demodulator
Individual programmable phase rotation
Output dynamic range per channel: >160 dBc/√Hz
Output-referred SNR: 155 dBc/√Hz, 1 kHz offset, −3 dBFS
Power-down of individual channels is supported to increase
battery life for portable applications. Standby mode allows quick
power-up for power cycling. In CW Doppler operation, the
VGA, AAF, and ADC are powered down. The ADC contains
several features designed to maximize flexibility and minimize
system cost, such as a programmable clock, data alignment, and
programmable digital test pattern generation. The digital test
patterns include built-in fixed patterns, built-in pseudo random
patterns, and custom user-defined test patterns entered via the
serial port interface.
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2
PDWN
STBY
DRVDD
LO-A TO LO-H
I/Q
DEMODULATOR
8 CHANNELS
LOSW-A TO LOSW-H
LI-A TO LI-H
DOUTA+ TO DOUTH+
DOUTA– TO DOUTH–
12-BIT
ADC
SERIAL
LVDS
LNA
VGA
AAF
LG-A TO LG-H
FCO+
FCO–
DCO+
DCO–
DATA
RATE
MULTIPLIER
SERIAL
PORT
INTERFACE
LO
REFERENCE
GENERATION
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
AD9279
TABLE OF CONTENTS
Features .............................................................................................. 1
Equivalent Circuits......................................................................... 17
Ultrasound Theory of Operation ................................................. 19
Channel Overview.......................................................................... 20
TGC Operation........................................................................... 20
CW Doppler Operation............................................................. 33
Serial Port Interface (SPI).............................................................. 37
Hardware Interface..................................................................... 37
Memory Map .................................................................................. 39
Reading the Memory Map Table.............................................. 39
Reserved Locations .................................................................... 39
Default Values............................................................................. 39
Logic Levels................................................................................. 39
Outline Dimensions....................................................................... 43
Ordering Guide .......................................................................... 43
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Specifications.......................................................................... 3
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
ADC Timing Diagrams ............................................................... 8
Absolute Maximum Ratings............................................................ 9
Thermal Impedance..................................................................... 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 13
TGC Mode................................................................................... 13
CW Doppler Mode..................................................................... 16
REVISION HISTORY
10/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 44
AD9279
SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (−40°C to +85°C), fIN = 5 MHz,
RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.3 dB, LNA bias = default, PGA gain = 27 dB, GAIN− = 0.8 V, GAIN+ = 0 V, AAF LPF
cutoff = fSAMPLE/3 (MODE I/II) = fSAMPLE/4.5 (MODE III), HPF cutoff = LPF cutoff/12, MODE I = fSAMPLE = 40 MSPS, MODE II = fSAMPLE
=
65 MSPS, MODE III = fSAMPLE = 80 MSPS, low power LVDS mode, unless otherwise noted.
Table 1.
Parameter1
LNA CHARACTERISTICS
Gain
Test Conditions/Comments
Min
Typ
Max
Unit
Single-ended input to differential
output
Single-ended input to single-ended
output
15.6/17.9/21.3
9.6/11.9/15.3
dB
dB
0.1 dB Input Compression Point
1 dB Input Compression Point
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
1.00
0.75
0.45
V p-p
V p-p
V p-p
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
1.20
0.90
0.60
2.2
V p-p
V p-p
V p-p
V
Input Common Mode (LI-x, LG-x)
Output Common Mode (LO-x)
Switch off
Switch on
High-Z
1.5
Ω
V
Output Common Mode (LOSW-x) Switch off
Switch on
High-Z
1.5
Ω
V
Input Resistance (LI-x)
RFB = 350 Ω, LNA gain = 21.3 dB
50
Ω
RFB = 1400 Ω, LNA gain = 21.3 dB
RFB = ∞, LNA gain = 21.3 dB
200
6
22
Ω
kΩ
pF
Input Capacitance (LI-x)
−3 dB Bandwidth
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
150
130
100
MHz
MHz
MHz
Input Noise Voltage
RS = 0 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RFB = ∞
0.95
0.85
0.75
2.5
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
Input Noise Current
Noise Figure
RS = 50 Ω
Active Termination Matched
LNA gain = 15.6 dB, RFB = 200 Ω
LNA gain = 17.9 dB, RFB = 250 Ω
LNA gain = 21.3 dB, RFB = 350 Ω
LNA gain = 15.6 dB, RFB = ∞
LNA gain = 17.9 dB, RFB = ∞
LNA gain = 21.3 dB, RFB = ∞
4.5
3.7
2.9
3.1
2.6
2.2
dB
dB
dB
dB
dB
dB
Unterminated
FULL-CHANNEL (TGC)
CHARACTERISTICS
AAF Low-Pass Cutoff
In Range AAF Bandwidth
Tolerance
−3 dB, programmable
8
18
MHz
%
10
Group Delay Variation
f = 1 MHz to 18 MHz, GAIN+ = 0 V to 1.6 V
0.3
ns
Rev. 0 | Page 3 of 44
AD9279
Parameter1
Test Conditions/Comments
GAIN+ = 1.6 V, RFB = ∞
Min
Typ
Max
Unit
Input-Referred Noise Voltage
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
1.12
0.96
0.81
nV/√Hz
nV/√Hz
nV/√Hz
Noise Figure
Active Termination Matched
GAIN+ = 1.6 V, RS = 50 Ω
LNA gain = 15.6 dB, RFB = 200 Ω
LNA gain = 17.9 dB, RFB = 250 Ω
LNA gain = 21.3 dB, RFB = 350 Ω
LNA gain = 15.6 dB, RFB = ∞
LNA gain = 17.9 dB, RFB = ∞
LNA gain = 21.3 dB, RFB = ∞
No signal, correlated/uncorrelated
5.6
4.5
3.3
3.5
2.9
2.3
−30
dB
dB
dB
dB
dB
dB
dB
Unterminated
Correlated Noise Ratio
Output Offset
−35
+35
LSB
dBFS
dBFS
Signal-to-Noise Ratio (SNR)
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V,
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
67
59
Harmonic Distortion
Second Harmonic
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
fIN = 5 MHz at −10 dBFS, GAIN+ = 0 V
fIN = 5 MHz at −1 dBFS, GAIN+ = 1.6 V
−72
−72
−69
−59
−70
dBc
dBc
dBc
dBc
dBc
Third Harmonic
Two-Tone Intermodulation (IMD3) fRF1 = 5.015 MHz, fRF2 = 5.020 MHz,
ARF1 = 0 dB, ARF2 = −20 dB, GAIN+ =
1.6 VIMD3 relative to ARF2
Channel-to-Channel Crosstalk
fIN1 = 5.0 MHz at −1 dBFS
Overrange condition2
Full TGC path, fIN = 5 MHz, GAIN+ = 0 V to
1.6 V
−60
−55
0.3
dB
dB
Degrees
Channel-to-Channel Delay
Variation
GAIN ACCURACY
25°C
Gain Law Conformance Error
0 < GAIN+ < 0.16 V
0.16 V < GAIN+ < 1.44 V
1.44 V < GAIN+ < 1.6 V
GAIN+ = 0.8 V, normalized for ideal AAF
loss
0.5
0.5
dB
dB
dB
dB
−1.6
−1.6
+1.6
+1.6
Linear Gain Error
Channel-to-Channel Matching
PGA Gain
0.16 V < GAIN+ < 1.44 V
0.1
dB
dB
21/24/27/30
GAIN CONTROL INTERFACE
Control Range
Differential
Single-ended
GAIN+ = 0 V to 1.6 V
−0.8
0
+0.8
1.6
V
V
Gain Range
Scale Factor
Response Time
Gain+ Impedance
Gain− Impedance
CW DOPPLER MODE
LO Frequency
Phase Resolution
Output DC Bias (Single-Ended)
Output AC Current Range
45
dB
dB/V
ns
MΩ
kΩ
28.0
750
10
45 dB change
Single-ended
Single-ended
70
fLO = f4LO/4
Per channel
CWI+, CWI−, CWQ+, CWQ−
Per CWI+, CWI−, CWQ+, CWQ−, each
channel enabled
1
10
MHz
Degrees
V
22.5
1.5
1.25
mA
Transconductance (Differential)
Demodulated IOUT/VIN, per CWI+, CWI−,
CWQ+, CWQ−
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
1.8
2.4
3.5
mA/V
mA/V
mA/V
Rev. 0 | Page 4 of 44
AD9279
Parameter1
Test Conditions/Comments
RS = 0 Ω, RFB = ∞
Min
Typ
Max
Unit
Input-Referred Noise Voltage
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RS = 50 Ω, RFB = ∞
1.5
1.4
1.3
nV/√Hz
nV/√Hz
nV/√Hz
Noise Figure
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
RS = 0 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.3 dB
5.7
5.3
4.8
dB
dB
dB
Input-Referred Dynamic Range
Output-Referred SNR
164
162
160
155
dBFS/√Hz
dBFS/√Hz
dBFS/√Hz
dBc/√Hz
−3 dBFS input, fRF = 2.5 MHz, f4LO
10 MHz, 1 kHz offset
=
Two-Tone Intermodulation (IMD3) fRF1 = 5.015 MHz, fRF2 = 5.020 MHz,
4LO = 20 MHz, ARF1 = −1 dBFS, ARF2
−58
dB
f
=
−21 dBFS, IMD3 relative to ARF2
Quadrature Phase Error
0.15
0.015
0.5
Degrees
dB
I to Q, all phases, 1 σ
I to Q, all phases, 1 σ
I/Q Amplitude Imbalance
Channel-to-Channel Matching
Degrees
dB
Phase I to I, Q to Q, 1 σ
Amplitude I to I, Q to Q, 1 σ
0.25
POWER SUPPLY, MODE I/II/III
AVDD1
AVDD23
DRVDD
IAVDD1
1.7
2.7
1.7
1.8
3.0
1.8
1.9
3.6
1.9
V
V
V
mA
mA
mA
mA
mA
TGC mode
197/270/328
32
240
CW Doppler mode
TGC mode, no signal
CW Doppler mode
ANSI-644 mode
Low power (IEEE 1596.3 similar) mode
TGC mode, no signal
IAVDD2
IDRVDD
144
49/51/52
33/35/36
1134/1269/
1375
Total Power Dissipation
(Including Output Drivers)
1275/1410/ mW
1594
CW Doppler mode
495
mW
Power-Down Dissipation
Standby Power Dissipation
Power Supply Rejection Ratio
(PSRR)
5
mW
mW
mV/V
542
1.6
ADC RESOLUTION
ADC REFERENCE
12
Bits
Output Voltage Error
Load Regulation at 1.0 mA
Input Resistance
VREF = 1 V
VREF = 1 V
50
mV
mV
kΩ
2
6
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed.
2 The overrange condition is specified as 6 dB more than the full-scale input range.
3 When the LNA gain is set to 15.6 dB, AVDD2 >3.0 V.
Rev. 0 | Page 5 of 44
AD9279
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted.
Table 2.
Parameter1
Temperature
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Full
Full
25°C
25°C
250
1.2
20
mV p-p
V
kΩ
pF
1.5
CW 4LO INPUTS (4LO+, 4LO−)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Full
Full
25°C
25°C
250
1.2
20
mV p-p
V
kΩ
pF
1.5
LOGIC INPUTS (PDWN, STBY, SCLK, SDIO)
Logic 1 Voltage
Logic 0 Voltage
Full
Full
1.2
AVDD1 + 0.3
0.3
V
V
Input Resistance
Input Capacitance
25°C
25°C
30
0.5
kΩ
pF
LOGIC INPUTS (RESET)
Logic 1 Voltage
Logic 0 Voltage
Full
Full
1.2
AVDD2 + 0.3
0.3
V
V
Input Resistance
Input Capacitance
25°C
25°C
30
0.5
kΩ
pF
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Full
Full
1.2
AVDD1 + 0.3
0.3
V
V
Input Resistance
Input Capacitance
25°C
25°C
70
0.5
kΩ
pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (DOUTx+, DOUTx−), (ANSI-644)
Logic Compliance
Full
Full
1.79
V
V
0.05
LVDS
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Full
Full
247
1.125
Offset binary
454
1.375
mV
V
DIGITAL OUTPUTS (DOUTx+, DOUTx−),
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Full
Full
150
1.10
Offset binary
250
1.30
mV
V
LOGIC OUTPUT (GPO0/GPO1/GPO2/GPO3)
Logic 0 Voltage (IOL = 50 μA)
Full
0.05
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
Rev. 0 | Page 6 of 44
AD9279
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, full temperature, unless otherwise noted.
Table 3.
Parameter1
CLOCK2
Temperature Min
Typ
Max
Unit
Clock Rate
40 MSPS (Mode I)
65 MSPS (Mode II)
80 MSPS (Mode III)
Full
Full
Full
Full
Full
18.5
18.5
18.5
40
65
80
MHz
MHz
MHz
ns
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO
DCO Propagation Delay (tCPD
DCO to Data Delay (tDATA
DCO to FCO Delay (tFRAME
Data-to-Data Skew (tDATA-MAX − tDATA-MIN
6.25
6.25
ns
Full
Full
Full
Full
Full
Full
Full
Full
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 1.5
(tSAMPLE/2) + 2.3
300
300
(tSAMPLE/2) + 2.3
tFCO + (tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24)
100
(tSAMPLE/2) + 3.1
(tSAMPLE/2) + 3.1
ns
ps
ps
ns
ns
ps
ps
ps
ꢀs
ms
)
)
4
4
)
(tSAMPLE/24) − 300
(tSAMPLE/24) − 300
(tSAMPLE/24) + 300
(tSAMPLE/24) + 300
350
4
)
)
Wake-Up Time (Standby), GAIN+ = 0.5 V 25°C
Wake-Up Time (Power-Down)
Pipeline Latency
2
1
8
25°C
Full
Clock
cycles
APERTURE
Aperture Uncertainty (Jitter)
LO GENERATION
25°C
<1
ps rms
4LO Frequency
Full
Full
Full
Full
4
5
5
20
40
MHz
ns
ns
LO Divider RESET Setup Time5
LO Divider RESET Hold Time5
LO Divider RESET High Pulse Width
ns
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Can be adjusted via the SPI.
3 Measurements were made using a part soldered to FR-4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
5 RESET edge to rising 4LO edge.
Rev. 0 | Page 7 of 44
AD9279
ADC TIMING DIAGRAMS
N – 1
AIN
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFRAME
tFCO
FCO–
FCO+
tPD
tDATA
D6
DOUTx–
DOUTx+
MSB
N – 8
D10
D9
D8
D7
D5
D4
N – 8
D3
N – 8
D2
N – 8
D1
N – 8
D0
N – 8
MSB
D10
N – 8 N – 8 N – 8 N – 8 N – 8 N – 8
N – 7 N – 7
Figure 2. 12-Bit Data Serial Stream (Default)
N – 1
AIN
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFRAME
tFCO
FCO–
FCO+
tPD
tDATA
DOUTx–
DOUTx+
LSB
N – 8
D0
D1
D2
D3
D4
D5
D6
N – 8
D7
N – 8
D8
N – 8
D9
N – 8
D10
N – 8
LSB
D0
N – 8 N – 8 N – 8 N – 8 N – 8 N – 8
N – 7 N – 7
Figure 3. 12-Bit Data Serial Stream, LSB First
Rev. 0 | Page 8 of 44
AD9279
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
AVDD1 to GND
AVDD2 to GND
DRVDD to GND
GND to GND
AVDD2 to AVDD1
AVDD1 to DRVDD
AVDD2 to DRVDD
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +2.0 V
−0.3 V to +0.3 V
−2.0 V to +3.9 V
−2.0 V to +2.0 V
−2.0 V to +3.9 V
−0.3 V to
THERMAL IMPEDANCE
Table 5.
Symbol Description
Digital Outputs (DOUTx+, DOUTx−,
DCO+, DCO−, FCO+, FCO−) to GND
Value1 Units
DRVDD + 0.3 V
−0.3 V to
Junction-to-ambient thermal
resistance, 0.0 m/s air flow per
JEDEC JESD51-2 (still air)
Junction-to-board thermal
characterization parameter, 0 m/s
air flow per JEDEC JESD51-8 (still air)
Junction-to-top-of-package
characterization parameter, 0 m/s
air flow per JEDEC JESD51-2 (still air)
22.0
°C/W
°C/W
°C/W
CLK+, CLK−, SDIO to GND
θJA
AVDD1 + 0.3 V
−0.3 V to
LI-x, LO-x, LOSW-x to GND
9.2
ΨJB
ΨJT
AVDD2 + 0.3 V
−0.3 V to
AVDD2 + 0.3 V
−0.3 V to
CWI−, CWI+, CWQ−, CWQ+ to GND
PDWN, STBY, SCLK, CSB to GND
0.12
AVDD1 + 0.3 V
−0.3 V to
AVDD2 + 0.3 V
−0.3 V to
GAIN+, GAIN−, RESET, 4LO+, 4LO−,
GPO0, GPO1, GPO2, GPO3 to GND
1 Results are from simulations. PCB is JEDEC multilayer. Thermal performance
for actual applications requires careful inspection of the conditions in the
application to determine if they are similar to those assumed in these
calculations.
VREF to GND
AVDD1 + 0.3 V
Operating Temperature Range (Ambient) −40°C to +85°C
ESD CAUTION
Storage Temperature Range (Ambient)
Maximum Junction Temperature
−65°C to +150°C
150°C
Lead Temperature (Soldering, 10 sec)
300°C
Rev. 0 | Page 9 of 44
AD9279
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
A
B
C
LI-E
LI-F
LI-G
LI-H
VREF
RBIAS GAIN+ GAIN–
LI-A
LI-B
LI-C
LI-D
LG-E
LO-E
LG-F
LO-F
LG-G
LO-G
LG-H
LO-H
GND
GND
GND
GND
AVDD2
GND
GND
GND
LG-A
LO-A
LG-B
LO-B
LG-C
LO-C
LG-D
LO-D
D
E
F
LOSW-E LOSW-F LOSW-G LOSW-H GND
GND
GND
GND
GND
GND
GND
GND
4LO+
GND LOSW-A LOSW-B LOSW-C LOSW-D
GND
AVDD1
GND
AVDD2 AVDD2 AVDD2
GND
AVDD1
GND
GND
AVDD1
GND
AVDD2 AVDD2 AVDD2
GND
AVDD1
GND
GND
AVDD1
GND
AVDD1
GND
GND
AVDD1
GND
GND
GND
AVDD1
GND
AVDD1
GND
GND
AVDD1
GND
G
H
J
GND
CLK–
CLK+
GND
GND
GND
GND
GND
CSB
GND
CWQ+
CWQ–
GND
CWI+
AVDD2
GND
GPO3
GPO1
GPO0
PDWN
STBY
SDIO
K
L
GND
GND
GND
CWI–
AVDD2
4LO–
RESET GPO2
SCLK
DRVDD DOUTH+ DOUTG+ DOUTF+ DOUTE+ DCO+
GND DOUTH– DOUTG– DOUTF– DOUTE– DCO–
FCO+ DOUTD+ DOUTC+ DOUTB+ DOUTA+ DRVDD
FCO– DOUTD– DOUTC– DOUTB– DOUTA– GND
M
Figure 4. Pin Configuration
4
6
8
10
12
2
1
3
5
7
9
11
A
B
C
D
E
F
G
H
J
K
L
M
TOP VIEW
(Not to Scale)
Figure 5.
Rev. 0 | Page 10 of 44
AD9279
Table 6. Pin Function Descriptions
Pin No.
Name
Description
B5, B6, B8, C5, C6, C7, C8, D5, D6, D7, D8, GND
E1, E5, E6, E7, E8, E12, F2, F4, F6, F7, F9,
F11, G1, G3, G5, G6, G7, G8, G10, G12,
H2, H3, H4, H5, H6, H7, H8, H9, H10, H11,
J2, J4, J8, K1, K2, K4, M1, M12
Ground (should be tied to a quiet analog ground)
F1, F3, F5, F8, F10, F12, G2, G4, G9, G11
AVDD1
1.8 V Analog Supply
B7, E2, E3, E4, E9, E10, E11, J6, K6
L1, L12
A1
AVDD2
DRVDD
LI-E
3.0 V Analog Supply
1.8 V Digital Output Driver Supply
LNA Analog Input for Channel E
LNA Ground for Channel E
B1
LG-E
C2
D2
A2
LO-F
LOSW-F
LI-F
LNA Analog Inverted Output for Channel F
LNA Analog Switched Output for Channel F
LNA Analog Input for Channel F
LNA Ground for Channel F
B2
LG-F
C3
D3
A3
LO-G
LOSW-G
LI-G
LNA Analog Inverted Output for Channel G
LNA Analog Switched Output for Channel G
LNA Analog Input for Channel G
LNA Ground for Channel G
B3
LG-G
C4
D4
A4
LO-H
LOSW-H
LI-H
LNA Analog Inverted Output for Channel H
LNA Analog Switched Output for Channel H
LNA Analog Input for Channel H
LNA Ground for Channel H
B4
LG-H
H1
J1
CLK−
CLK+
Clock Input Complement
Clock Input True
M2
L2
M3
L3
M4
L4
M5
L5
M6
L6
M7
L7
M8
L8
M9
L9
M10
L10
M11
L11
K11
J11
K12
J12
H12
B9
DOUTH−
DOUTH+
DOUTG−
DOUTG+
DOUTF−
DOUTF+
DOUTE−
DOUTE+
DCO−
DCO+
FCO−
ADC H Digital Output Complement
ADC H Digital Output True
ADC G Digital Output Complement
ADC G Digital Output True
ADC F Digital Output Complement
ADC F Digital Output True
ADC E Digital Output Complement
ADC E Digital Output True
Digital Clock Output Complement
Digital Clock Output True
Frame Clock Digital Output Complement
Frame Clock Digital Output True
ADC D Digital Output Complement
ADC D Digital Output True
ADC C Digital Output Complement
ADC C Digital Output True
ADC B Digital Output Complement
ADC B Digital Output True
ADC A Digital Output Complement
ADC A Digital Output True
Standby Power-Down
Full Power-Down
Serial Clock
Serial Data Input/Output
Chip Select Bar
LNA Ground for Channel A
FCO+
DOUTD−
DOUTD+
DOUTC−
DOUTC+
DOUTB−
DOUTB+
DOUTA−
DOUTA+
STBY
PDWN
SCLK
SDIO
CSB
LG-A
A9
D9
C9
LI-A
LOSW-A
LO-A
LNA Analog Input for Channel A
LNA Analog Switched Output for Channel A
LNA Analog Inverted Output for Channel A
Rev. 0 | Page 11 of 44
AD9279
Pin No.
B10
A10
D10
C10
B11
A11
D11
C11
B12
A12
D12
C12
K10
J10
K9
J9
K8
K7
J7
A8
A7
A6
A5
Name
LG-B
LI-B
LOSW-B
LO-B
LG-C
LI-C
LOSW-C
LO-C
LG-D
LI-D
Description
LNA Ground for Channel B
LNA Analog Input for Channel B
LNA Analog Switched Output for Channel B
LNA Analog Inverted Output for Channel B
LNA Ground for Channel C
LNA Analog Input for Channel C
LNA Analog Switched Output for Channel C
LNA Analog Inverted Output for Channel C
LNA Ground for Channel D
LNA Analog Input for Channel D
LOSW-D
LO-D
LNA Analog Switched Output for Channel D
LNA Analog Inverted Output for Channel D
General Purpose Open Drain Output 0
General Purpose Open Drain Output 1
General Purpose Open Drain Output 2
General Purpose Open Drain Output 3
Reset for Synchronizing 4LO Divide-by-4 Counter
CW Doppler 4LO Input Complement
CW Doppler 4LO Input True
Gain Control Voltage Input Complement
Gain Control Voltage Input True
External Resistor to Set the Internal ADC Core Bias Current
Voltage Reference Input/Output
GPO0
GPO1
GPO2
GPO3
RESET
4LO−
4LO+
GAIN−
GAIN+
RBIAS
VREF
K5
J5
K3
J3
C1
D1
CWI−
CWI+
CWQ−
CWQ+
LO-E
CW Doppler I Output Complement
CW Doppler I Output True
CW Doppler Q Output Complement
CW Doppler Q Output True
LNA Analog Inverted Output for Channel E
LNA Analog Switched Output for Channel E
LOSW-E
Rev. 0 | Page 12 of 44
AD9279
TYPICAL PERFORMANCE CHARACTERISTICS
TGC MODE
fSAMPLE = 40 MSPS, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = mid-high, PGA gain = 27 dB, GAIN− = 0.8 V, AAF LPF
cutoff = fSAMPLE/3.0, HPF cutoff = LPF cutoff/12.00 (default).
1.0
0.8
0.6
1.4
1.2
1.0
0.8
0.6
0.4
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1
2
3
4
5
6
7
8
9
10
GAIN+ (V)
FREQUENCY (MHz)
Figure 6. Gain Error vs. GAIN+
Figure 9. Short-Circuit, Input-Referred Noise vs. Frequency,
LNA Gain = 21.3 dB, PGA Gain = 30 dB, GAIN+ = 1.6 V
600
550
–128
1,000,000 TOTAL HITS
–130
500
450
400
350
300
250
200
150
100
50
–132
–134
LNA GAIN = 21.3dB
LNA GAIN = 17.9dB
LNA GAIN = 15.6dB
–136
–138
–140
–142
0
–8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
8
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
CODES
GAIN+ (V)
Figure 7. Output-Referred Noise Histogram, GAIN+ = 0.0 V
Figure 10. Short-Circuit, Output-Referred Noise vs. GAIN+
220
64
1,000,000 TOTAL HITS
SNR
200
180
160
62
60
58
140
120
SINAD
100
80
60
40
20
0
56
54
52
50
–8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
8
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
CODES
GAIN+ (V)
Figure 8. Output-Referred Noise Histogram, GAIN+ = 1.6 V
Figure 11. SNR/SINAD vs. GAIN+, AOUT = −1.0 dBFS
Rev. 0 | Page 13 of 44
AD9279
70
68
66
64
62
0
–10
–20
–30
–40
–50
–60
–70
–80
PGA = 21dB
PGA = 30dB
60
58
GAIN+ = 0.4V
GAIN+ = 1.0V
56
54
52
GAIN+ = 1.6V
SNR
SINAD
50
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0
2
4
6
8
10
12
14
16
GAIN+ (V)
INPUT FREQUENCY (MHz)
Figure 12. SNR/SINAD vs. GAIN+, AIN = −45 dBm
Figure 15. Third-Order Harmonic Distortion vs. Frequency, AOUT = −1.0 dBFS
0
–2
–4
–6
0
–10
–20
–30
MODE III = 80MSPS
MODE II = 65MSPS
–8
–10
–12
–14
–40
–50
GAIN+ = 0.4V
GAIN+ = 1.0V
–60
MODE I = 40MSPS
–70
–16
–80
GAIN+ = 1.6V
–18
0
–90
–40
5
10
15
20
–35
–30
–25
–20
–15
–10
–5
0
INPUT FREQUENCY (MHz)
ADC OUTPUT LEVEL (dBFS)
Figure 13. Antialiasing Filter (AAF) Pass-Band Response,
LPF Cutoff = 1 × (1/4.5) × fSAMPLE
Figure 16. Second-Order Harmonic Distortion vs. ADC Output Level, AOUT
0
0
–10
–20
–30
–40
–10
–20
–30
–40
–50
–60
–70
GAIN+ = 0.4V
–50
–60
GAIN+ = 0.4V
GAIN+ = 1.0V
–70
–80
GAIN+ = 1.6V
GAIN+ = 1.6V
–80
–90
GAIN+ = 1.0V
–90
–100
0
2
4
6
8
10
12
14
16
–40
–35
–30
–25
–20
–15
–10
–5
0
INPUT FREQUENCY (MHz)
ADC OUTPUT LEVEL (dBFS)
Figure 14. Second-Order Harmonic Distortion vs. Frequency,
AOUT = −1.0 dBFS
Figure 17. Third-Order Harmonic Distortion vs. ADC Output Level
Rev. 0 | Page 14 of 44
AD9279
0
8
7
f
f
= 5.00MHz
= 5.01MHz
IN1
IN2
6
5
4
3
2
FUND2 LEVEL = FUND1 LEVEL = –21dB
–20
GAIN = 0
GAIN = 0.8
GAIN = 1.6
–40
–60
–80
1
0
100k
1M
10M
FREQUENCY (Hz)
100M
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–120
–40
–35
–30
–25
–20
–15
–10
–5
0
100k
1M
10M
FREQUENCY (Hz)
100M
AMPLITUDE LEVEL (dBFS)
Figure 18. LNA Input Impedance Magnitude and Phase, Unterminated
Figure 20. IMD3 vs. ADC Output Level
0
f
f
= 5.00MHz
= 5.01MHz
IN1
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
IN2
FUND1 LEVEL = –1dBFS
FUND2 LEVEL = –21dBFS
f = 2.3MHz
f = 5MHz
f = 80MHz
0.4
0.6
0.8
1.0
1.2
1.4
1.6
GAIN+ (V)
Figure 19. IMD3 vs. Gain+
Rev. 0 | Page 15 of 44
AD9279
CW DOPPLER MODE
fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = mid-high, all CW channels enabled, phase rotation 0 degrees.
1.2
1.0
0.8
0.6
0.4
0.2
0
12
10
8
6
4
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
2
0
100
1k
10k
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
BASEBAND FREQUENCY (Hz)
BASEBAND FREQUENCY (Hz)
Figure 21. Quadrature (I/Q) Phase Error vs. Baseband Frequency
Figure 23. Noise Figure vs. Baseband Frequency
0.10
0.08
0.06
130
135
140
0.04
0.02
0
145
150
155
–0.02
–0.04
–0.06
–0.08
–0.10
160
165
100
1k
10k
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
BASEBAND FREQUENCY (Hz)
BASEBAND FREQUENCY (Hz)
Figure 22. Quadrature (I/Q) Amplitude Error vs. Baseband Frequency
Figure 24. Output-Referred SNR vs. Baseband Frequency
Rev. 0 | Page 16 of 44
AD9279
EQUIVALENT CIRCUITS
AVDD1
AVDD2
VCM
15kΩ
350Ω
30kΩ
LI-x,
LG-x
SDIO
Figure 25. Equivalent LNA Input Circuit (VCM = Common-Mode Voltage)
Figure 29. Equivalent SDIO Input Circuit
DRVDD
AVDD2
AVDD2
DRVDD
DRVDD
V
V
V
V
10Ω
LO-x,
LOSW-x
DOUTx–
DOUTx+
GND
Figure 26. Equivalent LNA Output Circuit
Figure 30. Equivalent Digital Output Circuit
AVDD1
350Ω
CLK+
AVDD1
10kΩ
10kΩ
SCLK,
PDWN,
OR STBY
350Ω
1.25V
AVDD1
30kΩ
350Ω
CLK–
Figure 27. Equivalent Clock Input Circuit
Figure 31. Equivalent SCLK, PDWN, or STBY Input Circuit
AVDD2
350Ω
4LO+
AVDD2
10kΩ
10kΩ
350Ω
RESET
1.25V
AVDD2
350Ω
4LO–
Figure 32. Equivalent RESET Input Circuit
Figure 28. Equivalent 4LO Input Circuit
Rev. 0 | Page 17 of 44
AD9279
AVDD1
AVDD2
AVDD1
70kΩ
50Ω
350Ω
GAIN+
CSB
Figure 33. Equivalent CSB Input Circuit
Figure 36. Equivalent GAIN+ Input Circuit
0.8V
AVDD2
AVDD2
70kΩ
50Ω
GAIN–
VREF
6kΩ
Figure 34. Equivalent VREF Circuit
Figure 37. Equivalent GAIN− Input Circuit
AVDD2
AVDD2
100Ω
RBIAS
CWx+,
CWx–
Figure 35. Equivalent RBIAS Circuit
Figure 38. Equivalent CWI , CWQ Output Circuit
AVDD2
10Ω
GPOx
Figure 39. Equivalent GPOx Output Circuit
Rev. 0 | Page 18 of 44
AD9279
ULTRASOUND THEORY OF OPERATION
Tx HV AMPLIFIERS
BEAMFORMER
CENTRAL CONTROL
Tx BEAMFORMER
MULTICHANNELS
AD9279
HV
Rx BEAMFORMER
(B AND F MODES)
MUX/
ADC
LNA
VGA
T/R
SWITCHES
DEMUX
AAF
TRANSDUCER
ARRAY
128, 256, ...
ELEMENTS
CW (ANALOG)
BEAMFORMER
IMAGE AND
MOTION
PROCESSING
(B MODE)
SPECTRAL
DOPPLER
PROCESSING
MODE
BIDIRECTIONAL
CABLE
COLOR
DOPPLER (PW)
PROCESSING
(F MODE)
AUDIO
OUTPUT
DISPLAY
Figure 40. Simplified Ultrasound System Block Diagram
The primary application for the AD9279 is medical ultrasound.
Figure 40 shows a simplified block diagram of an ultrasound
system. A critical function of an ultrasound system is the time
gain control (TGC) compensation for physiological signal
attenuation. Because the attenuation of ultrasound signals is
exponential with respect to distance (time), a linear-in-dB VGA
is the optimal solution.
The ADC resolution of 12 bits with up to 80 MSPS sampling
satisfies the requirements of both general-purpose and high
end systems. The power dissipation of the ADC scales with
programmable speed modes for optimum power performance
depending on system architecture.
Power conservation, high performance, and low cost are three
of the most important factors in low end and portable ultra-
sound machines, and the AD9279 is designed to meet these
criteria.
Key requirements in an ultrasound signal chain are very low
noise, active input termination, fast overload recovery, low power,
and differential drive to an ADC. Because ultrasound machines
use beamforming techniques requiring large binary-weighted
numbers of channels (for example, 32 to 512), using the lowest
power at the lowest possible noise is of chief importance.
For additional information regarding ultrasound systems, see
“How Ultrasound System Considerations Influence Front-End
Component Choice,” Analog Dialogue, Volume 36, Number 3,
May–July 2002, and “The AD9271—A Revolutionary Solution
for Portable Ultrasound,” Analog Dialogue, Volume 41, Number 7,
July 2007.
Most modern ultrasound machines use digital beamforming.
In this technique, the signal is converted to digital format
immediately following the TGC amplifier, and then beam-
forming is accomplished digitally.
Rev. 0 | Page 19 of 44
AD9279
CHANNEL OVERVIEW
4LO–
4LO+
RESET
LO
CWI+
CWI–
GENERATION
R
LO-x
FB1
CWQ+
CWQ–
R
LOSW-x
FB2
T/R
SWITCH
C
S
LI-x
DOUTx+
DOUTx–
PIPELINE
ADC
SERIAL
LVDS
ATTENUATOR
–45dB TO 0dB
POST
AMP
AAF
LNA
15.6dB,
17.9dB,
21.3dB
LG-x
C
SH
21dB,
C
LG
24dB,
27dB,
30dB
GAIN
INTERPOLATOR
TRANSDUCER
GAIN–
GAIN+
Figure 41. Simplified Block Diagram of a Single Channel
Each channel contains both a TGC signal path and a CW Doppler
signal path. Common to both signal paths, the LNA provides four
user-adjustable input impedance termination options for
matching different probe impedances. The CW Doppler path
includes an I/Q demodulator with programmable phase rotation
needed for analog beamforming. The TGC path includes a
differential X-AMP® VGA, an antialiasing filter, and an ADC.
Figure 41 shows a simplified block diagram with external
components.
Table 7. Channel Gain Distribution
Section
Nominal Gain (dB)
LNA
15.6/17.9/21.3 (LNAGAIN
)
Attenuator
VGA Amplifier
Filter
0 to −45 (VGAATT)
21/24/27/30 (PGAGAIN
0
0
)
ADC
Each LNA output is dc-coupled to a VGA input. The VGA
consists of an attenuator with a range of −45 dB to 0 dB followed
by an amplifier with 21 dB/24 dB/27 dB/30 dB of gain. The
X-AMP gain interpolation technique results in low gain error
and uniform bandwidth, and differential signal paths minimize
distortion.
TGC OPERATION
The TGC signal path is fully differential throughout to
maximize signal swing and reduce even-order distortion;
however, the LNAs are designed to be driven from a single-
ended signal source. Gain values are referenced from the single-
ended LNA input to the differential ADC input. A simple
exercise in understanding the maximum and minimum gain
requirements is shown in Figure 42.
The linear-in-dB gain (law conformance) range of the TGC path
is 45 dB. The slope of the gain control interface is 28 dB/V, and
the gain control range is −0.8 V to +0.8 V. Equation 3 is the
expression for the differential voltage, VGAIN, at the gain control
interface. Equation 4 is the expression for the VGA attenuation,
The maximum gain required is determined by
VGAATT as a function of VGAIN
.
(ADC Noise Floor/LNA Input Noise Floor) + Margin =
20 log(224/3.1) + 11 dB = 46 dB
V
GAIN (V) = (GAIN+) − (GAIN−)
(3)
(4)
The minimum gain required is determined by
dB
VGAATT (dB) = −28 (0.8 −VGAIN
)
V
(ADC Input FS/LNA Input FS) + Margin =
20 log(2/0.45) − 10 dB = 3 dB
The total channel gain can then be calculated as in Equation 5.
(5)
Therefore, 45 dB of gain range for a 12-bit, 40 MSPS ADC with
15 MHz of bandwidth should suffice in achieving the dynamic
range required for most of today’s ultrasound systems.
ChannelGain (dB) = LNAGAIN +VGAATT + PGAGAIN
The system gain is distributed as listed in Table 7.
Rev. 0 | Page 20 of 44
AD9279
In its default condition, the LNA has a gain of 21.3 dB (12×), and
the VGA postamp gain is 24 dB. If the voltage on the GAIN+
pin is 0 V and the voltage on the GAIN− pin is 0.8 V (44.8 dB
attenuation), the total gain of the channel is 0.5 dB if the LNA
input is unmatched. The channel gain is −5.5 dB if the LNA is
matched to 50 Ω (RFB = 350 Ω). However, if the voltage on the
GAIN+ pin is 1.6 V and the voltage on the GAIN− pin is 0.8 V
(0 dB attenuation), the VGAATT is 0 dB. This results in a total
gain of 45.3 dB through the TGC path if the LNA input is
unmatched or in a total gain of 39.3 dB if the LNA input is
matched.
ADC FULL SCALE (2V p-p)
~6dB MARGIN
MINIMUM GAIN
LNA FULL SCALE
(0.450V p-p SINGLE-ENDED)
70dB
ADC
94dB
>10dB MARGIN
ADC NOISE FLOOR
(224µV rms)
LNA
MAXIMUM GAIN
LNA INPUT-REFERRED
NOISE FLOOR
(3.1µV rms) AT AAF BW = 15MHz
LNA + VGA NOISE = 0.8nV/ Hz
VGA GAIN RANGE > 38dB
MAX CHANNEL GAIN > 47dB
Figure 42. Gain Requirements of TGC Operation for a 12-Bit, 40 MSPS ADC
Rev. 0 | Page 21 of 44
AD9279
Table 8. Sensitivity and Dynamic Range of Trade-Offs1, 2, 3
LNA
VGA
Channel
Gain
Typical Output Dynamic Range (dB)
Input-Referred Noise6 at
GAIN+ = 1.6 V (nV/√Hz)
Full-Scale
Input (V p-p)
Input Noise
(nV/√Hz)
GAIN+ = 0 V4
68.6
GAIN+ = 1.6 V5
66.8
Postamp Gain (dB)
(V/V) (dB)
6
15.6 0.733
0.95
0.85
0.75
21
24
27
30
21
24
27
30
21
24
27
30
1.28
1.15
1.09
1.05
1.07
0.98
0.93
0.91
0.86
0.81
0.78
0.77
68.1
65.0
67.2
62.9
65.8
60.5
7.8
11.6
17.9 0.550
68.6
66.1
68.1
64.3
67.2
62.0
65.8
59.5
21.3 0.367
68.6
64.9
68.1
62.8
67.2
60.4
65.8
57.6
1 LNA: output full scale = 4.4 V p-p differential.
2 Filter: loss ~ 1 dB, NBW = 13.3 MHz, GAIN− = 0.8 V.
3 ADC: 40 MSPS, 70 dB SNR, 2 V p-p full-scale input.
4 Output dynamic range at minimum VGA gain (VGA dominated).
5 Output dynamic range at maximum VGA gain (LNA dominated).
6 Channel noise at maximum VGA gain.
Table 8 demonstrates the sensitivity and dynamic range of
trade-offs that can be achieved relative to various LNA and
VGA gain settings.
the GAIN+ and GAIN− pins. The LNA has three limitations, or
full-scale settings, that can be applied through the SPI. Similarly,
the VGA has four postamp gain settings that can be applied
through the SPI. The voltage applied to the GAIN pins
determines which amplifier (the LNA or VGA) saturates first.
The maximum signal input level prior to 0.1 dB compression on
the output of the LNA that can be applied as a function of
voltage on the GAIN pins for the selectable gain options of the
SPI is shown in Figure 43 to Figure 45.
For example, when the VGA is set for the minimum gain voltage,
the TGC path is dominated by VGA noise and achieves the
maximum output SNR. However, as the postamp gain options
are increased, the input-referred noise is reduced and the SNR
is degraded.
If the VGA is set for the maximum gain voltage, the TGC path
is dominated by LNA noise and achieves the lowest input-
referred noise but with degraded output SNR. The higher the
TGC (LNA + VGC) gain, the lower the output SNR. As the
postamp gain is increased, the input-referred noise is reduced.
1.2
1.0
PGA GAIN = 21dB
0.8
PGA GAIN = 24dB
At low gains, the VGA should limit the system noise performance
(SNR); at high gains, the noise is defined by the source and the
LNA. The maximum voltage swing is bound by the full-scale
peak-to-peak ADC input voltage (2 V p-p).
0.6
0.4
PGA GAIN = 27dB
0.2
Both the LNA and VGA have full-scale limitations within each
section of the TGC path. These limitations are dependent on the
gain setting of each function block and on the voltage applied to
PGA GAIN = 30dB
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
GAIN+ (V)
Figure 43. LNA with 15.6 dB Gain Setting/VGA Full-Scale Limitations
Rev. 0 | Page 22 of 44
AD9279
0.8
0.7
0.6
0.5
set through the SPI. Overload protection ensures quick recovery
time from large input voltages. Because the inputs are
capacitively coupled to a bias voltage near midsupply, very large
inputs can be handled without interacting with the ESD
protection.
PGA GAIN = 21dB
PGA GAIN = 24dB
Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input-
referred noise voltage of 0.75 nV/√Hz (at a gain of 21.3 dB).
On-chip resistor matching results in precise single-ended gains,
which are critical for accurate impedance control. The use of a
fully differential topology and negative feedback minimizes
distortion. Low second-order harmonic distortion is particularly
important in second harmonic ultrasound imaging applications.
Differential signaling enables smaller swings at each output,
further reducing third-order harmonic distortion.
0.4
0.3
0.2
PGA GAIN = 27dB
0.1
0
PGA GAIN = 30dB
0.4 0.6
0
0.2
0.8
1.0
1.2
1.4
1.6
GAIN+ (V)
Figure 44. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations
0.55
0.50
0.45
0.40
Active Impedance Matching
The LNA consists of a single-ended voltage gain amplifier with
differential outputs and the negative output externally available.
For example, with a fixed gain of 8× (17.9 dB), an active input
termination is synthesized by connecting a feedback resistor
between the negative output pin, LO-x, and the positive input
pin, LI-x. This well-known technique is used for interfacing
multiple probe impedances to a single system. The input
resistance is shown in Equation 1.
0.35
0.30
0.25
0.20
0.15
PGA GAIN = 21dB
PGA GAIN = 24dB
PGA GAIN = 27dB
PGA GAIN = 30dB
0.10
0.05
RFB
(1)
RIN
=
A
0
(1+
)
2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
GAIN+ (V)
where A/2 is the single-ended gain or the gain from the LI-x
inputs to the LO-x outputs.
Figure 45. LNA with 21.3 dB Gain Setting/VGA Full-Scale Limitations
Low Noise Amplifier (LNA)
Because the amplifier has a gain of 8× from its input to its
differential output, it is important to note that the gain, A/2,
is the gain from Pin LI-x to Pin LO-x and that it is 6 dB less
than the gain of the amplifier, or 12.1 dB (4×). The input
resistance is reduced by an internal bias resistor of 6 kΩ in
parallel with the source resistance connected to Pin LI-x, with
Pin LG-x ac grounded. Equation 2 can be used to calculate the
required RFB for a desired RIN, even for higher values of RIN.
Good system sensitivity relies on a proprietary ultralow noise
LNA at the beginning of the signal chain, which minimizes the
noise contribution in the following VGA. Active impedance
control optimizes noise performance for applications that
benefit from input impedance matching.
The LNA input, LI-x, is capacitively coupled to the source.
An on-chip bias generator establishes dc input bias voltages of
approximately 2.2 V and centers the output common-mode
levels at 1.5 V (AVDD2 divided by 2). A capacitor, CLG, of the
same value as the input coupling capacitor, CS, is connected
from the LG-x pin to ground.
RFB
(1+ 4)
(2)
RIN
=
||6 k Ω
For example, to set RIN to 200 Ω with a single-ended LNA gain of
12.1 dB (4×), the value of RFB from Equation 1 must be 1000 Ω. If
the simplified equation (Equation 2) is used to calculate RIN, the
value is 194 Ω, resulting in a gain error of less than 0.27 dB.
Some factors, such as the presence of a dynamic source resistance,
may influence the absolute gain accuracy more significantly. At
higher frequencies, the input capacitance of the LNA must be
considered. The user must determine the level of matching
accuracy and adjust RFB accordingly.
It is highly recommended that the LG-x pins form a Kelvin type
connection to the input or probe connection ground. Simply
connecting the LG-x pin to ground near the device can allow
differences in potential to be amplified through the LNA. This
generally shows up as a dc offset voltage that can vary from
channel to channel and part to part depending on the appli-
cation and the layout of the PCB.
The LNA supports a nominal differential output voltage of
4.4 V p-p with positive and negative excursions of 1.1 V from a
common-mode voltage of 1.5 V. The LNA differential gain sets the
maximum input signal before saturation. One of three gains is
R
FB is the resulting impedance of the RFB1 and RFB2 combination
(see Figure 41).Using Register 0x2C in the SPI memory, the
AD9279 can be programmed for four impedance matching
options: three active terminations and unterminated. Table 9
Rev. 0 | Page 23 of 44
AD9279
shows an example of how to select RFB1 and RFB2 for 66 Ω, 100 Ω,
and 200 Ω input impedance for LNA gain = 21.3 dB (12×).
Table 10. Active Termination External Component Values
LNA Gain
(dB)
Minimum
CSH (pF)
RIN (Ω)
50
RFB (Ω)
200
BW (MHz)
Table 9. Active Termination Example for LNA Gain = 21.3 dB,
RFB1 = 700 Ω, RFB2 = 1400 Ω
15.6
17.9
21.3
15.6
17.9
21.3
15.6
17.9
21.3
90
57
69
88
57
69
88
72
72
72
50
250
70
Register
0x2C
Value
50
350
50
LO-x
Switch
LOSW-x
Switch
RIN (Ω)
(Eq. 1)
100
100
100
200
200
200
400
500
700
800
1000
1400
30
20
10
N/A
N/A
N/A
Rs (Ω)
RFB (Ω)
00
100
On
Off
RFB1
100
(default)
01
10
50
200
On
Off
On
On
RFB1||RFB2
RFB2
66
200
11
N/A
Off
Off
∞
∞
LNA Noise
The bandwidth (BW) of the LNA is greater than 100 MHz.
Ultimately, the BW of the LNA limits the accuracy of the
synthesized RIN. For RIN = RS up to about 200 Ω, the best match
is between 100 kHz and 10 MHz, where the lower frequency
limit is determined by the size of the ac coupling capacitors, and
the upper limit is determined by the LNA BW. Furthermore, the
input capacitance and RS limit the BW at higher frequencies.
Figure 46 shows RIN vs. frequency for various values of RFB.
1k
The short-circuit noise voltage (input-referred noise) is an
important limit on system performance. The short-circuit noise
voltage for the LNA is 0.75 nV/√Hz at a gain of 21.3 dB, including
the VGA noise at a VGA postamp gain of 27 dB. These measure-
ments, which were taken without a feedback resistor, provide
the basis for calculating the input noise and noise figure (NF)
performance of the configurations shown in Figure 47.
UNTERMINATED
R
IN
R
S
R
= 500Ω, R = 2kΩ
FB
S
+
–
V
OUT
LI-x
R
R
= 200Ω, R = 800Ω
S
FB
SHUNT TERMINATION
R
= 100Ω, R = 400Ω, C = 20pF
IN
S
FB
SH
R
100
S
+
–
R
S
V
R
= 50Ω, R = 200Ω, C = 70pF
FB SH
OUT
S
LI-x
ACTIVE TERMINATION
R
FB
R
IN
R
S
10
100k
1M
10M
100M
+
–
V
OUT
FREQUENCY (Hz)
LI-x
Figure 46. RIN vs. Frequency for Various Values of RFB
(Effects of RSH and CSH Are Also Shown)
R
FB
R
=
IN
1 + A/2
Note that, at the lowest value of RIN (50 Ω), RIN peaks at frequencies
greater than 10 MHz. This is due to the BW roll-off of the LNA.
Figure 47. Input Configurations
However, as can be seen for larger RIN values, parasitic capaci-
tance starts rolling off the signal BW before the LNA can produce
peaking. CSH further degrades the match; therefore, CSH should
not be used for values of RIN that are greater than 100 Ω.
Figure 48 and Figure 49 are simulations of noise figure vs. RS
results using these configurations and an input-referred noise
voltage of 2.5 nV/√Hz for the VGA. Unterminated (RFB = ∞)
operation exhibits the lowest equivalent input noise and noise
figure. Figure 49 shows the noise figure vs. source resistance
rising at low RS—where the LNA voltage noise is large compared
with the source noise—and at high RS due to the noise contribution
from RFB. The lowest NF is achieved when RS matches RIN.
Table 10 lists the recommended values for RFB and CSH in terms
of RIN.
CFB is needed in series with RFB because the dc levels at Pin LO-x
and Pin LI-x are unequal.
Rev. 0 | Page 24 of 44
AD9279
The main purpose of input impedance matching is to improve the
transient response of the system. With shunt termination, the input
noise increases due to the thermal noise of the matching resistor
and the increased contribution of the LNA input voltage noise
generator. With active termination, however, the contributions
of both are smaller (by a factor of 1/(1 + LNA Gain)) than they
would be for shunt termination.
Input Overdrive
Excellent overload behavior is of primary importance in
ultrasound. Both the LNA and VGA have built-in overdrive
protection and quickly recover after an overload event.
As with any amplifier, voltage clamping prior to the inputs
is highly recommended if the application is subject to high
transient voltages.
Figure 48 shows the relative noise figure performance. With an
LNA gain of 21.3 dB, the input impedance was swept with RS to
preserve the match at each point. The noise figures for a source
impedance of 50 ꢀ are 7.3 dB, 4.2 dB, and 2.8 dB for the shunt
termination, active termination, and unterminated configurations,
respectively. The noise figures for 200 ꢀ are 4.5 dB, 1.7 dB, and
1.0 dB, respectively.
Figure 50 shows a simplified ultrasound transducer interface.
A common transducer element serves the dual functions of
transmitting and receiving ultrasound energy. During the
transmitting phase, high voltage pulses are applied to the ceramic
elements. A typical transmit/receive (T/R) switch can consist of
four high voltage diodes in a bridge configuration. Although the
diodes ideally block transmit pulses from the sensitive receiver
input, diode characteristics are not ideal, and the resulting leakage
transients imposed on the LI-x inputs can be problematic.
Figure 49 shows the noise figure as it relates to RS for various
values of RIN, which is helpful for design purposes.
12.0
The external input overload protection scheme also contains a
pair of back-to-back signal diodes that should be in place prior to
the ac coupling capacitors. Keep in mind that all diodes are prone
to exhibiting some amount of shot noise. Many types of diodes are
available for achieving the desired noise performance. The
configuration shown in Figure 50 tends to add 2 nV/√Hz of
input-referred noise. Decreasing the 5 kΩ resistor and increasing
the 2 kΩ resistor may improve noise contribution, depending on
the application. With the diodes shown in Figure 50, clamping
levels of 0.5 V or less significantly enhance the overload
performance of the system.
10.5
9.0
7.5
SHUNT TERMINATION
6.0
4.5
3.0
ACTIVE TERMINATION
UNTERMINATED
1.5
0
Because ultrasound is a pulse system and time-of-flight is used
to determine depth, quick recovery from input overloads is
essential. Overload can occur in the preamplifier and in the
VGA. Immediately following a transmit pulse, the typical VGA
gains are low, and the LNA is subject to overload from T/R
switch leakage. With increasing gain, the VGA can become
overloaded due to strong echoes that occur near field echoes
and acoustically dense materials, such as bone.
10
100
(Ω)
1k
R
S
Figure 48. Noise Figure vs. RS for Shunt Termination, Active
Termination Matched and Unterminated Inputs, VGAIN = 1.6 V
8
R
R
R
R
= 50Ω
= 75Ω
= 100Ω
= 200Ω
IN
IN
IN
IN
7
6
5
4
3
2
1
0
UNTERMINATED
+5V
Tx
DRIVER
5kΩ
HV
AD9279
10nF
LNA
2kΩ
10nF
5kΩ
TRANSDUCER
–5V
Figure 50. Input Overload Protection
10
100
(Ω)
1k
R
S
Figure 49. Noise Figure vs. RS for Various Fixed Values of RIN
,
Active Termination Matched Inputs, VGAIN = 1.6 V
Rev. 0 | Page 25 of 44
AD9279
Variable Gain Amplifier (VGA)
VGA Noise
The differential X-AMP VGA provides precise input attenu-
ation and interpolation. It has a low input-referred noise of
2.5 nV/√Hz and excellent gain linearity. The VGA is driven by
a fully differential input signal from the LNA. The X-AMP archi-
tecture produces a linear-in-dB gain law conformance and low
distortion levels—only deviating 0.5 dB or less from the ideal.
The gain slope is monotonic with respect to the control voltage
and is stable with variations in process, temperature, and supply.
The resulting total gain range is 45 dB, which allows for range
loss at the endpoints.
In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. The
input-referred noise of the LNA limits the minimum resolvable
input signal, whereas the output-referred noise, which depends
primarily on the VGA, limits the maximum instantaneous
dynamic range that can be processed at any one particular gain
control voltage. This latter limit is set in accordance with the
total noise floor of the ADC.
Output-referred noise as a function of GAIN+ is shown in
Figure 7, Figure 8, and Figure 10 for the short-circuit input
conditions. The input noise voltage is simply equal to the output
noise divided by the measured gain at each point in the control
range.
The X-AMP inputs are part of a programmable gain feedback
amplifier (PGA) that completes the VGA. The PGA in the VGA
can be programmed to a gain of 21 dB, 24 dB, 27 dB, or 30 dB.
This allows for optimization of channel gain for different imaging
modes in the ultrasound system. The VGA bandwidth is
approximately 100 MHz. The input stage is designed to ensure
excellent frequency response uniformity across the gain setting.
For TGC mode, this minimizes time delay variation across the
gain range.
The output-referred noise is a flat 40 nV/√Hz (postamp gain =
24 dB) over most of the gain range because it is dominated by
the fixed output-referred noise of the VGA. At the high end of
the gain control range, the noise of the LNA and of the source
prevail. The input-referred noise reaches its minimum value
near the maximum gain control voltage, where the input-
referred contribution of the VGA is miniscule.
Gain Control
The gain control interface, GAIN , is a differential input. VGAIN
varies the gain of all VGAs through the interpolator by selecting
the appropriate input stages connected to the input attenuator.
For GAIN− at 0.8 V, the nominal GAIN+ range for 29.4 dB/V is
0 V to 1.6 V, with the best gain linearity from approximately
0.16 V to 1.44 V, where the error is typically less than 0.5 dB.
For GAIN+ voltages greater than 1.44 V and less than 0.16 V,
the error increases. The value of GAIN+ can exceed the supply
voltage by 1 V without gain foldover.
At lower gains, the input-referred noise and, therefore, the
noise figure, increases as the gain decreases. The instantaneous
dynamic range of the system is not lost, however, because the
input capacity increases as the input-referred noise increases.
The contribution of the ADC noise floor has the same depen-
dence. The important relationship is the magnitude of the VGA
output noise floor relative to that of the ADC.
Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resultant noise is proportional to the output
signal level and is usually evident only when a large signal is
present. The gain interface includes an on-chip noise filter,
which significantly reduces this effect at frequencies above
5 MHz. Care should be taken to minimize noise impinging at
the GAIN inputs. An external RC filter can be used to remove
Gain control response time is less than 750 ns to settle within 10%
of the final value for a change from minimum to maximum gain.
There are two ways in which the GAIN+ and GAIN− pins can
be interfaced. Using a single-ended method, a Kelvin type of
connection to ground can be used, as shown in Figure 51. For
driving multiple devices, it is preferable to use a differential
method, as shown in Figure 52. In either method, the GAIN+
and GAIN− pins should be dc-coupled and driven to accom-
modate a 1.6 V full-scale input.
V
GAIN source noise. The filter bandwidth should be sufficient to
accommodate the desired control bandwidth.
Antialiasing Filter (AAF)
The filter that the signal reaches prior to the ADC is used to
reject dc signals and to band limit the signal for antialiasing.
The antialiasing filter is a combination of a single-pole high-
pass filter and a second-order low-pass filter. The high-pass
filter can be configured at a ratio of the low-pass filter cutoff.
This is selectable through the SPI.
AD9279
100Ω
0V TO 1.6V DC
GAIN+
0.01µF
GAIN–
KELVIN
CONNECTION
0.01µF
Figure 51. Single-Ended GAIN Pin Configuration
AVDD2
The filter uses on-chip tuning to trim the capacitors and, in
turn, to set the desired cutoff frequency and reduce variations.
The default −3 dB low-pass filter cutoff is 1/3 or 1/4.5 the ADC
sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1,
1.2, or 1.3 times this frequency through the SPI. The cutoff
tolerance is maintained from 8 MHz to 18 MHz.
499Ω
±0.4V DC
AT 0.8V CM
31.3kΩ
AD9279
499Ω
100Ω
±0.8V DC
GAIN+
0.8V CM
0.01µF
AD8138
100Ω
523Ω
10kΩ
GAIN–
±0.4V DC
AT 0.8V CM
0.01µF
499Ω
Figure 52. Differential GAIN Pin Configuration
Rev. 0 | Page 26 of 44
AD9279
Tuning is normally off to avoid changing the capacitor settings
during critical times. The tuning circuit is enabled through the
SPI. It is disabled automatically after 512 cycles of the ADC
sample clock. Initializing the tuning of the filter must be
performed after initial power-up and after reprogramming the
filter cutoff scaling or ADC sample rate.
feeding through to other portions of the AD9279, and it
preserves the fast rise and fall times of the signal, which are
critical to low jitter performance.
3.3V
®
MINI-CIRCUITS
ADT1-1WT, 1:1Z
0.1µF
0.1µF
XFMR
CLK+
OUT
100Ω
A total of eight SPI-programmable settings allows the user to
vary the high-pass filter cutoff frequency as a function of the
low-pass cutoff frequency. Two examples are shown in Table 11:
one is for an 8 MHz low-pass cutoff frequency, and the other is
for an 18 MHz low-pass cutoff frequency. In both cases, as the
ratio decreases, the amount of rejection on the low-end fre-
quencies increases. Therefore, making the entire AAF frequency
pass band narrow can reduce low frequency noise or maximize
dynamic range for harmonic processing.
50Ω
AD9279
0.1µF
VFAC3
CLK–
SCHOTTKY
DIODES:
HSM2812
0.1µF
Figure 53. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac-couple
a differential PECL signal to the sample clock input pins, as
shown in Figure 54. The AD951x family of clock drivers offers
excellent jitter performance.
3.3V
Table 11. SPI-Selectable High-Pass Filter Cutoff Options
AD951x FAMILY
High-Pass Cutoff Frequency
VFAC3
OUT
0.1µF
0.1µF
CLK+
CLK
PECL DRIVER
CLK
Low-Pass
Cutoff = 8 MHz
Low-Pass
Cutoff = 18 MHz
SPI Setting Ratio1
50Ω*
0.1µF
100Ω
AD9279
0
1
2
3
4
5
6
7
12.00
8.57
6.67
5.46
4.62
4.00
3.53
3.16
670 kHz
930 kHz
1.2 MHz
1.47 MHz
1.73 MHz
2.0 MHz
2.27 MHz
2.53 MHz
1.5 MHz
2.1 MHz
2.7 MHz
3.3 MHz
3.9 MHz
4.5 MHz
5.1 MHz
5.7 MHz
0.1µF
CLK–
240Ω
240Ω
*50Ω RESISTOR IS OPTIONAL.
Figure 54. Differential PECL Sample Clock
3.3V
AD951x FAMILY
VFAC3
OUT
0.1µF
0.1µF
CLK+
CLK
LVDS DRIVER
CLK
1 Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency.
50Ω*
0.1µF
100Ω
AD9279
ADC
0.1µF
CLK–
The AD9279 uses a pipelined ADC architecture. The quantized
output from each stage is combined into a 12-bit result in the
digital correction logic. The pipelined architecture permits the
first stage to operate on a new input sample and the remaining
stages to operate on preceding samples. Sampling occurs on the
rising edge of the clock.
*50Ω RESISTOR IS OPTIONAL.
Figure 55. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 56). Although the
CLK+ input circuit supply is AVDD1 (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
selection of the drive logic voltage very flexible.
3.3V
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and output clocks.
Clock Input Considerations
For optimum performance, the AD9279 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
AD951x FAMILY
0.1µF
VFAC3
OUT
CLK
CMOS DRIVER
CLK
OPTIONAL
100Ω
0.1µF
50Ω*
Figure 53 shows the preferred method for clocking the AD9279.
A low jitter clock source, such as the Valpey Fisher oscillator,
VFAC3-BHL-50 MHz, is converted from single-ended to differ-
ential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9279 to approximately 0.8 V p-p differential. This
helps to prevent the large voltage swings of the clock from
CLK+
AD9279
0.1µF
CLK–
0.1µF
39kΩ
*50Ω RESISTOR IS OPTIONAL.
Figure 56. Single-Ended 1.8 V CMOS Sample Clock
Rev. 0 | Page 27 of 44
AD9279
3.3V
130
120
110
100
90
RMS CLOCK JITTER REQUIREMENT
AD951x FAMILY
0.1µF
50Ω*
VFAC3
OUT
CLK
CMOS DRIVER
CLK
OPTIONAL
100Ω
0.1µF
0.1µF
CLK+
16 BITS
AD9279
14 BITS
12 BITS
0.1µF
CLK–
80
70
10 BITS
*50Ω RESISTOR IS OPTIONAL.
60
0.125ps
Figure 57. Single-Ended 3.3 V CMOS Sample Clock
8 BITS
0.25ps
50
0.5ps
1.0ps
2.0ps
40
Clock Duty Cycle Considerations
30
1
10
100
1000
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9279 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9279. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See Table 19 for more details on
using this feature.
ANALOG INPUT FREQUENCY (MHz)
Figure 58. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 59 and Figure 60, the power dissipated by
the AD9279 is proportional to its sample rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and the bias current of the
LVDS output drivers.
350
300
250
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
200
150
100
Clock Jitter Considerations
50
0
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated as follows:
0
10
20
30
40
50
60
70
80
SAMPLING FREQUENCY (MSPS)
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
Figure 59. Supply Current vs. fSAMPLE for fIN = 5 MHz
180
170
160
150
140
130
120
110
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 58).
MODE III, fSAMPLE = 80MSPS
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9279.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources, such as the Valpey Fisher VFAC3 series.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the original
clock during the last step.
MODE II, fSAMPLE = 65MSPS
MODE I, fSAMPLE = 40MSPS
0
10
20
30
40
50
60
70
80
SAMPLING FREQUENCY (MSPS)
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about how
jitter performance relates to ADCs (visit www.analog.com).
Figure 60. Power per Channel vs. fSAMPLE for fIN = 5 MHz
The AD9279 features scalable LNA bias currents (see Table 19,
Register 0x12). The default LNA bias current settings are high.
Rev. 0 | Page 28 of 44
AD9279
Figure 61 shows the typical reduction of AVDD2 current with
each bias setting. It is also recommended that the LNA offset be
adjusted using Register 0x10 (see Table 19) when the LNA bias
setting is low.
A number of other power-down options are available when
using the SPI port interface. The user can individually power
down each channel or put the entire device into standby mode.
This allows the user to keep the internal PLL powered up when
fast wake-up times are required. The wake-up time is slightly
dependent on gain. To achieve a 1 ꢁs wake-up time when the
device is in standby mode, 0.8 V must be applied to the GAIN
pins. See Table 19 for more details on using these features.
HIGH
MID-HIGH
Power and Ground Recommendations
When connecting power to the AD9279, it is recommended that
two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one 1.8 V supply is
available, it should be routed to the AVDD1 pin first and then
tapped off and isolated with a ferrite bead or a filter choke
preceded by decoupling capacitors for the DRVDD pin. The
user should employ several decoupling capacitors on all
supplies to cover both high and low frequencies. Locate these
capacitors close to the point of entry at the PCB level and close
to the part, with minimal trace lengths.
MID-LOW
LOW
180
190
200
210
220
230
240
250
260
TOTAL AVDD2 CURRENT (mA)
Figure 61. AVDD2 Current at Different LNA Bias Settings, fSAMPLE = 40 MSPS
By asserting the PDWN pin high, the AD9279 is placed into
power-down mode. In this state, the device typically dissipates
5 mW. During power-down, the LVDS output drivers are placed
into a high impedance state. The AD9279 returns to normal
operating mode when the PDWN pin is pulled low. This pin
is both 1.8 V and 3.3 V tolerant.
A single PCB ground plane should be sufficient when using the
AD9279. With proper decoupling and smart partitioning of the
analog, digital, and clock sections of the PCB, optimum perfor-
mance can be easily achieved.
Digital Outputs and Timing
The AD9279 differential outputs conform to the ANSI-644
LVDS standard on default power-up. This can be changed to
a low power, reduced signal option similar to the IEEE 1596.3
standard via the SPI, using Register 0x14, Bit 6. This LVDS
standard can further reduce the overall power dissipation of the
device by approximately 36 mW.
By asserting the STBY pin high, the AD9279 is placed into a
standby mode. In this state, the device typically dissipates
175 mW. During standby, the entire part is powered down
except the internal references. The LVDS output drivers are
placed into a high impedance state. This mode is well suited for
applications that require power savings because it allows the
device to be powered down when not in use and then quickly
powered up. The time to power the device back up is also greatly
reduced. The AD9279 returns to normal operating mode when
the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V
tolerant.
The LVDS driver current is derived on chip and sets the output
current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing at the receiver.
The AD9279 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point network topologies are recommended with
a 100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length be no longer than 24 inches and that the
differential output traces be kept close together and at equal
lengths. An example of the FCO (CH2), DCO (CH1), and data
(CH3) stream with proper trace length and position is shown in
Figure 62.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on VREF are discharged
when entering power-down mode and must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in the power-down mode: shorter
cycles result in proportionally shorter wake-up times. To restore
the device to full operation, approximately 0.5 ms is required
when using the recommended 1 ꢁF and 0.1 ꢁF decoupling
capacitors on the VREF pin and the 0.01 ꢁF decoupling
capacitors on the GAIN pins. Most of this time is dependent
on the gain decoupling: higher value decoupling capacitors on
the GAIN pins result in longer wake-up times.
Rev. 0 | Page 29 of 44
AD9279
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 960 Mbps
(12 bits × 80 MSPS = 960 Mbps). The lowest typical conversion
rate is 10 MSPS, but the PLL can be set up for encode rates as
low as 5 MSPS via the SPI if lower sample rates are required for
a specific application. See Table 19 for details on enabling this
feature.
600
EYE: ALL BITS
ULS: 2398/2398
400
200
5.0ns/DIV
CH1 500mV/DIV = DCO
CH2 500mV/DIV = DATA
CH3 500mV/DIV = FCO
100
Figure 62. LVDS Output Timing Example in ANSI-644 Mode (Default)
0
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on regular FR-4 material
is shown in Figure 63. Figure 64 shows an example of the trace
lengths exceeding 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position; therefore,
the user must determine whether the waveforms meet the timing
budget of the design when the trace lengths exceed 24 inches.
–100
–200
–400
–600
–1.5ns
–1.0ns –0.5ns
0ns
0.5ns
1.0ns
1.5ns
25
20
Additional SPI options allow the user to further increase the
internal termination (and, therefore, increase the current) of all
eight outputs to drive longer trace lengths (see Figure 65). Even
though this produces sharper rise and fall times on the data
edges, is less prone to bit errors, and improves frequency
distribution (see Figure 65), the power dissipation of the
DRVDD supply increases when this option is used.
15
10
5
In cases that require increased driver strength to the DCO and
FCO outputs because of load mismatch, Register 0x15 allows
the user to double the drive strength. To do this, set the appro-
priate bit in Register 0x05. Note that this feature cannot be used
with Bits[5:4] in Register 0x15 because these bits take precedence
over this feature. See Table 19 for more details.
0
–200ps
–100ps
0ps
100ps
200ps
Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Less Than 24 Inches on Standard FR-4
The format of the output data is offset binary by default. Table 12
provides an example of the output coding format. To change the
output data format to twos complement, see the Memory Map
section.
Table 12. Digital Output Coding
(VIN+) − (VIN−),
Code Input Span = 2 V p-p (V)
Digital Output
Offset Binary (D11 to D0)
4095
2048
2047
0
+1.00
0.00
−0.000488
−1.00
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
Rev. 0 | Page 30 of 44
AD9279
400
300
600
400
200
EYE: ALL BITS
EYE: ALL BITS
ULS: 2396/2396
ULS: 2399/2399
200
100
0
0
–100
–200
–300
–400
–200
–400
–600
–1.5ns
–1.0ns –0.5ns
0ns
0.5ns
1.0ns
1.5ns
–1.5ns
–1.0ns –0.5ns
0ns
0.5ns
1.0ns
1.5ns
25
20
25
20
15
10
5
15
10
5
0
0
–200ps
–100ps
0ps
100ps
200ps
–200ps
–100ps
0ps
100ps
200ps
Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω
Termination On and Trace Lengths of Greater Than 24 Inches on Standard FR-4
Figure 64. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Greater than 24 Inches on Standard FR-4
Rev. 0 | Page 31 of 44
AD9279
Two output clocks are provided to assist in capturing data from
the AD9279. DCO is used to clock the output data and is equal
to six times the sampling clock rate. Data is clocked out of the
AD9279 and must be captured on the rising and falling edges
of DCO , which supports double data rate (DDR) capturing.
The frame clock output (FCO ) is used to signal the start of a
new output byte and is equal to the sampling clock rate. See the
timing diagram shown in Figure 2 for more information.
stream. However, this order this can be inverted so that the LSB is
represented first in the data output serial stream (see Figure 3).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This feature is useful when
validating receiver capture and timing. See Table 13 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns may not adhere to the data format select option. In
addition, custom user-defined test patterns can be assigned in
the user pattern registers (Address 0x19 through Address 0x1C).
All test mode options except PN sequence short and PN sequence
long can support 8- to 14-bit word lengths to verify data capture
to the receiver.
An 8-, 10-, or 14-bit serial stream can also be initiated from the
SPI. This allows the user to implement different serial streams and
to test device compatibility with lower and higher resolution
systems. When changing the resolution to an 8- or 10-bit serial
stream, the data stream is shortened. When using the 14-bit
option, the data stream stuffs two 0s at the end of the normal
12-bit serial data.
The PN sequence short pattern produces a pseudo random
bit sequence that repeats itself every 29 − 1 bits, or 511 bits. A
description of the PN sequence short and how it is generated
can be found in Section 5.1 of the ITU-T O.150 (05/96) standard.
The only difference is that the starting value is a specific value
instead of all 1s (see Table 14 for the initial values).
When using the SPI, all of the data outputs can also be inverted
from their nominal state by setting Bit 2 in the OUTPUT_MODE
register (Address 0x14). This is not to be confused with inverting
the serial stream to an LSB first mode. In default mode, as shown
in Figure 2, the MSB is represented first in the data output serial
Table 13. Flexible Output Test Modes1
Output Test Mode
Bit Sequence
Subject to Data
Format Select
Pattern Name
Off (default)
Digital Output Word 1
N/A
Digital Output Word 2
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
N/A
Same
Same
Same
0101 0101 0101
N/A
N/A
N/A
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No
Midscale short
+Full-scale short
−Full-scale short
Checkerboard
PN sequence long
PN sequence short
One-/zero-word toggle
User input
1000 0000 0000
1111 1111 1111
0000 0000 0000
1010 1010 1010
N/A
N/A
1111 1111 1111
0000 0000 0000
Register 0x19 and Register 0x1A Register 0x1B and Register 0x1C
1-/0-bit toggle
1× sync
One bit high
1010 1010 1010
0000 0011 1111
1000 0000 0000
1010 0011 0011
N/A
N/A
N/A
N/A
1100
Mixed bit frequency
1 N/A is not applicable.
Rev. 0 | Page 32 of 44
AD9279
These capacitor values are recommended for the ADC to
properly settle and acquire the next valid sample.
The PN sequence long pattern produces a pseudo random bit
sequence that repeats itself every 223 − 1 bits, or 8,388,607 bits.
A description of the PN sequence long and how it is generated
can be found in Section 5.6 of the ITU-T O.150 (05/96) standard.
The only differences are that the starting value is a specific value
instead of all 1s and that the AD9279 inverts the bit stream with
relation to the ITU-T standard (see Table 14 for the initial
values).
The reference settings can be selected using the SPI. The settings
allow two options: using the internal reference or using an
external reference. The internal reference option is the default
setting and has a resulting differential span of 2 V p-p.
Table 15. SPI-Selectable Reference Settings
Resulting Resulting Differential
SPI-Selected Mode
VREF (V)
Span (V p-p)
2 × external reference
2.0
Table 14. PN Sequence
External Reference
Internal Reference (Default) 1.0
N/A
Initial
Value
First Three Output Samples
(MSB First)
Sequence
PN Sequence Short 0x0DF
PN Sequence Long
0xDF9, 0x353, 0x301
0x29B80A 0x591, 0xFD7, 0x0A3
CW DOPPLER OPERATION
Each channel of the AD9279 includes a I/Q demodulator. Each
demodulator has an individual programmable phase shifter. The
I/Q demodulator is ideal for phased array beamforming applica-
tions in medical ultrasound. Each channel can be programmed
for 16 delay states/360° (or 22.5°/step), selectable via the SPI port.
The part has a RESET input used to synchronize the LO dividers of
each channel. If multiple AD9279s are used, a common RESET
across the array ensures a synchronized phase for all channels.
Internal to the AD9279, the individual Channel I and Channel Q
outputs are current summed. If multiple AD9279s are used, the
I and Q outputs from each AD9279 can be current summed and
converted to a voltage using an external transimpedance amplifier.
See the Memory Map section for information on how to change
these additional digital output timing features through the SPI.
SDIO Pin
This pin is required to operate the SPI. It has an internal 30 kΩ
pull-down resistor that pulls this pin low and is only 1.8 V
tolerant. If applications require that this pin be driven from a
3.3 V logic level, insert a 1 kΩ resistor in series with this pin to
limit the current.
SCLK Pin
This pin is required to operate the SPI port interface. It has an
internal 30 kΩ pull-down resistor that pulls this pin low and is
both 1.8 V and 3.3 V tolerant.
Quadrature Generation
The internal 0° and 90° LO phases are digitally generated by
a divide-by-4 logic circuit. The divider is dc-coupled and
inherently broadband; the maximum LO frequency is limited
only by its switching speed. The duty cycle of the quadrature LO
signals is intrinsically 50% and is unaffected by the asymmetry
of the externally connected 4LO input. Furthermore, the divider
is implemented such that the 4LO signal reclocks the final flip-
flops that generate the internal LO signals and, thereby,
CSB Pin
This pin is required to operate the SPI port interface. It has an
internal 70 kΩ pull-up resistor that pulls this pin high and is
both 1.8 V and 3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a
resistor other than the recommended 10.0 kΩ resistor for RBIAS
degrades the performance of the device. Therefore, it is imperative
that at least a 1% tolerance on this resistor be used to achieve
consistent performance.
minimizes noise introduced by the divide circuitry.
For optimum performance, the 4LO input is driven differen-
tially, as on the AD9279 evaluation board (see the Ordering
Guide). The common-mode voltage on each pin is approx-
imately 1.2 V with the nominal 3 V supply. It is important to
ensure that the LO source have very low phase noise (jitter), a
fast slew rate, and an adequate input level to obtain optimum
performance of the CW signal chain.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9279. This is gained up internally by a factor of 2, setting
VREF to 1.0 V, which results in a full-scale differential input span
of 2.0 V p-p for the ADC. VREF is set internally by default, but
the VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy. However, the AD9279 does not support
ADC full-scale ranges below 2.0 V p-p.
Beamforming applications require a precise channel-to-channel
phase relationship for coherence among multiple channels. A
RESET pin is provided to synchronize the LO divider circuits
in different AD9279s when they are used in arrays. The RESET
pin resets the dividers to a known state after power is applied to
multiple AD9279s. Accurate channel-to-channel phase matching
can only be achieved via a common pulse on the RESET pin when
using more than one AD9279.
When applying the decoupling capacitors to the VREF pin,
use ceramic, low ESR capacitors. These capacitors should be
close to the reference pin and on the same layer of the PCB as
the AD9279. The VREF pin should have both a 0.1 ꢁF capacitor
and a 1 ꢁF capacitor connected in parallel to the analog ground.
Rev. 0 | Page 33 of 44
AD9279
I/Q Demodulator and Phase Shifter
Dynamic Range and Noise
The I/Q demodulators consist of double-balanced passive mixers.
The RF input signals are converted into currents by transconduc-
tance stages that have a maximum differential input signal
capability matching the LNA output full scale. These currents
are then presented to the mixers, which convert them to base-
band (RF − LO) and twice RF (RF + LO). The signals are phase
shifted according to the codes programmed into the SPI latch
(see Table 16). The phase shift function is an integral part of the
overall circuit. The phase shift listed in Column 1 of Table 16 is
defined as being between the baseband I or Q channel outputs.
As an example, for a common signal applied to a pair of RF inputs
to an AD9279, the baseband outputs are in phase for matching
phase codes. However, if the phase code for Channel 1 is 0000
and that of Channel 2 is 0001, then Channel 2 leads Channel 1
by 22.5°.
Figure 66 is an interconnection block diagram of all eight
channels of the AD9279. Two stages of ADA4841 amplifiers are
used. The first stage does an I-to-V conversion and filters the
high frequency content that results from the demodulation
process. In beamforming applications, the I and Q outputs of a
number of receiver channels are summed. In the AD9279, the
summation of eight channels is the input to the first stage of the
ADA4841s. The second stage of ADA4841 amplifiers is used to
do the summation of additional AD9279 to ADA4841 outputs,
provide gain, and drive the AD7982, 18-bit SAR ADC. The
dynamic range of the system increases by the factor 10log10(N),
where N is the total number of channels (assuming random
uncorrelated noise). The noise in the 8-channel example of
Figure 66 is increased by 9 dB while the signal quadruples (18 dB),
yielding an aggregate SNR improvement of (18 − 9) = 9 dB.
The output-referred noise of the CW signal path depends on
the LNA gain and the selection of the first stage summing
amplifier and the value of RFILT. To determine the output
referred noise, it is important to know the active low-pass filter
(LPF) values RA, RFILT, and CFILT, shown in Figure 66. Typical
filter values for all eight channels of a single AD9279 are 100 Ω
for RA, 500 Ω for RFILT, and 2.0 nF for CFILT; these values
implement a 100 kHz single-pole LPF.
Table 16. Phase Select Code for Channel-to-Channel Phase Shift
I/Q Demodulator Phase
(SPI Register 0x2D[3:0])
Φ Shift
0°
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
22.5°
45°
67.5°
90°
112.5°
135°
157.5°
180°
If the RF and LO are offset by 10 kHz, the demodulated signal is
10 kHz and is passed by the LPF. The single-channel mixing gain
from the RF input to the ADA4841 output (for example, I1´,
Q1´) is approximately the LNA gain for RFILT and CFILT of 500 Ω
and 2.0 nF.
202.5°
225°
247.5°
270°
This gain can be increased by increasing the filter resistor while
maintaining the corner frequency. The factor limiting the mag-
nitude of the gain is the output swing and drive capability of the
op amp selected for the I-to-V converter, in this example, the
ADA4841. Because any amplifier has limited drive capability,
there is a finite number of channels that can be summed.
292.5°
315°
337.5°
Rev. 0 | Page 34 of 44
AD9279
RFILT
CFILT
CWI+
CWI–
Φ
Φ
AD7982
50Ω
50Ω
1.5V
1.5V
2.5V
2.5V
LNA
CHANNEL A
ADA4841
CFILT
ADA4841
18-BIT ADC
I
4nF
RA
RFILT
RFILT
CFILT
RA
CWQ+
CWQ–
AD7982
50Ω
50Ω
Φ
Φ
1.5V
1.5V
2.5V
2.5V
ADA4841
ADA4841
18-BIT ADC
Q
LNA
CHANNEL H
4nF
RA
CFILT
RFILT
4
LO
GENERATION
AD9279
Figure 66. Typical Connection Interface for I/Q Outputs in CW Mode
The resultant I and Q signals are filtered and then sampled by
two high resolution analog-to-digital converters. The sampled
signals are processed to extract the relevant Doppler information.
Phase Compensation and Analog Beamforming
Beamforming, as applied to medical ultrasound, is defined as
the phase alignment and summation of signals generated from a
common source but received at different times by a multielement
ultrasound transducer. Beamforming has two functions: it imparts
directivity to the transducer, enhancing its gain, and it defines a
focal point within the body from which the location of the return-
ing echo is derived. The primary application for the AD9279 I/Q
demodulators is in analog beamforming circuits for ultrasound
CW Doppler.
Alternatively, the RF signal can be processed by downconversion
on each channel individually, phase shifting the downconverted
signal, and then combining all channels. Because the dynamic
range expansion from beamforming occurs after demodulation,
the demodulator dynamic range has little effect on the output
dynamic range. The AD9279 implements this architecture. The
downconversion is done by an I/Q demodulator on each channel,
and the summed current output is the same as in the delay line
approach. The subsequent filters after the I-to-V conversion
and the ADCs are similar.
Modern ultrasound machines used for medical applications
employ an array of receivers for beamforming, with typical CW
Doppler array sizes of up to 64 receiver channels that are phase
shifted and summed together to extract coherent information.
When used in multiples, the desired signals from each of the
channels can be summed to yield a larger signal (increased by a
factor N, where N is the number of channels), whereas the noise
is increased by the square root of the number of channels. This
technique enhances the signal-to-noise performance of the
machine. The critical elements in a beamformer design are the
means to align the incoming signals in the time domain and the
means to sum the individual signals into a composite whole.
For CW Doppler operation, the AD9279 integrates the LNA,
phase shifter, frequency conversion, and I/Q demodulation
into a single package and directly yields the baseband signal.
Figure 67 is a simplified diagram showing the concept for four
channels. The ultrasound wave (US wave) is received by four
transducer elements, TE1 through TE4, in an ultrasound probe
and generates signals E1 through E4. In this example, the phase
at TE1 leads the phase at TE2 by 45°.
In a real application, the phase difference depends on the
element spacing, wavelength (λ), speed of sound, angle of
incidence, and other factors. In Figure 67, the signals E1
through E4 are amplified by the low noise amplifiers. For
optimum signal-to-noise performance, the output of the LNA
is applied directly to the input of the demodulators. To sum the
signals E1 through E4, E2 is shifted 45° relative to E1 by setting
the phase code in Channel 2 to 0010, E3 is shifted 90° (0100), and
E4 is shifted 135° (0110). The phase aligned current signals at
In traditional analog beamformers incorporating Doppler, a
V-to-I converter per channel and a crosspoint switch precede
passive delay lines used as a combined phase shifter and
summing circuit. The system operates at the carrier frequency
(RF) through the delay line, which also sums the signals from
the various channels, and then the combined signal is down-
converted by an I/Q demodulator. The dynamic range of the
demodulator can limit the achievable dynamic range.
Rev. 0 | Page 35 of 44
AD9279
the output of the AD9279 are summed in an I-to-V converter to
provide the combined output signal with a theoretical improve-
ment in dynamic range of 6 dB for the four channels.
operation of an array of AD9279s, the RESET pulse must go low
on all devices before the next rising edge of the 4LO clock.
Therefore, it is best to have the RESET pulse go low on the falling
edge of the 4LO clock; at the very least, the tSETUP should be ≥ 5 ns.
An optimal timing setup is for the RESET pulse to go high on a
4LO falling edge and to go low on a 4LO falling edge; this gives
15 ns of setup time even at a 4LO frequency of 32 MHz (8 MHz
internal LO). Use the following procedure to check the synch-
ronization of multiple AD9279s:
CW Application Information
The RESET pin is used to synchronize the LO dividers in AD9279
arrays. Because they are driven by the same internal LO, the four
channels in any AD9279 are inherently synchronous. However,
when multiple AD9279s are used, it is possible that their dividers
wake up in different phase states. The function of the RESET
pin is to phase align all the LO signals in multiple AD9279s.
1. Activate at least one channel per AD9279 by setting the
appropriate channel enable bit in the serial interface.
2. Set the phase code of all AD9279 channels to the same
logic state, for example, 0000.
3. Apply the same test signal to all devices to generate a sine
wave in the baseband output and measure the output of
one channel per device.
The 4LO divider of each AD9279 can be initiated in one of four
possible states: 0°, 90°, 180°, and 270° relative to other AD9279s.
The internally generated I/Q signals of each AD9279 LO are always
at a 90° angle relative to each other, but a phase shift can occur
during power-up between the dividers of multiple AD9279s
used in a common array.
4. Apply a RESET pulse to all AD9279s.
The RESET mechanism also allows the measurement of non-
mixing gain from the RF input to the output. The rising edge of
the active high RESET pulse can occur at any time; however, the
duration should be ≥ 20 ns minimum. When the RESET pulse
transitions from high to low, the LO dividers are reactivated on
the next rising edge of the 4LO clock. To guarantee synchronous
5. Because all phase codes of the AD9279s should be the
same, the combined signal of multiple devices should be N
times greater than a single channel. If the combined signal
is less than N times one channel, one or more of the LO
phases of the individual AD9279s are in error.
TRANSDUCER ELEMENT TE1
THROUGH ELEMENT TE4
CONVERT US WAVES TO
ELECTRICAL SIGNALS
S1 THROUGH S4
PHASE BIT
ARE NOW
SETTINGS
IN PHASE
E1
S1
CHANNEL 1
PHASE SET
FOR 135°
LAG
LNA
LNA
LNA
LNA
0°
E2
S2
CHANNEL 2
PHASE SET
OUTPUT
FOR 90°
SUMMED
4 US WAVES
S1 + S2 + S3 + S4
LAG
45°
ARE DELAYED
45° EACH WITH
RESPECT TO
EACH OTHER
E3
E4
S3
CHANNEL 3
PHASE SET
FOR 45°
90°
135°
LAG
S4
CHANNEL 4
PHASE SET
FOR 0°
LAG
Figure 67. Simplified Example of the AD9279 Phase Shifter
Rev. 0 | Page 36 of 44
AD9279
SERIAL PORT INTERFACE (SPI)
The AD9279 serial port interface allows the user to configure
the signal chain for specific functions or operations through a
structured register space provided inside the chip. The SPI
offers the user added flexibility and customization, depending
on the application. Addresses are accessed via the serial port
and can be written to or read from via the port. Memory is
organized into bytes that can be further divided into fields, as
documented in the Memory Map section. Detailed operational
information can be found in the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
In addition to the operation modes, the SPI port can be configured
to operate in different manners. For applications that do not
require a control port, the CSB line can be tied and held high.
This places the remainder of the SPI pins in their secondary
mode, as defined in the SDIO Pin and SCLK Pin sections. CSB
can also be tied low to enable 2-wire mode. When CSB is tied
low, SCLK and SDIO are the only pins required for communication.
Although the device is synchronized during power-up, caution
must be exercised when using this mode to ensure that the
serial port remains synchronized with the CSB line. When
operating in 2-wire mode, it is recommended that a 1-, 2-, or
3-byte transfer be used exclusively. Without an active CSB line,
streaming mode can be entered but not exited.
Three pins define the serial port interface, or SPI: SCLK, SDIO,
and CSB (see Table 17). The SCLK (serial clock) pin is used to
synchronize the read and write data presented to the device. The
SDIO (serial data input/output) pin is a dual-purpose pin that
allows data to be sent to and read from the internal memory map
registers of the device. The CSB (chip select bar) pin is an active
low control that enables or disables the read and write cycles.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used to both program the chip and to read
the contents of the on-chip memory. If the instruction is a read-
back operation, performing a readback causes the serial data
input/output (SDIO) pin to change direction from an input to
an output at the appropriate point in the serial frame.
Table 17. Serial Port Pins
Pin
Function
SCLK
Serial clock. Serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
Data can be sent in MSB first mode or LSB first mode. MSB
first mode is the default at power-up and can be changed by
adjusting the configuration register. For more information
about this and other features, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
SDIO
Serial data input/output. Dual-purpose pin that
typically serves as an input or an output, depending
on the instruction sent and the relative position in
the timing frame.
CSB
Chip select bar (active low). This control gates the
read and write cycles.
HARDWARE INTERFACE
The pins described in Table 17 constitute the physical interface
between the user’s programming device and the serial port of
the AD9279. The SCLK and CSB pins function as inputs when
using the SPI. The SDIO pin is bidirectional, functioning as an
input during write phases and as an output during readback.
The falling edge of CSB in conjunction with the rising edge of
SCLK determines the start of the framing sequence. During an
instruction phase, a 16-bit instruction is transmitted, followed
by one or more data bytes, which is determined by Bit Field W0
and Bit Field W1. An example of the serial timing and its defini-
tions can be found in Figure 69 and Table 18.
If multiple SDIO pins share a common connection, ensure that
proper VOH levels are met. Figure 68 shows the number of SDIO
pins that can be connected together and the resulting VOH level,
assuming the same load for each AD9279.
During normal operation, CSB is used to signal to the device
that SPI commands are to be received and processed. When
CSB is brought low, the device processes SCLK and SDIO to
execute instructions. Normally, CSB remains low until the
communication cycle is complete. However, if connected to a
slow device, CSB can be brought high between bytes, allowing
older microcontrollers enough time to transfer data into shift
registers. CSB can be stalled when transferring one, two, or three
bytes of data. When W0 and W1 are set to 11, the device enters
streaming mode and continues to process data, either reading
or writing, until CSB is taken high to end the communication
cycle. This allows complete memory transfers without the need
for additional instructions. Regardless of the mode, if CSB is taken
high in the middle of a byte transfer, the SPI state machine is
reset and the device waits for a new instruction.
1.800
1.795
1.790
1.785
1.780
1.775
1.770
1.765
1.760
1.755
1.750
1.745
1.740
1.735
1.730
1.725
1.720
1.715
0
10
20
30
40
50
60
70
80
90
100
NUMBER OF SDIO PINS CONNECTED TOGETHER
Figure 68. SDIO Pin Loading
Rev. 0 | Page 37 of 44
AD9279
This interface is flexible enough to be controlled by either serial
PROMs or PIC microcontrollers, providing the user with
an alternative method, other than a full SPI controller, for
programming the device (see the AN-812 Application Note).
tDS
tHIGH
tCLK
tH
tS
tDH
tLOW
CSB
SCLK
SDIO
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
Figure 69. Serial Timing Details
Table 18. Serial Timing Definitions
Parameter
Timing (ns min)
Description
tDS
tDH
tCLK
tS
5
2
40
5
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
tH
2
Hold time between CSB and SCLK
tHIGH
tLOW
tEN_SDIO
16
16
10
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling
edge (not shown in Figure 69)
tDIS_SDIO
10
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 69)
Rev. 0 | Page 38 of 44
AD9279
MEMORY MAP
All registers except Register 0x00, Register 0x04, Register 0x05,
and Register 0xFF are buffered with a master slave latch and
require writing to the transfer bit. For more information on this
and other functions, consult the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
READING THE MEMORY MAP TABLE
Each row in the memory map register table has eight bit loca-
tions. The memory map is roughly divided into three sections:
the chip configuration register map (Address 0x00 to Address 0x02),
the device index and transfer register map (Address 0x04 to
Address 0xFF), and the program register map (Address 0x08
to Address 0x2D).
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.
The leftmost column of the memory map indicates the register
address, and the default value is shown in the second rightmost
column. The Bit 7 (MSB) column is the start of the default
hexadecimal value given. For example, Address 0x09, the clock
register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 =
0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1,
or 0000 0001 in binary. This setting is the default for the duty
cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this
address, followed by 0x01 in Register 0xFF (the transfer bit), the
duty cycle stabilizer is turned off. It is important to follow each
writing sequence with a transfer bit to update the SPI registers.
DEFAULT VALUES
After a reset, critical registers are automatically loaded with
default values. These values are indicated in Table 19, where an
X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “bit is cleared” is synonymous with “bit is set
to Logic 0” or “writing Logic 0 for the bit.”
Rev. 0 | Page 39 of 44
AD9279
Table 19. AD9279 Memory Map Registers
Addr.
Bit 7
Bit 0
(LSB)
Default
Value
(Hex) Register Name
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
Chip Configuration Registers
0x00
CHIP_PORT_CONFIG
0
LSB first
1 = on
0 = off
Soft
reset
1 = on
0 = off
(default)
1
1
Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
0
0x18
Nibbles should be
mirrored so that
LSB or MSB first
mode is set cor-
rectly regardless of
shift mode.
(default)
(default)
0x01
0x02
CHIP_ID
Chip ID Bits[7:0]
(AD9279 = 0x7C), (default)
0x7C
0x00
Default is unique
chip ID, different
for each device.
Read-only register.
CHIP_GRADE
X
X
Speed Mode[5:4]
(identify device
X
X
X
X
Child ID used to
differentiate ADC
speed power
modes.
variants of chip ID)
00: Mode I
(40 MSPS) (default)
01: Mode II (65 MSPS)
10: Mode III (80 MSPS)
Device Index and Transfer Registers
0x04
0x05
0xFF
DEVICE_INDEX_2
DEVICE_INDEX_1
DEVICE_UPDATE
X
X
X
X
X
X
X
X
Data
Data
Data
Data
0x0F
0x0F
0x00
Bits are set to
Channel Channel Channel Channel
H
1 = on
(default)
0 = off
determine which
on-chip device
receives the next
write command.
G
F
E
1 = on
(default)
0 = off
1 = on
(default)
0 = off
1 = on
(default)
0 = off
Clock
Clock
Data
Data
Data
Data
Bits are set to
Channel Channel Channel Channel Channel Channel
DCO
1 = on
0 = off
(default)
determine which
on-chip device
receives the next
write command.
FCO
1 = on
0 = off
D
C
B
A
1 = on
(default)
1 = on
(default)
0 = off
1 = on
(default)
0 = off
1 = on
(default)
0 = off
(default) 0 = off
X
X
X
X
X
SW
Synchronously
transfers data
from the master
shift register to
the slave.
transfer
1 = on
0 = off
(default)
Program Function Registers
0x08
Modes
X
X
X
X
X
X
0
0
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
100 = CW mode (TGC PDWN)
0x00
Determines
generic modes
of chip operation
(global).
0x09
0x0D
Clock
X
X
X
X
DCS
0x01
0x00
Turns the internal
duty cycle stabilizer
(DCS) on and off
(global).
1 = on
(default)
0 = off
TEST_IO
User test mode
00 = off (default)
01 = on, single
alternate
10 = on, single once
11 = on, alternate once (default)
Reset PN Reset PN
long
gen
1 = on
0 = off
When this register
is set, the test data
is placed on the
output pins in
place of normal
data. (Local, expect
for PN sequence.)
Output test mode—see Table 13
0000 = off (default)
0001 = midscale short
0010 = +FS short
short
gen
1 = on
0 = off
(default)
0011 = −FS short
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency (format
determined by OUTPUT_MODE)
0x0E
GPO outputs
X
X
X
X
General-purpose digital outputs
0x00
Values placed on
GPO[0:3] pins
(global).
Rev. 0 | Page 40 of 44
AD9279
Addr.
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
(Hex) Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x0F
FLEX_CHANNEL_
INPUT
Filter cutoff frequency control
0000 = 1.3 × 1/3 × fSAMPLE
0001 = 1.2 × 1/3 × fSAMPLE
0010 = 1.1 × 1/3 × fSAMPLE
0011 = 1.0 × 1/3 × fSAMPLE (default)
0100 = 0.9 × 1/3 × fSAMPLE
0101 = 0.8 × 1/3 × fSAMPLE
0110 = 0.7 × 1/3 × fSAMPLE
1000 = 1.3 × 1/4.5 × fSAMPLE
1001 = 1.2 × 1/4.5 × fSAMPLE
1010 = 1.1 × 1/4.5 × fSAMPLE
1011 = 1.0 × 1/4.5 × fSAMPLE
1100 = 0.9 × 1/4.5 × fSAMPLE
1101 = 0.8 × 1/4.5 × fSAMPLE
1110 = 0.7 × 1/4.5 × fSAMPLE
X
X
X
X
0x30
Antialiasing filter
cutoff (global).
0x10
0x11
FLEX_OFFSET
FLEX_GAIN
X
X
X
X
1
0
0
0
0
0
0x20
0x06
Reserved.
X
X
PGA gain
00 = 21 dB
01 = 24 dB (default)
10 = 27 dB
11 = 30 dB
LNA gain
LNA and PGA gain
adjustment
(global).
00 = 15.6 dB
01 = 17.9 dB
10 = 21.3 dB
(default)
0x12
0x14
BIAS_CURRENT
OUTPUT_MODE
X
X
X
X
X
X
X
1
X
LNA bias
00 = high
01 = mid-high
(default)
10 = mid-low
11 = low
0x09
0x00
LNA bias current
adjustment
(global).
0 = LVDS
ANSI-644
(default)
1 = LVDS
low power,
(IEEE
X
Output
invert
enable
1 = on
0 = off
(default)
Data format select
00 = offset binary
(default)
01 = twos
complement
Configures the
outputs and the
format of the data
(Bits[7:3] and
Bits[1:0] are global;
Bit 2 is local).
1596.3
similar)
0x15
OUTPUT_ADJUST
X
X
Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X
X
X
DCO
and
FCO
2× drive
strength
1 = on
0 = off
(default)
0x00
Determines LVDS
or other output
properties.
Primarily functions
to set the LVDS
span and
common-mode
levels in place of
an external resistor
(Bits[7:1] are global;
Bit 0 is local).
0x16
OUTPUT_PHASE
X
X
X
X
Output clock phase adjust
0x03
On devices that
use global clock
divide, deter-
mines which
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge (default)
0100 = reserved
0101 = 300° relative to data edge
0110 = 360° relative to data edge
0111 = reserved
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
phase of the
divider output is
used to supply
the output clock.
Internal latching
is unaffected.
(global)
0x18
0x19
FLEX_VREF
X
0 =
X
X
X
X
1
1
0x03
0x00
Select internal
reference
(recommended
default) or
external reference
(global).
internal
reference
1 =
external
reference
USER_PATT1_LSB
B7
B6
B5
B4
B3
B2
B1
B0
User-Defined
Pattern 1, LSB
(global).
Rev. 0 | Page 41 of 44
AD9279
Addr.
Bit 7
(MSB)
Bit 0
(LSB)
Default
Value
(Hex) Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Comments
0x1A
0x1B
0x1C
0x21
USER_PATT1_MSB
USER_PATT2_LSB
USER_PATT2_MSB
SERIAL_CONTROL
B15
B14
B13
B12
B11
B10
B9
B8
B0
B8
0x00
0x00
0x00
0x00
User-Defined
Pattern 1, MSB
(global).
B7
B6
B14
X
B5
B13
X
B4
B12
X
B3
B2
B1
B9
User-Defined
Pattern 2, LSB
(global).
B15
B11
B10
User-Defined
Pattern 2, MSB
(global).
LSB first
1 = on
0 = off
<10
MSPS,
low
000 = 12 bits (default, normal
bit stream)
001 = 8 bits
Serial stream
control (global).
(default)
encode
rate
010 = 10 bits
011 = 12 bits
mode
1 = on
0 = off
(default)
100 = 14 bits
0x22
0x2B
SERIAL_CH_STAT
FLEX_FILTER
X
X
X
X
X
X
X
X
X
Channel Channel 0x00
Used to power
down individual
sections of a
output
reset
power-
down
1 = on
0 = off
1 = on
0 = off
converter (local).
(default) (default)
Enable
automatic
low-pass
tuning
1 = on
(self-
High-pass filter cutoff
0000 = fLP/12.00
0001 = fLP/8.57
0010 = fLP/6.67
0011 = fLP/5.46
0100 = fLP/4.62
0101 = fLP/4.00
0110 = fLP/3.53
0111 = fLP/3.16
0x00
Filter cutoff
(global).
(fLP = low-pass
filter cutoff
frequency.)
clearing)
0x2C
0x2D
ANALOG_INPUT
X
X
X
X
X
X
X
X
X
LO-x, LOSW-x
connection
00 = RFB1 (default)
01 = RFB1||RFB2
10 = RFB2
0x00
0x00
LNA active
termination/input
impedance
(global).
11 = ∞
CW Doppler
I/Q demodulator
phase
CW
I/Q demodulator phase
0000 = 0°
0001 = 22.5°
0010 = 45°
0011 = 67.5°
0100 = 90°
Phase of
demodulators
(local).
Doppler
channel
enable
1 = on
0 = off
0101 = 112.5°
0110 = 135°
0111 = 157.5°
1000 = 180°
1001 = 202.5°
1010 = 225°
1011 = 247.5°
1100 = 270°
1101 = 292.5°
1110 = 315°
1111 = 337.5°
Rev. 0 | Page 42 of 44
AD9279
OUTLINE DIMENSIONS
10.10
10.00 SQ
9.90
A1 BALL
CORNER
A1 BALL
CORNER
12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
8.80
BSC SQ
G
H
J
0.80
K
L
M
0.60
REF
TOP VIEW
DETAIL A
BOTTOM VIEW
*
1.40 MAX
0.65 MIN
DETAIL A
0.25 MIN
0.50
0.45
0.40
COPLANARITY
0.20
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT WITH JEDEC STANDARDS MO-275-EEAB-1
WITH EXCEPTION TO PACKAGE HEIGHT.
Figure 70. 144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]
(BC-144-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
BC-144-1
AD9279-BBCZ
AD9279-65EBZ
AD9279-80KITZ
−40°C to +85°C
144-Ball Chip Scale Package, Ball Grid Array [CSP_BGA]
Evaluation Board
Evaluation Board and High Speed FPGA-Based Data Capture Board
1 Z = RoHS Compliant Part.
Rev. 0 | Page 43 of 44
AD9279
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09423-0-10/10(0)
Rev. 0 | Page 44 of 44
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