AD9363ABCZ [ADI]
Radio frequency (RF) 2 Ã 2 transceiver with integrated 12-bit DACs and ADCs;
| 型号： | AD9363ABCZ |
| 厂家： | 
ADI |
| 描述： | Radio frequency (RF) 2 Ã 2 transceiver with integrated 12-bit DACs and ADCs |
| 文件： | 总32页 (文件大小：523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RF Agile Transceiver
Data Sheet
AD9363
FEATURES
FUNCTIONAL BLOCK DIAGRAM
RX1B_P,
RX1B_N
Radio frequency (RF) 2 × 2 transceiver with integrated 12-bit
DACs and ADCs
Wide bandwidth: 325 MHz to 3.8 GHz
Supports time division duplex (TDD) and frequency division
duplex (FDD) operation
AD9363
RX1A_P,
RX1A_N
ADC
RX1C_P,
RX1C_N
RX2B_P,
RX2B_N
P0_D11/
TX_D5_x TO P0_D0/
TX_D0_x
Tunable channel bandwidth (BW): up to 20 MHz
Receivers: 6 differential or 12 single-ended inputs
Superior receiver sensitivity with a noise figure: 3 dB
Receive (Rx) gain control
RX2A_P,
RX2A_N
ADC
RX2C_P,
RX2C_N
RX LO
TX LO
TX_MON1
P1_D11/
Real-time monitor and control signals for manual gain
Independent automatic gain control (AGC)
Dual transmitters: 4 differential outputs
Highly linear broadband transmitter
Transmit (Tx) error vector magnitude (EVM): −34 dB
Tx noise: ≤−157 dBm/Hz noise floor
Tx monitor: 66 dB dynamic range with 1 dB accuracy
Integrated fractional N synthesizers
2.4 Hz local oscillator (LO) step size
TX1A_P,
TX1A_N
DAC
DAC
RX_D5_x TO P1_D0/
RX_D0_x
TX1B_P,
TX1B_N
TX_MON2
TX2A_P,
TX2A_N
TX2B_P,
TX2B_N
RADIO
SWITCHING
GPO
SPI
CTRL
PLLs
CLK_OUT
CTRL
AUXADC AUXDACx
XTALN
CMOS/LVDS digital interface
NOTES
1. SPI, CTRL, P0_D11/TX_D5_x TO P0_D0/TX_D0_x, P1_D11/
RX_D5_x TO P1_D0/RX_D0_x, AND RADIO SWITCHING
CONTAIN MULTIPLE PINS.
APPLICATIONS
3G enterprise femtocell base stations
4G femtocell base stations
Figure 1.
Wireless video transmission
GENERAL DESCRIPTION
The AD9363 is a high performance, highly integrated RF agile
transceiver designed for use in 3G and 4G femtocell applications.
Its programmability and wideband capability make it ideal for a
broad range of transceiver applications. The device combines an
RF front end with a flexible mixed-signal baseband section and
integrated frequency synthesizers, simplifying design-in by
providing a configurable digital interface to a processor. The
AD9363 operates in the 325 MHz to 3.8 GHz range, covering
most licensed and unlicensed bands. Channel bandwidths from
less than 200 kHz to 20 MHz are supported.
sample rate.
The transmitters use a direct conversion architecture that achieves
high modulation accuracy with ultralow noise. This transmitter
design produces a best-in-class Tx EVM of −34 dB, allowing
significant system margin for the external power amplifier (PA)
selection. The on-board Tx power monitor can be used as a
power detector, enabling highly accurate Tx power
measurements.
The fully integrated phase-locked loops (PLLs) provide low
power fractional N frequency synthesis for all receive and
transmit channels. Channel isolation, demanded by FDD
systems, is integrated into the design. All voltage controlled
oscillators (VCOs) and loop filter components are integrated.
The two independent direct conversion receivers have state-of-
the-art noise figure and linearity. Each Rx subsystem includes
independent automatic gain control (AGC), dc offset correction,
quadrature correction, and digital filtering, thereby eliminating
the need for these functions in the digital baseband. The AD9363
also has flexible manual gain modes that can be externally
controlled. Two high dynamic range ADCs per channel digitize
the received I and Q signals and pass them through configurable
decimation filters and 128-tap finite impulse response (FIR)
filters to produce a 12-bit output signal at the appropriate
The core of the AD9363 can be powered directly from a 1.3 V
regulator. The IC is controlled via a standard 4-wire serial port
and four real-time I/O control pins. Comprehensive power-down
modes are included to minimize power consumption during
normal use. The AD9363 is packaged in a 10 mm × 10 mm,
144-ball chip scale package ball grid array (CSP_BGA).
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2016 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9363
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
2.4 GHz Frequency Band .......................................................... 24
Theory of Operation ...................................................................... 28
General......................................................................................... 28
Receiver........................................................................................ 28
Transmitter .................................................................................. 28
Clock Input Options .................................................................. 28
Synthesizers................................................................................. 28
Digital Data Interface................................................................. 29
Enable State Machine................................................................. 29
SPI Interface................................................................................ 30
Control Pins ................................................................................ 30
GPO Pins (GPO_3 to GPO_0)................................................. 30
Auxiliary Converters.................................................................. 30
Packaging and Ordering Information ......................................... 32
Outline Dimensions................................................................... 32
Ordering Guide .......................................................................... 32
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Current Consumption—VDD_INTERFACE........................... 8
Current Consumption—VDDD1P3_DIG and VDDAx
(Combination of All 1.3 V Supplies) ....................................... 11
Absolute Maximum Ratings ..................................................... 15
Reflow Profile.............................................................................. 15
Thermal Resistance .................................................................... 15
ESD Caution................................................................................ 15
Pin Configuration and Function Descriptions........................... 16
Typical Performance Characteristics ........................................... 20
800 MHz Frequency Band......................................................... 20
REVISION HISTORY
11/2016—Revision D: Initial Version
Rev. D | Page 2 of 32
Data Sheet
AD9363
SPECIFICATIONS
Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and all other VDDx pins (VDDA1P3_TX_LO, VDDA1P3_
TX_VCO_LDO, VDDA1P3_RX_LO, VDDA1P3_RX_VCO_LDO, VDDA1P3_RX_RF, VDDA1P3_RX_TX, VDDA1P3_TX_LO_BUFFER,
VDDA1P3_TX_SYNTH, VDDA1P3_RX_SYNTH, VDDD1P3_DIG, and VDDA1P3_BB) = 1.3 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter1
RECEIVERS, GENERAL
Center Frequency
Rx Bandwidth
Gain
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
325
3800 MHz
20
MHz
Minimum
Maximum
0
dB
dB
dB
dB
dB
74.5
73.0
72.0
1
At 800 MHz
At 2300 MHz (RX1A_x, RX2A_x)
At 2300 MHz (RX1B_x, RX1C_x, RX2B_x, RX2C_x)
Gain Step
Received Signal Strength Indicator
Range
Accuracy
RSSI
100
2
dB
dB
RECEIVERS, 800 MHz
Noise Figure
Third-Order Input Intermodulation
Intercept Point
NF
IIP3
2.5
−18
dB
dBm
Maximum Rx gain
Maximum Rx gain
Second-Order Input Intermodulation
Intercept Point
Local Oscillator (LO) Leakage
Quadrature
IIP2
40
dBm
dBm
Maximum Rx gain
−122
At Rx front-end input
Gain Error
0.2
%
Phase Error
Modulation Accuracy (EVM)
Input Return Loss
0.2
−34
−10
Degrees
dB
dB
19.2 MHz reference clock
S11
RX1x_x to RX2x_x Isolation
RX1A_x to RX2A_x, RX1C_x to RX2C_x
RX1B_x to RX2B_x
70
55
dB
dB
RX2_x to RX1_x Isolation
RX2A_x to RX1A_x, RX2C_x to RX1C_x
RX2B_x to RX1B_x
70
55
dB
dB
RECEIVERS, 2.4 GHz
Noise Figure
Third-Order Input Intermodulation
Intercept Point
NF
IIP3
3
−14
dB
dBm
Maximum Rx gain
Maximum Rx gain
Second-Order Input Intermodulation
Intercept Point
Local Oscillator (LO) Leakage
Quadrature
IIP2
45
dBm
dBm
Maximum Rx gain
−110
At Rx front-end input
Gain Error
0.2
%
Phase Error
Modulation Accuracy (EVM)
Input Return Loss
0.2
−34
−10
Degrees
dB
dB
40 MHz reference clock
S11
RX1x_x to RX2x_x Isolation
RX1A_x to RX2A_x, RX1C_x to RX2C_x
RX1B_x to RX2B_x
65
50
dB
dB
Rev. D | Page 3 of 32
AD9363
Data Sheet
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
RX2x_x to RX1x_x Isolation
RX2A_x to RX1A_x, RX2C_x to RX1C_x
RX2B_x to RX1B_x
65
50
dB
dB
RECEIVERS, 3.5 GHz
Noise Figure
Third-Order Input Intermodulation
Intercept Point
NF
IIP3
3.3
−15
dB
dBm
Maximum Rx gain
Maximum Rx gain
Second-Order Input Intermodulation
Intercept Point
Local Oscillator (LO) Leakage
Quadrature
IIP2
44
dBm
dBm
Maximum Rx gain
−100
At Rx front-end input
Gain Error
0.2
%
Phase Error
Modulation Accuracy (EVM)
Input Return Loss
0.2
−34
−10
Degrees
dB
dB
40 MHz reference clock
S11
RX1x_x to RX2x_x Isolation
RX1A_x to RX2A_x, RX1C_x to RX2C_x
RX1B_x to RX2B_x
60
48
dB
dB
RX2x_x to RX1x_x Isolation
RX2A_x to RX1A_x, RX2C_x to RX1C_x
RX2B_x to RX1B_x
60
48
dB
dB
TRANSMITTERS, GENERAL
Center Frequency
325
3800 MHz
Tx Bandwidth
20
MHz
dB
dB
Power Control Range
Power Control Resolution
TRANSMITTERS, 800 MHz
Output Return Loss
Maximum Output Power
Modulation Accuracy (EVM)
90
0.25
S22
−10
8
−34
23
dB
dBm
dB
1 MHz tone into 50 Ω load
19.2 MHz reference clock
Third-Order Output Intermodulation
Intercept Point
OIP3
dBm
Carrier Leakage
−50
−32
dBc
dBc
0 dB attenuation
40 dB attenuation
Noise Floor
−157
dBm/Hz 90 MHz offset
Isolation
TX1x_x to TX2x_x
TX2x_x to TX1x_x
TRANSMITTERS, 2.4 GHz
Output Return Loss
Maximum Output Power
Modulation Accuracy (EVM)
50
50
dB
dB
S22
−10
7.5
−34
19
dB
dBm
dB
1 MHz tone into 50 Ω load
40 MHz reference clock
Third-Order Output Intermodulation
Intercept Point
OIP3
dBm
Carrier Leakage
−50
−32
dBc
dBc
0 dB attenuation
40 dB attenuation
Noise Floor
−156
dBm/Hz 90 MHz offset
Isolation
TX1x_x to TX2x_x
TX2x_x to TX1x_x
TRANSMITTERS, 3.5 GHz
Output Return Loss
Maximum Output Power
Modulation Accuracy (EVM)
50
50
dB
dB
S22
−10
7.0
−34
dB
dBm
dB
1 MHz tone into 50 Ω load
40 MHz reference clock
Rev. D | Page 4 of 32
Data Sheet
AD9363
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
Third-Order Output Intermodulation
Intercept Point
OIP3
18
dBm
Carrier Leakage
−50
−31
dBc
dBc
0 dB attenuation
40 dB attenuation
Noise Floor
Isolation
−154
dBm/Hz 90 MHz offset
TX1 to TX2
TX2 to TX1
50
50
dB
dB
1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.
Table 2.
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
TX MONITOR INPUTS
(TX_MON1, TX_MON2)
Maximum Input Level
Dynamic Range
Accuracy
4
66
1
dBm
dB
dB
LO SYNTHESIZER
LO Frequency Step
Integrated Phase Noise
REFERENCE CLOCK (REF_CLK)
2.4
0.3
Hz
°rms
2.4 GHz, 40 MHz reference clock
100 Hz to 100 MHz
REF_CLK is the input to the
XTALN pin
Input Frequency Range
Input Signal Level
AUXILIARY ADC
Resolution
10
80
MHz
External oscillator
1.3
12
V p-p AC-coupled external oscillator
Bits
Input Voltage
Minimum
Maximum
0.05
VDDA1P3_BB −
0.05
V
V
AUXILIARY DAC
Resolution
10
Bits
Output Voltage
Minimum
0.5
V
Maximum
Output Current
VDD_GPO − 0.3
10
V
mA
DIGITAL SPECIFICATIONS
(CMOS)
Logic Inputs
Input Voltage High
VDD_INTERFACE ×
0.8
0
VDD_INTERFACE
V
V
Input Voltage Low
VDD_INTERFACE ×
0.2
Input Current High
Input Current Low
Logic Outputs
−10
−10
+10
+10
μA
μA
Output Voltage High
VDD_INTERFACE ×
0.8
0
VDD_INTERFACE
V
V
Output Voltage Low
VDD_INTERFACE ×
0.2
DIGITAL SPECIFICATIONS (LVDS)
Logic Inputs
Input Voltage Range
825
1575
+100
mV
mV
Each differential input in the
pair
Input Differential Voltage
Threshold
−100
Rev. D | Page 5 of 32
AD9363
Data Sheet
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
Receiver Differential Input
100
Ω
Impedance
Logic Outputs
Output Voltage High
Output Voltage Low
Output Differential
Voltage
1375
mV
mV
mV
1025
150
Programmable in 75 mV steps
Output Offset Voltage
GENERAL-PURPOSE OUTPUTS
Output Voltage High
Output Voltage Low
Output Current
SPI TIMING
1200
10
mV
VDD_GPO × 0.8
0
VDD_GPO
VDD_GPO × 0.2
V
V
mA
VDD_INTERFACE = 1.8 V
SPI_CLK
Period
Pulse Width
SPI_EN Setup to First
SPI_CLK Rising Edge
tCP
tMP
tSC
20
9
1
ns
ns
ns
Last SPI_CLK Falling Edge to
SPI_ENB Hold
tHC
0
ns
SPI_DI
Data Input Setup to
SPI_CLK
Data Input Hold to
SPI_CLK
tS
2
1
ns
ns
tH
SPI_CLK Rising Edge to
Output Data Delay
4-Wire Mode
3-Wire Mode
Bus Turnaround Time, Read
(Master)
tCO
tCO
tHZM
3
3
tH
8
8
ns
ns
ns
tCO (MAX)
After baseband processors
(BBP) drives the last address bit
Bus Turnaround Time, Read
(Slave)
tHZS
0
tCO (MAX)
ns
After AD9363 drives the last
data bit
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 1.8 V
DATA_CLK_x Clock Period
DATA_CLK_x and FB_CLK_x
Pulse Width
tCP
tMP
16.276
45% of tCP
ns
ns
61.44 MHz
55% of tCP
Tx Data
TX_FRAME_x, P0_Dx, and
P1_Dx
Setup to FB_CLK_x
Hold to FB_CLK_x
DATA_CLK_x to Data Bus
Output Delay
tSTX
tHTX
tDDRX
1
0
0
ns
ns
ns
1.5
1.0
DATA_CLK_x to
tDDDV
0
ns
RX_FRAME_x Delay
Pulse Width
ENABLE
TXNRX
tENPW
tTXNRXPW
tCP
tCP
ns
ns
FDD independent enable state
machine (ENSM) mode
TXNRX Setup to ENABLE
Bus Turnaround Time
Before Rx
After Rx
Capacitive Load
Capacitive Input
tTXNRXSU
0
ns
TDD ENSM mode
TDD mode
tRPRE
tRPST
2 × tCP
2 × tCP
ns
ns
pF
pF
3
3
Rev. D | Page 6 of 32
Data Sheet
AD9363
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 2.5 V
DATA_CLK_x Clock Period
DATA_CLK_x and FB_CLK_x
Pulse Width
tCP
tMP
16.276
45% of tCP
ns
ns
61.44 MHz
55% of tCP
Tx Data
TX_FRAME_x, P0_Dx, and P1_Dx
Setup to FB_CLK_x
Hold to FB_CLK_x
DATA_CLK_x to Data Bus
Output Delay
tSTX
tHTX
tDDRX
1
0
0.25
ns
ns
ns
1.25
1.25
DATA_CLK_x to
tDDDV
0.25
ns
RX_FRAME_x Delay
Pulse Width
ENABLE
TXNRX
TXNRX Setup to ENABLE
Bus Turnaround Time
Before Rx
tENPW
tTXNRXPW
tTXNRXSU
tCP
tCP
0
ns
ns
ns
FDD independent ENSM mode
TDD ENSM mode
TDD mode
tRPRE
tRPST
2 × tCP
2 × tCP
ns
ns
pF
pF
After Rx
Capacitive Load
Capacitive Input
DIGITAL DATA TIMING (LVDS)
DATA_CLK_x Clock Period
DATA_CLK_x and FB_CLK_x
Pulse Width
3
3
tCP
tMP
4.069
45% of tCP
ns
ns
245.76 MHz
55% of tCP
Tx Data
TX_FRAME_x and TX_Dx
Setup to FB_CLK_x
Hold to FB_CLK_x
DATA_CLK_x to Data Bus
Output Delay
tSTX
tHTX
tDDRX
1
0
0
ns
ns
ns
1.5
1.0
DATA_CLK_x to
tDDDV
0
ns
RX_FRAME_x Delay
Pulse Width
ENABLE
TXNRX
TXNRX Setup to ENABLE
Bus Turnaround Time
Before Rx
tENPW
tTXNRXPW
tTXNRXSU
tCP
tCP
0
ns
ns
ns
FDD independent ENSM mode
TDD ENSM mode
tRPRE
tRPST
2 × tCP
2 × tCP
ns
ns
pF
pF
After Rx
Capacitive Load
Capacitive Input
SUPPLY CHARACTERISTICS
1.3 V Main Supply
VDD_INTERFACE Supply
CMOS
3
3
1.267
1.3
1.33
V
1.2
1.8
1.3
2.5
2.5
3.465
V
V
V
LVDS
VDD_GPO Supply
3.3
When unused, must be set to
1.3 V
Current Consumption
VDDx, Sleep Mode
VDD_GPO
180
50
µA
μA
Sum of all input currents
No load
1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.
Rev. D | Page 7 of 32
AD9363
Data Sheet
CURRENT CONSUMPTION—VDD_INTERFACE
Table 3. VDD_INTERFACE = 1.2 V
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SLEEP MODE
45
μA
Power applied, device disabled
ONE Rx CHANNEL, ONE Tx CHANNEL, DOUBLE
DATA RATE (DDR)
LTE10
Single Port
Dual Port
2.9
2.7
mA
mA
30.72 MHz data clock, CMOS
15.36 MHz data clock, CMOS
LTE20
Dual Port
5.2
1.3
mA
mA
30.72 MHz data clock, CMOS
7.68 MHz data clock, CMOS
TWO Rx CHANNELS, TWO Tx CHANNELS, DDR
LTE3
Dual Port
LTE10
Single Port
Dual Port
LTE20
4.6
5.0
mA
mA
61.44 MHz data clock, CMOS
30.72 MHz data clock, CMOS
Dual Port
GSM
8.2
0.2
3.3
mA
mA
mA
61.44 MHz data clock, CMOS
1.08 MHz data clock, CMOS
20 MHz data clock, CMOS
Dual Port
WiMAX 8.75 MHz
Dual Port
WiMAX 10 MHz
Single Port
TDD Rx
0.5
3.6
3.8
mA
mA
mA
22.4 MHz data clock, CMOS
22.4 MHz data clock, CMOS
44.8 MHz data clock, CMOS
TDD Tx
FDD
WiMAX 20 MHz
Dual Port
FDD
6.7
mA
44.8 MHz data clock, CMOS
Rev. D | Page 8 of 32
Data Sheet
AD9363
Table 4. VDD_INTERFACE = 1.8 V
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SLEEP MODE
84
μA
Power applied, device disabled
ONE Rx CHANNEL, ONE Tx CHANNEL, DDR
LTE10
Single Port
Dual Port
4.5
4.1
mA
mA
30.72 MHz data clock, CMOS
15.36 MHz data clock, CMOS
LTE20
Dual Port
8.0
2.0
mA
mA
30.72 MHz data clock, CMOS
7.68 MHz data clock, CMOS
TWO Rx CHANNELS, TWO Tx CHANNELS, DDR
LTE3
Dual Port
LTE10
Single Port
Dual Port
LTE20
8.0
7.5
mA
mA
61.44 MHz data clock, CMOS
30.72 MHz data clock, CMOS
Dual Port
GSM
14.0
0.3
mA
mA
mA
61.44 MHz data clock, CMOS
1.08 MHz data clock, CMOS
20 MHz data clock, CMOS
Dual Port
WiMAX 8.75 MHz
Dual Port
WiMAX 10 MHz
Single Port
TDD Rx
5.0
0.7
5.6
6.0
mA
mA
mA
22.4 MHz data clock, CMOS
22.4 MHz data clock, CMOS
44.8 MHz data clock, CMOS
TDD Tx
FDD
WiMAX 20 MHz
Dual Port
FDD
10.7
mA
44.8 MHz data clock, CMOS
Rev. D | Page 9 of 32
AD9363
Data Sheet
Table 5. VDD_INTERFACE = 2.5 V
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SLEEP MODE
150
μA
Power applied, device disabled
ONE Rx CHANNEL, ONE Tx CHANNEL, DDR
LTE10
Single Port
Dual Port
6.5
6.0
mA
mA
30.72 MHz data clock, CMOS
15.36 MHz data clock, CMOS
LTE20
Dual Port
11.5
3.0
mA
mA
30.72 MHz data clock, CMOS
7.68 MHz data clock, CMOS
TWO Rx CHANNELS, TWO Tx CHANNELS, DDR
LTE3
Dual Port
LTE10
Single Port
Dual Port
LTE20
11.5
10.0
mA
mA
61.44 MHz data clock, CMOS
30.72 MHz data clock, CMOS
Dual Port
GSM
20.0
0.5
mA
mA
mA
61.44 MHz data clock, CMOS
1.08 MHz data clock, CMOS
20 MHz data clock, CMOS
Dual Port
WiMAX 8.75 MHz
Dual Port
WiMAX 10 MHz
Single Port
TDD Rx
7.3
1.3
8.0
8.7
mA
mA
mA
22.4 MHz data clock, CMOS
22.4 MHz data clock, CMOS
44.8 MHz data clock, CMOS
TDD Tx
FDD
WiMAX 20 MHz
Dual Port
FDD
15.3
mA
44.8 MHz data clock, CMOS
Rev. D | Page 10 of 32
Data Sheet
AD9363
CURRENT CONSUMPTION—VDDx (COMBINATION OF ALL 1.3 V SUPPLIES)
Table 6. TDD Mode, 800 MHz
Parameter
ONE Rx CHANNEL
5 MHz BW
10 MHz BW
20 MHz BW
TWO Rx CHANNELS
5 MHz BW
10 MHz BW
20 MHz BW
ONE Tx CHANNEL
5 MHz BW
7 dBm
Min
Typ
Max
Unit
Test Conditions/Comments
Continuous Rx
180
210
260
mA
mA
mA
Continuous Rx
Continuous Tx
265
315
405
mA
mA
mA
340
190
mA
mA
−27 dBm
10 MHz BW
7 dBm
−27 dBm
360
220
mA
mA
20 MHz BW
7 dBm
−27 dBm
400
250
mA
mA
TWO Tx CHANNELS
5 MHz BW
7 dBm
Continuous Tx
550
260
mA
mA
−27 dBm
10 MHz BW
7 dBm
−27 dBm
600
310
mA
mA
20 MHz BW
7 dBm
−27 dBm
660
370
mA
mA
Rev. D | Page 11 of 32
AD9363
Data Sheet
Table 7. TDD Mode, 2.4 GHz
Parameter
ONE Rx CHANNEL
5 MHz BW
10 MHz BW
20 MHz BW
TWO Rx CHANNELS
5 MHz BW
10 MHz BW
20 MHz BW
ONE Tx CHANNEL
5 MHz BW
Min
Typ
Max
Unit
Test Conditions/Comments
Continuous Rx
175
200
240
mA
mA
mA
Continuous Rx
Continuous Tx
260
305
390
mA
mA
mA
7 dBm
−27 dBm
350
160
mA
mA
10 MHz BW
7 dBm
−27 dBm
380
220
mA
mA
20 MHz BW
7 dBm
−27 dBm
410
260
mA
mA
TWO Tx CHANNELS
5 MHz BW
Continuous Tx
7 dBm
−27 dBm
580
280
mA
mA
10 MHz BW
7 dBm
−27 dBm
635
330
mA
mA
20 MHz BW
7 dBm
−27 dBm
690
390
mA
mA
Rev. D | Page 12 of 32
Data Sheet
AD9363
Table 8. FDD Mode, 800 MHz
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ONE Rx CHANNEL, ONE Tx CHANNEL
5 MHz BW
7 dBm
−27 dBm
10 MHz BW
7 dBm
−27 dBm
20 MHz BW
7 dBm
−27 dBm
Continuous Rx and Tx
Continuous Rx and Tx
Continuous Rx and Tx
490
345
mA
mA
540
395
mA
mA
615
470
mA
mA
TWO Rx CHANNELS, ONE Tx CHANNEL
5 MHz BW
7 dBm
−27 dBm
10 MHz BW
7 dBm
−27 dBm
20 MHz BW
7 dBm
−27 dBm
555
410
mA
mA
625
480
mA
mA
740
600
mA
mA
ONE Rx CHANNEL, TWO Tx CHANNELS
5 MHz BW
7 dBm
−27 dBm
685
395
mA
mA
10 MHz BW
7 dBm
−27 dBm
755
465
mA
mA
20 MHz BW
7 dBm
−27 dBm
850
570
mA
mA
TWO Rx CHANNELS, TWO Tx CHANNELS
5 MHz BW
7 dBm
−27 dBm
10 MHz BW
7 dBm
−27 dBm
20 MHz BW
7 dBm
790
495
mA
mA
885
590
mA
mA
1020
730
mA
mA
−27 dBm
Rev. D | Page 13 of 32
AD9363
Data Sheet
Table 9. FDD Mode, 2.4 GHz
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
ONE Rx CHANNEL, ONE Tx CHANNEL
5 MHz BW
7 dBm
−27 dBm
10 MHz BW
7 dBm
−27 dBm
20 MHz BW
7 dBm
−27 dBm
Continuous Rx and Tx
Continuous Rx and Tx
Continuous Rx and Tx
Continuous Rx and Tx
500
350
mA
mA
540
390
mA
mA
620
475
mA
mA
TWO Rx CHANNELS, ONE Tx CHANNEL
5 MHz BW
7 dBm
−27 dBm
10 MHz BW
7 dBm
−27 dBm
20 MHz BW
7 dBm
−27 dBm
590
435
mA
mA
660
510
mA
mA
770
620
mA
mA
ONE Rx CHANNEL, TWO Tx CHANNELS
5 MHz BW
7 dBm
−27 dBm
10 MHz BW
7 dBm
−27 dBm
20 MHz BW
7 dBm
−27 dBm
730
425
mA
mA
800
500
mA
mA
900
600
mA
mA
TWO Rx CHANNELS, TWO Tx CHANNELS
5 MHz BW
7 dBm
−27 dBm
10 MHz BW
7 dBm
−27 dBm
20 MHz BW
7 dBm
820
515
mA
mA
900
595
mA
mA
1050
740
mA
mA
−27 dBm
Rev. D | Page 14 of 32
Data Sheet
AD9363
ABSOLUTE MAXIMUM RATINGS
REFLOW PROFILE
The AD9363 reflow profile is in accordance with the JEDEC
JESD20 criteria for Pb-free devices. The maximum reflow
temperature is 260°C.
Table 10.
Parameter
Rating
VDDx to VSSx
−0.3 V to +1.4 V
−0.3 V to +3.0 V
−0.3 V to +3.9 V
−0.3 V to
VDD_INTERFACE + 0.3 V
THERMAL RESISTANCE
VDD_INTERFACE to VSSx
VDD_GPO to VSSx
Logic Inputs and Outputs to VSSx
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment.
Careful attention to PCB thermal design is required.
Input Current to Any Pin Except
Supplies
RF Inputs (Peak Power)
Tx Monitor Input Power (Peak Power)
Package Power Dissipation
10 mA
θ
JA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
JC is the junction to case thermal resistance.
2.5 dBm
9 dBm
θ
(TJMAX − TA)/θJA
110°C
Maximum Junction Temperature (TJMAX
)
Table 11. Thermal Resistance
Temperature Range
Operating
Storage
Package
Type
Airflow Velocity
(m/sec)
2
3
−40°C to +85°C
−65°C to +150°C
260°C
θJA
θJC
Unit
°C/W
°C/W
°C/W
BC-144-71
0
32.3
29.6
27.8
9.6
1.0
2.5
N/A4
Reflow
N/A4
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
1 Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-STD-883, Method 1012.1.
4 N/A means not applicable.
ESD CAUTION
Rev. D | Page 15 of 32
AD9363
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
VDDA1P1_
TX_VCO
A
B
C
D
E
F
RX2A_N
VSSA
RX2A_P
VSSA
VSSA
DNC
VSSA
GPO_3
TX_MON2
GPO_2
VSSA
GPO_1
TX2A_N
GPO_0
VSSA
TX2A_P
VDD_GPO
VSSA
TX2B_N
TX2B_P
VSSA
VSSA
VDDA1P3_
TX_VCO_
LDO
VDDA1P3_
TX_LO
TX_VCO_
LDO_OUT
AUXDAC1
AUXDAC2
TEST/
ENABLE
RX2C_P
RX2C_N
CTRL_IN0
CTRL_IN1
CTRL_IN2
VSSA
VSSA
VSSA
VSSA
VSSD
VDDA1P3_ VDDA1P3_
RX_RF
P0_D9/
TX_D4_P
P0_D7/
TX_D3_P
P0_D5/
TX_D2_P
P0_D3/
TX_D1_P
P0_D1/
TX_D0_P
CTRL_OUT0 CTRL_IN3
RX_TX
VDDA1P3_
TX_LO_
BUFFER
VDDA1P3_
RX_LO
P0_D11/
TX_D5_P
P0_D8/
TX_D4_N
P0_D6/
TX_D3_N
P0_D4/
TX_D2_N
P0_D2/
TX_D1_N
P0_D0/
TX_D0_N
RX2B_P
CTRL_OUT1 CTRL_OUT2 CTRL_OUT3
CTRL_OUT6 CTRL_OUT5 CTRL_OUT4
VDDA1P3_
RX_VCO_
LDO
P0_D10/
TX_D5_N
VDDD1P3_
DIG
RX2B_N
VSSA
VSSA
VSSD
VSSD
FB_CLK_P
FB_CLK_N
VSSD
VSSD
RX_VCO_ VDDA1P1_
LDO_OUT
RX_
FRAME_N
RX_
FRAME_P
TX_
FRAME_P
DATA_
CLK_P
G
H
J
CTRL_OUT7 EN_AGC
ENABLE
VSSA
VSSD
RX_VCO
P1_D11/
RX_D5_P
TX_
FRAME_N
DATA_
CLK_N
VDD_
INTERFACE
RX1B_P
VSSA
VSSA
TXNRX
SPI_DI
VSSA
VSSD
VDDA1P3_
RX_SYNTH
P1_D10/
RX_D5_N
P1_D9/
RX_D4_P
P1_D7/
RX_D3_P
P1_D5/
RX_D2_P
P1_D3/
RX_D1_P
P1_D1/
RX_D0_P
RX1B_N
RX1C_P
RX1C_N
RX1A_P
VSSA
VSSA
SPI_CLK
RESET
CLK_OUT
SPI_EN
SPI_DO
VSSA
VDDA1P3_ VDDA1P3_
TX_SYNTH
P1_D8/
RX_D4_N
P1_D6/
RX_D3_N
P1_D4/
RX_D2_N
P1_D2/
RX_D1_N
P1_D0/
RX_D0_N
K
L
VSSD
VSSA
BB
VSSA
VSSA
RBIAS
AUXADC
TX_MON1
VSSA
VSSA
VSSA
VSSA
VSSA
DNC
RX1A_N
DNC
VSSA
TX1A_P
TX1A_N
TX1B_P
TX1B_N
XTALN
M
ANALOG I/O
DIGITAL I/O
DC POWER
GROUND
DO NOT CONNECT
Figure 2. Pin Configuration, Top View
Table 12. Pin Function Descriptions
Pin No.
Type1 Mnemonic
Description
A1, A2
I
RX2A_N, RX2A_P
Receive Channel 2 Differential A Inputs. Alternatively, each pin can be used as a
single-ended input. Unused pins must be tied to ground.
A3, M3, M11
NC
DNC
Do Not Connect. Do not connect to these pins.
A4, A6, A12,
B1, B2, B12,
C2, C7 to C12,
F3, G1, H2, H3,
H5, H6, J2, K2,
L2, L3, L7 to
L12, M4, M6
GND
VSSA
Analog Ground. Tie these pins directly to the VSSD digital ground on the PCB
(one ground plane).
A5
I
TX_MON2
Transmit Channel 2 Power Monitor Input. If this pin is unused, tie it to ground.
Transmit Channel 2 Differential A Outputs. Unused pins must be tied to 1.3 V.
Transmit Channel 2 Differential B Outputs. Unused pins must be tied to 1.3 V.
Transmit VCO Supply Input. Connect to B11.
Auxiliary DAC 1 Output. If using the auxiliary DAC, connect a 0.1 µF capacitor from
this pin to ground.
A7, A8
A9, A10
A11
O
O
P
O
TX2A_N, TX2A_P
TX2B_N, TX2B_P
VDDA1P1_TX_VCO
AUXDAC1
B3
B4 to B7
B8
O
I
GPO_3 to GPO_0
VDD_GPO
3.3 V Capable General-Purpose Outputs.
2.5 V to 3.3 V Supply for the AUXDAC and General-Purpose Output Pins. If the
VDD_GPO supply is not used, this supply must be set to 1.3 V.
B9
B10
B11
I
I
O
VDDA1P3_TX_LO
VDDA1P3_TX_VCO_LDO
TX_VCO_LDO_OUT
Transmit Local Oscillator (LO) 1.3 V Supply Input.
Transmit VCO LDO 1.3 V Supply Input. Connect to B9.
Transmit VCO LDO Output. Connect to A11 and to a 1 μF bypass capacitor in series
with a 1 Ω resistor to ground.
C1, D1
C3
I
RX2C_P, RX2C_N
AUXDAC2
Receive Channel 2 Differential C Inputs. Alternatively, use each pin as a single-ended
input. Unused pins must be tied to ground.
Auxiliary DAC 2 Output. If using the auxiliary DAC, connect a 0.1 µF capacitor from
this pin to ground.
O
C4
I
I
TEST/ENABLE
CTRL_IN0 to CTRL_IN3
Test Input. Ground this pin for normal operation.
Control Inputs. Use these pins for manual Rx gain and Tx attenuation control.
Rev. D | Page 16 of 32
C5, C6, D5, D6
Data Sheet
AD9363
Pin No.
D2
D3
Type1 Mnemonic
Description
I
VDDA1P3_RX_RF
VDDA1P3_RX_TX
Receiver 1.3 V Supply Input. Connect to D3.
Receiver and Transmitter 1.3 V Supply Input.
I
D4, E4 to E6,
F4 to F6, G4
O
CTRL_OUT0, CTRL_OUT1 to Control Outputs. These pins are multipurpose outputs that have programmable
CTRL_OUT3, CTRL_OUT6 to functionality.
CTRL_OUT4, CTRL_OUT7
D7
I/O
I/O
I/O
I/O
I/O
P0_D9/TX_D4_P
P0_D7/TX_D3_P
P0_D5/TX_D2_P
P0_D3/TX_D1_P
P0_D1/TX_D0_P
VSSD
Digital Data Port 0, Data Bit 9/Transmit Differential Input Bus, Data Bit 4. This is a dual
function pin. As P0_D9, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D4_P, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
Digital Data Port 0, Data Bit 7/Transmit Differential Input Bus, Data Bit 3. This is a dual
function pin. As P0_D7, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D3_P, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
Digital Data Port 0, Data Bit 5/Transmit Differential Input Bus, Data Bit 2. This is a dual
function pin. As P0_D5, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D2_P, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
Digital Data Port 0, Data Bit 3/Transmit Differential Input Bus, Data Bit 1. This is a dual
function pin. As P0_D3, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D1_P, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
D8
D9
D10
D11
Digital Data Port 0, Data Bit 1/Transmit Differential Input Bus, Data Bit 0. This is a dual
function pin. As P0_D1, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D0_P, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
Digital Ground. Tie these pins directly to the VSSA analog ground on the PCB (one
ground plane).
D12, F7, F9,
F11, G12, H7,
H10, K12
GND
I
E1, F1
RX2B_P, RX2B_N
VDDA1P3_RX_LO
Receive Channel 2 Differential B Inputs. Alternatively, each pin can be used as a
single-ended input. Unused pins must be tied to ground.
Receive LO 1.3 V Supply Input.
E2
E3
E7
I
I
VDDA1P3_TX_LO_BUFFER Transmitter LO Buffer 1.3 V Supply Input.
Digital Data Port 0, Data Bit 11/Transmit Differential Input Bus, Data Bit 5. This is a
I/O
P0_D11/TX_D5_P
P0_D8/TX_D4_N
P0_D6/TX_D3_N
P0_D4/TX_D2_N
P0_D2/TX_D1_N
P0_D0/TX_D0_N
VDDA1P3_RX_VCO_LDO
dual function pin. As P0_D11, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 0. Alternatively, as TX_D5_P, it functions as part of the LVDS 6-
bit Tx differential input bus with internal LVDS termination.
Digital Data Port 0, Data Bit 8/Transmit Differential Input Bus, Data Bit 4. This is a dual
function pin. As P0_D8, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D4_N, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
Digital Data Port 0, Data Bit 6/Transmit Differential Input Bus, Data Bit 3. This is a dual
function pin. As P0_D6, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D3_N, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
Digital Data Port 0, Data Bit 4/Transmit Differential Input Bus, Data Bit 2. This is a dual
function pin. As P0_D4, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D2_N, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
Digital Data Port 0, Data Bit 2/Transmit Differential Input Bus, Data Bit 1. This is a dual
function pin. As P0_D2, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D1_N, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
Digital Data Port 0, Data Bit 0/Transmit Differential Input Bus, Data Bit 0. This is a dual
function pin. As P0_D0, it functions as part of the 12-bit bidirectional parallel CMOS
level Data Port 0. Alternatively, as TX_D0_N, it functions as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
E8
I/O
I/O
I/O
I/O
I/O
I
E9
E10
E11
E12
F2
Receive VCO LDO 1.3 V Supply Input. Connect to E2.
Rev. D | Page 17 of 32
AD9363
Data Sheet
Pin No.
Type1 Mnemonic
Description
F8
I/O
P0_D10/TX_D5_N
Digital Data Port 0, Data Bit 10/Transmit Differential Input Bus, Data Bit 5. This is a
dual function pin. As P0_D10, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 0. Alternatively, as TX_D5_N, it functions as part of the LVDS 6-
bit Tx differential input bus with internal LVDS termination.
F10, G10
I
FB_CLK_P, FB_CLK_N
Feedback Clock Inputs. These pins receive the FB_CLK signal that clocks in Tx data. In
CMOS mode, use FB_CLK_P as the input and tie FB_CLK_N to ground.
F12
G2
I
O
VDDD1P3_DIG
RX_VCO_LDO_OUT
1.3 V Digital Supply Input.
Receive VCO LDO Output. Connect to G3 and to a 1 μF bypass capacitor in series
with a 1 Ω resistor to ground.
G3
G5
G6
I
I
I
VDDA1P1_RX_VCO
EN_AGC
ENABLE
Receive VCO Supply Input. Connect to G2.
Manual Control Input for Automatic Gain Control (AGC).
Control Input. This pin moves the device through various operational states.
G7, G8
O
RX_FRAME_N,
RX_FRAME_P
Receive Digital Data Framing Outputs. These pins transmit the RX_FRAME signal that
indicates whether the Rx output data is valid. In CMOS mode, use RX_FRAME_P as
the output and leave RX_FRAME_N unconnected.
G9, H9
I
TX_FRAME_P,
TX_FRAME_N
Transmit Digital Data Framing Inputs. These pins receive the TX_FRAME signal that
indicates when Tx data is valid. In CMOS mode, use TX_FRAME_P as the input and tie
TX_FRAME_N to ground.
G11, H11
O
DATA_CLK_P,
DATA_CLK_N
Receive Data Clock Outputs. These pins transmit the DATA_CLK signal that the BBP
uses to clock the Rx data. In CMOS mode, use DATA_CLK_P as the output and leave
DATA_CLK_N unconnected.
H1, J1
H4
I
RX1B_P, RX1B_N
TXNRX
Receive Channel 1 Differential B Inputs. Alternatively, use each pin as a single-ended
input. Unused pins must be tied to ground.
Enable State Machine Control Signal. This pin controls the data port bus direction. A
logic low selects the Rx direction; a logic high selects the Tx direction.
I
H8
I/O
P1_D11/RX_D5_P
Digital Data Port P1, Data Bit 11/Receive Differential Output Bus, Data Bit 5. This is a
dual function pin. As P1_D11, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D5_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
H12
J3
J4
I
I
I
VDD_INTERFACE
VDDA1P3_RX_SYNTH
SPI_DI
1.2 V to 2.5 V Supply for Digital I/O Pins (1.8 V to 2.5 V in LVDS Mode).
Receiver Synthesizer 1.3 V Supply Input.
SPI Serial Data Input.
J5
I
SPI_CLK
SPI Clock Input.
J6
O
CLK_OUT
Output Clock. This pin can be configured to output either a buffered version of the
external input clock (the digital controlled crystal oscillator (DCXO)) or a divided-
down version of the internal ADC sample clock (ADC_CLK).
J7
I/O
I/O
I/O
I/O
I/O
P1_D10/RX_D5_N
P1_D9/RX_D4_P
P1_D7/RX_D3_P
P1_D5/RX_D2_P
P1_D3/RX_D1_P
Digital Data Port 1, Data Bit 10/Receive Differential Output Bus, Data Bit 5. This is a
dual function pin. As P1_D10, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D5_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
Digital Data Port 1, Data Bit 9/Receive Differential Output Bus, Data Bit 4. This is a
dual function pin. As P1_D9, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D4_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
Digital Data Port 1, Data Bit 7/Receive Differential Output Bus, Data Bit 3. This is a
dual function pin. As P1_D7, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D3_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
Digital Data Port 1, Data Bit 5/Receive Differential Output Bus, Data Bit 2. This is a
dual function pin. As P1_D5, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D2_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
J8
J9
J10
J11
Digital Data Port 1, Data Bit 3/Receive Differential Output Bus, Data Bit 1. This is a
dual function pin. As P1_D3, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D1_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
Rev. D | Page 18 of 32
Data Sheet
AD9363
Pin No.
Type1 Mnemonic
Description
J12
I/O
P1_D1/RX_D0_P
Digital Data Port 1, Data Bit 1/Receive Differential Output Bus, Data Bit 0. This is a
dual function pin. As P1_D1, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D0_P, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
K1, L1
K3
I
I
I
RX1C_P, RX1C_N
VDDA1P3_TX_SYNTH
VDDA1P3_BB
Receive Channel 1 Differential C Inputs. Alternatively, use each pin as a single-ended
input. Tie unused pins to ground.
Transmitter Synthesizer 1.3 V Supply Input. Connect this pin to a 1.3 V regulator
through a separate trace to a common supply point.
Baseband 1.3 V Supply Input. Connect this pin to a 1.3 V regulator through a
separate trace to a common supply point.
K4
K5
K6
K7
I
RESET
Asynchronous Reset Input. A logic low resets the device.
SPI Enable. Set this pin to logic low to enable the SPI bus.
I
SPI_EN
I/O
P1_D8/RX_D4_N
Digital Data Port 1, Data Bit 8/Receive Differential Output Bus, Data Bit 4. This is a
dual function pin. As P1_D8, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D4_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
K8
I/O
I/O
I/O
I/O
I
P1_D6/RX_D3_N
P1_D4/RX_D2_N
P1_D2/RX_D1_N
P1_D0/RX_D0_N
RBIAS
Digital Data Port 1, Data Bit 6/Receive Differential Output Bus, Data Bit 3. This is a
dual function pin. As P1_D6, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D3_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
Digital Data Port 1, Data Bit 4/Receive Differential Output Bus, Data Bit 2. This is a
dual function pin. As P1_D4, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D2_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
Digital Data Port 1, Data Bit 2/Receive Differential Output Bus, Data Bit 1. This is a
dual function pin. As P1_D2, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D1_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
Digital Data Port 1, Data Bit 0/Receive Differential Output Bus, Data Bit 0. This is a
dual function pin. As P1_D0, it functions as part of the 12-bit bidirectional parallel
CMOS level Data Port 1. Alternatively, as RX_D0_N, it functions as part of the LVDS 6-
bit Rx differential output bus with internal LVDS termination.
K9
K10
K11
L4
Bias Input Reference. Connect this pin through a 14.3 kΩ (1% tolerance) resistor to
ground.
L5
L6
M1, M2
I
O
I
AUXADC
SPI_DO
RX1A_P, RX1A_N
Auxiliary ADC Input. If this pin is unused, tie it to ground.
SPI Serial Data Output in 4-Wire Mode, High-Z in 3-Wire Mode.
Receive Channel 1 Differential A Inputs. Alternatively, use each pin as a single-ended
input. Tie unused pins to ground.
M5
I
TX_MON1
Transmit Channel 1 Power Monitor Input. If this pin is unused, tie it to ground.
Transmit Channel 1 Differential A Outputs. Tie unused pins to 1.3 V.
Transmit Channel 1 Differential B Outputs. Tie unused pins to 1.3 V.
Reference Frequency Connection. Connect the external clock source to XTALN.
M7, M8
M9, M10
M12
O
O
I
TX1A_P, TX1A_N
TX1B_P, TX1B_N
XTALN
1 I is input, NC is not connected, GND is ground, O is output, P is power, and I/O is input/output.
Rev. D | Page 19 of 32
AD9363
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
ATTEN is the attenuation setting. fLO_RX and fLO_TX are the receive and transmit local oscillator frequencies, respectively.
800 MHZ FREQUENCY BAND
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–4
–8
–12
–16
–56 –54 –52 –50 –48 –46 –44 –42 –40 –38 –36
700
750
800
850
900
INTERFERER POWER LEVEL (dBm)
RF FREQUENCY (MHz)
Figure 3. Rx Noise Figure vs. RF Frequency
Figure 6. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest
with PIN = −90 dBm, 5 MHz OFDM Blocker at 17.5 MHz Offset
5
4
14
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
12
3
10
8
2
1
6
0
4
–1
–2
–3
2
0
–47
–100 –90
–80
–70
–60
–50
–40
–30
–20
–10
–43
–39
–35
–31
–27
–23
Rx INPUT POWER (dBm)
INTERFERER POWER LEVEL (dBm)
Figure 4. RSSI Error vs. Rx Input Power, LTE 10 MHz Modulation
(Referenced to −50 dBm Input Power at 800 MHz)
Figure 7. Rx Noise Figure vs. Interferer Power Level, Enhanced Data Rates for
GSM Evolution (EDGE) Signal of Interest with PIN = −90 dBm, Continuous
Wave (CW) Blocker at 3 MHz Offset, Gain Index = 64
0
80
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
78
–5
–10
–15
–20
–25
–30
76
74
72
70
68
66
–
72
–68
–64
–60
–56
–52
–48
–44
–40
–36
–32
700
750
800
850
900
INTERFERER POWER LEVEL (dBm)
Rx LO FREQUENCY (MHz)
Figure 5. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest
with PIN = −82 dBm, 5 MHz Orthogonal Frequency Division Multiplexing
(OFDM) Blocker at 7.5 MHz Offset
Figure 8. Rx Gain vs. Rx LO Frequency, Gain Index = 76 (Maximum Setting)
Rev. D | Page 20 of 32
Data Sheet
AD9363
0
–20
20
15
10
5
–40
0
–60
–5
–40°C
–80
+25°C
+85°C
–10
–15
–20
–25
–100
–120
0
2000
4000
6000
8000
10000
12000
20
28
36
44
52
60
68
76
Rx GAIN INDEX
FREQUENCY (MHz)
Figure 9. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index,
f1 = 1.45 MHz, f2 = 2.89 MHz, GSM Mode
Figure 12. Rx Emission at LNA Input vs. Frequency, DC to 12 GHz, fLO_RX = 800
MHz, LTE 10 MHz, fLO_TX = 860 MHz
10.0
100
90
80
70
60
50
40
30
–40°C
+25°C
+85°C
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
20
–40°C
10
+25°C
+85°C
0
700
750
800
850
900
20
28
36
44
52
60
68
76
Tx LO FREQUENCY (MHz)
Rx GAIN INDEX
Figure 10. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index,
f1 = 2.00 MHz, f2 = 2.01 MHz, GSM Mode
Figure 13. Tx Output Power vs. Tx LO Frequency, Attenuation Setting = 0 dB,
Single-Tone Output
–100
0.5
–40°C
+25°C
+85°C
–40°C
+25°C
0.4
+85°C
–105
–110
–115
–120
–125
–130
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
700
750
800
850
900
0
10
20
30
40
50
Rx LO FREQUENCY (MHz)
ATTENUATION SETTING (dB)
Figure 14. Tx Power Control Step Linearity Error vs. Attenuation Setting
Figure 11. Rx LO Leakage vs. Rx LO Frequency
Rev. D | Page 21 of 32
AD9363
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–50
–55
–60
–65
–70
–75
–80
ATT 0dB
ATT 3dB
ATT 6dB
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–100
–15
–10
–5
0
5
10
15
700
750
800
850
900
FREQUENCY OFFSET FROM CARRIER FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Tx Output Power vs. Frequency Offset from Carrier Frequency,
LO_TX = 800 MHz, LTE 10 MHz Downlink (Digital Attenuation Variations Shown)
Figure 18. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency
f
0.5
–20
–40°C
+25°C
+85°C
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–25
–30
–35
–40
–45
–50
–55
–60
0.4
0.3
0.2
0.1
0
700
750
800
850
900
700
750
800
850
900
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. Integrated Tx LO Phase Noise vs. Frequency, 19.2 MHz REF_CLK
Figure 19. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency
–30
30
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–40°C
+25°C
+85°C
–35
–40
–45
–50
–55
–60
–65
–70
25
20
15
10
5
0
700
750
800
850
900
0
4
8
12
16
20
FREQUENCY (MHz)
Tx ATTENUATION SETTING (dB)
Figure 17. Tx Carrier Rejection vs. Frequency
Figure 20. Tx Third-Order Output Intercept Point (OIP3) vs. Tx Attenuation Setting
Rev. D | Page 22 of 32
Data Sheet
AD9363
170
–30
–35
–40
–45
–50
–55
–60
–65
–70
–40°C
+25°C
+85°C
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
165
160
155
150
145
140
0
3
6
9
12
15
700
750
800
850
900
Tx ATTENUATION SETTING (dB)
FREQUENCY (MHz)
Figure 22. Tx Single Sideband Rejection vs. Frequency,
1.5375 MHz Offset
Figure 21. Tx Signal-to-Noise Ratio (SNR) vs. Tx Attenuation Setting,
LTE 10 MHz Signal of Interest with Noise Measured at 90 MHz Offset
Rev. D | Page 23 of 32
AD9363
Data Sheet
2.4 GHZ FREQUENCY BAND
0
–5
4.0
–40°C
+25°C
+85°C
3.5
3.0
2.5
2.0
1.5
1.0
–10
–15
–20
–25
–30
0.5
–40°C
+25°C
+85°C
0
–60
–55
–50
–45
–40
–35
–30
–25
–20
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
RF FREQUENCY (MHz)
INTERFERER POWER LEVEL (dBm)
Figure 23. Rx Noise Figure vs. RF Frequency
Figure 26. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest
with PIN = −75 dBm, LTE 20 MHz Blocker at 40 MHz Offset
5
80
–40°C
–40°C
+25°C
+85°C
+25°C
+85°C
4
3
78
76
74
72
70
68
2
1
0
–1
–2
–3
66
–
100
–
90
–
80
–
70
–
60
–
50
–
40
–
30
–
20
–10
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
INPUT POWER (dBm)
Rx LO FREQUENCY (MHz)
Figure 27. Rx Gain vs. Rx LO Frequency, Gain Index = 76 (Maximum Setting)
Figure 24. RSSI Error vs. Input Power (Referenced to −50 dBm Input Power
at 2.4 GHz)
20
0
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
15
10
–5
–10
–15
–20
–25
5
0
–5
–10
–15
–20
–25
–30
20
28
36
44
52
60
68
76
–72 –68 –64 –60 –56 –52 –48 –44 –40 –36 –32 –28
Rx GAIN INDEX
INTERFERER POWER LEVEL (dBm)
Figure 28. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index,
f1 = 30 MHz, f2 = 61 MHz
Figure 25. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest
with PIN = −75 dBm, LTE 20 MHz Blocker at 20 MHz Offset
Rev. D | Page 24 of 32
Data Sheet
AD9363
80
70
60
50
40
30
20
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
20
28
36
44
52
60
68
76
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
Rx GAIN INDEX
Tx LO FREQUENCY (MHz)
Figure 32. Tx Output Power vs. Tx LO Frequency, Attenuation Setting = 0 dB,
Single-Tone Output
Figure 29. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index,
f1 = 60 MHz, f2 = 61 MHz
0.5
–100
–40°C
+25°C
+85°C
–40°C
+25°C
0.4
+85°C
–105
–110
–115
–120
–125
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–130
0
10
20
30
40
50
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
ATTENUATION SETTING (dB)
Rx LO FREQUENCY (MHz)
Figure 30. Rx Local Oscillator (LO) Leakage vs. Rx LO Frequency
Figure 33. Tx Power Control Step Linearity Error vs. Attenuation Setting
0
–20
0
ATT 0dB
ATT 3dB
ATT6dB
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
2000
4000
6000
8000
10000
12000
–25 –20 –15 –10
–5
0
5
10
15
20
25
FREQUENCY (MHz)
FREQUENCY OFFSET FROM CARRIER FREQUENCY (MHz)
Figure 31. Rx Emission at LNA Input vs. Frequency, DC to 12 GHz,
LO_RX = 2.4 GHz, LTE 20 MHz, fLO_TX = 2.46 GHz
Figure 34. Tx Output Power vs. Frequency Offset from Carrier Frequency,
f
f
LO_TX = 2.3 GHz, LTE 20 MHz Downlink (Digital Attenuation
Variations Shown)
Rev. D | Page 25 of 32
AD9363
Data Sheet
0.5
–50
–55
–60
–65
–70
–75
–80
–40°C
+25°C
+85°C
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
0.4
0.3
0.2
0.1
0
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 35. Integrated Tx LO Phase Noise vs. Frequency, 40 MHz REF_CLK
Figure 37. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency
–30
–20
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–35
–40
–45
–50
–55
–60
–65
–70
–25
–30
–35
–40
–45
–50
–55
–60
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 36. Tx Carrier Rejection vs. Frequency
Figure 38. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency
Rev. D | Page 26 of 32
Data Sheet
AD9363
30
–30
–35
–40
–45
–50
–55
–60
–65
–70
–40°C
+25°C
+85°C
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
25
20
15
10
5
0
0
4
8
12
16
20
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
Tx ATTENUATION SETTING (dB)
FREQUENCY (MHz)
Figure 41. Tx Single Sideband Rejection vs. Frequency,
3.075 MHz Offset
Figure 39. Tx Third-Order Output Intercept Point (OIP3) vs. Tx Attenuation Setting
160
–40°C
+25°C
158
+85°C
156
154
152
150
148
146
144
142
140
0
3
6
9
12
15
Tx ATTENUATION SETTING (dB)
Figure 40. Tx Signal-to-Noise Ratio (SNR) vs. Tx Attenuation Setting,
LTE 20 MHz Signal of Interest with Noise Measured at 90 MHz Offset
Rev. D | Page 27 of 32
AD9363
Data Sheet
THEORY OF OPERATION
GENERAL
TRANSMITTER
The AD9363 is a highly integrated radio frequency (RF)
transceiver capable of being configured for a wide range of
applications. The device integrates all RF, mixed-signal, and
digital blocks necessary to provide all transceiver functions in a
single device. Programmability allows this broadband transceiver
to be adapted for use with multiple communication standards,
including FDD and TDD systems. This programmability also
allows the device to interface to various BBPs using a single 12-
bit parallel data port, dual 12-bit parallel data ports, or a 12-bit
low voltage differential signaling (LVDS) interface.
The transmitter section consists of two identical and indepen-
dently controlled channels that provide all digital processing,
mixed-signal, and RF blocks necessary to implement a direct
conversion system while sharing a common frequency synthe-
sizer. The digital data received from the BBP passes through a
fully programmable 128-tap FIR filter with interpolation options.
The FIR output is sent to a series of interpolation filters that
provide additional filtering and data rate interpolation prior to
reaching the DAC. Each 12-bit DAC has an adjustable sampling
rate. Both the I and Q channels are fed to the RF block for
upconversion.
The AD9363 also provides self calibration and AGC systems to
maintain a high performance level under varying temperatures
and input signal conditions. In addition, the device includes
several test modes that allow system designers to insert test tones
and create internal loopback modes to debug their designs
during prototyping and optimize their radio configuration for a
specific application.
After being converted to baseband analog signals, the I and Q
signals are filtered to remove sampling artifacts and provide band
shaping, and then they are passed to the upconversion mixers.
At this point, the I and Q signals are recombined and modulated
on the carrier frequency for transmission to the output stage.
The output stage provides attenuation control that provides a
range of output levels while keeping the output impedance at 50 Ω.
A wide range of attenuation adjustment with fine granularity is
included to help designers optimize SNR.
RECEIVER
The receiver section contains all blocks necessary to receive RF
signals and convert them to digital data that is usable by a BBP.
Two independently controlled channels can receive signals from
different sources, allowing the device to be used in multiple
input, multiple output (MIMO) systems while sharing a
common frequency synthesizer.
Self calibration circuitry is included in the transmit channel to
provide internal adjustment capability. The transmitter also
provides a Tx monitor block that receives the transmitter output
and routes it back through an unused receiver channel to the
BBP for signal monitoring. The Tx monitor blocks are available
only in TDD mode operation while the receiver is idle.
Each channel has three inputs that can be multiplexed to the
signal chain, making the AD9363 suitable for use in diversity
systems with multiple antenna inputs. The receiver is a direct
conversion system that contains a low noise amplifier (LNA)
followed by matched in-phase (I) and quadrature (Q) amplifiers,
mixers, and band shaping filters that downconvert received
signals to baseband for digitization. External LNAs can also
be interfaced to the device, allowing designers the flexibility to
customize the receiver front end for their specific application.
CLOCK INPUT OPTIONS
The AD9363 uses a reference clock provided by an external
oscillator or clock distribution device (such as the AD9548)
connected to the XTALN pin. The frequency of this reference
clock can vary from 10 MHz to 80 MHz. This reference clock
supplies the synthesizer blocks that generate all data clocks,
sample clocks, and local oscillators inside the device.
Gain control is achieved by following a preprogrammed gain
index map that distributes gain among the blocks for optimal
performance at each level. This gain control can be achieved by
enabling the internal AGC in either fast or slow mode or by
using manual gain control, allowing the BBP to make the gain
adjustments as needed. Additionally, each channel contains
independent RSSI measurement capability, dc offset tracking,
and all circuitry necessary for self calibration.
SYNTHESIZERS
RF PLLs
The AD9363 contains two identical synthesizers to generate the
required LO signals for the RF signal paths—one for the receiver
and one for the transmitter. PLL synthesizers are fractional N
designs that incorporate completely integrated VCOs and loop
filters. In TDD mode, the synthesizers turn on and off as appropri-
ate for the Rx and Tx frames. In FDD mode, the Tx PLL and the
Rx PLL can be activated at the same time. These PLLs require no
external components.
The receivers include 12-bit, sigma-delta (Σ-Δ) ADCs and adjust-
able sample rates that produce data streams from the received
signals. The digitized signals can be conditioned further by a
series of decimation filters and a fully programmable 128-tap
FIR filter with additional decimation settings. The sample rate
of each digital filter block can also be adjusted by changing the
decimation factors to produce the desired output data rate.
Rev. D | Page 28 of 32
Data Sheet
AD9363
BB PLL
ENABLE STATE MACHINE
The AD9363 also contains a baseband PLL (BB PLL) synthesizer
that generates all baseband related clock signals. These signals
include the ADC and DAC sampling clocks, the DATA_CLK signal
(see the Digital Data Interface section), and all data framing
signals. The BB PLL is programmed from 700 MHz to 1400 MHz
based on the data rate and sample rate requirements of the system.
The AD9363 transceiver includes an ENSM that allows real-
time control over the current state of the device. The device can
be placed in several different states during normal operation,
including
•
•
•
•
•
•
Wait—power save, synthesizers disabled
Sleep—wait with all clocks and the BB PLL disabled
Tx—Tx signal chain enabled
Rx—Rx signal chain enabled
FDD—Tx and Rx signal chains enabled
Alert—synthesizers enabled
DIGITAL DATA INTERFACE
The AD9363 data interface uses parallel data ports (P0 and P1)
to transfer data between the device and the BBP. The data ports
can be configured in either single-ended CMOS format or dif-
ferential LVDS format. Both formats can be configured in multiple
arrangements to match system requirements for data ordering
and data port connections. These arrangements include single
port data bus, dual port data bus, single data rate, double data
rate, and various combinations of data ordering to transmit data
from different channels across the bus at appropriate times.
The ENSM has two control modes: SPI control and pin control.
SPI Control Mode
In SPI control mode, the ENSM is controlled asynchronously by
writing to SPI registers to advance the current state to the next
state. SPI control is considered asynchronous to the DATA_CLK
signal because the SPI clock can be derived from a different
clock reference and can still function properly. The SPI control
ENSM mode is recommended when real-time control of the
synthesizers is not necessary. SPI control can be used for real-
time control as long as the BBP can perform timed SPI writes
accurately.
Bus transfers are controlled using simple hardware handshake
signaling. The two ports can be operated in either bidirectional
(TDD) mode or in full duplex (FDD) mode, where half the bits
are used for transmitting data and half are used for receiving
data. The interface can also be configured to use only one of the
data ports for applications that do not require high data rates
and require fewer interface pins.
Pin Control Mode
DATA_CLK Signal
In pin control mode, the enable functions of the ENABLE pin
and the TXNRX pin allow real-time control of the current state.
The ENSM allows TDD or FDD operation, depending on the
configuration of the corresponding SPI register. The ENABLE
and TXNRX pin control mode is recommended if the BBP has
extra control outputs that can be controlled in real time, allow-
ing a simple 2-wire interface to control the state of the device.
To advance the current state of the ENSM to the next state,
drive the enable function of the ENABLE pin by either a pulse
(edge detected internally) or a level.
The AD9363 outputs the DATA_CLK signal that the BBP uses
to sample receiver data. The signal is synchronized with the
receiver data such that data transitions occur out of phase with
DATA_CLK. The DATA_CLK can be set to a rate that provides
single data rate (SDR) timing, where data is sampled on each rising
clock edge, or it can be set to provide double data rate (DDR)
timing, where data is captured on both rising and falling clock
edges. SDR or DDR timing applies to operation using either a
single port or both ports.
When a pulse is used, it must have a minimum pulse width of
one cycle of the FB_CLK signal. In level mode, the ENABLE
and TXNRX pins are also edge detected by the AD9363 and
must meet the same minimum pulse width requirement of one
cycle of the FB_CLK signal.
FB_CLK Signal
For transmit data, the interface uses the FB_CLK signal as the
timing reference. The FB_CLK signal allows source synchro-
nous timing with rising edge capture for burst control signals
and either rising edge capture (SDR mode) or both edge capture
(DDR mode) for transmit signal bursts. The FB_CLK signal
must have the same frequency and duty cycle as DATA_CLK.
In FDD mode, the ENABLE and TXNRX pins can be remapped
to serve as real-time Rx and Tx data transfer control signals. In
this mode, the ENABLE pin assumes the receive on (RXON)
function (controls when the Rx path is enabled and disabled), and
the TXNRX pin assumes the transmit on (TXON) function
(controls when the Tx path is enabled and disabled). The ENSM
must be controlled by SPI writes in this mode while the ENABLE
and TXNRX pins control all data flow. For more information
about RXON and TXON, see the AD9363 reference manual,
available from Integrated Wideband RF Transceiver Design
Resources.
RX_FRAME and TX_FRAME Signals
The device generates an RX_FRAME output signal whenever
the receiver outputs valid data. This signal has two modes: level
mode (the RX_FRAME signal stays high as long as the data is
valid) and pulse mode (the RX_FRAME signal pulses with a 50%
duty cycle). Similarly, the BBP must provide a TX_FRAME
signal that indicates the beginning of a valid data transmission
with a rising edge. Like the RX_FRAME signal, the TX_FRAME
signal stays high throughout the burst or it pulses with a 50% duty
cycle.
Rev. D | Page 29 of 32
AD9363
Data Sheet
SPI INTERFACE
AUXILIARY CONVERTERS
AUXADC
The AD9363 uses a serial peripheral interface (SPI) to communi-
cate with the BBP. The SPI can be configured as a 4-wire interface
with dedicated receive and transmit ports, or it can be configured
as a 3-wire interface with a bidirectional data communication
port. This bus allows the BBP to set all device control parameters
using a simple address data serial bus protocol.
The AD9363 contains an auxiliary ADC that monitors system
functions such as temperature or power output. The converter is
12 bits wide and has an input range of 0.05 V to VDDA1P3_BB −
0.05 V. When enabled, the ADC is free running. SPI reads
provide the last value latched at the ADC output. A multiplexer in
front of the ADC allows the user to select between the AUXADC
input pin and a built-in temperature sensor.
Write commands follow a 24-bit format. The first six bits set the
bus direction and number of bytes to transfer. The next 10 bits set
the address where data is to be written. The final eight bits are the
data to be transferred to the specified register address (MSB to
LSB). The AD9363 also supports an LSB first format that allows
the commands to be written in LSB to MSB format. In this mode,
the register addresses are incremented for multibyte writes.
AUXDAC1 and AUXDAC2
The AD9363 contains two identical auxiliary DACs that can
provide power amplifier (PA) bias or other system functionality.
The auxiliary DACs are 10 bits wide, have an output voltage range
of 0.5 V to VDD_GPO − 0.3 V and a current drive of 10 mA, and
can be directly controlled by the internal ENSM.
Read commands follow a similar format with the exception that
the first 16 bits are transferred on the SPI_DI pin, and the final
eight bits are read from the AD9363, either on the SPI_DO pin
in 4-wire mode or on the SPI_DI pin in 3-wire mode.
POWERING THE AD9363
The AD9363 must be powered by the following three supplies:
the analog supply (VDDx = 1.3 V), the interface supply (VDD_
INTERFACE = 1.8 V), and the GPO supply (VDD_GPO = 3.3 V).
CONTROL PINS
Control Outputs (CTRL_OUT7 to CTRL_OUT0)
For applications requiring optimal noise performance, split and
source the 1.3 V analog supply from low noise, low dropout
(LDO) regulators. Figure 42 shows the recommended method.
3.3V
The AD9363 provides eight simultaneous real-time output
signals for use as interrupts to the BBP. These outputs can
be configured to output a number of internal settings and
measurements that the BBP uses when monitoring trans-ceiver
performance in different situations. The control output pointer
register selects the information that is output to these pins, and
the control output enable register determines which signals are
activated for monitoring by the BBP. Signals used for manual
gain mode, calibration flags, state machine states, and the ADC
output are among the outputs that can be monitored on these
pins.
ADP2164
1.8V
ADP1755
ADP1755
1.3V_A
1.3V_B
Figure 42. Low Noise Power Solution for the AD9363
For applications where board space is at a premium, and
optimal noise performance is not an absolute requirement,
provide the 1.3 V analog rail directly from a switcher, and adopt
a more integrated power management unit (PMU) approach.
Figure 43 shows this approach.
Control Inputs (CTRL_IN3 to CTRL_IN0)
The AD9363 provides four edge detected control input pins. In
manual gain mode, the BBP uses these pins to change the gain
table index in real time.
1.3V
ADP5040
ADP1755
VDDx
GPO PINS (GPO_3 TO GPO_0)
LDO
1.2A
BUCK
The AD9363 provides four 3.3 V capable general-purpose logic
output pins: GPO_3, GPO_2, GPO_1, and GPO_0. These pins
control other peripheral devices such as regulators and switches
via the AD9363 SPI bus, or they function as slaves for the
internal AD9363 state machine.
AD9363
1.8V
3.3V
300mA
LDO
VDD_INTERFACE
300mA
LDO
VDD_GPO
Figure 43. Space Optimized Power Solution for the AD9363
Rev. D | Page 30 of 32
Data Sheet
AD9363
APPLICATIONS INFORMATION
For additional information about how to program the AD9363
device, see the AD9363 reference manual, and for additional
information about the AD9363 registers, see the AD9363
register map reference manual, both of which are available by
registering at the Integrated Wideband RF Transceiver Design
Resources web page and clicking Download the AD9363
Design File Package. The register map is provided as a
convenient and informational resource about low level
operation of the device; however, it is not recommended for
creating user software.
Analog Devices, Inc., provides complete drivers for the AD9363
for both bare metal/no operating system (no OS) and Linux
operating systems. The AD9361, AD9363, and AD9364 share
the same application program interface (API). For the AD9361
drivers, visit the following online locations:
•
•
Linux wiki page
No OS wiki page
For support for these drivers, visit the following online
locations:
•
•
Linux Engineer Zone® page
No OS Engineer Zone page
Rev. D | Page 31 of 32
AD9363
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
10.10
A1 BALL
CORNER
10.00 SQ
9.90
A1 BALL
CORNER
12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
8.80 SQ
G
H
J
0.80
K
L
M
0.60
REF
TOP VIEW
DETAIL A
BOTTOM VIEW
1.70 MAX
1.00 MIN
DETAIL A
0.32 MIN
0.50
0.45
0.40
COPLANARITY
0.12
SEATING
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1.
Figure 44. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-144-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
BC-144-7
BC-144-7
AD9363ABCZ
AD9363ABCZ-REEL
ADRV9363-W/PCBZ
−40°C to +85°C
−40°C to +85°C
144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board, 325 MHz to 3800 MHz Matching Circuits
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10558-0-11/16(D)
Rev. D | Page 32 of 32
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