AD9364BBCZ [ADI]
1 x 1 RF Agile Transceiver;
| 型号： | AD9364BBCZ |
| 厂家： | 
ADI |
| 描述： | 1 x 1 RF Agile Transceiver 电信 电信集成电路 |
| 文件： | 总32页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RF Agile Transceiver
AD9364
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
RF 1 × 1 transceiver with integrated 12-bit DACs and ADCs
Band: 70 MHz to 6.0 GHz
Supports time division duplex (TDD) and frequency division
duplex (FDD) operation
Tunable channel bandwidth (BW): <200 kHz to 56 MHz
3-band receiver: 3 differential or 6 single-ended inputs
Superior receiver sensitivity with a noise figure of <2.5 dB
Rx gain control
AD9364
RXB_P,
RXB_N
RXA_P,
RXA_N
ADC
P0_[D11:D0]/
TX_[D5:D0]
RXC_P,
RXC_N
Rx LO
Tx LO
P1_[D11:D0]/
RX_[D5:D0]
TX_MON
TXA_P,
TXA_N
DAC
TXB_P,
TXB_N
Real-time monitor and control signals for manual gain
Independent automatic gain control
2-band differential output transmitter
Highly linear broadband transmitter
Tx EVM: ≤−40 dB
RADIO
GPO
PLLs
SWITCHING
SPI
CTRL
CLK_OUT
CTRL
AUXADC AUXDACx
XTALN
NOTES
1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0],
AND RADIO SWITCHING CONTAIN MULTIPLE PINS.
Tx noise: ≤−157 dBm/Hz noise floor
Tx monitor: ≥66 dB dynamic range with 1 dB accuracy
Integrated fractional-N synthesizers
Figure 1.
2.4 Hz maximum local oscillator (LO) step size
Multichip synchronization
CMOS/LVDS digital interface
APPLICATIONS
Point to point communication systems
Femtocell/picocell/microcell base stations
General-purpose radio systems
GENERAL DESCRIPTION
The AD9364 is a high performance, highly integrated radio fre-
quency (RF) Agile Transceiver™ designed for use in 3G and 4G base
station applications. Its programmability and wideband capability
make it ideal for a broad range of transceiver applications.
and 128-tap FIR filters to produce a 12-bit output signal at the
appropriate sample rate.
The transmitter uses a direct conversion architecture that achieves
high modulation accuracy with ultralow noise. This transmitter
design produces a Tx EVM of ≤−40 dB, allowing significant system
margin for the external power amplifier (PA) selection. The on-
board transmit (Tx) power monitor can be used as a power
detector, enabling highly accurate Tx power measurements.
The device combines an RF front end with a flexible mixed-signal
baseband section and integrated frequency synthesizers, simpli-
fying design-in by providing a configurable digital interface to a
processor. The AD9364 operates in the 70 MHz to 6.0 GHz range,
covering most licensed and unlicensed bands. Channel bandwidths
from less than 200 kHz to 56 MHz are supported.
The fully integrated phase-locked loops (PLLs) provide low
power fractional-N frequency synthesis for all Rx and Tx channels.
All VCO and loop filter components are integrated.
The direct conversion receiver has state-of-the-art noise figure
and linearity. The receive (Rx) subsystem includes independent
automatic gain control (AGC), dc offset correction, quadrature
correction, and digital filtering, thereby eliminating the need for
these functions in the digital baseband. The AD9364 also has
flexible manual gain modes that can be externally controlled.
Two high dynamic range ADCs digitize the received I and Q
signals and pass them through configurable decimation filters
The core of the AD9364 can be powered directly from a 1.3 V
regulator. The IC is controlled via a standard 4-wire serial port and
four real-time input control pins. Comprehensive power-down
modes are included to minimize power consumption during
normal use. The AD9364 is packaged in a 10 mm × 10 mm,
144-ball chip scale package ball grid array (CSP_BGA).
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9364
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
5.5 GHz Frequency Band .......................................................... 24
Theory of Operation ...................................................................... 28
General......................................................................................... 28
Receiver........................................................................................ 28
Transmitter.................................................................................. 28
Clock Input Options .................................................................. 28
Synthesizers................................................................................. 29
Digital Data Interface................................................................. 29
Enable State Machine..................................................................... 29
SPI Interface................................................................................ 30
Control Pins ................................................................................ 30
GPO Pins (GPO_3 to GPO_0)................................................. 30
Auxiliary Converters.................................................................. 30
Packaging and Ordering Information ......................................... 31
Outline Dimensions................................................................... 31
Ordering Guide .......................................................................... 31
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Current Consumption—VDD_Interface.................................. 7
Current Consumption—VDDD1P3_DIG and VDDAx
(Combination of All 1.3 V Supplies) ......................................... 8
Absolute Maximum Ratings ..................................................... 10
Reflow Profile.............................................................................. 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 15
800 MHz Frequency Band......................................................... 15
2.4 GHz Frequency Band .......................................................... 20
REVISION HISTORY
2/14—Revision B: Initial Version
Rev. B | Page 2 of 32
Data Sheet
AD9364
SPECIFICATIONS
Electrical characteristics at VDD_GPO = 3.3 V, VDD_INTERFACE = 1.8 V, and all other VDDx pins = 1.3 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter1
RECEIVER, GENERAL
Center Frequency
Gain
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
70
6000
MHz
Minimum
0
dB
dB
dB
dB
dB
dB
Maximum
74.5
73.0
72.0
65.5
1
At 800 MHz
At 2300 MHz, RXA
At 2300 MHz, RXB, RXC
At 5500 MHz, RXA
Gain Step
Received Signal Strength
Indicator
RSSI
Range
Accuracy
100
2
dB
dB
RECEIVER, 800 MHz
Noise Figure
NF
2
dB
Maximum Rx gain
Maximum Rx gain
Third-Order Input Intermod-
ulation Intercept Point
IIP3
−18
dBm
Second-Order Input Intermod- IIP2
ulation Intercept Point
40
dBm
dBm
Maximum Rx gain
Local Oscillator (LO) Leakage
Quadrature
−122
At Rx front-end input
Gain Error
0.2
%
Phase Error
0.2
Degrees
dB
Modulation Accuracy (EVM)
Input S11
−42
−10
19.2 MHz reference clock
dB
RECEIVER, 2.4 GHz
Noise Figure
NF
3
dB
Maximum Rx gain
Maximum Rx gain
Third-Order Input Intermod-
ulation Intercept Point
IIP3
−14
dBm
Second-Order Input Intermod- IIP2
ulation Intercept Point
45
dBm
dBm
Maximum Rx gain
Local Oscillator (LO) Leakage
Quadrature
−110
At Rx front-end input
Gain Error
0.2
%
Phase Error
0.2
Degrees
dB
Modulation Accuracy (EVM)
Input S11
−42
−10
40 MHz reference clock
dB
RECEIVER, 5.5 GHz
Noise Figure
NF
3.8
dB
Maximum Rx gain
Maximum Rx gain
Third-Order Input Intermod-
ulation Intercept Point
IIP3
−17
dBm
Second-Order Input Intermod- IIP2
ulation Intercept Point
42
dBm
dBm
Maximum Rx gain
Local Oscillator (LO) Leakage
Quadrature
−95
At Rx front-end input
Gain Error
0.2
%
Phase Error
0.2
Degrees
dB
Modulation Accuracy (EVM)
−37
40 MHz reference clock
(doubled internally for RF
synthesizer)
Input S11
−10
dB
TRANSMITTER—GENERAL
Center Frequency
70
6000
MHz
dB
Power Control Range
Power Control Resolution
90
0.25
dB
Rev. B | Page 3 of 32
AD9364
Data Sheet
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
TRANSMITTER, 800 MHz
Output S22
−10
8
dB
Maximum Output Power
Modulation Accuracy (EVM)
dBm
dB
1 MHz tone into 50 Ω load
19.2 MHz reference clock
−40
23
Third-Order Output Intermod-
ulation Intercept Point
OIP3
dBm
Carrier Leakage
−50
dBc
0 dB attenuation
40 dB attenuation
90 MHz offset
−32
dBc
Noise Floor
−157
dBm/Hz
TRANSMITTER, 2.4 GHz
Output S22
−10
7.5
dB
Maximum Output Power
Modulation Accuracy (EVM)
dBm
dB
1 MHz tone into 50 Ω load
40 MHz reference clock
−40
19
Third-Order Output Intermod-
ulation Intercept Point
OIP3
dBm
Carrier Leakage
−50
dBc
0 dB attenuation
40 dB attenuation
90 MHz offset
−32
dBc
Noise Floor
−156
dBm/Hz
TRANSMITTER, 5.5 GHz
Output S22
−10
6.5
dB
Maximum Output Power
Modulation Accuracy (EVM)
dBm
dB
7 MHz tone into 50 Ω load
−36
40 MHz reference clock
(doubled internally for RF
synthesizer)
Third-Order Output Intermod-
ulation Intercept Point
OIP3
17
dBm
Carrier Leakage
−50
dBc
0 dB attenuation
40 dB attenuation
90 MHz offset
−30
dBc
Noise Floor
−151.5
dBm/Hz
TX MONITOR INPUT (TX_MON)
Maximum Input Level
Dynamic Range
4
dBm
dB
66
1
Accuracy
dB
LO SYNTHESIZER
LO Frequency Step
2.4
Hz
2.4 GHz, 40 MHz reference
clock
Integrated Phase Noise
800 MHz
0.13
° rms
100 Hz to 100 MHz, 30.72 MHz
reference clock (doubled
internally for RF synthesizer)
2.4 GHz
5.5 GHz
0.37
0.59
° rms
° rms
100 Hz to 100 MHz, 40 MHz
reference clock
100 Hz to 100 MHz, 40 MHz
reference clock (doubled
internally for RF synthesizer)
REFERENCE CLOCK (REF_CLK)
REF_CLK is either the input to
the XTALP/XTALN pins or a
line directly to the XTALN pin
Input
Frequency Range
19
10
50
80
MHz
MHz
V p-p
Crystal input
External oscillator
Signal Level
AUXILIARY CONVERTERS
ADC
1.3
12
AC-coupled external oscillator
Resolution
Bits
Input Voltage
Minimum
0.05
V
V
Maximum
VDDA1P3_BB − 0.05
DAC
Resolution
10
Bits
Rev. B | Page 4 of 32
Data Sheet
AD9364
Parameter1
Output Voltage
Minimum
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
0.5
V
Maximum
VDD_GPO − 0.3
10
V
Output Current
DIGITAL SPECIFICATIONS (CMOS)
Logic Inputs
Input Voltage
High
mA
VDD_INTERFACE × 0.8
VDD_INTERFACE
V
V
Low
0
VDD_INTERFACE × 0.2
Input Current
High
−10
−10
+10
+10
μA
μA
Low
Logic Outputs
Output Voltage
High
VDD_INTERFACE × 0.8
V
V
Low
VDD_INTERFACE × 0.2
DIGITAL SPECIFICATIONS (LVDS)
Logic Inputs
Input Voltage Range
825
1575
+100
mV
mV
Ω
Each differential input in the
pair
Input Differential Voltage
Threshold
−100
Receiver Differential Input
Impedance
100
Logic Outputs
Output Voltage
High
1375
mV
mV
mV
Low
1025
150
Output Differential Voltage
Programmable in 75 mV
steps
Output Offset Voltage
GENERAL-PURPOSE OUTPUTS
Output Voltage
High
1200
10
mV
VDD_GPO × 0.8
V
Low
VDD_GPO × 0.2
V
Output Current
SPI TIMING
mA
VDD_INTERFACE = 1.8 V
SPI_CLK
Period
tCP
20
9
ns
ns
ns
Pulse Width
tMP
SPI_ENB Setup to First SPI_CLK tSC
Rising Edge
1
Last SPI_CLK Falling Edge to
SPI_ENB Hold
tHC
0
ns
SPI_DI
Data Input Setup to
SPI_CLK
tS
2
1
ns
ns
Data Input Hold to SPI_CLK
tH
SPI_CLK Rising Edge to Output
Data Delay
4-Wire Mode
tCO
3
8
ns
ns
ns
3-Wire Mode
tCO
3
8
Bus Turnaround Time, Read
tHZM
tH
tCO (max)
After baseband processor
(BBP) drives the last address
bit
Bus Turnaround Time, Read
tHZS
0
tCO (max)
ns
After the AD9364 drives the
last data bit
Rev. B | Page 5 of 32
AD9364
Data Sheet
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 1.8 V
DATA_CLK Clock Period
tCP
16.276
ns
ns
61.44 MHz
DATA_CLK and FB_CLK Pulse
Width
tMP
45% of tCP
55% of tCP
Tx Data
TX_FRAME, P0_D, and P1_D
Setup to FB_CLK
Hold to FB_CLK
tSTX
tHTX
1
0
0
ns
ns
ns
DATA_CLK to Data Bus Output tDDRX
Delay
1.5
1.0
DATA_CLK to RX_FRAME
Delay
tDDDV
0
ns
Pulse Width
ENABLE
tENPW
tCP
tCP
ns
ns
TXNRX
tTXNRXPW
FDD independent ENSM
mode
TXNRX Setup to ENABLE
Bus Turnaround Time
Before Rx
tTXNRXSU
0
ns
TDD ENSM mode
tRPRE
tRPST
2 × tCP
2 × tCP
ns
ns
pF
pF
TDD mode
TDD mode
After Rx
Capacitive Load
Capacitive Input
3
3
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 2.5 V
DATA_CLK Clock Period
tCP
16.276
ns
ns
61.44 MHz
DATA_CLK and FB_CLK Pulse
Width
tMP
45% of tCP
55% of tCP
Tx Data
TX_FRAME, P0_D, and P1_D
Setup to FB_CLK
Hold to FB_CLK
tSTX
tHTX
1
0
0
ns
ns
ns
DATA_CLK to Data Bus Output tDDRX
Delay
1.2
1.0
DATA_CLK to RX_FRAME
Delay
tDDDV
0
ns
Pulse Width
ENABLE
tENPW
tCP
tCP
ns
ns
TXNRX
tTXNRXPW
FDD independent ENSM
mode
TXNRX Setup to ENABLE
Bus Turnaround Time
Before Rx
tTXNRXSU
0
ns
TDD ENSM mode
tRPRE
tRPST
2 × tCP
2 × tCP
ns
ns
pF
pF
TDD mode
TDD mode
After Rx
Capacitive Load
3
3
Capacitive Input
DIGITAL DATA TIMING (LVDS)
DATA_CLK Clock Period
tCP
4.069
ns
ns
245.76 MHz
DATA_CLK and FB_CLK Pulse
Width
tMP
45% of tCP
55% of tCP
Tx Data
TX_FRAME and TX_D
Setup to FB_CLK
Hold to FB_CLK
tSTX
tHTX
1
ns
ns
ns
0
DATA_CLK to Data Bus Output tDDRX
Delay
0.25
1.25
1.25
DATA_CLK to RX_FRAME
Delay
tDDDV
0.25
ns
Pulse Width
ENABLE
tENPW
tCP
tCP
ns
ns
TXNRX
tTXNRXPW
FDD independent ENSM
mode
TXNRX Setup to ENABLE
tTXNRXSU
0
ns
TDD ENSM mode
Rev. B | Page 6 of 32
Data Sheet
AD9364
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
Bus Turnaround Time
Before Rx
tRPRE
tRPST
2 × tCP
ns
ns
pF
pF
After Rx
2 × tCP
Capacitive Load
Capacitive Input
SUPPLY CHARACTERISTICS
1.3 V Main Supply Voltage
3
3
1.267
1.3
1.33
V
VDD_INTERFACE Supply
Nominal Settings
CMOS
1.2
1.8
−5
2.5
2.5
+5
V
LVDS
V
VDD_INTERFACE Tolerance
%
Tolerance is applicable to
any voltage setting
VDD_GPO Supply Nominal
Setting
1.3
−5
3.3
+5
V
When unused, must be set
to 1.3 V
VDD_GPO Tolerance
%
Tolerance is applicable to
any voltage setting
Current Consumption
VDDx, Sleep Mode
VDD_GPO
180
50
μA
μA
Sum of all input currents
No load
1 When referencing a single function of a multifunction pin in the parameters, only the portion of the pin name that is relevant to the specification is listed. For full pin
names of multifunction pins, refer to the Pin Configuration and Function Descriptions section.
CURRENT CONSUMPTION—VDD_INTERFACE
Table 2. VDD_INTERFACE = 1.2 V
Parameter
Min
Min
Min
Typ
Max
Max
Max
Unit
Test Conditions/Comments
SLEEP MODE
45
μA
Power applied, device disabled
RX AND TX, DOUBLE DATA RATE (DDR)
LTE 10 MHz
Single Port
Dual Port
LTE 20 MHz
Dual Port
2.9
2.7
mA
mA
30.72 MHz data clock, CMOS
15.36 MHz data clock, CMOS
5.2
mA
30.72 MHz data clock, CMOS
Table 3. VDD_INTERFACE = 1.8 V
Parameter
SLEEP MODE
Typ
Unit
Test Conditions/Comments
84
μA
Power applied, device disabled
RX AND TX, DDR
LTE 10 MHz
Single Port
Dual Port
LTE 20 MHz
Dual Port
4.5
4.1
mA
mA
30.72 MHz data clock, CMOS
15.36 MHz data clock, CMOS
8.0
mA
30.72 MHz data clock, CMOS
Table 4. VDD_INTERFACE = 2.5 V
Parameter
Typ
Unit
Test Conditions/Comments
SLEEP MODE
150
μA
Power applied, device disabled
RX AND TX, DDR
LTE 10 MHz
Single Port
Dual Port
6.5
6.0
mA
mA
30.72 MHz data clock, CMOS
15.36 MHz data clock, CMOS
LTE 20 MHz
Dual Port
11.5
mA
30.72 MHz data clock, CMOS
Rev. B | Page 7 of 32
AD9364
Data Sheet
CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES)
Table 5. 800 MHz, TDD Mode
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RX
5 MHz Bandwidth
10 MHz Bandwidth
20 MHz Bandwidth
TX
180
210
260
mA
mA
mA
Continuous Rx
Continuous Rx
Continuous Rx
5 MHz Bandwidth
7 dBm
−27 dBm
340
190
mA
mA
Continuous Tx
Continuous Tx
10 MHz Bandwidth
7 dBm
−27 dBm
360
220
mA
mA
Continuous Tx
Continuous Tx
20 MHz Bandwidth
7 dBm
−27 dBm
400
250
mA
mA
Continuous Tx
Continuous Tx
Table 6. TDD Mode, 2.4 GHz
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RX
5 MHz Bandwidth
10 MHz Bandwidth
20 MHz Bandwidth
TX
175
200
240
mA
mA
mA
Continuous Rx
Continuous Rx
Continuous Rx
5 MHz Bandwidth
7 dBm
−27 dBm
350
160
mA
mA
Continuous Tx
Continuous Tx
10 MHz Bandwidth
7 dBm
−27 dBm
380
220
mA
mA
Continuous Tx
Continuous Tx
20 MHz Bandwidth
7 dBm
−27 dBm
410
260
mA
mA
Continuous Tx
Continuous Tx
Table 7. TDD Mode, 5.5 GHz
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RX
5 MHz Bandwidth
40 MHz Bandwidth
TX
175
275
mA
mA
Continuous Rx
Continuous Rx
5 MHz Bandwidth
7 dBm
−27 dBm
400
240
mA
mA
Continuous Tx
Continuous Tx
40 MHz Bandwidth
7 dBm
−27 dBm
490
385
mA
mA
Continuous Tx
Continuous Tx
Rev. B | Page 8 of 32
Data Sheet
AD9364
Table 8. FDD Mode, 800 MHz
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Test Conditions/Comments
Test Conditions/Comments
RX AND TX
5 MHz Bandwidth
7 dBm
−27 dBm
10 MHz Bandwidth
7 dBm
−27 dBm
20 MHz Bandwidth
7 dBm
490
345
mA
mA
540
395
mA
mA
615
470
mA
mA
−27 dBm
Table 9. FDD Mode, 2.4 GHz
Parameter
Min
Typ
Max
Unit
RX AND TX
5 MHz Bandwidth
7 dBm
−27 dBm
10 MHz Bandwidth
7 dBm
−27 dBm
20 MHz Bandwidth
7 dBm
500
350
mA
mA
540
390
mA
mA
620
475
mA
mA
−27 dBm
Table 10. FDD Mode, 5.5 GHz
Parameter
Min
Typ
Max
Unit
RX AND TX
5 MHz Bandwidth
7 dBm
−27 dBm
550
385
mA
mA
Rev. B | Page 9 of 32
AD9364
Data Sheet
ABSOLUTE MAXIMUM RATINGS
REFLOW PROFILE
The AD9364 reflow profile is in accordance with the JEDEC
JESD20 criteria for Pb-free devices. The maximum reflow
temperature is 260°C.
Table 11.
Parameter
Rating
VDDx to VSSx
VDD_INTERFACE to VSSx
VDD_GPO to VSSx
Logic Inputs and Outputs to
VSSx
−0.3 V to +1.4 V
−0.3 V to +3.0 V
−0.3 V to +3.9 V
−0.3 V to VDD_INTERFACE + 0.3 V
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Input Current to Any Pin
Except Supplies
RF Inputs (Peak Power)
Tx Monitor Input Power (Peak
Power)
Package Power Dissipation
10 mA
Table 12. Thermal Resistance
Airflow
2.5 dBm
9 dBm
Package
Type
Velocity
(m/sec)
1, 2
1, 3
1, 4
1, 2
θJA
θJC
9.6
θJB
20.2
ΨJT
Unit
°C/W
°C/W
°C/W
144-Ball
CSP_BGA
0
32.3
29.6
27.8
0.27
0.43
0.57
(TJMAX − TA)/θJA
110°C
1.0
2.5
Maximum Junction
Temperature (TJMAX
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
)
1 Per JEDEC JESD51-7, plus JEDEC JESD51-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-STD 883, Method 1012.1.
4 Per JEDEC JESD51-8 (still air).
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. B | Page 10 of 32
Data Sheet
AD9364
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P3_ VDDA1P1_
TX_EXT_
LO_IN
VSSA
VSSA
NC
VSSA
VSSA
VSSA
A
B
C
D
E
F
RX_TX
RX_TX
RX_TX
RX_TX
TX_VCO
VDDA1P3_
TX_VCO_
LDO
VDDA1P3_
TX_LO
TX_VCO_
LDO_OUT
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
AUXDAC1
AUXDAC2
GPO_3
GPO_2
GPO_1
GPO_0
VDD_GPO
VSSA
VSSA
VSSD
TEST/
ENABLE
CTRL_IN0
CTRL_IN1
CTRL_IN2
VSSA
VSSA
VSSA
VSSA
VSSA
VDDA1P3_ VDDA1P3_
RX_RF
P0_D9/
P0_D7/
P0_D5/
P0_D3/
P0_D1/
CTRL_OUT0 CTRL_IN3
RX_TX
TX_D4_P
TX_D3_P
TX_D2_P
TX_D1_P
TX_D0_P
VDDA1P3_
TX_LO_
BUFFER
VDDA1P3_
RX_LO
P0_D11/
P0_D8/
P0_D6/
P0_D4/
P0_D2/
P0_D0/
TX_D0_N
CTRL_OUT1 CTRL_OUT2 CTRL_OUT3
CTRL_OUT6 CTRL_OUT5 CTRL_OUT4
TX_D5_P
TX_D4_N
TX_D3_N
TX_D2_N
TX_D1_N
VDDA1P3_
RX_VCO_
LDO
P0_D10/
TX_D5_N
VDDD1P3_
DIG
VSSA
VSSD
VSSD
FB_CLK_P
FB_CLK_N
VSSD
VSSD
RX_EXT_
LO_IN
RX_VCO_
LDO_OUT
VDDA1P1_
RX_VCO
RX_
FRAME_N
RX_
FRAME_P
TX_
FRAME_P
DATA_
CLK_P
CTRL_OUT7
TXNRX
EN_AGC
SYNC_IN
SPI_CLK
RESETB
AUXADC
TX_MON
ENABLE
VSSA
VSSD
G
H
J
P1_D11/
RX_D5_P
TX_
FRAME_N
DATA_
CLK_N
VDD_
INTERFACE
RXB_P
RXB_N
RXC_P
RXC_N
RXA_P
VSSA
VSSA
VSSA
VSSA
RXA_N
VSSA
VSSD
VDDA1P3_
RX_SYNTH
P1_D10/
P1_D9/
P1_D7/
P1_D5/
P1_D3/
P1_D1/
RX_D0_P
SPI_DI
CLK_OUT
SPI_ENB
SPI_DO
VSSA
RX_D5_N
RX_D4_P
RX_D3_P
RX_D2_P
RX_D1_P
VDDA1P3_ VDDA1P3_
TX_SYNTH
P1_D8/
P1_D6/
P1_D4/
P1_D2/
P1_D0/
K
L
VSSD
VSSA
BB
RX_D4_N
RX_D3_N
RX_D2_N
RX_D1_N
RX_D0_N
VSSA
RBIAS
VSSA
VSSA
VSSA
VSSA
VSSA
M
NC
VSSA
TXA_P
TXA_N
TXB_P
TXB_N
XTALP
XTALN
ANALOG I/O
DIGITAL I/O
DC POWER
GROUND
NO CONNECT
Figure 2. Pin Configuration, Top View
Table 13. Pin Function Descriptions
Pin No.
Type1 Mnemonic
Description
A1, A2, A4 to
A6, B1, B2,
I
VSSA
Analog Ground. Tie these pins directly to the VSSD digital ground on the printed
circuit board (one ground plane).
B12, C1, C2,
C7 to C12, D1,
E1, F1, F3, H2,
H3, H6, J2, K2,
L2, L3, L7 to
L12, M4, M6
A3, M3
A7 to A10, D3
A11
NC
NC
No Connect. Do not connect to these pins.
1.3 V Supply Input.
Transmit VCO Supply Input. Connect to B11.
External Transmit Local Oscillator (LO) Input. When this pin is unused, tie it to
ground.
I
I
I
VDDA1P3_RX_TX
VDDA1P1_TX_VCO
TX_EXT_LO_IN
A12
B3
B4 to B7
B8
O
O
I
AUXDAC1
GPO_3 to GPO_0
VDD_GPO
Auxiliary DAC 1 Output.
3.3 V Capable General-Purpose Outputs.
2.5 V to 3.3 V Supply for the Auxiliary DAC and General-Purpose Output Pins.
When the VDD_GPO supply is not used, this supply must be set to 1.3 V.
B9
I
VDDA1P3_TX_LO
Transmit LO 1.3 V Supply Input.
B10
B11
I
O
VDDA1P3_TX_VCO_LDO
TX_VCO_LDO_OUT
Transmit VCO LDO 1.3 V Supply Input. Connect to B9.
Transmit VCO LDO Output. Connect B11 to A11 and a 1 μF bypass capacitor in
series with a 1 Ω resistor to ground.
C3
C4
O
I
AUXDAC2
TEST/ENABLE
Auxiliary DAC 2 Output.
Test Input. Ground this pin for normal operation.
Rev. B | Page 11 of 32
AD9364
Data Sheet
Pin No.
Type1 Mnemonic
Description
C5, C6, D5, D6
I
CTRL_IN0 to CTRL_IN3
Control Inputs. Use C5, C6, D5, and D6 for manual Rx gain and Tx attenuation
control.
D2
I
VDDA1P3_RX_RF
Receiver 1.3 V Supply Input. Connect to D3.
D4, E4 to E6,
F4 to F6, G4
O
CTRL_OUT0, CTRL_OUT1 to
CTRL_OUT3, CTRL_OUT6 to
CTRL_OUT4, CTRL_OUT7
Control Outputs. These pins are multipurpose outputs that have programmable
functionality.
D7
I/O
I/O
I/O
I/O
I/O
I
P0_D9/TX_D4_P
P0_D7/TX_D3_P
P0_D5/TX_D2_P
P0_D3/TX_D1_P
P0_D1/TX_D0_P
VSSD
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D9, it functions as part of the 12-bit, bidirectional, parallel CMOS level
Data Port 0. Alternatively, this pin (TX_D4_P) can function as part of the LVDS 6-
bit Tx differential input bus with internal LVDS termination.
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data
Port 0. Alternatively, this pin (TX_D3_P) can function as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D5, it functions as part of the 12-bit, bidirectional, parallel CMOS level
Data Port 0. Alternatively, this pin (TX_D2_P) can function as part of the LVDS
6-bit Tx differential input bus with internal LVDS termination.
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D3, it functions as part of the 12-bit, bidirectional, parallel CMOS level
Data Port 0. Alternatively, this pin (TX_D1_P) can function as part of the LVDS
6-bit Tx differential input bus with internal LVDS termination.
D8
D9
D10
D11
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data
Port 0. Alternatively, this pin (TX_D0_P) can function as part of the LVDS 6-bit Tx
differential input bus with internal LVDS termination.
Digital Ground. Tie these pins directly to the VSSA analog ground on the printed
circuit board (one ground plane).
D12, F7, F9,
F11, G12, H7,
H10, K12
E2
E3
E7
I
I
VDDA1P3_RX_LO
VDDA1P3_TX_LO_BUFFER
P0_D11/TX_D5_P
Receive LO 1.3 V Supply Input.
1.3 V Supply Input.
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D11, it functions as part of the 12-bit, bidirectional, parallel CMOS level
Data Port 0. Alternatively, this pin (TX_D5_P) can function as part of the LVDS
6-bit Tx differential input bus with internal LVDS termination.
I/O
E8
I/O
I/O
I/O
I/O
I/O
I
P0_D8/TX_D4_N
P0_D6/TX_D3_N
P0_D4/TX_D2_N
P0_D2/TX_D1_N
P0_D0/TX_D0_N
VDDA1P3_RX_VCO_LDO
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D8, it functions as part of the 12-bit, bidirectional, parallel CMOS level
Data Port 0. Alternatively, this pin (TX_D4_N) can function as part of the LVDS
6-bit Tx differential input bus with internal LVDS termination.
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D6, it functions as part of the 12-bit, bidirectional, parallel CMOS level
Data Port 0. Alternatively, this pin (TX_D3_N) can function as part of the LVDS
6-bit Tx differential input bus with internal LVDS termination.
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D4, it functions as part of the 12-bit, bidirectional, parallel CMOS level
Data Port 0. Alternatively, this pin (TX_D2_N) can function as part of the LVDS
6-bit Tx differential input bus with internal LVDS termination.
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D2, it functions as part of the 12-bit, bidirectional, parallel CMOS level
Data Port 0. Alternatively, this pin (TX_D1_N) can function as part of the LVDS
6-bit Tx differential input bus with internal LVDS termination.
E9
E10
E11
E12
F2
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D0, it functions as part of the 12-bit, bidirectional, parallel CMOS level
Data Port 0. Alternatively, this pin (TX_D0_N) can function as part of the LVDS
6-bit Tx differential input bus with internal LVDS termination.
Receive VCO LDO 1.3 V Supply Input. Connect F2 to E2.
Rev. B | Page 12 of 32
Data Sheet
AD9364
Pin No.
Type1 Mnemonic
I/O P0_D10/TX_D5_N
Description
F8
Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.
As P0_D10, it functions as part of the 12-bit, bidirectional, parallel CMOS level
Data Port 0. Alternatively, this pin (TX_D5_N) can function as part of the LVDS
6-bit Tx differential input bus with internal LVDS termination.
F10, G10
I
FB_CLK_P, FB_CLK_N
Feedback Clock. These pins receive the FB_CLK signal that clocks in Tx data. In
CMOS mode, use FB_CLK_P as the input and tie FB_CLK_N to ground.
F12
G1
G2
I
I
O
VDDD1P3_DIG
RX_EXT_LO_IN
RX_VCO_LDO_OUT
1.3 V Digital Supply Input.
External Receive LO Input. When this pin is unused, tie it to ground.
Receive VCO LDO Output. Connect this pin directly to G3 and a 1 μF bypass
capacitor in series with a 1 Ω resistor to ground.
G3
G5
I
I
VDDA1P1_RX_VCO
EN_AGC
Receive VCO Supply Input. Connect this pin directly to G2 only.
Manual Control Input for Automatic Gain Control (AGC).
G6
I
ENABLE
Control Input. This pin moves the device through various operational states.
G7, G8
O
RX_FRAME_N, RX_FRAME_P
Receive Digital Data Framing Output Signal. These pins transmit the RX_FRAME
signal that indicates whether the Rx output data is valid. In CMOS mode, use
RX_FRAME_P as the output and leave RX_FRAME_N unconnected.
G9, H9
G11, H11
H1, J1
I
TX_FRAME_P, TX_FRAME_N
DATA_CLK_P, DATA_CLK_N
RXB_P, RXB_N
Transmit Digital Data Framing Input Signal. These pins receive the TX_FRAME
signal that indicates when Tx data is valid. In CMOS mode, use TX_FRAME_P as
the input and tie TX_FRAME_N to ground.
Receive Data Clock Output. These pins transmit the DATA_CLK signal that is used
by the BBP to clock Rx data. In CMOS mode, use DATA_CLK_P as the output and
leave DATA_CLK_N unconnected.
Receive Channel Differential Input B. Alternatively, each pin can be used as a
single-ended input. These inputs experience degraded performance above
3 GHz. Unused pins must be tied to ground.
O
I
H4
H5
H8
I
TXNRX
Enable State Machine Control Signal. This pin controls the data port bus direction.
Logic low selects the Rx direction; logic high selects the Tx direction.
Input to Synchronize Digital Clocks Between Multiple AD9364 Devices. If this pin
is unused, it must be tied to ground.
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D11, it functions as part of the 12-bit bidirectional parallel CMOS level
Data Port 1. Alternatively, this pin (RX_D5_P) can function as part of the LVDS
6-bit Rx differential output bus with internal LVDS termination.
I
SYNC_IN
I/O
P1_D11/RX_D5_P
H12
J3
J4
I
I
I
I
VDD_INTERFACE
VDDA1P3_RX_SYNTH
SPI_DI
1.2 V to 2.5 V Supply for Digital I/O Pins (1.8 V to 2.5 V in LVDS Mode).
1.3 V Supply Input.
SPI Serial Data Input.
SPI Clock Input.
J5
SPI_CLK
J6
O
CLK_OUT
Output Clock. This pin can be configured to output either a buffered version of the
external input clock, the DCXO, or a divided-down version of the internal ADC_CLK.
J7
I/O
I/O
I/O
I/O
I/O
P1_D10/RX_D5_N
P1_D9/RX_D4_P
P1_D7/RX_D3_P
P1_D5/RX_D2_P
P1_D3/RX_D1_P
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D10, it functions as part of the 12-bit bidirectional parallel CMOS level
Data Port 1. Alternatively, this pin (RX_D5_N) can function as part of the LVDS
6-bit Rx differential output bus with internal LVDS termination.
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D9, it functions as part of the 12-bit bidirectional parallel CMOS level
Data Port 1. Alternatively, this pin (RX_D4_P) can function as part of the LVDS
6-bit Rx differential output bus with internal LVDS termination.
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D7, it functions as part of the 12-bit bidirectional parallel CMOS level
Data Port 1. Alternatively, this pin (RX_D3_P) can function as part of the LVDS
6-bit Rx differential output bus with internal LVDS termination.
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D5, it functions as part of the 12-bit bidirectional parallel CMOS level
Data Port 1. Alternatively, this pin (RX_D2_P) can function as part of the LVDS
6-bit Rx differential output bus with internal LVDS termination.
J8
J9
J10
J11
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D3, it functions as part of the 12-bit bidirectional parallel CMOS level
Data Port 1. Alternatively, this pin (RX_D1_P) can function as part of the LVDS
6-bit Rx differential output bus with internal LVDS termination.
Rev. B | Page 13 of 32
AD9364
Data Sheet
Pin No.
Type1 Mnemonic
Description
J12
I/O
P1_D1/RX_D0_P
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D1, it functions as part of the 12-bit bidirectional parallel CMOS level
Data Port 1. Alternatively, this pin (RX_D0_P) can function as part of the LVDS
6-bit Rx differential output bus with internal LVDS termination.
K1, L1
I
RXC_P, RXC_N
Receive Channel Differential Input C. Alternatively, each pin can be used as a
single-ended input. These inputs experience degraded performance above
3 GHz. Unused pins must be tied to ground.
K3
K4
K5
K6
K7
I
I
I
I
VDDA1P3_TX_SYNTH
VDDA1P3_BB
RESETB
SPI_ENB
P1_D8/RX_D4_N
1.3 V Supply Input.
1.3 V Supply Input.
Asynchronous Reset. Logic low resets the device.
SPI Enable Input. Set this pin to logic low to enable the SPI bus.
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D8, it functions as part of the 12-bit bidirectional parallel CMOS level
Data Port 1. Alternatively, this pin (RX_D4_N) can function as part of the LVDS
6-bit Rx differential output bus with internal LVDS termination.
I/O
K8
I/O
I/O
I/O
I/O
I
P1_D6/RX_D3_N
P1_D4/RX_D2_N
P1_D2/RX_D1_N
P1_D0/RX_D0_N
RBIAS
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D6, it functions as part of the 12-bit bidirectional parallel CMOS level
Data Port 1. Alternatively, this pin (RX_D3_N) can function as part of the LVDS
6-bit Rx differential output bus with internal LVDS termination.
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D4, it functions as part of the 12-bit bidirectional parallel CMOS level
Data Port 1. Alternatively, this pin (RX_D2_N) can function as part of the LVDS
6-bit Rx differential output bus with internal LVDS termination.
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D2, it functions as part of the 12-bit bidirectional parallel CMOS level
Data Port 1. Alternatively, this pin (RX_D1_N) can function as part of the LVDS
6-bit Rx differential output bus with internal LVDS termination.
Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.
As P1_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data
Port 1. Alternatively, this pin (RX_D0_N) can function as part of the LVDS 6-bit Rx
differential output bus with internal LVDS termination.
K9
K10
K11
L4
Bias Input Reference. Connect this pin through a 14.3 kΩ (1% tolerance) resistor
to ground.
L5
L6
M1, M2
I
O
I
AUXADC
SPI_DO
RXA_ P, RXA_N
Auxiliary ADC Input. If this pin is unused, tie it to ground.
SPI Serial Data Output in 4-Wire Mode, High-Z in 3-Wire Mode.
Receive Channel Differential Input A. Alternatively, each pin can be used as a
single-ended input. Unused pins must be tied to ground.
M5
I
TX_MON
Transmit Channel Power Monitor Input. If this pin is unused, tie it to ground.
Transmit Channel Differential Output A. Unused pins must be tied to 1.3 V.
Transmit Channel Differential Output B. Unused pins must be tied to 1.3 V.
Reference Frequency Crystal Connections. When a crystal is used, connect it
between these two pins. When an external clock source is used, connect it to
XTALN and leave XTALP unconnected.
M7, M8
M9, M10
M11, M12
O
O
I
TXA_P, TXA_N
TXB_P, TXB_N
XTALP, XTALN
1 I is input, O is output, I/O is input/output, NC is not connected.
Rev. B | Page 14 of 32
Data Sheet
AD9364
TYPICAL PERFORMANCE CHARACTERISTICS
800 MHZ FREQUENCY BAND
0
–5
4.0
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–10
–15
–20
–25
–30
–35
–40
–45
–75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25
700
750
800
850
900
INPUT POWER (dBm)
FREQUENCY (MHz)
Figure 3. Rx Noise Figure vs. Frequency
Figure 6. Rx EVM vs. Input Power, 64 QAM LTE 10 MHz Mode,
19.2 MHz REF_CLK
5
4
0
–40°C
+25°C
+85°C
–5
–40°C
+25°C
+85°C
–10
–15
–20
–25
–30
–35
–40
–45
3
2
1
0
–1
–2
–3
–100 –90
–80
–70
–60
–50
–40
–30
–20
–10
–90
–80
–70
–60
–50
–40
–30
–20
–10
INPUT POWER (dBm)
INPUT POWER (dBm)
Figure 4. RSSI Error vs. Input Power, LTE 10 MHz Modulation
(Referenced to −50 dBm Input Power at 800 MHz)
Figure 7. Rx EVM vs. Input Power, GSM Mode, 30.72 MHz REF_CLK (Doubled
Internally for RF Synthesizer)
3
0
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
2
1
0
–5
–10
–15
–20
–25
–30
–1
–2
–3
–
72
–68
–64
–60
–56
–52
–48
–44
–40
–36
–32
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
INPUT POWER (dBm)
INTERFERER POWER LEVEL (dBm)
Figure 5. RSSI Error vs. Input Power, EDGE Modulation
(Referenced to −50 dBm Input Power at 800 MHz)
Figure 8. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with
PIN = −82 dBm, 5 MHz OFDM Blocker at 7.5 MHz Offset
Rev. B | Page 15 of 32
AD9364
Data Sheet
0
20
15
–40°C
+25°C
+85°C
10
–4
–8
5
0
–5
–40°C
+25°C
+85°C
–10
–15
–20
–25
–12
–16
–56 –54 –52 –50 –48 –46 –44 –42 –40 –38 –36
20
28
36
44
52
60
68
76
Rx GAIN INDEX
INTERFERER POWER LEVEL (dBm)
Figure 12. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index,
f1 = 1.45 MHz, f2 = 2.89 MHz, GSM Mode
Figure 9. Rx EVM vs. Interferer Power Level, LTE 10 MHz Signal of Interest with
PIN = −90 dBm, 5 MHz OFDM Blocker at 17.5 MHz Offset
14
100
90
–40°C
+25°C
+85°C
12
10
8
80
70
–40°C
+25°C
+85°C
60
50
40
30
20
10
0
6
4
2
0
–47
20
28
36
44
52
60
68
76
–43
–39
–35
–31
–27
–23
INTERFERER POWER LEVEL (dBm)
Rx GAIN INDEX
Figure 10. Rx Noise Figure vs. Interferer Power Level, EDGE Signal of Interest
with PIN = −90 dBm, CW Blocker at 3 MHz Offset, Gain Index = 64
Figure 13. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index,
f1 = 2.00 MHz, f2 = 2.01 MHz, GSM Mode
80
–100
–40°C
–40°C
+25°C
+85°C
+25°C
+85°C
78
–105
–110
–115
–120
–125
–130
76
74
72
70
68
66
700
750
800
850
900
700
750
800
850
900
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. Rx Gain vs. Frequency, Gain Index = 76 (Maximum Setting)
Figure 14. Rx Local Oscillator (LO) Leakage vs. Frequency
Rev. B | Page 16 of 32
Data Sheet
AD9364
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
ATT 0dB
ATT 3dB
ATT 6dB
–20
–40
–60
–80
–100
–120
0
2000
4000
6000
8000
10000
12000
–15
–10
–5
0
5
10
15
FREQUENCY (MHz)
FREQUENCY OFFSET (MHz)
Figure 15. Rx Emission at LNA Input, DC to 12 GHz, fLO_RX = 800 MHz,
LTE 10 MHz, fLO_TX = 860 MHz
Figure 18. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX
800 MHz, LTE 10 MHz Downlink (Digital Attenuation Variations Shown)
=
10.0
20
–40°C
+25°C
+85°C
ATT 0dB
ATT 3dB
ATT 6dB
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
0
–20
–40
–60
–80
–100
700
750
800
850
900
FREQUENCY (MHz)
FREQUENCY OFFSET (MHz)
Figure 16. Tx Output Power vs. Frequency, Attenuation Setting = 0 dB,
Single Tone Output
Figure 19. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX =
800 MHz, GSM Downlink (Digital Attenuation Variations Shown), 3 MHz Range
0.5
20
–40°C
+25°C
0.4
+85°C
ATT 0dB
0
ATT 3dB
ATT 6dB
0.3
0.2
–20
0.1
–40
–60
0
–0.1
–0.2
–0.3
–0.4
–0.5
–80
–100
–120
0
10
20
30
40
50
–6
–4
–2
0
2
4
6
ATTENUATION SETTING (dB)
FREQUENCY OFFSET (MHz)
Figure 17. Tx Power Control Linearity Error vs. Attenuation Setting
Figure 20. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX
=
800 MHz, GSM Downlink (Digital Attenuation Variations Shown), 12 MHz Range
Rev. B | Page 17 of 32
AD9364
Data Sheet
–20
–25
–30
–35
–40
–45
0.30
0.25
0.20
0.15
0.10
0.05
0
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–50
0
5
10
15
20
25
30
35
40
700
750
800
850
900
ATTENUATION SETTING (dB)
FREQUENCY (MHz)
Figure 21. Tx EVM vs. Transmitter Attenuation Setting, fLO_TX
800 MHz, LTE 10 MHz, 64 QAM Modulation, 19.2 MHz REF_CLK
=
Figure 24. Integrated Tx LO Phase Noise vs. Frequency, 30.72 MHz REF_CLK
(Doubled Internally for RF Synthesizer)
–30
–20
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–35
–40
–45
–50
–55
–60
–65
–70
–40°C
–25
+25°C
+85°C
–30
–35
–40
–45
–50
700
750
800
850
900
0
10
20
30
40
50
FREQUENCY (MHz)
ATTENUATION SETTING (dB)
Figure 22. Tx EVM vs. Transmitter Attenuation Setting, fLO_TX = 800 MHz, GSM
Modulation, 30.72 MHz REF_CLK (Doubled Internally for RF Synthesizer)
Figure 25. Tx Carrier Rejection vs. Frequency
0.5
–50
–55
–60
–65
–70
–75
–80
–40°C
+25°C
+85°C
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
0.4
0.3
0.2
0.1
0
700
750
800
850
900
700
750
800
850
900
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 23. Integrated Tx LO Phase Noise vs. Frequency, 19.2 MHz REF_CLK
Figure 26. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency
Rev. B | Page 18 of 32
Data Sheet
AD9364
–20
170
165
160
155
150
145
140
ATT 0, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
ATT 25, –40°C
ATT 50, –40°C
–25
–30
–35
–40
–45
–50
–55
–60
–40°C
+25°C
+85°C
700
750
800
850
900
0
4
8
12
16
20
FREQUENCY (MHz)
ATTENUATION SETTING (dB)
Figure 27. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency
Figure 30. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting,
GSM Signal of Interest with Noise Measured at 20 MHz Offset
30
–30
–40°C
+25°C
+85°C
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–35
–40
–45
–50
–55
–60
–65
–70
25
20
15
10
5
0
0
4
8
12
16
20
700
750
800
850
900
ATTENUATION SETTING (dB)
FREQUENCY (MHz)
Figure 28. Tx Third-Order Output Intercept Point (OIP3) vs.
Attenuation Setting
Figure 31. Tx Single Sideband (SSB) Rejection vs. Frequency,
1.5375 MHz Offset
170
–40°C
+25°C
+85°C
165
160
155
150
145
140
0
3
6
9
12
15
ATTENUATION SETTING (dB)
Figure 29. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting,
LTE 10 MHz Signal of Interest with Noise Measured at 90 MHz Offset
Rev. B | Page 19 of 32
AD9364
Data Sheet
2.4 GHZ FREQUENCY BAND
0
–5
4.0
–40°C
+25°C
+85°C
3.5
3.0
2.5
2.0
1.5
1.0
–10
–15
–20
–25
–30
0.5
0
–40°C
+25°C
+85°C
–72 –68 –64 –60 –56 –52 –48 –44 –40 –36 –32 –28
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
INTERFERER POWER LEVEL (dBm)
FREQUENCY (MHz)
Figure 32. Rx Noise Figure vs. Frequency
Figure 35. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest
with PIN = −75 dBm, LTE 20 MHz Blocker at 20 MHz Offset
5
0
–40°C
–40°C
+25°C
+85°C
+25°C
+85°C
4
–5
–10
–15
–20
–25
–30
3
2
1
0
–1
–2
–3
–100
–
90
–
80
–
70
–
60
–
50
–
40
–
30
–
20
–
10
–60
–55
–50
–45
–40
–35
–30
–25
–20
INPUT POWER (dBm)
INTERFERER POWER LEVEL (dBm)
Figure 33. RSSI Error vs. Input Power, Referenced to −50 dBm Input Power
at 2.4 GHz
Figure 36. Rx EVM vs. Interferer Power Level, LTE 20 MHz Signal of Interest
with PIN = −75 dBm, LTE 20 MHz Blocker at 40 MHz Offset
0
80
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
–5
–10
–15
–20
–25
–30
–35
–40
–45
78
76
74
72
70
68
66
–75 –70 –65 –60 –55 –50 –45 –40 –35 –30 –25
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
INPUT POWER (dBm)
FREQUENCY (MHz)
Figure 37. Rx Gain vs. Frequency, Gain Index = 76 (Maximum Setting)
Figure 34. Rx EVM vs. Input Power, 64 QAM LTE 20 MHz Mode,
40 MHz REF_CLK
Rev. B | Page 20 of 32
Data Sheet
AD9364
20
0
–20
–40°C
+25°C
+85°C
15
10
5
–40
0
–60
–5
–10
–15
–20
–25
–80
–100
–120
0
2000
4000
6000
8000
10000
12000
20
28
36
44
52
60
68
76
Rx GAIN INDEX
FREQUENCY (MHz)
Figure 38. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index,
f1 = 30 MHz, f2 = 61 MHz
Figure 41. Rx Emission at LNA Input, DC to 12 GHz, fLO_RX = 2.4 GHz,
LTE 20 MHz, fLO_TX = 2.46 GHz
80
10.0
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
70
60
50
40
30
20
20
28
36
44
52
60
68
76
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
Rx GAIN INDEX
FREQUENCY (MHz)
Figure 39. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index,
f1 = 60 MHz, f2 = 61 MHz
Figure 42. Tx Output Power vs. Frequency, Attenuation Setting = 0 dB,
Single Tone Output
–100
0.5
–40°C
+25°C
+85°C
–40°C
+25°C
0.4
+85°C
–105
–110
–115
–120
–125
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–130
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
0
10
20
30
40
50
FREQUENCY (MHz)
ATTENUATION SETTING (dB)
Figure 43. Tx Power Control Linearity Error vs. Attenuation Setting
Figure 40. Rx Local Oscillator (LO) Leakage vs. Frequency
Rev. B | Page 21 of 32
AD9364
Data Sheet
0
–30
–35
–40
–45
–50
–55
–60
–65
–70
ATT 0dB
ATT 3dB
ATT 6dB
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–20
–40
–60
–80
–100
–120
–25 –20 –15 –10
–5
0
5
10
15
20
25
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
FREQUENCY OFFSET (MHz)
FREQUENCY (MHz)
Figure 44. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX
2.3 GHz, LTE 20 MHz Downlink (Digital Attenuation Variations Shown)
=
Figure 47. Tx Carrier Rejection vs. Frequency
–20
–50
–55
–60
–65
–70
–75
–80
–40°C
+25°C
+85°C
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–25
–30
–35
–40
–45
–50
0
5
10
15
20
25
30
35
40
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
ATTENUATION SETTING (dB)
FREQUENCY (MHz)
Figure 45. Tx EVM vs. Transmitter Attenuation Setting, 40 MHz REF_CLK,
LTE 20 MHz, 64 QAM Modulation
Figure 48. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency
0.5
–20
–40°C
+25°C
+85°C
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–25
–30
–35
–40
–45
–50
–55
–60
0.4
0.3
0.2
0.1
0
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 46. Integrated Tx LO Phase Noise vs. Frequency, 40 MHz REF_CLK
Figure 49. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency
Rev. B | Page 22 of 32
Data Sheet
AD9364
30
–30
–35
–40
–45
–50
–55
–60
–65
–70
–40°C
+25°C
+85°C
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
25
20
15
10
5
0
0
4
8
12
16
20
1800 1900 2000 2100 2200 2300 2400 2500 2600 2700
FREQUENCY (MHz)
ATTENUATION SETTING (dB)
Figure 50. Tx Third-Order Output Intercept Point (OIP3) vs.
Attenuation Setting
Figure 52. Tx Single Sideband (SSB) Rejection vs. Frequency,
3.075 MHz Offset
160
–40°C
+25°C
+85°C
158
156
154
152
150
148
146
144
142
140
0
3
6
9
12
15
ATTENUATION SETTING (dB)
Figure 51. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting,
LTE 20 MHz Signal of Interest with Noise Measured at 90 MHz Offset
Rev. B | Page 23 of 32
AD9364
Data Sheet
5.5 GHZ FREQUENCY BAND
6
5
0
5
4
–5
3
–10
–15
–20
–25
–40°C
+25°C
+85°C
–40°C
+25°C
+85°C
2
1
0
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
–72
–67
–62
–57
–52
–47
–42
–37
–32
FREQUENCY (GHz)
INTERFERER POWER LEVEL (dBm)
Figure 53. Rx Noise Figure vs. Frequency
Figure 56. Rx EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of Interest
with PIN = −74 dBm, WiMAX 40 MHz Blocker at 40 MHz Offset
5
5
4
3
0
–40°C
+25°C
+85°C
–5
2
–40°C
+25°C
+85°C
–10
–15
–20
–25
1
0
–1
–2
–3
–90
–80
–70
–60
–50
–40
–30
–20
–10
–60
–55
–50
–45
–40
–35
–30
–25
INTERFERER POWER LEVEL (dBm)
INPUT POWER (dBm)
Figure 54. RSSI Error vs. Input Power, Referenced to −50 dBm Input Power
at 5.8 GHz
Figure 57. Rx EVM vs. Interferer Power Level, WiMAX 40 MHz Signal of Interest
with PIN = −74 dBm, WiMAX 40 MHz Blocker at 80 MHz Offset
0
70
68
66
–5
–40°C
–10
–15
–20
–25
–30
–35
–40
+25°C
+85°C
64
–40°C
+25°C
+85°C
62
60
–74
–68
–62
–56
–50
–44
–38
–32
–26
–20
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
INPUT POWER (dBm)
FREQUENCY (GHz)
Figure 58. Rx Gain vs. Frequency, Gain Index = 76 (Maximum Setting)
Figure 55. Rx EVM vs. Input Power, 64 QAM WiMAX 40 MHz Mode,
40 MHz REF_CLK (Doubled Internally for RF Synthesizer)
Rev. B | Page 24 of 32
Data Sheet
AD9364
20
15
10
5
0
–20
–40
–40°C
+25°C
+85°C
0
–5
–60
–80
–10
–15
–20
–100
–120
6
16
26
36
46
56
66
76
0
5
10
15
20
25
30
Rx GAIN INDEX
FREQUENCY (GHz)
Figure 59. Third-Order Input Intercept Point (IIP3) vs. Rx Gain Index,
f1 = 50 MHz, f2 = 101 MHz
Figure 62. Rx Emission at LNA Input, DC to 26 GHz, fLO_RX = 5.8 GHz,
WiMAX 40 MHz
80
70
60
10
–40°C
+25°C
+85°C
9
8
7
6
5
4
–40°C
+25°C
50
40
30
20
+85°C
20
28
36
44
52
60
68
76
5.0
5.1
5.2
5.3
5.4 5.5. 5.6
5.7
5.8
5.9
6.0
Rx GAIN INDEX
FREQUENCY (GHz)
Figure 60. Second-Order Input Intercept Point (IIP2) vs. Rx Gain Index,
f1 = 70 MHz, f2 = 71 MHz
Figure 63. Tx Output Power vs. Frequency, Attenuation Setting = 0 dB,
Single Tone
–90
–92
–94
–96
0.5
0.4
0.3
0.2
–98
0.1
–40°C
–100
–102
–104
–106
–108
–110
+25°C
+85°C
0.0
–0.1
–0.2
–40°C
+25°C
+85°C
–0.3
–0.4
–0.5
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
0
10
20
30
40
50
60
70
80
90
FREQUENCY (GHz)
ATTENUATION SETTING (dB)
Figure 61. Rx Local Oscillator (LO) Leakage vs. Frequency
Figure 64. Tx Power Control Linearity Error vs. Attenuation Setting
Rev. B | Page 25 of 32
AD9364
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
ATT 0dB
ATT 3dB
ATT 6dB
–50 –40 –30 –20 –10
0
10
20
30
40
50
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
FREQUENCY OFFSET (MHz)
FREQUENCY (GHz)
Figure 65. Tx Spectrum vs. Frequency Offset from Carrier Frequency, fLO_TX
=
Figure 68. Tx Carrier Rejection vs. Frequency
5.8 GHz, WiMAX 40 MHz Downlink (Digital Attenuation Variations Shown)
–30
–50
–55
–60
–65
–70
–75
–80
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–32
–34
–36
–40°C
+25°C
+85°C
–38
–40
0
2
4
6
8
10
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
ATTENUATION SETTING (dB)
FREQUENCY (GHz)
Figure 66. Tx EVM vs. Transmitter Attenuation Setting,
Figure 69. Tx Second-Order Harmonic Distortion (HD2) vs. Frequency
WiMAX 40 MHz, 64 QAM Modulation, fLO_TX = 5.495 GHz, 40 MHz REF_CLK
(Doubled Internally for RF Synthesizer)
0.8
0.7
0.6
0.5
–10
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–15
–20
–25
–30
–35
–40
–45
–50
0.4
–40°C
+25°C
+85°C
0.3
0.2
0.1
0
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 67. Integrated Tx LO Phase Noise vs. Frequency, 40 MHz REF_CLK
(Doubled Internally for RF Synthesizer)
Figure 70. Tx Third-Order Harmonic Distortion (HD3) vs. Frequency
Rev. B | Page 26 of 32
Data Sheet
AD9364
20
16
12
–30
–35
–40
–45
–50
–55
–60
–65
–70
ATT 0, –40°C
ATT 25, –40°C
ATT 50, –40°C
ATT 0, +25°C
ATT 25, +25°C
ATT 50, +25°C
ATT 0, +85°C
ATT 25, +85°C
ATT 50, +85°C
–40°C
+25°C
+85°C
8
4
0
–4
0
4
8
12
16
20
5.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.0
ATTENUATION SETTING (dB)
FREQUENCY (GHz)
Figure 71. Tx Third-Order Output Intercept Point (OIP3) vs.
Attenuation Setting, fLO_TX = 5.8 GHz
Figure 73. Tx Single Sideband (SSB) Rejection vs. Frequency, 7 MHz Offset
150
149
148
147
146
145
144
143
142
–40°C
+25°C
+85°C
0
3
6
9
12
15
ATTENUATION SETTING (dB)
Figure 72. Tx Signal-to-Noise Ratio (SNR) vs. Transmitter Attenuation Setting,
WiMAX 40 MHz Signal of Interest with Noise Measured at 90 MHz Offset,
fLO_TX = 5.745 GHz
Rev. B | Page 27 of 32
AD9364
Data Sheet
THEORY OF OPERATION
GENERAL
TRANSMITTER
The transmitter section consists of two differential output stages
that can be multiplexed to the transmit channel. The transmit
channel provides all digital processing, mixed signal, and RF
blocks necessary to implement a direct conversion system. The
digital data received from the BBP passes through a fully
programmable 128-tap FIR filter with interpolation options. The
FIR output is sent to a series of interpolation filters that provide
additional filtering and data rate interpolation prior to reaching the
DAC. Each 12-bit DAC has an adjustable sampling rate. Both
the I and Q channels are fed to the RF block for upconversion.
The AD9364 is a highly integrated radio frequency (RF)
transceiver capable of being configured for a wide range of
applications. The device integrates all RF, mixed signal, and
digital blocks necessary to provide all transceiver functions in a
single device. Programmability allows this broadband transceiver
to be adapted for use with multiple communication standards,
including frequency division duplex (FDD) and time division
duplex (TDD) systems. This programmability also allows the
device to be interfaced to various baseband processors (BBPs) using
a single 12-bit parallel data port, dual 12-bit parallel data ports,
or a 12-bit low voltage differential signaling (LVDS) interface.
When converted to baseband analog signals, the I and Q signals
are filtered to remove sampling artifacts and fed to the upcon-
version mixers. At this point, the I and Q signals are recombined
and modulated on the carrier frequency for transmission to the
output stage. The combined signal also passes through analog
filters that provide additional band shaping, and then the signal
is transmitted to the output amplifier. The transmit channel
provides a wide attenuation adjustment range with fine granularity
to help designers optimize signal-to-noise ratio (SNR).
The AD9364 also provides self calibration and automatic gain
control (AGC) systems to maintain a high performance level
under varying temperatures and input signal conditions. In addi-
tion, the device includes several test modes that allow system
designers to insert test tones and create internal loopback modes
that can be used by designers to debug their designs during
prototyping and optimize their radio configuration for a
specific application.
Self calibration circuitry is built into each transmit channel to
provide automatic real-time adjustment. The transmitter block
also provides a Tx monitor block. This block monitors the
transmitter output and routes it back through the receiver
channel to the BBP for signal monitoring. The Tx monitor
block is available only in TDD mode operation while the
receiver is idle.
RECEIVER
The receiver section contains all blocks necessary to receive RF
signals and convert them to digital data that is usable by a BBP.
It has three inputs that can be multiplexed to the signal chain,
making the AD9364 suitable for use in multiband systems with
multiple antenna inputs. The receiver is a direct conversion
system that contains a low noise amplifier (LNA), followed by
matched in-phase (I) and quadrature (Q) amplifiers, mixers,
and band shaping filters that downconvert received signals to
baseband for digitization. External LNAs can also be interfaced
to the device, allowing designers the flexibility to customize the
receiver front end for their specific application.
CLOCK INPUT OPTIONS
The AD9364 operates using a reference clock that can be provided
by two different sources. The first option is to use a dedicated
crystal with a frequency between 19 MHz and 50 MHz connected
between the XTALP and XTALN pins. The second option is to
connect an external oscillator or clock distribution device (such as
the AD9548) to the XTALN pin (with the XTALP pin remaining
unconnected). If an external oscillator is used, the frequency
can vary between 10 MHz and 80 MHz. This reference clock is
used to supply the synthesizer blocks that generate all data
clocks, sample clocks, and local oscillators inside the device.
Gain control is achieved by following a preprogrammed gain
index map that distributes gain among the blocks for optimal
performance at each level. This can be achieved by enabling the
internal AGC in either fast or slow mode or by using manual
gain control, allowing the BBP to make the gain adjustments as
needed. Additionally, each channel contains independent RSSI
measurement capability, dc offset tracking, and all circuitry
necessary for self calibration.
Errors in the crystal frequency can be removed by using the
digitally programmable digitally controlled crystal oscillator
(DCXO) function to adjust an on-chip variable capacitor. This
capacitor can tune the crystal frequency variance out of the
system, resulting in a more accurate reference clock from which
all other frequency signals are generated. This function can also
be used with on-chip temperature sensing to provide oscillator
frequency temperature compensation during normal operation.
The receiver includes 12-bit, Σ-Δ ADCs and adjustable sample
rates that produce data streams from the received signals. The
digitized signals can be conditioned further by a series of
decimation filters and a fully programmable 128-tap FIR filter
with additional decimation settings. The sample rate of each
digital filter block is adjustable by changing decimation factors
to produce the desired output data rate.
Rev. B | Page 28 of 32
Data Sheet
AD9364
RX_FRAME Signal
SYNTHESIZERS
The device generates an RX_FRAME output signal whenever the
receiver outputs valid data. This signal has two modes: level
mode (RX_FRAME stays high as long as the data is valid) and
pulse mode (RX_FRAME pulses with a 50% duty cycle). Similarly,
the BBP must provide a TX_FRAME signal that indicates the
beginning of a valid data transmission with a rising edge. Similar
to the RX_FRAME signal, the TX_FRAME signal can remain
high throughout the burst or it can be pulsed with a 50% duty
cycle.
RF PLLs
The AD9364 contains two identical synthesizers to generate the
required LO signals for the RF signal paths—one for the receiver
and one for the transmitter. Phase-locked loop (PLL) synthesizers
are fractional-N designs incorporating completely integrated
voltage controlled oscillators (VCOs) and loop filters. In TDD
mode, the synthesizers turn on and off as appropriate for the Rx
and Tx frames. In FDD mode, the Tx PLL and the Rx PLL can
be activated at the same time. These PLLs require no external
components.
ENABLE STATE MACHINE
BB PLL
The AD9364 transceiver includes an enable state machine (ENSM)
that allows real-time control over the current state of the device.
The device can be placed in several different states during normal
operation, including
The AD9364 also contains a baseband PLL (BB PLL)
synthesizer that is used to generate all baseband related clock
signals. These include the ADC and DAC sampling clocks, the
DATA_CLK signal (see the Digital Data Interface section), and
all data framing signals. This PLL is programmed from 700 MHz
to 1400 MHz based on the data rate and sample rate requirements
of the system.
• Wait—power save, synthesizers disabled
• Sleep—wait with all clocks/BB PLL disabled
• Tx—Tx signal chain enabled
• Rx—Rx signal chain enabled
DIGITAL DATA INTERFACE
• FDD—Tx and Rx signal chains enabled
• Alert—synthesizers enabled
The AD9364 data interface uses parallel data ports (P0 and P1)
to transfer data between the device and the BBP. The data ports can
be configured in either single-ended CMOS format or differential
LVDS format. Both formats can be configured in multiple arrange-
ments to match system requirements for data ordering and data
port connections. These arrangements include single port data
bus, dual port data bus, single data rate, and double data rate.
The ENSM has two possible control methods: SPI control and
pin control.
SPI Control Mode
In SPI control mode, the ENSM is controlled asynchronously by
writing SPI registers to advance the current state to the next
state. SPI control is considered asynchronous to the DATA_CLK
because the SPI_CLK can be derived from a different clock
reference and can still function properly. The SPI control ENSM
method is recommended when real-time control of the
synthesizers is not necessary. SPI control can be used for real-
time control as long as the BBP has the ability to perform timed
SPI writes accurately.
Bus transfers are controlled using simple hardware handshake
signaling. The two ports can be operated in either bidirectional
(half-duplex) mode or in full duplex mode where half the bits
are used for transmitting data and half are used for receiving data.
The interface can also be configured to use only one of the data
ports for applications that do not require high data rates and
prefer to use fewer interface pins.
Pin Control Mode
DATA_CLK Signal
In pin control mode, the enable function of the ENABLE pin and
the TXNRX pin allow real-time control of the current state. The
ENSM allows TDD or FDD operation depending on the
configuration of the corresponding SPI register. The ENABLE
and TXNRX pin control method is recommended if the BBP
has extra control outputs that can be controlled in real time,
allowing a simple 2-wire interface to control the state of the
device. To advance the current state of the ENSM to the next
state, the enable function of the ENABLE pin can be driven by
either a pulse (edge detected internally) or a level.
The AD9364 supplies the DATA_CLK signal that the BBP uses
when receiving the data. The DATA_CLK signal can be set to a
rate that provides single data rate (SDR) timing where data is
sampled on each rising clock edge, or it can be set to provide
double data rate (DDR) timing where data is captured on both
rising and falling edges. SDR or DDR timing applies to
operation using either a single port or both ports.
FB_CLK Signal
For transmit data, the interface uses the FB_CLK signal as the
timing reference. FB_CLK allows source synchronous timing
with rising edge capture for burst control signals and either
rising edge (SDR mode) or both edge capture (DDR mode) for
transmit signal bursts. The FB_CLK signal must have the same
frequency and duty cycle as DATA_CLK.
When a pulse is used, it must have a minimum pulse width of
one FB_CLK cycle. In level mode, the ENABLE and TXNRX
pins are also edge detected by the AD9364 and must meet the
same minimum pulse width requirement of one FB_CLK cycle.
In FDD mode, the ENABLE and TXNRX pins can be remapped to
serve as real-time Rx and Tx data transfer control signals. In this
mode, the enable function of the ENABLE pin assumes the RXON
Rev. B | Page 29 of 32
AD9364
Data Sheet
function (controlling when the Rx path is enabled and disabled),
and the TXNRX pin assumes the TXON function (controlling
when the Tx path is enabled and disabled). In this mode, the
ENSM is removed from the system for control of all data flow
by these pins.
Control Inputs (CTRL_IN3 to CTRL_IN0)
The AD9364 provides four edge detected control input pins. In
manual gain mode, the BBP can use these pins to change the gain
table index in real time. In transmit mode, the BBP can use two
of the pins to change the transmit gain in real time.
SPI INTERFACE
GPO PINS (GPO_3 TO GPO_0)
The AD9364 uses a serial peripheral interface (SPI) to communi-
cate with the BBP. The SPI can be configured as a 4-wire
interface with dedicated receive and transmit ports, or it can
be configured as a 3-wire interface with a bidirectional data
communication port. This bus allows the BBP to set all device
control parameters using a simple address data serial bus
protocol.
The AD9364 provides four, 3.3 V capable general-purpose logic
output pins: GPO_3, GPO_2, GPO_1, and GPO_0. These pins
can be used to control other peripheral devices such as regulators
and switches via the AD9364 SPI bus, or they can function as
slaves for the internal AD9364 state machine.
AUXILIARY CONVERTERS
AUXADC
Write commands follow a 24-bit format. The first six bits are
used to set the bus direction and number of bytes to transfer.
The next 10 bits set the address where data is to be written.
The final eight bits are the data to be transferred to the specified
register address (MSB to LSB). The AD9364 also supports an
LSB-first format that allows the commands to be written in LSB
to MSB format. In this mode, the register addresses are incre-
mented for multibyte writes.
The AD9364 contains an auxiliary ADC that can be used to mon-
itor system functions such as temperature or power output. The
converter is 12 bits wide and has an input range of 0.05 V to
VDDA1P3_BB − 0.05 V. When enabled, the ADC is free running.
SPI reads provide the last value latched at the ADC output. A
multiplexer in front of the ADC allows the user to select between
the AUXADC input pin and a built-in temperature sensor.
AUXDAC1 and AUXDAC2
Read commands follow a similar format with the exception that
the first 16 bits are transferred on the SPI_DI pin and the final
eight bits are read from the AD9364, either on the SPI_DO pin
in 4-wire mode or on the SPI_DI pin in 3-wire mode.
The AD9364 contains two identical auxiliary DACs that can
provide power amplifier (PA) bias or other system functionality.
The auxiliary DACs are 10 bits wide, have an output voltage range
of 0.5 V to VDD_GPO − 0.3 V, a current drive of 10 mA, and
can be directly controlled by the internal enable state machine.
CONTROL PINS
Control Outputs (CTRL_OUT7 to CTRL_OUT0)
The AD9364 provides eight simultaneous real-time output signals
for use as interrupts to the BBP. These outputs can be configured to
output a number of internal settings and measurements that the
BBP can use when monitoring transceiver performance in different
situations. The control output pointer register selects what
information is output to these pins, and the control output enable
register determines which signals are activated for monitoring by
the BBP. Signals used for manual gain mode, calibration flags,
state machine states, and the ADC output are among the outputs
that can be monitored on these pins.
Rev. B | Page 30 of 32
Data Sheet
AD9364
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
10.10
A1 BALL
CORNER
10.00 SQ
9.90
A1 BALL
CORNER
12 11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
8.80 SQ
G
H
J
0.80
K
L
M
0.60
REF
TOP VIEW
DETAIL A
BOTTOM VIEW
1.70 MAX
1.00 MIN
DETAIL A
0.32 MIN
0.50
0.45
0.40
COPLANARITY
0.12
SEATING
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1.
Figure 74. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-144-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
144-Ball CSP_BGA
144-Ball CSP_BGA
Package Option
BC-144-7
BC-144-7
AD9364BBCZ
AD9364BBCZREEL
−40°C to +85°C
−40°C to +85°C
1 Z = RoHS Compliant Part.
Rev. B | Page 31 of 32
AD9364
NOTES
Data Sheet
©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11846-0-2/14(B)
Rev. B | Page 32 of 32
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