AD9375BBCZ-REEL [ADI]
Integrated, Dual RF Transceiver with Observation Path;
| 型号： | AD9375BBCZ-REEL |
| 厂家： | 
ADI |
| 描述： | Integrated, Dual RF Transceiver with Observation Path |
| 文件： | 总61页 (文件大小：852K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated, Dual RF Transceiver
with Observation Path
AD9375
Data Sheet
The transceiver consists of wideband direct conversion signal
paths with state-of-the-art noise figure and linearity. Each complete
Rx and Tx subsystem includes dc offset correction, quadrature error
correction (QEC), and programmable digital filters, eliminating
the need for these functions in the digital baseband. Several
auxiliary functions such as an auxiliary analog-to-digital converter
(ADC), auxiliary digital-to-analog converters (DACs), and general-
purpose input/outputs (GPIOs) are integrated to provide additional
monitoring and control capability.
FEATURES
Dual differential Tx
Dual differential Rx
Observation receiver with 2 inputs
Fully integrated, ultralow power DPD actuator and adaptation
engine for PA linearization
Sniffer receiver with 3 inputs
Tunable range: 300 MHz to 6000 MHz
Linearization signal BW to 40 MHz
Tx synthesis BW to 250 MHz
An ORx channel with two inputs is included to monitor each Tx
output and implement calibration applications. This channel also
connects to three sniffer receiver (SnRx) inputs that can monitor
radio activity in different bands.
Rx BW: 8 MHz to 100 MHz
Supports FDD and TDD operation
Fully integrated independent fractional-N RF synthesizers for
Tx, Rx, ORx, and clock generation
JESD204B digital interface
The high speed JESD204B interface supports lane rates up to
6144 Mbps. Four lanes are dedicated to the transmitters and four
lanes are dedicated to the receiver and observation receiver channels.
APPLICATIONS
3G/4G small cell base transceiver station (BTS)
3G/4G massive MIMO/active antenna systems
The fully integrated phase-locked loops (PLLs) provide high
performance, low power, fractional-N frequency synthesis for
the Tx, the Rx, the ORx, and the clock sections. Careful design
and layout techniques provide the isolation demanded in high
performance base station applications. All voltage controlled
oscillator (VCO) and loop filter components are integrated to
minimize the external component count.
GENERAL DESCRIPTION
The AD9375 is a highly integrated, wideband radio frequency (RF)
transceiver offering dual-channel transmitters (Tx) and receivers
(Rx), integrated synthesizers, a fully integrated digital predistortion
(DPD) actuator and adaptation engine, and digital signal processing
functions. The IC delivers a versatile combination of high
performance and low power consumption required by 3G/4G
small cell and massive multiple input, multiple output (MIMO)
equipment in both frequency division duplex (FDD) and time
division duplex (TDD) applications. The AD9375 operates from
300 MHz to 6000 MHz, covering most of the licensed and unlicensed
cellular bands. The DPD algorithm supports linearization on
signal bandwidths up to 40 MHz depending on the power amplifier
(PA) characteristics (for example, two adjacent 20 MHz carriers).
The IC supports Rx bandwidths up to 100 MHz. It also supports
observation receiver (ORx) and Tx synthesis bandwidths up to
250 MHz to accommodate digital correction algorithms.
The device contains a fully integrated, low power DPD actuator
and adaptation engine for use in PA linearization. The DPD feature
enables use of high efficiency PAs, significantly reducing the power
consumption of small cell base station radios while also reducing
the number of JESD204B lanes necessary to interface with baseband
processors.
A 1.3 V supply is required to power the AD9375 core, and a
standard 4-wire serial port controls it. Other voltage supplies
provide proper digital interface levels and optimize transmitter
and auxiliary converter performance. The
AD9375 is packaged in a
12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2017 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9375
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 56
Transmitter (Tx)......................................................................... 56
Receiver (Rx)............................................................................... 56
Observation Receiver (ORx)..................................................... 56
Sniffer Receiver (SnRx) ............................................................. 56
Clock Input.................................................................................. 56
Synthesizers................................................................................. 57
Serial Peripheral Interface (SPI)............................................... 57
GPIO_x AND GPIO_3P3_x Pins ............................................ 57
Auxiliary Converters.................................................................. 57
JESD204B Data Interface .......................................................... 58
Power Supply Sequence ............................................................. 58
Digital Predistortion (DPD) ..................................................... 59
JTAG Boundary Scan................................................................. 60
Outline Dimensions ....................................................................... 61
Ordering Guide .......................................................................... 61
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Current and Power Consumption Specifications................... 10
Timing Specifications ................................................................ 12
Absolute Maximum Ratings.......................................................... 14
Reflow Profile.............................................................................. 14
Thermal Resistance .................................................................... 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions........................... 15
Typical Performance Characteristics ........................................... 18
700 MHz Band............................................................................ 18
2.6 GHz Band.............................................................................. 28
3.5 GHz Band.............................................................................. 38
5.5 GHz Band.............................................................................. 48
REVISION HISTORY
3/2017—Revision 0: Initial Version
Rev. 0 | Page 2 of 61
Data Sheet
AD9375
FUNCTIONAL BLOCK DIAGRAM
AD9375
RX1+
Rx1
DECIMATION,
pFIR, AGC,
DC OFFSET
QEC,
RX1–
RX2+
LPF
LPF
Rx2
ADC
ADC
JESD204B
TUNING,
RX2–
RSSI,
OVERLOAD
MICRO-
CONTROLLER
RX_EXTLO+
RX_EXTLO–
LO
GENERATOR
RF
SYNTHESIZER
CONTROL
INTERFACE
EXTERNAL
OPTION
CTRL INT
SPI
TX1+
TX1–
TX2+
Tx1
Tx2
SPI
PORT
LPF
DAC
DAC
pFIR,
DC OFFSET,
QEC, TUNNING,
INTER-
TX2–
LPF
JESD204B
POLATION
TX_EXTLO+
TX_EXTLO–
LO
GENERATOR
RF
GPIO
AUXADC
AUXDAC
SYNTHESIZER
EXTERNAL
OPTION
LO
GENERATOR
RF
SYNTHESIZER
CLOCK
GENERATOR
DEV_CLK_IN+,
DEV_CLK_IN–
OBSERVATION
Rx
ORX1+
ORX1–
ORX2+
ORX2–
SNIFFER
Rx
SNRXA+
SNRXA–
SNRXB+
SNRXB–
SNRXC+
SNRXC–
DECIMATION,
pFIR,
LPF
LPF
ADC
ADC
AGC,
DC OFFSET,
QEC,
JESD204B
TUNING,
RSSI,
OVERLOAD
Figure 1.
Rev. 0 | Page 3 of 61
AD9375
Data Sheet
SPECIFICATIONS
Electrical characteristics at ambient temperature range, VDDA_SER = 1.3 V, V DDA _DES = 1.3 V, JESD_VTT_DES = 1.3 V, VDDA_1P31 =
1.3 V, VDIG = 1.3 V, VDDA_1P8 = 1.8 V, VDD_IF = 2.5 V, and VDDA_3P3 = 3.3 V; all RF specifications based on measurements that
include printed circuit board (PCB) and matching circuit losses, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
TRANSMITTERS (Tx)
Center Frequency
Tx Large Signal Bandwidth (BW)
Normal Operation
DPD Activated
300
6000
MHz
100
40
250
MHz
MHz
MHz
Tx Synthesis BW2
Wider bandwidth for use in
digital processing algorithms
BW Flatness
0.5
dB
dB
250 MHz BW, compensated
by programmable finite
impulse response (pFIR) filter
0.15
Any 20 MHz BW span,
compensated by pFIR filter
Deviation from Linear Phase
Power Control Range
10
Degrees
dB
250 MHz BW
0
42
Increased calibration time,
reduced QEC3, LOL4
performance beyond 20 dB
Power Control Resolution
0.05
dB
ACLR5 (Four Universal Mobile
Telecommunications System
(UMTS) Carriers)
−11.2 dBFS rms,
0 dB RF attenuation
700 MHz Local Oscillator (LO)
2600 MHz LO
3500 MHz LO
5500 MHz LO
In Band Noise
−64
−64
−63
−61
−155
dB
dB
dB
dB
dBFS6/Hz
Tx to Tx Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
70
65
65
50
dB
dB
dB
dB
Image Rejection
Up to 20 dB RF attenuation,
within large signal BW,
QEC3 active
700 MHz LO
2600 MHz LO
3500 MHz LO
65
65
65
50
dB
dB
dB
dB
5500 MHz LO
Maximum Output Power
0 dBFS, 1 MHz signal input,
50 Ω load, 0 dB RF attenuation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
7
7
6
4
dBm
dBm
dBm
dBm
Output Third-Order Intercept Point OIP3
−5 dBFS rms,
0 dB RF attenuation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
27
27
25
25
dBm
dBm
dBm
dBm
Rev. 0 | Page 4 of 61
Data Sheet
AD9375
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Carrier Leakage
After calibration,
LOL correction active,
CW7 input signal, 3 dB RF
and 3 dB digital attenuation,
40 kHz measurement BW
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
−81
−81
−81
−75
dBFS6
dBFS6
dBFS6
dBFS6
Error Vector Magnitude (3GPP
Test Signals)
EVM
Long-term evolution (LTE)
20 MHz downlink,
5 dB RF attenuation
700 MHz LO
2600 MHz LO
3500 MHz LO
−45
−39
−38.5
−37.5
50
dB
dB
dB
dB
Ω
5500 MHz LO
Output Impedance
RECEIVERS (Rx)
Center Frequency
Gain Range
Differential
300
0
6000
30
MHz
dB
Analog Gain Step
BW Ripple
0.5
0.5
dB
dB
100 MHz BW, compensated
by programmable FIR filter
0.2
dB
Any 20 MHz span,
compensated by
programmable FIR filter
Rx Bandwidth
8
100
MHz
Analog low-pass filter (LPF)
BW is 20 MHz minimum,
programmable FIR BW
configurable over the entire
range
Rx Alias Band Rejection
Maximum Recommended Input
Power8
75
dB
dBm
Due to digital filters
−14
Input is a CW7 signal at a 0 dB
attenuation setting; this level
increases decibel for decibel
with attenuation
Noise Figure
NF
Maximum Rx gain, at Rx port,
matching losses de-embedded
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
12
13.5
14
dB
dB
dB
dB
18
Input Third-Order Intercept Point IIP3
Maximum Rx gain, third-
order intermodulation (IM3)
1 MHz offset from LO
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
22
22
20
20
dBm
dBm
dBm
dBm
Input Second-Order Intercept
Point
IIP2
Maximum Rx gain, second-
order intermodulation (IM2)
1 MHz offset from LO
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
65
65
65
57
dBm
dBm
dBm
dBm
Rev. 0 | Page 5 of 61
AD9375
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Image Rejection
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Input Impedance
QEC3 active, within Rx BW
75
75
75
75
200
dB
dB
dB
dB
Ω
Differential
Tx1 to Rx1 Signal Isolation and
Tx2 to Rx2 Signal Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
68
68
62
60
dB
dB
dB
dB
Tx1 to Rx2 Signal Isolation and
Tx2 to Rx1 Signal Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
70
70
62
60
dB
dB
dB
dB
5500 MHz LO
Rx1 to Rx2 Signal Isolation
700 MHz LO
60
dB
2600 MHz LO
60
dB
3500 MHz LO
60
dB
5500 MHz LO
60
dB
Rx Band Spurs Referenced to
RF Input at Maximum Gain
−95
dBm
No more than one spur at
this level per 10 MHz of Rx
BW; excludes harmonics of
the reference clock
Rx LO Leakage at Rx Input at
Maximum Gain
Leakage decreases decibel
for decibel with attenuation
for first 12 dB
700 MHz LO
2600 MHz LO
3500 MHz LO
−65
−65
−62
−62
dBm
dBm
dBm
dBm
5500 MHz LO
OBSERVATION RECEIVER (ORx)
Center Frequency
Gain Range
300
0
6000
18
MHz
dB
Analog Gain Step
BW Ripple
1
dB
dB
0.5
250 MHz RF BW, compensated
by programmable FIR filter
Deviation from Linear Phase
ORx Bandwidth
10
Degrees
MHz
250 MHz RF BW
250
ORx Alias Band Rejection
Maximum Recommended Input
Power8
60
dB
dBm
Due to digital filters
−13
Input is a CW7 signal at 0 dB
attenuation setting; this level
increases decibel for decibel
with attenuation
Signal-to-Noise Ratio9
700 MHz LO
2600 MHz LO
3500 MHz LO
SNR
Maximum gain at ORx port
60
60
60
59
dB
dB
dB
dB
5500 MHz LO
200 MHz BW, 245.76 MSPS
Rev. 0 | Page 6 of 61
Data Sheet
AD9375
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Input Third-Order Intercept Point IIP3
Maximum ORx gain,
IM3 1 MHz offset from LO
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
22
22
18
18
dBm
dBm
dBm
dBm
Input Second-Order Intercept
Point
IIP2
Maximum ORx gain,
IM2 1 MHz offset from LO
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Image Rejection
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
Input Impedance
65
65
65
60
dBm
dBm
dBm
dBm
After online tone calibration
65
65
65
65
200
dB
dB
dB
dB
Ω
Differential
Tx1 to ORx1 Signal and Tx2 to
ORx2 Signal Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
5500 MHz LO
70
70
70
70
dB
dB
dB
dB
Tx1 to ORx2 Signal and Tx2 to
ORx1 Signal Isolation
700 MHz LO
2600 MHz LO
3500 MHz LO
70
70
70
70
dB
dB
dB
dB
5500 MHz LO
SNIFFER RECEIVER (SnRx)
Center Frequency
Gain Range
300
0
6000
52
MHz
dB
Analog Gain Step
BW Ripple
1
dB
dB
0.5
20 MHz RF BW, compensated
by programmable FIR filter
Rx Bandwidth
Rx Alias Band Rejection
20
MHz
dB
60
Due to digital filters
Maximum Recommended Input
Power8
−26
dBm
Input is a CW7 signal at 0 dB
attenuation setting
Noise Figure
NF
Maximum gain at SnRx port,
matching losses de-embedded
700 MHz LO
2600 MHz LO
3500 MHz LO
5
5
7
dB
dB
dB
Input Third-Order Intercept Point IIP3
Maximum gain, IM3 1 MHz
offset from LO, gain control
limited to the first 20 steps
700 MHz LO
2600 MHz LO
3500 MHz LO
1
1
1
dBm
dBm
dBm
Rev. 0 | Page 7 of 61
AD9375
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Input Second-Order Intercept
Point
IIP2
Maximum gain, IM2 1 MHz
offset from LO, gain control
limited to the first 20 steps
700 MHz LO
2600 MHz LO
3500 MHz LO
Image Rejection
700 MHz LO
2600 MHz LO
3500 MHz LO
Input Impedance
45
45
45
dBm
dBm
dBm
After online tone calibration
75
75
75
400
dB
dB
dB
Ω
Differential
Tx1 to SnRx Signal and Tx2 to
SnRx Signal Isolation
Applies to each SnRx input
700 MHz LO
2600 MHz LO
3500 MHz LO
60
60
60
dB
dB
dB
LO SYNTHESIZER
LO Frequency Step
2.3
Hz
1.5 GHz to 3 GHz, 76.8 MHz
phase frequency detector
(PFD) frequency
LO Spur
−80
dBc
Excludes integer boundary
spurs 1 kHz to 100 MHz
Spot Phase Noise
700 MHz LO
10 kHz
−104
−107
−133
dBc
dBc
dBc
100 kHz
1 MHz
2600 MHz LO
10 kHz
100 kHz
−93
−97
−123
dBc
dBc
dBc
1 MHz
3500 MHz LO
10 kHz
100 kHz
−91
−97
−123
dBc
dBc
dBc
1 MHz
5500 MHz LO
10 kHz
100 kHz
−98
−100
−110
dBc
dBc
dBc
1 MHz
Integrated Phase Noise
Integrated from 1 kHz to
100 MHz
700 MHz LO
2600 MHz LO
3500 MHz LO
0.20
0.49
0.55
0.75
°rms
°rms
°rms
°rms
5500 MHz LO
EXTERNAL LO INPUT
Input Frequency
fEXTLO
600
0
8000
6
MHz
dBm
Input frequency must be 2×
the desired LO frequency
50 Ω matching at the source
Input Signal Power
3
Rev. 0 | Page 8 of 61
Data Sheet
AD9375
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE CLOCK (DEV_CLK_IN
SIGNAL)
Frequency Range
Signal Level
10
0.3
320
2.0
MHz
V p-p
AC-coupled, common-mode
voltage (VCM) = 618 mV; for
best spurious performance,
use a <1 V p-p input clock
AUXILIARY CONVERTERS
ADC
ADC Resolution
Input Voltage
Minimum
12
Bits
0.25
3.05
V
V
Maximum
DAC
DAC Resolution
Output Voltage
Minimum
Maximum
Drive Capability
10
Bits
Includes four offset levels
0.5
3.0
10
V
V
mA
Reference voltage (VREF) = 1 V
VREF = 2.5 V
DIGITAL SPECIFICATIONS (CMOS),
GPIO_x, RX1_ENABLE,
RX2_ENABLE, TX1_ENABLE,
TX2 ENABLE, SYNCINBx+,
SYNCOUTB0+, GP_INTERRUPT,
SDIO, SDO, SCLK, CSB, RESET
Logic Inputs
Input Voltage
High Level
VDD_IF ×
0.8
0
VDD_IF
V
V
Low Level
VDD_IF ×
0.2
Input Current
High Level
Low Level
−10
−10
+10
+10
µA
µA
Logic Outputs
Output Voltage
High Level
VDD_IF ×
0.8
V
Low Level
VDD_IF ×
0.2
V
Drive Capability
3
mA
DIGITAL SPECIFICATIONS (LVDS),
SYSREF_INx , SYNCOUTB0 ,
SYNCINBx PAIRS
Logic Inputs
Input Voltage Range
Input Differential Voltage
Threshold
Receiver Differential Input
Impedance
825
−100
1675
+100
mV
mV
Each differential input in the pair
Internal termination enabled
100
Ω
Logic Outputs
Output Voltage
High
1375
mV
mV
mV
mV
Low
Differential
Offset
1025
225
1200
Rev. 0 | Page 9 of 61
AD9375
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL SPECIFICATIONS (CMOS),
GPIO_3P3_x SIGNALS
Logic Inputs
Input Voltage
High Level
VDDA_
3P3 × 0.8
0
VDDA_3P3
V
V
Low Level
VDDA_
3P3 × 0.2
Input Current
High Level
Low Level
−10
−10
+10
+10
µA
µA
Logic Outputs
Output Voltage
High Level
VDDA_
V
3P3 × 0.8
Low Level
VDDA_
V
3P3 × 0.2
Drive Capability
4
mA
1 VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO,
VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
2 Synthesis BW) is the extended bandwidth used by digital correction algorithms to measure conditions and generate compensation.
3 Quadrature error correction (QEC) is the system for minimizing quadrature images of a desired signal.
4 Local oscillator leakage (LOL) is a measure of the amount of the LO signal that is passed from a mixer with the desired signal.
5 Adjacent channel level reduction (ACLR) is a measure of the amount of power from the desired signal leaking into an adjacent channel.
6 dBFS represents the ratio of the actual output signal to the maximum possible output level for a continuous wave output signal at the given RF attenuation setting.
7 Continuous wave (CW) is a single frequency signal.
8 Note that the input signal power limit does not correspond to 0 dBFS at the digital output because of the nature of the continuous time Σ-Δ ADCs. Unlike the hard
clipping characteristic of pipeline ADCs, these converters exhibit a soft overload behavior when the input approaches the maximum level.
9 Signal-to-noise ratio is limited by the baseband quantization noise.
CURRENT AND POWER CONSUMPTION SPECIFICATIONS
Table 2.
Parameter
Min
Typ
Max
Unit Test Conditions / Comments
SUPPLY CHARACTERISTICS
VDDA_1P3 Analog Supplies1
VDIG Supply
VDDA_1P8 Supply
VDD_IF Supply
VDDA_3P3 Supply
VDDA_SER, VDDA_DES,
JESD_VTT_DES Supplies
1.267 1.3
1.267 1.3
1.33
1.33
1.89
2.625
3.465
1.365
V
V
V
V
V
V
1.71
1.71
1.8
1.8
CMOS and LVDS supply, 1.8 V to 2.5 V nominal range
3.135 3.3
1.14
1.3
POSITIVE SUPPLY CURRENT (Rx MODE)
Two Rx channels enabled, Tx upconverter disabled, 100 MHz
Rx BW, 122.88 MSPS data rate
VDDA_1P3 Analog Supplies1
VDIG Supply
VDD_IF Supply (CMOS and LVDS)
VDDA_3P3 Supply
1055
625
8
mA
mA
mA
mA
Rx QEC2 enabled, QEC2 engine active
1
No auxiliary DACs or auxiliary ADCs enabled; if enabled, the
auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA
VDDA_SER, VDDA_DES,
JESD_VTT_DES Supplies
Total Power Dissipation
375
mA
W
2.70
Rev. 0 | Page 10 of 61
Data Sheet
AD9375
Parameter
Min
Typ
Max
Unit Test Conditions / Comments
POSITIVE SUPPLY CURRENT (Tx MODE)
Two Tx channels enabled, Rx downconverter disabled, 200 MHz
Tx BW, 245.76 MSPS data rate (ORx disabled)
VDDA_1P3 Analog Supplies1
VDIG Supply
1000
410
mA
mA
Tx QEC2 active
Full-scale CW3
VDDA_1P8 Supply
405
80
8
mA
mA
mA
mA
Tx RF attenuation = 0 dB,
Tx RF attenuation = 15 dB
VDD_IF Supply
VDDA_3P3 Supply
1
No auxiliary DACs or auxiliary ADCs enabled; if enabled, the
auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA
VDDA_SER, VDDA_DES,
JESD_VTT_DES Supplies
Total Power Dissipation
375
mA
Typical supply voltages, Tx QEC2 active
Tx RF attenuation = 0 dB
3.70
3.11
W
W
Tx RF attenuation = 15 dB
POSITIVE SUPPLY CURRENT (FDD
MODE), 2× Rx, 2× Tx, ORx ACTIVE
100 MHz Rx BW, 122.88 MSPS data rate; 200 MHz Tx BW,
245.76 MSPS data rate; 200 MHz ORx BW, 245.76 MSPS data rate
VDDA_1P3 Analog Supplies1
VDIG Supply
1700
1080
mA
mA
Tx QEC2 active
Full scale CW3
VDDA_1P8 Supply
405
80
8
mA
mA
mA
mA
Tx RF attenuation = 0 dB
Tx RF attenuation = 15 dB
VDD_IF Supply
VDDA_3P3 Supply
2
No auxiliary DACs or auxiliary ADCs enabled; if enabled, the
auxiliary ADC adds 2.7 mA, and each auxiliary ADC adds 1.5 mA
VDDA_SER, VDDA_DES,
JESD_VTT_DES Supplies
Total Power Dissipation
375
mA
Typical supply voltages, Tx QEC2 active
Tx RF attenuation = 0 dB
4.86
4.27
W
W
°C
Tx RF attenuation = 15 dB
MAXIMUM OPERATING JUNCTION
TEMPERATURE
110
Device designed for 10-year lifetime when operating at
maximum junction temperature
1 VDDA_1P3 refers to all analog 1.3 V supplies including the following: VDDA_BB, VDDA_CLKSYNTH, VDDA_TXLO, VDDA_RXRF, VDDA_RXSYNTH, VDDA_RXVCO,
VDDA_RXTX, VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH, VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
2 QEC is the system for minimizing quadrature images of a desired signal.
3 CW is a single frequency signal.
Rev. 0 | Page 11 of 61
AD9375
Data Sheet
TIMING SPECIFICATIONS
Table 3.
Parameter
Symbol Min
Typ Max
Unit
Test Conditions/Comments
SERIAL PERIPHERAL INTERFACE (SPI) TIMING
SCLK Period
SCLK Pulse Width
CSB Setup to First SCLK Rising Edge
Last SCLK Falling Edge to CSB Hold
SDIO Data Input Setup to SCLK
SDIO Data Input Hold to SCLK
SCLK Falling Edge to Output Data Delay (3- or 4-Wire Mode)
tCP
tMP
tSC
tHC
tS
tH
tCO
tHZM
20
10
3
0
2
0
3
tH
ns
ns
ns
ns
ns
ns
ns
ns
8
tCO
Bus Turnaround Time After Baseband Processor (BBP) Drives
Last Address Bit
Bus Turnaround Time After AD9375 Drives Last Address Bit
DIGITAL TIMING
tHZS
0
tCO
ns
TXx_ENABLE Pulse Width
RXx_ENABLE Pulse Width
JESD204B DATA OUTPUT TIMING
Unit Interval
Data Rate per Channel (Nonreturn to Zero (NRZ))
Rise Time
10
10
µs
µs
UI
162.76
614.4
24
1627.6 ps
6144
Mbps
ps
ps
tR
tF
35
35
20% to 80% in 100 Ω load
20% to 80% in 100 Ω load
AC-coupled
Fall Time
24
Output Common-Mode Voltage
Termination Voltage (VTT) = 1.2 V
Differential Output Voltage
Short-Circuit Current
Differential Termination Impedance
Total Jitter
Uncorrelated Bounded High Probability Jitter
Duty Cycle Distortion
SYSREF_IN Signal Setup Time to DEV_CLK_IN Signal
SYSREF_IN Signal Hold Time to DEV_CLK_IN Signal
JESD204B DATA INPUT TIMING
Unit Interval
Data Rate per Channel (NRZ)
Input Common-Mode Voltage
VTT = 1.2 V
Differential Input Voltage
VTT Source Impedance
VCM
0
1.8
1135
466 770
+100
100 120
V
735
360
−100
80
mV
mV
mA
Ω
ps
ps
ps
ns
ns
DC-coupled
VDIFF
IDSHORT
ZRDIFF
17
1.2
3
48.8
24.4
8.1
Bit error rate (BER) = 10−15
UBHPJ
DCD
tS
2.5
−1.5
See Figure 2 and Figure 3
See Figure 2 and Figure 3
tH
UI
162.76
614.4
0.05
720
125
1627.6 ps
6144
1.85
1200
750
30
Mbps
V
mV
mV
Ω
VCM
AC-coupled
DC-coupled
VDIFF
ZTT
1.2
Differential Termination Impedance
VTT
ZRDIFF
80
106 120
Ω
AC-Coupled
DC-Coupled
1.27
1.14
1.33
1.26
V
V
Rev. 0 | Page 12 of 61
Data Sheet
AD9375
Timing Diagrams
DEV_CLK_IN DELAY
IN REFERENCE TO SYSREF
AT DEVICE PINS
tS
AT DIGITAL CORE
t'H
tS
t'H
t'S
tH
tH
DEV_CLK_IN
tH = –1.5ns
tS = +2.5ns
t'H = +0.5ns
t'S = +0.5ns
CLK DELAY = 2ns
Figure 2. SYSREF_IN Signal Setup and Hold Timing
tS
tS
tS
tS
tH
tH
tH
tH
DEV_CLK_IN
SYSREF_IN
tH = –1.5ns
tS = +2.5ns
VALID SYSREF_IN
INVALID SYSREF_IN
Figure 3. SYSREF_IN Signal Setup and Hold Timing Examples Relative to DEV_CLK_IN Signal
Rev. 0 | Page 13 of 61
AD9375
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
REFLOW PROFILE
The AD9375 reflow profile is in accordance with the JEDEC
JESD20 criteria for Pb-free devices. The maximum reflow
temperature is 260°C.
Parameter
Rating
VDDA_1P31 to VSSA
−0.3 V to +1.4 V
−0.3 V to +1.4 V
VDDA_SER, VDDA_DES, and
JESD_VTT_DES to VSSA
VDIG to VSSD
VDDA_1P8 to VSSA
VDD_IF to VSSA
THERMAL RESISTANCE
−0.3 V to +1.4 V
−0.3 V to +2.0 V
−0.3 V to +3.0 V
−0.3 V to +3.9 V
−0.3 V to VDD_IF + 0.3 V
−0.3 V to VDDA_SER
−0.3 V to VDDA_DES
10 mA
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
VDDA_3P3 to VSSA
θJA is the natural convection junction-to-ambient thermal resistance
measured in a one cubic foot sealed enclosure. θJC is the junction-
to-case thermal resistance.
Logic Inputs and Outputs to VSSD
JESD204B Logic Outputs to VSSA
JESD204B Logic Inputs to VSSA
Input Current to Any Pin Except
Supplies
Maximum Input Power into RF Ports
(Excluding Sniffer Receiver Inputs)
Maximum Input Power into SNRXA ,
SNRXB , and SNRXC
Table 5. Thermal Resistance
Airflow
23 dBm (peak)
2 dBm (peak)
Package
BC-196-12
JEDEC5
Velocity1 (m/sec) θJA2, 3 (°C/W) θJC2, 4 (°C/W)
0.0
1.0
2.5
20.5
18.5
17.2
14.1
12.4
11.6
0.05
N/A6
N/A6
0.05
N/A6
N/A6
Maximum Junction Temperature (TJ MAX
Operating Temperature Range
Storage Temperature Range
)
110°C
−40°C to +85°C
−65°C to +150°C
10-Layer PCB 0.0
1.0
2.5
1 VDDA_1P3 refers to all analog 1.3 V supplies: VDDA_BB, VDDA_CLKSYNTH,
VDDA_TXLO, VDDA_RXSYNTH, VDDA_RXVCO, VDDA_RXTX, VDDA_RXRF,
VDDA_TXSYNTH, VDDA_TXVCO, VDDA_CALPLL, VDDA_SNRXSYNTH,
VDDA_SNRXVCO, VDDA_CLK, and VDDA_RXLO.
1 Power dissipation is 3.0 W for all test cases.
2 Per JEDEC JESD51-7 for JEDEC JESD51-5 2S2P test board.
3 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
4 Per MIL-STD 883, Method 1012.1.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
5 JEDEC entries refer to the JEDEC JESD51-9 (high-K thermal test board).
6 N/A means not applicable.
ESD CAUTION
Rev. 0 | Page 14 of 61
Data Sheet
AD9375
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9375
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VSSA
ORX2+
ORX2–
VSSA
RX2+
RX2–
VSSA
VSSA
RX1+
RX1–
VSSA
ORX1+
ORX1–
VSSA
A
B
C
D
E
F
VDDA_RXRF
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VDDA_RXLO
VSSA
RX_EXTLO– RX_EXTLO+
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VDDA_3P3
RBIAS
VSNRX_
VCO_LDO
VDDA_
SNRXVCO
VDDA_
RXVCO
VRX_
VCO_LDO
GPIO_3P3_0 GPIO_3P3_1
AUXADC_1
AUXADC_3
AUXADC_2
GPIO_3P3_9
GPIO_3P3_3
GPIO_3P3_4
SNRXC–
SNRXC+
SNRXB–
SNRXB+
VSSA
SNRXA–
SNRXA+
VSSA
GPIO_3P3_5
VDDA_BB
VSSA
VSSA
VSSA
VDDA_1P8
VSSA
GPIO_3P3_7 GPIO_3P3_8 GPIO_3P3_10
DEV_
CLK_IN+
DEV_
CLK_IN–
VSSA
TX_EXTLO– TX_EXTLO+
VDDA_
AUXADC_0
GPIO_3P3_6
GPIO_3P3_11
VSSA
VTX_
VCO_LDO
GPIO_3P3_2 VDDA_RXTX
VSSA
VSSA
VSSA
VSSA
VDDA_TXLO
TXVCO
VDDA_
CALPLL
VDDA_
CLKSYNTH
VDDA_
SNRXSYNTH
VDDA_
TXSYNTH
VDDA_
RXSYNTH
VSSA
TX2–
TX2+
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
GPIO_11
GPIO_10
GPIO_9
VSSA
VSSA
VSSA
VSSA
VSSA
G
H
J
VSSA
VSSA
VSSA
VSSA
TEST
VSSA
GPIO_2
GPIO_3
VSSD
VSSA
GPIO_1
GPIO_0
VDIG
VSSA
SDIO
VSSA
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
SERDIN2+
SERDIN0–
TX1+
GP_
INTERRUPT
GPIO_18
RESET
SDO
TX1–
SYSREF_IN+ SYSREF_IN–
GPIO_5
GPIO_6
GPIO_4
GPIO_7
SCLK
CSB
VSSA
K
L
SYNCINB1–
SYNCINB0–
SYNCINB1+
SYNCINB0+
VDIG
VSSD
GPIO_8
VSSA
VCLK_
VCO_LDO
RX1_
ENABLE
TX1_
ENABLE
RX2_
ENABLE
TX2_
ENABLE
VSSA
GPIO_17
SERDIN2–
VSSA
VDD_IF
SYNCOUTB0+ SYNCOUTB0–
M
N
P
VDDA_CLK
VSSA
SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+
VSSA
VDDA_SER
VDDA_SER
VDDA_DES
SERDIN3–
SERDIN0+
SERDIN3+
SERDIN1–
VSSA
JESD_VTT_
DES
VSSA
SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+
SERDIN1+
ANALOG
INPUT/OUTPUT
DIGITAL
INPUT/OUTPUT
DC POWER
GROUND
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Type1
Mnemonic
VSSA
Description
Analog ground.
A1, A4, A7, A8, A11, A14, B2 to B6,
B9 to B13, C5, C9, C10, D6 to D9,
E6, E9, E10, F3 to F10, G1 to G3, G5,
G10 to G14, H2 to H10, H13, J2, J13,
K1, K2, K13, K14, L1, L2, L13, L14,
I
M2, M9, N2, N7, N14, P1, P2, P3, P10
A2, A3
A5, A6
A9, A10
A12, A13
B1
I
I
I
I
I
ORX2+, ORX2−
RX2+, RX2−
Differential Input for Observation Receiver 2. Do not
connect if these pins are unused.
Differential Input for Receiver 2. Do not connect if these pins
are unused.
Differential Input for Receiver 1. Do not connect if these pins
are unused.
Differential Input for Observation Receiver 1. Do not
connect if these pins are unused.
RX1+, RX1−
ORX1+, ORX1−
VDDA_RXRF
1.3 V Supply Input.
Rev. 0 | Page 15 of 61
AD9375
Data Sheet
Pin No.
Type1
Mnemonic
Description
B7, B8
I/O
RX_EXTLO−, RX_EXTLO+
Differential Rx External LO Input/Output. If used for the
external LO, the input frequency must be 2× the desired
carrier frequency. Do not connect if these pins are unused.
B14
I
VDDA_3P3
Supply Voltage for GPIO_3P3_x.
C1, C2, C13, D1, D5, D12 to D14,
E1, E14, F1, F14
I/O
GPIO_3P3_0 to GPIO_3P3_11 General-Purpose Inputs and Outputs Referenced to 3.3 V
Supply. See Figure 4 to match the ball location to the
GPIO_3P3_x signal name. Some GPIO_3P3_x pins can also
function as auxiliary DAC outputs.
C3
C4
C6
O
I
VSNRX_VCO_LDO
VDDA_SNRXVCO
VDDA_RXLO
Sniffer VCO LDO 1.1 V Output. Bypass this pin with a 1 µF
capacitor.
1.3 V Supply Input for Sniffer VCO Low Dropout (LDO)
Regulator.
1.3 V Supply for the Rx Synthesizer LO Generator. This pin
is sensitive to aggressors.
I
C7
C8
I
O
VDDA_RXVCO
VRX_VCO_LDO
1.3 V Supply Input for Receiver VCO LDO Regulator.
Receiver VCO LDO 1.1 V Output. Bypass this pin with a 1 µF
capacitor.
C11
C12
C14
I
I
AUXADC_1
AUXADC_2
RBIAS
Auxiliary ADC 1 Input.
Auxiliary ADC 2 Input.
Bias Resistor Connection. This pin generates an internal
current based on an external 1% resistor. Connect a
14.3 kΩ resistor between this pin and ground (VSSA).
N/A
D2, E2
D3, E3
D4, E4
I
I
I
SNRXC−, SNRXC+
SNRXB−, SNRXB+
SNRXA−, SNRXA+
Differential Input for Sniffer Receiver Input C. If these pins are
unused, connect to VSSA with a short or with a 1 kΩ resistor.
Differential Input for Sniffer Receiver Input B. If these pins are
unused, connect to VSSA with a short or with a 1 kΩ resistor.
Differential Input for Sniffer Receiver Input A. If these pins are
unused, connect to VSSA with a short or with a 1 kΩ resistor.
D10
D11
E5
I
I
I
VDDA_1P8
AUXADC_3
VDDA_BB
1.8 V Tx Supply.
Auxiliary ADC 3 Input.
1.3 V Supply Input for ADCs, DACs, and Auxiliary ADCs.
E7, E8
E11, E12
I
DEV_CLK_IN+, DEV_CLK_IN− Device Clock Differential Input.
I/O
TX_EXTLO−, TX_EXTLO+
Differential Tx External LO Input/Output. If these pins are
used for the external LO, the input frequency must be 2×
the desired carrier frequency. Do not connect if these pins
are unused.
E13
F2
I
I
AUXADC_0
VDDA_RXTX
Auxiliary ADC 0 Input.
1.3 V Supply Input for Tx/Rx Baseband Circuits,
Transimpedance Amplifier (TIA), Tx Transconductance (Gm),
Baseband Filters, and Auxiliary DACs.
F11
F12
I
I
VDDA_TXVCO
VDDA_TXLO
1.3 V Supply Input for Transmitter VCO LDO Regulator.
1.3 V Supply for the Tx Synthesizer LO Generator. This pin is
sensitive to aggressors.
F13
G4
O
I
VTX_VCO_LDO
VDDA_CALPLL
VDDA_CLKSYNTH
VDDA_SNRXSYNTH
VDDA_TXSYNTH
VDDA_RXSYNTH
TX2−, TX2+
Transmitter VCO LDO 1.1 V Output. Bypass this pin with a
1 µF capacitor.
1.3 V Supply Input for Calibration PLL Circuits. Use a
separate trace on the PCB back to a common supply point.
1.3 V Clock Synthesizer Supply Input. This pin is sensitive
to aggressors.
1.3 V Sniffer Rx Synthesizer Supply Input. This pin is
sensitive to aggressors.
1.3 V Tx Synthesizer Supply Input. This pin is sensitive to
aggressors.
1.3 V Rx Synthesizer Supply Input. This pin is sensitive to
aggressors.
G6
I
G7
I
G8
I
G9
I
H1, J1
O
Differential Output for Transmitter 2.
Rev. 0 | Page 16 of 61
Data Sheet
AD9375
Pin No.
Type1
Mnemonic
Description
H11, H12, J3, J7, J8, J11, J12, K5 to K8,
K11, K12, L5, L6, L11, L12, M10, M11
I/O
GPIO_0 to GPIO_18
General-Purpose Inputs and Outputs Referenced to
VDD_IF. See Figure 4 to match the ball location to the
GPIO_x signal name.
H14, J14
O
I
TX1+, TX1−
RESET
Differential Output for Transmitter 1.
Active Low Chip Reset.
J4
J5
J6
O
I
GP_INTERRUPT
TEST
General-Purpose Interrupt Signal.
Test Pin Used for JTAG Boundary Scan. Ground this pin if
unused.
J9
I/O
SDIO
Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire
Mode.
J10
K3, K4
O
I
SDO
Serial Data Output.
LVDS System Reference Clock Inputs for the JESD204B
Interface.
SYSREF_IN+, SYSREF_IN−
K9
K10
L3, L4
I
I
I
SCLK
CSB
Serial Data Bus Clock.
Serial Data Bus Chip Select. Active low.
LVDS Sync Signal Associated with ORx/Sniffer Channel
Data on the JESD204B Interface. Alternatively, these pins
can be set to a CMOS input using SYNCINB1+ as the input
and connecting SYNCINB1− with a 1 kΩ resistor to GND.
SYNCINB1−, SYNCINB1+
L7, L10
L8, L9
I
I
VSSD
VDIG
Digital Ground.
1.3 V Digital Core Supply. Use a separate trace on the PCB
back to a common supply point.
M1
O
I
VCLK_VCO_LDO
Clock VCO LDO 1.1 V Output. Bypass this pin with a 1 µF
capacitor.
LVDS Sync Signal Associated with Rx Channel Data on the
JESD204B Interface. Alternatively, these pins can be set to
a CMOS input using SYNCINB0+ as the input and
M3, M4
SYNCINB0−, SYNCINB0+
connecting SYNCINB0− with a 1 kΩ resistor to GND.
M5
M6
M7
M8
M12
M13, M14
I
I
I
I
I
O
RX1_ENABLE
TX1_ENABLE
RX2_ENABLE
TX2_ENABLE
VDD_IF
SYNCOUTB0+, SYNCOUTB0−
Enables Rx Channel 1 Signal Path.
Enables Tx Channel 1 Signal Path.
Enables Rx Channel 2 Signal Path.
Enables Tx Channel 2 Signal Path.
CMOS/LVDS Interface Supply.
LVDS Sync Signal Associated with Transmitter Channel
Data on the JESD204B Interface. Alternatively, these pins
can be set to a CMOS output using SYNCOUTB0+ as the
output while leaving SYNCOUTB0− floating.
N1
I
VDDA_CLK
1.3 V Clock Supply Input.
N3, N4
O
SERDOUT3−, SERDOUT3+
RF Current Mode Logic (CML) Differential Output 3. This
JESD204B lane can be used by the receiver data or by the
sniffer/observation receiver data.
N5, N6
O
SERDOUT2−, SERDOUT2+
RF CML Differential Output 2. This lane can be used by the
receiver data or by the sniffer/observation receiver data.
N8, P8
N9
N10, N11
N12, N13
P4, P5
I
I
I
I
VDDA_SER
VDDA_DES
SERDIN2−, SERDIN2+
SERDIN3−, SERDIN3+
SERDOUT1−, SERDOUT1+
JESD204B 1.3 V Serializer Supply Input.
JESD204B 1.3 V Deserializer Supply Input.
RF CML Differential Input 2.
RF CML Differential Input 3.
RF CML Differential Output 1. This JESD204B lane can be used
by receiver data or by sniffer/observation receiver data.
O
P6, P7
O
SERDOUT0−, SERDOUT0+
RF CML Differential Output 0. This JESD204B lane can be used
by receiver data or by sniffer/observation receiver data.
P9
P11, P12
P13, P14
I
I
I
JESD_VTT_DES
SERDIN0−, SERDIN0+
SERDIN1−, SERDIN1+
JESD204B Deserializer Termination Supply Input.
RF CML Differential Input 0.
RF CML Differential Input 1.
1 I is input, I/O is input/output, O is output, and N/A is not applicable.
Rev. 0 | Page 17 of 61
AD9375
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Temperature settings refer to the die temperature. The die temperature is 40°C for single-trace plots.
700 MHz BAND
–30
100
90
80
70
60
50
40
30
20
10
0
–40
+110°C
+40°C
–40°C
–50
–60
–70
–80
–90
+110°C
+40°C
–40°C
–100
–110
300
400
500
600
700
800
900
1000
0
3
6
9
12
15
RECEIVER LO FREQUENCY (MHz)
f1 OFFSET FREQUENCY (MHz)
Figure 8. Receiver IIP2 vs. f1 Offset Frequency, 900 MHz LO, 0 dB Attenuation,
20 MHz RF Bandwidth, f2 = f1 + 1 MHz, 30.72 MSPS Sample Rate
Figure 5. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
100
90
80
70
60
50
45
40
+110°C
+40°C
–40°C
35
30
25
20
15
10
5
f2
f2
f2
f2
f2
f2
–
–
–
+
+
+
f1, +110°C
f1, +40°C
f1, –40°C
f1, +110°C
f1, +40°C
f1, –40°C
40
30
20
10
0
0
4
6
8
10
12
0
3
6
9
12
15
INTERMODULATION FREQUENCY (MHz)
RECEIVER ATTENUATION (dB)
Figure 9. Receiver IIP2 vs. Intermodulation Frequency, 900 MHz LO,
0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Figure 6. Receiver Noise Figure vs. Receiver Attenuation, 700 MHz LO,
20 MHz Bandwidth, 30.72 MSPS Sample Rate, 20 MHz Integration Bandwidth
(Includes 1 dB Matching Circuit Loss)
40
35
30
25
20
30
+110°C
+40°C
–40°C
25
20
15
10
5
15
+110°C
+40°C
–40°C
10
5
0
0
300
0
3
6
9
12
15
400
500
600
700
800
900
1000
RECEIVER LO FREQUENCY (MHz)
f1 OFFSET FREQUENCY (MHz)
Figure 7. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver
Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate, 20 MHz
Integration Bandwidth (Includes 1 dB Matching Circuit Loss)
Figure 10. Receiver IIP3 vs. f1 Offset Frequency, 900 MHz LO,
0 dB Attenuation, 20 MHz RF Bandwidth, f2 = 2f1 + 1 MHz,
30.72 MSPS Sample Rate
Rev. 0 | Page 18 of 61
Data Sheet
AD9375
40
35
30
25
20
15
10
5
–40
–50
+110°C
+40°C
–40°C
–60
–70
–80
f2 – 2f1, +110°C
f2 – 2f1, +40°C
f2 – 2f1, –40°C
f2 + 2f1, +110°C
f2 + 2f1, +40°C
f2 + 2f1, –40°C
–90
–100
–110
0
4
6
8
10
12
0
5
10
15
20
25
30
INTERMODULATION FREQUENCY (MHz)
RECEIVER ATTENUATION (dB)
Figure 11. Receiver IIP3 vs. Intermodulation Frequency, 900 MHz LO,
0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Figure 14. Receiver DC Offset vs. Receiver Attenuation, 800 MHz LO,
20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
0
–40
–10
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–50
–20
–30
–40
–60
–70
–80
–50
–60
–70
–80
–90
–90
–100
–110
–100
–110
0
5
10
15
20
25
30
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
RECEIVER ATTENUATION (dB)
Figure 12. Receiver Image vs. Receiver Attenuation, 800 MHz LO, Continuous
Wave (CW) Signal 3 MHz Offset, 20 MHz RF Bandwidth, Background
Tracking Calibration (BTC) Active, 30.72 MSPS Sample Rate
Figure 15. Receiver HD2 vs. Receiver Attenuation, 800 MHz LO, CW Signal
3 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel for
Decibel with Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
25
–40
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
20
15
10
5
–50
–60
–70
–80
0
–90
–5
–10
–15
–100
–110
0
5
10
15
20
25
30
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
RECEIVER ATTENUATION (dB)
Figure 13. Receiver Gain vs. Receiver Attenuation, 800 MHz LO, CW Signal
3 MHz Offset, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Figure 16. Receiver HD3 vs. Receiver Attenuation, 800 MHz LO, CW Signal
3 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel for
Decibel with Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Rev. 0 | Page 19 of 61
AD9375
Data Sheet
0
–10
–20
–30
–40
–50
–60
30
25
20
15
10
5
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
0
–35
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
–30
–25
–20
–15
–10
–5
0
5
10
RECEIVER INPUT POWER (dBm)
OUT-OF-BAND INTERFERER SIGNAL POWER (dBm)
Figure 17. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power,
900 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,
BTC Active, 30.72 MSPS Sample Rate
Figure 20. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power,
703 MHz LO, 901 MHz CW Interferer, NF Integrated over 7 MHz to 10 MHz,
20 MHz RF Bandwidth
–20
–30
0
+110°C
+40°C
–40°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
–110
–120
300
400
500
600
700
800
900
1000
0
5
10
15
30
RECEIVER LO FREQUENCY (MHz)
RF ATTENUATION (dB)
Figure 18. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency,
100 MHz RF Bandwidth, CW Tone 3 MHz Offset from LO
Figure 21. Transmitter Image vs. RF Attenuation, 20 MHz RF Bandwidth,
900 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run with
Two 20 MHz LTE Downlink Carriers, Then Image Measured with CW 10 MHz
Offset from LO, 3 dB Digital Backoff, 122.88 MSPS Sample Rate
30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
25
20
15
10
5
0
–50
–45
–40
–35
–30
–25
–20
–10
–5
0
5
10
CLOSE-IN INTERFERER SIGNAL POWER (dBm)
DESIRED OFFSET FREQUENCY (MHz)
Figure 19. Receiver Noise Figure vs. Close-In Interferer Signal Power,
703 MHz LO, 709 MHz CW Interferer, NF Integrated over 7 MHz to 10 MHz,
20 MHz RF Bandwidth
Figure 22. Transmitter Image vs. Desired Offset Frequency,
20 MHz RF Bandwidth, 900 MHz LO, 0 dB RF Attenuation, Transmitter
QEC Tracking Run with Two 20 MHz LTE Downlink Carriers, Then Image
Measured with CW Signal, 3 dB Digital Backoff, 122.88 MSPS Sample Rate
Rev. 0 | Page 20 of 61
Data Sheet
AD9375
10
8
–20
–30
6
–40
4
–50
2
–60
0
–70
–2
–4
–6
–8
–10
–80
–90
+110°C
+40°C
–40°C
–100
–110
–120
300
400
500
600
700
800
900
1000
300
400
500
600
700
800
900
1000
FREQUENCY (MHz)
RECEIVER LO FREQUENCY (MHz)
Figure 23. Tx Output Power, Transmitter QEC, and External LO Leakage
Tracking Active, 10 MHz CW Offset Signal, 1 MHz Resolution Bandwidth,
122.88 MSPS Sample Rate
Figure 26. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,
20 MHz Receiver RF Bandwidth, 20 MHz Transmitter RF Bandwidth,
CW Signal 3 MHz Offset from LO
–60
–20
–30
+110°C
+40°C
–40°C
–65
–70
–75
–80
–85
–90
–95
–100
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
5
10
15
20
300
400
500
600
700
800
900
1000
RF ATTENUATION (dB)
RECEIVER LO FREQUENCY (MHz)
Figure 27. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency, 20 MHz Receiver RF
Bandwidth, 20 MHz Transmitter RF Bandwidth, CW Signal 3 MHz Offset from LO
Figure 24. Transmitter LO Leakage vs. RF Attenuation, 900 MHz LO, Transmitter
QEC and External LO Leakage Tracking Active, CW Signal 5 MHz Offset from LO,
6 dB Digital Backoff, 1 MHz Measurement Bandwidth (If Input Power to ORx
Channel Is Not Held Constant, Performance Degrades As Shown in This Plot)
–20
–30
–60
900MHz, +110°C
900MHz, +40°C
900MHz, –40°C
–65
–40
600MHz, +110°C
600MHz, +40°C
600MHz, –40°C
300MHz, +110°C
300MHz, +40°C
300MHz, –40°C
–70
–75
–80
–85
–90
–95
–100
–50
–60
–70
–80
–90
–100
–110
–120
300
400
500
600
700
800
900
1000
–10
–5
0
5
10
TRANSMITTER LO FREQUENCY (MHz)
OFFSET FREQUENCY (MHz)
Figure 28. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,
20 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO
Figure 25. Transmitter LO Leakage vs. Offset Frequency,
Transmitter QEC and External LO Leakage Tracking Active,
5 dB Digital Backoff, 1 MHz Measurement Bandwidth
Rev. 0 | Page 21 of 61
AD9375
Data Sheet
–80
–90
–60
–70
+110°C
+40°C
–40°C
–100
–110
–120
–130
–140
–150
–160
–170
–80
–90
–100
–110
–120
–130
–140
–150
–180
0
5
10
15
20
100
1k
10k
100k
1M
10M
RF ATTENUATION (dB)
OFFSET FREQUENCY (Hz)
Figure 29. Transmitter Noise vs. RF Attenuation, 800 MHz LO,
20 MHz Offset Frequency
Figure 32. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,
710 MHz LO
–40
1.0
+110°C LOWER
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
+110°C
+40°C
–40°C
+40°C LOWER
–40°C LOWER
+110°C UPPER
+40°C UPPER
–40°C UPPER
–45
–50
–55
–60
–65
–70
–75
–80
0
4
8
12
16
20
300
400
500
600
700
800
900
1000
RF ATTENUATION (dB)
TRANSMITTER LO FREQUENCY (MHz)
Figure 33. Tx Integrated Phase Noise vs. Transmitter LO Frequency,
20 MHz RF Bandwidth, CW 20 MHz Offset from LO, 3 dB Digital Backoff
Figure 30. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation, 900 MHz LO,
20 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal, Transmitter
QEC and LO Leakage Tracking Active
35
30
25
20
–40
+110°C LOWER
+40°C LOWER
–40°C LOWER
+110°C UPPER
+40°C UPPER
–40°C UPPER
–45
–50
–55
–60
–65
–70
–75
–80
15
+110°C
+40°C
–40°C
10
5
0
0
2
4
6
8
10
12
14
16
18
20
0
4
8
12
16
20
RF ATTENUATION (dB)
RF ATTENUATION (dB)
Figure 34. Transmitter OIP3 vs. RF Attenuation, 800 MHz LO,
20 MHz RF Bandwidth, f1 = 10 MHz, f2 = 11 MHz, 3 dB Digital Backoff,
122.88 MSPS Sample Rate
Figure 31. Tx Alternate Channel Leakage Ratio vs. RF Attenuation,
900 MHz LO, 20 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active
Rev. 0 | Page 22 of 61
Data Sheet
AD9375
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
700
725
750
775
800
825
850
875
900
0
5
10
15
20
25
30
FREQUENCY (MHz)
RF ATTENUATION (dB)
Figure 35. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff,
20 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,
LTE 10 MHz Signal, 800 MHz LO, 1 MHz Resolution Bandwidth,
Figure 38. Transmitter HD2 vs. RF Attenuation, 800 MHz LO,
810 MHz CW Desired Signal, 20 MHz RF Bandwidth,
122.88 MSPS Sample Rate
122.88 MSPS Sample Rate, Test Equipment Noise Floor De-Embedded
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
+110°C
+40°C
–40°C
–20
–30
–40
–50
–60
–70
–80
–100
300 400 500 600 700 800 900 1000 1100 1200 1300
0
5
10
15
20
FREQUENCY (MHz)
RF ATTENUATION (dB)
Figure 36. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff,
20 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,
LTE 10 MHz Signal, 800 MHz LO, 1 MHz Resolution Bandwidth,
122.88 MSPS Sample Rate, Expanded Frequency View, Test Equipment Noise
Floor De-Embedded
Figure 39. Transmitter HD3 vs. RF Attenuation, 800 MHz LO,
810 MHz CW Desired Signal, 20 MHz RF Bandwidth,
122.88 MSPS Sample Rate
–20
10
+110°C
+40°C
+110°C
+40°C
–25
5
–40°C
–40°C
–30
0
–35
–40
–45
–50
–5
–10
–15
–20
0
4
8
12
16
20
0
5
10
15
20
RF ATTENUATION (dB)
RF ATTENUATION (dB)
Figure 37. Transmitter EVM vs. RF Attenuation, 900 MHz LO,
Transmitter LO Leakage and Transmitter QEC Tracking Active, 20 MHz RF
Bandwidth, LTE 20 MHz Downlink Signal, 122.88 MSPS Sample Rate
Figure 40. Transmitter Output Power vs. RF Attenuation, 800 MHz LO,
810 MHz CW Desired Signal, 20 MHz RF Bandwidth,
122.88 MSPS Sample Rate
Rev. 0 | Page 23 of 61
AD9375
Data Sheet
0.10
0.08
0.06
0.04
0.02
0
30
25
20
15
10
5
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–0.02
–0.04
–0.06
–0.08
–0.10
0
0
300
5
10
15
20
25
30
400
500
600
700
800
900
1000
RF ATTENUATION (dB)
OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 44. Observation Receiver Noise Figure vs. Observation Receiver LO
Frequency, 0 dB Receiver Attenuation, 100 MHz RF Bandwidth,
122.88 MSPS Sample Rate, 100 MHz Integration Bandwidth
Figure 41. Tx Attenuation Step Error vs. RF Attenuation, 800 MHz LO,
810 MHz CW Desired Signal, 20 MHz RF Bandwidth,
122.88 MSPS Sample Rate
80
70
60
50
40
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
30
+110°C
+40°C
–40°C
20
10
0
–50 –40 –30 –20 –10
0
10
20
30
40
50
0
10
20
30
40
50
60
70
80
90 100 110
FREQUENCY OFFSET FROM LO (MHz)
f1 OFFSET FREQUENCY (MHz)
Figure 45. Observation Receiver IIP2 vs. f1 Offset Frequency, 900 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, f2 = f1 + 1 MHz,
122.88 MSPS Sample Rate
Figure 42. Transmitter Frequency Response Deviation from Flatness vs.
Frequency Offset from LO, 800 MHz LO, 20 MHz RF Bandwidth,
6 dB Digital Backoff, 122.88 MSPS Sample Rate
80
70
60
50
40
–40
+110°C
+40°C
–40°C
–50
–60
–70
–80
30
+110°C
+40°C
20
–40°C
–90
10
0
–100
0
10
15
20
25
30
35
40
45
50
55
60
300
400
500
600
700
800
900
1000
INTERMODULATION FREQUENCY (MHz)
OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 46. Observation Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),
900 MHz LO, 0 dB Attenuation, 100 MHz RF Bandwidth,
122.88 MSPS Sample Rate
Figure 43. Observation Receiver LO Leakage vs. Observation Receiver LO
Frequency, 0 dB Receiver Attenuation, 100 MHz RF Bandwidth,
122.88 MSPS Sample Rate
Rev. 0 | Page 24 of 61
Data Sheet
AD9375
40
35
30
25
20
15
10
5
25
20
15
10
5
0
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–5
–10
–15
0
0
3
6
9
12
15
18
0
10
20
30
40
50
60
70
80
90 100 110
OBSERVATION RECEIVER ATTENUATION (dB)
f1 OFFSET FREQUENCY (MHz)
Figure 47. Observation Receiver IIP3 vs. f1 Offset Frequency, 900 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, f2 = 2f1 + 1 MHz,
122.88 MSPS Sample Rate
Figure 50. Observation Receiver Gain vs. Observation Receiver Attenuation,
800 MHz LO, CW Signal 16 MHz Offset, 100 MHz RF Bandwidth,
122.88 MSPS Sample Rate
40
35
30
25
20
–40
–50
+110°C
+40°C
–40°C
–60
–70
–80
15
–90
+110°C
+40°C
–40°C
10
–100
–110
–120
5
0
5
10
15
20
25
30
35
40
45
50
55
60
0
3
6
9
12
15
18
INTERMODULATION FREQUENCY (MHz)
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 48. Observation Receiver IIP3 vs. Intermodulation Frequency (2f2 − f1),
900 MHz LO, 0 dB Attenuation, 100 MHz RF Bandwidth,
122.88 MSPS Sample Rate
Figure 51. Observation Receiver DC Offset vs. Observation Receiver
Attenuation, 800 MHz LO, 100 MHz RF Bandwidth,
122.88 MSPS Sample Rate
0
0
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
3
6
9
12
15
18
0
3
6
9
12
15
18
OBSERVATION RECEIVER ATTENUATION (dB)
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 49. Observation Receiver Image vs. Observation Receiver Attenuation,
800 MHz LO, CW Signal 16 MHz Offset, 100 MHz RF Bandwidth, BTC Active,
122.88 MSPS Sample Rate
Figure 52. Observation Receiver HD2 vs. Observation Receiver Attenuation,
800 MHz LO, CW Signal 16 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Rev. 0 | Page 25 of 61
AD9375
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
90
80
70
60
50
40
30
20
10
0
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–100
0
3
6
9
12
15
18
3
6
9
12
15
OBSERVATION RECEIVER ATTENUATION (dB)
INTERMODULATION FREQUENCY (MHz)
Figure 53. Observation Receiver HD3 vs. Observation Receiver Attenuation,
800 MHz LO, CW Signal 16 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Figure 56. Sniffer Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),
600 MHz LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
–50
20
15
10
5
–60
–70
+110°C
+40°C
–40°C
–80
–90
–100
–110
–120
–130
0
+110°C
+40°C
–40°C
–5
–10
300
400
500
600
700
3
6
9
12
15
SNIFFER RECEIVER LO FREQUENCY (MHz)
INTERMODULATION FREQUENCY (MHz)
Figure 54. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Figure 57. Sniffer Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), 600 MHz
LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
30
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
25
20
15
10
5
0
300
400
500
600
700
0
5
10
15
20
SNIFFER RECEIVER LO FREQUENCY (MHz)
SNIFFER RECEIVER ATTENUATION (dB)
Figure 55. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate,
20 MHz Integration Bandwidth
Figure 58. Sniffer Receiver Image vs. Sniffer Receiver Attenuation,
600 MHz LO, CW Signal 3 MHz Offset, 20 MHz RF Bandwidth,
30.72 MSPS Sample Rate
Rev. 0 | Page 26 of 61
Data Sheet
AD9375
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–110
0
5
10
15
20
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
SNIFFER RECEIVER ATTENUATION (dB)
SNIFFER RECEIVER INPUT POWER (dBm)
Figure 59. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation,
600 MHz LO, CW Signal 3 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Figure 62. Sniffer Receiver EVM vs. Sniffer Receiver Input Power, 600 MHz LO,
20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC, BTC Active,
30.72 MSPS Sample Rate
0
40
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
30
+110°C
+40°C
–40°C
20
10
0
–10
–20
–30
–40
0
5
10
15
20
0
4
8
12 16 20 24 28 32 36 40 44 48 52
SNIFFER RECEIVER ATTENUATION (dB)
SNIFFER RECEIVER ATTENUATION (dB)
Figure 60. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation, 600 MHz LO,
CW Signal 3 MHz Offset, −35 dBm at 0 dB Attenuation, Input Power Increasing
Decibel for Decibel with Attenuation, 20 MHz RF Bandwidth,
30.72 MSPS Sample Rate
Figure 63. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,
600 MHz LO, CW Signal 3 MHz Offset, 20 MHz RF Bandwidth,
30.72 MSPS Sample Rate
0
–10
+110°C
+40°C
–40°C
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
SNIFFER RECEIVER ATTENUATION (dB)
Figure 61. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 600 MHz LO,
CW Signal 3 MHz Offset, −35 dBm at 0 dB Attenuation, Input Power
Increasing Decibel for Decibel with Attenuation, 20 MHz RF Bandwidth,
30.72 MSPS Sample Rate
Rev. 0 | Page 27 of 61
AD9375
Data Sheet
2.6 GHz BAND
–30
100
90
80
70
60
50
40
30
20
10
0
–40
–50
–60
–70
–80
+110°C
+40°C
–40°C
–90
–100
–110
+110°C
+40°C
–40°C
0
5
10
15
20
25
30
f1 OFFSET FREQUENCY (MHz)
RECEIVER LO FREQUENCY (MHz)
Figure 64. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency,
0 dB Receiver Attenuation, 40 MHz RF Bandwidth,
122.88 MSPS Sample Rate
Figure 67. Receiver IIP2 vs. f1 Offset Frequency, 2600 MHz LO,
0 dB Attenuation, 40 MHz RF Bandwidth, f2 = f1 + 1 MHz,
122.88 MSPS Sample Rate
45
40
35
30
25
20
15
100
90
80
70
60
50
40
30
f2
f2
f2
f2
f2
f2
–
–
–
+
+
+
f1, +110°C
f1, +40°C
f1, –40°C
f1, +110°C
f1, +40°C
f1, –40°C
10
20
10
0
+110°C
+40°C
–40°C
5
0
0
3
6
9
12
15
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
INTERMODULATION FREQUENCY (MHz)
Figure 65. Receiver Noise Figure vs. Receiver Attenuation, 2600 MHz LO,
40 MHz Bandwidth, 122.88 MSPS Sample Rate, 20 MHz Integration
Bandwidth (Includes 1.4 dB Matching Circuit Loss)
Figure 68. Receiver IIP2 vs. Intermodulation Frequency, 2600 MHz LO,
0 dB Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
30
25
20
40
35
30
25
20
15
10
15
+110°C
+40°C
–40°C
10
5
+110°C
+40°C
–40°C
5
0
0
0
5
10
15
20
25
30
f1 OFFSET FREQUENCY (MHz)
RECEIVER LO FREQUENCY (MHz)
Figure 69. Receiver IIP3 vs. f1 Offset Frequency, 2600 MHz LO,
0 dB Attenuation, 40 MHz RF Bandwidth, f2 = 2 f1 + 2 MHz,
122.88 MSPS Sample Rate
Figure 66. Receiver Noise Figure vs. Receiver LO Frequency,
0 dB Receiver Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate,
20 MHz Integration Bandwidth (Includes 1.4 dB Matching Circuit Loss)
Rev. 0 | Page 28 of 61
Data Sheet
AD9375
40
35
30
25
20
15
10
5
–40
–50
+110°C
+40°C
–40°C
–60
–70
–80
–90
f2 – 2f1, +110°C
f2 – 2f1, +40°C
f2 – 2f1, –40°C
f2 + 2f1, +110°C
f2 + 2f1, +40°C
f2 + 2f1, –40°C
–100
–110
–120
0
5
10
15
20
25
30
0
5
10
15
20
25
30
INTERMODULATION FREQUENCY (MHz)
RECEIVER ATTENUATION (dB)
Figure 70. Receiver IIP3 vs. Intermodulation Frequency, 2600 MHz LO,
0 dB Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Figure 73. Receiver DC Offset vs. Receiver Attenuation, 2550 MHz LO,
40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
–40
–40
+110°C
+40°C
–40°C
–50
+110°C
+40°C
–40°C
–50
–60
–70
–60
–70
–80
–80
–90
–90
–100
–110
–100
0
5
10
15
20
25
30
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
RECEIVER ATTENUATION (dB)
Figure 71. Receiver Image vs. Receiver Attenuation, 2600 MHz LO,
Continuous Wave (CW) Signal 5 MHz Offset, 40 MHz RF Bandwidth,
Background Tracking Calibration (BTC) Active, 122.88 MSPS Sample Rate
Figure 74. Receiver HD2 vs. Receiver Attenuation, 2600 MHz LO, CW Signal
5 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel
for Decibel with Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
25
–40
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
20
15
10
5
–50
–60
–70
–80
0
–90
–5
–10
–15
–100
–110
0
5
10
15
20
25
30
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
RECEIVER ATTENUATION (dB)
Figure 72. Receiver Gain vs. Receiver Attenuation, 2600 MHz LO, CW Signal
5 MHz Offset, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Figure 75. Receiver HD3 vs. Receiver Attenuation, 2600 MHz LO, CW Signal
5 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power Increasing Decibel
for Decibel with Attenuation, 40 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Rev. 0 | Page 29 of 61
AD9375
Data Sheet
0
30
25
20
15
10
5
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–5
–10
–15
–20
–25
–30
–35
–40
–45
0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
–40
–35
–30
–25
–20
–15
–10
–5
0
RECEIVER INPUT POWER (dBm)
OUT-OF-BAND INTERFERER SIGNAL POWER (dBm)
Figure 76. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power,
2600 MHz LO, 40 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC, BTC
Active, 122.88 MSPS Sample Rate
Figure 79. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power,
2614 MHz LO, 2435 MHz CW Interferer, Noise Figure Integrated over
7 MHz to 10 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
+110°C
+40°C
–10
–40°C
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
RF ATTENUATION (dB)
RECEIVER LO FREQUENCY (MHz)
Figure 77. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency, 40 MHz
RF Bandwidth, CW Tone 3 MHz Offset from LO
Figure 80. Transmitter Image vs. RF Attenuation, 40 MHz RF Bandwidth,
2600 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run
with Two 20 MHz LTE Downlink Carriers, Then Image Measured with CW
10 MHz Offset from LO, 3 dB Digital Backoff, 245.76 MSPS Sample Rate
30
25
20
15
10
0
+110°C
+40°C
–10
–40°C
–20
–30
–40
–50
–60
–70
–80
–90
–100
5
+110°C
+40°C
–40°C
0
–50
–45
–40
–35
–30
–25
–20
–20
–15
–10
–5
0
5
10
15
20
CLOSE-IN INTERFERER SIGNAL POWER (dBm)
DESIRED OFFSET FREQUENCY (MHz)
Figure 81. Transmitter Image vs. Desired Offset Frequency, 40 MHz RF
Bandwidth, 2300 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking
Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with
CW Signal, 3 dB Digital Backoff, 245.76 MSPS Sample Rate
Figure 78. Receiver Noise Figure vs. Close-In Interferer Signal Power,
2614 MHz LO, 2625 MHz CW Interferer, Noise Figure Integrated over
7 MHz to 10 MHz, 40 MHz RF Bandwidth
Rev. 0 | Page 30 of 61
Data Sheet
AD9375
10
8
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
6
4
2
0
–2
–4
–6
–8
–10
+110°C
+40°C
–40°C
FREQUENCY (MHz)
RECEIVER LO FREQUENCY (MHz)
Figure 82. Tx Output Power, Transmitter QEC, and External LO Leakage
Active, 5 MHz CW Offset Signal, 1 MHz Resolution Bandwidth,
245.76 MSPS Sample Rate
Figure 85. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,
40 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
CW Signal 3 MHz Offset from LO
–60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
–65
–70
–75
–80
–85
–90
–95
–100
0
5
10
15
20
RF ATTENUATION (dB)
RECEIVER LO FREQUENCY (MHz)
Figure 83. Transmitter LO Leakage vs. RF Attenuation, 2300 MHz LO,
External Transmitter QEC and LO Leakage Tracking Active, CW Signal 10 MHz
Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Bandwidth (If Input
Power to the ORx Channel Is Not Held Constant, Device Performance
Degrades as Shown in This Figure)
Figure 86. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency,
40 MHz Receiver RF Bandwidth, 40 MHz Transmitter RF Bandwidth,
CW Signal 3 MHz Offset from LO
–60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1.8GHz, +110°C
1.8GHz, +40°C
1.8GHz, –40°C
2.3GHz, +110°C
2.3GHz, +40°C
2.3GHz, –40°C
2.8GHz, +110°C
2.8GHz, +40°C
2.8GHz, –40°C
–65
–70
–75
–80
–85
–90
–95
–100
–30
–20
–10
0
10
20
30
OFFSET FREQUENCY (MHz)
TRANSMITTER LO FREQUENCY (MHz)
Figure 84. Transmitter LO Leakage vs. Offset Frequency, External Transmitter
QEC and LO Leakage Tracking Active, 6 dB Digital Backoff,
1 MHz Measurement Bandwidth
Figure 87. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,
40 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO
Rev. 0 | Page 31 of 61
AD9375
Data Sheet
–60
–70
–80
–90
+110°C
+40°C
–40°C
–100
–110
–120
–130
–140
–150
–160
–170
–80
–90
–100
–110
–120
–130
–140
–150
–180
0
5
10
15
20
100
1k
10k
100k
1M
10M
RF ATTENUATION (dB)
OFFSET FREQUENCY (Hz)
Figure 88. Transmitter Noise vs. RF Attenuation, 2600 MHz LO,
10 MHz Offset Frequency
Figure 91. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,
2600 MHz
–40
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
+110°C UPPER
+40°C UPPER
–40°C UPPER
+110°C LOWER
+40°C LOWER
–40°C LOWER
–45
–50
–55
–60
–65
–70
–75
–80
0.2
+110°C
+40°C
–40°C
0.1
0
0
4
8
12
16
20
RF ATTENUATION (dB)
TRANSMITTER LO FREQUENCY (MHz)
Figure 89. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation,
2600 MHz LO, 40 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
Transmitter QEC and LO Leakage Tracking Active
Figure 92. Tx Integrated Phase Noise vs. Transmitter LO Frequency,
40 MHz RF Bandwidth, Continuous Wave 20 MHz Offset from LO,
3 dB Digital Backoff
–40
35
+110°C
+40°C
–40°C
+110°C UPPER
+40°C UPPER
–40°C UPPER
+110°C LOWER
+40°C LOWER
–40°C LOWER
–45
–50
–55
–60
–65
–70
–75
–80
30
25
20
15
10
5
0
0
4
8
12
16
20
0
2
4
6
8
10
12
14
16
18
20
RF ATTENUATION (dB)
RF ATTENUATION (dB)
Figure 90. Tx Alternate Channel Leakage Ratio vs. RF Attenuation,
2600 MHz LO, 40 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active
Figure 93. Transmitter OIP3 vs. RF Attenuation, 2600 MHz LO,
40 MHz RF Bandwidth, f1 = 20 MHz, f2 = 21 MHz, 3 dB Digital Backoff,
245.76 MSPS Sample Rate
Rev. 0 | Page 32 of 61
Data Sheet
AD9375
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
2500
2525
2550
2575
2600
2625
2650
2675
2700
0
5
10
15
20
FREQUENCY (MHz)
RF ATTENUATION (dB)
Figure 94. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff,
40 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active,
LTE 10 MHz Signal, 2600 MHz LO, 1 MHz Resolution Bandwidth,
245.76 MSPS Sample Rate, Test Equipment Noise Floor De-Embedded
Figure 97. Transmitter HD2 vs. RF Attenuation, 2600 MHz LO,
2605 MHz CW Desired Signal, 40 MHz RF Bandwidth,
245.76 MSPS Sample Rate
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
+110°C
+40°C
–40°C
–10
–20
–30
–40
–50
–60
–70
–80
0
5
10
15
20
RF ATTENUATION (dB)
FREQUENCY (MHz)
Figure 95. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff,
40 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active,
LTE 10 MHz Signal, 2600 MHz LO, 1 MHz Resolution Bandwidth,
245.76 MSPS Sample Rate, Expanded Frequency View, Test Equipment Noise
Floor De-Embedded
Figure 98. Transmitter HD3 vs. RF Attenuation, 2600 MHz LO,
2605 MHz CW Desired Signal, 40 MHz RF Bandwidth,
245.76 MSPS Sample Rate
–20
10
+110°C
+40°C
–40°C
–25
+110°C
+40°C
–40°C
5
–30
–35
–40
–45
–50
0
–5
–10
–15
–20
0
4
8
12
16
20
0
5
10
15
20
RF ATTENUATION (dB)
RF ATTENUATION (dB)
Figure 96. Transmitter EVM vs. RF Attenuation, 2550 MHz LO, Transmitter LO
Leakage and Transmitter QEC Tracking Active, 200 MHz RF Bandwidth,
LTE 20 MHz Downlink Signal, 245.76 MSPS Sample Rate
Figure 99. Transmitter Output Power vs. RF Attenuation, 2600 MHz LO, 2605
MHz CW Desired Signal, 40 MHz RF Bandwidth,
245.76 MSPS Sample Rate
Rev. 0 | Page 33 of 61
AD9375
Data Sheet
0.10
0.08
0.06
0.04
0.02
0
30
25
20
15
10
5
+110°C
+40°C
–40°C
–0.02
–0.04
–0.06
–0.08
+110°C
+40°C
–40°C
–0.10
0
0
2
4
6
8
10
12
14
16
18
20
RF ATTENUATION (dB)
OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 103. Observation Receiver Noise Figure vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate, 100 MHz Integration Bandwidth
Figure 100. Tx Attenuation Step Error vs. RF Attenuation, 2600 MHz LO,
2610 MHz CW Desired Signal, 40 MHz RF Bandwidth,
245.76 MSPS Sample Rate
80
70
60
50
40
30
20
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
+110°C
+40°C
–40°C
10
0
–100 –80 –60 –40 –20
0
20
40
60
80
100
0
10
20
30
40
50
60
70
80
90 100 110
FREQUENCY OFFSET FROM LO (MHz)
f1 OFFSET FREQUENCY (MHz)
Figure 101. Transmitter Frequency Response Deviation from Flatness vs.
Frequency Offset from LO, 2600 MHz LO, 100 MHz RF Bandwidth,
6 dB Digital Backoff, 245.76 MSPS Sample Rate
Figure 104. Observation Receiver IIP2 vs. f1 Offset Frequency, 2600 MHz LO,
0 dB Attenuation, 200 MHz RF Bandwidth, f2 = f1 + 1 MHz,
245.76 MSPS Sample Rate
–40
80
70
60
50
40
30
20
+110°C
+40°C
–40°C
–45
–50
–55
–60
–65
–70
–75
–80
+110°C
+40°C
–40°C
10
0
5
15
25
35
45
55
65
75
85
95 105 115
INTERMODULATION FREQUENCY (MHz)
OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 102. Observation Receiver LO Leakage vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
Figure 105. Observation Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),
2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
Rev. 0 | Page 34 of 61
Data Sheet
AD9375
40
35
30
25
20
15
10
5
25
20
15
10
5
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
0
–5
–10
–15
0
0
3
6
9
12
15
18
0
10
20
30
40
50
60
70
80
90 100 110
OBSERVATION RECEIVER ATTENUATION (dB)
f1 OFFSET FREQUENCY (MHz)
Figure 106. Observation Receiver IIP3 vs. f1 Offset Frequency,
2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,
f2 = 2f1 + 1 MHz, 245.76 MSPS Sample Rate
Figure 109. Observation Receiver Gain vs. Observation Receiver Attenuation,
2600 MHz LO, CW Signal 25 MHz Offset, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
40
–40
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–50
35
30
25
20
15
10
5
–60
–70
–80
–90
0
–100
5
15
25
35
45
55
65
75
85
95 105 115
0
3
6
9
12
15
18
INTERMODULATION FREQUENCY (MHz)
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 107. Observation Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1),
2600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
Figure 110. Observation Receiver DC Offset vs. Observation Receiver
Attenuation, 2600 MHz LO, 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
0
0
+110°C
+40°C
–40°C
–20
+110°C
+40°C
–40°C
–20
–40
–60
–40
–60
–80
–80
–100
–120
–100
–120
0
3
6
9
12
15
18
0
3
6
9
12
15
18
OBSERVATION RECEIVER ATTENUATION (dB)
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 108. Observation Receiver Image vs. Observation Receiver
Attenuation, 2600 MHz LO, CW Signal 25 MHz Offset, 200 MHz RF
Bandwidth, BTC Active, 245.76 MSPS Sample Rate
Figure 111. Observation Receiver HD2 vs. Observation Receiver Attenuation,
2600 MHz LO, CW Signal 25 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
Rev. 0 | Page 35 of 61
AD9375
Data Sheet
0
90
80
70
60
50
40
30
20
10
0
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–20
–40
–60
–80
–100
–120
0
3
6
9
12
15
18
3
6
9
12
OBSERVATION RECEIVER ATTENUATION (dB)
INTERMODULATION FREQUENCY (MHz)
Figure 112. Observation Receiver HD3 vs. Observation Receiver Attenuation,
2600 MHz LO, CW Signal 25 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
Figure 115. Sniffer Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),
2600 MHz LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
–40
20
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
15
–50
–60
10
5
–70
–80
–90
0
–100
–110
–120
–5
–10
2300
2400
2500
2600
2700
2800
0
2
4
6
8
10
12
SNIFFER RECEIVER LO FREQUENCY (MHz)
INTERMODULATION FREQUENCY (MHz)
Figure 113. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Figure 116. Sniffer Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1), 2600 MHz
LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
30
0
+110°C
+110°C
+40°C
+40°C
–10
–40°C
–40°C
25
–20
–30
–40
–50
–60
–70
–80
–90
–100
20
15
10
5
0
2300
2400
2500
2600
2700
2800
0
5
10
15
20
SNIFFER RECEIVER LO FREQUENCY (MHz)
SNIFFER RECEIVER ATTENUATION (dB)
Figure 114. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate,
20 MHz Integration Bandwidth
Figure 117. Sniffer Receiver Image vs. Sniffer Receiver Attenuation, 2600 MHz
LO, CW Signal 1 MHz Offset, 20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Rev. 0 | Page 36 of 61
Data Sheet
AD9375
–40
–50
–60
–70
–80
–90
–100
0
–5
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–10
–15
–20
–25
–30
–35
–40
–45
–50
–110
0
5
10
15
20
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
SNIFFER RECEIVER ATTENUATION (dB)
SNIFFER RECEIVER INPUT POWER (dBm)
Figure 118. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation,
2600 MHz LO, CW Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Figure 121. Sniffer Receiver EVM vs. Sniffer Receiver Input Power,
2600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,
BTC Active, 30.72 MSPS Sample Rate
0
40
+110°C
+40°C
–40°C
+110°C
+40°C
–10
–40°C
30
–20
–30
–40
–50
–60
–70
–80
–90
–100
20
10
0
–10
–20
–30
–40
0
5
10
15
20
0
4
8
12 16 20 24 28 32 36 40 44 48 52
SNIFFER RECEIVER ATTENUATION (dB)
SNIFFER RECEIVER ATTENUATION (dB)
Figure 119. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation,
2600 MHz LO, CW Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
20 MHz RF Bandwidth, 30.72 MSPS Sample Rate
Figure 122. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,
2600 MHz LO, CW Signal 1 MHz Offset, 20 MHz RF Bandwidth,
30.72 MSPS Sample Rate
0
+110°C
+40°C
–40°C
–20
–40
–60
–80
–100
–120
0
5
10
15
20
SNIFFER RECEIVER ATTENUATION (dB)
Figure 120. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation, 2600 MHz
LO, CW Signal 1 MHz Offset, −35 dBm at 0 dB Attenuation, Input Power
Increasing Decibel for Decibel with Attenuation, 20 MHz RF Bandwidth,
30.72 MSPS Sample Rate
Rev. 0 | Page 37 of 61
AD9375
Data Sheet
3.5 GHz BAND
–30
90
80
70
60
50
40
30
20
10
0
+110°C
+40°C
–40°C
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
+110°C
+40°C
–40°C
3300
3400
3500
3600
3700
3800
5
10
15
20
25
30
35
40
45
50
55
60
RECEIVER LO FREQUENCY (MHz)
f1 OFFSET FREQUENCY (MHz)
Figure 123. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency,
0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
Figure 126. Receiver IIP2 vs. f1 Offset Frequency, 3500 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, f2 = f1 + 1 MHz,
153.6 MSPS Sample Rate
45
100
f2
f2
f2
f2
f2
f2
–
–
–
+
+
+
f1, +110°C
f1, +40°C
f1, –40°C
f1, +110°C
f1, +40°C
f1, –40°C
+110°C
+40°C
–40°C
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
0
5
10
15
20
25
30
35
40
45
50
55
60
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
INTERMODULATION FREQUENCY (MHz)
Figure 127. Receiver IIP2 vs. Intermodulation Frequency, 3500 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
Figure 124. Receiver Noise Figure vs. Receiver Attenuation, 3500 MHz LO,
100 MHz Bandwidth, 153.6 MSPS Sample Rate, 50 MHz Integration Bandwidth
(Includes 1 dB Matching Circuit Loss)
40
30
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
35
30
25
20
15
10
5
25
20
15
10
5
0
3300
0
3400
3500
3600
3700
3800
5
10
15
20
25
30
35
40
45
50
55
60
RECEIVER LO FREQUENCY (MHz)
f1 OFFSET FREQUENCY (MHz)
Figure 128. Receiver IIP3 vs. f1 Offset Frequency, 3500 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, f2 = 2 f1 + 1 MHz,
153.6 MSPS Sample Rate
Figure 125. Receiver Noise Figure vs. Receiver LO Frequency,
0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate,
50 MHz Integration Bandwidth (Includes 1 dB Matching Circuit Loss)
Rev. 0 | Page 38 of 61
Data Sheet
AD9375
40
35
30
25
20
15
10
5
–40
–50
f2
f2
f2
f2
f2
f2
–
–
–
+
+
+
f1, +110°C
f1, +40°C
f1, –40°C
f1, +110°C
f1, +40°C
f1, –40°C
+110°C
+40°C
–40°C
–60
–70
–80
–90
–100
–110
–120
0
5
10
15
20
25
30
35
40
45
50
55
60
0
5
10
15
20
25
30
INTERMODULATION FREQUENCY (MHz)
RECEIVER ATTENUATION (dB)
Figure 132. Receiver DC Offset vs. Receiver Attenuation, 3500 MHz LO,
100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
Figure 129. Receiver IIP3 vs. Intermodulation Frequency, 3500 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
–40
–40
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–50
–50
–60
–70
–60
–70
–80
–80
–90
–90
–100
–110
–100
–110
0
5
10
15
20
25
30
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
RECEIVER ATTENUATION (dB)
Figure 133. Receiver HD2 vs. Receiver Attenuation, 3500 MHz LO, CW Signal
17 MHz Offset, −14 dBm at 0 dB Attenuation, Input Power Increasing Decibel for
Decibel with Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
Figure 130. Receiver Image vs. Receiver Attenuation, 3500 MHz LO,
Continuous Wave (CW) Signal 17 MHz Offset, 100 MHz RF Bandwidth,
Background Tracking Calibration (BTC) Active, 153.6 MSPS Sample Rate
–40
25
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
20
–50
15
10
5
–60
–70
–80
0
–90
–5
–10
–15
–100
–110
0
5
10
15
20
25
30
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
RECEIVER ATTENUATION (dB)
Figure 131. Receiver Gain vs. Receiver Attenuation, 3500 MHz LO, CW Signal
17 MHz Offset, 100 MHz RF Bandwidth, De-Embedded to Receiver Port,
153.6 MSPS Sample Rate
Figure 134. Receiver HD3 vs. Receiver Attenuation, 3500 MHz LO, CW Signal
17 MHz Offset, −14 dBm at 0 dB Attenuation, Input Power Increasing Decibel
for Decibel with Attenuation, 100 MHz RF Bandwidth, 153.6 MSPS Sample Rate
Rev. 0 | Page 39 of 61
AD9375
Data Sheet
0
30
25
20
15
10
5
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–5
–10
–15
–20
–25
–30
–35
–40
–45
0
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
–30
–25
–20
–15
–10
–5
0
RECEIVER INPUT POWER (dBm)
OUT-OF-BAND INTERFERER SIGNAL POWER (dBm)
Figure 135. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power,
3600 MHz LO, 100 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,
BTC Active, 153.6 MSPS Sample Rate
Figure 138. Receiver Noise Figure vs. Out of Band Interferer Signal Power,
3614 MHz LO, 3665 MHz CW Interferer, Noise Figure Integrated over
7 MHz to 10 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
+110°C
+40°C
–40°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
3300
3400
3500
3600
3700
3800
0
5
10
15
20
RECEIVER LO FREQUENCY (MHz)
RF ATTENUATION (dB)
Figure 136. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency,
100 MHz RF Bandwidth, CW Tone 3 MHz Offset from LO
Figure 139. Transmitter Image vs. RF Attenuation, 100 MHz RF Bandwidth,
3550 MHz LO, Transmitter Quadrature Error Correction (QEC) Tracking Run
with Two 20 MHz, LTE Downlink Carriers, Then Image Measured with CW
10 MHz Offset from LO, 6 dB Digital Backoff, 307.2 MSPS Sample Rate
30
0
+110°C
+110°C
+40°C
–40°C
+40°C
28
26
24
22
20
18
16
14
12
10
–10
–20
–40°C
–30
–40
–50
–60
–70
–80
–90
–100
–50
–45
–40
–35
–30
–25
–20
–50 –40 –30 –20 –10
0
10
20
30
40
50
CLOSE-IN INTERFERER SIGNAL POWER (dBm)
DESIRED OFFSET FREQUENCY (MHz)
Figure 137. Receiver Noise Figure vs. Close-In Interferer Signal Power,
3614 MHz LO, 3625 MHz CW Interferer, Noise Figure Integrated over
7 MHz to 10 MHz, 100 MHz RF Bandwidth
Figure 140. Transmitter Image vs. Desired Offset Frequency, 100 MHz RF
Bandwidth, 3550 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking
Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with
CW Signal, 6 dB Digital Backoff, 307.2 MSPS Sample Rate
Rev. 0 | Page 40 of 61
Data Sheet
AD9375
10
8
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
6
4
2
0
–2
–4
–6
–8
–10
+110°C
+40°C
–40°C
3300
3400
3500
3600
3700
3800
3300
3400
3500
3600
3700
3800
FREQUENCY (MHz)
RECEIVER LO FREQUENCY (MHz)
Figure 141. Tx Output Power, Transmitter QEC and
External LO Leakage Active, 5 MHz CW Offset Signal,
1 MHz Resolution Bandwidth, 307.2 MSPS Sample Rate
Figure 144. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency,
100 MHz Receiver RF Bandwidth, 100 MHz Transmitter RF Bandwidth,
CW Signal 3 MHz Offset from LO
–60
–65
–70
–75
–80
–85
–90
–95
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
0
5
10
15
20
3300
3400
3500
3600
3700
3800
RF ATTENUATION (dB)
RECEIVER LO FREQUENCY (MHz)
Figure 142. Transmitter LO Leakage vs. RF Attenuation, 3550 MHz LO,
Transmitter QEC and External LO Leakage Tracking Active, CW Signal 10 MHz
Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Bandwidth
(If Input Power to ORx Channel Is Not Held Constant, Performance Degrades
as Shown in This Plot)
Figure 145. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency,
100 MHz Receiver RF Bandwidth, 100 MHz Transmitter RF Bandwidth,
CW Signal 3 MHz Offset from LO
–60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
3.3GHz, +110°C
3.3GHz, +40°C
–65
–70
–75
–80
–85
–90
–95
–100
3.3GHz, –40°C
3.55GHz, +110°C
3.55GHz, +40°C
3.55GHz, –40°C
3.8GHz, +110°C
3.8GHz, +40°C
3.8GHz, –40°C
–30
–20
–10
0
10
20
30
3300
3800
3400
3500
3600
3700
OFFSET FREQUENCY (MHz)
TRANSMITTER LO FREQUENCY (MHz)
Figure 143. Transmitter LO Leakage vs. Offset Frequency,
Transmitter QEC and External LO Leakage Tracking Active,
6 dB Digital Backoff, 1 MHz Measurement Bandwidth
Figure 146. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,
100 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO
Rev. 0 | Page 41 of 61
AD9375
Data Sheet
–80
–90
–60
–70
+110°C
+40°C
–40°C
–100
–110
–120
–130
–140
–150
–160
–170
–80
–90
–100
–110
–120
–130
–140
–150
–180
0
5
10
15
20
100
10M
1k
10k
100k
1M
RF ATTENUATION (dB)
OFFSET FREQUENCY (Hz)
Figure 147. Transmitter Noise vs. RF Attenuation, 3500 MHz LO,
100 MHz Offset Frequency, Zeros Input Data
Figure 150. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,
3500 MHz LO
–40
1.0
+110°C
+110°C UPPER
+40°C UPPER
–40°C UPPER
+110°C LOWER
+40°C LOWER
–40°C LOWER
+40°C
0.9
–45
–50
–55
–60
–65
–70
–75
–80
–40°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
5
10
15
20
3300
3400
3500
3600
3700
3800
RF ATTENUATION (dB)
TRANSMITTER LO FREQUENCY (MHz)
Figure 148. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation,
3500 MHz LO, 100 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active
Figure 151. Tx Integrated Phase Noise vs. Transmitter LO Frequency,
100 MHz RF Bandwidth, CW 20 MHz Offset from LO, 3 dB Digital Backoff
–40
35
+110°C UPPER
+40°C UPPER
–40°C UPPER
+110°C LOWER
+40°C LOWER
–40°C LOWER
+110°C
+40°C
–45
–50
–55
–60
–65
–70
–75
–80
–40°C
30
25
20
15
10
5
0
2
4
6
8
10
12
14
16
18
0
5
10
15
20
0
20
RF ATTENUATION (dB)
RF ATTENUATION (dB)
Figure 149. Tx Alternate Channel Leakage Ratio vs. RF Attenuation,
3500 MHz LO, 100 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active
Figure 152. Transmitter OIP3 vs. RF Attenuation, 3500 MHz LO,
100 MHz RF Bandwidth, f1 = 20 MHz, f2 = 21 MHz, 3 dB Digital Backoff,
307.2 MSPS Sample Rate
Rev. 0 | Page 42 of 61
Data Sheet
AD9375
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
0
20
5
10
15
3400
3425
3450
3475
3500
3525
3550
3575
3600
RF ATTENUATION (dB)
FREQUENCY (MHz)
Figure 153. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff,
100 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active,
LTE 10 MHz Signal, 3500 MHz LO, 1 MHz Resolution Bandwidth,
Figure 156. Transmitter HD2 vs. RF Attenuation, 3500 MHz LO,
3505 MHz CW Desired Signal, 100 MHz RF Bandwidth,
307.2 MSPS Sample Rate
307.2 MSPS Sample Rate, Test Equipment Noise Floor De-Embedded
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
+110°C
+40°C
–40°C
–10
–20
–30
–40
–50
–60
–70
–80
–100
0
5
10
15
20
3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000
RF ATTENUATION (dB)
FREQUENCY (MHz)
Figure 157. Transmitter HD3 vs. RF Attenuation, 3500 MHz LO,
3505 MHz CW Desired Signal, 100 MHz RF Bandwidth,
307.2 MSPS Sample Rate
Figure 154. Tx Output Power Spectrum, 2 dB Digital and 3 dB RF Backoff,
100 MHz RF Bandwidth, Transmitter QEC and Internal LO Leakage Active,
LTE 10 MHz Signal, 3500 MHz LO, 1 MHz Resolution Bandwidth,
307.2 MSPS Sample Rate, Expanded Frequency View, Test Equipment Noise
Floor De-Embedded
–20
10
+110°C
+40°C
–40°C
–25
+110°C
+40°C
–40°C
5
0
–5
–30
–35
–40
–45
–50
–10
–15
–20
–25
0
5
10
15
20
0
5
10
15
20
RF ATTENUATION (dB)
RF ATTENUATION (dB)
Figure 155. Transmitter EVM vs. RF Attenuation, 3500 MHz LO,
Transmitter LO Leakage, and Transmitter QEC Tracking Active,
100 MHz RF Bandwidth, LTE 20 MHz Downlink Signal, 307.2 MSPS Sample Rate
Figure 158. Transmitter Output Power vs. RF Attenuation, 3500 MHz LO,
3505 MHz CW Desired Signal, 100 MHz RF Bandwidth,
2 dB Digital Backoff, 307.2 MSPS Sample Rate
Rev. 0 | Page 43 of 61
AD9375
Data Sheet
0.10
0.08
0.06
0.04
0.02
0
+110°C
+40°C
–40°C
30
25
20
15
10
5
–0.02
–0.04
–0.06
–0.08
+110°C
+40°C
–40°C
–0.10
0
2
4
6
8
10
12
14
16
18
20
0
3300
RF ATTENUATION (dB)
3400
3500
3600
3700
3800
OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 159. Tx Attenuation Step Error vs. RF Attenuation, 3500 MHz LO,
3510 MHz CW Desired Signal, 100 MHz RF Bandwidth,
Figure 162. Observation Receiver Noise Figure vs. Observation Receiver LO
Frequency, 0 dB Receiver Attenuation, 240 MHz RF Bandwidth,
307.2 MSPS Sample Rate, 120 MHz Integration Bandwidth
De-Embedded to Transmitter Port, 307.2 MSPS Sample Rate
80
70
60
50
40
30
20
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
+110°C
+40°C
–40°C
10
0
–100 –80 –60 –40 –20
0
20
40
60
80
100
0
10
20
30
40
50
60
70
80
90 100 110
FREQUENCY OFFSET FROM LO (MHz)
f1 OFFSET FREQUENCY (MHz)
Figure 163. Observation Receiver IIP2 vs. f1 Offset Frequency, 3600 MHz LO,
0 dB Attenuation, 240 MHz RF Bandwidth, f2 = f1 + 1 MHz,
307.2 MSPS Sample Rate
Figure 160. Transmitter Frequency Response Deviation from Flatness vs.
Frequency Offset from LO, 3500 MHz LO, 100 MHz RF Bandwidth,
6 dB Digital Backoff, 307.2 MSPS Sample Rate
80
–40
+110°C
+40°C
+110°C
+40°C
–40°C
70
60
50
40
30
20
10
0
–45
–50
–55
–60
–65
–70
–75
–80
–40°C
5
15
25
35
45
55
65
75
85
95 105 115
3300
3400
3500
3600
3700
3800
INTERMODULATION FREQUENCY (MHz)
OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 164. Observation Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),
3500 MHz LO, 0 dB Attenuation, 240 MHz RF Bandwidth,
307.2 MSPS Sample Rate
Figure 161. Observation Receiver LO Leakage vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 240 MHz RF Bandwidth,
307.2 MSPS Sample Rate
Rev. 0 | Page 44 of 61
Data Sheet
AD9375
40
35
30
25
20
15
10
5
25
20
15
10
5
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
0
–5
–10
–15
0
0
3
6
9
12
15
18
0
10
20
30
40
50
60
70
80
90 100 110
OBSERVATION RECEIVER ATTENUATION (dB)
f1 OFFSET FREQUENCY (MHz)
Figure 165. Observation Receiver IIP3 vs. f1 Offset Frequency, 3600 MHz LO,
0 dB Attenuation, 240 MHz RF Bandwidth, f2 = 2f1 + 1 MHz,
307.2 MSPS Sample Rate
Figure 168. Observation Receiver Gain vs. Observation Receiver Attenuation,
3500 MHz LO, CW Signal 25 MHz Offset, 240 MHz RF Bandwidth,
De-Embedded to Receiver Port, 307.2 MSPS Sample Rate
40
–40
+110°C
+40°C
+110°C
+40°C
–40°C
35
30
25
20
15
10
5
–40°C
–50
–60
–70
–80
–90
–100
–110
0
5
15
25
35
45
55
65
75
85
95 105 115
0
3
6
9
12
15
18
INTERMODULATION FREQUENCY (MHz)
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 166. Observation Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1),
3500 MHz LO, 0 dB Attenuation, 240 MHz RF Bandwidth,
307.2 MSPS Sample Rate
Figure 169. Observation Receiver DC Offset vs. Observation Receiver
Attenuation, 3500 MHz LO, 240 MHz RF Bandwidth, 307.2 MSPS Sample Rate
0
0
+110°C
+110°C
+40°C
–40°C
–20
+40°C
–10
–20
–40°C
–30
–40
–50
–60
–70
–80
–90
–100
–40
–60
–80
–100
–120
0
3
6
9
12
15
18
0
18
3
6
9
12
15
OBSERVATION RECEIVER ATTENUATION (dB)
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 167. Observation Receiver Image vs. Observation Receiver
Attenuation, 3500 MHz LO, CW Signal 25 MHz Offset,
240 MHz RF Bandwidth, BTC Active, 307.2 MSPS Sample Rate
Figure 170. Observation Receiver HD2 vs. Observation Receiver Attenuation,
3500 MHz LO, CW Signal 25 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
240 MHz RF Bandwidth, 307.2 MSPS Sample Rate
Rev. 0 | Page 45 of 61
AD9375
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
90
80
70
60
50
40
30
20
10
0
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–100
0
3
6
9
12
15
18
2
6
10
14
18
OBSERVATION RECEIVER ATTENUATION (dB)
INTERMODULATION FREQUENCY (MHz)
Figure 171. Observation Receiver HD3 vs. Observation Receiver Attenuation,
3500 MHz LO, CW Signal 25 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
240 MHz RF Bandwidth, 307.2 MSPS Sample Rate
Figure 174. Sniffer Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),
3500 MHz LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
–40
20
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
15
–50
–60
10
5
–70
–80
–90
0
–100
–110
–120
–5
–10
3300
3400
3500
3600
3700
3800
0
2
4
6
8
10
12
SNIFFER RECEIVER LO FREQUENCY (MHz)
INTERMODULATION FREQUENCY (MHz)
Figure 172. Sniffer Receiver LO Leakage vs. Sniffer Receiver LO Frequency,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
Figure 175. Sniffer Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1),
3500 MHz LO, 0 dB Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
20
0
+110°C
+110°C
+40°C
+40°C
18
–10
–40°C
–40°C
16
14
12
10
8
–20
–30
–40
–50
–60
–70
–80
–90
–100
6
4
2
0
3300
3400
3500
3600
3700
3800
0
5
10
15
20
25
30
35
40
45
50
SNIFFER RECEIVER LO FREQUENCY (MHz)
SNIFFER RECEIVER ATTENUATION (dB)
Figure 173. Sniffer Receiver Noise Figure vs. Sniffer Receiver LO Frequency,
0 dB Receiver Attenuation, 20 MHz RF Bandwidth, 38.4 MSPS Sample Rate,
10 MHz Integration Bandwidth
Figure 176. Sniffer Receiver Image vs. Sniffer Receiver Attenuation,
3500 MHz LO, CW Signal 5 MHz Offset, 20 MHz RF Bandwidth,
38.4 MSPS Sample Rate
Rev. 0 | Page 46 of 61
Data Sheet
AD9375
–40
–50
–60
–70
–80
–90
–100
0
–5
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–10
–15
–20
–25
–30
–35
–40
–45
–110
0
5
10
15
20
–70
–65
–60
–55
–50
–45
–40
–35
–30
SNIFFER RECEIVER ATTENUATION (dB)
SNIFFER RECEIVER INPUT POWER (dBm)
Figure 177. Sniffer Receiver DC Offset vs. Sniffer Receiver Attenuation,
3500 MHz LO, CW Signal 5 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
Figure 180. Sniffer Receiver EVM vs. Sniffer Receiver Input Power,
3600 MHz LO, 20 MHz RF Bandwidth, LTE 20 MHz Uplink Centered at DC,
BTC Active, 38.4 MSPS Sample Rate
0
35
+110°C
+110°C
+40°C
–40°C
+40°C
–10
–40°C
25
–20
–30
–40
–50
–60
–70
–80
–90
–100
15
5
–5
–15
–25
–35
0
5
10
15
20
25
30
35
40
45
50
55
0
5
10
15
20
SNIFFER RECEIVER ATTENUATION (dB)
SNIFFER RECEIVER ATTENUATION (dB)
Figure 178. Sniffer Receiver HD2 vs. Sniffer Receiver Attenuation,
3500 MHz LO, CW Signal 5 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
Figure 181. Sniffer Receiver Gain vs. Sniffer Receiver Attenuation,
3600 MHz LO, CW Signal 5 MHz Offset, 20 MHz RF Bandwidth,
De-Embedded to Receiver Port, 38.4 MSPS Sample Rate
0
+110°C
+40°C
–10
–40°C
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
SNIFFER RECEIVER ATTENUATION (dB)
Figure 179. Sniffer Receiver HD3 vs. Sniffer Receiver Attenuation,
3500 MHz LO, CW Signal 5 MHz Offset, −35 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
20 MHz RF Bandwidth, 38.4 MSPS Sample Rate
Rev. 0 | Page 47 of 61
AD9375
Data Sheet
5.5 GHz BAND
–30
100
90
80
70
60
50
40
30
20
10
0
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–40
–50
–60
–70
–80
–90
–100
5300
5400
5500
5600
5700
5800
5900
0
10
20
30
40
50
60
RECEIVER LO FREQUENCY (MHz)
f1 OFFSET FREQUENCY (MHz)
Figure 182. Receiver Local Oscillator (LO) Leakage vs. Receiver LO Frequency,
0 dB Receiver Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Figure 185. Receiver IIP2 vs. f1 Offset Frequency, 5600 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, f2 = f1 + 1 MHz,
122.88 MSPS Sample Rate
45
100
90
80
70
60
50
40
+110°C
+40°C
–40°C
35
30
25
20
15
10
5
40
30
20
10
0
f2
f2
f2
f2
f2
f2
+
+
+
–
–
–
f1, +110°C
f1, +40°C
f1, –40°C
f1, +110°C
f1, +40°C
f1, –40°C
0
0
3
6
9
12
15
15
20
25
30
35
40
45
RECEIVER ATTENUATION (dB)
INTERMODULATION FREQUENCY (MHz)
Figure 183. Receiver Noise Figure vs. Receiver Attenuation, 5600 MHz LO,
100 MHz Bandwidth, 122.88 MSPS Sample Rate, 50 MHz Integration
Bandwidth (Includes 1.2 dB Matching Circuit Loss)
Figure 186. Receiver IIP2 vs. Intermodulation Frequency, 5600 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
30
25
20
15
40
+110°C
+40°C
–40°C
35
30
25
20
15
10
5
10
5
+110°C
+40°C
–40°C
0
5300
5400
5500
5600
5700
5800
5900
0
0
10
20
30
40
50
60
RECEIVER LO FREQUENCY (MHz)
f1 OFFSET FREQUENCY (MHz)
Figure 184. Receiver Noise Figure vs. Receiver LO Frequency, 0 dB Receiver
Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate, 50 MHz
Integration Bandwidth (Includes 1.2 dB Matching Circuit Loss)
Figure 187. Receiver IIP3 vs. f1 Offset Frequency, 5600 MHz LO, 0 dB Attenuation,
100 MHz RF Bandwidth, f2 = 2 f1 + 2 MHz, 122.88 MSPS Sample Rate
Rev. 0 | Page 48 of 61
Data Sheet
AD9375
40
35
30
25
20
15
10
5
–40
–50
+110°C
+40°C
–40°C
–60
–70
–80
+110°C
+40°C
–40°C
–90
–100
–110
0
10
15
20
25
30
35
0
5
10
15
20
25
30
INTERMODULATION FREQUENCY (MHz)
RECEIVER ATTENUATION (dB)
Figure 188. Receiver IIP3 vs. Intermodulation Frequency, 5600 MHz LO,
0 dB Attenuation, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Figure 191. Receiver DC Offset vs. Receiver Attenuation, 5850 MHz LO,
100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
–40
–40
–50
+110°C
+40°C
–40°C
–50
–60
+110°C
+40°C
–40°C
–60
–70
–80
–70
–80
–90
–90
–100
–110
–100
0
5
10
15
20
25
30
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
RECEIVER ATTENUATION (dB)
Figure 189. Receiver Image vs. Receiver Attenuation, 5600 MHz LO,
Continuous Wave (CW) Signal 10 MHz Offset, 100 MHz RF Bandwidth,
Background Tracking Calibration (BTC) Active, 122.88 MSPS Sample Rate
Figure 192. Receiver HD2 vs. Receiver Attenuation, 5600 MHz LO,
CW Signal 10 MHz Offset, −20 dBm at 0 dB Attenuation,
Input Power Increasing Decibel for Decibel with Attenuation,
100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
20
15
10
5
–40
–50
–60
–70
0
–80
–5
+110°C
+40°C
–90
+110°C
–10
–40°C
+40°C
–40°C
–100
–15
–20
–110
0
5
10
15
20
25
30
0
5
10
15
20
25
30
RECEIVER ATTENUATION (dB)
RECEIVER ATTENUATION (dB)
Figure 193. Receiver HD3 vs. Receiver Attenuation, 5600 MHz LO,
CW Signal 10 MHz Offset, −20 dBm at 0 dB Attenuation, Input Power
Increasing Decibel for Decibel with Attenuation,100 MHz RF Bandwidth,
122.88 MSPS Sample Rate
Figure 190. Receiver Gain vs. Receiver Attenuation, 5600 MHz LO,
CW Signal 10 MHz Offset, 100 MHz RF Bandwidth, 122.88 MSPS Sample Rate
Rev. 0 | Page 49 of 61
AD9375
Data Sheet
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
–5
+110°C
+40°C
–40°C
–10
–15
–20
–25
–30
–35
–40
–45
–55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
0
0
5
10
15
20
RECEIVER INPUT POWER (dBm)
RF ATTENUATION (dB)
Figure 194. Receiver Error Vector Magnitude (EVM) vs. Receiver Input Power,
5600 MHz LO, 100 MHz RF Bandwidth LTE, 20 MHz Uplink Centered at DC,
BTC Active, 122.88 MSPS Sample Rate
Figure 197. Transmitter Image vs. RF Attenuation, 75 MHz RF Bandwidth,
5600 MHz LO, 0 dB RF Attenuation, Transmitter Quadrature Error Correction
(QEC) Tracking Run with Two 20 MHz LTE Downlink Carriers, Then Image
Measured with CW 10 MHz Offset from LO, 3 dB Digital Backoff,
245.76 MSPS Sample Rate
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
5300
5400
5500
5600
5700
5800
5900
–40
–30
–20
–10
0
10
20
30
40
RECEIVER LO FREQUENCY (MHz)
DESIRED OFFSET FREQUENCY (MHz)
Figure 195. Rx2 to Rx1 Crosstalk vs. Receiver LO Frequency,
100 MHz RF Bandwidth, CW Tone 3 MHz Offset from LO
Figure 198. Transmitter Image vs. Desired Offset Frequency, 75 MHz RF
Bandwidth, 5600 MHz LO, 0 dB RF Attenuation, Transmitter QEC Tracking
Run with Two 20 MHz LTE Downlink Carriers, Then Image Measured with
CW Signal, 3 dB Digital Backoff, 245.76 MSPS Sample Rate
30
10
8
25
20
15
10
5
6
4
2
0
–2
+110°C
+40°C
–40°C
+110°C
–4
–6
+40°C
–40°C
–8
0
–40
–10
5300
–35
–30
–25
–20
–15
–10
–5
0
5400
5500
5600
5700
5800
5900
OUT-OF-BAND INTERFERER SIGNAL POWER (dBm)
RECEIVER LO FREQUENCY (MHz)
Figure 196. Receiver Noise Figure vs. Out-of-Band Interferer Signal Power,
5400 MHz LO, 5600 MHz CW Interferer, NF Integrated over 7 MHz to 10 MHz
Figure 199. Tx Output Power, Transmitter QEC, and External LO Leakage
Active, 5 MHz CW Offset Signal, 1 MHz Resolution Bandwidth,
245.76 MSPS Sample Rate
Rev. 0 | Page 50 of 61
Data Sheet
AD9375
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
+110°C
+40°C
–40°C
–100
0
5
10
15
20
5300
5400
5500
5600
5700
5800
5900
RF ATTENUATION (dB)
RECEIVER LO FREQUENCY (MHz)
Figure 200. Transmitter LO Leakage vs. RF Attenuation, 5600 MHz LO,
External Transmitter QEC, and LO Leakage Tracking Active, CW Signal
10 MHz Offset from LO, 6 dB Digital Backoff, 1 MHz Measurement Bandwidth
Figure 203. Tx2 to Rx2 Crosstalk vs. Receiver LO Frequency,
100 MHz Receiver RF Bandwidth, 75 MHz Transmitter RF Bandwidth,
CW Signal 3 MHz Offset from LO
–60
–65
–70
–75
–80
–85
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
5.9GHz, +110°C
5.9GHz, +40°C
5.9GHz, –40°C
5.6GHz, +110°C
5.6GHz, +40°C
5.6GHz, –40°C
5.3GHz, +110°C
5.3GHz, +40°C
5.3GHz, –40°C
–90
–95
–100
–40
–30
–20
–10
0
10
20
30
40
5300
5400
5500
5600
5700
5800
5900
OFFSET FREQUENCY (MHz)
TRANSMITTER LO FREQUENCY (MHz)
Figure 201. Transmitter LO Leakage vs. Offset Frequency,
External Transmitter QEC and LO Leakage Tracking Active,
6 dB Digital Backoff, 1 MHz Measurement Bandwidth
Figure 204. Tx2 to Tx1 Crosstalk vs. Transmitter LO Frequency,
75 MHz RF Bandwidth, CW Signal 3 MHz Offset from LO
0
–80
–10
–90
–100
–110
–120
–130
–140
–150
–160
–170
–180
+110°C
+40°C
–40°C
–20
–30
–40
–50
–60
–70
–80
–90
–100
5300
5400
5500
5600
5700
5800
5900
0
5
10
15
20
RECEIVER LO FREQUENCY (MHz)
RF ATTENUATION (dB)
Figure 202. Tx1 to Rx1 Crosstalk vs. Receiver LO Frequency, 100 MHz Receiver RF
Bandwidth, 75 MHz Transmitter RF Bandwidth, CW Signal 3 MHz Offset from LO
Figure 205. Transmitter Noise vs. RF Attenuation, 5600 MHz LO,
1 MHz Offset Frequency
Rev. 0 | Page 51 of 61
AD9375
Data Sheet
–40
–45
–50
–55
–60
–65
–70
–75
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
+110°C LOWER
+40°C LOWER
–40°C LOWER
+110°C UPPER
+40°C UPPER
–40°C UPPER
+110°C
+40°C
–40°C
–80
0
5
10
15
20
5300
5400
5500
5600
5700
5800
5900
RF ATTENUATION (dB)
TRANSMITTER LO FREQUENCY (MHz)
Figure 206. Tx Adjacent Channel Leakage Ratio vs. RF Attenuation,
5600 MHz LO, 75 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
Transmitter QEC and LO Leakage Tracking Active
Figure 209. Tx Integrated Phase Noise vs. Transmitter LO Frequency,
75 MHz RF Bandwidth, CW 10 MHz Offset from LO, 3 dB Digital Backoff
–40
–45
–50
–55
–60
30
+110°C
+40°C
–40°C
25
20
15
10
5
–65
–70
–75
–80
+110°C LOWER
+40°C LOWER
–40°C LOWER
+110°C UPPER
+40°C UPPER
–40°C UPPER
0
0
5
10
15
20
0
5
10
15
20
RF ATTENUATION (dB)
RF ATTENUATION (dB)
Figure 207. Tx Alternate Channel Leakage Ratio vs. RF Attenuation,
5600 MHz LO, 75 MHz RF Bandwidth, Four-Carrier W-CDMA Desired Signal,
2 dB Digital Backoff, Transmitter QEC and LO Leakage Tracking Active
Figure 210. Transmitter OIP3 vs. RF Attenuation, 5600 MHz LO,
75 MHz RF Bandwidth, f1 = 20 MHz, f2 = 21 MHz, 3 dB Digital Backoff,
245.76 MSPS Sample Rate
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–80
–90
–100
–110
–120
–130
–140
–150
100
1k
10k
100k
1M
10M
5750
5775
5800
5825
5850
5875
5900
5925
5950
OFFSET FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 208. LO Phase Noise vs. Offset Frequency, 3 dB Digital Backoff,
5850 MHz LO
Figure 211. Tx Output Power Spectrum, 3 dB Digital and 1 dB RF Backoff,
40 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,
LTE 10 MHz Signal, 5850 MHz LO, 1 MHz Resolution Bandwidth,
122.88 MSPS Sample Rate, Test Equipment Noise Floor De-Embedded
Rev. 0 | Page 52 of 61
Data Sheet
AD9375
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
+110°C
+40°C
–40°C
5350 5450 5550 5650 5750 5850 5950 6050 6150 6250 6350
0
5
10
15
20
FREQUENCY (MHz)
RF ATTENUATION (dB)
Figure 212. Tx Output Power Spectrum, 3 dB Digital and 1 dB RF Backoff,
40 MHz RF Bandwidth, Transmitter QEC, and Internal LO Leakage Active,
LTE 10 MHz Signal, 5850 MHz LO, 1 MHz Resolution Bandwidth,
122.88 MSPS Sample Rate, Expanded Frequency View, Test Equipment Noise
Floor De-Embedded
Figure 215. Transmitter HD3 vs. RF Attenuation, 5850 MHz LO,
5855 MHz CW Desired Signal, 75 MHz RF Bandwidth,
245.76 MSPS Sample Rate
–20
10
+110°C
+40°C
–40°C
–25
5
0
+110°C
+40°C
–40°C
–30
–35
–40
–45
–50
–5
–10
–15
–20
0
5
10
15
20
0
5
10
15
20
25
RF ATTENUATION (dB)
RF ATTENUATION (dB)
Figure 213. Transmitter EVM vs. RF Attenuation, 5600 MHz LO, Transmitter
LO Leakage, and Transmitter QEC Tracking Active, 75 MHz RF Bandwidth,
LTE 20 MHz Downlink Signal, 245.76 MSPS Sample Rate
Figure 216. Transmitter Output Power vs. RF Attenuation, 5850 MHz LO,
5855 MHz CW Desired Signal, 75 MHz RF Bandwidth,
245.76 MSPS Sample Rate
0
0.10
–10
0.08
0.06
0.04
0.02
0
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–20
–30
–40
–50
–60
–70
–80
–90
–100
–0.02
–0.04
–0.06
–0.08
–0.10
0
5
10
15
20
0
5
10
15
20
RF ATTENUATION (dB)
RF ATTENUATION (dB)
Figure 214. Transmitter HD2 vs. RF Attenuation, 5850 MHz LO, 5855 MHz
CW Desired Signal, 75 MHz RF Bandwidth, 245.76 MSPS Sample Rate
Figure 217. Tx Attenuation Step Error vs. RF Attenuation, 5850 MHz LO,
5855 MHz CW Desired Signal, 75 MHz RF Bandwidth, 245.76 MSPS Sample Rate
Rev. 0 | Page 53 of 61
AD9375
Data Sheet
0.5
0.4
80
70
60
50
40
30
20
10
0
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
+110°C
+40°C
–40°C
–100 –80 –60 –40 –20
0
20
40
60
80
100
0
10
20
30
40
50
60
70
80
90 100 110
FREQUENCY OFFSET FROM LO (MHz)
f1 OFFSET FREQUENCY (MHz)
Figure 218. Transmitter Frequency Response Deviation from Flatness vs.
Frequency Offset from LO, 5850 MHz LO, 200 MHz Synthesis Bandwidth,
6 dB Digital Backoff, 245.76 MSPS Sample Rate
Figure 221. Observation Receiver IIP2 vs. f1 Offset Frequency, 5600 MHz LO,
0 dB Attenuation, 200 MHz RF Bandwidth, f2 = f1 + 1 MHz,
245.76 MSPS Sample Rate
80
70
60
50
40
–40
–45
+110°C
+40°C
–50
–40°C
–55
–60
–65
–70
–75
–80
30
+110°C
20
+40°C
–40°C
10
0
10
20
30
40
50
60
70
80
90
100 110
5300
5400
5500
5600
5700
5800
5900
INTERMODULATION FREQUENCY (MHz)
OBSERVATION RECEIVER LO FREQUENCY (MHz)
Figure 219. Observation Receiver LO Leakage vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
Figure 222. Observation Receiver IIP2 vs. Intermodulation Frequency (f2 − f1),
5600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
40
35
30
25
20
30
25
20
15
+110°C
+40°C
–40°C
15
10
5
+110°C
+40°C
–40°C
10
5
0
5300
0
5400
5500
5600
5700
5800
5900
0
10
20
30
40
50
60
70
80
90 100 110
OBSERVATION RECEIVER LO FREQUENCY (MHz)
f1 OFFSET FREQUENCY (MHz)
Figure 223. Observation Receiver IIP3 vs. f1 Offset Frequency, 5600 MHz LO,
0 dB Attenuation, 200 MHz RF Bandwidth, f2 = 2 f1 + 1 MHz,
245.76 MSPS Sample Rate
Figure 220. Observation Receiver Noise Figure vs. Observation Receiver
LO Frequency, 0 dB Receiver Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate, 100 MHz Integration Bandwidth
Rev. 0 | Page 54 of 61
Data Sheet
AD9375
40
35
30
25
20
15
10
5
–40
–50
–60
–70
–80
–90
–10
–110
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
0
5
15
25
35
45
55
65
75
85
95 105 115
0
3
6
9
12
15
18
INTERMODULATION FREQUENCY (MHz)
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 224. Observation Receiver IIP3 vs. Intermodulation Frequency (f2 − 2f1),
5600 MHz LO, 0 dB Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
Figure 227. Observation Receiver DC Offset vs. Observation Receiver
Attenuation, 5850 MHz LO, CW Signal 30 MHz Offset, −15 dBm Input,
200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
3
6
9
12
15
18
0
3
6
9
12
15
18
OBSERVATION RECEIVER ATTENUATION (dB)
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 225. Observation Receiver Image vs. Observation Receiver
Attenuation, 5600 MHz LO, CW Signal 30 MHz Offset,
200 MHz RF Bandwidth, BTC Active, 245.76 MSPS Sample Rate
Figure 228. Observation Receiver HD2 vs. Observation Receiver Attenuation,
5600 MHz LO, CW Signal 30 MHz Offset, −15 dBm Input, Input Power
Increasing Decibel for Decibel with Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
25
0
20
15
10
5
+110°C
+40°C
–40°C
+110°C
+40°C
–40°C
–20
–40
–60
0
–80
–5
–10
–15
–100
–120
0
3
6
9
12
15
18
0
3
6
9
12
15
18
OBSERVATION RECEIVER ATTENUATION (dB)
OBSERVATION RECEIVER ATTENUATION (dB)
Figure 226. Observation Receiver Gain vs. Observation Receiver Attenuation,
5600 MHz LO, CW Signal 30 MHz Offset,
Figure 229. Observation Receiver HD3 vs. Observation Receiver Attenuation,
5600 MHz LO, CW Signal 30 MHz Offset, −15 dBm Input, Input Power
Increasing Decibel for Decibel with Attenuation, 200 MHz RF Bandwidth,
245.76 MSPS Sample Rate
200 MHz RF Bandwidth, 245.76 MSPS Sample Rate
Rev. 0 | Page 55 of 61
AD9375
Data Sheet
THEORY OF OPERATION
The AD9375 is a highly integrated RF transceiver that can be
configured for a wide range of applications. The device integrates
all the RF, mixed-signal, and digital blocks necessary to provide
transmit and receive functions in a single device. Programmability
allows the two receiver channels and two transmitter channels
to be used in TDD and FDD systems for 3G and 4G cellular
standards.
RECEIVER (Rx)
The AD9375 contains dual receiver channels. Each Rx channel
is a direct conversion system that contains a programmable
attenuator stage, followed by matched I and Q mixers that
downconvert received signals to baseband for digitization.
To achieve gain control, a programmed gain index map is
implemented. This gain map distributes attenuation among the
various Rx blocks for optimal performance at each power level.
In addition, support is available for both automatic and manual
gain control modes.
The observation receiver channel has two inputs for use in
monitoring the transmitter outputs. This channel has a wide
channel bandwidth that receives the entire transmit band and
feeds it back to the digital section for error correction purposes.
In addition, three sniffer receiver inputs can monitor different
radio frequency bands (one at a time). These channels share the
baseband ADC and digital processing with the two ORx inputs.
The receiver includes Σ-Δ ADCs and adjustable sample rates
that produce data streams from the received signals. The signals
can be conditioned further by a series of decimation filters and
a fully programmable 72-tap FIR filter with additional decimation
settings. The sample rate of each digital filter block is adjustable
by changing the decimation factors to produce the desired
output data rate.
The AD9375 contains four high speed serial interface links for
the transmit chain and four high speed serial interface links
shared by the Rx, ORx, and SnRx channels (JESD204B,
Subclass 1 compliant), providing a low pin count and reliable
data interface to a field-programmable gate array (FPGA) or
other custom integrated baseband solutions.
OBSERVATION RECEIVER (ORx)
The ORx operates in a similar manner to the main receivers.
Each input is differential and uses a dedicated mixer. The ORx
inputs share a baseband ADC and baseband section; therefore,
only one can be active at any time. The mixed signal and digital
section is identical in design and operation to the main receiver
channels. This channel can monitor the Tx channels and
implement error correction functions. It can also be used as a
general-purpose receiver.
The AD9375 also provides self calibration for dc offset and
quadrature error correction to maintain a high performance
level under varying temperatures and input signal conditions.
The device includes test modes that allow system designers to
debug designs during prototyping and optimize radio
configurations.
TRANSMITTER (Tx)
SNIFFER RECEIVER (SnRx)
The AD9375 employs a direct conversion transmitter
architecture consisting of two identical and independently
controlled channels that provide all the digital processing,
mixed-signal, and RF blocks necessary to implement a direct
conversion system. Both channels share a common frequency
synthesizer.
The sniffer receiver provides three differential inputs that can
monitor different frequency bands. Each input has a low noise
amplifier (LNA) that is multiplexed to feed a single mixer. The
output of this mixer stage is multiplexed with the ORx receiver
mixers to feed the same baseband section. The SnRx bandwidth
is limited to 20 MHz. This receiver can also be used as a general-
purpose receiver if the bandwidth and RF performance are
acceptable for a given application. The sniffer channel is also
limited to operation from 300 MHz to 4000 MHz. Performance
cannot be guaranteed for LO settings above 4000 MHz.
The digital data from the JESD204B lanes pass through a fully
programmable 96-tap FIR filter with optional interpolation.
The FIR output is sent to a series of conversion filters that
provide additional filtering and data rate interpolation prior to
reaching the DAC. Each DAC has an adjustable sample rate and
is linear up to full scale.
These receiver inputs also provide an LNA bypass mode that
removes the gain of the LNA when large signals are present.
Note that no requirements for the LNA bypass mode are included
in Table 1; performance specifications are only relative to the
scenario in which the LNA is enabled.
Once converted to baseband analog signals, the in-phase (I) and
quadrature (Q) signals are filtered to remove sampling artifacts,
and then the signals are fed to the upconversion mixers. At the
mixer stage, the I and Q signals are recombined and modulated
onto the carrier frequency for transmission to the output stage.
Each transmit chain provides a wide attenuation adjustment
range with fine granularity to help designers optimize SNR.
CLOCK INPUT
The AD9375 requires a differential clock connected to the
DEV_CLK_IN+/DEV_CLK_IN− pins. The frequency of the
clock input must be between 10 MHz and 320 MHz, and it must
have very low phase noise because this signal generates the RF
local oscillator and internal sampling clocks.
Rev. 0 | Page 56 of 61
Data Sheet
AD9375
SYNTHESIZERS
AUXILIARY CONVERTERS
RF PLL
Auxiliary ADC Inputs (AUXADC_x)
The AD9375 contains three fractional-N PLLs to generate the
RF LOs used by the transmitter, receiver, and observation
receiver. The PLL incorporates an internal VCO and loop filter
that require no external components. The internal VCO LDO
regulators eliminate the need for additional external power
supplies for the PLLs. These regulators only require an external
bypass capacitor for each supply.
The AD9375 contains an auxiliary ADC that is multiplexed to four
input pins (AUXADC_0 through AUXADC_3). This block can
monitor system voltages without adding additional components.
The auxiliary ADC is 12 bits with an input voltage range of 0.05 V
to VDDA_3P3 − 0.05 V. When enabled, the auxiliary ADC is
free running. Software reads of the output value provide the last
value latched at the ADC output.
Clock PLL
Auxiliary DACs (AUXDAC_x)
The AD9375 contains a PLL synthesizer that generates all of the
baseband related clock signals and SERDES clocks. This PLL is
programmed based on the data rate and sample rate requirements
of the system.
The AD9375 contains 10 identical auxiliary DACs (AUXDAC_0 to
AUXDAC_9) that can supply bias voltages, analog control voltages,
or other system functionality. The inputs of these auxiliary DACs
(AUXDAC_0 to AUXDAC_9) are multiplexed with the GPIO_
3P3_x pins according to Table 7. The auxiliary DACs are 10 bits,
have an output voltage range of approximately 0.5 V to 3.0 V,
and have a current drive of 10 mA.
SERIAL PERIPHERAL INTERFACE (SPI)
The AD9375 uses a SPI to communicate with the baseband
processor (BBP). This interface can be configured as a 4-wire
interface with dedicated receive and transmit ports, or it can be
configured as a 3-wire interface with a bidirectional data
communications port. This bus allows the BBP to set all device
control parameters using a simple address data serial bus protocol.
Table 7. AUXDAC Input Pin Assignments
AUXDAC_x Output
AUXDAC_0
AUXDAC_1
AUXDAC_2
AUXDAC_3
AUXDAC_4
AUXDAC_5
AUXDAC_6
AUXDAC_7
AUXDAC_8
AUXDAC_9
GPIO_3P3_x Pin
GPIO_3P3_9
GPIO_3P3_7
GPIO_3P3_6
GPIO_3P3_10
GPIO_3P3_0
GPIO_3P3_1
GPIO_3P3_3
GPIO_3P3_4
GPIO_3P3_5
GPIO_3P3_8
Write commands follow a 24-bit format. The first bit sets the
bus direction of the bus transfer. The next 15 bits set the address
where data is written. The final eight bits are the data being
transferred to the specific register address.
Read commands follow a similar format with the exception that
the first 16 bits are transferred on the SDIO pin, and the final
eight bits are read from the AD9375, either on the SDO pin in
4-wire mode or on the SDIO pin in 3-wire mode.
GPIO_x AND GPIO_3P3_x PINS
The AD9375 general-purpose input/output signals referenced
to the VDD_IF supply can be configured for numerous functions.
Some of these pins, when configured as outputs, are used by the
BBP as real-time signals to provide a number of internal settings
and measurements. This configuration allows the BBP to monitor
receiver performance in different situations. A pointer register
selects the information that is output to these pins. Signals used
for manual gain mode, calibration flags, state machine states,
and various receiver parameters are among the outputs that
can be monitored on these pins. In addition, certain pins can
be configured as inputs and used in various functions such as
setting the receiver gain in real time.
The GPIO_3P3_x pins are referenced to the VDDA_3P3 supply.
These pins can provide control signals to other components
such as voltage gain amplifiers (VGAs) or attenuators in the RF
section that typically use a higher reference voltage.
Rev. 0 | Page 57 of 61
AD9375
Data Sheet
JESD204B DATA INTERFACE
POWER SUPPLY SEQUENCE
The digital data interface for the AD9375 uses JEDEC Standard
JESD204B Subclass 1. The serial interface operates at speeds of
up to 6144 Mbps. The benefits of the JESD204B interface
include a reduction in required board area for data interface
routing and smaller package options due to the need for fewer
pins. Digital filtering is included in all receiver and transmitter
paths to provide proper signal conditioning and sampling rates
to meet the JESD204B data requirements. Examples of the
digital filtering configurations for the Tx and Rx paths are
shown in Figure 230 and Figure 231, respectively.
The AD9375 requires a specific power-up sequence to avoid
undesired power-up currents. The optimal power-on sequence
starts the process by powering up the VDIG and the VDDA_1P3
(analog) supplies simultaneously. If they cannot power up
simultaneously, the VDIG supply must power up first. The
VDDA_3P3, VDDA_1P8, and JESD_VTT_DES supplies must
then power up after the VDIG and VDDA_1P3 supplies. Note
that the VDD_IF supply can power up at any time. It is also
RESET
recommended to toggle the
signal after power has
stabilized prior to configuration. Follow the reverse order of
the power-up sequence to power down.
Table 8. Example Rx/Tx Interface Rates (Two Rx/Two Tx Channels, Maximum JESD204B Lane Rates)
Tx/Tx Synthesis/
Rx Bandwidth (MHz)
Tx Input
Rate (MSPS) Rate (MSPS) (Mbps), Two Tx/Two Rx
Rx Output
JESD204B Lane Rate
JESD204B (No.
of Lanes) Tx/Rx Reference Clock Options (MHz)
100/250/100
75/200/100
20/100/40
20/100/20
307.2
153.6
122.88
61.44
30.72
6144
4/2
4/2
4/2
4/1
122.88, 153.6, 245.76, 307.2
122.88, 245.76
122.88, 245.76
245.76
122.88
122.88
4915.2
2457.6
2457.6
122.88, 245.76
TRANSMITTER
HALF-BAND
FILTER 0
(DPD)
HB
TRANSMITTER
HALF-BAND
FILTER 2
TRANSMITTER
HALF-BAND
FILTER 1
QUADRATURE
ERROR
CORRECTION
DPD
ACTUATOR
DIGITAL
GAIN
TRANSMITTER FIR
(INTERPOLATION
1, 2, 4)
I/Q DAC
JESD204B
Figure 230. Example Tx Data Path Filter Implementation
DEC5
RECEIVER
HALF-BAND
FILTER 3
RECEIVER
HALF-BAND
FILTER 2
RECEIVER
HALF-BAND
FILTER 1
RECEIVER FIR
(DECIMATION
1, 2, 4)
QEC
FILTER
DIGITAL
GAIN
DC
CORRECTION
JESD204B
ADC
Figure 231. Data Rx Data Path Filter Implementation
Rev. 0 | Page 58 of 61
Data Sheet
AD9375
20
10
DIGITAL PREDISTORTION (DPD)
DPD
NO DPD
This device provides a fully integrated DPD function that
linearizes the output of the power amplifier (PA) of the transmit
system by altering the digital waveform to compensate for
nonlinearities in the PA response. Both the DPD actuator and
coefficient calculation engine are integrated. This functionality
uses the ORx channel to monitor the output of the PA and
calculates the appropriate predistortion to linearize the output.
The integrated DPD capability allows the system to drive the PA
closer to saturation, enabling a higher efficiency PA while
maintaining linearity. The DPD is optimized for small cell PAs
with rms output powers in the 250 mW to 10 W range and for a
maximum occupied signal bandwidth of 40 MHz. The
additional power consumed by the DPD block when enabled is
less than 100 mW.
0
–10
–20
–30
–40
–50
–60
2540
2560
2580
2600
2620
2640
2660
FREQUENCY (MHz)
Figure 232. Output Spectrum for Normal Operation (Red) and with DPD
Activated (Blue) for a 20 MHz LTE Signal
20
Performance enhancement is shown in Figure 232 for a 20 MHz
LTE signal and in Figure 233 for a 40 MHz LTE output. In both
cases, a Band 7 Skyworks SKY66297 high efficiency PA is used
to demonstrate the adjacent channel level reduction (ACLR)
improvement for a particular device. Table 9 and Table 10 show
the details of ACLR improvement that are achieved for these two
scenarios when DPD is activated. Note that the magnitude of
improvement in ACLR is heavily PA dependent and generally
degrades as signal bandwidth increases.
DPD
NO DPD
10
0
–10
–20
–30
–40
–50
–60
2500
2525
2550
2575
2600
2625
2650
2675
2700
FREQUENCY (MHz)
Figure 233. Output Spectrum for Normal Operation (Red) and with DPD
Activated (Blue) for a 40 MHz LTE Output
Table 9. ACLR Comparison With and Without DPD for a 20 MHz LTE Waveform
20 MHz Offset (dBc)
40 MHz Offset (dBc)
60 MHz Offset (dBc)
Lower Upper
Mode1
Lower
Upper
Lower
−51.71
−52.63
Upper
−51.16
−56.57
Normal Operation
DPD Activated
−32.15
−50.89
−34.18
−51.90
−59.29
−57.23
−58.99
−59.49
1 Waveform is 10 ms (full-frame) LTE evolved universal terrestrial radio access (E-UTRA) Test Model 1.1 (E-TM 1.1) at 7.5 dB peak to average ratio (PAR), with crest factor
reduction (CFR), 28 dBm output, and 18.02 MHz occupied bandwidth.
Table 10. ACLR Comparison With and Without DPD for a 40 MHz LTE Waveform
20 MHz Offset (dBc)
40 MHz Offset (dBc)
60 MHz Offset (dBc)
Lower Upper
Mode1
Lower
Upper
Lower
Upper
Normal Operation
DPD Activated
−29.74
−47.42
−33.69
−48.22
−37.45
−49.84
−41.65
−49.62
−48.31
−52.06
−47.95
−54.38
1 Waveform is 10 ms (full frame) LTE E-UTRA Test Model 1.1 (E-TM 1.1) at 7.5 dB PAR (with CFR), 27 dBm output, and 36.04 MHz occupied bandwidth.
Rev. 0 | Page 59 of 61
AD9375
Data Sheet
Table 12. JTAG Modes
JTAG BOUNDARY SCAN
Test Pin Level
GPIO_0 to GPIO_3 Description
The AD9375 provides support for a JTAG boundary scan. Five
dual-function pins are associated with the JTAG interface.
These pins, listed in Table 11, are used to access the on-chip test
access port. To enable the JTAG functionality, set the GPIO_0
through GPIO_3 pins according to Table 12 depending on how the
desired JESD204B sync pin (that is, SYNCINB0+, SYNCINB0−,
SYNCINB1+, SYNCINB1−, SYNCOUTB0+, or SYNCOUTB0−)
is configured in the software (LVDS or CMOS mode). Pull the
TEST pin high to enable the JTAG mode.
0
1
XXXX1
1001
Normal operation
JTAG mode with LVDS
JESD204B sync signals
JTAG mode with CMOS
JESD204B sync signals
1
1011
1 X means don’t care.
Table 11. Dual-Function Boundary Scan Test Pins
Mnemonic JTAG Mnemonic Description
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_18
TRST
TDO
TDI
TMS
TCK
Test access port reset
Test data output
Test data input
Test access port mode select
Test clock
Rev. 0 | Page 60 of 61
Data Sheet
AD9375
OUTLINE DIMENSIONS
12.10
12.00 SQ
11.90
A1 BALL
PAD CORNER
A1 BALL
CORNER
14 13 12 11 10 9
8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
PIN A1
INDICATOR
10.40 SQ
7.755 REF
K
L
0.80
M
N
P
TOP VIEW
BOTTOM VIEW
0.80 REF
8.165 REF
DETAIL A
1.27
1.18
1.09
0.91
0.84
0.77
DETAIL A
0.39
0.34
0.29
0.44 REF
0.50
0.45
0.40
SEATING
PLANE
COPLANARITY
0.12
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.
Figure 234. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-196-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range2
Package Description
Package Option
AD9375BBCZ
AD9375BBCZ-REEL
ADRV9375-N/PCBZ
−40°C to +85°C
−40°C to +85°C
196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board, 2600 MHz Matching Circuits
BC-196-12
BC-196-12
1 Z = RoHS-Compliant Part.
2 See the Thermal Resistance section.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15657-0-3/17(0)
Rev. 0 | Page 61 of 61
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