AD9432BSQ-105 [ADI]
12-Bit, 80 MSPS/105 MSPS A/D Converter; 12位， 80 MSPS / 105 MSPS A / D转换器
| 型号： | AD9432BSQ-105 |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 80 MSPS/105 MSPS A/D Converter |
| 文件： | 总20页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 80 MSPS/105 MSPS
A/D Converter
a
AD9432
FEATURES
FUNCTIONAL BLOCK DIAGRAM
On-Chip Reference and Track/Hold
On-Chip Input Buffer
V
V
DD
CC
850 mW Typical Power Dissipation at 105 MSPS
500 MHz Analog Bandwidth
12
12
AIN
PIPELINE
ADC
BUF
T/H
D11–D0
OR
OUTPUT
AIN
SNR = 67 dB @ 49 MHz AIN at 105 MSPS
SFDR = 80 dB @ 49 MHz AIN at 105 MSPS
2.0 V p-p Differential Analog Input Range
Single 5.0 V Supply Operation
3.3 V CMOS/TTL Outputs
STAGING
ENCODE
REF
TIMING
ENCODE
AD9432
VREFIN
GND VREFOUT
Two’s Complement Output Format
APPLICATIONS
Communications
Basestations and ‘Zero-IF’ Subsystems
Wireless Local Loop (WLL)
Local Multipoint Distribution Service (LMDS)
HDTV Broadcast Cameras and Film Scanners
GENERAL INTRODUCTION
external reference or driver components are required for many
applications. The digital outputs are TTL/CMOS compatible
and a separate output power supply pin supports interfacing
with 3.3 V logic. The encode input supports either differential
or single-ended and is TTL/CMOS-compatible.
The AD9432 is a 12-bit monolithic sampling analog-to-digital
converter with an on-chip track-and-hold circuit and is optimized
for high-speed conversion and ease of use. The product operates
at a 105 MSPS conversion rate with outstanding dynamic per-
formance over its full operating range.
Fabricated on an advanced BiCMOS process, the AD9432 is
available in a 52-lead plastic quad flatpack package (LQFP)
specified over the industrial temperature range (–40°C to +85°C).
The ADC requires only a single 5.0 V power supply and a
105 MHz encode clock for full-performance operation. No
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(VDD = 3.3 V, VCC = 5.0 V; external reference; differential encode input, unless
AD9432–SPECIFICATIONS otherwise noted.)
Test
Level
AD9432BST/BSQ-80
AD9432BST/BSQ-105
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
12
12
Bits
DC ACCURACY
Differential Nonlinearity
25°C
Full
25°C
Full
Full
25°C
Full
I
VI
I
VI
VI
I
–0.75
–1.0
–1.0
–1.5
0.25 +0.75
–0.75
–1.0
–1.0
–1.5
0.25 +0.75
LSB
LSB
LSB
LSB
0.5
0.5
1.0
+1.0
+1.0
+1.5
0.5
0.5
1.0
+1.0
+1.0
+1.5
Integral Nonlinearity
No Missing Codes
Gain Error1
Guaranteed
+2
Guaranteed
+2
–5
+7
–5
+7
% FS
ppm/°C
Gain Tempco1
V
150
150
ANALOG INPUT
Input Voltage Range (AIN–AIN)
Common-Mode Voltage
Input Offset Voltage
Input Resistance
Input Capacitance
Full
Full
Full
Full
25°C
25°C
V
V
VI
VI
V
1.0
3.0
0
3
4
1.0
3.0
0
3
4
V
V
mV
kΩ
pF
MHz
–5
2
+5
4
–5
2
+5
4
Analog Bandwidth, Full Power
V
500
500
ANALOG REFERENCE
Output Voltage
Tempco
Full
Full
Full
VI
V
VI
2.4
80
2.5
50
15
2.6
50
2.4
2.5
50
15
2.6
50
V
ppm/°C
µΑ
Input Bias Current
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulsewidth High (tEH
Encode Pulsewidth Low (tEL
Aperture Delay (tA)
Full
Full
25°C
25°C
25°C
25°C
Full
Full
Full
Full
VI
IV
IV
IV
V
105
MSPS
MSPS
ns
ns
ns
ps rms
ns
ns
ns
ns
1
1
)
)
4.0
4.0
6.2
6.2
2.0
0.25
5.3
5.5
2.1
1.9
2
4.0
4.0
4.8
4.8
2.0
0.25
5.3
5.5
2.1
1.9
2
Aperture Uncertainty (Jitter)
V
Output Valid Time (tV)2
VI
VI
V
V
V
V
IV
3.0
3.0
2
Output Propagation Delay (tPD
Output Rise Time (tR)2
Output Fall Time (tF)
Out-of-Range Recovery Time
Transient Response Time
Latency
)
8.0
8.0
25°C
25°C
Full
ns
ns
Cycles
2
10
2
10
DIGITAL INPUTS
Encode Input Common Mode
Differential Input (ENC–ENC)
Single-Ended
Full
Full
V
V
1.6
750
1.6
750
V
mV
Logic “1” Voltage
Logic “0” Voltage
Input Resistance
Full
Full
Full
25°C
IV
IV
VI
V
2.0
3
2.0
3
V
V
kΩ
pF
0.8
8
0.8
8
5
4.5
5
4.5
Input Capacitance
DIGITAL OUTPUTS
Logic “1” Voltage (VDD = 3.3 V)
Logic “0” Voltage (VDD = 3.3 V)
Output Coding
Full
Full
VI
VI
VDD – 0.05
VDD – 0.05
V
V
0.05
0.05
Two’s Complement
Two’s Complement
POWER SUPPLY
Power Dissipation3
Power Supply Rejection Ratio (PSRR) 25°C
IVCC
IVDD
Full
VI
I
VI
VI
790
+0.5
158
9.5
1000
+5
200
12.2
850
+0.5
170
12.5
1100
mW
mV/V
mA
–5
–5
+5
220
16
Full
Full
mA
–2–
REV. E
AD9432
Test
Level
AD9432BST/BSQ-80
AD9432BST/BSQ-105
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE4
Signal-to-Noise Ratio (SNR)
(Without Harmonics)
f
IN = 10.3 MHz
25°C
25°C
25°C
25°C
I
I
I
V
65.5
65
67.5
67.2
67.0
66.1
65.5
64
67.5
67.2
67.0
66.1
dB
dB
dB
dB
fIN = 40 MHz
f
f
IN = 49 MHz
IN = 70 MHz
Signal-to-Noise Ratio (SINAD)
(With Harmonics)
fIN = 10.3 MHz
25°C
25°C
25°C
25°C
I
I
I
V
65
64.5
67.2
66.9
66.7
65.8
65
63
67.2
66.9
66.7
65.8
dB
dB
dB
dB
fIN = 40 MHz
f
f
IN = 49 MHz
IN = 70 MHz
Effective Number of Bits
fIN = 10 MHz
25°C
25°C
25°C
25°C
V
V
V
V
11.0
10.9
10.9
10.7
11.0
10.9
10.9
10.7
Bits
Bits
Bits
Bits
f
IN = 40 MHz
fIN = 49 MHz
IN = 70 MHz
f
Second and Third Harmonic Distortion
fIN = 10 MHz
25°C
25°C
25°C
25°C
I
I
I
V
–75
–73
–85
–85
–83
–80
–75
–72
–85
–83
–80
–78
dBc
dBc
dBc
dBc
f
f
IN = 40 MHz
IN = 49 MHz
fIN = 70 MHz
Worst Harmonic or Spur
(Excluding Second and Third)
fIN = 10 MHz
25°C
25°C
25°C
25°C
I
I
I
V
–80
–80
–90
–90
–90
–90
–80
–80
–90
–90
–90
–90
dBc
dBc
dBc
dBc
f
f
IN = 40 MHz
IN = 49 MHz
fIN = 70 MHz
Two-Tone Intermod Distortion (IMD)
f
IN1 = 29.3 MHz; fIN2 = 30.3 MHz
25°C
25°C
V
V
–75
–66
–75
–66
dBc
dBc
fIN1 = 70.3 MHz; fIN2 = 71.3 MHz
NOTES
1Gain error and gain temperature coefficients are based on the ADC only (with a fixed 2.5 V external reference and a 2 V p-p differential analog input).
2tV and tPD are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is
not to exceed an ac load of 10 pF or a dc current of 40 µA. Rise and fall times measured from 10% to 90%.
3Power dissipation measured with encode at rated speed and a dc analog input. (Outputs Static, IVDD = 0.)
4SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 2 V full-scale input range.
Specifications subject to change without notice.
REV. E
–3–
AD9432
ABSOLUTE MAXIMUM RATINGS*
THERMAL CHARACTERISTICS
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
VREFIN . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C
52-Lead Plastic LQFP (ST-52)
JA = 50°C/W, No Airflow
52-lead PowerQuad® 4 LQFP (SQ-52)
JA = 25°C/W, Soldered Exposed Heat Sink, No Airflow
JA = 33°C/W, Unsoldered Exposed Heat Sink, No Airflow
JC = 2°C/W, Bottom of package (Exposed Heat Sink)
Simulated Typical performance for 4-layer JEDEC board,
horizontal orientation.
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Ranges
Package
Descriptions
Package
Option
Model
AD9432BSQ –40°C to +85°C 52-Lead Thermally
SQ-52
-80, -105
Enhanced Plastic
Quad Flatpack
EXPLANATION OF TEST LEVELS
Test Level
AD9432BST –40°C to +85°C 52-Lead Plastic Quad ST-52
-80, -105
AD9432/PCB 25°C
Flatpack (LQFP)
Evaluation Board
I
100% production tested.
II 100% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V
Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9432 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PowerQuad is a registered trademark of AMkor Technology, Inc.
REV. E
–4–
AD9432
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
GND
39 GND
38 GND
PIN 1
IDENTIFIER
V
CC
3
37
36
35
34
33
32
31
30
29
28
27
V
V
GND
GND
CC
CC
4
5
V
GND
GND
GND
CC
6
V
CC
AD9432
TOP VIEW
(Not to Scale)
7
ENCODE
ENCODE
GND
V
8
DD
9
DGND
D0 (LSB)
D1
10
11
12
13
V
CC
GND
D2
DGND
V
D3
DD
14 15 16 17 18 19 20 21 22 23 24 25 26
PIN FUNCTION DESCRIPTIONS
Pin Number (AD9432BST)
Mnemonic
Function
1, 3, 4, 9, 11, 33, 34, 35, 38, 39, 40, 43, 48, 51 GND
Analog Ground
2, 5, 6, 10, 36, 37, 42, 44, 47, 52
VCC
Analog Supply (5 V)
7
8
14
ENCODE
ENCODE
OR
Encode Clock for ADC–Complementary
Encode Clock for ADC–True (ADC samples on rising edge of ENCODE)
Out of Range Output
15–20, 25–30
D11–D6, D5–D0 Digital Output
12, 21, 24, 31
13, 22, 23, 32
DGND
VDD
DNC
Digital Output Ground
Digital Output Power Supply (2.7 V to 3.6 V)
Do Not Connect
41
45
46
49
50
VREFIN
VREFOUT
AIN
Reference Input for ADC (2.5 V Typical); Bypass with 0.1 µF to Ground.
Internal Reference Output (2.5 V Typical)
Analog Input–True
AIN
Analog Input–Complementary
DEFINITION OF SPECIFICATIONS
Analog Bandwidth (Small Signal)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Aperture Delay
The delay between a differential crossing of ENCODE and
ENCODE and the instant at which the analog input is sampled.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Power Supply Rejection Ratio
Differential Nonlinearity
The deviation of any code from an ideal 1 LSB step.
The ratio of a change in input offset voltage to a change in
power supply voltage.
Encode Pulsewidth/Duty Cycle
Signal-to-Noise Plus Distortion (SINAD)
Pulsewidth high is the minimum amount of time that the ENCODE
pulse should be left in Logic “1” state to achieve rated performance;
pulsewidth low is the minimum time ENCODE pulse should be left
in low state. At a given clock rate, these specs define an acceptable
Encode duty cycle.
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, including harmonics but excluding dc.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
REV. E
–5–
AD9432
Spurious-Free Dynamic Range (SFDR)
Two-Tone SFDR
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious compo-
nent may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
Worst Harmonic
The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component, reported in dBc.
SAMPLE N
SAMPLE N+10
SAMPLE N+11
SAMPLE N–1
AIN
SAMPLE N+1
tA
SAMPLE N+9
tEH
tEL
1/fS
ENCODE
ENCODE
tPD
tV
DATA N–11
DATA N–10
N–9
N–2
DATA N–1
DATA N
DATA N+1
D11–D0
Figure 1. Timing Diagram
V
CC
V
CC
17k⍀
8k⍀
17k⍀
8k⍀
ENCODE
ENCODE
VREFIN
100⍀
100⍀
Figure 2. Equivalent Voltage Reference Input Circuit
Figure 4. Equivalent Encode Input Circuit
V
CC
V
DD
Q1
NPN
DIGITAL
OUTPUT
VREFOUT
V
OUTPUT
REF
DIGITAL OUTPUT
Figure 3. Equivalent Voltage Reference Output Circuit
Figure 5. Equivalent Digital Output Circuit
V
CC
5k⍀
7k⍀
5k⍀
AIN
AIN
7k⍀
ANALOG INPUT
Figure 6. Equivalent Analog Input Circuit
REV. E
–6–
Typical Performance Characteristics–AD9432
90
85
70
AIN = 10.3MHz
SFDR
65
80
75
70
65
60
60
55
50
SNR
SINAD
250
0
20
40
60
80
100
120
140
160
0
50
100
150
200
AIN INPUT FREQUENCY – MHz (–0.5dBFS)
ENCODE – MSPS
TPC 1. SNR/SINAD/SFDR vs. fS: fIN = 10.3 MHz
TPC 4. SNR vs. AIN Input Frequency,
Encode = 105 MSPS
100
90
–50
AIN = 10.3MHz
ENCODE = 105MSPS
–55
–60
–65
–70
–75
–80
80
2nd or 3rd (–6.0dBFS)
70
60
50
–85
3rd
–90
2nd or 3rd (–0.5dBFS)
2nd or 3rd (–3.0dBFS)
2nd
–95
40
–100
0
20
40
60
80
100 120 140 160 180 200
0
20
40
60
80
100
120
140
160
ANALOG INPUT FREQUENCY – MHz
ENCODE – MSPS
TPC 2. Harmonics vs. fS: fIN = 10.3 MHz
TPC 5. Harmonics vs. fIN: fS = 105 MSPS
100
90
70
65
60
55
50
ENCODE = 105MSPS
ENCODE = 105MSPS
WORST OTHER (–0.5dBFS)
80
WORST OTHER (–6.0dBFS)
WORST OTHER (–3.0dBFS)
SINAD (–3.0dBFS)
SINAD (–6.0dBFS)
70
SINAD (–0.5dBFS)
60
50
40
45
40
200
0
20
40
60
80
100 120 140 160 180
0
20
40
60
80
100 120 140 160 180 200
ANALOG INPUT FREQUENCY – MHz
ANALOG INPUT FREQUENCY – MHz
TPC 3. SINAD vs. fIN: fS = 105 MSPS
TPC 6. Worst-Case Spur (Other than Second and
Third) vs. fIN: fS = 105 MSPS
REV. E
–7–
AD9432
0
–10
–20
–30
–40
–50
–60
–70
0
ENCODE = 105MSPS
AIN = 50.3MHz (–0.46dBFS)
SNR = 67.0dB
SINAD = 66.7dB
SFDR = –80dBc
ENCODE = 105MSPS
AIN = 10.3MHz (–0.53dBFS)
SNR = 67.32dB
–10
–20
–30
SINAD = 67.07dB
SFDR = –85dBc
–40
–50
–60
–70
–80
–90
–80
–90
–100
–100
–110
–120
–110
–120
SAMPLES
SAMPLES
TPC 10. Spectrum: fS = 105 MSPS, fIN = 50.3 MHz
TPC 7. Spectrum: fS = 105 MSPS, fIN = 10.3 MHz
0
0
ENCODE = 105MSPS
AIN1 = 29.3MHz (–7dBFS)
–10
–10
AIN = 27.0MHz (–0.52dBFS)
AIN2 = 30.3MHz (–7dBFS)
SNR = 67.3dB
ENCODE = 105MSPS
–20
–30
–40
–50
–60
–70
–20
SINAD = 67.0dB
SFDR = –83.1dBc
–30
–40
–50
–60
–70
–80
–90
–80
–90
–100
–100
–110
–120
–110
–120
SAMPLES
SAMPLES
TPC 11. Two-Tone Spectrum, Wideband: fS =
105 MSPS, AIN1 = 29.3 MHz, AIN2 = 30.3 MHz
TPC 8. Spectrum: fS = 105 MSPS, fIN = 27 MHz
0
0
ENCODE = 105MSPS
AIN1 = 70.3MHz (–7dBFS)
–10
–10
AIN = 40.9MHz (–0.56dBFS)
AIN2 = 71.3MHz (–7dBFS)
SNR = 67.2dB
ENCODE = 105MSPS
–20
–30
–40
–50
–60
–70
–20
SINAD = 66.9dB
–30
–40
–50
–60
–70
SFDR = –80dBc
–80
–90
–80
–90
–100
–100
–110
–120
–110
–120
SAMPLES
SAMPLES
TPC 12. Two-Tone Spectrum, Wideband: fS =
105 MSPS, AIN1 = 70.3 MHz, AIN2 = 71.3 MHz
TPC 9. Spectrum: fS = 105 MSPS, fIN = 40.9 MHz
REV. E
–8–
AD9432
110
100
1.00
0.75
dBFS
90
80
70
60
50
40
30
20
10
0
0.50
ENCODE = 105MSPS
AIN = 50.3MHz
0.25
0.00
dBc
–0.25
–0.50
–0.75
–1.00
–80
–70
–60
–50
–40
–30
–20
–10
0
INL
ANALOG INPUT POWER LEVEL – dBFS
TPC 13. Single Tone SFDR
TPC 15. Integral Nonlinearity: fS = 105 MSPS
1.00
0.75
3.0
0.50
2.5
2.0
1.5
0.25
0.00
–0.25
–0.50
–0.75
–1.00
0
2
4
6
8
10
DNL
CURRENT – mA
TPC 14. Differential Nonlinearity: fS = 105 MSPS
TPC 16. Voltage Reference Output vs. Current Load
REV. E
–9–
AD9432
APPLICATION NOTES
Theory of Operation
AD9432
0.1F
0.1F
ENCODE
PECL
GATE
The AD9432 is a multibit pipeline converter that uses a switched
capacitor architecture. Optimized for high speed, this converter
provides flat dynamic performance up to frequencies near Nyquist.
DNL transitional errors are calibrated at final test to a typical
accuracy of 0.25 LSB or less.
ENCODE
510⍀
510⍀
GND
Figure 8. AC Coupling to ENCODE Inputs
ENCODE Voltage Level Definition
The voltage level definitions for driving ENCODE and ENCODE
USING THE AD9432
Analog Input
The analog input to the AD9432 is a differential buffer. The input
buffer is self-biased by an on-chip resistor divider that sets the
dc common-mode voltage to a nominal 3 V (see Equivalent
Circuits section). Rated performance is achieved by driving the
input differentially. Minimum input offset voltage is obtained when
driving from a source with a low differential source impedance
such as a transformer in ac applications. Capacitive coupling at the
inputs will increase the input offset voltage by as much as 25 mV.
Driving the ADC single-endedly will degrade performance.
For best dynamic performance, impedances at AIN and AIN
should match.
in single-ended and differential mode are shown in Figure 9.
ENCODE Inputs
Differential Signal Amplitude (VID) . . . . . . . . . . . 500 mV min
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 mV nom
High Differential Input Voltage (VIHD) . . . . . . . . . . 3.5 V max
Low Differential Input Voltage (VILD) . . . . . . . . . . . . . 0 V min
Common-Mode Input (VICM) . . . . . . . 1.25 V min, 1.6 V nom
High Single-Ended Voltage (VIHS) . . . . . 2 V min to 3.5 V max
Low Single-Ended Voltage (VILS
)
. . . . . 0 V min to 0.8 V max
Special care was taken in the design of the analog input section
of the AD9432 to prevent damage and corruption of data when
the input is overdriven. The nominal input range is 2 V p-p.
Each analog input will be 1 V p-p when driven differentially.
ENCODE
V
V
IHD
V
ID
ICM
ENCODE
V
ILD
4.0
V
IHS
ENCODE
AIN
3.5
0.1F
V
ILS
Figure 9. Differential and Single-Ended Input Levels
3.0
Often, the cleanest clock source is a crystal oscillator producing
a pure sine wave. In this configuration, or with any roughly
symmetrical clock input, the input can be ac-coupled and biased
to a reference voltage that also provides the ENCODE. This
ensures that the reference voltage is centered on the encode signal.
AIN
2.5
2.0
Digital Outputs
The digital outputs are 3.3 V (2.7 V to 3.6 V) TTL/CMOS-
compatible for lower power consumption. The output data
format is Two’s Complement, illustrated in Table I. The out of
range (OR) output (logic LOW for normal operation) will be
HIGH during any clock cycle when the ADC output data (Dx)
reach positive or negative full scale (–2048 or +2047). The OR
is internally generated each clock cycle, has the same pipe-
line latency and propagation delay as the ADC output data, and
will remain HIGH until the output data reflect an in-range
condition. The ADC output bits (Dx) will not roll over, and
will therefore remain at positive or negative full scale (+2048 or
–2047) while the OR output is HIGH.
Figure 7. Full-Scale Analog Input Range
ENCODE Input
Any high speed A/D converter is extremely sensitive to the qual-
ity of the sampling clock provided by the user. A track/hold
circuit is essentially a mixer, and any noise, distortion, or timing
jitter on the clock will be combined with the desired signal at the
A/D output. For that reason, considerable care has been taken
in the design of the ENCODE input of the AD9432, and the
user is advised to give commensurate thought to the clock source.
The ENCODE input supports either differential or single-ended
and is fully TTL/CMOS compatible.
Note that the ENCODE inputs cannot be driven directly from
PECL level signals (VIHD is 3.5 V max). PECL level signals can
easily be accommodated by ac coupling as shown in Figure 8.
Good performance is obtained using an MC10EL16 in the
circuit to drive the encode inputs.
REV. E
–10–
AD9432
Table I. Output Coding (VREF = 2.5 V) (Two’s Complement)
The dc common-mode voltage for the AD8138 outputs can be
adjusted via input VOCM to provide the 3 V common-mode voltage
the AD9432 inputs require.
Code
AIN–AIN (V)
Digital Output
+2047
1.000
0111 1111 1111
500⍀
•
•
•
AD9432
10pF
•
•
•
0
0
0000 0000 0000
50⍀
VIN
–1
–0.00049
1111 1111 1111
AIN
500⍀
•
•
•
22pF
AD8138
50⍀
•
•
•
50⍀
AIN
–2048
–1.000
1000 0000 0000
V
OCM
5V
Voltage Reference
500⍀
2k⍀
A stable and accurate 2.5 V voltage reference is built into the
AD9432 (VREFOUT). In normal operation the internal refer-
ence is used by strapping Pin 45 to Pin 46 and placing a 0.1 µF
decoupling capacitor at VREFIN.
3k⍀
0.1F
10pF
25⍀
500⍀
The input range can be adjusted by varying the reference voltage
applied to the AD9432. No appreciable degradation in perfor-
mance occurs when the reference is adjusted 5%. The full-scale
range of the ADC tracks reference voltage changes linearly.
Figure 10. AD8138/AD9432 Schematic
66
65
Timing
The AD9432 provides latched data outputs, with 10 pipeline
delays. Data outputs are included or available one propagation
delay (tPD) after the rising edge of the encode command
(see Figure 1). The length of the output data lines and loads
placed on them should be minimized to reduce transients within
the AD9432; these transients can detract from the converter’s
dynamic performance.
SNR
64
63
SINAD
62
61
60
The minimum guaranteed conversion rate of the AD9432 is
1 MSPS. At internal clock rates below 1 MSPS, dynamic
performance may degrade. Therefore, input clock rates below
1 MHz should be avoided.
During initial power-up, or whenever the clock to the AD9432
is interrupted, the output data will not be accurate data for 200 ns
or 10 clock cycles, whichever is longer.
0
20
40
60
AIN – MHz
Figure 11. Measured SNR and SINAD (Encode = 105 MSPS)
Using the AD8138 to Drive the AD9432
–70
A new differential output op amp from Analog Devices, Inc.,
the AD8138, can be used to drive the AD9432 in dc-coupled
applications. The AD8138 was specifically designed for ADC
driver applications. Superior SNR performance is maintained up
to analog frequencies of 30 MHz. The AD8138 op amp provides
single-ended-to-differential conversion, providing for a low-cost
option to transformer coupling for ac applications as well.
H2
–80
H3
The circuit in Figure 10 was breadboarded and the measured
performance is shown in Figures 11 and 12. The figures shown
are for 5 V supplies at the AD8138—performance dropped by
about 1 dB–2 dB with a single 5 V supply at the AD8138.
–90
Figure 11 shows SNR and SINAD for a –1 dBFS analog input
frequency varied from 2 MHz to 40 MHz with an encode rate of
105 MSPS. The measurements are for nominal conditions at
room temperature. Figure 12 shows the second and third har-
monic distortion performance under the same conditions.
–100
0
20
40
60
AIN – MHz
Figure 12. Measured Second and Third Order Harmonic
Distortion (Encode = 105 MSPS)
REV. E
–11–
AD9432
EVALUATION BOARD
14 ACQS
[T]
TEK STOP: 5.00GS/s
The AD9432 evaluation board offers an easy way to test the
AD9432. It requires an analog signal, encode clock, and power
supplies as inputs. The clock is buffered on the board to provide
the clocks for an on-board DAC and latches. The digital outputs
and output clock are available at a standard 37-pin connector P7.
C1 MAX
3.4V
T
C1 MIN
2.5mV
Power Connector
Power is supplied to the board via two detachable 4-pin power
strips P30, P40.
C1 FREQ
49.995MHz
LOW SIGNAL
AMPLITUDE
P40
P1 VCC2 5 V/165 mA
P2 GND
DAC Supply
2
P3 VCC 5 V/200 mA
P4 GND
ADC Analog Supply
CH1 500mV
CH3 2.00V
500mV
M 5.00ns CH1
3.00V
CH2
P30
Figure 14. Analog Input Levels
The full-scale analog inputs to the ADC should be two 1 V p-p
signals 180 degrees out of phase with each other, as shown in
Figure 14. The analog inputs are dc biased by two on-chip
resistor dividers that set the common-mode voltage to approxi-
mately 0.6 × VCC (0.6 × 5 = 3 V). AIN+ and AIN– each vary
between 2.5 V and 3.5 V as shown in the two upper traces in Fig-
ure 14. The lower trace is the input at SMB P2 (on a 2 V/div scale).
P5
P6
P7 VD
No Connect
No Connect
3.3 V /105 mA Latch, ADC Digital Output Supply
P8 GND
Analog Inputs
The evaluation board accepts a 2 V p-p analog input signal at
SMB connector P2. This single-ended signal is ac-coupled by
capacitor C11 and drives a wideband RF transformer T1 (Mini-
Circuits ADT1-1WT) that converts the single-ended signal to a
differential signal. (The AD9432 should be driven differentially to
provide optimum performance.) The evaluation board is shipped
with termination resistors R4, R5, which provide the effective
50 Ω termination impedance; input termination resistor R10 is
optional. Note: The second harmonic distortion that some RF
transformers tend to introduce at high frequencies can be reduced
by coupling two transformers in series as shown in Figure 13.
(Improvements on the order of 3 dB–4 dB can be realized.)
Encode
The encode input to the board is at SMB connector P3. The
(>1 V p-p) input is ac-coupled and drives two high-speed differ-
ential line receivers (MC10EL16). These receivers provide
subnanosecond rise times at their outputs—a requirement for
the ADC clock inputs for optimum performance. The EL16
outputs are PECL levels and must be ac-coupled to meet the
common-mode dc levels required at the AD9432 encode inputs.
A PECL/TTL translator (MC100ELT23), provides the clocks
required at the output latches, DAC, and 37-pin connector.
Note: Jitter performance on the clock source is critical at this
performance level; a stable, crystal-controlled signal generator is
used to generate all of the ADC performance plots. Figure 15
shows the Encode+ clock at the ADC. The 3 V latch clock
generated on the card is also shown in the plot.
TO AIN+
C2
0.1F
R1
T1
T2
25⍀
IN
C1
0.1F
R2
25⍀
TEK
STOP:
5.00GS/s
86 ACQS
[T]
TO AIN–
Figure 13. Improving Second Harmonic Distortion
Performance
C1 MAX
2.33V
C1 MIN
810mV
T
C1 FREQ
106.3167MHz
LOW
SIGNAL
AMPLITUDE
2
CH1
1.00V
CH2
1.00V
M 5.00ns CH1
1.20V
Figure 15. Encode+ Clock and Latch Clock
REV. E
–12–
AD9432
DATA OUTPUTS
DAC
The ADC digital outputs are latched on the board by two 574s;
the latch outputs are available at the 37-pin connector at Pins
25–36. A latch output clock (data ready) is available at Pin 21,
with the complement at Pin 2. There are series termination
resistors on the data and clock outputs. These can be changed if
required to accommodate different loading situations. Figure
16 shows a data bit switching and output clock (DR) at the
connector.
The evaluation board has an on-board reconstruction DAC
(AD9752). This is placed only to facilitate testing and debug of
the board. It should not be used to measure the performance of
the ADC, as it will not accurately indicate the ADC performance.
The DAC output is available at SMB P1. It will drive a 50 Ω
load. Provision to power down the DAC is at Pin 15 at the DAC.
PCB LAYOUT
The PCB is designed on a four-layer (1 oz. Cu) board. Compo-
nents and routing are on the top layer with a ground flood for
additional isolation. Test and ground points were judiciously
placed to facilitate high-speed probing. A common ground plane
exists on the second layer. The third layer has three split power
planes, two for the ADC and one for support logic. The DAC,
components, and routing are located on the bottom layer.
TEK
STOP:
5.00GS/s
265 ACQS
[T]
C1 MAX
3.06V
C1 MIN
–390mV
T
TROUBLESHOOTING
If the board does not seem to be working correctly, try the
following:
C1 FREQ
105.4562MHz
•
•
Verify power at IC pins.
Check that all jumpers are in the correct position for the
desired mode of operation.
2
•
•
Verify VREF is at 2.5 V.
CH1
1.00V
CH2
1.00V
M 5.00ns CH1
1.20V
Try running encode clock and analog inputs at low speeds
(10 MSPS/1 MHz) and monitor 574 outputs, DAC output,
and ADC outputs for toggling.
Figure 16. Data Bit and Clock at 37-Pin Connector
REFERENCE
The AD9432 has an on-chip reference of 2.5 V available at
VREFOUT (Pin 46). Most applications will simply tie this
output to the VREFIN input (Pin 45). This is accomplished
jumping E4 to E6 on the board. An external voltage reference
can drive the VREFIN pin if desired by strapping E4 to E3 and
placing an AD780 voltage reference on the board (not supplied).
The AD9432 Evaluation Board is provided as a design example
for customers of Analog Devices, Inc. ADI makes no warranties,
express, statutory, or implied, regarding merchantability or fitness
for a particular purpose.
REV. E
–13–
AD9432
PCB Bill of Materials
Device
#
Quantity
REFDES
Package
Value
1
30
C1–C8, C10–C13, C17, C19–C22,
C27–C29, C41, C42, C47, C48,
C53, C56, C58, C60, C61, C70
Capacitor
603
0.1 µF
2
3
4
5
6
7
8
9
1
4
1
18
3
1
2
6
C9
Capacitor
Capacitor
Capacitor
E-HOLE
Connector
37-Pin Connector
Power Connector
Resistor
603
0.01 µF
10 µF
1 µF
C14, C18, C31, C34
C15
E1–E13, E30, E32, E40, E42, E43
P1, P2, P3
P7
P30, P40
R1, R2, R7, R8, R10, R18
(R1, R2, R10 Optional)
CAPTAJD
CAPTAJD
Test Point
SMB
Female
AMP 747462-2
1206
50 Ω
10
11
12
13
14
2
4
2
4
1
R3, R35
R25, R26, R31, R32
R6, R24
RP1–RP4
T1
Resistor
Resistor
Resistor
RES PAK
Transformer
1206
1206
1206
100 Ω
500 Ω
2 kΩ
100 Ω
Mini-Circuits
ADT1-1WT
15
16
17
18
19
20
21
22
1
1
2
1
2
1
2
3
U1
U2
U3, U4
U9
U12–U13
Z1
DAC
SOIC
SOIC
SC70
52QFP
SOIC
SOIC
SOIC
1206
AD9752
AD780N
Reference (Not Supplied)
Inverter (U4 Not Supplied)
ADC
NC7SZ04P5
AD9432
74AC574M
MC100ELT23
MC10EL16
24.9 Ω
Latch
PECL/TTL Translator
Differential Receiver
Resistor
Z2, Z3
R4, R5, R15
REV. E
–14–
AD9432
2
5
1
3
4
6
3 7
4 4
4 7
5 2
3 8
4 3
4 8
5 1
1 3
3 6
1 2
3 5
2 2
2 3
3 2
1 1
3 3
1 0
2 1
2 4
3 1
9
3 4
Figure 17a. PCB Schematic
–15–
REV. E
AD9432
Figure 17b. PCB Schematic (Continued)
REV. E
–16–
AD9432
Figure 18. Top Silkscreen
Figure 19. Top Level Routing
Figure 20. Ground Plane
Figure 21. Split Power Plane
Figure 22. Bottom Layer Route
Figure 23. Bottom Silkscreen
REV. E
–17–
AD9432
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
52-Lead Plastic Quad Flatpack (LQFP)
(ST-52)
0.063 (1.60)
MAX
0.472 (12.00) SQ
0.030 (0.75)
0.018 (0.45)
39
27
40
26
SEATING
PLANE
0.394
(10.0)
SQ
TOP VIEW
(PINS DOWN)
14
52
1
13
0.006 (0.15)
0.002 (0.05)
0.026 (0.65)
BSC
0.015 (0.38)
0.009 (0.22)
0.057 (1.45)
0.053 (1.35)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE
ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
THERMALLY ENHANCED
52-Lead Power Thin Plastic Quad Flatpack (LQFP_ED)
(SQ-52)
0.093 (2.35)
0.087 (2.20) (4 PLCS)
0.104 (2.65)
0.081 (2.05)
0.472 (12.00) SQ
0.307 (7.80)
0.098 (2.50)
0.093 (2.35)
(4 PLCS)
52
40
40
39
52
1
39
1
0.402 (10.20)
0.394 (10.00) SQ
0.386 (9.80)
0.236 (6.00)
0.232 (5.90)
0.228 (5.80)
EXPOSED
HEATSINK
(CENTERED)
TOPVIEW
(PINS DOWN)
13
27
27
26
13
14
26
14
0.236 (6.00)
0.232 (5.90)
0.228 (5.80)
0.026 (0.65) 0.015 (0.38)
0.013 (0.32)
0.009 (0.22)
BOTTOMVIEW
(PINS UP)
0.063
(1.60)
MAX
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
0.006 (0.15)
0.002 (0.05)
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
SEATING
PLANE
VIEW A
0.004 (0.10)
COPLANARITY
VIEW A
NOTES
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER
EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
2. ALTHOUGH NOT REQUIRED IN ALL APPLICATIONS,THE AD9432 HAS AN EXPOSED METALLIC PAD ONTHE
PACKAGE BOTTOMWHICH IS INTENDEDTO ENHANCETHE HEAT REMOVAL PATH. TO MAXIMIZETHE REMOVAL
OF HEAT, A LAND PATTERNWITH CLOSELY SPACEDTHERMAL VIASTOTHE GROUND PLANE(S) SHOULD
BE INCORPORATED ONTHE PCBWITHINTHE FOOTPRINT OFTHE PACKAGE CORRESPONDINGTOTHE
EXPOSED METAL PAD DIMENSIONS OFTHE PACKAGE. THE SOLDERABLE LAND AREA SHOULD BE SOLDER
MASK DEFINED AND BE AT LEASTTHE SAME SIZE AND SHAPE ASTHE EXPOSED PAD AREA ONTHE
PACKAGE. AT LEAST 0.25 MM CLEARANCE BETWEENTHE OUTER EDGES OFTHE LAND PATTERN ANDTHE
INNER EDGES OFTHE PAD PATTERN SHOULD BE MAINTAINEDTO AVOID ANY SHORTS.
REV. E
–18–
AD9432
Revision History
Location
Page
Data Sheet changed from REV. D to REV. E.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Addition of text to USING THE AD9432 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Edits to Figure 17a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Edits to Figure 17b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Addition of SQ-52 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REV. E
–19–
–20–
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