AD9434BCPZRL7-370 [ADI]
12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter; 12位， 370 MSPS / 500 MSPS ， 1.8 V模拟数字转换器
| 型号： | AD9434BCPZRL7-370 |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 370 MSPS/500 MSPS, 1.8 V Analog-to-Digital Converter |
| 文件： | 总28页 (文件大小：1012K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 370 MSPS/500 MSPS,
1.8 V Analog-to-Digital Converter
AD9434
FUNCTIONAL BLOCK DIAGRAM
FEATURES
VREF
PWDN
AGND
AVDD
SNR = 65 dBFS at fIN up to 250 MHz at 500 MSPS
ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
SFDR = 78 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
Integrated input buffer
Excellent linearity
DNL = 0.5 LSB typical
REFERENCE
AD9434
CML
DRVDD
DRGND
VIN+
VIN–
TRACK-AND-HOLD
12
12
ADC
CORE
OUTPUT
STAGING
LVDS
D11± TO D0±
INL = 0.6 LSB typical
LVDS at 500 MSPS (ANSI-644 levels)
1 GHz full power analog bandwidth
On-chip reference, no external decoupling required
Low power dissipation
CLK+
CLK–
CLOCK
MANAGEMENT
OR+
OR–
SERIAL PORT
DCO+
DCO–
690 mW at 500 MSPS—LVDS SDR mode
660 mW at 500 MSPS—LVDS DDR mode
Programmable (nominal) input voltage range
1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
SCLK/DFS
SDIO
CSB
Figure 1.
Clock duty cycle stabilizer
Integrated data clock output with programmable clock and
data alignment
APPLICATIONS
Fabricated on an advanced BiCMOS process, the AD9434 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C). This part is protected
under a U.S. patent.
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
PRODUCT HIGHLIGHTS
1. High Performance.
GENERAL DESCRIPTION
Maintains 65 dBFS SNR at 500 MSPS with a 250 MHz input.
2. Low Power.
Consumes only 660 mW at 500 MSPS.
3. Ease of Use.
The AD9434 is a 12-bit monolithic sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The part operates at up to a 500 MSPS
conversion rate and is optimized for outstanding dynamic
performance in wideband carrier and broadband systems. All
necessary functions, including a sample-and-hold and voltage
reference, are included on the chip to provide a complete signal
conversion solution. The VREF pin can be used to monitor the
internal reference or provide an external voltage reference
(external reference mode must be enabled through the SPI
port).
LVDS output data and output clock signal allow interface
to FPGA technology. The on-chip reference and sample-
and-hold provide flexibility in system design. Use of a
single 1.8 V supply simplifies system power supply design.
4. Serial Port Control.
Standard serial port interface supports various product
functions, such as data formatting, power-down, gain
adjust, and output test pattern generation.
5. The AD9434 is pin compatible with the AD9230, and can
be substituted in many applications with minimal design
changes.
The ADC requires a 1.8 V analog voltage supply and a differen-
tial clock for full performance operation. The digital outputs are
LVDS (ANSI-644) compatible and support twos complement,
offset binary format, or Gray code. A data clock output is
available for proper output data timing.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
AD9434
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 19
Analog Input and Voltage Reference ....................................... 19
Clock Input Considerations...................................................... 20
Power Dissipation and Power-Down Mode ........................... 21
Digital Outputs ........................................................................... 21
Timing ......................................................................................... 22
VREF............................................................................................ 22
AD9434 Configuration Using the SPI..................................... 22
Using the AD9434 to Replace the AD9230............................. 23
Hardware Interface..................................................................... 23
Configuration Without the SPI ................................................ 23
Memory Map .................................................................................. 25
Reading the Memory Map Table.............................................. 25
Reserved Locations .................................................................... 25
Default Values............................................................................. 25
Logic Levels................................................................................. 25
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 13
Equivalent Circuits......................................................................... 18
REVISION HISTORY
5/11—Rev. 0 to Rev. A
Changes to General Description .................................................... 1
Changes to Table 4, Aperture Time Values ................................... 6
Changes to Figure 32...................................................................... 17
Changes to Figure 42...................................................................... 19
Changes to Table 13, Register 10, Bits[7:0] Value, Register 14
Default Value, Register 15 Default Value, Register 17, Bit 7 Value
and Register 18, Bit[4:0] Values.................................................... 26
3/11—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD9434
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 1.
AD9434-370
Typ
AD9434-500
Typ
Parameter1
RESOLUTION
ACCURACY
Temp
Min
Max
Min
Max
Unit
12
12
Bits
No Missing Codes
Offset Error
Full
25°C
Full
25°C
Full
25°C
Full
Guaranteed
±±.25
Guaranteed
±±.25
mV
mV
−3.±
−5.±
−±.9
−±.92
±.71
+1.±
+7.±
+±.9
+±.92
±.78
−3.±
−5.±
−±.95
−1.3
±.71
+1.±
+7.±
+1.±
+1.3
±.78
Gain Error
1.±
1.±
% FS
% FS
LSB
LSB
LSB
LSB
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
±±.ꢀ
±±.ꢀ
±±.5
±±.ꢁ
25°C
Full
INTERNAL REFERENCE
VREF
Full
±.75
±.75
V
TEMPERATURE DRIFT
Offset Error
Gain Error
Full
Full
18
±.±7
18
±.±7
μV/°C
%/°C
ANALOG INPUTS (VIN+, VIN−)
Differential Input Voltage Range2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Differential)
POWER SUPPLY
Full
Full
Full
25°C
1.18
1.5
1.7
1
1.ꢁ
1.18
1.5
1.7
1
1.ꢁ
V p-p
V
kΩ
pF
1.3
1.3
AVDD
DRVDD
Full
Full
1.75
1.75
1.8
1.8
1.9
1.9
1.75
1.75
1.8
1.8
1.9
1.9
V
V
Supply Currents
3
IAVDD
Full
Full
Full
2ꢁ±
88
7±
28±
1±±
8±
283
1±±
82
3±1
11ꢀ
9ꢁ
mA
mA
mA
IDRVDD3/SDR Modeꢀ
IDRVDD3/DDR Mode5
Power Dissipation
SDR Modeꢀ
DDR Mode5
Standby Mode
Full
Full
Full
Full
ꢁ25
595
ꢀ±
ꢁ85
ꢁꢀ8
5±
ꢁ9±
ꢁ57
ꢀ±
7ꢀ7
715
5±
mW
mW
mW
mW
Power-Down Mode
2.5
7
2.5
7
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.
3 IAVDD and IDRVDD are measured with a −1 dBFS, 3±.3 MHz sine input at rated sample rate.
ꢀ Single data rate mode; this is the default mode of the AD9ꢀ3ꢀ.
5 Double data rate mode; user-programmable feature. See the Memory Map section.
Rev. A | Page 3 of 28
AD9434
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 2.
AD9434-370
AD9434-500
Typ
Parameter1, 2
SNR
Temp
Min
Typ
Max
Min
Max
Unit
fIN = 3±.3 MHz
fIN = 7±.3 MHz
fIN = 1±±.3 MHz
25°C
25°C
25°C
Full
ꢁꢁ.3
ꢁꢁ.2
ꢁꢁ.1
ꢁ5.9
ꢁ5.9
ꢁ5.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
ꢁ5.3
ꢁꢀ.5
fIN = 25±.3 MHz
fIN = ꢀ5±.3 MHz
SINAD
25°C
25°C
ꢁ5.5
ꢁꢀ.±
ꢁ5.2
ꢁ3.5
fIN = 3±.3 MHz
fIN = 7±.3 MHz
fIN = 1±±.3 MHz
25°C
25°C
25°C
Full
ꢁꢁ.1
ꢁꢁ.1
ꢁꢁ.±
ꢁ5.9
ꢁ5.8
ꢁ5.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
ꢁ5.2
ꢁꢀ.ꢀ
fIN = 25±.3 MHz
fIN = ꢀ5±.3 MHz
25°C
25°C
ꢁ5.3
ꢁ3.7
ꢁꢀ.8
ꢁ2.9
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 3±.3 MHz
25°C
25°C
25°C
25°C
25°C
1±.7
1±.7
1±.7
1±.ꢁ
1±.3
1±.7
1±.ꢁ
1±.ꢁ
1±.5
1±.2
Bits
Bits
Bits
Bits
Bits
fIN = 7±.3 MHz
fIN = 1±±.3 MHz
fIN = 25±.3 MHz
fIN = ꢀ5±.3 MHz
WORST HARMONIC (SECOND or THIRD)
fIN = 3±.3 MHz
25°C
25°C
25°C
Full
−93
−89
−83
−93
−91
−87
dBc
dBc
dBc
dBc
dBc
dBc
fIN = 7±.3 MHz
fIN = 1±±.3 MHz
−75
−7ꢀ
fIN = 25±.3 MHz
fIN = ꢀ5±.3 MHz
SFDR
25°C
25°C
−8±
−78
−78
−ꢁ9
fIN = 3±.3 MHz
fIN = 7±.3 MHz
fIN = 1±±.3 MHz
25°C
25°C
25°C
Full
89
88
83
8ꢀ
82
83
dBc
dBc
dBc
dBc
dBc
dBc
75
7ꢀ
fIN = 25±.3 MHz
25°C
25°C
79
78
78
ꢁ8
fIN = ꢀ5±.3 MHz
WORST OTHER HARMONIC (SFDR EXCLUDING SECOND and THIRD)
fIN = 3±.3 MHz
fIN = 7±.3 MHz
fIN = 1±±.3 MHz
25°C
25°C
25°C
Full
−9±
−9±
−91
−85
−82
−8ꢀ
dBc
dBc
dBc
dBc
dBc
dBc
−75
−7ꢀ
fIN = 25±.3 MHz
25°C
25°C
−83
−82
−85
−78
fIN = ꢀ5±.3 MHz
TWO-TONE IMD
fIN1 = 119.5 MHz, fIN2 = 122.5 MHz
ANALOG INPUT BANDWIDTH
Full Power
25°C
25°C
−85
1
−85
1
dBc
GHz
1 All ac specifications tested by driving CLK+ and CLK− differentially.
2 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. A | Page ꢀ of 28
AD9434
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 3.
AD9434-370
Typ Max
AD9434-500
Typ Max
Parameter1
Temp
Min
Min
Unit
CLOCK INPUTS
Logic Compliance
Full
Full
CMOS/LVDS/LVPECL
±.9
CMOS/LVDS/LVPECL
±.9
Internal Common-Mode Bias
Differential Input Voltage
High Level Input (VIH)
Low Level Input (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance (Differential)
Input Capacitance
V
Full
Full
Full
Full
Full
Full
±.2
1.8
±.2
1.8
V p-p
V p-p
μA
μA
kΩ
−1.8
−1±
−1±
8
−±.2
+1±
+1±
−1.8
−1±
−1±
8
−±.2
+1±
+1±
1±
ꢀ
12
1±
ꢀ
12
pF
LOGIC INPUTS
Logic 1 Voltage
Logic ± Voltage
Logic 1 Input Current (SDIO, CSB)
Logic ± Input Current (SDIO, CSB)
Logic 1 Input Current (SCLK, PDWN) Full
Logic ± Input Current (SCLK, PDWN) Full
Full
Full
Full
Full
±.8 × DRVDD
±.8 × DRVDD
V
V
±.2 × DRVDD
±.2 × DRVDD
±
±
μA
μA
μA
μA
pF
−ꢁ±
5±
±
−ꢁ±
5±
±
Input Capacitance
LOGIC OUTPUTS2
25°C
ꢀ
ꢀ
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
Full
Full
2ꢀ7
1.125
ꢀ5ꢀ
1.375
2ꢀ7
1.125
ꢀ5ꢀ
1.375
mV
V
Twos complement, Gray code, or offset binary (default)
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 LVDS RTERMINATION = 1±± Ω.
Rev. A | Page 5 of 28
AD9434
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 4.
AD9434-370
Typ
AD9434-500
Typ
Parameter
Temp
Full
Min
Max
Min
Max
Unit
MSPS
MSPS
ns
Maximum Conversion Rate
Minimum Conversion Rate
CLK+ Pulse Width High (tCH)1, 2
CLK+ Pulse Width Low (tCL)
Output (LVDS—SDR Mode)1
Data Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD
370
500
Full
50
11
11
50
11
11
Full
Full
1.1
1.1
0.9
0.9
ns
Full
0.85
0.15
0.15
0.6
0.85
0.15
0.15
0.6
ns
ns
ns
ns
25°C
25°C
Full
)
Data to DCO Skew (tSKEW
)
Full
0.15
0.38
0.15
0.38
ns
Latency
Full
15
15
Cycles
Output (LVDS—DDR Mode)2
Data Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD
Full
0.6
0.6
ns
ns
ns
ns
25°C
25°C
Full
0.15
0.15
0.6
0.15
0.15
0.6
)
Data to DCO Skew (tSKEW
Latency
Aperture Time (tA)
)
Full
Full
25°C
25°C
−0.07
+0.07
−0.07
+0.07
ns
Cycles
ns
15
0.85
80
15
0.85
80
Aperture Uncertainty (Jitter, tJ)
fs rms
1 See Figure 2.
2 See Figure 3.
Rev. A | Page 6 of 28
AD9434
Timing Diagrams
N – 1
tA
N + 4
N + 5
N
N + 3
VIN+, VIN–
N + 1
N + 2
tCH
tCL
1/fS
CLK+
CLK–
tCPD
DCO+
DCO–
tSKEW
tPD
Dx+
Dx–
N – 15
N – 14
N – 13
N – 12
N – 11
Figure 2. Single Data Rate Mode
N – 1
tA
N + 4
N + 5
N
N + 3
VIN+, VIN–
N + 1
N + 2
tCH
tCL
1/fS
CLK+
CLK–
tCPD
DCO+
DCO–
tSKEW
tPD
D0/D6+
D0/D6–
D6
N – 15
D0
N – 14
D6
N – 14
D0
N – 13
D6
N – 13
D0
N – 12
D6
N – 12
D0
N – 11
D6
N – 11
D0
N – 10
D5/D11+
D5/D11–
D11
N – 15
D5
N – 14
D11
D5
N – 13
D11
N – 13
D5
N – 12
D11
N – 12
D5
N – 11
D11
N – 11
D5
N – 10
N – 14
6 MSBs
6 LSBs
Figure 3. Double Data Rate Mode
Rev. A | Page 7 of 28
AD9434
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
Electrical
AVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
D±+/D±− Through D11+/D11−
to DRGND
−±.3 V to +2.± V
−±.3 V to +2.± V
−±.3 V to +±.3 V
−2.± V to +2.± V
−±.3 V to DRVDD + ±.2 V
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints, maximizing the
thermal capability of the package.
DCO+, DCO− to DRGND
OR+, OR− to DRGND
CLK+ to AGND
CLK− to AGND
VIN+ to AGND
VIN− to AGND
CML to AGND
VREF to AGND
SDIO to DRGND
PDWN to AGND
CSB to AGND
SCLK/DFS to AGND
Environmental
−±.3 V to DRVDD + ±.2 V
−±.3 V to DRVDD + ±.2 V
−±.3 V to AVDD + ±.2 V
−±.3 V to AVDD + ±.2 V
−±.3 V to AVDD + ±.2 V
−±.3 V to AVDD + ±.2 V
−±.3 V to AVDD + ±.2 V
−±.3 V to AVDD + ±.2 V
−±.3 V to DRVDD + ±.2 V
−±.3 V to DRVDD + ±.2 V
−±.3 V to DRVDD + ±.2 V
−±.3 V to DRVDD + ±.2 V
Table 6.
Package Type
θJA
θJC
Unit
5ꢁ-Lead LFCSP_VQ (CP-5ꢁ-5) 23.7
1.7
°C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA.
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering, 1± sec)
−ꢁ5°C to +125°C
−ꢀ±°C to +85°C
3±±°C
ESD CAUTION
Junction Temperature
15±°C
Rev. A | Page 8 of 28
AD9434
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D3–
D3+
D4–
D4+
D5–
1
2
3
4
5
6
7
8
9
PIN 1
42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
INDICATOR
D5+
AD9434
TOP VIEW
(Not to Scale)
DRVDD
DRGND
D6–
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 VREF
30 AVDD
29 PWDN
D6+ 10
D7– 11
D7+ 12
D8– 13
D8+ 14
PIN 0 (EXPOSED PADDLE) = AGND
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. AGND AND DRGND SHOULD BE TIED TO A COMMON
QUIET GROUND PLANE.
3. THE EXPOSED PADDLE MUST BE SOLDERED TO
A GROUND PLANE.
Figure 4. Pin Configuration—Single Data Rate Mode
Table 7. Pin Function Descriptions—Single Data Rate Mode
Pin No.
Mnemonic
Description
±
AGND1
Analog Ground. The exposed paddle must be soldered to a ground plane.
1.8 V Analog Supply.
3±, 32 to 3ꢀ, 37 to 39, AVDD
ꢀ1 to ꢀ3, ꢀꢁ
7, 2ꢀ, ꢀ7
8, 23, ꢀ8
35
DRVDD
DRGND1
VIN+
1.8 V Digital Output Supply.
Digital Output Ground.
Analog Input—True.
3ꢁ
VIN−
Analog Input—Complement.
ꢀ±
CML
Common-Mode Output. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
ꢀꢀ
ꢀ5
31
28
25
2ꢁ
27
29
ꢀ9
5±
51
52
53
5ꢀ
55
5ꢁ
1
CLK+
CLK−
VREF
DNC
SDIO
SCLK/DFS
CSB
PWDN
DCO−
DCO+
D±−
D±+
D1−
D1+
D2−
D2+
D3−
Clock Input—True.
Clock Input—Complement.
Voltage Reference Internal/Input/Output. Nominally ±.75 V.
Do Not Connect. Do not connect to this pin. This pin should be left floating.
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode).
Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode).
Serial Port Chip Select (Active Low).
Chip Power-Down.
Data Clock Output—Complement.
Data Clock Output—True.
D± Complement Output (LSB).
D± True Output (LSB).
D1 Complement Output.
D1 True Output.
D2 Complement Output.
D2 True Output.
D3 Complement Output.
2
D3+
D3 True Output.
3
Dꢀ−
Dꢀ Complement Output.
Rev. A | Page 9 of 28
AD9434
Pin No.
ꢀ
Mnemonic
Dꢀ+
Description
Dꢀ True Output.
5
ꢁ
D5−
D5+
D5 Complement Output.
D5 True Output.
9
Dꢁ−
Dꢁ+
D7−
D7+
D8−
D8+
D9−
D9+
D1±−
D1±+
D11−
D11+
OR−
Dꢁ Complement Output.
Dꢁ True Output.
D7 Complement Output.
D7 True Output.
D8 Complement Output.
D8 True Output.
D9 Complement Output.
D9 True Output.
D1± Complement Output.
D1± True Output.
D11 Complement Output (MSB).
D11 True Output (MSB).
Overrange Complement Output.
Overrange True Output.
1±
11
12
13
1ꢀ
15
1ꢁ
17
18
19
2±
21
22
OR+
1 AGND and DRGND should be tied to a common quiet ground plane.
Rev. A | Page 1± of 28
AD9434
D3/D9–
D3/D9+
D4/D10–
D4/D10+
D5/D11–
D5/D11+
DRVDD
DRGND
OR–
1
2
3
4
5
6
7
8
9
PIN 1
42 AVDD
41 AVDD
40 CML
39 AVDD
38 AVDD
37 AVDD
36 VIN–
INDICATOR
AD9434
TOP VIEW
(Not to Scale)
35 VIN+
34 AVDD
33 AVDD
32 AVDD
31 VREF
30 AVDD
29 PWDN
OR+ 10
DNC 11
DNC 12
DNC 13
DNC 14
PIN 0 (EXPOSED PADDLE) = AGND
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. AGND AND DRGND SHOULD BE TIED TO A COMMON
QUIET GROUND PLANE.
3. THE EXPOSED PADDLE MUST BE SOLDERED TO
A GROUND PLANE.
Figure 5. Pin Configuration—Double Data Rate Mode
Table 8. Pin Function Descriptions—Double Data Rate Mode
Pin No.
Mnemonic Description
±
AGND1
Analog Ground. The exposed paddle must be soldered to a ground plane.
1.8 V Analog Supply.
3±, 32 to 3ꢀ, 37 to 39, ꢀ1 AVDD
to ꢀ3, ꢀꢁ
7, 2ꢀ, ꢀ7
8, 23, ꢀ8
35
DRVDD
DRGND1
VIN+
1.8 V Digital Output Supply.
Digital Output Ground.
Analog Input—True.
3ꢁ
VIN−
Analog Input—Complement.
ꢀ±
CML
Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized
internal bias voltage for VIN+/VIN−.
ꢀꢀ
ꢀ5
31
25
2ꢁ
27
29
ꢀ9
5±
51
52
53
5ꢀ
55
5ꢁ
1
CLK+
CLK−
VREF
SDIO
SCLK/DFS
CSB
PWDN
DCO−
DCO+
D±/Dꢁ−
D±/Dꢁ+
D1/D7−
D1/D7+
D2/D8−
D2/D8+
D3/D9−
D3/D9+
Dꢀ/D1±−
Dꢀ/D1±+
D5/D11−
Clock Input—True.
Clock Input—Complement.
Voltage Reference Internal/Input/Output. Nominally ±.75 V.
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode).
Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode).
Serial Port Chip Select (Active Low).
Chip Power-Down.
Data Clock Output—Complement.
Data Clock Output—True.
D±/Dꢁ Complement Output (LSB).
D±/Dꢁ True Output (LSB).
D1/D7 Complement Output.
D1/D7 True Output.
D2/D8 Complement Output.
D2/D8 True Output.
D3/D9 Complement Output.
D3/D9 True Output.
Dꢀ/D1± Complement Output.
Dꢀ/D1± True Output.
2
3
ꢀ
5
D5/D11 Complement Output (MSB).
Rev. A | Page 11 of 28
AD9434
Pin No.
Mnemonic Description
ꢁ
9
D5/D11+
OR−
D5/D11 True Output (MSB).
Overrange Complement Output. (This pin is disabled if Pin 21 is reconfigured through the SPI to
be OR−.)
1±
OR+
DNC
Overrange True Output. (This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.)
Do Not Connect. Do not connect to these pins. These pins should be left floating.
11 to 2±, 28
21
DNC/(OR−) Do Not Connect. Do not connect to this pin. (This pin can be reconfigured as the overrange
complement output through the serial port register.)
22
DNC/(OR+) Do Not Connect. Do not connect to this pin. (This pin can be reconfigured as the overrange true
output through the serial port register.)
1 Tie AGND and DRGND to a common quiet ground plane.
Rev. A | Page 12 of 28
AD9434
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, TA = 25°C, 1.5 V p-p differential input, AIN = −1 dBFS, unless otherwise noted.
0
0
370MSPS
30.3MHz AT –1.0dBFS
SNR: 65.4dB
ENOB: 10.7 BITS
SFDR: 90dBc
500MSPS
30.3MHz AT –1.0dBFS
SNR: 65.0dB
ENOB: 10.7 BITS
SFDR: 85dBc
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
20
40
60
80
100
120
140
160
180
0
20 40 60 80 100 120 140 160 180 200 220 240
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. AD9434-370 64k Point Single-Tone FFT; 370 MSPS, 30.3 MHz
Figure 9. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 30.3 MHz
0
0
370MSPS
500MSPS
100.3MHz AT –1.0dBFS
100.3MHz AT –1.0dBFS
–20
–20
SNR: 65.3dB
SNR: 64.9dB
ENOB: 10.7 BITS
ENOB: 10.6 BITS
SFDR: 83dBc
SFDR: 84dBc
–40
–60
–40
–60
–80
–80
–100
–120
–100
–120
0
20
40
60
80
100
120
140
160
180
0
20 40 60 80 100 120 140 160 180 200 220 240
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. AD9434-370 64k Point Single-Tone FFT; 370 MSPS, 100.3 MHz
Figure 10. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 100.3 MHz
0
0
370MSPS
500MSPS
140.3MHz AT –1.0dBFS
140.3MHz AT –1.0dBFS
–20
–20
SNR: 65.2dB
SNR: 64.8dB
ENOB: 10.6 BITS
SFDR: 79dBc
ENOB: 10.7 BITS
SFDR: 85dBc
–40
–60
–40
–60
–80
–80
–100
–120
–100
–120
0
20
40
60
80
100
120
140
160
180
0
20 40 60 80 100 120 140 160 180 200 220 240
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. AD9434-370 64k Point Single-Tone FFT; 370 MSPS, 140.3 MHz
Figure 11. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 140.3 MHz
Rev. A | Page 13 of 28
AD9434
0
90
85
80
75
70
65
60
55
50
SFDR (dBc), T = –40°C
A
491.52MSPS
368.3MHz AT –1.0dBFS
SNR: 64.0dB
ENOB: 10.5 BITS
SFDR: 79dBc
SFDR (dBc), T = +25°C
A
–20
–40
SFDR (dBc), T = +85°C
A
–60
SNR (dBFS), T = –40°C
A
–80
SNR (dBFS), T = +25°C
A
SNR (dBFS), T = +85°C
A
–100
–120
0
20 40 60 80 100 120 140 160 180 200 220
FREQUENCY (MHz)
240
0
50
100 150 200 250 300 350 400 450 500
ANALOG INPUT FREQUECY (MHz)
Figure 12. AD9434-500 64k Point Single-Tone; 491.52 MSPS, 368.3 MHz
Figure 15. AD9434-500 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature; 500 MSPS
0
100
SFDR (dBc), 30.3MHz
491.52MSPS
450.3MHz AT –1.0dBFS
–20
90
SNR: 63.5dB
ENOB: 10.3 BITS
SFDR: 72dBc
–40
–60
80
SFDR (dBc), 100.3MHz
SNR (dBFS), 30.3MHz
70
–80
60
SNR (dBFS), 100.3MHz
–100
–120
50
40
0
20 40 60 80 100 120 140 160 180 200 220 240
FREQUENCY (MHz)
50
100 150 200 250 300 350 400 450 500 550
SAMPLE RATE (MSPS)
Figure 13. AD9434-500 64k Point Single-Tone; 491.52 MSPS, 450.3 MHz
Figure 16. AD9434-370 SNR/SFDR vs. Sample Rate; 30.3 MHz, 100.3 MHz
100
95
100
SFDR (dBc), 30.3MHz
SFDR (dBc), T = –40°C
A
90
90
85
80
75
70
65
60
55
50
SFDR (dBc), T = +25°C
A
80
SFDR (dBc), 100.3MHz
SNR (dBFS), 30.3MHz
70
SFDR (dBc), T = +85°C
A
SNR (dBFS), T = –40°C
A
60
SNR (dBFS), 100.3MHz
SNR (dBFS), T = +25°C
A
SNR (dBFS), T = +85°C
A
50
40
0
50
100 150 200 250 300 350 400 450 500
ANALOG INPUT FREQUECY (MHz)
50
100 150 200 250 300 350 400 450 500 550
SAMPLE RATE (MSPS)
Figure 14. AD9434-370 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature; 370 MSPS
Figure 17. AD9434-500 SNR/SFDR vs. Sample Rate; 30.3 MHz, 100.3 MHz
Rev. A | Page 1ꢀ of 28
AD9434
100
90
80
70
60
50
40
30
20
10
0
0.8
0.6
SFDR (dBFS)
SNR (dBFS)
0.4
0.2
0
SFDR (dBc)
–0.2
–0.4
–0.6
–0.8
SNR (dB)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
–1
1023
2047
3071
4095
AMPLITUDE (dB)
OUTPUT CODE
Figure 18. AD9434-370 SNR/SFDR vs. Input Amplitude; 500 MSPS, 140.3 MHz
Figure 21. AD9434-500 INL; 500 MSPS
100
0.4
0.3
90
SFDR (dBFS)
80
0.2
70
60
50
40
30
20
10
0
SNR (dBFS)
0.1
0
SFDR (dBc)
–0.1
–0.2
–0.3
–0.4
SNR (dB)
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
–1
1023
2047
3071
4095
AMPLITUDE (dB)
OUTPUT CODE
Figure 19. AD9434-500 SNR/SFDR vs. Input Amplitude; 500 MSPS, 140.3 MHz
Figure 22. AD9434-370 DNL; 370 MSPS
0.5
0.4
0.6
0.5
0.3
0.4
0.2
0.3
0.1
0.2
0
0.1
–0.1
–0.2
–0.3
–0.4
–0.5
0
–0.1
–0.2
–0.3
–0.4
–1
1023
2047
3071
4095
–1
1023
2047
3071
4095
OUTPUT CODE
OUTPUT CODE
Figure 20. AD9434-370 INL; 370 MSPS
Figure 23. AD9434-500 DNL, 500 MSPS
Rev. A | Page 15 of 28
AD9434
2.5
2.0
1.5
1.0
0.5
0
0
–20
1.17LSB rms
500MSPS
fIN1 = 119.5MHz AT –7.0dBFS
fIN2 = 122.5MHz AT –7.0dBFS
SFDR: 86dBc
–40
–60
–80
–100
–120
N – 3
N – 2 N – 1
N
N + 1 N + 2 N + 3 MORE
0
50
100
150
200
250
BINS
FREQUENCY (MHz)
Figure 24. AD9434-370 Grounded Input Histogram; 370 MSPS
Figure 27. AD9434-500 64k Point, Two-Tone FFT; 500 MSPS, 119.2 MHz,
122.5 MHz
2.5
120
1.24LSB rms
IMD3 (dBFS)
100
2.0
1.5
1.0
0.5
0
SFDR (dBFS)
80
60
SFDR (dBc)
40
20
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
N – 3
N – 2 N – 1
N
N + 1 N + 2 N + 3 MORE
BINS
AMPLITUDE (dBFS)
Figure 25. AD9434-500 Grounded Input Histogram; 500 MSPS
Figure 28. AD9434-370 Two-Tone SFDR vs. Input Amplitude; 370 MSPS,
119.5 MHz, 122.5 MHz
120
0
IMD3 (dBFS)
370MSPS
fIN1 = 119.5MHz AT –7.0dBFS
fIN2 = 122.5MHz AT –7.0dBFS
SFDR: 82dBc
100
–20
SFDR (dBFS)
80
–40
–60
60
SFDR (dBc)
40
–80
20
0
–100
–120
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0
50
100
150
AMPLITUDE (dBFS)
FREQUENCY (MHz)
Figure 29. AD9434-500 Two-Tone SFDR vs. Input Amplitude; 500 MSPS,
119.5 MHz, 122.5 MHz
Figure 26. AD9434-370 64k Point, Two-Tone FFT; 370 MSPS,
119.5 MHz, 122.5 MHZ
Rev. A | Page 1ꢁ of 28
AD9434
90
85
80
75
70
65
60
55
50
80
75
70
65
60
55
50
SFDR (dBc)
SFDR (dBc)
AD9434, 370MSPS
SNR (dBFS)
AD9434, 370MSPS
SNR (dBFS)
AD9434, 500MSPS
AD9434, 500MSPS
1.5
1.6
1.7
1.8
1.9
2.0
500
600
700
800
900
1000
V
(V)
ANALOG INPUT FREQUENCY (MHz)
CM
Figure 30. SNR/SFDR vs. Common-Mode Voltage; 370 MSPS, 500 MSPS,
fIN = 140.3 MHz
Figure 32. SNR/SFDR for AD9434-370 and AD9434-500 at 370 MSPS and
500 MSPS; AIN Sweep at −1.0 dBFS
350
300
250
200
150
100
50
800
700
600
500
400
300
200
100
0
TOTAL POWER
I
AVDD
I
DRVDD
SAMPLE RATE (MSPS)
Figure 31. Current and Power vs. Sample Rate, fIN = 30.3 MHz
Rev. A | Page 17 of 28
AD9434
EQUIVALENT CIRCUITS
AVDD
DRVDD
AVDD
AVDD
0.9V
DRVDD
30kΩ
15kΩ
15kΩ
CLK+
CLK–
DRVDD
350Ω
CSB
Figure 33. Clock Inputs
Figure 37. Equivalent CSB Input Circuit
V
BOOST
AVDD
DRVDD
CML
V+
V–
D11– TO D0–
V–
D11+ TO D0+
V+
AVDD
VIN+
A
+
IN
500Ω
500Ω
DC
Figure 38. LVDS Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−)
AVDD
SPI
CONTROLLED
AVDD
VIN+
20kΩ
A
–
(00)
IN
(01)
VREF
(10)
Figure 34. Analog Input DC Equivalent Circuit (VCML = ~1.7 V)
NOT USED
(11)
DRVDD
SPI CTRL V
SELECT
REF
00 = INTERNAL V
REF
REF
01 = IMPORT V
10 = EXPORT V
11 = NOT USED
REF
DRVDD
350Ω
Figure 39. Equivalent VREF Input/Output Circuit
SCLK/DFS
30kΩ
DRVDD
DRVDD
30kΩ
Figure 35. Equivalent SCLK/DFS, PDWN Input Circuit
350Ω
VIN+
SDIO
1.3pF
1000Ω
CTRL
VIN–
Figure 36. Analog Input AC Equivalent Circuit
Figure 40. Equivalent SDIO Input Circuit
Rev. A | Page 18 of 28
AD9434
THEORY OF OPERATION
The AD9434 architecture consists of a front-end sample-and-
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, whereas the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
Differential Input Configurations
Optimum performance is achieved while driving the AD9434
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to pro-
vide band limiting of the input signal.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
1V p-p
49.9Ω
499Ω
AVDD
VIN+
33Ω
499Ω
523Ω
20pF
AD8138
AD9434
0.1µF
VIN–
CML
33Ω
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended mode. The output
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
enter a high impedance state.
499Ω
Figure 41. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve
the true performance of the AD9434. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The signal characteristics must be considered
when selecting a transformer. Most RF transformers saturate at
frequencies below a few megahertz (MHz), and excessive signal
power can cause core saturation, which leads to distortion.
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9434 is a differential buffer. For best
dynamic performance, match the source impedances driving
VIN+ and VIN− such that common-mode settling errors are
symmetrical. The analog input is optimized to provide superior
wideband performance and requires that the analog inputs be
driven differentially. SNR and SINAD performance degrades
significantly if the analog input is driven with a single-ended
signal.
In any configuration, the value of the shunt capacitor, C (see
Figure 43), is dependent on the input frequency and may need
to be reduced or removed.
A wideband transformer, such as Mini-Circuits® ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip reference to a nominal 1.7 V.
15Ω
VIN+
1.5V p-p
50Ω
2pF
AD9434
VIN–
15Ω
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.5 V p-p fixed span
of the ADC core. This internal voltage reference can be adjusted
by means of an SPI control. See the AD9434 Configuration
Using the SPI section for more details.
0.1µF
Figure 42. Differential Transformer—Coupled Configuration
As an alternative to using a transformer-coupled input at frequen-
cies in the second Nyquist zone, the AD8352 differential driver
can be used (see Figure 43).
Rev. A | Page 19 of 28
AD9434
V
CC
0.1µF
11
0.1µF
0Ω
16
1
8, 13
0.1µF
0.1µF
ANALOG INPUT
R
R
2
VIN+
200Ω
200Ω
C
D
R
D
R
AD8352
C
AD9434
G
3
4
5
CML
VIN–
ANALOG INPUT
10
0.1µF
14
0Ω
0.1µF
0.1µF
Figure 43. Differential Input Configuration Using the AD8352
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD9434 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased at ~0.9 V
internally and require no additional bias. If the clock signal is
dc-coupled, then the common-mode voltage should remain
within a range of 0.9 V.
0.1µF
0.1µF
0.1µF
CLOCK
INPUT
CLK
PECL DRIVER
CLK
CLK+
ADC
100Ω
AD9434
0.1µF
CLOCK
INPUT
CLK–
1
1
240Ω
240Ω
50Ω
50Ω
1
50Ω RESISTORS ARE OPTIONAL.
Figure 45. Differential PECL Sample Clock
Figure 44 shows one preferred method for clocking the AD9434.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9434 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9434 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
0.1µF
CLOCK
INPUT
CLK
LVDS DRIVER
CLK
CLK+
ADC
100Ω
AD9434
0.1µF
0.1µF
CLOCK
INPUT
CLK–
1
1
50Ω
50Ω
1
50Ω RESISTORS ARE OPTIONAL.
Figure 46. Differential LVDS Sample Clock
MINI-CIRCUITS
ADT1–1WT, 1:1Z
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate,
and bypass the CLK− pin to ground with a 0.1 μF capacitor in
parallel with a 39 kΩ resistor (see Figure 47).
0.1µF
0.1µF
XFMR
CLOCK
INPUT
CLK+
ADC
AD9434
100Ω
50Ω
0.1µF
CLK–
0.1µF
SCHOTTKY
DIODES:
HSM2812
V
CC
OPTIONAL
0.1µF
1
Figure 44. Transformer-Coupled Differential Clock
0.1µF
1kΩ
1kΩ
AD951x
CMOS DRIVER
100Ω
CLOCK
INPUT
CLK+
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
shown in Figure 45. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
50Ω
ADC
AD9434
CLK–
0.1µF
39kΩ
1
50Ω RESISTOR IS OPTIONAL.
Figure 47. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Rev. A | Page 2± of 28
AD9434
Clock Duty Cycle Considerations
POWER DISSIPATION AND POWER-DOWN MODE
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. A 5% tolerance is commonly
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9434 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9434.
As shown in Figure 31, the power dissipated by the AD9434 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
By asserting PDWN (Pin 29) high, the AD9434 is placed in
standby mode or full power-down mode, as determined by the
contents of Serial Port Register 08. Reasserting the PDWN pin
low returns the AD9434 to its normal operational mode.
An additional standby mode is supported by means of varying
the clock input. When the clock rate falls below 50 MHz, the
AD9434 assumes a standby state. In this case, the biasing network
and internal reference remain on, but digital circuitry is powered
down. Upon reactivating the clock, the AD9434 resumes normal
operation after allowing for the pipeline latency.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 5 ꢀs to allow the
DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) can be calculated by
DIGITAL OUTPUTS
Digital Outputs and Timing
The AD9434 differential outputs conform to the ANSI-644
LVDS standard on default power-up. This can be changed to a
low power, reduced signal option similar to the IEEE 1596.3
standard using the SPI. This LVDS standard can further reduce
the overall power dissipation of the device, which reduces the
power by ~39 mW. See the Memory Map section for more infor-
mation. The LVDS driver current is derived on chip and sets
the output current at each output equal to a nominal 3.5 mA.
A 100 ꢁ differential termination resistor placed at the LVDS
receiver inputs results in a nominal 350 mV swing at the receiver.
SNR Degradation = 20 × log10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 48).
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9434. Separate power
supplies for clock drivers from the ADC output driver supplies
to avoid modulating the clock signal with digital noise. Low
jitter, crystal-controlled oscillators make the best clock sources.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the
original clock at the last step.
The AD9434 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 ꢁ termination resistor placed as close to the receiver as
possible. No far end receiver termination or poor differential
trace routing may result in timing errors. It is recommended
that the trace length be no longer than 24 inches and that the
differential output traces be kept close together and at equal
lengths.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).
130
RMS CLOCK JITTER REQUIREMENT
120
110
An example of the LVDS output using the ANSI standard (default)
data eye and a time interval error (TIE) jitter histogram with
trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 49. Figure 50 shows an example of when the
trace lengths exceed 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is up to
the user to determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.
16 BITS
14 BITS
12 BITS
100
90
80
70
60
50
40
30
10 BITS
8 BITS
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
1
10
100
1000
ANALOG INPUT FREQUENCY (MHz)
Figure 48. Ideal SNR vs. Input Frequency and Jitter
Rev. A | Page 21 of 28
AD9434
14
12
10
8
Out-of-Range (OR)
500
400
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR+ and OR− (OR )
are digital outputs that are updated along with the data output
corresponding to the particular sampled input voltage. Thus,
OR has the same pipeline latency as the digital data. OR is
low when the analog input voltage is within the analog input
range and high when the analog input voltage exceeds the input
range, as shown in Figure 51. OR remains high until the analog
input returns to within the input range and another conversion
is completed. By logically AND’ing OR with the MSB and its
complement, overrange high or underrange low conditions can
be detected.
300
200
100
0
6
–100
–200
–300
–400
–500
4
2
0
–40
–3 –2 –1
0
1
2
3
–20
0
20
40
TIME (ns)
TIME (ps)
+FS – 1 LSB
OR± DATA OUTPUTS
Figure 49. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less
than 24 Inches on Standard FR-4, AD9434-500
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
OR±
600
400
200
0
12
10
8
–FS + 1/2 LSB
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
–FS
–FS – 1/2 LSB
+FS
+FS – 1/2 LSB
6
Figure 51. OR Relation to Input Voltage and Output Data
TIMING
–200
–400
–600
4
The AD9434 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propaga-
tion delay (tPD) after the rising edge of the clock signal.
2
0
–100
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9434. These transi-
ents can degrade the dynamic performance of the converter.
The AD9434 also provides a data clock output (DCO) intended
for capturing the data in an external register. The data outputs are
valid on the rising edge of DCO.
–3 –2 –1
0
1
2
3
0
100
TIME (ns)
TIME (ps)
Figure 50. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, AD9434-500
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 12.
If it is desired to change the output data format to twos comple-
ment, see the AD9434 Configuration Using the SPI section.
The lowest conversion rate of the AD9434 is 50 MSPS. At clock
rates below 1 MSPS, the AD9434 assumes the standby mode.
An output clock signal is provided to assist in capturing data
from the AD9434. The DCO is used to clock the output data
and is equal to the sampling clock (CLK) rate. In single data
rate mode (SDR), data is clocked out of the AD9434 and must
be captured on the rising edge of the DCO. In double data rate
mode (DDR), data is clocked out of the AD9434 and must be
captured on the rising and falling edges of the DCO. See the
timing diagrams shown in Figure 2 and Figure 3 for more
information.
VREF
The AD9434 VREF pin (Pin 31) allows the user to monitor the
on-board voltage reference, or provide an external reference
(requires configuration through the SPI). The three optional
settings are internal VREF (pin is connected to 20 kꢁ to ground),
export VREF, and import VREF. Do not attach a bypass capacitor
to this pin. VREF is internally compensated and additional
loading may impact performance.
AD9434 CONFIGURATION USING THE SPI
Output Data Rate and Pinout Configuration
The AD9434 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or readback) serially in
1-byte words. Each byte can be further divided into fields,
which are documented in the Memory Map section.
The output data of the AD9434 can be configured to drive 12
pairs of LVDS outputs at the same rate as the input clock signal
(SDR mode), or six pairs of LVDS outputs at 2× the rate of the
input clock signal (DDR mode). SDR is the default mode; the
device can be reconfigured for DDR by setting Bit 3 in Register 14
(see Table 13).
Rev. A | Page 22 of 28
AD9434
There are three pins that define the serial port interface (SPI) to
this particular ADC. They are the SCLK/DFS, SDIO, and CSB
pins. The SCLK/DFS (serial clock) is used to synchronize the
read and write data presented to the ADC. The SDIO (serial
data input/output) is a dual-purpose pin that allows data to be
sent to and read from the internal ADC memory map registers.
The CSB is an active low control that enables or disables the
read and write cycles (see Table 9).
the W0 and W1 bits, which is one or more bytes of data. All
data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether this is a read or write com-
mand. This allows the serial data input/output (SDIO) pin to
change direction from an input to an output.
Data can be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI at www.analog.com.
USING THE AD9434 TO REPLACE THE AD9230
The AD9434 can be used to replace the AD9230 in many
applications. In these designs, the user should consider these
important differences:
HARDWARE INTERFACE
The pins described in Table 9 comprise the physical interface
between the programming device of the user and the serial port
of the AD9434. The SCLK pin and the CSB pin function as
inputs when using the SPI interface. The SDIO pin is bidirec-
tional, functioning as an input during the write phase and as an
output during readback.
•
Pin 28 is a DNC (do not connect) on the AD9434, and
should be left floating. The reset functionality of the
AD9230 is not available through an external pin, but is
available through the SPI interface.
•
Pin 31 is the interface to the AD9434 reference circuit. It
can be used to monitor the internal reference or provide an
external reference voltage (nominally 0.5 V). If the internal
reference is used, then this pin can float. The RBIAS func-
tion of the AD9230 is not necessary with the AD9434.
The input voltage range of the AD9434 is nominally
1.5 V p-p, whereas the AD9230 input range is 1.25 V p-p.
This interface is flexible enough to be controlled by either
PROMs or PIC® mirocontrollers as well. This provides the user
with an alternate method to program the ADC other than a SPI
controller.
•
If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device power-
on. The Configuration Without the SPI section describes the
strappable functions supported on the AD9434.
Table 9. Serial Port Pins
Mnemonic
Function
SCLK
SCLK (serial clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SCLK/DFS pin can alternately serve as a standalone CMOS-
compatible control pin. In this mode, connect the CSB pin to
AVDD, which disables the serial port interface.
SDIO
SDIO (serial data input/output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (chip select) is an active low control that
gates the read and write cycles.
CSB
Table 10. Mode Selection
External
Voltage
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 52
and Table 11.
Mnemonic
Configuration
SCLK/DFS
AVDD
AGND
Twos complement enabled
Offset binary enabled
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
Rev. A | Page 23 of 28
AD9434
tDS
tHIGH
tCLK
tH
tS
tDH
tLOW
CSB
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
R/W
DON’T CARE
Figure 52. Serial Port Interface Timing Diagram
Table 11. Serial Timing Definitions
Parameter
Min (ns)
Description
tDS
tDH
tCLK
tS
5
2
ꢀ±
5
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
tH
2
Hold time between CSB and SCLK
tHIGH
tLOW
tEN_SDIO
1ꢁ
1ꢁ
1
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 52)
tDIS_SDIO
5
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 52)
Table 12. Output Data Format
Input (V)
Condition (V)
< −±.75 − ±.5 LSB
= −±.75
= ±
= ±.75
Offset Binary Output Mode, D11 to D0 Twos Complement Mode, D11 to D0
OR
1
±
±
±
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
±±±± ±±±± ±±±±
±±±± ±±±± ±±±±
1±±± ±±±± ±±±±
1111 1111 1111
1111 1111 1111
1±±± ±±±± ±±±±
1±±± ±±±± ±±±±
±±±± ±±±± ±±±±
±111 1111 1111
±111 1111 1111
> ±.75 + ±.5 LSB
1
Rev. A | Page 2ꢀ of 28
AD9434
MEMORY MAP
READING THE MEMORY MAP TABLE
RESERVED LOCATIONS
Each row in the memory map table (see Table 13) has eight
address locations. The memory map is roughly divided into
three sections: chip configuration register map (Address 0x00 to
Address 0x02), transfer register map (Address 0xFF), and ADC
functions register map (Address 0x08 to Address 0x2A).
Undefined memory locations should not be written to other
than with the default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
The Addr. (Hex) column of the memory map indicates the
register address in hexadecimal, and the Default Value (Hex)
column shows the default hexadecimal value that is already
written into the register. The Bit 7 (MSB) column is the start of
the default hexadecimal value given. For example, Hexadecimal
Address 0x2A, OVR_CONFIG, has a hexadecimal default value
of 0x01. This means that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0,
Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in
binary. The default value enables the OR output. Overwriting
this default so that Bit 0 = 0 disables the OR output. For more
information on this and other functions, consult the AN-877
Application Note, Interfacing to High-Speed ADCs via SPI® at
www.analog.com.
Exiting out of reset, critical registers are preloaded with default
values. These values are indicated in Table 13. Other registers
do not have default values and retain the previous value when
exiting reset.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
Table 13. Memory Map Register
Default
Addr.
Bit 7
(MSB)
Bit 0
(LSB)
Value
(Hex)
Default Notes/
Comments
(Hex) Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Chip Configuration Registers
±±
CHIP_PORT_CONFIG
±
LSB
first
Soft
reset
1
1
Soft
reset
LSB
first
±
±x18
The nibbles
should be
mirrored by the
user so that LSB
or MSB first
mode registers
correctly,
regardless of
shift mode.
±1
±2
CHIP_ID
8-bit chip ID, Bits[7:±] = ±xꢁA
Read
only
Default is a
unique chip ID,
different for
each device.
This is a read-
only register.
CHIP_GRADE
±
±
±
±
±
±
Speed grade:
±± = 5±± MSPS
±1 = 37± MSPS
X1
X1
±
X1
Read
only
Child ID used to
differentiate
graded devices.
Transfer Register
FF
DEVICE_UPDATE
±
±
±
±
SW
transfer
±x±±
Synchronously
transfers data
from the master
shift register to
the slave.
ADC Functions Registers
±8
Modes
±
±
PDWN:
± = full
(default)
1 =
±
Internal power-down mode:
±±± = normal (power-up,
default)
±±1 = full power-down
±1± = standby
±x±±
Determines
various generic
modes of chip
operation.
standby
±11 = normal (power-up)
Note that external PDWN pin
overrides this setting
Rev. A | Page 25 of 28
AD9434
Default
Value
(Hex)
Addr.
Bit 7
(MSB)
Bit 0
(LSB)
Default Notes/
Comments
(Hex) Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
10
Offset
8-bit device offset adjustment [7:0]
0111 1111 = +127 codes
0000 0000 = 0 codes
0x00
Device offset
trim: codes are
relative to the
output
1000 0000 = −128 codes
resolution.
0D
TEST_IO
(For user-defined
mode only, set
Bits[3:0] = 1000)
Reset
PN23
gen:
Reset
PN9
gen:
1 = on
0 = off
Output test mode:
0000 = off (default)
0001 = midscale short
0010 = +FS short
0x00
When set, the
test data is
placed on the
output pins in
place of normal
data.
Set pattern
values:
P1 = Reg 0x19,
Reg 0x1A
00 = Pattern 1 only 1 = on
01 = toggle P1/P2
10 = toggle
P1/0000
11 = toggle P1/P2/
0000
0 = off
(default) (default)
0011 = −FS short
0100 = checkerboard output
0101 = PN23 sequence
0110 = PN9
0111 = one/zero word toggle
1000 = user defined
1001 = unused
P2 = Reg 0x1B,
Reg 0x1C.
1010 = unused
1011 = unused
1100 = unused
(Format determined by OUTPUT_MODE)
0F
14
AIN_CONFIG
0
0
0
0
0
0
0
Analog
input
disable:
1 = on
0 = off
(default)
0
0
0x00
0x00
OUTPUT_MODE
0
0
Output
enable:
0 =
enable
(default)
1 =
DDR:
1 =
enabled
0 =
disabled (default)
(default)
Output
invert:
1 = on
0 = off
Data format select:
00 = offset binary
(default)
01 = twos
complement
10 = Gray code
disable
15
16
17
OUTPUT_ADJUST
OUTPUT_PHASE
0
0
0
0
0
0
0
0
0
LVDS
LVDS fine adjust:
001 = 3.50 mA
0x00
0x00
0x00
course
adjust:
0 =
3.5 mA
(default)
1 =
010 = 3.25 mA
011 = 3.00 mA
100 = 2.75 mA
101 = 2.50 mA
110 = 2.25 mA
111 = 2.00 mA
2.0 mA
Output
clock
polarity
1 =
inverted
0 =
normal
(default)
0
0
0
0
FLEX_OUTPUT_DELAY
0
Output clock delay:
0000 = 0
Shown as
fractional value
of sampling
clock period
that is
subtracted or
added to initial
0001 = −1/10
0010 = −2/10
0011 = −3/10
0100 = reserved
0101 = +5/10
0110 = +4/10
0111 = +3/10
1000 = +2/10
1001 = +1/10
tSKEW, see
Figure 2
Rev. A | Page 26 of 28
AD9434
Default
Value
(Hex)
Addr.
Bit 7
(MSB)
Bit 0
(LSB)
Default Notes/
Comments
(Hex) Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
18
FLEX_VREF
VREF select
±
Input voltage range setting:
±x±±
±± = internal VREF
(2± kΩ pull-down)
±1 = import VREF
(±.59 V to ±.8 V on
VREF pin)
1± = export VREF
(from internal
reference)
111±± = 1.ꢁ±
±±1±1 = 1.3ꢁ
±±11± = 1.3ꢀ
±±111 = 1.31
±1±±± = 1.28
±1±±1 = 1.2ꢁ
±1±1± = 1.23
±1±11 = 1.2±
±11±± = 1.18
111±1 = 1.58
1111± = 1.55
11111 = 1.52
±±±±± = 1.5±
±±±±1 = 1.ꢀ7
±±±1± = 1.ꢀꢀ
±±±11 = 1.ꢀ2
±±1±± = 1.39
B3
11 = not used
19
1A
1B
1C
2A
USER_PATT1_LSB
USER_PATT1_MSB
USER_PATT2_LSB
USER_PATT2_MSB
OVR_CONFIG
B7
Bꢁ
Bꢁ
Bꢁ
Bꢁ
±
B5
B5
B5
B5
±
Bꢀ
Bꢀ
Bꢀ
Bꢀ
±
B2
B2
B2
B2
±
B1
B±
±x±±
±x±±
±x±±
±x±±
±x±1
User-defined
pattern, 1 LSB.
B7
B7
B7
±
B3
B3
B3
±
B1
B±
User-defined
pattern, 1 MSB.
B1
B±
User-defined
pattern, 2 LSBs.
B1
B±
User-defined
pattern, 2 MSBs.
OR±
OR±
position enable:
(DDR
mode
only):
± =
1 = on
(default)
± = off
Pin 9,
Pin 1±
1 =
Pin 21,
Pin 22
2C
Input coupling
±
±
±
±
±
DC
coupling
enable
±
±
±x±±
Default is
ac coupling.
1 X = don’t care.
Rev. A | Page 27 of 28
AD9434
OUTLINE DIMENSIONS
0.30
0.23
0.18
8.10
0.60 MAX
8.00 SQ
7.90
0.60
MAX
PIN 1
INDICATOR
43
42
56
1
0.50
BSC
PIN 1
INDICATOR
7.85
EXPOSED
PAD
7.75 SQ
7.65
5.25
5.10 SQ
4.95
14
29
28
15
0.50
0.40
0.30
0.25 MIN
BOTTOM VIEW
6.50 REF
TOP VIEW
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.20 REF
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
Figure 53. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
8 mm × 8 mm Body, Very Thin Quad
(CP-56-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
AD9434BCPZ-370
AD9434BCPZRL7-370
AD9434BCPZ-500
AD9434BCPZRL7-500
AD9434-370EBZ
AD9434-500EBZ
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
LVDS Evaluation Board with AD9434BCPZ-370
LVDS Evaluation Board with AD9434BCPZ-500
CP-56-5
CP-56-5
CP-56-5
CP-56-5
1 Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09383-0-5/11(A)
Rev. A | Page 28 of 28
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