AD9516-3/PCBZ_技术文档

14-Output Clock Generator with

Integrated 2.0 GHz VCO

AD9516-3

FUNCTIONAL BLOCK DIAGRAM

FEATURES

CP

LF

Low phase noise, phase-locked loop

On-chip VCO tunes from 1.75 GHz to 2.25 GHz

External VCO/VCXO to 2.4 GHz optional

1 differential or 2 single-ended reference inputs

Reference monitoring capability

Auto and manual reference switchover/holdover modes

Autorecover from holdover

Accepts references to 250 MHz

Programmable delays in path to PFD

Digital or analog lock detect, selectable

3 pairs of 1.6 GHz LVPECL outputs

Each pair shares 1 to 32 dividers with coarse phase delay

Additive output jitter 225 f_Srms

Channel-to-channel skew paired outputs <10 ps

2 pairs of 800 MHz LVDS clock outputs

Each pair shares two cascaded 1 to 32 dividers with coarse

phase delay

REF1

REF2

STATUS

MONITOR

REFIN

CLK

VCO

DIVIDER

AND MUXs

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

DIV/Φ

LVPECL

ΔT

DIV/Φ

LVDS/CMOS

SERIAL CONTROL PORT

AND

Additive output jitter 275 f_Srms

AD9516-3

DIGITAL LOGIC

Fine delay adjust (ΔT) on each LVDS output

Eight 250 MHz CMOS outputs (two per LVDS output)

Automatic synchronization of all outputs on power-up

Manual synchronization of outputs as needed

Serial control port

Figure 1.

The AD9516-3 features six LVPECL outputs (in three pairs);

four LVDS outputs (in two pairs); and eight CMOS outputs

(two per LVDS output). The LVPECL outputs operate to 1.6 GHz,

the LVDS outputs operate to 800 MHz, and the CMOS outputs

operate to 250 MHz.

64-lead LFCSP

APPLICATIONS

Each pair of outputs has dividers that allow both the divide

ratio and coarse delay (or phase) to be set. The range of division

for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs

allow a range of divisions up to a maximum of 1024.

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

The AD9516-3 is available in a 64-lead LFCSP and can be

operated from a single 3.3 V supply. An external VCO, which

requires an extended voltage range, can be accommodated

by connecting the charge pump supply (VCP) to 5.5 V. A

separate LVPECL power supply can be from 2.375 V to 3.6 V.

ATE

GENERAL DESCRIPTION

The AD9516-3¹provides a multi-output clock distribution

function with subpicosecond jitter performance, along with an on-

chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to

2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz

may be used.

The AD9516-3 is specified for operation over the standard

industrial range of −40°C to +85°C.

¹AD9516 is used throughout to refer to all the members of the AD9516

family. However, when AD9516-3 is used, it is referring to that specific

member of the AD9516 family.

The AD9516-3 emphasizes low jitter and phase noise to

maximize data converter performance, and it can benefit other

applications with demanding phase noise and jitter requirements.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9516-3

TABLE OF CONTENTS

Features .............................................................................................. 1

Phase-Locked Loop (PLL) .................................................... 33

Configuration of the PLL...................................................... 33

Phase Frequency Detector (PFD) ........................................ 33

Charge Pump (CP)................................................................. 34

On-Chip VCO ........................................................................ 34

PLL External Loop Filter....................................................... 34

PLL Reference Inputs............................................................. 34

Reference Switchover............................................................. 35

Reference Divider R............................................................... 35

VCXO/VCO Feedback Divider N: P, A, B, R ..................... 35

Digital Lock Detect (DLD) ....................................................... 37

Analog Lock Detect (ALD)................................................... 37

Current Source Digital Lock Detect (DLD) ....................... 37

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Power Supply Requirements ....................................................... 4

PLL Characteristics ...................................................................... 4

Clock Inputs .................................................................................. 6

Clock Outputs............................................................................... 6

Timing Characteristics ................................................................ 7

Clock Output Additive Phase Noise (Distribution Only; VCO

Divider Not Used) ........................................................................ 8

Clock Output Absolute Phase Noise (Internal VCO Used).... 9

CLK

External VCXO/VCO Clock Input (CLK/

)................ 37

Clock Output Absolute Time Jitter (Clock Generation Using

Internal VCO)............................................................................. 10

Holdover.................................................................................. 38

Manual Holdover Mode........................................................ 38

Automatic/Internal Holdover Mode.................................... 38

Frequency Status Monitors ................................................... 39

VCO Calibration .................................................................... 40

Clock Distribution ..................................................................... 41

Internal VCO or External CLK as Clock Source ............... 41

CLK or VCO Direct to LVPECL Outputs........................... 41

Clock Frequency Division..................................................... 42

VCO Divider........................................................................... 42

Channel Dividers—LVPECL Outputs................................. 42

Channel Dividers—LVDS/CMOS Outputs........................ 44

Synchronizing the Outputs—SYNC Function................... 47

Clock Outputs......................................................................... 49

LVPECL Outputs: OUT0 to OUT5 ..................................... 49

LVDS/CMOS Outputs: OUT6 to OUT9............................. 50

Reset Modes ................................................................................ 50

Clock Output Absolute Time Jitter (Clock Cleanup Using

Internal VCO)............................................................................. 10

Clock Output Absolute Time Jitter (Clock Generation Using

External VCXO) ......................................................................... 10

Clock Output Additive Time Jitter (VCO Divider Not Used)....11

Clock Output Additive Time Jitter (VCO Divider Used) ..... 11

Delay Block Additive Time Jitter.............................................. 12

Serial Control Port ..................................................................... 12

,

, and

Pins ..................................................... 13

RESET

PD SYNC

LD, STATUS, REFMON Pins.................................................... 13

Power Dissipation....................................................................... 14

Timing Diagrams............................................................................ 15

Absolute Maximum Ratings.......................................................... 16

Thermal Resistance .................................................................... 16

ESD Caution................................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Typical Performance Characteristics ........................................... 19

Terminology .................................................................................... 25

Detailed Block Diagram ................................................................ 26

Theory of Operation ...................................................................... 27

Operational Configurations...................................................... 27

Power-On Reset—Start-Up Conditions When V_SIs

Applied .................................................................................... 50

RESET

Asynchronous Reset via the

Pin ............................. 50

Soft Reset via 0x00<5> .......................................................... 50

Power-Down Modes .................................................................. 50

PD

Chip Power-Down via

.................................................... 50

High Frequency Clock Distribution—CLK or External

VCO >1600 MHz ................................................................... 27

PLL Power-Down................................................................... 51

Distribution Power-Down .................................................... 51

Individual Clock Output Power-Down............................... 51

Internal VCO and Clock Distribution................................. 29

Clock Distribution or External VCO <1600 MHz............. 31

Rev. 0 | Page 2 of 84

AD9516-3

Individual Circuit Block Power-Down ................................51

Serial Control Port ..........................................................................52

Serial Control Port Pin Descriptions........................................52

General Operation of Serial Control Port ...............................52

Communication Cycle—Instruction Plus Data..................52

Write .........................................................................................52

Read ..........................................................................................53

The Instruction Word (16 Bits).................................................53

MSB/LSB First Transfers ............................................................53

Register Map Overview ..................................................................56

Register Map Descriptions.............................................................60

Application Notes............................................................................79

Using the AD9516 Outputs for ADC Clock Applications ....79

LVPECL Clock Distribution......................................................79

LVDS Clock Distribution...........................................................79

CMOS Clock Distribution.........................................................80

Outline Dimensions........................................................................81

Ordering Guide ...........................................................................81

REVISION HISTORY

6/07—Revision 0: Initial Version

Rev. 0 | Page 3 of 84

AD9516-3

SPECIFICATIONS

Typical (typ) is given for V_S= V_{S_LVPECL}= 3.3 V 5ꢀ; V_S≤ V_CP≤ 5.25 V; T_A= 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ,

unless otherwise noted. Minimum (min) and maximum (max) values are given over full V_Sand T_A(−40°C to +85°C) variation.

POWER SUPPLY REQUIREMENTS

Table 1.

Parameter

Min

Typ Max

Unit Test Conditions/Comments

V_S

V_{S_LVPECL}

V_CP

RSET Pin Resistor

CPRSET Pin Resistor

3.135 3.3

2.375

V_S

3.465

V_S

5.25

V

kΩ

This is 3.3 V 5%

This is nominally 2.5 V to 3.3 V 5%

This is nominally 3.3 V to 5.0 V 5%

Sets internal biasing currents; connect to ground

4.12

5.1

Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);

actual current can be calculated by: CP_lsb = 3.06/CPRSET; connect to ground

BYPASS Pin Capacitor

220

nF

Bypass for internal LDO regulator; necessary for LDO stability; connect to ground

PLL CHARACTERISTICS

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VCO (ON-CHIP)

Frequency Range

1750

0.5

2250

MHz

MHz/V

V

See Figure 15

See Figure 10

V_CP≤ V_Swhen using internal VCO; outside of this

range, the CP spurs may increase due to CP up/

down mismatch

VCO Gain (K_VCO

)

50

Tuning Voltage (V_T)

V_CP− 0.5

Frequency Pushing (Open-Loop)

Phase Noise @ 100 kHz Offset

Phase Noise @ 1 MHz Offset

REFERENCE INPUTS

1

MHz/V

dBc/Hz

−108

−126

f = 2000 MHz

Differential Mode (REFIN, REFIN)

Differential mode (can accommodate single-

ended input by ac grounding undriven input)

Input Frequency

Input Sensitivity

0

250

MHz

Frequencies below about 1 MHz should be

dc-coupled; be careful to match V_CM(self-bias voltage)

250

mV p-p PLL figure of merit increases with increasing

slew rate; see Figure 14

Self-Bias Voltage, REFIN

Input Resistance, REFIN

1.35

1.30

4.0

1.60

1.50

4.8

1.75

1.60

5.9

V

Self-bias voltage of REFIN¹

Self-biased¹

kΩ

4.4

5.3

6.4

Self-biased¹

Dual Single-Ended Mode (REF1, REF2)

Input Frequency (AC-Coupled)

Input Frequency (DC-Coupled)

Input Sensitivity (AC-Coupled)

Input Logic High

Input Logic Low

Input Current

Input Capacitance

Two single-ended CMOS-compatible inputs

Slew rate > 50V/μs

Slew rate > 50V/μs; CMOS levels

Should not exceed V_Sp-p

20

0

250

MHz

V p-p

V

μA

0.8

2

2.0

0.8

+100

−100

pF

Each pin, REFIN/REFIN (REF1/REF2)

Rev. 0 | Page 4 of 84

AD9516-3

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PHASE/FREQUENCY DETECTOR (PFD)

PFD Input Frequency

100

45

MHz

ns

Antibacklash pulse width = 1.3 ns, 2.9 ns

Antibacklash pulse width = 6.0 ns

0x17<1:0> = 01b

0x17<1:0> = 00b; 0x17<1:0> = 11b

0x17<1:0> = 10b

Antibacklash Pulse Width

1.3

2.9

6.0

CHARGE PUMP (CP)

I_CPSink/Source

Programmable

High Value

Low Value

4.8

0.60

2.5

2.7/10

1

2

1.5

2

mA

%

kΩ

nA

%

With CPRSET = 5.1 kΩ

Absolute Accuracy

CPRSET Range

I_CPHigh Impedance Mode Leakage

Sink-and-Source Current Matching

I_CPvs. V_CP

I_CPvs. Temperature

PRESCALER (PART OF N DIVIDER)

Prescaler Input Frequency

P = 1 FD

V_CP= VCP/2

0.5 < V_CP< VCP − 0.5 V

V_CP= VCP/2 V

%

300

600

900

600

1000

2400

3000

300

MHz

P = 2 FD

P = 3 FD

P = 2 DM (2/3)

P = 4 DM (4/5)

P = 8 DM (8/9)

P = 16 DM (16/17)

P = 32 DM (32/33)

Prescaler Output Frequency

A, B counter input frequency (prescaler

input frequency divided by P)

PLL DIVIDER DELAYS

Register 0x19: R<5:3>, N<2:0>; see Table 52

000

001

010

011

100

101

110

111

off

ps

330

440

550

660

770

880

990

NOISE CHARACTERISTICS

In-Band Phase Noise of the Charge

Pump/Phase Frequency Detector

(In-Band Means Within the LBW

of the PLL)

The PLL in-band phase noise floor is estimated

by measuring the in-band phase noise at the

output of the VCO and subtracting 20 log(N)

(where N is the value of the N divider)

@ 500 kHz PFD Frequency

@ 1 MHz PFD Frequency

@ 10 MHz PFD Frequency

@ 50 MHz PFD Frequency

PLL Figure of Merit (FOM)

−165

−162

−151

−143

−220

dBc/Hz

Reference slew rate > 0.25 V/ns. FOM +10 log(f_PFD

is an approximation of the PFD/CP in-band

phase noise (in the flat region) inside the PLL

loop bandwidth; when running closed loop,

the phase noise, as observed at the VCO output,

is increased by 20 log(N)

)

Rev. 0 | Page 5 of 84

AD9516-3

Parameter

PLL DIGITAL LOCK DETECT WINDOW²

Min

Typ

Max

Unit

Test Conditions/Comments

Signal available at LD, STATUS, and REFMON pins

when selected by appropriate register settings

Required to Lock (Coincidence of Edges)

Low Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 6 ns)

Selected by 0x17<1:0> and 0x18<4>

0x17<1:0> = 00b, 01b,11b; 0x18<4> = 1b

0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b

0x17<1:0> = 10b; 0x18<4> = 0b

3.5

7.5

3.5

ns

To Unlock After Lock (Hysteresis)²

Low Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 1.3 ns, 2.9 ns)

High Range (ABP 6 ns)

7

15

11

ns

0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 1b

0x17<1:0> = 00b, 01b, 11b; 0x18<4> = 0b

0x17<1:0> = 10b; 0x18<4> = 0b

1

REFIN

REFIN and

self-bias points are offset slightly to avoid chatter on an open input condition.

²For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.

CLOCK INPUTS

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOCK INPUTS (CLK, CLK)

Input Frequency

Differential input

0¹

2.4

1.6

GHz

High frequency distribution (VCO divider)

Distribution only (VCO divider bypassed)

Input Sensitivity, Differential

Input Level, Differential

150

mV p-p

Measured at 2.4 GHz; jitter performance is improved

with slew rates > 1 V/ns

Larger voltage swings may turn on the protection

diodes and can degrade jitter performance

2

V p-p

Input Common-Mode Voltage, V_CM

Input Common-Mode Range, V_CMR

Input Sensitivity, Single-Ended

Input Resistance

1.3

1.57

1.8

V

Self-biased; enables ac coupling

With 200 mV p-p signal applied; dc-coupled

CLK ac-coupled; CLK ac-bypassed to RF ground

Self-biased

150

4.7

2

mV p-p

kΩ

pF

3.9

5.7

Input Capacitance

¹Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V_CM

.

CLOCK OUTPUTS

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL CLOCK OUTPUTS

OUT0, OUT1, OUT2, OUT3, OUT4, OUT5

Output Frequency, Maximum

Output High Voltage (V_OH)

Output Low Voltage (V_OL)

Output Differential Voltage (V_OD)

LVDS CLOCK OUTPUTS

OUT6, OUT7, OUT8, OUT9

Output Frequency

Termination = 50 Ω to V_S− 2 V

OUT

Differential (OUT,

)

2950

MHz

V

Using direct to output; see Figure 25

V_S− 1.12

V_S− 2.03

550

V_S− 0.98

V_S− 1.77

790

V_S− 0.84

V_S− 1.49

980

mV

Differential termination 100 Ω @ 3.5 mA

OUT

Differential (OUT,

See Figure 26

)

800

454

25

1.375

25

MHz

mV

V

mV

mA

Differential Output Voltage (V_OD)

Delta V_OD

Output Offset Voltage (V_OS)

Delta V_OS

247

360

1.24

14

1.125

Short-Circuit Current (I_SA, I_SB)

24

Output shorted to GND

Rev. 0 | Page 6 of 84

AD9516-3

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CMOS CLOCK OUTPUTS

OUT6A, OUT6B, OUT7A, OUT7B, OUT8A,

OUT8B, OUT9A, OUT9B

Single-ended; termination = 10 pF

Output Frequency

Output Voltage High (V_OH)

Output Voltage Low (V_OL)

250

0.1

MHz

V

see Figure 27

@ 1 mA load

V_S− 0.1

TIMING CHARACTERISTICS

Table 5.

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

LVPECL

Output Rise Time, t_RP

Output Fall Time, t_FP

Termination = 50 Ω to V_S− 2 V; level = 810 mV

20% to 80%, measured differentially

80% to 20%, measured differentially

70

180

ps

PROPAGATION DELAY, t_PECL, CLK-TO-LVPECL OUTPUT

High Frequency Clock Distribution Configuration

Clock Distribution Configuration

Variation with Temperature

OUTPUT SKEW, LVPECL OUTPUTS¹

LVPECL Outputs That Share the Same Divider

LVPECL Outputs on Different Dividers

All LVPECL Outputs Across Multiple Parts

LVDS

835

773

995

933

0.8

1180 ps

1090 ps

See Figure 42

See Figure 44

ps/°C

5

13

15

ps

40

220

ps

Termination = 100 Ω differential; 3.5 mA

20% to 80%, measured differentially²

Delay off on all outputs

Output Rise Time, t_RL

Output Fall Time, t_FL

170

160

350

ps

PROPAGATION DELAY, t_LVDS, CLK-TO-LVDS OUTPUT

OUT6, OUT7, OUT8, OUT9

For All Divide Values

1.4

1.8

2.1

ns

Variation with Temperature

OUTPUT SKEW, LVDS OUTPUTS¹

LVDS Outputs That Share the Same Divider

LVDS Outputs on Different Dividers

All LVDS Outputs Across Multiple Parts

CMOS

1.25

ps/°C

Delay off on all outputs

6

25

62

150

430

ps

Termination = open

20% to 80%; C_LOAD= 10 pF

80% to 20%; C_LOAD= 10 pF

Fine delay off

Output Rise Time, t_RC

Output Fall Time, t_FC

495

475

1000 ps

985

ps

PROPAGATION DELAY, t_CMOS, CLK-TO-CMOS OUTPUT

For All Divide Values

1.6

2.1

2.6

ns

ps/°C

Variation with Temperature

OUTPUT SKEW, CMOS OUTPUTS¹

CMOS Outputs That Share the Same Divider

All CMOS Outputs on Different Dividers

All CMOS Outputs Across Multiple Parts

DELAY ADJUST³

Shortest Delay Range⁴

Zero Scale

Full Scale

Longest Delay Range⁴

Fine delay off

4

28

66

180

675

ps

LVDS and CMOS

0xA1 (0xA4) (0xA7) (0xAA) <5:0> 101111b

0xA2 (0xA5) (0xA8) (0xAB) <5:0> 000000b

0xA2 (0xA5) (0xA8) (0xAB) <5:0> 101111b

0xA1 (0xA4) (0xA7) (0xAA) <5:0> 000000b

0xA2 (0xA5) (0xA8) (0xAB) <5:0> 000000b

0xA2 (0xA5) (0xA8) (0xAB) <5:0> 001100b

0xA2 (0xA5) (0xA8) (0xAB) <5:0> 101111b

50

540

315

880

680

ps

1180 ps

Zero Scale

Quarter Scale

Full Scale

200

570

1.72 2.31

5.7 8.0

950

2.89

10.1

ps

ns

Rev. 0 | Page 7 of 84

AD9516-3

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

Delay Variation with Temperature

Short Delay Range⁵

Zero Scale

Full Scale

Long Delay Range⁵

0.23

−0.02

ps/°C

Zero Scale

Full Scale

0.3

0.24

ps/°C

¹This is the difference between any two similar delay paths while operating at the same voltage and temperature.

²Corresponding CMOS drivers set to A for noninverting, and B for inverting.

³The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.

⁴Incremental delay; does not include propagation delay.

⁵All delays between zero scale and full scale can be estimated by linear interpolation.

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK-TO-LVPECL ADDITIVE PHASE NOISE

Distribution section only; does not

include PLL and VCO

CLK = 1 GHz, OUTPUT = 1 GHz

Divider = 1

Input slew rate > 1 V/ns

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

@ 10 MHz Offset

@ 100 MHz Offset

CLK = 1 GHz, OUTPUT = 200 MHz

Divider = 5

−109

−118

−130

−139

−144

−146

−147

−149

dBc/Hz

Input slew rate > 1 V/ns

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

>10 MHz Offset

−120

−126

−139

−150

−155

−157

dBc/Hz

CLK-TO-LVDS ADDITIVE PHASE NOISE

Distribution section only; does not

include PLL and VCO

CLK = 1.6 GHz, OUTPUT = 800 MHz

Divider = 2

Input slew rate > 1 V/ns

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

−103

−110

−120

−127

−133

−138

−147

−149

dBc/Hz

@ 10 MHz Offset

@ 100 MHz Offset

Rev. 0 | Page 8 of 84

AD9516-3

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLK = 1.6 GHz, OUTPUT = 400 MHz

Divider = 4

Input slew rate > 1 V/ns

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

>10 MHz Offset

−114

−122

−132

−140

−146

−150

−155

dBc/Hz

CLK-TO-CMOS ADDITIVE PHASE NOISE

Distribution section only; does not

include PLL and VCO

CLK = 1 GHz, OUTPUT = 250 MHz

Divider = 4

Input slew rate > 1 V/ns

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

>10 MHz Offset

CLK = 1 GHz, OUTPUT = 50 MHz

Divider = 20

−110

−120

−127

−136

−144

−147

−154

dBc/Hz

Input slew rate > 1 V/ns

@ 10 Hz Offset

@ 100 Hz Offset

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

−124

−134

−142

−151

−157

−160

−163

dBc/Hz

>10 MHz Offset

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL ABSOLUTE PHASE NOISE

VCO = 2.25 GHz; OUTPUT = 2.25 GHz

@ 1 kHz Offset

InternalVCO; direct to LVPECL output

−49

−79

−104

−123

−143

−147

dBc/Hz

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

@ 10 MHz Offset

@ 40 MHz Offset

VCO = 2.00 GHz; OUTPUT = 2.00 GHz

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

−53

−83

−108

−126

−142

−147

dBc/Hz

@ 10 MHz Offset

@ 40 MHz Offset

Rev. 0 | Page 9 of 84

AD9516-3

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VCO = 1.75 GHz; OUTPUT = 1.75 GHz

@ 1 kHz Offset

@ 10 kHz Offset

@ 100 kHz Offset

@ 1 MHz Offset

@ 10 MHz Offset

@ 40 MHz Offset

−54

−88

−112

−130

−143

−147

dBc/Hz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)

Table 8.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical

setup where the reference source is

clean, so a wider PLL loop bandwidth is

used; reference = 15.36 MHz; R = 1

VCO = 1.97 GHz; LVPECL = 245.76 MHz; PLL LBW = 143 kHz

VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 143 kHz

VCO = 1.97 GHz; LVPECL = 61.44 MHz; PLL LBW = 143 kHz

129

303

135

302

179

343

f_Srms Integration BW = 200 kHz to 10 MHz

f_Srms Integration BW = 12 kHz to 20 MHz

f_Srms Integration BW = 200 kHz to 10 MHz

f_Srms Integration BW = 12 kHz to 20 MHz

f_Srms Integration BW = 200 kHz to 10 MHz

f_Srms Integration BW = 12 kHz to 20 MHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)

Table 9.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical

setup where the reference source is

jittery, so a narrower PLL loop bandwidth

is used; reference = 10.0 MHz; R = 20

VCO = 1.87 GHz; LVPECL = 622.08 MHz; PLL LBW = 125 Hz

VCO = 1.87 GHz; LVPECL = 155.52 MHz; PLL LBW = 125 Hz

VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 125 Hz

400

390

485

f_Srms Integration BW = 12 kHz to 20 MHz

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)

Table 10.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ABSOLUTE TIME JITTER

Application example based on a typical setup using an

external 245.76 MHz VCXO (Toyocom TCO-2112);

reference = 15.36 MHz; R = 1

LVPECL = 245.76 MHz; PLL LBW = 125 Hz

LVPECL = 122.88 MHz; PLL LBW = 125 Hz

LVPECL = 61.44 MHz; PLL LBW = 125 Hz

54

77

109

79

114

163

124

176

259

f_Srms Integration BW = 200 kHz to 5 MHz

f_Srms Integration BW = 200 kHz to 10 MHz

f_Srms Integration BW = 12 kHz to 20 MHz

f_Srms Integration BW = 200 kHz to 5 MHz

f_Srms Integration BW = 200 kHz to 10 MHz

f_Srms Integration BW = 12 kHz to 20 MHz

f_Srms Integration BW = 200 kHz to 5 MHz

f_Srms Integration BW = 200 kHz to 10 MHz

f_Srms Integration BW = 12 kHz to 20 MHz

Rev. 0 | Page 10 of 84

AD9516-3

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)

Table 11.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not

include PLL and VCO; rising edge of

clock signal

CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1

CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4

CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16

40

80

215

f_Srms BW = 12 kHz to 20 MHz

f_Srms Calculated from SNR of ADC method;

DCC not used for even divides

CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5

LVDS OUTPUT ADDITIVE TIME JITTER

245

f_Srms Calculated from SNR of ADIC method;

DCC on

Distribution section only; does not

include PLL and VCO; rising edge of

clock signal

CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2; VCO Divider Not Used

CLK = 1 GHz; LVDS = 200 MHz; Divider = 5

CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16

85

113

280

f_Srms BW = 12 kHz to 20 MHz

f_Srms Calculated from SNR of ADC method;

DCC not used for even divides

CMOS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not

include PLL and VCO; rising edge of

clock signal

CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16

365

f_Srms Calculated from SNR of ADC method;

DCC not used for even divides

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)

Table 12.

Parameter

Min Typ Max Unit

Test Conditions/Comments

LVPECL OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL and VCO;

uses rising edge of clock signal

CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

210

285

350

f_Srms Calculated from SNR of ADC method

LVDS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL and VCO;

rising edge of clock signal

f_Srms Calculated from SNR of ADC method

CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

CMOS OUTPUT ADDITIVE TIME JITTER

Distribution section only; does not include PLL and VCO;

rising edge of clock signal

f_Srms Calculated from SNR of ADC method

CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;

Divider = 12; Duty-Cycle Correction = Off

Rev. 0 | Page 11 of 84

AD9516-3

DELAY BLOCK ADDITIVE TIME JITTER

Table 13.

Parameter

DELAY BLOCK ADDITIVE TIME JITTER¹

Min

Typ

Max

Unit

Test Conditions/Comments

Incremental additive jitter

100 MHz Output

Delay (1600 μA, 1C) Fine Adj. 000000

Delay (1600 μA, 1C) Fine Adj. 101111

Delay (800 μA, 1C) Fine Adj. 000000

Delay (800 μA, 1C) Fine Adj. 101111

Delay (800 μA, 4C) Fine Adj. 000000

Delay (800 μA, 4C) Fine Adj. 101111

Delay (400 μA, 4C) Fine Adj. 000000

Delay (400 μA, 4C) Fine Adj. 101111

Delay (200 μA, 1C) Fine Adj. 000000

Delay (200 μA, 1C) Fine Adj. 101111

Delay (200 μA, 4C) Fine Adj. 000000

Delay (200 μA, 4C) Fine Adj. 101111

0.54

0.60

0.65

0.85

0.79

1.2

2.0

1.3

2.5

ps rms

1.9

3.8

¹This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

SERIAL CONTROL PORT

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CS (INPUT)

CS has an internal 30 kΩ pull-up resistor

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SCLK (INPUT)

2.0

V

μA

pF

0.8

3

110

2

SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO (WHEN INPUT)

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

Output Logic 0 Voltage

2.0

2.7

V

μA

pF

0.8

1

110

2

V

nA

pF

0.8

0.4

10

20

2

V

Rev. 0 | Page 12 of 84

AD9516-3

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TIMING

Clock Rate (SCLK, 1/t_SCLK

Pulse Width High, t_HI

Pulse Width Low, t_LO

SDIO to SCLK Setup, t_DS

SCLK to SDIO Hold, t_DH

)

25

MHz

ns

16

2

1.1

SCLK to Valid SDIO and SDO, t_DV

CS to SCLK Setup and Hold, t_S, t_H

CS Minimum Pulse Width High, t_PWH

8

ns

2

3

ns

,

, AND

PINS

RESET

PD SYNC

Table 15.

Parameter

Min Typ Max Unit

Test Conditions/Comments

These pins each have a 30 kΩ internal pull-up resistor

INPUT CHARACTERISTICS

Logic 1 Voltage

Logic 0 Voltage

Logic 1 Current

Logic 0 Current

Capacitance

2.0

V

0.8

1

V

110

2

μA

pF

RESET TIMING

Pulse Width Low

SYNC TIMING

50

ns

Pulse Width Low

1.5

High speed clock cycles

High speed clock is CLK input signal

LD, STATUS, REFMON PINS

Table 16.

Parameter

Min Typ Max Unit Test Conditions/Comments

When selected as a digital output (CMOS); there are other

OUTPUT CHARACTERISTICS

modes in which these pins are not CMOS digital outputs;

see Table 53, 0x17, 0x1A, and 0x1B

Output Voltage High (V_OH)

Output Voltage Low (V_OL)

MAXIMUM TOGGLE RATE

2.7

V

0.4

100

3

MHz Applies when mux is set to any divider or counter output,

or PFD up/down pulse; also applies in analog lock detect

mode; usually debug mode only; beware that spurs may

couple to output when any of these pins are toggling

ANALOG LOCK DETECT

Capacitance

pF

On-chip capacitance; used to calculate RC time constant

for analog lock detect readback; use a pull-up resistor

REF1, REF2, AND VCO FREQUENCY STATUS MONITOR

Normal Range

1.02

8

MHz Frequency above which the monitor indicates the

presence of the reference

Extended Range

kHz

Frequency above which the monitor indicates the

presence of the reference

LD PIN COMPARATOR

Trip Point

1.6

V

Hysteresis

260

mV

Rev. 0 | Page 13 of 84

AD9516-3

POWER DISSIPATION

Table 17.

Parameter

Min Typ Max Unit Test Conditions/Comments

POWER DISSIPATION, CHIP

Power-On Default

1.0

1.6

1.2

2.2

W

No clock; no programming; default register values;

does not include power dissipated in external resistors

Full Operation; CMOS Outputs at 225 MHz

Full Operation; LVDS Outputs at 225 MHz

PLL on; internal VCO = 2250 MHz; VCO divider = 2;

all channel dividers on; six LVPECL outputs @ 562.5 MHz;

eight CMOS outputs (10 pF load) @ 225 MHz; all fine

delay on, maximum current; does not include power

dissipated in external resistors

PLL on; internal VCO = 2250 MHz, VCO divider = 2;

all channel dividers on; six LVPECL outputs @ 562.5 MHz;

four LVDS outputs @ 225 MHz; all fine delay on,

maximum current; does not include power dissipated

in external resistors

1.6

2.3

W

PD

75

31

185

mW

PD

Power-Down

pin pulled low; does not include power dissipated

in terminations

PD

Power-Down, Maximum Sleep

pin pulled low; PLL power-down 0x10<1:0> = 01b;

SYNC power-down 0x230<2> = 1b; REF for distribution

power-down 0x230<1> = 1b

VCP Supply

1.5

mW

PLL operating; typical closed loop configuration

Power delta when a function is enabled/disabled

VCO divider not used

All references off to differential reference enabled

All references off to REF1 or REF2 enabled; differential

reference not enabled

POWER DELTAS, INDIVIDUAL FUNCTIONS

VCO Divider

REFIN (Differential)

30

20

4

mW

REF1, REF2 (Single-Ended)

VCO

PLL

70

75

30

160

90

120

50

100

0

mW

CLK input selected to VCO selected

PLL off to PLL on, normal operation; no reference enabled

Divider bypassed to divide-by-2 to 32

No LVPECL output on to one LVPECL output on

Second LVPECL output turned on, same channel

No LVDS output on to one LVDS output on

Second LVDS output turned on, same channel

Static; no CMOS output on to one CMOS output on

Static; second CMOS output, same pair, turned on

Channel Divider

LVPECL Channel (Divider Plus Output Driver)

LVPECL Driver

LVDS Channel (Divider Plus Output Driver)

LVDS Driver

CMOS Channel (Divider Plus Output Driver)

CMOS Driver (Second in Pair)

CMOS Driver (First in Second Pair)

Fine Delay Block

30

50

mW Static; first output, second pair, turned on

mW

Delay block off to delay block enabled; maximum

current setting

Rev. 0 | Page 14 of 84

AD9516-3

TIMING DIAGRAMS

t_CLK

CLK

DIFFERENTIAL

80%

t_PECL

LVDS

20%

t_LVDS

t_RL

t_FL

t_CMOS

CLK

Figure 2. CLK/

to Clock Output Timing, DIV = 1

Figure 4. LVDS Timing, Differential

DIFFERENTIAL

80%

SINGLE-ENDED

80%

LVPECL

CMOS

10pF LOAD

20%

t_RP

t_FP

t_RC

t_FC

Figure 3. LVPECL Timing, Differential

Figure 5. CMOS Timing, Single-Ended, 10 pF Load

Rev. 0 | Page 15 of 84

AD9516-3

ABSOLUTE MAXIMUM RATINGS

Table 18.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

With

Parameter or Pin

VS, VS_LVPECL

VCP

REFIN, REFIN

REFIN

Respect To Rating

GND

REFIN

GND

CLK

−0.3 V to +3.6 V

−0.3 V to + 5.8 V

−0.3 V to V_S+ 0.3 V

−3.3 V to +3.3 V

THERMAL RESISTANCE¹

RSET

CPRSET

CLK, CLK

−0.3 V to V_S+ 0.3 V

−1.2 V to +1.2 V

Table 19.

Package Type

θ_JA

Unit

CLK

64-Lead LFCSP

24

°C/W

SCLK, SDIO, SDO, CS

GND

−0.3 V to V_S+ 0.3 V

OUT0, OUT0, OUT1, OUT1,

OUT2, OUT2, OUT3, OUT3,

OUT4, OUT4, OUT5, OUT5,

OUT6, OUT6, OUT7, OUT7,

OUT8, OUT8, OUT9, OUT9

ESD CAUTION

SYNC

GND

−0.3 V to V_S+ 0.3 V

150°C

−65°C to +150°C

300°C

REFMON, STATUS, LD

Junction Temperature¹

Storage Temperature Range

Lead Temperature (10 sec)

¹Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-7.

¹See Table 19 for θ_JA

.

Rev. 0 | Page 16 of 84

AD9516-3

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

LVPECL LVPECL

VS

REFMON

LD

VCP

CP

STATUS

REF_SEL

SYNC

LF

BYPASS 10

VS 11

1

2

3

4

5

6

7

48 OUT6 (OUT6A)

47 OUT6 (OUT6B)

46 OUT7 (OUT7A)

45 OUT7 (OUT7B)

44 GND

43 OUT2

42 OUT2

41 VS_LVPECL

40 OUT3

39 OUT3

PIN 1

INDICATOR

AD9516-3

TOP VIEW

(Not to Scale)

8

9

38 VS

VS 12

37 GND

CLK 13

CLK 14

NC 15

36 OUT9 (OUT9B)

35 OUT9 (OUT9A)

34 OUT8 (OUT8B)

33 OUT8 (OUT8A)

SCLK 16

LVPECL LVPECL

NC = NO CONNECT

Figure 6. Pin Configuration

Table 20. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 11, 12, 30, 31,

32, 38, 49, 50, 51,

57, 60, 61

VS

3.3 V Power Pins.

2

3

4

5

6

7

8

REFMON

LD

VCP

Reference Monitor (Output). This pin has multiple selectable outputs; see Table 53 0x1B.

Lock Detect (Output). This pin has multiple selectable outputs; see Table 53 0x1A.

Power Supply for Charge Pump (CP); V_S< V_CP< 5.0 V.

Charge Pump (Output). Connects to external loop filter.

Status (Output). This pin has multiple selectable outputs; see Table 53 0x17.

Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor.

CP

STATUS

REF_SEL

SYNC

Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is

also used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor.

9

10

13

LF

BYPASS

CLK

Loop Filter (Input). Connects to VCO control voltage node internally.

This pin is for bypassing the LDO to ground with a capacitor.

Along with CLK, this is the differential input for the clock distribution section.

No Connection.

14

CLK

15, 18, 19, 20

NC

16

17

SCLK

CS

Serial Control Port Data Clock Signal.

Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor.

Serial Control Port Unidirectional Serial Data Out.

21

22

23

SDO

SDIO

RESET

PD

Serial Control Port Bidirectional Serial Data In/Out.

Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor.

Chip Power Down; Active Low. This pin has an internal 30 kΩ pull-up resistor.

Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.

Ground Pins; Includes External Paddle (EPAD).

LVPECL Output; One Side of a Differential LVPECL Output.

24

27, 41, 54

37, 44, 59, EPAD

56

VS_LVPECL

GND

OUT0

Rev. 0 | Page 17 of 84

AD9516-3

Pin No.

55

53

52

43

42

40

39

25

26

28

29

48

47

46

45

33

34

35

36

58

62

63

Mnemonic

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

Description

LVPECL Output; One Side of a Differential LVPECL Output.

OUT6 (OUT6A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output.

OUT6 (OUT6B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output.

OUT7 (OUT7A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output.

OUT7 (OUT7B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output.

OUT8 (OUT8A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output.

OUT8 (OUT8B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output.

OUT9 (OUT9A) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output.

OUT9 (OUT9B) LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output.

RSET

CPRSET

REFIN (REF2)

Resistor Connected Here Sets Internal Bias Currents. Nominal value = 4.12 kΩ.

Resistor Connected Here Sets the CP Current Range. Nominal value = 5.1 kΩ.

Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a

single-ended input for REF2.

64

REFIN (REF1)

Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a

single-ended input for REF1.

Rev. 0 | Page 18 of 84

AD9516-3

TYPICAL PERFORMANCE CHARACTERISTICS

300

70

65

60

55

50

45

40

35

30

25

3 CHANNELS—6 LVPECL

280

260

240

220

200

180

160

140

120

100

3 CHANNELS—3 LVPECL

2 CHANNELS—2 LVPECL

1 CHANNEL—1 LVPECL

0

500

1000

1500

2000

2500

3000

1.7

1.8

1.9

2.0

2.1

2.2

2.3

FREQUENCY (MHz)

VCO FREQUENCY (GHz)

Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs

Figure 10. VCO K_VCOvs. Frequency

180

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2 CHANNELS—4 LVDS

160

PUMP DOWN

PUMP UP

140

2 CHANNELS—2 LVDS

120

100

1 CHANNEL—1 LVDS

80

0

200

400

600

800

0

0.5

1.0

1.5

2.0

2.5

3.0

FREQUENCY (MHz)

VOLTAGE ON CP PIN (V)

Figure 8. Current vs. Frequency—LVDS Outputs

Figure 11. Charge Pump Characteristics @ VCP = 3.3 V

240

220

200

180

160

140

120

100

80

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2 CHANNELS—8 CMOS

2 CHANNELS—2 CMOS

PUMP DOWN

PUMP UP

1 CHANNEL—2 CMOS

1 CHANNEL—1 CMOS

0

50

100

150

200

250

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

FREQUENCY (MHz)

VOLTAGE ON CP PIN (V)

Figure 9. Current vs. Frequency—CMOS Outputs

Figure 12. Charge Pump Characteristics @ VCP = 5.0 V

Rev. 0 | Page 19 of 84

AD9516-3

10

0

–140

–145

–150

–155

–160

–165

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–170

0.1

CENTER 122.88MHz

5MHz/DIV

SPAN 50MHz

1

10

100

PFD FREQUENCY (MHz)

Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;

LBW = 127 kHz; I_CP= 3.0 mA; F_VCO= 2.21 GHz

Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency

10

–210

–212

–214

–216

–218

–220

–222

–224

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

CENTER 122.88MHz

100kHz/DIV

SPAN 1MHz

0

0.5

1.0

1.5

2.0

2.5

SLEW RATE (V/ns)

REFIN

Figure 17. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz;

LBW = 127 kHz; I_CP= 3.0 mA; F_VCO= 2.21 GHz

Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/

1.9

10

0

1.7

1.5

1.3

1.1

0.9

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

1.7

1.8

1.9

2.0

2.1

2.2

2.3

VCO FREQUENCY (GHz)

CENTER 122.88MHz

100kHz/DIV

SPAN 1MHz

Figure 15. VCO Tuning Voltage vs. Frequency

Figure 18. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz;

LBW = 127 kHz; I_CP= 3.0 mA; F_VCO= 2.21 GHz

Rev. 0 | Page 20 of 84

AD9516-3

1.0

0.6

0.4

0.2

0

–0.2

–0.6

–1.0

–0.2

–0.4

0

5

10

15

20

25

0

1

2

TIME (ns)

Figure 19. LVPECL Output (Differential) @ 100 MHz

Figure 22. LVDS Output (Differential) @ 800 MHz

1.0

0.6

2.8

1.8

0.2

–0.2

–0.6

–1.0

0.8

–0.2

0

20

40

60

80

100

0

1

2

TIME (ns)

Figure 20. LVPECL Output (Differential) @ 1600 MHz

Figure 23. CMOS Output @ 25 MHz

0.4

0.2

2.8

1.8

0

0.8

–0.2

–0.4

–0.2

0

2

4

6

8

10

12

0

5

10

15

20

25

TIME (ns)

Figure 21. LVDS Output (Differential) @ 100 MHz

Figure 24. CMOS Output @ 250 MHz

Rev. 0 | Page 21 of 84

AD9516-3

1600

–80

–90

1400

1200

1000

–100

–110

–120

–130

–140

–150

800

0

1

2

3

10k

100k

1M

10M

100M

FREQUENCY (GHz)

FREQUENCY (Hz)

Figure 25. LVPECL Differential Swing vs. Frequency

Figure 28. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2250 MHz

–80

–90

700

600

500

–100

–110

–120

–130

–140

–150

0

100

200

300

400

500

600

700

800

10k

100k

1M

10M

100M

FREQUENCY (MHz)

FREQUENCY (Hz)

Figure 26. LVDS Differential Swing vs. Frequency

Figure 29. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2000 MHz

–80

–90

C

= 2pF

L

3

2

1

0

C

= 10pF

–100

–110

–120

–130

–140

–150

C

= 20pF

L

0

100

200

300

400

500

600

10k

100k

1M

10M

100M

OUTPUT FREQUENCY (MHz)

FREQUENCY (Hz)

Figure 30. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 1750 MHz

Figure 27. CMOS Output Swing vs. Frequency and Capacitive Load

Rev. 0 | Page 22 of 84

AD9516-3

–120

–125

–130

–135

–140

–145

–150

–155

–160

–110

–120

–130

–140

–150

–160

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 31. Phase Noise (Additive) LVPECL @ 245.76 MHz, Divide-by-1

Figure 34. Phase Noise (Additive) LVDS @ 200 MHz, Divide-by-1

–100

–110

–120

–130

–140

–150

–120

–130

–140

–150

–160

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 35. Phase Noise (Additive) LVDS @ 800 MHz, Divide-by-2

Figure 32. Phase Noise (Additive) LVPECL @ 200 MHz, Divide-by-5

–120

–100

–130

–140

–150

–160

–170

–110

–120

–130

–140

–150

10

100

1k

10k

100k

1M

10M

100M

10

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 36. Phase Noise (Additive) CMOS @ 50 MHz, Divide-by-20

Figure 33. Phase Noise (Additive) LVPECL @ 1600 MHz, Divide-by-1

Rev. 0 | Page 23 of 84

AD9516-3

–100

–110

–120

–130

–140

–150

–160

–90

–100

–110

–120

–130

–140

–150

–160

10

100

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 37. Phase Noise (Additive) CMOS @ 250 MHz, Divide-by-4

Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 1.87 GHz;

PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz

–100

–110

–120

–130

–140

–150

–160

–120

–130

–140

–150

–160

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO @

1.97 GHz; PFD = 15.36 MHz; LBW = 143 kHz; LVPECL Output = 122.88 MHz

Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)

@ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz

Rev. 0 | Page 24 of 84

AD9516-3

TERMINOLOGY

Time Jitter

Phase Jitter and Phase Noise

Phase noise is a frequency domain phenomenon. In the time

domain, the same effect is exhibited as time jitter. When

observing a sine wave, the time of successive zero crossings

varies. In a square wave, the time jitter is a displacement of the

edges from their ideal (regular) times of occurrence. In both

cases, the variations in timing from the ideal are the time jitter.

Because these variations are random in nature, the time jitter is

specified in units of seconds root mean square (rms) or 1 sigma

of the Gaussian distribution.

An ideal sine wave can be thought of as having a continuous

and even progression of phase with time from 0° to 360° for

each cycle. Actual signals, however, display a certain amount

of variation from ideal phase progression over time. This

phenomenon is called phase jitter. Although many causes can

contribute to phase jitter, one major cause is random noise,

which is characterized statistically as being Gaussian (normal)

in distribution.

This phase jitter leads to a spreading out of the energy of the

sine wave in the frequency domain, producing a continuous

power spectrum. This power spectrum is usually reported as a

series of values whose units are dBc/Hz at a given offset in

frequency from the sine wave (carrier). The value is a ratio

(expressed in dB) of the power contained within a 1 Hz

bandwidth with respect to the power at the carrier frequency.

For each measurement, the offset from the carrier frequency is

also given.

Time jitter that occurs on a sampling clock for a DAC or an

ADC decreases the signal-to-noise ratio (SNR) and dynamic

range of the converter. A sampling clock with the lowest possible

jitter provides the highest performance from a given converter.

Additive Phase Noise

Additive phase noise is the amount of phase noise that is

attributable to the device or subsystem being measured. The

phase noise of any external oscillators or clock sources are

subtracted. This makes it possible to predict the degree to which

the device impacts the total system phase noise when used in

conjunction with the various oscillators and clock sources, each

of which contribute its own phase noise to the total. In many

cases, the phase noise of one element dominates the system

phase noise. When there are multiple contributors to phase

noise, the total is the square root of the sum of squares of the

individual contributors.

It is meaningful to integrate the total power contained within

some interval of offset frequencies (for example, 10 kHz to

10 MHz). This is called the integrated phase noise over that

frequency offset interval and can be readily related to the time

jitter due to the phase noise within that offset frequency interval.

Phase noise has a detrimental effect on the performance of

ADCs, DACs, and RF mixers. It lowers the achievable dynamic

range of the converters and mixers, although they are affected

in somewhat different ways.

Additive Time Jitter

Additive time jitter is the amount of time jitter that is

attributable to the device or subsystem being measured. The

time jitter of any external oscillators or clock sources are subtracted.

This makes it possible to predict the degree to which the device

impacts the total system time jitter when used in conjunction with

the various oscillators and clock sources, each of which

contribute its own time jitter to the total. In many cases, the

time jitter of the external oscillators and clock sources dominates

the system time jitter.

Rev. 0 | Page 25 of 84

AD9516-3

DETAILED BLOCK DIAGRAM

REF_ SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

VCO STATUS

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

LOW DROPOUT

REGULATOR (LDO)

BYPASS

LF

PROGRAMMABLE

N DELAY

CP

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

VCO

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

OUT0

DIVIDE BY

1 TO 32

LVPECL

PD

SYNC

OUT1

DIGITAL

LOGIC

RESET

OUT2

DIVIDE BY

1 TO 32

LVPECL

OUT3

SCLK

SDIO

SDO

CS

SERIAL

CONTROL

PORT

OUT4

DIVIDE BY

1 TO 32

OUT5

OUT6 (OUT6A)

OUT6 (OUT6B)

ΔT

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT7 (OUT7A)

OUT7 (OUT7B)

ΔT

OUT8 (OUT8A)

OUT8 (OUT8B)

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT9 (OUT9A)

OUT9 (OUT9B)

AD9516-3

ΔT

Figure 41. Detailed Block Diagram

Rev. 0 | Page 26 of 84

AD9516-3

THEORY OF OPERATION

OPERATIONAL CONFIGURATIONS

Table 21. Default Settings of Some PLL Registers

Register

Function

The AD9516 can be configured in several ways. These

configurations must be set up by loading the control registers

(see Table 51 and Table 52 through Table 61). Each section or

function must be individually programmed by setting the

appropriate bits in the corresponding control register or registers.

0x10<1:0> = 01b

0x1E0<2:0> = 010b

0x1E1<0> = 0b

0x1E1<1> = 0b

PLL asynchronous power-down (PLL off)

Set VCO divider = 4

Use the VCO divider

CLK selected as the source

High Frequency Clock Distribution—CLK or External

VCO >1600 MHz

When using the internal PLL with an external VCO, the PLL

must be turned on.

The AD9516 power-up default configuration has the PLL

powered off and the routing of the input set so that the

Table 22. Settings When Using an External VCO

CLK

CLK/

input is connected to the distribution section

Register

Function

through the VCO divider (divide-by-2/ divide-by-3/divide-by-4/

divide-by-5/divide-by-6). This is a distribution only mode that

allows for an external input up to 2400 MHz (see Table 3). The

maximum frequency that can be applied to the channel dividers

is 1600 MHz; therefore, higher input frequencies must be

divided down before reaching the channel dividers. This input

routing can also be used for lower input frequencies, but the

minimum divide is 2 before the channel dividers.

0x10 to 0x1E

PLL normal operation (PLL on).

0x1E1<1> = 0b PLL settings. Select and enable a reference

input; set R, N (P, A, B), PFD polarity, and I_CP

according to the intended loop configuration.

An external VCO requires an external loop filter that must be

connected between CP and the tuning pin of the VCO. This

loop filter determines the loop bandwidth and stability of the

PLL. Make sure to select the proper PFD polarity for the VCO

being used.

When the PLL is enabled, this routing also allows the use of the

PLL with an external VCO or VCXO with a frequency less than

2400 MHz. In this configuration, the internal VCO is not used

and is powered off. The external VCO/VCXO feeds directly into

the prescaler.

Table 23. Setting the PFD Polarity

Register

0x10<7> = 0b

Function

PFD polarity positive (higher control

voltage produces higher frequency)

PFD polarity negative (higher control

voltage produces lower frequency)

The register settings shown in Table 21 are the default values of

these registers at power-up or after a reset operation. If the

contents of the registers are altered by prior programming after

power-up or reset, these registers may also be set intentionally

to these values.

0x10<7> = 1b

Rev. 0 | Page 27 of 84

AD9516-3

REF_SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

VCO STATUS

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

LOW DROPOUT

REGULATOR (LDO)

BYPASS

LF

PROGRAMMABLE

N DELAY

CP

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

VCO

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

OUT0

DIVIDE BY

1 TO 32

LVPECL

PD

SYNC

OUT1

DIGITAL

LOGIC

RESET

OUT2

DIVIDE BY

1 TO 32

LVPECL

OUT3

SCLK

SDIO

SDO

CS

SERIAL

CONTROL

PORT

OUT4

DIVIDE BY

1 TO 32

OUT5

OUT6 (OUT6A)

OUT6 (OUT6B)

ΔT

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT7 (OUT7A)

OUT7 (OUT7B)

ΔT

OUT8 (OUT8A)

OUT8 (OUT8B)

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

AD9516-3

OUT9 (OUT9A)

OUT9 (OUT9B)

ΔT

Figure 42. High Frequency Clock Distribution or External VCO > 1600 MHz

Rev. 0 | Page 28 of 84

AD9516-3

Internal VCO and Clock Distribution

Table 24. Settings When Using Internal VCO

When using the internal VCO and PLL, the VCO divider must

be employed to ensure that the frequency presented to the

channel dividers does not exceed its specified maximum

frequency (1600 MHz, see Table 3). The internal PLL uses an

external loop filter to set the loop bandwidth. The external loop

filter is also crucial to the loop stability.

Register

Function

0x10<1:0> = 00b

0x10 to 0x1E

PLL normal operation (PLL on).

PLL settings. Select and enable a reference

input; set R, N (P, A, B), PFD polarity, and I_CP

according to the intended loop configuration.

Reset VCO calibration (first time after

power-up, this does not have to be done,

but must be done subsequently).

0x18<0> = 0,

0x232<0> = 1

When using the internal VCO, it is necessary to calibrate the

VCO (0x18<0>) to ensure optimal performance.

0x18<0> = 1,

0x232<0> = 1

0x1E0<2:0>

Initiate VCO calibration.

For internal VCO and clock distribution applications, the

register settings shown in Table 24 should be used.

VCO divider set to divide-by-2, divide-by-3,

divide-by-4, divide-by-5, and divide-by-6.

0x1E1<0> = 0b

0x1E1<1> = 1b

Use the VCO divider as source for

distribution section.

VCO selected as the source.

Rev. 0 | Page 29 of 84

AD9516-3

REF_SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

VCO STATUS

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

LOW DROPOUT

REGULATOR (LDO)

BYPASS

LF

PROGRAMMABLE

N DELAY

CP

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

VCO

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

OUT0

DIVIDE BY

1 TO 32

LVPECL

PD

SYNC

OUT1

DIGITAL

LOGIC

RESET

OUT2

DIVIDE BY

1 TO 32

LVPECL

OUT3

SCLK

SDIO

SDO

CS

SERIAL

CONTROL

PORT

OUT4

DIVIDE BY

1 TO 32

OUT5

OUT6 (OUT6A)

OUT6 (OUT6B)

ΔT

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT7 (OUT7A)

OUT7 (OUT7B)

ΔT

OUT8 (OUT8A)

OUT8 (OUT8B)

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

AD9516-3

OUT9 (OUT9A)

OUT9 (OUT9B)

ΔT

Figure 43. Internal VCO and Clock Distribution

Rev. 0 | Page 30 of 84

AD9516-3

Clock Distribution or External VCO <1600 MHz

When the external clock source to be distributed or the external

VCO/VCXO is less than 1600 MHz, a configuration that

bypasses the VCO divider can be used. This only differs from

the High Frequency Clock Distribution—CLK or External VCO

>1600 MHz section in that the VCO divider (divide-by-2,

divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is

bypassed. This limits the frequency of the clock source to

<1600 MHz (due to the maximum input frequency allowed at

the channel dividers).

When using the internal PLL with an external VCO <1600 MHz,

the PLL must be turned on.

Table 26. Settings for Using Internal PLL with External VCO

<1600 MHz

Register

Function

0x1E1<0> = 1b

Bypass the VCO divider as source for

distribution section

0x10<1:0> = 00b PLL normal operation (PLL on) along with

other appropriate PLL settings in 0x10 to 0x1E

Configuration and Register Settings

For clock distribution applications where the external clock is

<1600 MHz, the register settings shown in Table 25 should be

used.

An external VCO/VCXO requires an external loop filter that

must be connected between CP and the tuning pin of the

VCO/VCXO. This loop filter determines the loop bandwidth

and stability of the PLL. Make sure to select the proper PFD

polarity for the VCO/VCXO being used.

Table 25. Settings for Clock Distribution < 1600 MHz

Register

Function

0x10<1:0> = 01b

0x1E1<0> = 1b

PLL asynchronous power-down (PLL off)

Bypass the VCO divider as source for

distribution section

Table 27. Setting the PFD Polarity

Register

Function

0x10<7> = 0

PFD polarity positive (higher control voltage

produces higher frequency)

0x1E1<1> = 0b

CLK selected as the source

0x10<7> = 1

PFD polarity negative (higher control

voltage produces lower frequency)

Rev. 0 | Page 31 of 84

AD9516-3

REF_SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

VCO STATUS

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

LOW DROPOUT

REGULATOR (LDO)

BYPASS

LF

PROGRAMMABLE

N DELAY

CP

P, P + 1

PRESCALER

A/B

COUNTERS

N DIVIDER

VCO

STATUS

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

OUT0

DIVIDE BY

1 TO 32

LVPECL

PD

SYNC

OUT1

DIGITAL

LOGIC

RESET

OUT2

DIVIDE BY

1 TO 32

LVPECL

OUT3

SCLK

SDIO

SDO

CS

SERIAL

CONTROL

PORT

OUT4

DIVIDE BY

1 TO 32

OUT5

OUT6 (OUT6A)

OUT6 (OUT6B)

ΔT

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

OUT7 (OUT7A)

OUT7 (OUT7B)

ΔT

OUT8 (OUT8A)

OUT8 (OUT8B)

DIVIDE BY

1 TO 32

DIVIDE BY

1 TO 32

LVDS/CMOS

AD9516-3

OUT9 (OUT9A)

OUT9 (OUT9B)

ΔT

Figure 44. Clock Distribution or External VCO < 1600 MHz

Rev. 0 | Page 32 of 84

AD9516-3

Phase-Locked Loop (PLL)

REF_SEL

VS

GND

RSET

REFMON

CPRSET VCP

DIST

REF

REFERENCE

SWITCHOVER

LD

LOCK

DETECT

REF1

REF2

STATUS

PROGRAMMABLE

R DELAY

HOLD

R DIVIDER

PLL

REF

REFIN (REF1)

REFIN (REF2)

PHASE

CHARGE PUMP

FREQUENCY

DETECTOR

CP

N DIVIDER

P, P + 1

LOW DROPOUT

REGULATOR (LDO)

BYPASS

A/B

PROGRAMMABLE

N DELAY

PRESCALER

COUNTERS

VCO STATUS

LF

STATUS

VCO

DIVIDE BY

2, 3, 4, 5, OR 6

0

1

CLK

1

0

Figure 45. PLL Functional Blocks

The AD9516 includes an on-chip PLL with an on-chip VCO.

The PLL blocks can be used either with the on-chip VCO to

create a complete phase-locked loop, or with an external VCO

or VCXO. The PLL requires an external loop filter, which

usually consists of a small number of capacitors and resistors.

The configuration and components of the loop filter help to

establish the loop bandwidth and stability of the operating PLL.

Successful PLL operation and satisfactory PLL loop performance

are highly dependant upon proper configuration of the PLL

settings. The design of the external loop filter is crucial to the

proper operation of the PLL. A thorough knowledge of PLL

theory and design is helpful.

ADIsimCLK™ (V1.2 or later) is a free program that can help

with the design and exploration of the capabilities and features

of the AD9516, including the design of the PLL loop filter. It is

available at www.analog.com/clocks.

The AD9516 PLL is useful for generating clock frequencies

from a supplied reference frequency. This includes conversion

of reference frequencies to much higher frequencies for subsequent

division and distribution. In addition, the PLL can be exploited to

clean up jitter and phase noise on a noisy reference. The exact

choices of PLL parameters and loop dynamics is application

specific. The flexibility and depth of the AD9516 PLL allows the

part to be tailored to function in many different applications

and signal environments.

Phase Frequency Detector (PFD)

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. The PFD includes a programmable

delay element that controls the width of the antibacklash pulse.

This pulse ensures that there is no dead zone in the PFD

transfer function and minimizes phase noise and reference

spurs. The antibacklash pulse width is set by 0x17<1:0>.

Configuration of the PLL

The AD9516 allows flexible configuration of the PLL,

An important limit to keep in mind is the maximum frequency

allowed into the PFD. The maximum input frequency into the

PFD is a function of the antibacklash pulse setting, as specified

in the Phase/Frequency Detector section of Table 2.

accomodating various reference frequencies, PFD comparison

frequencies, VCO frequencies, internal or external VCO/VCXO,

and loop dynamics. This is accomplished by the various settings

that include the R divider, the N divider, the PFD polarity (only

applicable to external VCO/VCXO), the antibacklash pulse

width, the charge pump current, the selection of internal VCO

or external VCO/VCXO, and the loop bandwidth. These are

managed through programmable register settings (see Table 51

and Table 53) and by the design of the external loop filter.

Rev. 0 | Page 33 of 84

AD9516-3

Charge Pump (CP)

AD9516-3

The charge pump is controlled by the PFD. The PFD monitors

the phase and frequency relationship between its two inputs,

and tells the CP to pump up or pump down to charge or

discharge the integrating node (part of the loop filter). The

integrated and filtered CP current is transformed into a voltage

that drives the tuning node of the internal VCO through the LF

pin (or the tuning pin of an external VCO) to move the VCO

frequency up or down. The CP can be set (0x10<6:4>) for high

impedance (allows holdover operation), for normal operation

(attempts to lock the PLL loop), pump up, or pump down (test

modes). The CP current is programmable in eight steps from

(nominally) 600 μA to 4.8 mA. The exact value of the CP

current LSB is set by the CP_RSET resistor, which is

nominally 5.1 kΩ.

LF

VCO

R2

CP

R1

C2

CHARGE

PUMP

C1

C3

BYPASS

C

= 220nF

BP

Figure 46. Example of External Loop Filter for PLL

PLL Reference Inputs

The AD9516 features a flexible PLL reference input circuit that

allows either a fully differential input or two separate single-

ended inputs. The input frequency range for the reference

inputs is specified in Table 2. Both the differential and the

single-ended inputs are self-biased, allowing for easy ac

coupling of input signals.

On-Chip VCO

The AD9516 includes an on-chip VCO covering the frequency

range shown in Table 2. Achieving low VCO phase noise was a

priority in the design of the VCO.

The differential input and the single-ended inputs share the two

REFIN

pins, REFIN (REF1)/

(REF2). The desired reference input

type is selected and controlled by 0x1C (see Table 51 and Table 53).

To tune over the wide range of frequencies covered by this

VCO, ranges are used. This is largely transparent to the user but

is the reason that the VCO must be calibrated when the PLL

loop is first set up. The calibration procedure ensures that the

VCO is operating within the correct band range for the frequency

that it is asked to produce. See the VCO Calibration section for

additional information.

When the differential reference input is selected, the self-bias

level of the two sides is offset slightly (~100 mV, see Table 2) to

prevent chattering of the input buffer when the reference is slow

or missing. This increases the voltage swing required of the

driver and overcomes the offset.

The single-ended inputs can be driven by either a dc-coupled

CMOS level signal or an ac-coupled sine-wave or square wave.

Each single-ended input can be independently powered down

when not needed to increase isolation and reduce power. Either

a differential or a single-ended reference must be specifically

enabled. All PLL reference inputs are off by default.

The on-chip VCO is powered by an on-chip, low dropout

(LDO), linear voltage regulator. The LDO provides some

isolation of the VCO from variations in the power supply

voltage level. The BYPASS pin should be connected to ground

by a 220 nF capacitor to ensure stability. This LDO employs the

same technology used in the anyCAP® line of regulators from

Analog Devices, Inc., making it insensitive to the type of

capacitor used. Driving an external load from the BYPASS pin

is not supported.

The differential reference input is powered down whenever the

PLL is powered down, or when the differential reference input

is not selected. The single-ended buffers power down when the

PLL is powered down, and when their individual power down

registers are set. When the differential mode is selected, the

single-ended inputs are powered down.

PLL External Loop Filter

When using the internal VCO, the external loop filter should be

referenced to the BYPASS pin for optimal noise and spurious

performance. An example of an external loop filter for the PLL

is shown in Figure 46. A loop filter must be calculated for each

desired PLL configuration. The values of the components

depend upon the VCO frequency, the K_VCO, the PFD frequency,

the CP current, the desired loop bandwidth, and the desired

phase margin. The loop filter affects the phase noise, the loop

settling time, and the loop stability. A knowledge of PLL theory

is necessary for understanding the subject of loop filter design.

There are tools available, such as ADIsimCLK, that can help

with the calculation of a loop filter according to the application

requirements.

In differential mode, the reference input pins are internally self-

biased so that they can be ac-coupled via capacitors. It is possible to

dc couple to these inputs. If the differential REFIN is driven by

a single-ended signal, the unused side (

) should be

REFIN

decoupled via a suitable capacitor to a quiet ground. Figure 47

shows the equivalent circuit of REFIN.

Rev. 0 | Page 34 of 84

AD9516-3

V

S

In automatic mode, REF1 is monitored by REF2. If REF1

disappears (two consecutive falling edges of REF2 without an

edge transition on REF1), REF1 is considered missing. Upon

the next subsequent rising edge of REF2, REF2 is used as the

reference clock to the PLL. If 0x1C<3> = 0b (default), when

REF1 returns (four rising edges of REF1 without two falling

edges of REF2 between the REF1 edges), the PLL reference

switchs back to REF1. If 0x1C<3> = 1b, the user can control

when to switch back to REF1. This is done by programming the

part to manual reference select mode (0x1C<4> = 0b) and by

ensuring that the registers and/or REF_SEL pin are set to select

the desired reference. Auto mode can be re-enabled once REF1

is reselected.

85kΩ

REF1

V

S

10kΩ 12kΩ

150Ω

REFIN

150Ω

10kΩ 10kΩ

Manual switchover requires the presence of a clock on the

reference input that is being switched to, or that the deglitching

feature be disabled (0x1C<7>).

V

S

REF2

Reference Divider R

85kΩ

The reference inputs are routed to the reference divider, R.

R (a 14-bit counter) can be set to any value from 0 to 16383 by

writing to 0x11 and 0x12. (Both R = 0 and R = 1 give divide-by-1.)

The output of the R divider goes to one of the PFD inputs to be

compared with the VCO frequency divided by the N divider.

The frequency applied to the PFD must not exceed the

maximum allowable frequency, which depends on the

antibacklash pulse setting (see Table 2).

Figure 47. REFIN Equivalent Circuit

Reference Switchover

The AD9516 supports dual single-ended CMOS inputs, as well

as a single differential reference input. In the dual single-ended

reference mode, the AD9516 supports automatic and manual

PLL reference clock switching between REF1 (on Pin REFIN)

The R counter has its own reset. R counter can be reset using

the shared reset bit of the R, A, and B counters. It can also be

REFIN

and REF2 (on Pin

). This feature supports networking

SYNC

reset by a

operation.

and other applications that require redundant references. When

using reference switchover, the single-ended reference inputs

should be dc-coupled CMOS levels and never be allowed to go

to high impedance. If these inputs are allowed to go to high

impedance, noise may cause the buffer to chatter, causing a false

detection of the presence of a reference.

VCXO/VCO Feedback Divider N: P, A, B, R

The N divider is a combination of a prescaler (P) and two

counters, A and B. The total divider value is

N = (P × B) + A

where P can be 2, 4, 8, 16, or 32.

Prescaler

There are several configurable modes of reference switchover.

The switchover can be performed manually or automatically.

The manual switchover is done either through a register setting

(0x1D) or by using the REF_SEL pin. The automatic switchover

occurs when REF1 disappears. There is also a switchover deglitch

feature which ensures that the PLL does not receive rising edges

that are far out of alignment with the newly selected reference.

The prescaler of the AD9516 allows for two modes of operation:

a fixed divide (FD) mode of 1, 2, or 3 and dual modulus (DM)

mode where the prescaler divides by P and (P + 1) {2 and 3, 4

and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes of

operation are given in Table 53, 0x16<2:0>. Not all modes are

available at all frequencies (see Table 2).

There are two reference automatic switchover modes (0x1C):

When operating the AD9516 in dual modulus mode (P//P + 1),

the equation used to relate input reference frequency to VCO

output frequency is

• Prefer REF1: Switch from REF1 to REF2 when REF1

disappears. Return to REF1 from REF2 when REF1 returns.

• Stay on REF2: Automatically switch to REF2 if REF1 disappears,

but do not switch back to REF1 if it reappears. The reference

can be set back to REF1 manually at an appropriate time.

f

_VCO= (f_REF/R) × (P × B + A) = f_REF× N/R

However, when operating the prescaler in FD mode 1, 2, or 3,

the A counter is not used (A = 0) and the equation simplifies to

f

_VCO= (f_REF/R) × (P × B) = f_REF× N/R

Rev. 0 | Page 35 of 84

AD9516-3

When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,

in which case the previous equation also applies.

The maximum input frequency to the A/B counter is reflected

in the maximum prescaler output frequency (~300 MHz)

specified in Table 2. This is the prescaler input frequency (VCO

or CLK) divided by P.

By using combinations of DM and FD modes, the AD9516 can

achieve values of N all the way down to N = 1. Table 28 shows

how a 10 MHz reference input may be locked to any integer

multiple of N.

Although manual reset is not normally required, the A/B counters

have their own reset bit. A and B counters can be reset using the

shared reset bit of the R, A, and B counters. They may also be

Note that the same value of N may be derived in different ways,

as illustrated by the case of N = 12. The user may choose a fixed

divide mode P = 2 with B = 6, or use the dual modulus mode

2/3 with A = 0, B = 6, or use the dual modulus mode 4/5 with

A = 0, B = 3.

SYNC

reset through a

R, A, and B Counters:

The R, A and B counters may also be reset simultaneously

SYNC

operation.

SYNC

Pin Reset

through the

(see Table 53). The

R and N Divider Delays

pin. This function is controlled by 0x19<7:6>

A and B Counters

SYNC

pin reset is disabled by default.

The AD9516 B counter can be bypassed (B = 1). This B counter

bypass mode is only valid when using the prescaler in FD mode.

When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32.

Both the R and N dividers feature a programmable delay cell.

These delays may be enabled to allow adjustment of the phase

relationship between the PLL reference clock and the VCO or

CLK. Each delay is controlled by three bits. The total delay

range is about 1 ns. See 0x19 in Table 53.

Unlike the R-counter, an A = 0 is actually a zero. The B counter

must be ≥3 or bypassed.

Table 28. How a 10 MHz Reference Input May Be Locked to Any Integer Multiple of N

FREF

10

R

1

P

1

2

1

2

4

A

X

0

1

2

1

X

0

1

X

0

1

B

1

3

4

5

3

4

5

6

3

N

FVCO

Mode

Notes

1

2

3

4

5

6

7

10

20

30

40

50

60

70

FD

DM

FD

DM

FD

P = 1, B = 1 (bypassed)

P = 2, B = 1 (bypassed)

P = 1, B = 3

P = 1, B = 4

P = 1, B = 5

P = 2, B = 3

P and P + 1 = 2 and 3, A = 0, B = 3

P and P + 1 = 2 and 3, A = 1, B = 3

P and P + 1 = 2 and 3, A = 2, B = 3

P and P + 1 = 2 and 3, A = 1, B = 4

P = 2, B = 5

P and P + 1 = 2 and 3, A = 0, B = 5

P and P + 1 = 2 and 3, A = 1, B = 5

P = 2, B = 6

8

9

80

90

10

11

12

13

100

110

120

130

DM

P and P + 1 = 2 and 3, A = 0, B = 6

P and P + 1 = 4 and 5, A = 0, B = 3

P and P + 1 = 4 and 5, A = 1, B = 3

Rev. 0 | Page 36 of 84

AD9516-3

current source lock detect function. This function is set by

selecting it as the output from the LD pin control (0x1A<5:0>).

DIGITAL LOCK DETECT (DLD)

By selecting the proper output through the mux on each pin,

the DLD function is available at the LD, STATUS, and

REFMON pins. The digital lock detect circuit indicates a lock

when the time difference of the rising edges at the PFD inputs is

less than a specified value (the lock threshold). The loss of a

lock is indicated when the time difference exceeds a specified

value (the unlock threshold). Note that the unlock threshold is

wider than the lock threshold, which allows some phase error in

excess of the lock window to occur without chattering on the

lock indicator.

The current source lock detect provides a current of 110 μA

when DLD is true and shorts to ground when DLD is false.

If a capacitor is connected to the LD pin, it charges at a rate

determined by the current source during the DLD true time

but is discharged nearly instantly when DLD is false. By

monitoring the voltage at the LD pin (top of the capacitor), it is

only possible to get a Logic High level after the DLD has been

true for a sufficiently long time. Any momentary DLD false

resets the charging. By selecting a properly sized capacitor, it is

possible to delay a lock detect indication until the PLL is stably

locked, and the lock detect does not chatter.

The lock detect window timing depends on three settings: the

digital lock detect window bit (0x18<4>), the antibacklash pulse

width setting (0x17<1:0>, see Table 2), and the lock detect

counter (0x18<6:5>). A lock is not indicated until there is a

programmable number of consecutive PFD cycles with a time

difference less than the lock detect threshold. The lock detect

circuit continues to indicate a lock until a time difference

greater than the unlock threshold occurs on a single subsequent

cycle. For the lock detect to work properly, the period of the

PFD frequency must be greater than the unlock threshold. The

number of consecutive PFD cycles required for lock is

programmable (0x18<6:5>).

The voltage on the capacitor can be sensed by an external

comparator connected to the LD pin. However, there is an

internal LD pin comparator that can be read at the REFMON

pin control (0x1B<4:0>) or the STATUS pin control (0x17<7:2>)

as an active high signal. It is also available as an active low signal

(REFMON, 0x1B<4:0> and STATUS, 0x17<7:2>). The internal

LD pin comparator trip point and hysteresis are given in Table 16.

AD9516-3

110µA

DLD

V

OUT

Analog Lock Detect (ALD)

LD

The AD9516 provides an ALD function that may be selected for

use at the LD pin. There are two versions of ALD:

C

LD PIN

COMPARATOR

REFMON

OR

• N-channel open-drain lock detect. This signal requires a

pull-up resistor to the positive supply, VS. The output is

normally high with short, low-going pulses. Lock is indicated

by the minimum duty cycle of the low-going pulses.

STATUS

Figure 49. Current Source Lock Detect

CLK

External VCXO/VCO Clock Input (CLK/

)

• P-channel open-drain lock detect. This signal requires a pull-

down resistor to GND. The output is normally low with

short, high-going pulses. Lock is indicated by the minimum

duty cycle of the high-going pulses.

CLK is a differential input that can be used as an input to drive

the AD9516 clock distribution section. This input can receive

up to 2.4 GHz. The pins are internally self-biased and the input

signal should be ac-coupled via capacitors.

The analog lock detect function requires an R-C filter to

provide a logic level indicating lock/unlock.

CLOCK INPUT

STAGE

VS

V

= 3.3V

S

AD9516-3

CLK

R2

V

OUT

R1

LD

CLK

ALD

C

2.5kΩ

5kΩ

2.5kΩ

5kΩ

Figure 48. Example of Analog Lock Detect Filter, Using

N-Channel Open-Drain Driver

Figure 50. CLK Equivalent Input Circuit

Current Source Digital Lock Detect (DLD)

CLK

The CLK/

input can be used either as a distribution only

input (with the PLL off), or as a feedback input for an external

VCO/VCXO using the internal PLL, when the internal VCO is

During the PLL locking sequence, it is normal for the DLD

signal to toggle a number of times before remaining steady

when the PLL is completely locked and stable. There may be

applications where it is desirable to have DLD asserted only

after the PLL is solidly locked. This is possible by using the

CLK

not used. The CLK/

to 2.4 GHz.

input can be used for frequencies up

Rev. 0 | Page 37 of 84

AD9516-3

Holdover

Automatic/Internal Holdover Mode

The AD9516 PLL has a holdover function. Holdover is

implemented by putting the charge pump into a high

impedance state. This is useful when the PLL reference clock is

lost. Holdover mode allows the VCO to maintain a relatively

constant frequency even though there is no reference clock.

Without this function, the charge pump is placed into a

constant pump-up or pump-down state, resulting in a massive

VCO frequency shift. Because the charge pump is placed in a

high impedance state, any leakage that occurs at the charge

pump output or the VCO tuning node causes a drift of the VCO

frequency. This can be mitigated by using a loop filter that

contains a large capacitive component because this drift is

limited by the current leakage induced slew rate (I_LEAK/C) of the

VCO control voltage.

When enabled, this function automatically puts the charge

pump into a high impedance state when the loop loses lock.

The assumption is that the only reason the loop loses lock is due

to the PLL losing the reference clock; therefore, the holdover

function puts the charge pump into a high impedance state to

maintain the VCO frequency as close as possible to the original

frequency before the reference clock disappeared.

A flow chart of the internal/automatic holdover function

operation is shown in Figure 51.

PLL ENABLED

LOOP OUT OF LOCK. DIGITAL LOCK

NO

DETECT SIGNAL GOES LOW WHEN THE

LOOP LEAVES LOCK AS DETERMINED

BY THE PHASE DIFFERENCE AT THE

SYNC

Both a manual holdover, using the

pin, and an automatic

DLD == LOW

INPUT OF THE PFD.

holdover mode are provided. To use either function, the

holdover function must be enabled (0x1D<0> and 0x1D<2>).

YES

NO

[Note that the VCO cannot be calibrated with the holdover

enabled because the holdover resets the N divider during

calibration, which prevents proper calibration. Disable holdover

before issuing a VCO calibration.]

ANALOG LOCK DETECT PIN INDICATES

WAS

LOCK WAS PREVIOUSLY ACHIEVED.

(0x1D<3> = 1: USE LD PIN VOLTAGE

WITH HOLDOVER.

LD PIN == HIGH

WHEN DLD WENT

LOW?

0x1D<3> = 0: IGNORE LD PIN VOLTAGE,

TREAT LD PIN AS ALWAYS HIGH.)

YES

Manual Holdover Mode

CHARGE PUMP IS MADE

HIGH IMPEDANCE.

A manual holdover mode can be enabled that allows the user to

place the charge pump into a high impedance state when the

HIGH IMPEDANCE

CHARGE PUMP

PLL COUNTERS CONTINUE

OPERATING NORMALLY.

YES

SYNC

pin is asserted low. This operation is edge sensitive, not

NO

level sensitive. The charge pump enters a high impedance state

immediately. To take the charge pump out of a high impedance

CHARGE PUMP REMAINS HIGH

IMPEDANCE UNTIL THE REFERENCE

HAS RETURNED.

REFERENCE

EDGE AT PFD?

SYNC

state take the

pin high. The charge pump then leaves

high impedance state synchronously with the next PFD rising

edge from the reference clock. This prevents extraneous charge

YES

SYNC

pump events from occurring during the time between

RELEASE

TAKE CHARGE PUMP OUT OF

HIGH IMPEDANCE. PLL CAN

NOW RESETTLE.

CHARGE PUMP

HIGH IMPEDANCE

going high and the next PFD event. This also means that the

charge pump stays in a high impedance state as long as there is

no reference clock present.

YES

The B-counter (in the N divider) is reset synchronously with

the charge pump leaving the high impedance state on the

reference path PFD event. This helps align the edges out of the

R and N dividers for faster settling of the PLL. Because the

prescaler is not reset, this feature works best when the B and R

numbers are close because this results in a smaller phase

difference for the loop to settle out.

NO

WAIT FOR DLD TO GO HIGH. THIS TAKES

5 TO 255 CYCLES (PROGRAMMING OF THE DLD

DELAY COUNTER) WITH THE REFERENCE AND

FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT

THE PFD. THIS ENSURES THAT THE HOLDOVER

FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK

BEFORE THE HOLDOVER FUNCTION CAN BE

RETRIGGERED.

DLD == HIGH

Figure 51. Flowchart of Automatic/Internal Holdover Mode

The holdover function senses the logic level of the LD pin as a

condition to enter holdover. The signal at LD can be from the

DLD, ALD, or current source LD mode. It is possible to disable

the LD comparator (0x1D<3>), which causes the holdover

function to always sense LD as high. If DLD is used, it is

possible for the DLD signal to chatter some while the PLL is

reacquiring lock. The holdover function may retrigger, thereby

preventing the holdover mode from terminating. Use of

the current source lock detect mode is recommended to avoid this

situation (see the Current Source Digital Lock Detect section).

When using this mode, the channel dividers should be set to

SYNC

ignore the

pin (at least after an initial

event). If the

SYNC

is

dividers are not set to ignore the

pin, any time

taken low to put the part into holdover, the distribution outputs

turn off.

Rev. 0 | Page 38 of 84

AD9516-3

Once in holdover mode, the charge pump stays in a high

impedance state as long as there is no reference clock present.

For example, to use automatic holdover with:

• Automatic reference switchover, prefer REF1.

As in the external holdover mode, the B counter (in the N

divider) is reset synchronously with the charge pump leaving

high impedance state on the reference path PFD event. This

helps align the edges out of the R and N dividers for faster

settling of the PLL and to reduce frequency errors during

settling. Because the prescaler is not reset, this feature works

best when the B and R numbers are close because this results in

a smaller phase difference for the loop to settle out.

• Digital lock detect: five PFD cycles, high range window.

• Automatic holdover using the LD pin comparator.

The following registers are set (in addition to the normal PLL

registers):

• 0x18<6:5> = 00b; lock detect counter = five cycles.

• 0x18<4> = 0b; lock detect window = high range.

• 0x18<3> = 0b; DLD normal operation.

After leaving holdover, the loop then reacquires lock and the

LD pin must charge (if 0x1D<3> = 1) before it can re-enter

holdover (CP high impedance).

• 0x1A<5:0> = 000100b; current source lock detect mode.

• 0x1C<4> = 1b; automatic reference switchover enabled.

• 0x1C<3> = 0b; prefer REF1.

The holdover function always responds to the state of the

currently selected reference (0x1C). If the loop loses lock during

a reference switchover (see the Reference Switchover section),

holdover is triggered briefly until the next reference clock edge

at the PFD.

• 0x1C<2:1> = 11b; enable REF1 and REF2 input buffers.

• 0x1D<3> = 1b; enable LD pin comparator.

• 0x1D<2> = 1b; enable the holdover function.

• 0x1D<1> = 0b; use internal/automatic holdover mode.

• 0x1D<0> = 1b; enable the holdover function.

Frequency Status Monitors

The following registers affect the internal/automatic holdover

function:

• 0x18<6:5>—lock detect counter. This changes how many

consecutive PFD cycles with edges inside the lock detect

window are required for the DLD indicator to indicate lock.

This impacts the time required before the LD pin can begin

to charge as well as the delay from the end of a holdover

event until the holdover function can be re-engaged.

The AD9516 contains three frequency status monitors that are

used to indicate if the PLL reference (or references in the case of

single-ended mode) and the VCO have fallen below a threshold

frequency. A diagram showing their location in the PLL is

shown in Figure 52.

• 0x18<3>—disable digital lock detect. This bit must be set to a

0 to enable the DLD circuit. Internal/automatic holdover does

not operate correctly without the DLD function enabled.

The PLL reference monitors have two threshold frequencies:

normal and extended (see Table 16). The reference frequency

monitor thresholds are selected in 0x1F.

• 0x1A<5:0>—lock detect pin output select. Set this to 000100b

to put it in the current source lock detect mode if using the

LD pin comparator. Load the LD pin with a capacitor of an

appropriate value.

• 0x1D<3>—enable LD pin comparator. 1 = enable; 0 =

disable. When disabled, the holdover function always senses

the LD pin as high.

• 0x1D<1>—enable external holdover control.

• 0x1D<0> and Register 0x1D<2>—holdover function enable.

If holdover is disabled, both external and internal/automatic

holdover are disabled.

Rev. 0 | Page 39 of 84

AD9516-3

REF_SEL

VS

GND

RSET

REFMON

CPRSET VCP

DISTRIBUTION

REFERENCE

SWITCHOVER

LD

REF1

REF2

LOCK

DETECT

STATUS

R

PROGRAMMABLE

R DELAY

DIVIDER

REFIN (REF1)

REFIN (REF2)

HOLD

N DIVIDER

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

LOW DROPOUT

REGULATOR (LDO)

BYPASS

LF

PROGRAMMABLE

N DELAY

CP

P, P + 1

A/B

PRESCALER

COUNTERS

VCO STATUS

VCO

STATUS

0

DIVIDE BY

2, 3, 4, 5, OR 6

CLK

1

0

Figure 52. Reference and VCO Status Monitors

VCO Calibration

A SYNC is executed during the VCO calibration; therefore, the

outputs of the AD9516 are held static during the calibration,

which prevents unwanted frequencies from being produced.

However, at the end of a VCO calibration, the outputs may

resume clocking before the PLL loop is completely settled.

The AD9516 on-chip VCO must be calibrated to ensure proper

operation over process and temperature. The VCO calibration

is controlled by a calibration controller running off of a divided

REFIN clock. The calibration requires that the PLL be set up

properly to lock the PLL loop and that the REFIN clock be

present. During the first initialization after a power-up or a

reset of the AD9516, a VCO calibration sequence is initiated by

setting 0x18<0> = 1b. This can be done as part of the initial

setup before executing update registers (0x232<0> = 1b).

Subsequent to the initial setup, a VCO calibration sequence is

initiated by resetting 0x18<0> = 0b, executing an update registers

operation, setting 0x18<0> = 1b, and executing another update

registers operation. A readback bit (0x1F<6>) indicates when a

VCO calibration is finished by returning a logic true (that is, 1b).

The VCO calibration clock divider is set as shown in Table 53

(0x18<2:1>).

The calibration divider divides the PFD frequency (reference

frequency divided by R) down to the calibration clock. The

calibration occurs at the PFD frequency divided by the

calibration divider setting. Lower VCO calibration clock

frequencies result in longer times for a calibration to be

completed.

The VCO calibration clock frequency is given by

f_{CAL_CLOCK}= f_REFIN/(R × cal_div)

where:

The sequence of operations for the VCO calibration is:

• Program the PLL registers to the proper values for the PLL loop.

f

_REFINis the frequency of the REFIN signal.

• For the initial setting of the registers after a power-up or

reset, initiate a VCO calibration by setting 0x18<0> = 1b.

Subsequently, whenever a calibration is desired, set 0x18<0> =

0b, update registers, and set 0x18<0> = 1b, update registers.

R is the value of the R divider.

cal_div is the division set for the VCO calibration divider

(0x18<2:1>).

The VCO calibration takes 4400 calibration clock cycles.

Therefore, the VCO calibration time in PLL reference clock

cycles is given by

• A SYNC operation is initiated internally, causing the outputs

to go to a static state determined by normal SYNC function

operation.

Time to Calibrate VCO =

• VCO calibrates to the desired setting for the requested VCO

frequency.

4400 × R × cal_div PLL Reference Clock Cycles

Table 29. Example Time to Complete a VCO Calibration with

Different f_REFINFrequencies

• Internally, the SYNC signal is released, allowing outputs to

continue clocking.

f_REFIN(MHz) R Divider PFD

Time to Calibrate VCO

• PLL loop is closed.

• PLL locks.

100

10

1

10

100

100 MHz 88 μs

1 MHz

8.8 ms

88 ms

100 kHz

Rev. 0 | Page 40 of 84

AD9516-3

VCO calibration must be manually initiated. This allows for

flexibility in deciding what order to program registers and when

to initiate a calibration, instead of having it happen every time

certain PLL registers have their values change. For example, this

allows for the VCO frequency to be changed by small amounts

without having an automatic calibration occur each time; this

should be done with caution and only when the user knows the

VCO control voltage is not going to exceed the nominal best

performance limits. For example, a few 100 kHz steps are fine,

but a few MHz might not be. Additionally, as the calibration

procedure results in rapid changes in the VCO frequency, the

distribution section is automatically placed in SYNC until the

calibration is finished. Therefore, this temporary loss of outputs

must be expected.

The channel dividers allow for a selection of various duty cycles,

depending on the currently set division. That is, for any specific

division, D, the output of the divider can be set to high for

N + 1 input clock cycles and low for M + 1 input clock cycles

(where D = N + M + 2). For example, a divide-by-5 can be high

for one divider input cycle and low for four cycles, or a divide-

by-5 can be high for three divider input cycles and low for two

cycles. Other combinations are also possible.

The channel dividers include a duty-cycle correction function

that can be disabled. In contrast to the selectable duty cycle

just described, this function can correct a non-50ꢀ duty cycle

caused by an odd division. However, this requires that the

division be set by M = N + 1.

In addition, the channel dividers allow a coarse phase offset or

delay to be set. Depending on the division selected, the output

can be delayed by up to 31 input clock cycles. The divider

outputs can also be set to start high or to start low.

A VCO calibration should be initiated under the following

conditions:

• After changing any of the PLL R, P, B, and A divider settings,

or after a change in the PLL reference clock frequency. This,

in effect, means any time a PLL register or reference clock is

changed such that a different VCO frequency results.

Internal VCO or External CLK as Clock Source

The clock distribution of the AD9516 has two clock input

sources: an internal VCO or an external clock connected to the

• Whenever system calibration is desired. The VCO is designed

to operate properly over extremes of temperatures even when

it is first calibrated at the opposite extreme. However, a VCO

calibration can be initiated at any time, if desired.

CLK

CLK/

pins. Either the internal VCO or CLK must be

chosen as the source of the clock signal to distribute. When the

internal VCO is selected as the source, the VCO divider must be

used. When CLK is selected as the source, it is not necessary to

use the VCO divider if the CLK frequency is less than the

maximum channel divider input frequency (1600 MHz);

otherwise, the VCO divider must be used to reduce the

frequency to one acceptable by the channel dividers. Table 30

shows how the VCO, CLK, and VCO divider are selected.

0x1E1<1:0> selects the channel divider source and determines

whether the VCO divider is used. It is not possible to select the

VCO without using the VCO divider.

CLOCK DISTRIBUTION

A clock channel consists of a pair (or double pair, in the case of

CMOS) of outputs that share a common divider. A clock output

consists of the drivers that connect to the output pins. The clock

outputs have either LVPECL or LVDS/CMOS signal levels at

the pins.

The AD9516 has five clock channels: three channels are

LVPECL (six outputs); two channels are LVDS/CMOS (up

to four LVDS outputs, or up to eight CMOS outputs).

Table 30. Selecting VCO or CLK as Source for Channel

Divider, and Whether VCO Divider Is Used

0x1E1

Each channel has its own programmable divider that divides

the clock frequency applied to its input. The LVPECL channel

dividers contain a divider that can divide by any integer from

1 to 32. Each LVDS/CMOS channel divider contains two

cascaded dividers that can be set to divide by any integer from

1 to 32. The total division of the channel is the product of the

divide value of the two cascaded dividers. This allows divide

values of (1 to 32) × (1 to 32), or up to 1024 (notice that this is

not all values from 1 to 1024 but only the set of numbers that

are the product of the two dividers).

Channel Divider Source

VCO Divider

Used

<1>

0

1

<0>

0

1

0

1

CLK

VCO

Not used

Used

Not allowed

CLK or VCO Direct to LVPECL Outputs

It is possible to connect either the internal VCO or the CLK

(whichever is selected as the input to the VCO divider) directly

to the LVPECL outputs, OUT0 to OUT5. This configuration

can pass frequencies up to the maximum frequency of the VCO

directly to the LVPECL outputs. The LVPECL outputs may not

be able to provide full a voltage swing at the highest frequencies.

Because the internal VCO frequency is above the maximum

channel divider input frequency (1600 MHz), the VCO divider

must be used after the on-chip VCO. The VCO divider can be

set to divide by 2, 3, 4, 5, or 6. External clock signals connected

to the CLK input also require the VCO divider if the frequency

of the signal is greater than 1600 MHz.

Rev. 0 | Page 41 of 84

AD9516-3

To connect the LVPECL outputs directly to the internal VCO or

CLK, the VCO divider must be selected as the source to the

distribution section, even if no channel uses it.

The channel dividers feeding the LVPECL output drivers

contain one 2-to-32 frequency divider. This divider provides for

division by 1 to 32. Division by 1 is accomplished by bypassing

the divider. The dividers also provide for a programmable duty

cycle, with optional duty-cycle correction when the divide ratio

is odd. A phase offset or delay in increments of the input clock

cycle is selectable. The channel dividers operate with a signal at

their inputs up to 1600 MHz. The features and settings of the

dividers are selected by programming the appropriate setup

and control registers (see Table 51 through Table 61).

Either the internal VCO or the CLK can be selected as the

source for the direct to output routing.

Table 31. Settings for Routing VCO Divider Input Directly

to LVPECL Outputs

Register Setting

0x1E1<1:0> = 00b

0x1E1<1:0> = 10b

0x192<1> = 1b

0x195<1> = 1b

0x198<1> = 1b

Selection

CLK is the source; VCO divider selected

VCO is the source; VCO divider selected

Direct to output OUT0, OUT1

Direct to output OUT2, OUT3

Direct to output OUT4, OUT5

VCO Divider

The VCO divider provides frequency division between the

internal VCO or the external CLK input and the clock

distribution channel dividers. The VCO divider can be set

to divide by 2, 3, 4, 5, or 6 (see Table 59, 0x1E0<2:0>).

Clock Frequency Division

Channel Dividers—LVPECL Outputs

The total frequency division is a combination of the VCO

divider (when used) and the channel divider. When the VCO

divider is used, the total division from the VCO or CLK to the

output is the product of the VCO divider (2, 3, 4, 5, and 6) and

the division of the channel divider. Table 32 and Table 33 indicate

how the frequency division for a channel is set. For the LVPECL

outputs, there is only one divider per channel. For the LVDS/

CMOS outputs, there are two dividers (X.1, X.2) cascaded

per channel.

Each pair of LVPECL outputs is driven by a channel divider.

There are three channel dividers (0, 1, and 2) driving six

LVPECL outputs (OUT0 to OUT5). Table 34 gives the register

locations used for setting the division and other functions of

these dividers. The division is set by the values of M and N. The

divider can be bypassed (equivalent to divide-by-1, divider circuit

is powered down) by setting the bypass bit. The duty-cycle

correction can be enabled or disabled according to the setting of

the DCCOFF bits.

Table 32. Frequency Division for Divider 0 to Divider 2

CLK or VCO VCO

Channel

Divider

Direct to Frequency

Table 34. Setting D_Xfor Divider 0, Divider 1, and Divider 2

Selected

CLK/VCO

Divider

Output

Division

Low Cycles High Cycles

2 to 6

1 (bypassed) Yes

1 (bypassed) No

1

Divider

M

N

Bypass

DCCOFF

(2 to 6) × (1)

0

1

2

0x190<7:4> 0x190<3:0> 0x191<7> 0x192<0>

0x193<7:4> 0x193<3:0> 0x194<7> 0x195<0>

0x196<7:4> 0x196<3:0> 0x197<7> 0x198<0>

(2 to 6) ×

(2 to 32)

2 to 6

2 to 32

1 (bypassed) No

2 to 32 No

No

CLK

Not

used

Not

1

Channel Frequency Division (0, 1, and 2)

2 to 32

used

For each channel (where the channel number is x: 0, 1, or 2),

the frequency division, D_X, is set by the values of M and N

(four bits each, representing decimal 0 to 15), where

Table 33. Frequency Division for Divider 3 and Divider 4

Number of Low Cycles = M + 1

Number of High Cycles = N + 1

CLK or

VCO

Selected

Channel Divider

VCO

Divider

Frequency

Division

X.1

X.2

The cycles are cycles of the clock signal currently routed to the

input of the channel dividers (VCO divider out or CLK).

CLK/VCO

2 to 6

1

(2 to 6) ×

(bypassed) (bypassed) (1) × (1)

2 to 32

1

(2 to 6) ×

When a divider is bypassed, D_X= 1.

(bypassed) (2 to 32) × (1)

2 to 32

Otherwise, D_X= (N + 1) + (M + 1) = N + M + 2. This allows

each channel divider to divide by any integer from 1 to 32.

(2 to 6) ×

(2 to 32) ×

(2 to 32)

CLK

Not

used

Not

used

Not

used

1

2 to 32

1

(2 to 32) × (1)

2 to 32

2 to 32 ×

(2 to 32)

Rev. 0 | Page 42 of 84

AD9516-3

Duty Cycle and Duty-Cycle Correction (0, 1, and 2)

The duty cycle of the clock signal at the output of a channel is a

result of some or all of the following conditions:

Table 36. Duty Cycle with VCO Divider, Input Duty Cycle Is X%

D_X

Output Duty Cycle

VCO

Divider

N + M + 2 DCCOFF = 1 DCCOFF = 0

• What are the M and N values for the channel?

• Is the DCC enabled?

Even

1 (divider

bypassed)

50%

Odd = 3 1 (divider

bypassed)

Odd = 5 1 (divider

bypassed)

33.3%

40%

(1 + X%)/3

(2 + X%)/5

• Is the VCO divider used?

• What is the CLK input duty cycle? (The internal VCO has a

50ꢀ duty cycle.)

Even

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

(N + 1)/

(N + M + 2)

50%,

requires M = N

50%,

requires M = N + 1

50%,

requires M = N

(3N + 4 + X%)/(6N + 9),

requires M = N + 1

50%,

The DCC function is enabled by default for each channel

divider. However, the DCC function can be disabled

individually for each channel divider by setting the

DCCOFF bit for that channel.

Odd

Odd = 3 Even

Odd = 3 Odd

Odd = 5 Even

Odd = 5 Odd

Certain M and N values for a channel divider result in a non-

50ꢀ duty cycle. A non-50ꢀ duty cycle can also result with an

even division, if M ≠ N. The duty-cycle correction function

automatically corrects non-50ꢀ duty cycles at the channel

divider output to 50ꢀ duty cycle. Duty-cycle correction

requires the following channel divider conditions:

requires M = N

(5N + 7 + X%)/(10N + 15),

requires M = N + 1

• An even division must be set as M = N

• An odd division must be set as M = N + 1

Table 37. Channel Divider Output Duty Cycle When the

VCO Divider Is Not Used

When not bypassed or corrected by the DCC function, the duty

cycle of each channel divider output is the numerical value of

(N + 1)/(N + M + 2) expressed as a ꢀ.

D_X

Output Duty Cycle

Input Clock

Duty Cycle

N + M + 2 DCCOFF = 1 DCCOFF = 0

Any

50%

X%

1

1 (divider

bypassed)

(N + 1)/

(M + N + 2)

(N + 1)/

(M + N + 2)

(N + 1)/

(M + N + 2)

Same as input

duty cycle

50%, requires M = N

The duty cycle at the output of the channel divider for various

configurations is shown in Table 35 to Table 37.

Even

Odd

Table 35. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%

50%, requires

M = N + 1

(N + 1 + X%)/(2 × N + 3),

requires M = N + 1

D_X

Output Duty Cycle

VCO

Divider

N + M + 2 DCCOFF = 1 DCCOFF = 0

Even

1 (divider

bypassed)

50%

Odd = 3

Odd = 5

1 (divider

bypassed)

1 (divider

bypassed)

33.3%

40%

50%

The internal VCO has a duty cycle of 50ꢀ. Therefore, when the

VCO is connected directly to the output, the duty cycle is 50ꢀ.

If the CLK input is routed directly to the output, the duty cycle of

the output is the same as the CLK input.

50%

Even, Odd Even

Even, Odd Odd

(N + 1)/

(N + M + 2)

(N + 1)/

50%; requires M = N

50%; requires M = N + 1

(N + M + 2)

Rev. 0 | Page 43 of 84

AD9516-3

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

Phase Offset or Coarse Time Delay (0, 1, and 2)

CHANNEL

DIVIDER INPUT

Each channel divider allows for a phase offset, or a coarse time

delay, to be programmed by setting register bits (see Table 38).

These settings determine the number of cycles (successive

rising edges) of the channel divider input frequency by which to

offset, or delay, the rising edge of the output of the divider. This

delay is with respect to a nondelayed output (that is, with a

phase offset of zero). The amount of the delay is set by 5 bits

loaded into the phase offset (PO) register plus the start high

(SH) bit for each channel divider. When the start high bit is set,

the delay is also affected by the number of low cycles (M)

programmed for the divider.

Tx

TPUTS

CHANNEL DIVIDER OU

DIV = 4, DUTY = 50%

SH = 0

PO = 0

DIVIDER 0

DIVIDER 1

DIVIDER 2

SH = 0

PO = 1

SH = 0

PO = 2

1 × Tx

2 × Tx

Figure 53. Effect of Coarse Phase Offset (or Delay)

Channel Dividers—LVDS/CMOS Outputs

Channel Divider 3 and Channel Divider 4 each drive a pair of

LVDS outputs, giving four LVDS outputs (OUT6 to OUT9).

Alternatively, each of these LVDS differential outputs can be

configured individually as a pair (A and B) of CMOS single-

ended outputs, providing for up to eight CMOS outputs. By

default, the B output of each pair is off but can be turned on as

desired.

It is necessary to use the SYNC function to make phase offsets

effective (See the Synchronizing the Outputs—SYNC Function

section).

Table 38. Setting Phase Offset and Division for Divider 0,

Divider 1, and Divider 2

Start

Divider High (SH) Offset (PO)

Phase

Low Cycles High Cycles

M

N

Channel Divider 3 and Channel Divider 4 each consist of two

cascaded, 1 to 32, frequency dividers. The channel frequency

division is D_X.1× D_X.2or up to 1024. Both of the dividers also

have DCC enabled by default, but this function can be disabled,

if desired, by setting the DCCOFF bit of the channel. A coarse

phase offset or delay is also programmable (see the Phase Offset

or Coarse Time Delay (Divider 3 and Divider 4) section). The

channel dividers operate up to 1600 MHz. The features and

settings of the dividers are selected by programming the

appropriate setup and control registers (see Table 51 and Table

52 through Table 61).

0

1

2

0x191<4> 0x191<3:0> 0x190<7:4> 0x190<3:0>

0x194<4> 0x194<3:0> 0x193<7:4> 0x193<3:0>

0x197<4> 0x197<3:0> 0x196<7:4> 0x196<3:0>

Let

Δ_t= delay (in seconds).

Δ_c= delay (in cycles of clock signal at input to D_X).

T_X= period of the clock signal at the input of the divider, D_X(in

seconds).

Φ =

16 × SH<4> + 8 × PO<3> + 4 × PO<2> + 2 × PO<1> + 1 × PO<0>

The channel divide-by is set as N = high cycles and M = low

cycles.

Table 39. Setting Division (D_X) for Divider 3 and Divider 4

Divider

M

N

Bypass

DCCOFF

Case 1

3

4

3.1 0x199<7:4> 0x199<3:0> 0x19C<4> 0x19D<0>

3.2 0x19B<7:4> 0x19B<3:0> 0x19C<5> 0x19D<0>

4.1 0x19E<7:4> 0x19E<3:0> 0x1A1<4> 0x1A2<0>

4.2 0x1A0<7:4> 0x1A0<3:0> 0x1A1<5> 0x1A2<0>

For Φ ≤ 15:

Δ_t= Φ × T_X

Δ_c= Δ_t/T_X= Φ

Case 2

Channel Frequency Division (Divider 3 and Divider 4)

For Φ ≥ 16:

Δ_t= (Φ − 16 + M + 1) × T_X

Δ_c= Δ_t/T_X

The division for each channel divider is set by the bits in the

registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2).

By giving each divider a different phase offset, output-to-output

delays can be set in increments of the channel divider input

clock cycle. Figure 53 shows the results of setting such a coarse

offset between outputs.

Number of Low Cycles = M_X.Y+ 1

Number of High Cycles = N_X.Y+ 1

When both X.1 and X.2 are bypassed, D_X= 1 × 1 = 1.

When only X.2 is bypassed, D_X= (N_X.1+ M_X.1+ 2) × 1.

When both X.1 and X.2 are not bypassed, D_X= (N_X.1+ M_X.1+ 2) ×

(N_X.2+ M_X.2+ 2).

Rev. 0 | Page 44 of 84

AD9516-3

By cascading the dividers, channel division up to 1024 can be

obtained. However, not all integer value divisions from 1 to

1024 are obtainable; only the values that are the product of the

separate divisions of the two dividers (D_X.1× D_X.2) can be realized.

Table 41. Divider 3 and Divider 4 Duty Cycle; VCO Divider

Not Used; Duty Cycle Correction Off (DCCOFF = 1)

D_X.1

D_X.2

Output

Duty Cycle

Input Clock

Duty Cycle

N

_X.1+ M_X.1+ 2 N_X.2+ M_X.2+ 2

If only one divider is needed when using Divider 3 and Divider 4,

use the first one (X.1) and bypass the second one (X.2). Do not

bypass X.1 and use X.2.

50%

X%

1

50%

X%

50%

Even, Odd

1

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

(N_X.2+ 1)/

(N_X.2+ M_X.2+ 2)

(N_X.2+ 1)/

Duty Cycle and Duty-Cycle Correction (Divider 3 and

Divider 4)

X%

1

The same duty cycle and DCC considerations apply to Divider 3

and Divider 4 as to Divider 0, Divider 1, and Divider 2 (see

Duty Cycle and Duty-Cycle Correction (0, 1, and 2)); however,

with these channel dividers, the number of possible

configurations is even more complex.

50%

X%

Even, Odd

(N_X.2+ M_X.2+ 2)

Duty-cycle correction on Divider 3 and Divider 4 requires the

following channel divider conditions:

Table 42. Divider 3 and Divider 4 Duty Cycle; VCO Divider

Used; Duty Cycle Correction Is On (DCCOFF = 0); VCO

Divider Input Duty Cycle = 50%

• An even D_X.Ymust be set as M_X.Y= N_X.Y(low cycles = high

cycles).

D_X.1

D_X.2

VCO

Output

Divider

Duty Cycle

• An odd D_X.Ymust be set as M_X.Y= N_X.Y+ 1 (the number of

low cycles must be one greater than the number of high cycles).

N_X.1+ M_X.1+ 2

1

Even (N_X.1= M_X.1)

Odd (M_X.1= N_X.1+ 1)

Even (N_X.1= M_X.1)

N_X.2+ M_X.2+ 2

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

Even

Odd

1

50%

• If only one divider is bypassed, it must be the second

divider, X.2.

• If only one divider has an even divide by, it must be the

second divider, X.2.

Even (N_X.2= M_X.2)

The possibilities for the duty cycle of the output clock from

Divider 3 and Divider 4 are shown in Table 40 through Table 44

Odd (M_X.1= N_X.1+ 1) Even (N_X.2= M_X.2)

Table 40. Divider 3 and Divider 4 Duty Cycle; VCO Divider

Used; Duty Cycle Correction Off (DCCOFF = 1)

Odd (M_X.1= N_X.1+ 1) Odd (M_X.2= N_X.2+ 1) 50%

D_X.1

D_X.2

VCO

Divider

Output Duty Cycle

N

1

_X.1+ M_X.1+ 2

N_X.2+ M_X.2+ 2

Even

1

50%

33.3%

40%

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

(N_X.1+ 1)/

(N_X.1+ M_X.1+ 2)

(N_X.2+ 1)/

(N_X.2+ M_X.2+ 2)

Odd = 3

Odd = 5

Even

Even, Odd

Odd

Even

Odd

1

Even, Odd

(N_X.2+ 1)/

(N_X.2+ M_X.2+ 2)

Rev. 0 | Page 45 of 84

AD9516-3

Table 44. Divider 3 and Divider 4 Duty Cycle; VCO Divider

Not Used; Duty Cycle Correction On (DCCOFF = 0)

Input

Table 43. Divider 3 and Divider 4 Duty Cycle; VCO Divider

Used; Duty Cycle Correction On (DCCOFF = 0); VCO

Divider Input Duty Cycle = X%

D_X.1

D_X.2

Clock

Duty

Cycle N_X.1+ M_X.1+ 2

D_X.1

D_X.2

Output

Duty Cycle

VCO

Output

N_X.2+ M_X.2+ 2

Divider

Duty Cycle

N_X.1+ M_X.1+ 2 N_X.2+ M_X.2+ 2

50%

1

Even

1

50%

Even

Odd = 3

Odd = 5

1

50%

(1 + X%)/3

(2 + X%)/5

(N_X.1= M_X.1)

X%

1

Even

1

X% (High)

50%

Even

(N_X.1= M_X.1)

Even

(N_X.1= M_X.1)

Odd

(M_X.1= N_X.1+ 1)

Odd

(M_X.1= N_X.1+ 1)

Odd

(M_X.1= N_X.1+ 1)

Even

(N_X.1= M_X.1)

Even

(N_X.1= M_X.1)

Odd

Even

1

50%

(N_X.1= M_X.1)

Odd

50%

X%

Odd

(M_X.1= N_X.1+ 1)

Odd

(M_X.1= N_X.1+ 1)

Odd

(M_X.1= N_X.1+ 1)

1

50%

Even

(N_X.1+ 1 + X%)/

(2N_X.1+ 3)

(N_X.1+ 1 + X%)/

(2N_X.1+ 3)

(3N_X.1+ 4 + X%)/

(6N_X.1+ 9)

(5N_X.1+ 7 + X%)/

(10N_X.1+ 15)

Odd = 3

Odd = 5

Even

50%

X%

Even

(N_X.1= M_X.1)

Even

(N_X.1= M_X.1)

Odd

(M_X.1= N_X.1+ 1)

Odd

(M_X.1= N_X.1+ 1)

Odd

(M_X.1= N_X.1+ 1)

Odd

(M_X.1= N_X.1+ 1)

Even

(N_X.2= M_X.2)

Even

(N_X.2= M_X.2)

Even

(N_X.2= M_X.2)

Even

(N_X.2= M_X.2)

Odd

(M_X.2= N_X.2+ 1)

Odd

(M_X.2= N_X.2+ 1)

50%

Even

(N_X.2= M_X.2)

Even

(N_X.2= M_X.2)

50%

Odd

50%

X%

Even

(M_X.1= N_X.1+ 1) (N_X.2= M_X.2)

Odd Even

(M_X.1= N_X.1+ 1) (N_X.2= M_X.2)

Odd Odd

(M_X.1= N_X.1+ 1) (M_X.2= N_X.2+ 1)

Odd

50%

X%

Even

50%

(2N_X.1N_X.2+ 3N_X.1

3N_X.2+ 4 + X%)/

+

(6N_X.1N_X.2+ 9N_X.1

9N_X.2+ 13 + X%)/

+

((2N_X.1+ 3)(2N_X.2+ 3))

Odd

Odd = 3

Odd = 5

(M_X.1= N_X.1+ 1) (M_X.2= N_X.2+ 1) (3(2N_X.1+ 3)

(2N_X.2+ 3))

Phase Offset or Coarse Time Delay (Divider 3 and Divider 4)

(10N_X.1N_X.2+ 15N_X.1

15N_X.2+ 22 + X%)/

+

Divider 3 and Divider 4 can be set to have a phase offset or

delay. The phase offset is set by a combination of the bits in the

phase offset and start high registers (see Table 45).

Odd

(M_X.1= N_X.1+ 1) (M_X.2= N_X.2+ 1) (5(2 N_X.1+ 3)

(2 N_X.2+ 3))

Table 45. Setting Phase Offset and Division for Divider 3 and

Divider 4

Start

Divider High (SH) Offset (PO) Cycles M

Phase

Low

High

Cycles N

3

3.1 0x19C<0> 0x19A<3:0> 0x199<7:4> 0x199<3:0>

3.2 0x19C<1> 0x19A<7:4> 0x19B<7:4> 0x19B<3:0>

4.1 0x1A1<0> 0x19F<3:0> 0x19E<7:4> 0x19E<3:0>

4.2 0x1A1<1> 0x19F<7:4> 0x1A0<7:4> 0x1A0<3:0>

4

Let:

Δ_t= delay (in seconds).

_x.y= 16 × SH<0> + 8 × PO<3> + 4 × PO<2> + 2 × PO<1> +

1 × PO<0>.

Φ

T

_X.1= period of the clock signal at the input to D_X.1(in seconds).

T_X.2= period of the clock signal at the input to D_X.2(in seconds).

Rev. 0 | Page 46 of 84

AD9516-3

Case 1

Calculating the Fine Delay

When Φ_x.1≤ 15 and Φ_x.2≤ 15:

Δ_t= Φ_x.1× T_X.1+ Φ_X.2× T_x.2

Case 2

The following values and equations are used to calculate the

delay of the delay block.

I

_RAMP(μA) = 200 × (Ramp Current + 1)

Number of Capacitors = Number of Bits =

0 in Ramp Capacitors + 1

When Φ_x.1≤ 15 and Φ_x.2≥ 16:

Δ_t= Φ_X.1× T_X.1+ (Φ_X.2– 16 + M_X.2+ 1) × T_X.2

Case 3

Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3;

001 = 2 + 1 = 3; 111 = 0 + 1 = 1.

When Φ_X.1≥ 16 and Φ_X.2≤ 15:

Δ_t= (Φ_X.1− 16 + M_X.1+ 1) × T_X.1+ Φ_X.2× T_X.2

Case 4

Delay Range (ns) = 200 × ((No. of Caps + 3)/(I_RAMP)) × 1.3286

⎛ No.of Caps −1⎞

×10⁻⁴

+

×6

⎜

⎝

⎟

⎠

Offset

(

ns

)

= 0.34 +

(

1600 − I_RAMP

)

I_RAMP

When Φ_X.1≥ 16 and Φ_X.2≥ 16:

Δ_t=

Delay Full Scale (ns) = Delay Range + Offset

Fine Delay (ns) =

Delay Range × Delay Fraction × (1/63) + Offset

(Φ_X.1− 16 + M_X.1+ 1) × T_X.1+ (Φ_X.2− 16 + M_X.2+ 1) × T_X.2

Fine Delay Adjust (Divider 3 and Divider 4)

Note that only delay fraction values up to 47 decimal (101111b;

0x2F) are supported.

Each AD9516 LVDS/CMOS output (OUT6 to OUT9) includes

an analog delay element that can be programmed to give

variable time delays (Δ_t) in the clock signal at that output.

In no case can the fine delay exceed one-half of the output clock

period. If a delay longer than half of the clock period is

attempted, the output stops clocking.

VCO

CLK DIVIDER

BYPASS

CMOS

LVDS

CMOS

OUTM

The delay function adds some jitter greater than that specified

for the nondelayed output. This means that the delay function

should be used primarily for clocking digital chips, such as

FPGA, ASIC, DUC, and DDC. An output with this delay

enabled may not be suitable for clocking data converters. The

jitter is higher for long full scales because the delay block uses a

ramp and trip points to create the variable delay. A slower ramp

time produces more time jitter.

ΔT

FINE DELAY

ADJUST

OUTPUT

DRIVERS

DIVIDER

X.1

DIVIDER

X.2

BYPASS

CMOS

LVDS

CMOS

OUTN

ΔT

FINE DELAY

ADJUST

Figure 54. Fine Delay (OUT6 to OUT9)

Synchronizing the Outputs—SYNC Function

The amount of delay applied to the clock signal is determined

by programming four registers per output (see Table 46).

The AD9516 clock outputs can be synchronized to each other.

Outputs can be individually excluded from synchronization.

Synchronization consists of setting the nonexcluded outputs to

a preset set of static conditions and subsequently releasing these

outputs to continue clocking at the same instant with the preset

conditions applied. This allows for the alignment of the edges of

two or more outputs or for the spacing of edges according to the

coarse phase offset settings for two or more outputs.

Table 46. Setting Analog Fine Delays

OUTPUT

(LVDS/CMOS) Capacitors Current

Ramp

Delay

Fraction

Delay

Bypass

OUT6

OUT7

OUT8

OUT9

0xA1<5:3> 0xA1<2:0> 0xA2<5:0> 0xA0<0>

0xA4<5:3> 0xA4<2:0> 0xA5<5:0> 0xA3<0>

0xA7<5:3> 0xA7<2:0> 0xA8<5:0> 0xA6<0>

0xAA<5:3> 0xAA<2:0> 0xAB<5:0> 0xA9<0>

Rev. 0 | Page 47 of 84

AD9516-3

Synchronization of the outputs is executed in several ways:

The most common way to execute the SYNC function is to use

SYNC

the

pin to do a manual synchronization of the outputs.

SYNC

• The

pin is forced low and then released (manual sync).

This requires a low-going signal on the

pin, which is held

• By setting and then resetting any one of the following three

bits: the soft sync bit (0x230<0>), the soft reset bit (0x00<5>

[mirrored]), and the distribution power-down bit (0x230<1>).

low and then released when synchronization is desired. The

timing of the SYNC operation is shown in Figure 55 (using

VCO divider) and Figure 56 (VCO divider not used). There is

an uncertainty of up to 1 cycle of the clock at the input to the

channel divider due to the asynchronous nature of the SYNC

signal with respect to the clock edges inside the AD9516. The

• Synchronization of the outputs can be executed as part of the

chip power-up sequence.

RESET

• The

pin is forced low and then released (chip reset).

SYNC

delay from the

rising edge to the beginning of synchronized

PD

pin is forced low and then released (chip power-down).

output clocking is between 14 and 15 cycles of clock at the

channel divider input, plus either one cycle of the VCO divider

input (see Figure 55), or one cycle of the channel divider input

(see Figure 56), depending on whether the VCO divider is used.

Cycles are counted from the rising edge of the signal.

• Whenever a VCO calibration is completed, an internal SYNC

signal is automatically asserted at the beginning and released

upon the completion of a VCO calibration.

Another common way to execute the SYNC function is by

setting and resetting the soft SYNC bit at 0x230<0> (see Table

52 through Table 61 for details). Both setting and resetting of

the soft SYNC bit require an update all registers (0x232<0> = 1)

operation to take effect.

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER OUTPUT STATIC

INPUT TO VCO DIVIDER

1

11

13

14

1

2

3

4

5

6

7

9

10

12

INPUT TO CHANNEL DIVIDER

8

SYNC PIN

OUTPUT OF

CHANNEL DIVIDER

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

Figure 55. SYNC Timing when VCO Divider Is Used—CLK or VCO Is Input

Rev. 0 | Page 48 of 84

AD9516-3

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER OUTPUT STATIC

INPUT TO CLK

1

11

13

14

INPUT TO CHANNEL DIVIDER

1

2

3

4

5

6

7

9

10

12

8

SYNC PIN

OUTPUT OF

CHANNEL DIVIDER

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

Figure 56. SYNC Timing when VCO Divider Is Not Used—CLK Input Only

A SYNC operation brings all outputs that have not been

excluded (by the nosync bit) to a preset condition before

allowing the outputs to begin clocking in synchronicity. The

preset condition takes into account the settings in each of the

channel’s start high bit and its phase offset. These settings

govern both the static state of each output when the SYNC

operation is happening and the state and relative phase of the

outputs when they begin clocking again upon completion of the

SYNC operation. Between outputs and after synchronization,

this allows for the setting of phase offsets.

LVPECL Outputs: OUT0 to OUT5

The LVPECL differential voltage (V_OD) is selectable (from

~400 mV to 960 mV, see 0xF0:5<3:2>. The LVPECL outputs

have dedicated pins for power supply (VS_LVPECL), allowing

a separate power supply to be used. V_{S_LVPECL}can be from

2.5 V to 3.3 V.

The LVPECL output polarity can be set as noninverting or

inverting, which allows for the adjustment of the relative

polarity of outputs within an application without requiring a

board layout change. Each LVPECL output can be powered

down or powered up as needed. Because of the architecture of

the LVPECL output stages, there is the possibility of electrical

overstress and breakdown under certain power-down conditions.

For this reason, the LVPECL outputs have several power-down

modes. This includes a safe power-down mode that continues

to protect the output devices while powered down, although it

consumes somewhat more power than a total power-down. If

the LVPECL output pins are terminated, it is best to select the

safe power-down mode. If the pins are not connected (unused),

it is acceptable to use the total power-down mode.

The AD9516 outputs are in pairs, sharing a channel divider per

pair (two pairs of pairs, four outputs, in the case of CMOS). The

synchronization conditions apply to both outputs of a pair.

Each channel (a divider and its outputs) can be excluded from

any SYNC operation by setting the nosync bit of the channel.

Channels that are set to ignore SYNC (excluded channels) do

not set their outputs static during a SYNC operation, and their

outputs are not synchronized with those of the nonexcluded

channels.

Clock Outputs

3.3V

The AD9516 offers three output level choices: LVPECL, LVDS,

and CMOS. OUT0 to OUT5 are LVPECL differential outputs;

and OUT6 to OUT9 are LVDS/CMOS outputs. These outputs

can be configured as either LVDS differential or as pairs of

single-ended CMOS outputs.

OUT

GND

Figure 57. LVPECL Output Simplified Equivalent Circuit

Rev. 0 | Page 49 of 84

AD9516-3

LVDS/CMOS Outputs: OUT6 to OUT9

Power-On Reset—Start-Up Conditions When V_SIs

Applied

OUT6 to OUT9 can be configured as either an LVDS

differential output or as a pair of CMOS single-ended outputs.

The LVDS outputs allow for selectable output current from

~1.75 mA to ~7 mA.

A power-on reset (POR) is issued when the V_Spower supply is

turned on. This initializes the chip to the power-on conditions

that are determined by the default register settings. These are

indicated in the Default Value (Hex) column of Table 51. At

power-on, the AD9516 also executes a SYNC operation, which

brings the outputs into phase alignment according to the default

settings.

The LVDS output polarity can be set as noninverting or

inverting, which allows for the adjustment of the relative

polarity of outputs within an application without requiring a

board layout change. Each LVDS output can be powered down

if not needed to save power.

RESET

Asynchronous Reset via the

An asynchronous hard reset is executed by momentarily pulling

RESET

3.5mA

low. A reset restores the chip registers to the default

settings.

Soft Reset via 0x00<5>

OUT

A soft reset is executed by writing 0x00<5> and 0x00<2> = 1b.

This bit is not self-clearing; therefore, it must be cleared by

writing 0x00<5> and 0x00<2> = 0b to reset it and complete the

soft reset operation. A soft reset restores the default values to

the internal registers. The soft reset bit does not require an

update registers command (0x232) to be issued.

3.5mA

Figure 58. LVDS Output Simplified Equivalent Circuit with

3.5 mA Typical Current Source

POWER-DOWN MODES

OUT6 to OUT9 can also be CMOS outputs. Each LVDS output

can be configured to be two CMOS outputs. This provides for

up to eight CMOS outputs: OUT6A, OUT6B, OUT7A, OUT7B,

OUT8A, OUT8B, OUT9A, and OUT9B. When an output is

configured as CMOS, the CMOS Output A is automatically

turned on. The CMOS Output B can be turned on or off

independently. The relative polarity of the CMOS outputs can also

be selected for any combination of inverting and noninverting. See

Table 56, 0x140<7:5>, 0x141<7:5>, 0x142<7:5>, and 0x143<7:5>.

PD

Chip Power-Down via

The AD9516 can be put into a power-down condition by

PD

pulling the

functions and currents inside the AD9516. The chip remains in

PD

pin low. Power-down turns off most of the

this power-down state until

is brought back to Logic High.

When woken up, the AD9516 returns to the settings

programmed into its registers prior to the power-down, unless

the registers are changed by new programming while the

pin is held low.

PD

Each LVDS/CMOS output can be powered-down as needed to

save power. The CMOS output power-down is controlled by the

same bit that controls the LVDS power-down for that output.

This power-down control affects both the CMOS A and

CMOS B outputs. However, when the CMOS A output is powered

up, the CMOS B output can be powered on or off separately.

PD

The

power-down shuts down the currents on the chip,

except the bias current necessary to maintain the LVPECL

outputs in a safe shutdown mode. This is needed to protect the

LVPECL output circuitry from damage that could be caused by

certain termination and load configurations when tristated.

Because this is not a complete power-down, it can be called

sleep mode.

V

S

PD

When the AD9516 is in a

following state:

power-down, the chip is in the

OUT1/

OUT1

•

The PLL is off (asynchronous power-down).

The VCO is off.

Figure 59. CMOS Equivalent Output Circuit

The CLK input buffer is off.

All dividers are off.

RESET MODES

The AD9516 has several ways to force the chip into a reset

condition that restores all registers to their default values and

makes these settings active.

All LVDS/CMOS outputs are off.

All LVPECL outputs are in safe off mode.

The serial control port is active, and the chip responds to

commands.

Rev. 0 | Page 50 of 84

AD9516-3

If the AD9516 clock outputs must be synchronized to each

other, a SYNC is required upon exiting power-down (see the

Synchronizing the Outputs—SYNC Function section). A VCO

calibration is not required when exiting power-down.

Individual Clock Output Power-Down

Any of the clock distribution outputs may be powered down

individually by writing to the appropriate registers. The register

map details the individual power-down settings for each output.

The LVDS/CMOS outputs may be powered down, regardless of

their output load configuration.

PLL Power-Down

The PLL section of the AD9516 can be selectively powered

down. There are three PLL operating modes set by 0x10<1:0>,

as shown in Table 53.

The LVPECL outputs have multiple power-down modes

(see Table 52), which give some flexibility in dealing with the

various output termination conditions. When the mode is set to

10b, the LVPECL output is protected from reverse bias to

2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is

not protected from reverse bias and can be damaged under

certain termination conditions. This setting also affects the

operation when the distribution block is powered down with

0x230<1> = 1b (see the Distribution Power-Down section).

In asynchronous power-down mode, the device powers down as

soon as the registers are updated.

In synchronous power-down mode, the PLL power-down is

gated by the charge pump to prevent unwanted frequency

jumps. The device goes into power-down on the occurrence of

the next charge pump event after the registers are updated.

Distribution Power-Down

Individual Circuit Block Power-Down

The distribution section can be powered down by writing

0x230<1> = 1b. This turns off the bias to the distribution

section. If the LVPECL power-down mode is normal operation

(00b), it is possible for a low impedance load on that LVPECL

output to draw significant current during this power-down. If

the LVPECL power-down mode is set to 11b, the LVPECL

output is not protected from reverse bias and can be damaged

under certain termination conditions.

Other AD9516 circuit blocks (such as CLK, REF1, and REF2)

can be powered down individually. This gives flexibility in

configuring the part for power savings whenever certain chip

functions are not needed.

Rev. 0 | Page 51 of 84

AD9516-3

SERIAL CONTROL PORT

The AD9516 serial control port is a flexible, synchronous, serial

communications port that allows an easy interface with many

industry-standard microcontrollers and microprocessors. The

AD9516 serial control port is compatible with most synchronous

transfer formats, including both the Motorola SPI® and Intel®

SSR® protocols. The serial control port allows read/write access

to all registers that configure the AD9516. Single or multiple

byte transfers are supported, as well as MSB first or LSB first

transfer formats. The AD9516 serial control port can be

configured for a single bidirectional I/O pin (SDIO only) or

for two unidirectional I/O pins (SDIO/SDO). By default, the

AD9516 is in bidirectional mode, long instruction (long

instruction is the only instruction mode supported).

During this period, the serial control port state machine enters

a wait state until all data is sent. If the system controller decides

to abort the transfer before all of the data is sent, the state machine

must be reset by either completing the remaining transfers or by

returning the

low for at least one complete SCLK cycle (but

CS

less than eight SCLK cycles). Raising the

on a nonbyte

CS

boundary terminates the serial transfer and flushes the buffer.

In the streaming mode (see Table 47), any number of data bytes

can be transferred in a continuous stream. The register address

is automatically incremented or decremented (see the MSB/LSB

First Transfers section).

must be raised at the end of the last

CS

byte to be transferred, thereby ending the stream mode.

Communication Cycle—Instruction Plus Data

SERIAL CONTROL PORT PIN DESCRIPTIONS

There are two parts to a communication cycle with the AD9516.

The first writes a 16-bit instruction word into the AD9516,

coincident with the first 16 SCLK rising edges. The instruction

word provides the AD9516 serial control port with information

regarding the data transfer, which is the second part of the

communication cycle. The instruction word defines whether

the upcoming data transfer is a read or a write, the number of

bytes in the data transfer, and the starting register address for

the first byte of the data transfer.

SCLK (serial clock) is the serial shift clock. This pin is an input.

SCLK is used to synchronize serial control port reads and

writes. Write data bits are registered on the rising edge of this

clock, and read data bits are registered on the falling edge. This

pin is internally pulled down by a 30 kΩ resistor to ground.

SDIO (serial data input/output) is a dual-purpose pin and acts

as either an input only (unidirectional mode) or as both an

input/output (bidirectional mode). The AD9516 defaults to the

bidirectional I/O mode (0x00<7> = 0).

Write

SDO (serial data out) is used only in the unidirectional I/O

mode (0x00<7>) as a separate output pin for reading back data.

If the instruction word is for a write operation, the second part

is the transfer of data into the serial control port buffer of the

AD9516. Data bits are registered on the rising edge of SCLK.

(chip select bar) is an active low control that gates the read

CS

and write cycles. When

is high, SDO and SDIO are in a high

CS

The length of the transfer (1, 2, 3 bytes or streaming mode) is

indicated by two bits (W1:W0) in the instruction byte. When

impedance state. This pin is internally pulled up by a 30 kΩ

resistor to VS.

the transfer is 1, 2, or 3 bytes, but not streaming,

can be

CS

raised after each sequence of eight bits to stall the bus (except

after the last byte, where it ends the cycle). When the bus is

16

SCLK

AD9516-3

SERIAL

CONTROL

PORT

17

CS

21

stalled, the serial transfer resumes when

is lowered. Raising

CS

SDO

22

SDIO

on a nonbyte boundary resets the serial control port. During a

write, streaming mode does not skip over reserved or blank

registers; therefore, the user must know what bit pattern to

write to the reserved registers to preserve proper operation of

the part. It does not matter what data is written to blank registers.

Figure 60. Serial Control Port

GENERAL OPERATION OF SERIAL CONTROL PORT

A write or a read operation to the AD9516 is initiated by pulling

low.

CS

Because data is written into a serial control port buffer area, not

directly into the actual control registers of the AD9516, an

additional operation is needed to transfer the serial control port

buffer contents to the actual control registers of the AD9516,

thereby causing them to become active. The update registers

operation consists of setting 0x232<0> = 1b (this bit is self-

clearing). Any number of bytes of data can be changed before

executing an update registers. The update registers simultaneously

actuates all register changes that have been written to the buffer

since any previous update.

stall high is supported in modes where three or fewer bytes

CS

of data (plus instruction data) are transferred (see Table 47). In

these modes, can temporarily return high on any byte

CS

boundary, allowing time for the system controller to process the

next byte. can go high on byte boundaries only and can go

CS

high during either part (instruction or data) of the transfer.

Rev. 0 | Page 52 of 84

AD9516-3

Read

A12:A0: These 13 bits select the address within the register map

that is written to or read from during the data transfer portion

of the communications cycle. Only Bits<A9:A0> are needed to

cover the range of the 0x232 registers used by the AD9516.

Bits<A12:A10> must always be 0b. For multibyte transfers, this

address is the starting byte address. In MSB first mode,

subsequent bytes increment the address.

If the instruction word is for a read operation, the next N × 8

SCLK cycles clock out the data from the address specified in the

instruction word, where N is 1 to 3 as determined by W1:W0.

If N = 4, the read operation is in streaming mode, continuing

until

is raised. Streaming mode does not skip over reserved

CS

or blank registers. The readback data is valid on the falling

edge of SCLK.

MSB/LSB FIRST TRANSFERS

The AD9516 instruction word and byte data can be MSB first

or LSB first. Any data written to 0x00 must be mirrored, the

upper four bits (<7:4>) must mirror the lower four bits (<3:0>).

This makes it irrelevant whether LSB first or MSB first is in

effect. As an example of this mirroring, see the default setting

for this register: 0x00, which mirrors Bit 4 and Bit 3. This sets

the long instruction mode (default, and is the only mode

supported).

The default mode of the AD9516 serial control port is the

bidirectional mode. In bidirectional mode, both the sent data

and the readback data appear on the SDIO pin. It is also possible to

set the AD9516 to unidirectional mode (SDO enable register,

0x00<7>). In unidirectional mode, the readback data appears

on the SDO pin.

A readback request reads the data that is in the serial control

port buffer area, or the data in the active registers (see Figure 61).

Readback of the buffer or active registers is controlled by 0x04<0>.

The default for the AD9516 is MSB first.

The AD9516 supports only the long instruction mode;

therefore, 0x00<4:3> must be set to 11b (this register uses

mirrored bits). Long instruction mode is the default at power-

up or reset.

When LSB first is set by 0x00<2> and 0x00<6>, it takes effect

immediately, because it only affects the operation of the serial

control port and does not require that an update be executed.

When MSB first mode is active, the instruction and data bytes

must be written from MSB to LSB. Multibyte data transfers in

MSB first format start with an instruction byte that includes the

register address of the most significant data byte. Subsequent

data bytes must follow in order from the high address to the low

address. In MSB first mode, the serial control port internal

address generator decrements for each data byte of the

multibyte transfer cycle.

The AD9516 uses Register Address 0x000 to Register

Address 0x232.

SCLK

SDIO

SDO

UPDATE

REGISTERS

CS

SERIAL

CONTROL

PORT

When LSB first is active, the instruction and data bytes must be

written from LSB to MSB. Multibyte data transfers in LSB first

format start with an instruction byte that includes the register

address of the least significant data byte followed by multiple

data bytes. The internal byte address generator of the serial

control port increments for each byte of the multibyte

transfer cycle.

WRITE REGISTER 0x232 = 0x01

TO UDATE REGISTERS

Figure 61. Relationship Between Serial Control Port Buffer Registers and

Active Registers of the AD9516

THE INSTRUCTION WORD (16 BITS)

W

The MSB of the instruction word is R/ , which indicates

The AD9516 serial control port register address decrements

from the register address just written toward 0x00 for multibyte

I/O operations if the MSB first mode is active (default). If the

LSB first mode is active, the register address of the serial control

port increments from the address just written toward 0x232 for

multibyte I/O operations.

whether the instruction is a read or a write. The next two bits,

W1:W0, indicate the length of the transfer in bytes. The final

13 bits are the address (A12:A0) at which to begin the read or

write operation.

For a write, the instruction word is followed by the number of

bytes of data indicated by Bits W1:W0, see Table 47.

Streaming mode always terminates when it hits Address 0x232.

Note that unused addresses are not skipped during multibyte

I/O operations.

Table 47. Byte Transfer Count

W1

W0

Bytes to Transfer

0

1

Table 48. Streaming Mode (No Addresses Are Skipped)

0

1

2

Write Mode Address Direction Stop Sequence

1

0

3

LSB first

MSB first

Increment

Decrement

0x230, 0x231, 0x232, stop

0x001, 0x000, 0x232, stop

1

Streaming mode

Rev. 0 | Page 53 of 84

AD9516-3

Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First

MSB

LSB

I0

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1

R/W

W1

W0

A12 = 0

A11 = 0

A10 = 0

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

CS

SCLK DON'T CARE

DON'T CARE

SDIO

R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA

Figure 62. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data

CS

SCLK

DON'T CARE

R/W W1 W0 A12 A11A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DON'T CARE

SDIO

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDO DON'T CARE

16-BIT INSTRUCTION HEADER

REGISTER (N) DATA

REGISTER (N – 1) DATA

REGISTER (N – 2) DATA

REGISTER (N – 3) DATA

DON'T

CARE

Figure 63. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data

t_DS

t_HI

t_S

t_C

t_CLK

t_DH

t_LO

CS

DON'T CARE

SCLK

SDIO

R/W

W1

W0

A12

A11

A10

A9

A8

A7

A6

A5

D4

D3

D2

D1

D0

DON'T CARE

Figure 64. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements

CS

SCLK

t_DV

SDIO

SDO

DATA BIT N

DATA BIT N – 1

Figure 65. Timing Diagram for Serial Control Port Register Read

CS

SCLK DON'T CARE

DON'T CARE

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA

SDIO

Figure 66. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data

Rev. 0 | Page 54 of 84

AD9516-3

t_S

t_C

CS

t_CLK

t_HI

t_LO

t_DS

SCLK

SDIO

t_DH

BIT N

BIT N + 1

Figure 67. Serial Control Port Timing—Write

Table 50. Serial Control Port Timing

Parameter

Description

t_DS

t_DH

t_CLK

t_S

Setup time between data and rising edge of SCLK

Hold time between data and rising edge of SCLK

Period of the clock

Setup time between CS falling edge and SCLK rising edge (start of communication cycle)

Setup time between SCLK rising edge and CS rising edge (end of communication cycle)

Minimum period that SCLK should be in a Logic High state

t_C

t_HI

t_LO

t_DV

Minimum period that SCLK should be in a Logic Low state

SCLK to valid SDIO and SDO (see Figure 65)

Rev. 0 | Page 55 of 84

AD9516-3

REGISTER MAP OVERVIEW

Table 51. Register Map Overview

Default

Value

(Hex)

Addr

(Hex)

Bit 7

(MSB)

Parameter

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Serial Port Configuration

00

Serial Port

SDO

LSB First

Soft Reset

Long

Soft Reset

LSB First

SDO Active

18

Configuration Active

Instruction

01

Blank

Reserved

02 to

03

04

Read Back

Control

Blank

Read Back

Active

00

Registers

PLL

10

PFD and

PFD

Charge Pump Current

Charge Pump Mode

PLL Power-Down

7D

Charge Pump

Polarity

11

12

13

14

15

16

R Counter

14-Bit R Divider Bits<7:0> (LSB)

01

00

03

00

06

Blank

14-Bit R Divider Bits<13:8> (MSB)

6-Bit A Counter

A Counter

B Counter

13-Bit B Counter Bits<7:0> (LSB)

13-Bit B Counter Bits<12:8> (MSB)

B Counter Prescaler P

Blank

Reset R

Counter

PLL Control 1

Set CP Pin

to VCP/2

Reset A and

B Counters

Reset All

Counters

Bypass

17

18

PLL Control 2

PLL Control 3

STATUS Pin Control

Antibacklash Pulse Width

00

06

Reserved

Lock Detect Counter

Digital Lock

Detect

Disable

Digital Lock

Detect

VCO Calibration Divider

VCO Cal

Now

Window

19

1A

PLL Control 4

PLL Control 5

SYNC

R Path Delay

N Path Delay

00

R, A, B Counters

Pin Reset

Reserved

Reference

Frequency

Monitor

LD Pin Control

Threshold

1B

PLL Control 6

VCO

Frequency

Monitor

REF2

REF1 (REFIN)

Frequency

Monitor

REFMON Pin Control

00

REFIN

(

)

Frequency

Monitor

1C

1D

PLL Control 7

PLL Control 8

Disable

Switchover REF2

Deglitch

Select

Use

REF_SEL Pin

Automatic

Reference

Switchover

Stay on

REF2

Power On

REF1

Power On

Differential

Reference

00

Reserved

PLL Status

Register

Disable

LD Pin

Comparator

Enable

Holdover

Enable

External

Holdover

Control

Holdover

Enable

1E

1F

PLL Control 9

PLL Readback

00

--

Reserved

VCO Cal

Finished

Holdover

Active

REF2

Selected

VCO

Frequency

>Threshold

REF2

Frequency

> Threshold > Threshold

REF1

Frequency

Digital

Lock

Detect

20 to

4F

Blank

Rev. 0 | Page 56 of 84

AD9516-3

Default

Value

(Hex)

Addr

(Hex)

Bit 7

(MSB)

Parameter

Bit 6

Bit 5

Bit 4

Blank

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Fine Delay Adjust: OUT6 to OUT9

A0

A1

A2

A3

A4

A5

A6

OUT6 Delay

Bypass

OUT6 Delay

Bypass

01

00

01

00

01

OUT6 Delay

Full-Scale

Blank

OUT6 Ramp Capacitors

OUT6 Ramp Current

OUT6 Delay

Fraction

Blank

OUT6 Delay Fraction

OUT7 Delay Fraction

OUT7 Delay

Bypass

Blank

OUT7 Delay

Bypass

OUT7 Ramp Current

OUT7 Delay

Full-Scale

Blank

OUT7 Ramp Capacitors

OUT7 Delay

Fraction

OUT8 Delay

Bypass

Blank

OUT8 Delay

Bypass

A7

OUT8 Delay

Full-Scale

Blank

OUT8 Ramp Capacitors

OUT8 Ramp Current

00

A8

A9

OUT8 Delay

Fraction

OUT8 Delay Fraction

OUT9 Delay Fraction

00

01

OUT9 Delay

Bypass

Blank

OUT9 Delay

Bypass

AA

AB

OUT9 Delay

Full-Scale

Blank

OUT9 Ramp Capacitors

OUT9 Ramp Current

00

OUT9 Delay

Fraction

AC to

EF

Blank

LVPECL Outputs

F0

OUT0

Blank

OUT0

Invert

OUT0 LVPECL

Differential Voltage

OUT0 Power-Down

08

A

F1

OUT1

Invert

OUT1 LVPECL

Differential Voltage

OUT1 Power-Down

F2

F3

F4

F5

OUT2

OUT3

OUT4

OUT5

Blank

OUT2

Invert

OUT2 LVPECL

Differential Voltage

OUT2 Power-Down

OUT3 Power-Down

OUT4 Power-Down

OUT5 Power-Down

08

0A

08

0A

OUT3

Invert

OUT3 LVPECL

Differential Voltage

OUT4

Invert

OUT4 LVPECL

Differential Voltage

OUT5

Invert

OUT5 LVPECL

Differential Voltage

F6 to

13F

Blank

LVDS/CMOS Outputs

140

141

142

143

OUT6

OUT7

OUT8

OUT9

OUT6 CMOS Output

Polarity

OUT6 LVDS/ OUT6

OUT6 Select

LVDS/CMOS

OUT6 LVDS Output

OUT6

Power-Down

42

43

42

43

CMOS

CMOS B

Current

Output

Polarity

OUT7 CMOS Output

Polarity

OUT7 LVDS/ OUT7

OUT7 Select

LVDS/CMOS

OUT7 LVDS Output

Current

OUT7

Power-Down

CMOS

CMOS B

Output

Polarity

OUT8 CMOS Output

Polarity

OUT8 LVDS/ OUT8

OUT8 Select

LVDS/CMOS

OUT8 LVDS Output

Current

OUT8

Power-Down

CMOS

CMOS B

Output

Polarity

OUT9 CMOS Output

Polarity

OUT9 LVDS/ OUT9

OUT9 Select

LVDS/CMOS

OUT9 LVDS Output

Current

OUT9

Power-Down

CMOS

CMOS B

Output

Polarity

Rev. 0 | Page 57 of 84

AD9516-3

Default

Value

(Hex)

Addr

(Hex)

Bit 7

(MSB)

Parameter

Bit 6

Bit 5

Bit 4

Bit 3

Blank

Bit 2

Bit 1

Bit 0 (LSB)

144 to

18F

LVPECL Channel Dividers

190

191

192

Divider 0

(PECL)

Divider 0 Low Cycles

Divider 0 High Cycles

Divider 0 Phase Offset

00

80

00

Divider 0

Bypass

Divider 0

Nosync

Divider 0

Force High

Divider 0

Start High

Blank

Reserved

Divider 0

Direct to

Output

Divider 0

DCCOFF

193

194

195

Divider 1

(PECL)

Divider 1 Low Cycles

Divider 1 High Cycles

BB

00

Divider 1

Bypass

Divider 1

Nosync

Blank

Divider 1

Force High

Divider 1

Start High

Reserved

Divider 1 Phase Offset

Divider 1

Direct to

Output

Divider 1

DCCOFF

196

197

198

Divider 2

(PECL)

Divider 2 Low Cycles

Divider 2 High Cycles

00

Divider 2

Bypass

Divider 2

Nosync

Blank

Divider 2

Force High

Divider 2

Start High

Divider 2 Phase Offset

Reserved

Divider 2

Direct to

Output

Divider 2

DCCOFF

LVDS/CMOS Channel Dividers

199

Divider 3

(LVDS/CMOS)

Low Cycles Divider 3.1

High Cycles Divider 3.1

22

19A

19B

Phase Offset Divider 3.2

Low Cycles Divider 3.2

Phase Offset Divider 3.1

High Cycles Divider 3.2

00

11

19C

19D

19E

Reserved

Bypass

Divider 3.2

Bypass

Divider 3.1

Divider 3

Nosync

Divider 3

Force High

Start High

Divider 3.2

Start High

Divider 3.1

00

22

Blank

Reserved

Divider 3

DCCOFF

Divider 4

Low Cycles Divider 4.1

High Cycles Divider 4.1

(LVDS/CMOS)

19F

1A0

1A1

Phase Offset Divider 4.2

Low Cycles Divider 4.2

Phase Offset Divider 4.1

High Cycles Divider 4.2

00

11

00

Reserved

Bypass

Divider 4.2

Bypass

Divider 4.1

Divider 4

Nosync

Divider 4

Start High

Divider 4.2

Start High

Divider 4.1

Force High

1A2

1A3

Blank

Reserved

Divider 4

DCCOFF

00

Reserved

Blank

1A4

to

1DF

VCO Divider and CLK Input

1E0

VCO Divider

Blank

Reserved

VCO Divider

02

00

1E1

Input CLKs

Reserved

Power-

Down

Clock

Power-Down

VCO Clock

Interface

Power-

Down VCO

and CLK

Select

VCO or CLK

Bypass

VCO

Divider

Input

Section

1E2

to

Blank

22A

Rev. 0 | Page 58 of 84

AD9516-3

Default

Value

(Hex)

Addr

(Hex)

Bit 7

(MSB)

Parameter

Bit 6

Bit 5

Reserved

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

System

230

Power Down

and Sync

Power-

Soft Sync

00

Down Sync Down

Distribution

Reference

Reserved

231

Blank

00

Update All Registers

232

Update All

Registers

Blank

Update All

Registers

(Self-

Clearing

Bit)

Rev. 0 | Page 59 of 84

AD9516-3

REGISTER MAP DESCRIPTIONS

Table 52 through Table 61 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal

address. Reference to a specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, and

<5:2> refers to the range of bits from Bit 5 through Bit 2.

Table 52. Serial Port Configuration

Reg. Addr (Hex) Bit(s) Name

Description

00

<7>

SDO Active

Selects unidirectional or bidirectional data transfer mode.

<7> = 0; SDIO pin used for write and read; SDO set high impedance; bidirectional mode.

<7> = 1; SDO used for read; SDIO used for write; unidirectional mode.

MSB or LSB data orientation.

00

<6>

LSB First

<6> = 0; data-oriented MSB first; addressing decrements.

<6> = 1; data-oriented LSB first; addressing increments.

Soft Reset

<5> = 1 (not self-clearing). Soft reset; restores default values to internal registers.

Not self-clearing. Must be cleared to 0b to complete reset operation.

00

<5>

<4>

Soft Reset

Long Instruction

Short/long instruction mode (this part uses long instruction mode only, so this bit

should always be =1).

<4> = 0; 8-bit instruction (short).

<4> = 1; 16-bit instruction (long).

00

04

<3:0> Mirror <7:4>

Bits<3:0> should always mirror <7:4> so that it does not matter whether the part

is in MSB or LSB first mode (see Register 0x00 <6>). User should set bits as follows:

<0> = <7>.

<1> = <6>.

<2> = <5>.

<3> = <4>.

<0>

Read Back Active Registers Select register bank used for a readback.

<0> = 0; read back buffer registers.

<0> = 1; read back active registers.

Rev. 0 | Page 60 of 84

AD9516-3

Table 53. PLL

Reg.

Addr

(Hex) Bit(s) Name

Description

10

<7> PFD Polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only.

The on-chip VCO requires positive polarity <7> = 0.

<7> = 0; positive (higher control voltage produces higher frequency).

<7> = 1; negative (higher control voltage produces lower frequency).

<6:4> CP Current Charge pump current (with CPRSET = 5.1 kΩ).

10

<6> <5>

<4>

0

1

0

1

0

1

0

1

I_CP(mA)

0.6

1.2

1.8

2.4

3.0

3.6

4.2

4.8

0

1

0

1

0

1

10

<3:2> CP Mode

Charge pump operating mode.

<3> <2>

Charge Pump Mode

0

1

0

1

0

1

High impedance state.

Force source current (pump up).

Force sink current (pump down).

Normal operation.

<1:0> PLL Power- PLL operating mode.

Down

<1>

0

1

<0> Mode

0

1

0

1

Normal operation.

Asynchronous power-down.

Normal operation.

Synchronous power-down.

11

12

<7:0> 14-Bit

R divider LSBs—lower eight bits.

R Divider

Bits<7:0>

(LSB)

<5:0> 14-Bit

R divider MSBs—upper six bits.

R Divider

Bits<13:8>

(MSB)

13

14

<5:0> 6-Bit

A Counter

<7:0> 13-Bit

A counter (part of N divider).

B counter (part of N divider)—lower eight bits.

B Counter

Bits<7:0>

(LSB)

15

<4:0> 13-Bit

B counter (part of N divider)—upper five bits.

B Counter

Bits<12:8>

(MSB)

16

<7> Set CP Pin

to VCP/2

Set the CP pin to one-half of the VCP supply voltage.

<7> = 0; CP normal operation.

<7> = 1; CP pin set to VCP/2.

Reset R counter (R divider).

<6> Reset R

Counter

<6> = 0; normal.

<6> = 1; reset R counter.

Rev. 0 | Page 61 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

16

<5> Reset A and B Reset A and B counters (part of N divider).

Counters

<5> = 0; normal.

<5> = 1; reset A and B counters.

Reset R, A, and B counters.

<4> = 0; normal.

<4> Reset All

Counters

<4> = 1; reset R, A, and B counters.

B counter bypass. This is valid only when operating the prescaler in FD mode.

<3> = 0; normal.

<3> B Counter

Bypass

<3> = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for

the N divider.

16

<2:0> Prescaler P Prescaler: DM = dual modulus and FD = fixed divide.

<2>

0

1

<1> <0> Mode

Prescaler

Divide-by-1.

Divide-by-2.

0

1

0

1

0

1

0

1

0

1

0

1

FD

DM

FD

Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0.

Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0.

Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0.

Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0.

Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0.

Divide-by-3.

17

<7:2> STATUS

Pin Control

Select the signal that is connected to the STATUS pin

Level or

Dynamic

<2> Signal

<7>

0

<6> <5> <4> <3>

Signal at STATUS Pin

Ground (dc).

N divider output (after the delay).

R divider output (after the delay).

A divider output.

Prescaler output.

PFD up pulse.

PFD down pulse.

Ground (dc); for all other cases of 0XXXXX not specified above.

The selections that follow are the same as REFMON.

Ground (dc).

REF1 clock (differential reference when in differential mode).

REF2 clock (N/A in differential mode).

0

X

0

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

X

LVL

DYN

LVL

1

0

1

0

1

0

1

LVL

DYN

Selected reference to PLL (differential reference when in

differential mode).

1

0

1

0

1

0

1

0

DYN

LVL

Unselected reference to PLL (not available in differential

mode).

Status of selected reference (status of differential reference);

active high.

Status of unselected reference (not available in differential

mode); active high.

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

LVL

Status REF1 frequency (active high).

Status REF2 frequency (active high).

(Status REF1 frequency) AND (status REF2 frequency).

(DLD) AND (status of selected reference) AND (status of VCO).

Status of VCO frequency (active high).

Selected reference (low = REF1, high = REF2).

Digital lock detect (DLD); active high.

Holdover active (active high).

Rev. 0 | Page 62 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

Level or

Dynamic

<7>

1

<6> <5> <4> <3>

<2> Signal

Signal at STATUS Pin

LD pin comparator output (active high).

VS (PLL supply).

0

1

0

1

0

1

0

1

0

1

0

1

LVL

DYN

1

REF1 clock

REF2 clock

(differential reference when in differential mode).

(not available in differential mode).

1

Selected reference to PLL

differential mode).

(differential reference when in

1

0

1

0

1

0

1

0

DYN

LVL

Unselected reference to PLL

differential mode).

Status of selected reference (status of differential reference);

active low.

Status of unselected reference (not available in differential

mode); active low.

(not available when in

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LVL

Status of REF1 frequency (active low).

Status of REF2 frequency (active low).

(Status of REF1 frequency) AND (Status of REF2 frequency)

.

(DLD) AND (Status of selected reference) AND (Status of VCO)

.

Status of VCO Frequency (active low).

Selected reference (low = REF2, high = REF1).

Digital lock detect (DLD) (active low).

Holdover active (active low).

LD pin comparator output (active low).

17

18

<1:0> Antibacklash <1>

<0> Antibacklash Pulse Width (ns)

Pulse Width

0

1

0

1

0

1

2.9

1.3

6.0

2.9

<6:5> Lock Detect Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates

Counter a locked condition.

<6>

0

1

<5> PFD Cycles to Determine Lock

0

1

0

1

5

16

64

255

18

<4> Digital Lock If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time, the

Detect

digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.

Window

<4> = 0; high range.

<4> = 1; low range.

18

<3> Disable

Digital

Digital lock detect operation.

<3> = 0; normal lock detect operation.

Lock Detect <3> = 1; disable lock detect.

<2:1> VCO Cal

Divider

VCO Calibration Divider. Divider used to generate the VCO calibration clock from the PLL reference clock.

<2>

0

1

<1> VCO Calibration Clock Divider

0

1

0

1

2

4

8

16 (default)

18

<0> VCO Cal Now Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. The sequence

to initiate a calibration is: program to a 0, followed by an update bit (Register0x232 <0>); then programmed to

1, followed by another update bit (Register0x232 <0>). This sequence gives complete control over when the

VCO calibration occurs relative to the programming of other registers that can impact the calibration.

Rev. 0 | Page 63 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

19

<7:6> R, A, B

Counters

<7>

0

<6>

0

Action

SYNC

Do nothing on

(default).

SYNC

Reset

0

1

Asynchronous reset.

Synchronous reset.

1

0

1

SYNC

Do nothing on .

19

1A

<5:3> R Path Delay <5:3> R Path Delay (see Table 2).

<2:0> N Path Delay <2:0> N Path Delay (see Table 2).

<6> Reference

Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect

Frequency the VCO frequency monitor’s detection threshold (see Table 16, REF1, REF2, and VCO Frequency Status Monitor).

Monitor

Threshold

<6> = 0; frequency valid if frequency is above the higher frequency threshold.

<6> = 1; frequency valid if frequency is above the lower frequency threshold.

Select the signal which is connected to the LD pin.

1A

<5:0> LD Pin

Control

Level or

Dynamic

<1> <0> Signal

<5> <4> <3> <2>

Signal at LD Pin

0

X

0

X

0

1

X

0

1

0

X

0

1

0

1

0

X

LVL

Digital lock detect (high = lock, low = unlock).

P-channel, open-drain lock detect (analog lock detect).

N-channel, open-drain lock detect (analog lock detect).

High-Z LD pin.

Current source lock detect (110 μA when DLD is true).

Ground (dc); for all other cases of 0XXXXX not specified above.

The selections that follow are the same as REFMON.

Ground (dc).

REF1 clock (differential reference when in differential mode).

REF2 clock (N/A in differential mode).

Selected reference to PLL (differential reference when in

differential mode).

DYN

HIZ

CUR

LVL

1

0

1

0

1

0

1

LVL

DYN

1

0

1

0

1

DYN

LVL

Unselected reference to PLL (not available in differential mode).

Status of selected reference (status of differential reference);

active high.

1

0

1

0

LVL

Status of unselected reference (not available in differential

mode); active high.

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LVL

DYN

Status REF1 frequency (active high).

Status REF2 frequency (active high).

(Status REF1 frequency) AND (status REF2 frequency).

(DLD) AND (status of selected reference) AND (status of VCO).

Status of VCO frequency (active high).

Selected reference (low = REF1, high = REF2).

Digital lock detect (DLD); active high.

Holdover active (active high).

N/A—do not use.

VS (PLL supply).

REF1 clock

REF2 clock

(differential reference when in differential mode).

(not available in differential mode).

Selected reference to PLL

differential mode).

(differential reference when in

1

0

1

0

1

DYN

LVL

Unselected reference to PLL

mode).

Status of selected reference (status of differential reference);

active low.

(not available when in differential

Rev. 0 | Page 64 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

Level or

Dynamic

<5> <4> <3> <2>

<1> <0> Signal

Signal at LD Pin

1

0

1

0

LVL

Status of unselected reference (not available in differential

mode); active low.

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LVL

Status of REF1 frequency (active low).

Status of REF2 frequency (active low).

(Status of REF1 frequency) AND (Status of REF2 frequency)

.

(DLD) AND (Status of selected reference) AND (Status of VCO)

Status of VCO frequency (active low).

Selected reference (low = REF2, high = REF1).

Digital lock detect (DLD); active low.

Holdover active (active low).

.

N/A—do not use.

1B

<7> VCO

Frequency <7> = 0; disable VCO frequency monitor.

Monitor <7> = 1; enable VCO frequency monitor.

Enable or disable VCO frequency monitor.

<6> REF2 (REFIN) Enable or disable REF2 frequency monitor.

Frequency <6> = 0; disable REF2 frequency monitor.

Monitor

<6> = 1; enable REF2 frequency monitor.

<5> REF1 (REFIN) REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs

Frequency (as selected by differential reference mode).

Monitor

<5> = 0; disable REF1 (REFIN) frequency monitor.

<5> = 1; enable REF1 (REFIN) frequency monitor.

1B

<4:0> REFMON Pin Select the signal that is connected to the REFMON pin.

Control

Level or

Dynamic

<4> <3> <2> <1> <0> Signal

Signal at REFMON Pin

0

1

0

1

0

1

LVL

Ground (dc).

DYN

REF1 clock (differential reference when in differential mode).

REF2 clock (N/A in differential mode).

Selected reference to PLL (differential reference when in differential

mode).

0

1

0

1

DYN

LVL

Unselected reference to PLL (not available in differential mode).

Status of selected reference (status of differential reference);

active high.

0

1

0

LVL

Status of unselected reference (not available in differential mode);

active high.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LVL

DYN

Status REF1 frequency (active high).

Status REF2 frequency (active high).

(Status REF1 frequency) AND (status REF2 frequency).

(DLD) AND (status of selected reference) AND (status of VCO).

Status of VCO frequency (active high).

Selected reference (low = REF1, high = REF2).

Digital lock detect (DLD); active low.

Holdover active (active high).

LD pin comparator output (active high).

VS (PLL supply).

REF1 clock

REF2 clock

(differential reference when in differential mode).

(not available in differential mode).

Selected reference to PLL

differential mode).

(differential reference when in

Rev. 0 | Page 65 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

Level or

Dynamic

<4> <3> <2> <1> <0> Signal

Signal at REFMON Pin

Unselected reference to PLL

differential mode).

Status of selected reference (status of differential reference);

active low.

1

0

1

0

1

0

1

0

DYN

LVL

(not available when in

Status of unselected reference (not available in differential mode);

active low.

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LVL

Status of REF1 frequency (active low).

Status of REF2 frequency (active low).

(Status of REF1 frequency) AND (Status of REF2 frequency)

.

(DLD) AND (Status of selected reference) AND (Status of VCO)

Status of VCO frequency (active low).

Selected reference (low = REF2, high = REF1).

Digital lock detect (DLD); active low.

Holdover active (active low).

LD pin comparator output (active low).

.

1C

<7> Disable

Switchover <7> = 0; enable switchover deglitch circuit.

Deglitch <7> = 1; disable switchover deglitch circuit.

Disable or enable the switchover deglitch circuit.

<6> Select REF2 If Register 0x1C<5> = 0, select reference for PLL.

<6> = 0; select REF1.

<6> = 1; select REF2.

<5> Use REF_SEL If Register 0x1C<4> = 0 (manual), set method of PLL reference selection.

<5> = 0; use Register 0x1C<6>.

<5> = 1; use REF_SEL pin.

<4> Automatic

Reference

Automatic or manual reference switchover. Single-ended reference mode must be selected by

Register 0x1C<0> = 0.

Switchover <4> = 0; manual reference switchover.

<4> = 1; automatic reference switchover.

<3> Stay on REF2 Stay on REF2 after switchover.

<3> = 0; return to REF1 automatically when REF1 status is good again.

1C

<3> = 1; stay on REF2 after switchover. Do not automatically return to REF1.

When automatic reference switchover is disabled, this bit turns the REF2 power on.

<2> = 0; REF2 power off.

<2> REF2

Power On

<2> = 1; REF2 power on.

<1> REF1

Power On

When automatic reference switchover is disabled, this bit turns the REF1 power on.

<1> = 0; REF1 power off.

<1> = 1; REF1 power on.

<0> Differential Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the

Reference

automatic switchover or REF1 and REF2 to work.

<0> = 0; single-ended reference mode.

<0> = 1; differential reference mode.

Disables the PLL status register readback.

<4> = 0; PLL status register enable.

1D

<4> PLL Status

Register

Disable

<4> = 1; PLL status register disable.

Rev. 0 | Page 66 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode.

Comparator When in the internal (automatic) holdover mode, this enables the use of the voltage on the LD pin to

1D

<3> LD Pin

Enable

determine if the PLL was previously in a locked state (see Figure 51). Otherwise, this can be used with

the REFMON and STATUS pins to monitor the voltage on this pin.

<3> = 0; disable LD pin comparator; internal/automatic holdover controller treats this pin as true (high).

<3> = 1; enable LD pin comparator.

1D

<2> Holdover

Enable

Along with <0> enables the holdover function.

<2> = 0; holdover disabled.

<2> = 1; holdover enabled.

<1> External

Holdover

SYNC

pin. (This disables the internal holdover mode.)

Enables the external hold control through the

<1> = 0; automatic holdover mode—holdover controlled by automatic holdover circuit.

Control

SYNC

pin.

<1> = 1; external holdover mode—holdover controlled by

Along with <2> enables the holdover function.

<0> = 0; holdover disabled.

1D

1F

<0> Holdover

Enable

<0> = 1; holdover enabled.

<6> VCO Cal

Finished

Readback register: status of the VCO calibration.

<6> = 0; VCO calibration not finished.

<6> = 1; VCO calibration finished.

<5> Holdover

Active

Readback register: indicates if the part is in the holdover state (see Figure 51). This is not the same as

holdover enabled.

<5> = 0; not in holdover.

<5> = 1; holdover state active.

1F

<4> REF2

Selected

Readback register: indicates which PLL reference is selected as the input to the PLL.

<4> = 0; REF1 selected (or differential reference if in differential mode).

<4> = 1; REF2 selected.

<3> VCO

Readback register: indicates if the VCO frequency is greater than the threshold (see Table 16, REF1, REF2, and

Frequency > VCO Frequency Status Monitor).

Threshold

<3> = 0; VCO frequency is less than the threshold.

<3> = 1; VCO frequency is greater than the threshold.

1F

<2> REF2

Readback register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency

Frequency > set by Register 0x1A<6>.

Threshold <2> = 0; REF2 frequency is less than threshold frequency.

<2> = 1; REF2 frequency is greater than threshold frequency.

<1> REF1

Readback register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency

Frequency > set by Register 0x1A<6>.

Threshold <1> = 0; REF1 frequency is less than threshold frequency.

<1> = 1; REF1 frequency is greater than threshold frequency.

<0> Digital Lock Readback register: digital lock detect.

Detect

<0> = 0; PLL is not locked.

<0> = 1; PLL is locked.

Rev. 0 | Page 67 of 84

AD9516-3

Table 54. Fine Delay Adjust: OUT6 to OUT9

Reg.

Addr

(Hex) Bit(s) Name

Description

A0

<0> OUT6 Delay

Bypass or use the delay function.

<0> = 0; use delay function.

<0> = 1; bypass delay function.

Bypass

A1

<5:3> OUT6 Ramp

Capacitors

Selects the number of ramp capacitors used by the delay function. The combination of the number of the

capacitors and the ramp current sets the delay full scale.

<5> <4> <3> Number of Capacitors

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4

3

2

3

2

1

A1

<2:0> OUT6 Ramp

Current

Ramp current for the delay function. The combination of the number of capacitors and the ramp current

sets the delay full scale.

<2> <1> <0> Current (μA)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

200

400

600

800

1000

1200

1400

1600

A2

A3

<5:0> OUT6

Selects the fraction of the full-scale delay desired (6-bit binary).

000000 gives zero delay.

Only delay values up to 47 decimals (101111b; 0x2F) are supported.

Delay Fraction

<0> OUT7 Delay

Bypass

Bypass or use the delay function.

<0> = 0; use delay function.

<0> = 1; bypass delay function.

A4

<5:3> OUT7 Ramp

Capacitors

Selects the number of ramp capacitors used by the delay function. The combination of the number of the

capacitors and the ramp current sets the delay full scale.

<5> <4> <3> Number of Capacitors

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4

3

2

3

2

1

Rev. 0 | Page 68 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

A4

<2:0> OUT7 Ramp

Ramp current for the delay function. The combination of the number of capacitors and the ramp

current sets the delay full scale.

Current

<2> <1> <0> Current (μA)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

200

400

600

800

1000

1200

1400

1600

A5

A6

<5:0> OUT7 Delay

Fraction

Selects the fraction of the full-scale delay desired (6-bit binary).

000000 give zero delay.

Only delay values up to 47 decimals (101111b; 0x2F) are supported.

<0> OUT8 Delay

Bypass

Bypass or use the delay function.

<0> = 0; use delay function.

<0> = 1; bypass delay function.

A7

<5:3> OUT8 Ramp

Capacitors

Selects the number of ramp capacitors used by the delay function. The combination of the number of

capacitors and the ramp current sets the delay full scale.

<5> <4> <3> Number of Capacitors

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4

3

2

3

2

1

A7

<2:0> OUT8 Ramp

Current

Ramp current for the delay function. The combination of the number of capacitors and the ramp

current sets the delay full scale.

<2> <1> <0> Current (μA)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

200

400

600

800

1000

1200

1400

1600

A8

A9

<5:0> OUT8 Delay

Fraction

Selects the fraction of the full-scale delay desired (6-bit binary).

000000 gives zero delay.

Only delay values up to 47 decimals (101111b; 0x2F) are supported.

<0> OUT9 Delay

Bypass

Bypass or use the delay function.

<0> = 0; use delay function.

<0> = 1; bypass delay function.

Rev. 0 | Page 69 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

AA <5:3> OUT9 Ramp

Capacitors

Selects the number of ramp capacitors used by the delay function. The combination of the number of

capacitors and the ramp current sets the delay full scale.

<5> <4> <3> Number of Capacitors

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4

3

2

3

2

1

AA <2:0> OUT9 Ramp

Current

Ramp current for the delay function. The combination of the number of capacitors and the ramp

current sets the delay full scale.

<2> <1> <0> Current Value (μA)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

200

400

600

800

1000

1200

1400

1600

AB <5:0> OUT9 Delay

Fraction

Selects the fraction of the full-scale delay desired (6-bit binary).

000000 gives zero delay.

Only delay values up to 47 decimals (101111b; 0x2F) are supported.

Table 55. LVPECL Outputs

Reg.

Addr

(Hex) Bit(s) Name

Description

F0

<4> OUT0 Invert Sets the output polarity.

<4> = 0; noninverting.

<4> = 1; inverting.

F0

<3:2> OUT0 LVPECL Sets the LVPECL output differential voltage (V_OD).

Differential

Voltage

<3> <2> V_OD(mV)

0

1

0

1

0

1

400

600

780

960

F0

F1

<1:0> OUT0

LVPECL power-down modes.

Power-Down <1> <0> Mode

Output

On

Off

0

1

0

1

0

1

Normal operation.

Partial power-down, reference on; use only if there are no external load resistors.

Partial power-down, reference on, safe LVPECL power-down.

Total power-down, reference off; use only if there are no external load resistors.

<4> OUT1 Invert Sets the output polarity.

<4> = 0; noninverting.

<4> = 1; inverting.

Rev. 0 | Page 70 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

F1

<3:2> OUT1 LVPECL Sets the LVPECL output differential voltage (V_OD).

Differential

Voltage

<3> <2> V_OD(mV)

0

1

0

1

0

1

400

600

780

960

F1

<1:0> OUT1

LVPECL power-down modes.

Power-Down <1> <0> Mode

Output

On

Off

0

1

0

1

0

1

Normal operation.

Partial power-down, reference on; use only if there are no external load resistors.

Partial power-down, reference on, safe LVPECL power-down.

Total power-down, reference off; use only if there are no external load resistors.

F2

<4> OUT2 Invert Sets the output polarity.

<4> = 0; noninverting.

<4> = 1; inverting.

<3:2> OUT2 LVPECL Sets the LVPECL output differential voltage (V_OD).

Differential

Voltage

<3> <2> V_OD(mV)

0

1

0

1

0

1

400

600

780

960

F2

<1:0> OUT2

LVPECL power-down modes.

Power-Down <1> <0> Mode

Output

On

Off

0

1

0

1

0

1

Normal operation.

Partial power-down, reference on; use only if there are no external load resistors.

Partial power-down, reference on, safe LVPECL power-down.

Total power-down, reference off; use only if there are no external load resistors.

F3

<4> OUT3 Invert Sets the output polarity.

<4> = 0; noninverting.

<4> = 1; inverting.

<3:2> OUT3 LVPECL Sets the LVPECL output differential voltage (V_OD).

Differential

Voltage

<3> <2> V_OD(mV)

0

1

0

1

0

1

400

600

780

960

F3

<1:0> OUT3

LVPECL power-down modes.

Power-Down <1> <0>

Mode

Normal operation.

Output

On

Off

0

1

0

1

0

1

Partial power-down, reference on; use only if there are no external load resistors.

Partial power-down, reference on, safe LVPECL power-down.

Total power-down, reference off; use only if there are no external load resistors.

F4

<4> OUT4 Invert Sets the output polarity.

<4> = 0; noninverting.

<4> = 1; inverting.

<3:2> OUT4 LVPECL Sets the LVPECL output differential voltage (V_OD).

Differential

Voltage

<3> <2> V_OD(mV)

0

1

0

1

0

1

400

600

780

960

Rev. 0 | Page 71 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

F4

<1:0> OUT4

LVPECL power-down modes.

Power-Down <1> <0> Mode

Normal operation.

Output

On

0

1

0

1

Partial power-down, reference on; use only if there are no external load resistors.

Partial power-down, reference on, safe LVPECL power-down.

Total power-down, reference off; use only if there are no external load resistors.

Off

F5

<4> OUT5 Invert Sets the output polarity.

<4> = 0; noninverting.

<4> = 1; inverting.

<3:2> OUT5 LVPECL Sets the LVPECL output differential voltage (V_OD).

Differential

Voltage

<3> <2> V_OD(mV)

0

1

0

1

0

1

400

600

780

960

F5

<1:0> OUT5

LVPECL power-down modes.

Power-Down <1> <0> Mode

Output

On

Off

0

1

0

1

0

1

Normal operation.

Partial power-down, reference on; use only if there are no external load resistors.

Partial power-down, reference on, safe LVPECL power-down.

Total power-down, reference off; use only if there are no external load resistors.

Table 56. LVDS/CMOS Outputs

Reg.

Addr

(Hex) Bit(s) Name

Description

140

<7:5> OUT6 Output Polarity

In CMOS mode, <7:5> select the output polarity of each CMOS output.

In LVDS mode, only <5> determines LVDS polarity.

<7> <6> <5> OUT6A (CMOS)

OUT6B (CMOS)

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

OUT6 (LVDS)

Noninverting

Inverting

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Noninverting

Inverting

Noninverting

140

<4> OUT6 CMOS B

In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.

<4> = 0; turn off the CMOS B output.

<4> = 1; turn on the CMOS B output.

<3> OUT6 Select LVDS/CMOS

<2:1> OUT6 LVDS Output Current

Select LVDS or CMOS logic levels.

<3> = 0; LVDS.

<3> = 1; CMOS.

Set output current level in LVDS mode. This has no effect in CMOS mode.

<2> <1> Current (mA)

Recommended Termination (Ω)

0

1

0

1

0

1

1.75

3.5

5.25

7

100

50

Rev. 0 | Page 72 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

140

<0> OUT6 Power-Down

Power-down output (LVDS/CMOS).

<0> = 0; power on.

<0> = 1; power off.

141

<7:5> OUT7 Output Polarity

In CMOS mode, <7:5> select the output polarity of each CMOS output.

In LVDS mode, only <5> determines LVDS polarity.

<7> <6> <5> OUT7A (CMOS) OUT7B (CMOS)

OUT7 (LVDS)

Noninverting

Inverting

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

141

<4> OUT7 CMOS B

In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.

<4> = 0; turn off the CMOS B output.

<4> = 1; turn on the CMOS B output.

<3> OUT7 Select LVDS/CMOS

<2:1> OUT7 LVDS Output Current

Select LVDS or CMOS logic levels.

<3> = 0; LVDS.

<3> = 1; CMOS.

Set output current level in LVDS mode. This has no effect in CMOS mode.

<2> <1> Current (mA)

Recommended Termination (Ω)

0

1

0

1

0

1

1.75

3.5

5.25

7

100

50

141

142

<0> OUT7 Power-Down

<7:5> OUT8 Output Polarity

Power-down output (LVDS/CMOS).

<0> = 0; power on.

<0> = 1; power off.

In CMOS mode, <7:5> select the output polarity of each CMOS output.

In LVDS mode, only <5> determines LVDS polarity.

<7> <6> <5> OUT8A (CMOS) OUT8B (CMOS)

OUT8 (LVDS)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

142

<4> OUT8 CMOS B

In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.

<4> = 0; turn off the CMOS B output.

<4> = 1; turn on the CMOS B output.

<3> OUT8 Select LVDS/CMOS

<2:1> OUT8 LVDS Output Current

Select LVDS or CMOS logic levels.

<3> = 0; LVDS.

<3> = 1; CMOS.

Set output current level in LVDS mode. This has no effect in CMOS mode.

<2>

0

1

<1> Current (mA) Recommended Termination (Ω)

0

1

0

1

1.75

3.5

5.25

100

50

7

50

Rev. 0 | Page 73 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

142

<0> OUT8 Power-Down

Power-down output (LVDS/CMOS).

<0> = 0; power on.

<0> = 1; power off.

143

<7:5> OUT9 Output Polarity

In CMOS mode, <7:5> select the output polarity of each CMOS output.

In LVDS mode, only <5> determines LVDS polarity.

<7> <6> <5> OUT9A (CMOS) OUT9B (CMOS)

OUT9 (LVDS)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

Noninverting

Inverting

143

<4> OUT9 CMOS B

In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.

<4> = 0; turn off the CMOS B output.

<4> = 1; turn on the CMOS B output.

<3> OUT9 Select LVDS/CMOS

<2:1> OUT9 LVDS Output Current

Select LVDS or CMOS logic levels.

<3> = 0; LVDS.

<3> = 1; CMOS.

Set output current level in LVDS mode. This has no effect in CMOS mode.

<2> <1> Current (mA)

Recommended Termination (Ω)

0

1

0

1

0

1

1.75

3.5

5.25

7

100

50

143

<0> OUT9 Power-Down

Power-down output (LVDS/CMOS).

<0> = 0; power on.

<0> = 1; power off.

Table 57. LVPECL Channel Dividers

Reg.

Addr

(Hex) Bit(s) Name

Description

190

191

<7:4> Divider 0 Low Cycles

Number of clock cycles of the divider input during which divider output stays low.

<3:0> Divider 0 High Cycles

Number of clock cycles of the divider input during which divider output stays high.

<7>

<6>

<5>

<4>

Divider 0 Bypass

Bypass and power-down the divider; route input to divider output.

<7> = 0; use divider.

<7> = 1; bypass divider.

191

Divider 0 Nosync

Divider 0 Force High

Divider 0 Start High

Nosync.

<6> = 0; obey chip-level SYNC signal.

<6> = 1; ignore chip-level SYNC signal.

Force divider output to high. This requires that nosync also be set.

<5> = 0; divider output forced to low.

<5> = 1; divider output forced to high.

Selects clock output to start high or start low.

<4> = 0; start low.

<4> = 1; start high.

<3:0> Divider 0 Phase Offset

Phase offset.

Rev. 0 | Page 74 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

192

<1>

Divider 0 Direct to Output

Connect OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.

<1> = 0: OUT0 and OUT1 are connected to Divider 0.

<1> = 1:

If 0x1E1<1:0> = 10b, the VCO is routed directly to OUT0 and OUT1.

If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT0 and OUT1.

If 0x1E1<1:0> = 01b, there is no effect.

192

<0>

Divider 0 DCCOFF

Duty-cycle correction function.

<0> = 0; enable duty-cycle correction.

<0> = 1; disable duty-cycle correction.

193

194

<7:4> Divider 1 Low Cycles

<3:0> Divider 1 High Cycles

Number of clock cycles of the divider input during which divider output stays low.

Number of clock cycles of the divider input during which divider output stays high.

<7>

<6>

<5>

<4>

Divider 1 Bypass

Bypass and power-down the divider; route input to divider output.

<7> = 0; use divider.

<7> = 1; bypass divider.

194

Divider 1 Nosync

Divider 1 Force High

Divider 1 Start High

Nosync.

<6> = 0; obey chip-level SYNC signal.

<6> = 1; ignore chip-level SYNC signal.

Force divider output to high. This requires that nosync also be set.

<5> = 0; divider output forced to low.

<5> = 1; divider output forced to high.

Selects clock output to start high or start low.

<4> = 0; start low.

<4> = 1; start high.

194

195

<3:0> Divider 1 Phase Offset

Phase offset.

<1>

Divider 1 Direct to Output

Connect OUT2 and OUT3 to Divider 1 or directly to VCO or CLK.

<1> = 0; OUT2 and OUT3 are connected to Divider 1.

<1> = 1:

If 0x1E1<1:0> = 10b, the VCO is routed directly to OUT2 and OUT3.

If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT2 and OUT3.

If 0x1E1<1:0> = 01b, there is no effect.

195

<0>

Divider 1 DCCOFF

Duty-cycle correction function.

<0> = 0; enable duty-cycle correction.

<0> = 1; disable duty-cycle correction.

196

197

<7:4> Divider 2 Low Cycles

<3:0> Divider 2 High Cycles

Number of clock cycles of the divider input during which divider output stays low.

Number of clock cycles of the divider input during which divider output stays high.

<7>

<6>

<5>

<4>

Divider 2 Bypass

Bypass and power down the divider; route input to divider output.

<7> = 0; use divider.

<7> = 1; bypass divider.

197

Divider 2 Nosync

Divider 2 Force High

Divider 2 Start High

Nosync.

<6> = 0; obey chip-level SYNC signal.

<6> = 1; ignore chip-level SYNC signal.

Force divider output to high. This requires that nosync also be set.

<5> = 0; divider output forced to low.

<5> = 1; divider output forced to high.

Selects clock output to start high or start low.

<4> = 0; start low.

<4> = 1; start high.

<3:0> Divider 2 Phase Offset

Phase offset.

Rev. 0 | Page 75 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

198

<1>

Divider 2 Direct to Output

Connect OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.

<1> = 0; OUT4 and OUT5 are connected to Divider 2.

<1> = 1:

If 0x1E1<1:0> = 10b, the VCO is routed directly to OUT4 and OUT5.

If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT4 and OUT5.

If 0x1E1<1:0> = 01b, there is no effect.

198

<0>

Divider 2 DCCOFF

Duty-cycle correction function.

<0> = 0; enable duty-cycle correction.

<0> = 1; disable duty-cycle correction.

Table 58. LVDS/CMOS Channel Dividers

Reg.

Addr

(Hex) Bit(s) Name

Description

199

19A

19B

19C

<7:4> Low Cycles Divider 3.1

<3:0> High Cycles Divider 3.1

<7:4> Phase Offset Divider 3.2

<3:0> Phase Offset Divider 3.1

<7:4> Low Cycles Divider 3.2

<3:0> High Cycles Divider 3.2

Number of clock cycles of 3.1 divider input during which 3.1 output stays low.

Number of clock cycles of 3.1 divider input during which 3.1 output stays high.

Refer to LVDSCMOS channel divider function description.

Number of clock cycles of 3.2 divider input during which 3.2 output stays low.

Number of clock cycles of 3.2 divider input during which 3.2 output stays high.

<5>

<4>

<3>

<2>

<1>

<0>

Bypass Divider 3.2

Bypass Divider 3.1

Divider 3 Nosync

Bypass (and power-down) 3.2 divider logic, route clock to 3.2 output.

<5> = 0; do not bypass.

<5> = 1; bypass.

19C

19D

Bypass (and power-down) 3.1 divider logic, route clock to 3.1 output.

<4> = 0; do not bypass.

<4> = 1; bypass.

Nosync.

<3> = 0; obey chip-level SYNC signal.

<3> = 1; ignore chip-level SYNC signal.

Force Divider 3 output high. Requires that nosync also be set.

<2> = 0; force low.

Divider 3 Force High

Start High Divider 3.2

Start High Divider 3.1

Divider 3 DCCOFF

<2> = 1; force high.

Divider 3.2 start high/low.

<1> = 0; start low.

<1> = 1; start high.

Divider 3.1 start high/low.

<0> = 0; start low.

<0> = 1; start high.

Duty-cycle correction function.

<0> = 0; enable duty-cycle correction.

<0> = 1; disable duty-cycle correction.

Number of clock cycles of divider 4.1 input during which 4.1 output stays low.

19E

19F

1A0

<7:4> Low Cycles Divider 4.1

<3:0> High Cycles Divider 4.1

<7:4> Phase Offset Divider 4.2

<3:0> Phase Offset Divider 4.1

<7:4> Low Cycles Divider 4.2

<3:0> High Cycles Divider 4.2

Number of clock cycles of 4.1 divider input during which 4.1 output stays high.

Refer to LVDSCMOS channel divider function description.

Number of clock cycles of 4.2 divider input during which 4.2 output stays low.

Number of clock cycles of 4.2 divider input during which 4.2 output stays high.

Rev. 0 | Page 76 of 84

AD9516-3

Reg.

Addr

(Hex) Bit(s) Name

Description

1A1

1A2

<5>

<4>

<3>

<2>

<1>

<0>

Bypass Divider 4.2

Bypass Divider 4.1

Divider 4 Nosync

Bypass (and power down) 4.2 divider logic, route clock to 4.2 output.

<5> = 0; do not bypass.

<5> = 1; bypass.

Bypass (and power down) 4.1 divider logic, route clock to 4.1 output.

<4> = 0; do not bypass.

<4> = 1; bypass.

Nosync.

<3> = 0; obey chip-level SYNC signal.

<3> = 1; ignore chip-level SYNC signal.

Force Divider 4 output high. Requires that nosync also be set.

<2> = 0; force low.

Divider 4 Force High

Start High Divider 4.2

Start High Divider 4.1

Divider 4 DCCOFF

<2> = 1; force high.

Divider 4.2 start high/low.

<1> = 0; start low.

<1> = 1; start high.

Divider 4.1 start high/low.

<0> = 0; start low.

<0> = 1; start high.

Duty-cycle correction function.

<0> = 0; enable duty-cycle correction.

<0> = 1; disable duty-cycle correction.

Table 59. VCO Divider and CLK Input

Reg.

Addr

(Hex) Bit(s) Name

Description

1E0 <2:0> VCO Divider

<2>

<1>

<0>

Divide

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

Output static

1E1 <4> Power-Down Clock Input Section Power down the clock input section (including CLK buffer, VCO divider, and CLK tree).

<4> = 0; normal operation.

<4> = 1; power-down.

1E1 <3> Power-Down VCO Clock Interface Power down the interface block between VCO and clock distribution.

<3> = 0; normal operation.

<3> = 1; power-down.

1E1 <2> Power-Down VCO and CLK

1E1 <1> Select VCO or CLK

Power down both VCO and CLK input.

<2> = 0; normal operation.

<2> = 1; power-down.

Select either the VCO or the CLK as the input to VCO divider.

<1> = 0; select external CLK as input to VCO divider.

<1> = 1; select VCO as input to VCO divider; cannot bypass VCO divider when this is selected.

Bypass or use the VCO divider.

1E1 <0> Bypass VCO Divider

<0> = 0; use VCO divider.

<0> = 1; bypass VCO divider; cannot select VCO as input when this is selected.

Rev. 0 | Page 77 of 84

AD9516-3

Table 60. System

Reg.

Addr

(Hex) Bit(s) Name

Description

230 <2> Power-Down SYNC

Power down the SYNC function.

<2> = 0; normal operation of the SYNC function.

<2> = 1; power-down SYNC circuitry.

230 <1> Power-Down Distribution Reference Power down the reference for distribution section.

<1> = 0; normal operation of the reference for the distribution section.

<1> = 1; power down the reference for the distribution section.

SYNC

230 <0> Soft SYNC

The soft SYNC bit works the same as the

pin, except that the polarity of the bit is

reversed. That is, a high level forces selected channels into a predetermined static

state, and a 1-to-0 transition triggers a SYNC.

SYNC

<0> = 0; same as

<0> = 1; same as

high.

low.

Table 61. Update All Registers

Reg.

Addr

(Hex) Bit(s) Name

Description

232 <0> Update All

Registers

This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens

on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.

<0> = 1 (self-clearing); update all active registers to the contents of the buffer registers.

Rev. 0 | Page 78 of 84

AD9516-3

APPLICATION NOTES

USING THE AD9516 OUTPUTS FOR ADC CLOCK

APPLICATIONS

level, termination) should be considered when selecting the best

clocking/converter solution.

LVPECL CLOCK DISTRIBUTION

Any high speed ADC is extremely sensitive to the quality of its

sampling clock. An ADC can be thought of as a sampling mixer,

and any noise, distortion, or timing jitter on the clock is

combined with the desired signal at the analog-to-digital

output. Clock integrity requirements scale with the analog input

frequency and resolution, with higher analog input frequency

applications at ≥14-bit resolution being the most stringent. The

theoretical SNR of an ADC is limited by the ADC resolution

and the jitter on the sampling clock. Considering an ideal ADC

of infinite resolution where the step size and quantization error

can be ignored, the available SNR can be expressed

The LVPECL outputs of the AD9516 provide the lowest jitter

clock signals available from the AD9516. The LVPECL outputs

(because they are open emitter) require a dc termination to bias

the output transistors. The simplified equivalent circuit in

Figure 57 shows the LVPECL output stage.

In most applications, an LVPECL far-end Thevenin termination

is recommended, as shown in Figure 69. The resistor network is

designed to match the transmission line impedance (50 Ω) and

the switching threshold (V_S− 1.3 V).

VS_LVPECL

approximately by

VS_LVPECL

LVPECL

V

S

127Ω

50Ω

⎛

⎜

⎝

⎞

⎟

⎠

1

SNR(dB) = 20×log

2πf_At_J

SINGLE-ENDED

(NOT COUPLED)

LVPECL

where:

50Ω

f_Ais the highest analog frequency being digitized.

t_Jis the rms jitter on the sampling clock.

83Ω

V

= V – 1.3V

S

T

Figure 68 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

Figure 69. LVPECL Far-End Thevenin Termination

VS_LVPECL

110

0.1nF

18

1

SNR = 20log

2πf_At_J

100Ω DIFFERENTIAL

(COUPLED)

TRANSMISSION LINE

100

90

80

70

60

50

40

30

100Ω

LVPECL

16

14

12

10

8

0.1nF

200Ω

Figure 70. LVPECL with Parallel Transmission Line

LVDS CLOCK DISTRIBUTION

The AD9516 provides four clock outputs (OUT6 to OUT9) that

are selectable as either CMOS or LVDS level outputs. LVDS is a

differential output option that uses a current mode output stage.

The nominal current is 3.5 mA, which yields 350 mV output

swing across a 100 Ω resistor. The LVDS output meets or

exceeds all ANSI/TIA/EIA-644 specifications.

6

10

100

1k

f_A(MHz)

Figure 68. SNR and ENOB vs. Analog Input Frequency

A recommended termination circuit for the LVDS outputs is

shown in Figure 71.

See the AN-756 application note and the AN-501 application note

at www.analog.com.

VS

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. (Distributing a single-ended clock on a noisy PCB

can result in coupled noise on the sample clock. Differential

distribution has inherent common-mode rejection that can

provide superior clock performance in a noisy environment.)

The AD9516 features both LVPECL and LVDS outputs that

provide differential clock outputs, which enable clock solutions

that maximize converter SNR performance. The input

100Ω

LVDS

DIFFERENTIAL (COUPLED)

Figure 71. LVDS Output Termination

See the AN-586 application note at www.analog.com for more

information on LVDS.

requirements of the ADC (differential or single-ended, logic

Rev. 0 | Page 79 of 84

AD9516-3

Termination at the far end of the PCB trace is a second option.

The CMOS outputs of the AD9516 do not supply enough

current to provide a full voltage swing with a low impedance

resistive, far-end termination, as shown in Figure 73. The far-

end termination network should match the PCB trace impedance

and provide the desired switching point. The reduced signal

swing may still meet receiver input requirements in some

applications. This can be useful when driving long trace

lengths on less critical nets.

CMOS CLOCK DISTRIBUTION

The AD9516 provides four clock outputs (OUT6 to OUT9)

that are selectable as either CMOS or LVDS level outputs.

When selected as CMOS, each output becomes a pair of CMOS

outputs, each of which can be individually turned on or off and

set as noninverting or inverting. These outputs are 3.3 V CMOS

compatible.

Whenever single-ended CMOS clocking is used, some of the

following general guidelines should be used.

VS

Point-to-point nets should be designed such that a driver has

only one receiver on the net, if possible. This allows for simple

termination schemes and minimizes ringing due to possible

mismatched impedances on the net. Series termination at the

source is generally required to provide transmission line

matching and/or to reduce current transients at the driver.

The value of the resistor is dependent on the board design and

timing requirements (typically 10 Ω to 100 Ω is used). CMOS

outputs are also limited in terms of the capacitive load or trace

length that they can drive. Typically, trace lengths less than

3 inches are recommended to preserve signal rise/fall times and

preserve signal integrity.

100Ω

50Ω

10Ω

CMOS

100Ω

Figure 73. CMOS Output with Far-End Termination

Because of the limitations of single-ended CMOS clocking,

consider using differential outputs when driving high speed

signals over long traces. The AD9516 offers both LVPECL and

LVDS outputs that are better suited for driving long traces

where the inherent noise immunity of differential signaling

provides superior performance for clocking converters.

60.4Ω

(1.0 INCH)

10Ω

CMOS

MICROSTRIP

Figure 72. Series Termination of CMOS Output

Rev. 0 | Page 80 of 84

AD9516-3

OUTLINE DIMENSIONS

0.30

0.25

0.18

9.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

64

49

48

1

PIN 1

INDICATOR

6.35

6.20 SQ

6.05

8.75

BSC SQ

TOP

VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

33

32

16

17

7.50

REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

SEATING

PLANE

0.50 BSC

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 74. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

CP-64-4

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD9516-3BCPZ¹

AD9516-3BCPZ-REEL7¹

AD9516-3/PCBZ¹

Temperature Range

Package Description

Package Option

CP-64-4

−40°C to +85°C

64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. 0 | Page 81 of 84

AD9516-3

NOTES

Rev. 0 | Page 82 of 84

AD9516-3

NOTES

Rev. 0 | Page 83 of 84

AD9516-3

NOTES

registered trademarks are the property of their respective owners.

D06422-0-6/07(0)

Rev. 0 | Page 84 of 84


型号：	AD9516-3/PCBZ
厂家：	ADI
描述：	14-Output Clock Generator with Integrated 2.0 GHz VCO 14路输出时钟发生器，集成2.0 GHz的VCO 时钟发生器
文件：	总84页 (文件大小：951K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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