AD9576BCPZ-REEL7 [ADI]
Dual PLL, Asynchronous Clock Generator;型号: | AD9576BCPZ-REEL7 |
厂家: | ADI |
描述: | Dual PLL, Asynchronous Clock Generator |
文件: | 总65页 (文件大小:1324K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Dual PLL,
Asynchronous Clock Generator
Data Sheet
AD9576
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Single, low phase noise, fully integrated VCO/fractional-N
PLL core
2
SPI/I C
STATUS
MONITOR
AND PPRx
CONTROL
VCO range: 2375 MHz to 2725 MHz
OPTIONAL
REF2
REF2
Integrated loop filter (requires a single external capacitor)
2 differential, XTAL, or single-ended reference inputs
Reference monitoring capability
DIV
DIV
OUT10
GENERAL-
PURPOSE
PLL
OUT9
OUT8
Automatic redundant XTAL switchover
Minimal transient, smooth switching
Typical RMS jitter
OUT0
OUT1
OUT2
OUT3
DIV
OPTIONAL
OPTIONAL
REF0
REF0
<0.3 ps (12 kHz to 20 MHz), integer-N translations
<0.5 ps (12 kHz to 20 MHz), fractional-N translations
Input frequency
VCO
OUT4
OUT5
DIV
DIV
DIV
REF1
REF1
OUT6
OUT7
VCO
DIV
8 kHz, 1.544 MHz, 2.048 MHz, and 10 MHz to 325 MHz
Preset frequency translations via pin strapping (PPRx)
Using a 25 MHz input reference
AD9576
24.576 MHz, 25 MHz, 33.33 MHz, 50 MHz, 70.656 MHz,
100 MHz, 125 MHz, 148.5 MHz, 156.25 MHz,
161.1328 MHz, 312.5 MHz, 322.2656 MHz, 625 MHz,
or 644.5313 MHz
Figure 1.
GENERAL DESCRIPTION
The AD9576 provides a multiple output clock generator
function comprising two dedicated phase-locked loop (PLL)
cores with flexible frequency translation capability, optimized to
serve as a robust source of asynchronous clocks for an entire
system, providing extended operating life within frequency
tolerance through monitoring of and automatic switchover
between redundant crystal (XTAL) inputs with minimized
switching, induced transients. The fractional-N PLL design is
based on the Analog Devices, Inc., proven portfolio of high
performance, low jitter frequency synthesizers to maximize
network performance, whereas the integer-N PLL provides
general-purpose clocks for use as CPU and field-programmable
gate array (FPGA) reference clocks.
Using a 19.44 MHz input reference
50 MHz, 100 MHz, 125 MHz, 156.25 MHz, 161.1328 MHz,
or 644.5313 MHz
Using a 30.72 MHz input reference
25 MHz, 50 MHz, 100 MHz, 125 MHz, or 156.25 MHz
Single, general-purpose, fully integrated VCO/integer-N
PLL core
VCO range: 750 MHz to 825 MHz
Integrated loop filter
Independent, duplicate reference input or operation from
the fractional-N PLL active reference input
Input frequency: 25 MHz
Preset frequency translations via pin strapping (PPRx)
25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 100 MHz,
133.33 MHz, 200 MHz, or 400 MHz
The AD9576 uses pin strapping to select among a multitude of
power-on ready configurations for its 11 output clocks, which
require only the connection of external pull-up or pull-down
resistors to the appropriate pin program reader pins (PPRx).
These pins provide control of the internal dividers for establishing
the desired frequency translations, clock output functionality,
and input reference functionality. These parameters can also be
manually configured through a serial port interface (SPI).
Up to 3 copies of reference clock output
11 pairs of configurable differential outputs
Output drive formats
3 outputs: HSTL, LVDS, HCSL, 1.8 V CMOS, 2.5 V/3.3 V CMOS
8 outputs: HSTL, LVDS, or 1.8 V CMOS
2.5 V or 3.3 V single-supply operation
The AD9576 is packaged in a 64-lead, 9 mm × 9 mm LFCSP,
requiring only a single 2.5 V or 3.3 V supply. The operating
temperature range is −40°C to +85°C.
APPLICATIONS
Ethernet line cards, switches, and routers
Baseband units
Each OUTx output is differential and contains two pins: OUTx
SATA and PCI express
OUTx
and
. For simplicity, the term OUTx refers to the
Low jitter, low phase noise clock generation
Asynchronous clock generation
functional output block containing these two pins.
Rev. A
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Tel: 781.329.4700 ©2016–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9576
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
PLL0 Integer-N/Fractional-N PLL........................................... 29
PLL1 Integer-N PLL................................................................... 35
Output Distribution................................................................... 36
PPRx Pins .................................................................................... 38
Power-On Reset (POR) ............................................................. 41
Serial Control Port ......................................................................... 42
SPI/I²C Port Selection................................................................ 42
SPI Serial Port Operation.......................................................... 42
I2C Serial Port Operation .......................................................... 44
Control Register Map..................................................................... 48
Control Register Descriptions ...................................................... 51
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Conditions..................................................................................... 4
Supply Current Specifications..................................................... 4
Power Dissipation Specifications ............................................... 5
Reference Inputs ........................................................................... 6
Reference Switchover Output Disturbance Specifications...... 6
PLL0 Characteristics .................................................................... 7
PLL1 Characteristics .................................................................... 7
Clock Distribution Outputs Specifications............................... 7
Output Alignment and Startup Specifications ....................... 10
PLL0 Channels Absolute Clock Jitter Specifications ............. 11
Serial Port Configuration Registers (Register 0x000 to
Register 0x00F)........................................................................... 51
Status Indicator Registers (Register 0x020 to Register 0x021) .. 52
Chip Mode Register (Register 0x040) ..................................... 52
Reference Input Configuration Registers (Register 0x080 to
Register 0x081) ........................................................................... 53
PLL1 and Bypass Channel Absolute Clock Jitter
Reference Switchover Registers (Register 0x082 to
Specifications .............................................................................. 13
Register 0x083) ........................................................................... 54
OUT8 to OUT10 Channel Cycle to Cycle Clock Jitter
PLL0 Configuration Registers (Register 0x100 to
Specifications .............................................................................. 13
Register 0x111) ........................................................................... 55
RESET
Logic Input Pins Characteristics—REF_SEL,
, SPx,
PLL0 VCO Dividers Registers (Register 0x120 to
PPRx............................................................................................. 14
Register 0x122) ........................................................................... 57
Status Output Pins Characteristics—LD_0, LD_1, REF_SW,
REF_STATUS, REF_ACT ......................................................... 14
PLL0 Distribution Registers (Register 0x140 to
Register 0x14D).......................................................................... 58
Serial Control Port Specifications ............................................ 15
Absolute Maximum Ratings.......................................................... 17
Thermal Resistance .................................................................... 17
ESD Caution................................................................................ 17
Pin Configuration and Function Descriptions........................... 18
Typical Performance Characteristics ........................................... 22
Phase Noise and Voltage Waveforms....................................... 22
Reference Switching Frequency and Phase Disturbance ...... 24
Terminology .................................................................................... 25
Theory of Operation ...................................................................... 26
Overview...................................................................................... 26
Reference Inputs ......................................................................... 26
Reference Monitor...................................................................... 27
Reference Switching ................................................................... 28
PLL1 Configuration Registers (Register 0x200 to
Register 0x202) ........................................................................... 60
PLL1 Distribution Registers (Register 0x240 to
Register 0x246) ........................................................................... 60
Applications Information.............................................................. 63
Interfacing to CMOS Clock Outputs....................................... 63
Interfacing to LVDS and HSTL Clock Outputs ..................... 63
Interfacing to HCSL Clock Outputs ........................................ 63
Power Supply............................................................................... 64
Power and Grounding Considerations and Power Supply
Rejection...................................................................................... 64
Outline Dimensions....................................................................... 65
Ordering Guide .......................................................................... 65
Rev. A | Page 2 of 65
Data Sheet
AD9576
REVISION HISTORY
9/2018—Rev. 0 to Rev. A
Change to Table 47, Address 0x103, Bits[5:3], Reset Column.....55
Updated Outline Dimensions........................................................65
7/2016—Revision 0: Initial Version
Rev. A | Page 3 of 65
AD9576
Data Sheet
SPECIFICATIONS
Typical values are given for VDD_x = 2.5 V, TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD_x
and TA (−40°C to +85°C) range.
VDD_x and VDD_x refer to the following pins, and to the voltage on any of the following pins, respectively: VDD_REFMON, VDD_REF0,
VDD_REF1, VDD_IO, VDD_PLL0, VDD_VCO0, VDD_M0, VDD_M1, VDD_OUT67, VDD_OUT45, VDD_OUT23, VDD_OUT01,
VDD_OUT89, VDD_OUT10, VDD_VCO1, VDD_PLL1, and VDD_REF2.
Note that throughout this data sheet, multifunction pins, such as SCLK/SCL, are referred to either by the entire pin name or by a single
function of the pin, for example, SCLK, when only that function is relevant.
CONDITIONS
Table 1.
Parameter
Min Typ Max Unit Test Conditions/Comments
Applies to all VDD_x pins; 2.5 V and 3.3 V nominal supplies are supported on all
POWER SUPPLY
VOLTAGE
specifications, unless otherwise noted
(VDD_x
)
2.38
2.97
2.63
3.63
V
V
2.5 V 5%
3.3 V 10%
SUPPLY CURRENT SPECIFICATIONS
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLIES OTHER THAN CLOCK
OUTPUT DRIVERS
All blocks running (excludes clock distribution section); REF0
(differential) and REF1 (differential) at 300 MHz; PLL0 locked at
2500 MHz with a 100 MHz phase frequency detector (PFD) rate;
Divider M0 set to 2 and Divider M1 disabled; REF2 (XTAL) at
25 MHz, configured as PLL1 input; PLL1 locked to 800 MHz with
input doubler enabled
VDD_REFMON and VDD_REFx
(Pin 4, Pin 9, Pin 10, and
Pin 64)
35.6
26.5
39.2
29.5
mA
mA
Cumulative current draw from all listed supply pins
VDD_IO and VDD_PLL0 (Pin 16
and Pin 18)
Cumulative current draw from all listed supply pins
VDD_VCO0 (Pin 21)
VDD_Mx (Pin 23 and Pin 25)
VDD_VCO1 (Pin 60)
VDD_PLL1 (Pin 61)
33.8
81.0
19.2
20.4
36.9
88.7
21.8
23.7
mA
mA
mA
mA
Cumulative current draw from all listed supply pins
SUPPLY CURRENT FOR EACH
CLOCK DISTRIBUTION SUPPLY
Output driver supplies power both the output driver and output
divider
High Speed Transceiver Logic
(HSTL)
VDD_OUT67 (Pin 29)
VDD_OUT45 (Pin 35)
VDD_OUT23 (Pin 41)
VDD_OUT01(Pin 46)
VDD_OUT89 (Pin 52)
VDD_OUT10 (Pin 57)
59.8
59.8
46.7
36.4
57.4
34.2
69.7
69.7
53.8
42.6
67.1
39.5
mA
mA
mA
mA
mA
mA
Output at 1250 MHz
Output at 1250 MHz
Output at 625 MHz
Output at 625 MHz
Output at 400 MHz
Output at 400 MHz
Low Voltage Differential
Signaling (LVDS)
VDD_OUT67 (Pin 29)
VDD_OUT45 (Pin 35)
VDD_OUT23 (Pin 41)
VDD_OUT01(Pin 46)
VDD_OUT89 (Pin 52)
VDD_OUT10 (Pin 57)
41.3
41.3
31.1
20.8
37.5
24.1
49.2
49.2
34.9
23.6
43.6
27.7
mA
mA
mA
mA
mA
mA
Output at 1250 MHz
Output at 1250 MHz
Output at 625 MHz
Output at 625 MHz
Output at 400 MHz
Output at 400 MHz
Rev. A | Page 4 of 65
Data Sheet
AD9576
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
1.8 V CMOS
All outputs at 100 MHz with a 10 pF load
VDD_OUT67 (Pin 29)
27.2
27.2
28.2
17.4
32.7
21.4
34.7
34.7
31.7
21.9
42.5
26.8
mA
mA
mA
mA
mA
mA
VDD_OUT45 (Pin 35)
VDD_OUT23 (Pin 41)
VDD_OUT01(Pin 46)
VDD_OUT89 (Pin 52)
VDD_OUT10 (Pin 57)
2.5 V CMOS
VDD_x set to 2.5 V, output at 100 MHz with a 10 pF load; not
available on OUT0 to OUT7
VDD_OUT89 (Pin 52)
VDD_OUT10 (Pin 57)
3.3 V CMOS
38.5
24.4
48.8
30.1
mA
mA
VDD_x set to 3.3 V, all outputs at 100 MHz with a 10 pF load; not
available on OUT0 to OUT7
VDD_OUT89 (Pin 52)
VDD_OUT10 (Pin 57)
48.5
29.1
60.4
36.2
mA
mA
High Speed Current Sinking
Logic (HCSL)
All outputs at 400 MHz; not available on OUT0 to OUT7
VDD_OUT89 (Pin 52)
VDD_OUT10 (Pin 57)
30.7
20.8
41.4
26.6
mA
mA
POWER DISSIPATION SPECIFICATIONS
Table 3.
Parameter
Min Typ
Max
Unit
Test Conditions/Comments
POWER DISSIPATION
All supplies set to 2.5 V nominal; specifications do not include power
dissipated by external terminations
Typical Configuration 1
Typical Configuration 2
680
1168
mW
Asynchronous operation; PPR0 = State 0, PPR1 = State 0, PPR2 = State 3,
PPR3 = State 3; REF 0 and REF1 = 25 MHz XTAL, doubler enabled; OUT10 =
25 MHz CMOS; OUT0 to OUT3 = 100 MHz LVDS; OUT4 to OUT5 = 312.5 MHz
LVDS, OUT6 to OUT7 = 156.25 MHz LVDS, OUT8 to OUT9 = 125 MHz LVDS
619
979
145
974
mW
mW
mW
Synchronous operation; REF0 (differential) at 100 MHz, REF1 disabled, and
REF2 (XTAL) at 25 MHz; PLL1 disabled and PLL0 locked at 2500 MHz using R
divider of 2 and PLL0 feedback divider (N0) set to 50; M0 and M1 set to
divide by 2; Output 0 set to 625 MHz HSTL; Output 1 to Output 3 disabled;
Output 4 to Output 7 set to 125 MHz LVDS; Output 8 to Output 9 set to
156.25 MHz LVDS
All Blocks Running
1520
179
All blocks running; REF0 (differential) and REF1 (differential) at 300 MHz;
PLL0 locked at 2500 MHz with a 100 MHz PFD rate; M0 set to 2 and enabled to
Q0, Q1, and Q2; OUT0 to OUT3 = 625 MHz LVDS; OUT4 to OUT 7 = 1250 MHz
LVDS; REF2 (XTAL) at 25 MHz, configured as PLL1 input; PLL1 locked to
800 MHz with input doubler enabled; Divider Q3 and Divider Q4 set to 2 and
OUT8 to OUT10 = 400 MHz, HCSL
Minimal Power
Configuration
PPR0 = State 0, PPR1 = State 0, PPR2 = State 0, PPR3 = State 0
INCREMENTAL POWER
DISSIPATION
Typical configuration; values show the change in power due to the indicated
operation
Input Reference On/Off
Single-Ended
Applies to one reference clock input at 25 MHz
2.5
10
mW
mW
Differential
27.5
33.7
Output Driver On/Off
LVDS at 156.25 MHz
HSTL at 156.25 MHz
47.6
51.3
64.6
66.1
80.8
74.1
mW
mW
mW
1.8 V CMOS at
100 MHz
A single 1.8 V CMOS output with a 10 pF load
A single 2.5 V CMOS output with a 10 pF load
2.5 V CMOS at
100 MHz
88.4
102.5
mW
Rev. A | Page 5 of 65
AD9576
Data Sheet
REFERENCE INPUTS
Table 4.
Parameter
Min
Typ Max
Unit
Test Conditions/Comments
DIFFERENTIAL INPUT MODE
Input Frequency
Input Sensitivity
Minimum Input Slew Rate
325
MHz
100
100
mV p-p
V/µs
Minimum limit imposed for jitter performance (when using
a sinusoidal source)
Minimum Pulse Width
1.38
0.83
ns
V
Applies to both low and high pulses
Common-Mode Internally Generated
Bias Voltage
1.24
Common-Mode Voltage Tolerance
1.675
V
The acceptable common-mode range for a 200 mV p-p,
dc-coupled input signal
Differential Input Capacitance
Differential Input Resistance
SINGLE-ENDED INPUT CMOS MODE
Input Frequency
2
pF
4.3
kΩ
200
MHz
ns
Minimum Pulse Width
Hysteresis
2
Applies to both low and high pulses
240
2
mV
nA
Input Leakage
Input Capacitance
Input Voltage
2
pF
High
1.93
V
V
Low
1.04
CRYSTAL RESONATOR MODE
Input Frequency
Fundamental mode quartz resonator
Reference of PLL0 or Buffered
Output
19.44
30.72 MHz
Reference of PLL1
25
3
MHz
Ω
REF2
Effective Series Resistance (ESR)
Input Capacitance
80
pF
REFERENCE SWITCHOVER OUTPUT DISTURBANCE SPECIFICATIONS
Table 5.
Parameter
Min Typ
Max
Unit
Test Conditions/Comments
INSTANTANEOUS FREQUENCY (dθ/dt)
DISTURBANCE DUE TO REFERENCE
SWITCHOVER
350
ppm
peak
Applies only to PLL0 outputs; 1 ppm frequency offset
between the REF0 and REF1 channels; 400 kHz loop
bandwidth; smooth switchover enabled
INSTANTANEOUS PHASE DISTURBANCE
DUE TO REFERENCE SWITCHOVER
220
ps
Applies only to the active reference of PLL0; smooth
switchover enabled
Rev. A | Page 6 of 65
Data Sheet
AD9576
PLL0 CHARACTERISTICS
Table 6.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE INPUT PATH
Input Frequency
Divider
325
145
MHz
MHz
Doubler
PHASE FREQUENCY DETECTOR (PFD)
Frequency Range
Integer Mode
290
170
MHz
MHz
ppm
Fractional Mode
9.4
Lock Detect Window
16
INPUT FREQUENCY OF FEEDBACK DIVIDERS
N0
2725
156
MHz
MHz
MHz
N0A
QZD
1250
VOLTAGE CONTROLLED OSCILLATOR (VCO)
Frequency Range
2375
2725
1250
MHz
Gain
64
MHz/V
MHz
VCO DIVIDER (M0 AND M1) OUTPUT FREQUENCY
PLL1 CHARACTERISTICS
Table 7.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE INPUT PATH
Input Frequency
Divider
25
25
MHz
MHz
Doubler
PFD FREQUENCY
Frequency Range
Lock Detector Window
VCO
25
50
MHz
UI
2
Frequency Range
Gain
750
825
MHz
750
MHz/V
CLOCK DISTRIBUTION OUTPUTS SPECIFICATIONS
Rise and fall time measurement thresholds are 20% and 80% of the nominal low and high amplitude of the waveform.
Table 8.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HSTL (OUT0 TO OUT7)
Output Frequency
OUT0 to OUT3
100 Ω termination (differential)
1000
1250
163
MHz
MHz
ps
OUT4 to OUT7
Output Rise Time, tRL
Output Fall Time, tFL
Duty Cycle
108
108
45
136
136
Measured differentially; output at 100 MHz
Measured differentially; output at 100 MHz
161
ps
55
%
Differential Output Voltage Swing
861
1080
940
1374
mV
Magnitude of voltage across pins; output
driver static
Common-Mode Output Voltage
840
1034
mV
Output driver static
Rev. A | Page 7 of 65
AD9576
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVDS (OUT0 TO OUT7)
Output Frequency
OUT0 to OUT3
100 Ω termination (differential)
1000
1250
181
181
55
MHz
MHz
ps
OUT4 to OUT7
Output Rise Time, tRL
Output Fall Time, tFL
Duty Cycle
139
141
45
158
159
Measured differentially; output at 100 MHz
Measured differentially; output at 100 MHz
ps
%
Differential Output Voltage, VOD
276
375
490
mV
Magnitude of voltage across pins; output
driver static
Delta VOD
22
mV
V
Output Offset Voltage, VOS
Delta VOS
1.18
1.275
1.36
26
mV
mA
Short-Circuit Current (ISA, ISB)
25
Output shorted to GND; value represents the
magnitude of current draw
1.8 V CMOS (OUT0 TO OUT7)
Output Frequency
Output Rise Time, tRC
Output Fall Time, tFC
Duty Cycle
CLOAD = 10 pF
200
1.54
1.49
55
MHz
ns
0.84
1.04
45
1.19
1.25
Output at 25 MHz
Output at 25 MHz
ns
%
Output Voltage
High (VOH)
1.74
V
V
ILOAD = −1 mA
Low (VOL)
0.065
ILOAD = 1 mA
HSTL (OUT8 TO OUT10)
Output Frequency
Output Rise Time, tRL
Output Fall Time, tFL
Duty Cycle
100 Ω termination (differential)
1000
170
170
55
MHz
ps
124
125
45
144
144
Measured differentially; output at 100 MHz
Measured differentially; output at 100 MHz
Assumes 50% reference input duty cycle
ps
%
Differential Output Voltage Swing
861
1080
940
1374
mV
Magnitude of voltage across pins; output
driver static
Common-Mode Output Voltage
LVDS (OUT8 TO OUT10)
Output Frequency
840
1034
mV
Output driver static
100 Ω termination (differential)
1000
112
113
55
MHz
ps
Output Rise Time, tRL
65
85
86
Measured differentially; output at 100 MHz
Measured differentially; output at 100 MHz
Assumes 50% reference input duty cycle
Output Fall Time, tFL
66
ps
Duty Cycle
45
%
Differential Output Voltage, VOD
276
375
490
mV
Magnitude of voltage across pins; output
driver static
∆VOD
22
mV
V
Output Offset Voltage, VOS
∆VOS
1.18
1.275
1.36
26
mV
mA
Short-Circuit Current (ISA, ISB)
25
Output shorted to GND; value represents the
magnitude of current draw
1.8 V CMOS (OUT8 TO OUT10)
Output Frequency
Output Rise Time, tRC
Output Fall Time, tFC
Duty Cycle
CLOAD = 10 pF
200
1.41
1.24
55
MHz
ns
0.49
0.59
Output at 25 MHz
ns
Output at 25 MHz
45
%
Assumes 50% reference input duty cycle
Output Voltage
High (VOH)
1.74
V
V
ILOAD = −1 mA
ILOAD = 1 mA
Low (VOL)
0.065
Rev. A | Page 8 of 65
Data Sheet
AD9576
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
FULL SWING CMOS (OUT8 TO OUT10)
Output Frequency
Output Rise Time, tRC
Output Fall Time, tFC
Duty Cycle
CLOAD = 10 pF
250
1.38
1.19
55
MHz
ns
0.50
0.57
Output at 25 MHz
Output at 25 MHz
ns
45
%
Assumes 50% reference input duty cycle
Output Voltage
High (VOH)
VDD_x − 0.33
V
V
ILOAD = −10 mA
Low (VOL)
0.25
ILOAD = 10 mA
HCSL (OUT8 to OUT10)
Output Frequency
Output Rise Time, tRL
Output Fall Time, tFL
Duty Cycle
50 Ω from each output pin to GND
800
211
209
55
145
141
45
174
175
ps
ps
%
Measured differentially; output at 100 MHz
Measured differentially; output at 100 MHz
Assumes 50% reference input duty cycle
Differential Output Voltage Swing
570
770
400
975
mV
Magnitude of voltage across pins; output
driver static
Common-Mode Output Voltage
295
500
mV
Output driver static
Timing Diagrams
SINGLE-ENDED
80%
CMOS
10pF LOAD
20%
tRC
tFC
Figure 2. CMOS Timing, Single-Ended, 10 pF Load
DIFFERENTIAL
80%
LVDS/HSTL/HCSL
20%
tRL
tFL
Figure 3. LVDS, HSTL, and HCSL Timing, Differential
Rev. A | Page 9 of 65
AD9576
Data Sheet
OUTPUT ALIGNMENT AND STARTUP SPECIFICATIONS
The indicated times assume the voltage applied to all power supply pins is within specification and stable.
Table 9.
Parameter
Min
Typ Max Unit Test Conditions/Comments
Timing delay between input clock edge on REF0 or REF1 to any
ZERO DELAY
corresponding OUTx clock edge; R divider and doubler are bypassed
OUT0 to OUT7
3.44 3.87 ns
3.82 4.28 ns
OUT8 to OUT9
OUTPUT TO OUTPUT SKEW
Deviation between rising edges of outputs of a similar logic type; frequency
source to distribution is the output of the M0 divider; all output drivers are
configured to the same logic type, unless otherwise noted; all output
frequencies are 25 MHz
Between Outputs that
Share a Single Qx Divider
LVDS
OUT1, OUT2, and
OUT3
−36
+29
ps
Relative to OUT0
OUT5
OUT7
OUT9
HSTL
−13
−19
−22
+30
+15
+20
ps
ps
ps
Relative to OUT4
Relative to OUT6
Relative to OUT8
OUT1, OUT2, and
OUT3
−33
+30
ps
Relative to OUT0
OUT5
−16
−16
−23
+37
+19
+24
ps
ps
ps
Relative to OUT4
Relative to OUT6
Relative to OUT8
OUT7
OUT9
Between OUT0 to OUT9
LVDS
OUT4
−141
−105
229
−8
ps
ps
ps
Relative to OUT0
Relative to OUT0
Relative to OUT0
OUT6
+23
440
OUT8
HSTL
OUT4
−149
−116
271
−12
+17
487
ps
ps
ps
Relative to OUT0
Relative to OUT0
Relative to OUT0
OUT6
OUT8
PROPAGATION DELAY
3.88 4.47 ns
Rising edge on REF2 input to OUT8 to OUT10; 25 MHz reference input clock,
PLL1 bypassed, and Qx dividers set to 1
OUTPUT READY TIME
PLL0
25 MHz reference input clocks, input doublers disabled
Time interval from RESET pin = Logic 1 to LD_0 pin = Logic 1 (PLL0 lock
detection)
8
ms
µs
PLL1
455
Time interval from RESET pin = Logic 1 to LD_1 pin = Logic 1 (PLL1 lock
detection)
Rev. A | Page 10 of 65
Data Sheet
AD9576
PLL0 CHANNELS ABSOLUTE CLOCK JITTER SPECIFICATIONS
Reference input frequency source is a 25 MHz Taitien XTAL, and frequency multiplier (×2) at PLL input enabled, unless otherwise noted.
Table 10.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HSTL INTEGRATED RMS JITTER
Jitter Integration Bandwidth = 10 kHz to 10 MHz
Integer-N Translations
100 MHz Output
0.233
0.218
0.218
0.221
ps
ps
ps
ps
125 MHz Output
156.25 MHz Output
625 MHz Output
Fractional-N Translations
70.656 MHz Output
0.291
0.307
0.292
0.313
ps
ps
ps
ps
148.5 MHz Output
153.6 MHz Output
644.53125 MHz Output
Jitter Integration Bandwidth = 12 kHz to 20 MHz
Integer-N Translations
100 MHz Output
0.239
0.222
0.221
0.222
ps
ps
ps
ps
125 MHz Output
156.25 MHz Output
625 MHz Output
Fractional-N Translations
70.656 MHz Output
0.298
0.310
0.296
0.314
ps
ps
ps
ps
148.5 MHz Output
153.6 MHz Output
644.53125 MHz Output
Jitter Integration Bandwidth = 50 kHz to 80 MHz
312.5 MHz Output
0.237
ps
Jitter Integration Bandwidth = 1.875 MHz to 20 MHz
Integer-N Translations
100 MHz Output
0.088
0.076
0.071
0.053
ps
ps
ps
ps
125 MHz Output
156.25 MHz Output
625 MHz Output
Fractional-N Translations
70.656 MHz Output
0.119
0.106
0.103
0.096
ps
ps
ps
ps
148.5 MHz Output
153.6 MHz Output
644.53125 MHz Output
LVDS INTEGRATED RMS JITTER
Jitter Integration Bandwidth = 10 kHz to 10 MHz
Integer-N Translations
100 MHz Output
0.242
0.227
0.250
0.221
ps
ps
ps
ps
125 MHz Output
156.25 MHz Output
625 MHz Output
Fractional-N Translations
70.656 MHz Output
0.351
0.329
0.327
0.313
ps
ps
ps
ps
148.5 MHz Output
153.6 MHz Output
644.53125 MHz Output
Rev. A | Page 11 of 65
AD9576
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Jitter Integration Bandwidth = 12 kHz to 20 MHz
Integer-N Translations
100 MHz Output
0.268
0.240
0.257
0.221
ps
ps
ps
ps
125 MHz Output
156.25 MHz Output
625 MHz Output
Fractional-N Translations
70.656 MHz Output
0.412
0.336
0.334
0.314
ps
ps
ps
ps
148.5 MHz Output
153.6 MHz Output
644.53125 MHz Output
Jitter Integration Bandwidth = 50 kHz to 80 MHz
312.5 MHz Output
0.246
ps
Jitter Integration Bandwidth = 1.875 MHz to 20 MHz
Integer-N Translations
100 MHz Output
0.161
0.117
0.099
0.053
ps
ps
ps
ps
125 MHz Output
156.25 MHz Output
625 MHz Output
Fractional-N Translations
70.656 MHz Output
0.298
0.130
0.129
0.095
ps
ps
ps
ps
148.5 MHz Output
153.6 MHz Output
644.53125 MHz Output
HCSL INTEGRATED RMS JITTER
Jitter Integration Bandwidth = 10 kHz to 10 MHz
Integer-N Translations
100 MHz Output
OUT8 and OUT9 only
0.247
0.250
0.273
0.228
ps
ps
ps
ps
125 MHz Output
156.25 MHz Output
625 MHz Output
Jitter Integration Bandwidth = 12 kHz to 20 MHz
100 MHz Output
0.263
0.265
0.298
0.229
ps
ps
ps
ps
125 MHz Output
156.25 MHz Output
625 MHz Output
Jitter Integration Bandwidth = 50 kHz to 80 MHz
312.5 MHz Output
0.348
ps
Jitter Integration Bandwidth = 1.875 MHz to 20 MHz
100 MHz Output
0.145
0.144
0.176
0.063
ps
ps
ps
ps
125 MHz Output
156.25 MHz Output
625 MHz Output
Rev. A | Page 12 of 65
Data Sheet
AD9576
PLL1 AND BYPASS CHANNEL ABSOLUTE CLOCK JITTER SPECIFICATIONS
Table 11.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HSTL INTEGRATED RMS JITTER
25 MHz Output
0.125
1.605
1.641
ps
ps
ps
Source = 25 MHz Taitien XTAL; jitter integration bandwidth =
12 kHz to 5 MHz
100 MHz Output
400 MHz Output
Source = PLL1; Qx divider = 8; jitter integration bandwidth =
12 kHz to 20 MHz
Source = PLL1; Qx divider = 2; jitter integration bandwidth =
12 kHz to 20 MHz
HCSL INTEGRATED RMS JITTER
25 MHz Output
0.287
1.54
ps
ps
ps
Source = 25 MHz Taitien XTAL; jitter integration bandwidth =
12 kHz to 5 MHz
100 MHz Output
400 MHz Output
Source = PLL1; Qx divider = 8; jitter integration bandwidth =
12 kHz to 20 MHz
1.617
Source = PLL1; Qx divider = 2; jitter integration bandwidth =
12 kHz to 20 MHz
LVDS INTEGRATED RMS JITTER
25 MHz Output
0.535
1.535
1.605
ps
ps
ps
Source = 25 MHz Taitien XTAL; jitter integration bandwidth =
12 kHz to 5 MHz
100 MHz Output
400 MHz Output
Source = PLL1; Qx divider = 8; jitter integration bandwidth =
12 kHz to 20 MHz
Source = PLL1; Qx divider = 2; jitter integration bandwidth =
12 kHz to 20 MHz
2.5 V CMOS INTEGRATED RMS JITTER
25 MHz Output
0.17
ps
ps
ps
Source = 25 MHz Taitien XTAL; jitter integration bandwidth =
12 kHz to 5 MHz
100 MHz Output
400 MHz Output
1.669
1.586
Source = PLL1; Qx divider = 8; jitter integration bandwidth =
12 kHz to 20 MHz
Source = PLL1; Qx divider = 2; jitter integration bandwidth =
12 kHz to 20 MHz
OUT8 TO OUT10 CHANNEL CYCLE TO CYCLE CLOCK JITTER SPECIFICATIONS
Frequency multiplier (×2) at PLL input enabled. Cycle to cycle jitter magnitude varies with respect to the clock edge (rising or falling).
Table 12 indicates jitter for the worst edge (rising or falling). The better edge typically offers a factor of 2 improvement over the tabulated jitter.
Table 12.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVDS CYCLE TO CYCLE JITTER
66.6 MHz Output
Peak-to-peak jitter, 10,000 cycles
43.9
30.3
ps
ps
133.3 MHz Output
1.8 V CMOS CYCLE TO CYCLE JITTER
66.6 MHz Output
Peak-to-peak jitter, 10,000 cycles
Peak-to-peak jitter, 10,000 cycles
35.3
27.4
ps
ps
133.3 MHz Output
3.3 V CMOS CYCLE TO CYCLE JITTER
33.3 MHz Output
83
ps
ps
ps
66.6 MHz Output
44.9
65.4
133.3 MHz Output
Rev. A | Page 13 of 65
AD9576
Data Sheet
LOGIC INPUT PINS CHARACTERISTICS—REF_SEL, RESET, SPx, PPRx
Table 13.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT STATIC CHARACTERISTICS
REF_SEL Pin
Internal 30 kΩ pull-down resistor
Logic 1 Voltage (VIH)
Logic 0 Voltage (VIL)
Logic 1 Current (IIH)
2.11
V
1.0
V
195
µA
VIH = VDD_x; value represents the magnitude
of current draw
Logic 0 Current (IIL)
0.25
µA
VIL = GND; value represents the magnitude
of current draw
RESET Pin
Internal 30 kΩ pull-up resistor
Logic 1 Voltage (VIH)
Logic 0 Voltage (VIL)
Logic 1 Current (IIH)
1.9
V
0.9
V
0.04
µA
VIH = VDD_x; value represents the magnitude
of current draw
Logic 0 Current (IIL)
260
µA
VIL = GND; value represents the magnitude
of current draw
SPx Pins
Logic 1 Voltage (VIH)
Logic 0 Voltage (VIL)
Logic 1 Current (IIH)
VDD_x − 0.5
V
0.28
95
V
µA
VIH = VDD_x; value represents the magnitude
of current draw
Logic 0 Current (IIL)
0.04
µA
VIL = GND; value represents the magnitude
of current draw
RESET TIMING
Pule Width Low
1.25
1.25
ns
ns
RESET Inactive to Start of
Register Programming
PPR0 TO PPR3 PINS EXTERNAL
TERMINATION
Maximum resistor tolerance = 10%
State 0
State 1
State 2
State 3
State 4
State 5
State 6
State 7
820
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Pull-down to GND
Pull-down to GND
Pull-down to GND
Pull-down to GND
Pull-up to VDD_x
1800
3900
8200
820
1800
3900
8200
Pull-up to VDD_x
Pull-up to VDD_x
Pull-up to VDD_x
STATUS OUTPUT PINS CHARACTERISTICS—LD_0, LD_1, REF_SW, REF_STATUS, REF_ACT
Table 14.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT CHARACTERISTICS
Logic 1 Voltage
ILOAD = 1 mA (source or sink)
VDD_x − 0.1
V
V
Logic 0 Voltage
0.03
Rev. A | Page 14 of 65
Data Sheet
AD9576
SERIAL CONTROL PORT SPECIFICATIONS
Serial Port Interface (SPI) Mode
Table 15.
Parameter
CS (INPUT)
Input Voltage
Logic 1
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Input pin
VDD_x − 0.3
V
V
Logic 0
0.71
Input Current
Logic 1
−0.2
−0.3
2
nA
nA
pF
Logic 0
Input Capacitance
SCLK (INPUT) IN SPI MODE
Input Voltage
Logic 1
VDD_x − 0.3
VDD_x − 0.3
VDD_x − 0.1
V
V
Logic 0
0.71
Input Current
Logic 1
−0.7
−0.6
2
nA
nA
pF
Logic 0
Input Capacitance
SDIO (INPUT)
Input Voltage
Logic 1
Pin is bidirectional
V
V
Logic 0
0.71
Input Current
Logic 1
0.7
−0.8
2
nA
nA
pF
Logic 0
Input Capacitance
SDIO (OUTPUT)
Output Voltage
Logic 1
Pin is bidirectional
V
V
Logic 0
0.05
50
TIMING
Clock Rate (SCLK, 1/tSCLK
Pulse Width High
)
MHz
ns
tHIGH
tLOW
tDS
4
Pulse Width Low
2.2
2.5
2.7
ns
SDIO to SCLK Setup
SCLK to SDIO Hold
ns
tDH
tDV
tS
ns
SCLK to Valid SDIO and SDO
CS to SCLK Setup
6.44
ns
0
ns
CS to SCLK Hold
tC
0
ns
CS Minimum Pulse Width High
tPWH
2.7
ns
Rev. A | Page 15 of 65
AD9576
Data Sheet
I2C Mode
Table 16.
Parameter
Symbol Min
0.7 × VDD_x
Typ Max
Unit
Test Conditions/Comments
SDA, SCL VOLTAGE
Input Logic 1
Input Logic 0
Input Current
When inputting data
V
0.3 × VDD_x
V
−10
+10
µA
Input voltage between 0.1 × VDD_x and
0.9 × VDD_x
Hysteresis of Schmitt Trigger Inputs
SDA
0.015 × VDD_x
V
When outputting data
Output Logic 0 Voltage at 3 mA Sink
Current
0.2
V
1
Output Fall Time from VIHMIN to VILMAX
TIMING
20 + 0.1 CB
250
ns
Bus capacitance from 10 pF to 400 pF
All I2C timing values are referred to VIHMIN
(0.3 × VDD) and VILMAX levels (0.7 × VDD)
Clock Rate (SCL, fI2C)
400
kHz
µs
Bus Free Time Between a Stop and
Start Condition
tBUF
1.3
0.6
0.6
Setup Time for a Repeated Start
Condition
tSU; STA
µs
µs
Hold Time (Repeated) Start Condition tHD; STA
After this period, the first clock pulse is
generated
Setup Time for a Stop Condition
Low Period of the SCL Clock
High Period of the SCL Clock
SCL, SDA Rise Time
tSU; STO
tLOW
tHIGH
tR
0.6
1.3
0.6
µs
µs
µs
ns
ns
ns
ns
pF
1
20 + 0.1 CB
300
300
1
SCL, SDA Fall Time
tF
20 + 0.1 CB
Data Setup Time
tSU; DAT
100
0
Data Hold Time
tHD; DAT
1
Capacitive Load for Each Bus Line
CB
400
1 CB is the capacitance of one bus line in picofarads (pF).
Rev. A | Page 16 of 65
Data Sheet
AD9576
ABSOLUTE MAXIMUM RATINGS
Table 17.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
VDD_x to GND
Junction Temperature1
−0.3 V to +3.6 V
150°C
Storage Temperature Range
−65°C to +150°C
Table 18. Thermal Resistance
1 See Table 18 for θJA.
Package Type
θJA
Unit
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
CP-64-171
22.7
°C/W
1 Thermal impedance is based on a 4-layer board in still air in accordance with
a JEDEC JESD51-7 plus JEDEC JESD51-5 2S2P test board and in accordance with
JEDEC JESD51-2 (still air).
ESD CAUTION
Rev. A | Page 17 of 65
AD9576
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 OUT0
REF2
REF2
1
2
3
4
5
6
7
8
9
47 OUT0
46 VDD_OUT01
45 OUT1
44 OUT1
43 OUT2
42 OUT2
41 VDD_OUT23
40 OUT3
REF_SEL
VDD_REFMON
REF_ACT
REF_SW
REF0
AD9576
REF0
VDD_REF0
TOP VIEW
(Not to Scale)
39 OUT3
38 GND
VDD_REF1 10
REF1 11
REF1 12
37 OUT4
CS 13
36 OUT4
SCLK/SCL 14
SDIO/SDA 15
VDD_IO 16
35 VDD_OUT45
34 OUT5
33 OUT5
NOTES
1. THE EXPOSED PAD IS A GROUND CONNECTION ON THE CHIP THAT
MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO
ENSURE PROPER FUNCTIONALITY, HEAT DISSIPATION, NOISE,
AND MECHANICAL STRENGTH BENEFITS.
Figure 4. Pin Configuration
Table 19. Pin Function Descriptions
Input/
Pin No.
Mnemonic
Output Pin Type
Description
1
REF2
Input
Configurable
clock input
Complimentary Reference Clock Input 2. This pin is the complimentary
signal to the input on Pin 2 (REF2). When REF2 is configured as 2.5 V/3.3 V,
dc-coupled, single-ended LVCMOS, leave this pin floating. When REF2 is
configured as 1.8 V, ac-coupled, single-ended LVCMOS, this pin must be ac
grounded via a 100 nF capacitor.
2
3
REF2
Input
Configurable
clock input
Reference Clock Input 2. This clock can serve as the stable clock input to the
reference monitor, as well as an input to PLL1. Its format can be configured
as 2.5 V/3.3 V, dc-coupled, single-ended LVCMOS, or 1.8 V, ac-coupled, single-
ended LVCMOS, differential input (with a complimentary signal on REF2,
Pin 1, or as an XTAL input. The receiver format is power-on configurable via
PPR0 (Pin 24) and is independently configurable via the serial port.
REF_SEL
Input
Input
2.5 V/3.3 V CMOS
control
Reference Clock Select. This pin selects the output clock of the reference
selection mux, which can be either Reference Clock Input 0 or Reference Clock
Input 1 (Logic 0 or Logic 1, respectively). For this pin to function, automatic
reference switching and soft REF_SEL must be disabled (Register 0x082,
Bits[2:1] = 00). This pin has an internal 30 kΩ pull-down resistor.
4
5
VDD_REFMON
REF_ACT
Power
2.5 V or 3.3 V Power Supply.
Output 2.5 V/3.3 V CMOS
Currently Selected, Active Reference Indicator. This status signal represents
the output of the reference selector mux. Logic 0 means that REF0 is the
currently selected reference, Logic 1 means that REF1 is the currently
selected reference. This pin is on the VDD_REFMON power domain.
6
REF_SW
Output 2.5 V/3.3 V CMOS
Reference Switchover Status Indicator. Logic 0 = normal operation, Logic 1
means reference switch in progress. This pin is on the VDD_REFMON power
domain.
Rev. A | Page 18 of 65
Data Sheet
AD9576
Input/
Pin No.
Mnemonic
Output Pin Type
Description
7
REF0
Input
Configurable
clock input
Reference Clock Input 0. This clock is an input to the reference selection
mux. The clock format can be configured as 2.5 V/3.3 V, dc-coupled, single-
ended LVCMOS, or 1.8 V, ac-coupled, single-ended LVCMOS, differential
input (with a complimentary signal on REF0, Pin 8), or as an XTAL input. The
receiver format is power-on configurable via PPR0 (Pin 24) and is independently
configurable via the serial port.
8
REF0
Input
Configurable
clock input
Complimentary Reference Clock Input 0. Complimentary signal to the input
on Pin 7 (REF0). When REF0 is configured as 2.5 V/3.3 V, dc-coupled, single-
ended LVCMOS, leave this pin floating. When REF0 is configured as 1.8 V,
ac-coupled, single-ended LVCMOS, this pin must be ac grounded via a
100 nF capacitor.
9
VDD_REF0
VDD_REF1
REF1
Input
Input
Input
Power
Power
2.5 V or 3.3 V Power Supply. Configure this supply to set the full swing
CMOS logic high level of Reference Input 0, REF0.
10
11
2.5 V or 3.3 V Power Supply. Configure this supply to set the full swing
CMOS logic high level of Reference Input 1, REF1.
Configurable
clock input
Complimentary Reference Clock Input 1. Complimentary signal to the input
on Pin 12 (REF1). When REF1 is configured as 2.5 V/3.3 V, dc-coupled, single-
ended LVCMOS, leave this pin floating. When REF1 is configured as 1.8 V,
ac-coupled, single-ended LVCMOS, this pin must be ac grounded via a
100 nF capacitor.
12
REF1
Input
Configurable
clock output
Reference Clock Input 1. This clock is an input to the reference selection
mux. The clock format can be configured as 2.5 V/3.3 V, dc-coupled, single-
ended LVCMOS, or 1.8 V, ac-coupled, single-ended LVCMOS, differential
input (with a complimentary signal on REF1, Pin 11), or as an XTAL input.
The receiver format is power-on configurable via PPR0 (Pin 24) and is
independently configurable via the serial port.
13
14
CS
Input
Input
2.5 V/3.3 V CMOS
2.5 V/3.3 V CMOS
Chip Select for SPI Serial Communication (Active Low Input). When
programming the device in SPI mode, this pin must be held low, as shown
in Figure 32. The logic high level of this pin is determined by VDD_IO.
Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). This
pin is the data clock for serial programming. The logic high level of this pin
is determined by the VDD_IO pin.
SCLK/SCL
15
16
SDIO/SDA
VDD_IO
Input/
output
2.5 V/3.3 V CMOS
Power
Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO)
or I2C Mode (SDA). The logic high level of this pin is determined by VDD_IO
.
Input
2.5 V or 3.3 V Power Supply. Configure this pin to set the logic high level of
the serial port interface.
17
LD_0
Output 2.5 V/3.3 V CMOS
PLL0 Lock Detector Status. Logic 0 means unlocked; Logic 1 means locked.
2.5 V or 3.3 V Power Supply.
18
VDD_PLL0
LF
Input
Input
Input
Input
Power
Analog
Analog
Power
Control
19
Loop Filter. Connect a 4.7 nF capacitor from this pin to LDO_BYP (Pin 20).
LDO Bypass. Connect a 470 nF capacitor from this pin to ground.
2.5 V or 3.3 V Power Supply.
20
LDO_BYP
VDD_VCO0
SP1, SP0
21
22, 49
Input/
Serial Port Configuration Pins. These pins are latched at power-up and upon
release from reset to configure the serial port as well as to determine
whether a PPR load is to occur. See Table 35 for a complete decode of
configurations. These pins use three-state logic: high, low, and floating.
output
23
24
VDD_M0
PPR0
Input
Input
Power
2.5 V or 3.3 V Power Supply.
Control
Pin Program Reader 0. Connect a resistor to this pin to configure the
reference clock input formats and the PLL1 input source.
25
26
VDD_M1
PPR1
Input
Input
Power
2.5 V or 3.3 V Power Supply.
Control
Pin Program Reader 1. Connect a resistor to this pin to configure the OUT10
frequency, input source, and logic format.
27
28
OUT7
OUT7
Output HSTL, LVDS, 1.8 V
CMOS
Clock Output 7. The power-on format is determined via PPR2 (Pin 32) and
PPR3 (Pin 56). This pin is independently configurable via the serial port.
Output HSTL, LVDS, 1.8 V
CMOS
Complimentary Clock Output 7. This pin is the complimentary signal to the
output on Pin 27 (OUT7).
29
30
VDD_OUT67
OUT6
Input
Power
2.5 V or 3.3 V Power Supply.
Output HSTL, LVDS, 1.8 V
CMOS
Complimentary Clock Output 6. This pin is the complimentary signal to the
output on Pin 31 (OUT6).
Rev. A | Page 19 of 65
AD9576
Data Sheet
Input/
Pin No.
Mnemonic
Output Pin Type
Description
31
OUT6
Output HSTL, LVDS, 1.8 V
CMOS
Clock Output 6. The power-on format is determined via PPR2 (Pin 32) and
PPR3 (Pin 56). This pin is independently configurable via the serial port.
32, 56
33
PPR2, PPR3
OUT5
Input
Control
Pin Program Reader 2 and Pin Program Reader 3. Connect a resistor to
these pins to configure the REF0/REF1 input frequency and OUT0 to OUT9.
Output HSTL, LVDS, 1.8 V
CMOS
Clock Output 5. The power-on format is determined via PPR2 (Pin 32) and
PPR3 (Pin 56). This pin is independently configurable via the serial port.
34
OUT5
Output HSTL, LVDS, 1.8 V
CMOS
Complimentary Clock Output 5. This pin is the complimentary signal to the
output on Pin 33 (OUT5).
35
36
VDD_OUT45
OUT4
Input
Power
2.5 V or 3.3 V Power Supply.
Output HSTL, LVDS, 1.8 V
CMOS
Complimentary Clock Output 4. This pin is the complimentary signal to the
output on Pin 37 (OUT4).
37
OUT4
Output HSTL, LVDS, 1.8 V
CMOS
Clock Output 4. The power-on format is determined via PPR2 (Pin 32) and
PPR3 (Pin 56). This pin is independently configurable via the serial port.
38
39
GND
Input
Ground
Power Supply Common Ground.
OUT3
Output HSTL, LVDS, 1.8 V
CMOS
Clock Output 3. The power-on format is determined via PPR2 (Pin 32) and
PPR3 (Pin 56). This pin is independently configurable via the serial port.
40
OUT3
Output HSTL, LVDS, 1.8 V
CMOS
Complimentary Clock Output 3. This pin is the complimentary signal to the
output on Pin 39 (OUT3).
41
42
VDD_OUT23
OUT2
Input
Power
2.5 V or 3.3 V Power Supply.
Output HSTL, LVDS, 1.8 V
CMOS
Complimentary Clock Output 2. This pin is the complimentary signal to the
output on Pin 43 (OUT2).
43
44
45
OUT2
OUT1
OUT1
Output HSTL, LVDS, 1.8 V
CMOS
Clock Output 2. The power-on format is determined via PPR2 (Pin 32) and
PPR3 (Pin 56). This pin is independently configurable via the serial port.
Output HSTL, LVDS, 1.8 V
CMOS
Clock Output 1. The power-on format is determined via PPR2 (Pin 32) and
PPR3 (Pin 56). This pin is independently configurable via the serial port.
Output HSTL, LVDS, 1.8 V
CMOS
Complimentary Clock Output 1. This pin is the complimentary signal to the
output on Pin 44 (OUT1).
46
47
VDD_OUT01
OUT0
Input
Power
2.5 V or 3.3 V Power Supply.
Output HSTL, LVDS, 1.8 V
CMOS
Complimentary Clock Output 0. This pin is the complimentary signal to the
output on Pin 48 (OUT0).
48
50
OUT0
OUT8
Output HSTL, LVDS, 1.8 V
CMOS
Clock Output 0. The power-on format is determined via PPR2 (Pin 32) and
PPR3 (Pin 56). This pin is independently configurable via the serial port.
Output 2.5 V/3.3 V CMOS,
Clock Output 8. When configured as 2.5 V/3.3 V CMOS, the logic high level
1.8 V CMOS, HSTL, is determined by VDD_OUT89. The power-on format is determined via
LVDS, HCSL
PPR2 (Pin 32) and PPR3 (Pin 56). This pin is independently configurable via
the serial port.
51
OUT8
Output 2.5 V/3.3 V CMOS,
Complimentary Clock Output 8. This pin is the complimentary signal to the
1.8 V CMOS, HSTL, output on Pin 50 (OUT8).
LVDS, HCSL
52
53
VDD_OUT89
OUT9
Input
Power
2.5 V or 3.3 V Power Supply. Configure this supply to set the full swing
CMOS logic high level of Output 8 and Output 9.
Output 2.5 V/3.3 V CMOS,
Complimentary Clock Output 9. This pin is the complimentary signal to the
1.8 V CMOS, HSTL, output on Pin 54 (OUT9).
LVDS, HCSL
54
55
OUT9
Output 2.5 V/3.3 V CMOS,
Clock Output 9. When configured as 2.5 V/3.3 V CMOS, the logic high level
1.8 V CMOS, HSTL, is determined by VDD_OUT89. The power-on format is determined via
LVDS, HCSL
PPR2 (Pin 32) and PPR3 (Pin 56). This pin is independently configurable via
the serial port.
REF_STATUS
Output 2.5 V/3.3 V CMOS
Reference Status Indicator. When the reference monitor is enabled, this pin
indicates if the output of the reference selection mux is determined to be
within the configured tolerance setting. Logic 0 means the reference is within
tolerance; Logic 1 means the reference is outside of tolerance. When the
reference monitor is disabled, this pin indicates the loss of reference (LOR)
status for the requested reference.
57
VDD_OUT10
Input
Power
2.5 V or 3.3 V Power Supply. Configure this supply to set the full swing
CMOS logic high level of Output 10. This pin also serves as the PPRx power
supply.
Rev. A | Page 20 of 65
Data Sheet
AD9576
Input/
Pin No.
Mnemonic
Output Pin Type
Description
58
OUT10
Output
2.5 V/3.3 V CMOS,
1.8 V CMOS, HSTL,
LVDS, HCSL
Clock Output 10. When configured as 2.5 V/3.3 V CMOS, the logic high level is
determined by VDD_OUT10. The power-on format is determined via PPR1
(Pin 26). This pin is independently configurable via the serial port.
59
OUT10
Output 2.5 V/3.3 V CMOS,
Complimentary Clock Output 10. This pin is the complimentary signal to
1.8 V CMOS, HSTL, the output on Pin 58 (OUT10).
LVDS, HCSL
60
61
62
63
VDD_VCO1
VDD_PLL1
LD_1
Input
Input
Power
2.5 V or 3.3 V Power Supply.
Power
2.5 V or 3.3 V Power Supply.
Output 2.5 V/3.3 V CMOS
PLL1 Lock Detector Status. Logic 0 means unlocked; Logic 1 means locked.
RESET
Input
Input
Input
Control
Reset. Logic 0 initializes the device to its default state (see the PPRx Pins
section for details). This pin has an internal 30 kΩ pull-up resistor.
64
VDD_REF2
EPAD
Power
2.5 V or 3.3 V Power Supply. Configure this supply to set the full swing
CMOS logic high level of Reference Input 2, REF2.
Ground
Exposed Pad. The exposed pad is a ground connection on the chip that
must be soldered to the analog ground of the PCB to ensure proper
functionality, heat dissipation, noise, and mechanical strength benefits.
Rev. A | Page 21 of 65
AD9576
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
PHASE NOISE AND VOLTAGE WAVEFORMS
VDD_x = nominal, TA = 25°C. The only enabled output channels are those indicated in the figure captions. The phase noise plots (see Figure 5 to
Figure 9) show the Taitien XO A0145-L-006-3 (noted as XO in the figures) phase noise normalized to the output frequency. The voltage
waveform plots (see Figure 10 to Figure 16) embody ac coupling to the measurement instrument.
AD9576
XO
AD9576
XO
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
Figure 5. Phase Noise (OUT0)—fOUT0 = 644.53125 MHz (HSTL), Fractional
Figure 8. Phase Noise (OUT2)—fOUT2 = 156.25 MHz (HSTL)
AD9576
XO
AD9576
XO
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY OFFSET (Hz)
FREQUENCY OFFSET (Hz)
Figure 6. Phase Noise (OUT3)—fOUT3 = 100 MHz (HSTL), fOUT4 = 125 MHz (HSTL)
Figure 9. Phase Noise (OUT3)—fOUT3 = 125 MHz (HSTL), fOUT4 = 100 MHz (HSTL)
156.25MHz
312.5MHz
AD9576
XO
100
1k
10k
100k
1M
10M
0
5
10
15
20
25
FREQUENCY OFFSET (Hz)
TIME (ns)
Figure 7. Phase Noise (OUT4)—fOUT4 = 312.5 MHz (LVDS)
Figure 10. OUT0 Output Waveform, HSTL (156.25 MHz, 312.5 MHz)
Rev. A | Page 22 of 65
Data Sheet
AD9576
100MHz
400MHz
0
5
10
15
20
25
0
5
10
15
20
25
30
35
40
TIME (ns)
TIME (ns)
Figure 11. OUT8 Output Waveform, HCSL (100 MHz, 400 MHz)
Figure 14. OUT0 Output Waveform, LVDS ( 312.5 MHz)
0
10
20
30
40
50
60
0
20
40
60
80
100
120
140
160
TIME (ns)
TIME (ns)
Figure 12. OUT8 Output Waveform, 1.8 V CMOS (66.67 MHz), 10 pF Load
Figure 15. OUT8 Output Waveform, 3.3 V CMOS (25 MHz), 10 pF Load
0
5
10
15
20
25
30
0
5
10
15
20
25
30
TIME (ns)
TIME (ns)
Figure 13. OUT8 Output Waveform, LVDS (133.3 MHz)
Figure 16. OUT8 Output Waveform, 3.3 V CMOS (133.3 MHz), 10 pF Load
Rev. A | Page 23 of 65
AD9576
Data Sheet
REFERENCE SWITCHING FREQUENCY AND PHASE DISTURBANCE
VDD_x = nominal, TA = 25°C. The only enabled output channels are those indicated in the figure captions. The reference switchover phase
disturbance plots, Figure 17, Figure 18, and Figure 19, each show a collection of output phase variations due to approximately 250 reference
switching events between two references with a frequency offset of approximately 2 ppm. Each reference switch event (initiated by
toggling the REF_SEL pin) occurs at a random phase offset between the two references. The plots demonstrate the tightly controlled
phase disturbance at the output as a result of the reference switching logic seeking the optimal moment to switch references.
0
1
2
3
4
5
6
0
1
2
3
4
5
6
TIME (μs)
TIME (μs)
Figure 19. Reference Smooth Switchover Phase Disturbance for OUT8 at
25 MHz (PPR0 = 3, PPR1 = 0, PPR2 = 0, PPR3 = 3)
Figure 17. Reference Smooth Switchover Frequency Disturbance for OUT0 at
156.25 MHz (PPR0 = 3, PPR1 = 0, PPR2 = 0, PPR3 = 3)
9.0
6.5
4.0
1.5
–1.0
–3.5
–6.0
0
1
2
3
4
5
6
TIME (μs)
Figure 18. Reference Smooth Switchover Phase Disturbance for OUT0 at
156.25 MHz (PPR0 = 3, PPR1 = 0, PPR2 = 0, PPR3 = 3)
Rev. A | Page 24 of 65
Data Sheet
AD9576
TERMINOLOGY
Phase Jitter
Time Jitter
An ideal sine wave has a continuous and even progression of
phase with time from 0° to 360° for each cycle. Actual signals,
however, display a certain amount of variation from ideal phase
progression over time. This phenomenon is called phase jitter.
Although many causes can contribute to phase jitter, one major
cause is random noise, which is character-ized statistically as
Gaussian (normal) in distribution.
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings is seen to vary.
In a square wave, the time jitter is seen as a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or 1 Σ of the
Gaussian distribution.
This phase jitter leads to the energy of the sine wave spreading
out in the frequency domain, producing a continuous power
spectrum. This power spectrum is usually reported as a series of
values whose units are dBc/Hz at a given offset in frequency from
the sine wave (carrier). The value is a ratio (expressed in dB) of
the power contained within a 1 Hz bandwidth with respect to
the power at the carrier frequency. For each measurement, the
offset from the carrier frequency is also given.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured. The
phase noise of any external oscillators or clock sources is sub-
tracted, which makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise.
Phase Noise
When the total power contained within some interval of offset
frequencies (for example, 12 kHz to 20 MHz) is integrated, it is
called the integrated phase noise over that frequency offset interval,
and it can be readily related to the time jitter due to the phase
noise within that offset frequency interval.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable
to the device or subsystem being measured. The time jitter of
any external oscillators or clock sources is subtracted, which
makes it possible to predict the degree to which the device
impacts the total system time jitter when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own time jitter to the total. In many cases, the
time jitter of the external oscillators and clock sources dominates
the system time jitter.
Phase noise has a detrimental effect on error rate performance
by increasing eye closure at the transmitter output and reducing
the jitter tolerance/sensitivity of the receiver.
Rev. A | Page 25 of 65
AD9576
Data Sheet
THEORY OF OPERATION
1.8V CMOS
2.5V/3.3V CMOS
HCSL
AD9576
10
÷Q4
÷Q3
LVDS
HSTL
1.8V CMOS
2.5V/3.3V CMOS
HCSL
LVDS
HSTL
9
8
÷N1
×2
CHARGE
PUMP
VCO1
LPF
REF2
÷R1
0
PLL1
INTEGER-N
1
2
3
1.8V CMOS
LVDS
HSTL
REF_STATUS
÷Q0
REF0/REF1
MONITOR
PLL0
FRACTIONAL-N
÷Q
ZD
÷N0A
REF_SEL
REF_ACT
REF_SW
REF0/REF1
SWITCHOVER
÷N0
4
5
÷M0
1.8V CMOS
LVDS
÷Q0
÷Q1
REF0
REF1
HSTL
×2
CHARGE
PUMP
VCO0
LPF
÷M1
÷R0
6
7
1.8V CMOS
LVDS
HSTL
CONTROL
INTERFACE
PPRx LOGIC
2
(I C/SPI)
Figure 20. Detailed Functional Block Diagram
The AD9576 provides up to 11 output channel clocks (OUT0 to
OUT10). OUT0 to OUT7 are driven by PLL0 exclusively and
are comprised of three subgroups of outputs (OUT0 to OUT3,
OUT4 and OUT5, and OUT6 and OUT7). Each output within a
subgroup is individually configurable, but generates the same
output frequency. These outputs support LVDS, HSTL, or 1.8 V
LVCMOS output formats.
OVERVIEW
Figure 20 shows a block diagram of the AD9576. The AD9576
is a 2.5 V or 3.3 V single-supply, pin programmable, power-on
ready, dual-channel clock that is fully configurable via a serial
port interface (SPI). The two parallel channels consist of a high
performance, fractional-N PLL (PLL0) and a general-purpose,
integer-N PLL (PLL1).
OUT8 and OUT9 have three potential sources: the output of the
PLL1 reference selection mux directly, the output of PLL0, or
the output of PLL1. These outputs are individually configurable,
but must share the same source and, therefore, the same output
frequency. OUT10 is driven by either the output of the PLL1
reference selection mux directly or the output of PLL1. These
three outputs support LVDS, HSTL, HCSL, 1.8 V CMOS, and
2.5 V/3.3 V CMOS (the swing is determined by the supply
level) output formats.
There are a total of three reference inputs (REF0 to REF2) on
the AD9576. Each input receiver provides differential or single-
ended input configurations. REF0 and REF1 drive the reference
switchover multiplexer (mux). The output of this reference switch-
over mux drives the input of PLL0 and an input to the PLL1
reference selection mux. REF2 drives the alternate input of the
PLL1 reference selection mux and serves as monitor clock to
the on-board reference monitor, which monitors the reference
switchover mux output clock frequency. REF2 supports frequencies
of 8 kHz, 10 MHz, 19.44 MHz, 25 MHz, and 38.88 MHz, while
REF0 and REF1 support 8 kHz, 1.544 MHz, 2.048 MHz, and
10 MHz to 325 MHz. However, the PLL1 phase and PFD input
rate is limited to 25 MHz or 50 MHz, so only a subset of allowable
reference input frequencies are valid for use as an input to PLL1.
REFERENCE INPUTS
The AD9576 features a flexible PLL reference input circuit
that provides three operating modes: single-ended input, fully
differential input, or external crystal input. The operating
mode of the REF0, REF1, and REF2 input receivers are
selected and controlled by the scanned state of the PPR0 pin
or by Register 0x080 and Register 0x081 (see Table 45).
Register 0x080 and Register 0x081 allow fully independent
control of the operating mode selection for each reference input.
Rev. A | Page 26 of 65
Data Sheet
AD9576
In single-ended CMOS buffer mode, a 2.5 V or 3.3 V clock
source is connected directly to the positive reference input pin
(for example, REF0). Note that, in single-ended mode, it is best
to connect a 0.1 µF capacitor from the negative input pin (for
bits (Register 0x021, Bits[5:4]) and the REF_STATUS pin. To
enable the reference monitor, the user must set the enable reference
monitor bit (Register 0x083, Bit 7) to Logic 1. Note that the
frequency accuracy of the inactive reference channel is not
monitored.
REF0
example,
) to GND. The CMOS swing of the reference
input is dependent on VDD_x of said reference input supply and
does not exceed VDD_x. The single-ended CMOS receivers are
powered down when their individual power-down bits are set in
Register 0x080 and Register 0x081, or when operating in
differential or external crystal input mode.
Table 20. Reference Monitor Error Window
Frequency Error
Threshold (ppm)
Register 0x083, Bits[1:0] Value
10
00
01
10
11
25
In differential mode, a differential clock driver is connected to
50
REF0
the two reference input pins (for example, REF0 and
).
100
Note that, in differential operating mode, the reference input
pins are internally self biased to allow ac coupling. That is, a
0.1 µF capacitor is connected in series from each output of the
external differential clock driver to the corresponding reference
input pin. This mode also supports a single-ended, 1.8 V CMOS
clock source by connecting the source to the positive reference
input pins (for example, REF0) with the negative reference
Reference monitoring is only supported for two input frequencies,
19.44 MHz and 25 MHz. The user must specify which frequency is
to be monitored by configuring the monitored frequency bit
(Register 0x083, Bit 5). A Logic 0 value indicates that the PLL0
input frequency is 25 MHz, whereas a Logic 1 indicates a frequency
of 19.44 MHz. The reference monitor frequency reference, REF2,
can be one of five frequencies selectable via two bit fields, as
shown in Table 21.
REF0
input pin (for example,
) connected to GND via a 0.1 µF
capacitor. The differential input receivers are powered down
when their individual power-down bits are set in Register 0x080
and Register 0x081, or when operating in single-ended CMOS
or external crystal input mode.
Table 21. REF2 Monitor Frequency Decode
Register 0x083, Register 0x083,
REF2 Input Frequency
8 kHz
Bit 4 Value
Bits[3:2] Value
1
0
0
0
0
Not applicable
External crystal mode is comparable to differential mode,
except a fundamental mode AT cut crystal is connected across
10 MHz
00
01
10
11
19.44 MHz
25 MHz
REF0
the two reference input pins (REF0 and
, for example) and
is powered by an internal maintaining amplifier. The external
crystal receivers are powered down via the individual power down
bits in Register 0x080 and Register 0x081, or when operating in
single-ended or differential input mode. The REF0 and REF1
external crystal receivers are also powered down if they are not
the currently active/requested reference clock for PLL0.
38.88 MHz
After comparing the calculated input frequency ppm error to
the user specified threshold window, the resulting frequency
accuracy is reported on the reference status bits (Register 0x021.
Bits[5:4]) and on the REF_STATUS pin. The values of the reference
status bits and the respective significance are listed in Table 22.
The status indicated on the REF_STATUS pin is the logical OR
of the reference status bits.
The reference input format bits, REF0 format (Register 0x080,
Bits[1:0]), REF1 format (Register 0x080, Bits[5:4]), and REF2
format (Register 0x081, Bits[1:0]) must be set correctly for the
applied input. These bits are set to 00 for 2.5 V and 3.3 V CMOS
inputs, 01 for differential inputs and 1.8 V CMOS inputs, and
10 for XTAL inputs. Setting the reference input format bits
incorrectly for the applied input may cause undesired results. The
input frequency range for the reference inputs is specified in
Table 4.
Table 22. Reference Frequency Monitor Status Decode
Frequency Status
Register 0x021, Bits[5:4] Value
Valid
00
01
10
11
Slow
Fast
Indeterminate Fault
REFERENCE MONITOR
The REF_STATUS pin similarly reports whether the frequency
of the active input is within the user specified threshold window. A
Logic 0 on this pin indicates the selected input reference frequency
is within the tolerance threshold specified by the user, whereas a
Logic 1 indicates the selected input reference frequency is outside
the tolerance threshold specified by the user. Note that the
REF_STATUS pin only specifies whether the selected input
reference frequency is within the user specified tolerance threshold.
If more detailed information regarding the manifestation of the
error is required, refer to the reference status bits.
The AD9576 reference monitor function provides the user a
means to validate the frequency accuracy of the PLL0 active
reference (REF0 or REF1) in real time. When enabled, the
reference monitor uses REF2 as the frequency reference to
continuously test the frequency accuracy of the active reference.
The measured frequency error of the PLL0 active input reference is
compared to a user programmable frequency error threshold.
The result is reported as being either within or outside the user
specified threshold (see Table 20) on both the reference status
Rev. A | Page 27 of 65
AD9576
Data Sheet
In addition to the frequency monitoring function, the reference
monitor also checks for the presence of a clock signal at the REF0,
REF1, and REF2 inputs. The absence of a clock signal results in
an internal LOR indication for that particular clock input. A
Logic 1 LOR status indicates that the reference is not present,or
that the frequency is below approximately 1 MHz. A Logic 0 status
indicates that reference input is detected and the frequency is
greater than 1 MHz. When REF2 is configured as an 8 kHz
reference to be used with the reference monitor, the REF2 LOR
circuitry uses the PLL0 active reference to qualify the presence
and accuracy of the REF2 input clock. Table 23 defines the
REF2 LOR conditions for all valid operating modes.
clock is designated by the state of REF_SEL when the enable
XTAL redundancy switchover bit is set to Logic 1.
In manual reference switchover mode, the user manually
changes the input reference by toggling the state of either the
soft reference select bit (Register 0x082, Bit 0) or the REF_SEL pin
(Pin 3). The control method of manual reference switchover is
determined by the state of the enable soft reference select bit
(Register 0x082, Bit 1), as shown in Table 24.
Table 24. PLL0 Active Reference Selection Source Decode
PLL0 Active Reference Selection
Source
Register 0x082, Bit 1
Value
REF_SEL (Pin 3)
0
1
Table 23. REF2 LOR Status Decode
Register 0x082, Bit 0
REF2 Input
Frequency
REF0/REF1
Frequency
Reg. 0x021, REF2 LOR
Bit 2 Value
Condition
>6.1 kHz
< 6.1 kHz
>4.7 kHz
<4.7 kHz
>1 MHz
When the REF_SEL pin controls manual reference switchover, a
logic signal is supplied to the pin to specify the desired input
reference. A Logic 0 on the REF_SEL pin informs the internal
reference switching logic to make REF0 the active reference
input, whereas a Logic 1 makes REF1 the active reference.
When the soft reference select bit controls manual reference
switchover, setting this bit to a Logic 0 selects REF0 as the active
reference input, whereas setting this bit to a Logic 1 selects REF1
as the active input reference. Note that, with manual switching
enabled, the frequency monitoring function of the reference
monitor (see the Reference Monitor section) may still be used,
but it does not trigger a reference switchover for PLL0.
8 kHz
25 MHz
0
1
0
1
0
1
19.44 MHz
10 MHz, 19.44 MHz,
25 MHz, or 38.88 MHz
Not
applicable
<1 MHz
A LOR condition for a given reference is reported on its respective
status bit in Register 0x021 (see Table 43). Furthermore, when
reference frequency monitoring is disabled, the REF_STATUS pin
logic state indicates the LOR status for the PLL0 requested
reference input.
Both manual and XTAL redundancy reference switchover
modes provide the option of using the smooth switchover
function. The smooth switchover function is enabled by setting
the disable smooth switchover bit (Register 0x082, Bit 3) to
Logic 0. The smooth switchover function waits for a minimal
phase offset to occur between the REF0 and REF1 reference
inputs, prior to physically switching to the newly requested
reference. This functionality ensures a minimal frequency and
phase disturbance on the output clocks associated with the PLL
due to a reference switchover event. Correct operation of the
smooth switchover function requires the input references be
asynchronous and that a LOR fault condition does not occur on
either reference input while the switch is being made. When the
smooth switchover function is disabled (Register 0x082, Bit 3 = 1),
the switch to the new active reference is instantaneous and the
frequency disturbance on the output clocks during reference
switchover may increase.
REFERENCE SWITCHING
The AD9576 provides both manual switchover as well as a
single-shot, automatic XTAL redundancy switchover capability.
The reference switchover mode is specified through the enable
XTAL redundancy switchover bit (Register 0x082, Bit 2). By
default, this bit is Logic 0 and manual reference switching is
enabled. Setting this bit to a Logic 1 enables automatic XTAL
redundancy switchover.
Automatic XTAL redundancy switchover mode can only be
used when the following three conditions are met:
•
•
•
REF0/REF1 are external crystal inputs (Register 0x080,
Bits[5:4] and Register 0x080, Bits[1:0] are both set to 10).
The reference monitoring function is enabled
(Register 0x083, Bit 7 is set to 1).
The REF_SEL pin is held at a static logic state.
The reference switching logic provides information about
which reference channel is the currently active reference, via the
REF_ACT pin (Pin 5) and the active reference bit (Register 0x021,
Bit 3). The REF_ACT pin and the active reference bit are both
Logic 0 when REF0 is the active reference, and are both Logic 1
when REF1 is the active reference. Additionally, the reference
switching logic indicates when the device is in the process of
performing a smooth reference switchover via the REF_SW pin
(Pin 6). The REF_SW pin assumes a Logic 1 state when REF_SEL
changes states and returns to a Logic 0 state when the device
The XTAL redundancy switchover is a single use operation per
device reset, switching from the initial input reference (for example,
REF0) to the alternate input reference (for example, REF1). When
the reference monitor determines the selected input frequency
accuracy is outside of the specified error window, the alternate
input is automatically selected as the new active reference input.
Upon completion of the automatic XTAL redundancy switchover,
the newly selected alternate reference (for example, REF1)
continues to be the input reference source for PLL0, regardless
of the accuracy of the frequency. The initial input reference
Rev. A | Page 28 of 65
Data Sheet
AD9576
completes the reference switchover process. In manual smooth
reference switchover mode, confirm that the device has completed
the requested switch to the desired reference (REF_SW pin =
Logic 0) before initiating a subsequent change of reference request.
Changing the state of the REF_SEL pin or the soft reference
select bit before the internal state machine completes the previous
smooth reference switching process does not result in a
subsequent reference switch.
PLL0 Reference Frequency Scaling
The frequency of the active input reference (REF0 or REF1) is
scalable via the PLL0 doubler enable bit (Register 0x101, Bit 3)
and the R0 divider ratio bits (Register 0x105, Bits[5:0]). This
allows the user to scale the input reference frequency to satisfy
the input range of the PFD. When the PLL0 doubler enable bit
is set to Logic 1, the input frequency to the PFD of PLL0, fPFD0, is
twice the active reference input frequency. When the PLL0
doubler enable bit is set to Logic 0, fPFD0 is a function of the active
reference frequency scaled by the R0 divider ratio bits.
Because the smooth reference switchover function waits for a
minimal phase offset between references prior to making a
switch, if either of the reference inputs are removed completely
and a switchover request is initiated, the internal smooth
switching state machine stalls and the device is unable to switch
references, thereby retaining the currently active reference. If
the current active reference fails, the device loses lock, thereby
necessitating a device reset. If the requested reference fails, the
device retains the currently active reference, but switches to the
requested reference if it becomes available. Note that, as long as
a reference remains absent, the state machine remains stalled.
Only a device reset makes the state machine disregard the initial
request to switch references.
fREF
fPFD0
=
R0
where:
fREF is the frequency of the active reference, REF0 or REF1.
R0 is the value of the R0 divider ratio bits.
When the PLL0 doubler enable bit is set to Logic 1, the
frequency appearing at the input to the PFD of PLL0, fPFD0, is
the active reference frequency multiplied by a factor of two.
fPFD0 = fREF × 2
where fREF is the frequency of the active reference, REF0 or REF1.
PLL0 INTEGER-N/FRACTIONAL-N PLL
Note that, when the ×2 frequency multiplier is in use, the active
reference signal must have a duty cycle close to 50%. Otherwise,
spurious artifacts (harmonics) may propagate through the
signal path and appear at the output of PLL0.
PLL0 is a fractional-N PLL capable of operating in integer
mode. It consists of seven functional elements: a reference
frequency prescalar, a PFD, a charge pump, a loop filter, a VCO,
feedback dividers, and an optional, third-order, Σ-Δ modulator
(SDM) that allows fractional divide ratios. PLL0 provides two
independent reference clock input signals. The device supports
differential, single-ended, and XTAL operation for both reference
clocks. PLL0 provides 10 outputs, segregated into four groups.
Each group has a dedicated channel divider allowing the device
to produce four different output frequencies simultaneously.
Note that PLL0 is capable of several different loop configurations,
with each described in the following sections. Figure 21 shows
the functional block diagram of PLL0.
PLL0 Loop Configurations
PLL0 is capable of three different loop configurations. Loop 0 is the
fractional translation path, Loop 1 accommodates low frequency
reference inputs, and Loop 2 is a zero delay feedback path. The
PLL0 loop configuration is selected by programming the PLL0
loop mode bits (Register 0x101, Bits[2:1]) as shown in Table 25.
Table 25. PLL0 Loop Configuration Decode
Register 0x101,
Bits[2:1] Value
PLL0 Loop Configuration
Loop 0: Fractional-N/Integer-N
Loop 1: Low PFD Frequency
Loop 2: Zero Delay
00
01
10
11
PLL0
FRAC-N/
INT-N
÷Q
ZD
÷N0A
Reserved
÷N0
÷M0
÷M1
ACTIVE
REF
CHARGE
PUMP
×2
VCO0
÷R0
Figure 21. PLL0 Functional Block Diagram
Rev. A | Page 29 of 65
AD9576
Data Sheet
The resulting values to be used as the operating N0 fraction and
N0 modulus values are as follows:
Loop Configuration 0—Fractional-N/Integer-N
LDO_BYP
LF
N0 fraction = scalar × 73 = 69,042 × 73 = 5,040,066
N0 modulus = scalar × 243 = 69,042 × 243 = 16,777,206
The overall frequency translation equation for Loop 0 is
REF0
REF1
REF.
INPUT
OUT0
OUT9
1.8V
CP
LOOP
÷M0,
M1
VCO
FILTER
REF_SEL
÷N0
N0 fraction
N0 modulus
N0
SDM
AD9576: PLL0
f
REF
=
R0
fOUT
where:
Figure 22. PLL0 Loop Configuration 0
MZ QY
The Loop 0 configuration is the only configuration that supports a
fractional-N translation in addition to integer-N translations.
This configuration uses a single feedback divider, N0, with an
integrated Σ-Δ modulator.
fOUT is the frequency at the output driver, OUTx (OUT0 through
OUT9).
fREF is the frequency of the active reference (REF0 or REF1).
MZ is the VCO divider (M0 or M1) that is the input source of QY.
QY is the channel divider (Q0, Q1, Q2, or Q3) associated with
OUTx.
The VCO0 frequency is a function of the PFD input frequency
(see the PLL0 Reference Frequency Scaling section) and the
values programmed into the registers associated with N0, N0
fraction, and N0 modulus.
R0 is the divider value used to scale the input reference
frequency and is an element of the following set: {½, 1, 2 … 63}.
Note the value of ½ is the result of selecting the ×2 reference
multiplier (see the PLL0 Reference Frequency Scaling section).
N0 fraction
N0 modulus
fVCO0 fPFD0 N0
where:
N0 is an element of the set: {NMIN, NMIN + 1, …NMAX} where
NMIN, NMAX are 12 and 255, respectively, for integer-N operation
and NMIN, NMAX are 15 and 252, respectively, for fractional-N
operation.
fVCO0 is the frequency of the VCO.
fPFD0 is the frequency at the input to the PFD.
N0 is an element of the following set: {NMIN, NMIN + 1, …, 255},
where NMIN = 12 for integer-N operation and NMIN = 15 for
fractional-N operation.
N0 fraction is an element of the set: {0, 1, …, 16,777,214}.
N0 modulus is an element of the set: {1, 2, …, 16,777,215} with
the constraint N0 fraction < N0 modulus.
N0 fraction is an element of the following set: {0, 1, …,
16,777,214}.
MZ is the divide value of the VCO divider and is an element of
the set: {2, 3, …, 11}.
N0 modulus is an element of the following set, but with the
constraint of N0 fraction < N0 modulus: {1, 2, …, 16,777,215}.
QY is the divide value of the channel divider and is an element
of the set: {1, 2, …, 64}.
Programming the N0 SDM power-down bit (Register 0x101, Bit 0)
to Logic 1 disables the SDM, making N0 fraction functionally
equivalent to a value of 0, and PLL0 can only be configured as
an integer-N PLL. This is also the case if N0 fraction is program-
med to 0; however, the SDM circuitry is not placed into a low
power state. Integer-N operation yields the best performance in
terms of phase noise, spurs, and jitter.
Loop Configuration 1—Low PFD Frequency
LDO_BYP
LF
REF0
REF1
REF.
INPUT
OUT0
OUT9
1.8V
CP
LOOP
÷M0,
M1
VCO
FILTER
REF_SEL
÷N0A
÷N0
To obtain the best performance in fractional-N operation,
configure the N0 modulus value to the largest possible value as
allowed by the fractional translation being synthesized. For
example, if a 19.44 MHz input is being translated to a 625 MHz
output, the required VCO operating frequency is 2500 MHz.
Using the input doubler, this requires an N divider value of 64 +
73/243. To make the modulus as large as possible, both the
modulus and fraction values must be multiplied by the same
scaling value. The scaling value is calculated as follows:
AD9576: PLL0
Figure 23. PLL0 Loop Configuration 1
The Loop 1 configuration is an integer-N configuration that
uses a cascade of two feedback dividers, N0 and N0A, to operate at
much lower PFD frequencies. In this configuration, the charge
pump current is internally set to a value of 1024 μA, an internal
switch shorts RZERO in the integrated loop filter and automatically
sets the integrated pole capacitor (CPOLE2) to 100 pF. This
particular internal loop filter configuration provides the flexibility
to set the response zero and the first pole frequency of the loop
filter (via an external R-C network) to accommodate a low PFD
rate. Note that Loop 1 configures PLL0 as an integer-N PLL
only. Therefore, to ensure proper device operation, the N0 SDM
2
24 1
modulus
16,777,215
243
Scalar = floor
= floor
= 69,042
Rev. A | Page 30 of 65
Data Sheet
AD9576
power-down bit must be set to Logic 1, or the N0 fraction value
must be set to 0.
Loop Configuration 2—Zero Delay
LDO_BYP
LF
The VCO0 frequency is a function of the PFD input frequency
(see the PLL0 Reference Frequency Scaling section) and the values
programmed into the registers associated with N0 and N0A.
REF0
REF1
REF.
INPUT
OUT0
OUT9
1.8V
CP
LOOP
FILTER
VCO ÷M0
REF_SEL
fVCO0 = fPFD0 × N0 × N0A
÷Q
ZD
The divider value of N0 is set by programming the N0 divider
integer value bits to a value between 12 and 255. N0A is a 12-bit
divider that is set by programming the N0A Divider Ratio[11:0]
bits (Register 0x10E, Bits[7:0] and Register 0x10F, Bits[3:0]) as
shown in Table 26.
AD9576: PLL0
Figure 24. PLL0 Loop Configuration 2
In the Loop 2 configuration, the total feedback division ratio is
a cascade of the VCO divider, M0, and the channel divider, QZD
The channel divider, QZD, operates identically to any other
channel divider configured with M0 as an input clock source;
however, the output of the divider is not routed to an output
driver, but rather to the PLL0 PFD feedback clock input. This
feedback scheme, along with QZD being synchronized with the
other channel dividers (see the Synchronization section) allows
the loop to establish a minimal delay between the rising edges
.
Table 26. N0A Divider Ratio Decode
N0A Divider Ratio[11:0] Value
Divider Operation
Invalid setting
0 to 3
4 to 4095
Divide by this value
The overall frequency translation equation for Loop 1 is as follows:
(
N0 N0A
)
fREF
R0
of the reference input and the output clocks. See the PLL0 VCO
Calibration section for information concerning the impact of
the QZD synchronization on the VCO0 calibration procedure.
fOUT
=
MZ QY
where:
The VCO0 frequency is a function of the PFD input frequency
(see the PLL0 Reference Frequency Scaling section) and the values
fOUT is the frequency at the output driver, OUTx (OUT0 through
OUT9).
programmed into the registers associated with M0 and QZD
.
fREF is the frequency of the active reference (REF0 or REF1).
MZ is the VCO divider (M0 or M1) that is the input source of QY.
QY is the channel divider (Q0, Q1, Q2, or Q3) associated with
OUTx.
fVCO0 = fPFD0 × (M0 × QZD)
M0 is described in detail in the PLL0 VCO Dividers (M0 and
M1) section and QZD is described in detail in the Channel
Dividers section.
R0 is the divider value used to scale the input reference
frequency and is an element of the following set: {½, 1, 2 … 63}.
Note that the value of ½ is the result of selecting the ×2 reference
multiplier (see the PLL0 Reference Frequency Scaling section).
The overall frequency translation equation for Loop 2 is as follows:
M0 QZD
MZ QY
fREF
R0
fOUT
=
N0 is an element of the following set: {12, 13 … 255}.
N0A is an element of the following set: {4, 5 … 4095}.
where:
fOUT is the frequency at the input to the channel dividers, OUTx
(OUT0 through OUT9).
MZ is the divide value of the VCO divider and is an element of
the following set: {2, 3 … 11}.
fREF is the frequency of the active reference (REF0 or REF1).
QZD is the zero delay feedback divider.
QY is the divide value of the channel divider and is an element
of the following set: {1, 2 … 64}.
MZ is the VCO divider (M0 or M1) that is the input source of QY.
QY is the channel divider (Q0, Q1, Q2, or Q3) associated with
OUTx.
R0 is the divider value used to scale the input reference
frequency and is an element of the following set: {½, 1, 2, …,
63}. Note that the value of ½ is the result of selecting the ×2
reference multiplier (see the PLL0 Reference Frequency Scaling
section).
M0 and MZ are divide values of the VCO dividers and are
elements of the following set: {2, 3, …, 11}.
QZD and QY are divide values of the channel divider and are
elements of the following set: {1, 2, …, 64}.
Rev. A | Page 31 of 65
AD9576
Data Sheet
For deterministic phase alignment through a reference
switchover event, configure the output frequency of QZD (and,
therefore, the PLL0 PFD frequency) such that it is equal to the
greatest common denominator (GCD) of all channel divider
output frequencies on the PLL0 synchronization domain and the
reference input.
However, the maximum value for N0 is 255. Therefore, to
calibrate the VCO, use Loop Mode 1, which requires N0 = 50
and N0A = 8. See the PLL0 VCO Calibration section for
detailed information about calibrating in Loop Mode 2 when
M0 × QZD > 255.
Note that using smooth switchover minimizes the phase offset
between reference inputs for a reference switchover event.
Therefore, the use of smooth switching allows deterministic
phase alignment to be maintained through a switchover event
without the need for the reference input divider.
In the following example,
•
•
•
•
•
•
•
f
f
f
f
f
f
f
IN = 25 MHz
OUT0_TO_OUT3 = 125 MHz
OUT4_TO_OUT5 = 312.5 MHz
PLL0 Phase Frequency Detector (PFD) and Charge Pump
OUT6_TO_OUT7 = 625 MHz
The PFD determines the phase difference between the edges of
the reference divider output and the feedback divider output.
The maximum operating frequency of the PFD depends on the
operating mode of the PLL (see Table 6).
OUT8_TO_OUT10 = 25 MHz from the PLL0 active reference input.
PFD0 = GCD (25, 125, 312.5, 625) = 12.5 MHz
VCO0 = 625 MHz × 4 = 2500 MHz
Therefore, R0 = 2 and M0 × QZD = 2500/12.5 = 200. This
requires the following conditions:
The circuit provides two pulse-width modulated output signals:
up and down. These up/down pulses drive the charge pump
circuit. The instantaneous phase error determines the amount
of charge delivered from the charge pump to the loop filter. The
closed-loop of the PLL typically drives the frequency and phase
difference between the two PFD input signals toward zero.
•
•
•
•
•
•
•
•
•
M0 ≥ 4 = ceil(200/64)
M0 = 4
Q
ZD = 50
Q0 = 5
Q1 = 2
The 1.8 V charge pump current is user-programmable in
increments of 4 µA up to 1.02 mA via the PLL0 charge pump
current bits (Register 0x102, Bits[7:0]). The charge pump
current is determined by multiplying the bit field value of the
PLL0 charge pump current bits by 4 µA. For example, the
default setting of 0x8D produces a charge pump current of
141 × 4 µA = 564 µA.
Q1 source = M0
Q2 = 1
Q2 source = M0
N0 = 200
In the following example,
•
•
•
•
•
•
•
f
f
f
f
f
f
f
IN = 25 MHz
PLL0 Loop Filter
OUT0_TO_OUT3 = 156.25 MHz
The loop filter affects the dynamic characteristics of a PLL (for
example, lock time and stability). The AD9576 provides both
internal and external partially integrated loop filter capabilities
for VCO0. The loop filter used is specified by the PLL0 loop
filter bypass bit (Register 0x104, Bit 0). Setting this bit to Logic 0
uses the internal loop filter, whereas Logic 1 uses an external
loop filter for VCO0. For both the external and internal loop
filter, the value of CPOLE2 is fixed internally to 16 pF.
OUT4_TO_OUT5 = 125 MHz
OUT6_TO_OUT7 = 625 MHz
OUT8_TO_OUT10 = 25 MHz from the PLL0 active reference input
PFD0 = GCD (25, 125, 156.25, 625) = 6.25 MHz
VCO0 = 625 MHz × 4 = 2500 MHz
Therefore, R0 = 4 and M0 × QZD = 2500/6.25 = 400. This
requires M0 ≥ 7 = ceil(400/64). M1 must be used to generate all
the required frequencies in this configuration, resulting in the
following settings:
Operating VCO0 with the internal loop filter requires a
single 4.7 nF external capacitor connected between the LF and
LDO_BYP pins. The other loop filter components are internal
and can be programmed through the PLL0 loop filter bits
(Register 0x103, Bits[7:0]). Note PLL0 uses a static charge
pump current; therefore, the nominal bandwidth of 400 kHz
varies slightly as the feedback divide ratio deviates from a value
of 50.
•
•
•
•
•
•
•
•
•
M0 = 8
ZD = 50
Q
Q0 = 2
M1 = 4
Q1 = 5
Q1 source = M1
Q2 = 1
When VCO0 uses the external loop filter, the value of
RPOLE2 is internal and set by the PLL0 loop filter RPOLE2 bits
Q2 source = M1
N0 = 400
(Register 0x103, Bits[7:6]). The remaining components, RZERO
ZERO, and CPOLE1 are external to the AD9576 and are configured
by the user.
,
C
Rev. A | Page 32 of 65
Data Sheet
AD9576
The dual VCO dividers provide flexibility for the output
frequencies. VCO Divider M0 drives the Q0, Q1, Q2, Q3, and
ZD channel output drivers, whereas VCO Divider M1 only
AD9576
INTERNAL
LF
19
660Ω
Q
15kΩ
drives the Q1 and Q2 channel dividers.
3.9nF
16pF
120nF
The VCO dividers, M0 and M1, have a synchronous reset function
that must be exercised after power-up or a change in divide
value to guarantee proper operation. Under normal operation,
there is no need for the user to reset the M0 or M1 dividers
manually because they are automatically reset by the VCO0
calibration process. However, when the user wants to change
the M0 or M1 divider value after the VCO0 calibration, the user
must either reissue a VCO0 calibration (see the PLL0 VCO
Calibration section) or manually reset the VCO dividers by
executing the following sequence:
LDO_BYP
20
Figure 25. 8 kHz PFD PLL0 External Loop Filter
When using an 8 kHz PFD rate, an external loop filter must be
used. Figure 25 shows the recommended external loop filter design
for an 8 kHz PFD rate. With a VCO0 frequency of 2500 MHz
and a charge pump current of 888 μA (Register 0x102, Bits[7:0] =
0xDE), the loop filter has a bandwidth of 520 Hz with 70° of
phase margin.
1. Force a reset on the M0 VCO divider. Set Register 0x120,
PLL0 Internal VCO
Bit 0 = 1.
PLL0 incorporates a low phase noise LC tank VCO0. This VCO
has 256 frequency bands spanning from 2.375 GHz to 2.75 GHz.
A VCO calibration is required to select the appropriate operating
frequency band for the programmed divider configuration (see
the PLL0 VCO Calibration section).
2. Force a reset on the M1 VCO divider. Set Register 0x120,
Bit 4 = 1.
3. Issue an input/output (I/O) update. Write Register 0x00F =
0x01.
4. Clear the M0 VCO divider reset state. Set Register 0x120,
Bit 0 = 0.
VCO0 has an integrated low dropout (LDO) linear voltage
regulator that isolates VCO0 from possible external supply
voltage variations. The regulated LDO voltage appears at the
LDO_BYP pin. To ensure stability, connect a 0.47 μF chip
monolithic ceramic capacitor between this pin and ground.
5. Clear the M1 VCO divider reset state. Set Register 0x120,
Bit 4 = 0.
6. Issue an I/O update. Write Register 0x00F = 0x01.
Note that, if only a single VCO divider value is changed, only
that divider must be reset. However, resetting both dividers
simultaneously ensures synchronization between the respective
downstream dividers.
Note that using the LDO_BYP pin to power an external circuit
may degrade VCO0 performance.
PLL0 VCO Dividers (M0 and M1)
The internal VCO of PLL0 operates in the 2.5 GHz range, which is
too high to clock the output channel dividers directly. The AD9576
has two independent VCO dividers, M0 and M1, used to scale
down the internal VCO frequency to an acceptable range for
the output channel dividers. Both the M0 and M1 dividers are
programmable over the range of 2 to 11 using the M0 divide
ratio and M1 divider ratio bits, Register 0x121, Bits[3:0] and
Register 0x121, Bits[7:4], respectively. The values of these bits
and their corresponding functions are shown in Table 27.
PLL0 VCO Calibration
The AD9576 on-chip VCO0 must be calibrated to ensure
proper operation over process and temperature. Calibration
centers the VCO0 control voltage at the VCO0 frequency
established after PLL0 locks, allowing VCO0 a sufficient
operating range to maintain lock over extremes of temperature
and voltage.
The VCO calibration routine works by comparing the VCO
feedback clock to the reference input clock. This requires that a
valid reference input clock is present at the time of calibration.
Therefore, the LOR status indicator of the PLL0 active reference
input is used to gate the VCO calibration operation so that it
waits for the presence of a reference input clock. Note that, in
Loop Mode 1, the REF0/REF1 frequency may be lower than the
detection threshold of the LOR status indicator, causing the
LOR status to remain Logic 1 even with a fully valid reference.
In this case, the VCO calibration cannot be gated by the PLL0
active reference input LOR status. Therefore, the LOR gating of
the calibration is removed when operating in Loop Mode 1 with
a total feedback divide value equal to or greater than a value of
divide by 512. When these conditions are met, the calibration
still waits for the presence of a reference input clock, but no
assessment of the frequency accuracy of the signal is made prior
to the execution of the calibration.
Table 27. VCO Divider Ratio Decode
M0 or M1 Divider Ratio Bit Field Value
Divider Operation
Power down
0 to 1
2 to 11
12 to 15
Divide by this value
Power down
Rev. A | Page 33 of 65
AD9576
Data Sheet
When a PPR load is executed on power-up, an automatic
calibration sequence is issued following the completion of the
load. Otherwise, a manual VCO0 calibration must be initiated
via the PLL0 calibration bit (Register 0x100, Bit 3). Setting the
PLL0 calibration bit to Logic 1 initiates a calibration of VCO0.
The PLL0 calibration bit is not a self clearing bit. Therefore,
the bit must be reset to Logic 0 before a subsequent manual
calibration can be initiated. The PLL0 calibration in progress
bit (Register 0x020, Bit 2) indicates when a VCO0 calibration is
occurring. A Logic 1 reported on the PLL0 calibration in progress
bit indicates a VCO0 calibration is active, whereas a Logic 0
indicates normal PLL0 operation.
Loop Mode 2 Calibration Considerations
When using the PLL0 Loop 2 feedback configuration, the
VCO0 calibration requires special treatment because the M0
and QZD dividers stop during VCO0 calibration (a result of the
automatic synchronization function imposed during calibration),
which prevents the calibration circuitry from receiving the
required feedback clock edges. Therefore, the calibration
controller detects that Loop 2 is in effect and automatically
switches to the Loop 0 configuration to perform the VCO0
calibration sequence. Upon completion of the calibration
sequence, the calibration controller automatically restores the
Loop 2 configuration. Because the calibration controller uses
the Loop 0 configuration, the N0 divider is necessarily in the
feedback path during the calibration sequence. Therefore, the
user must program the value of the N0 divider before initiating
a calibration sequence in the Loop 2 configuration, where
After a successful calibration, the VCO operates in a condition
with optimal margin to maintain lock in operation across the
entire specified temperature range, which includes margin for a
deviation in the reference input clock carrier up to 200 ppm.
However, if the active reference clock frequency exceeds this
limit, or if the user alters the nominal VCO operating frequency
by reconfiguring the reference scaling section or feedback divider,
the ability for the PLL to maintain lock over temperature may be
compromised. If this occurs, an additional VCO calibration is
necessary. To accomplish this, write the following register
sequence:
N0 = M0 × QZD
That is, N0 must match the product of the M0 divider and the
Q
ZD channel divider. The N0 divider is programmed via the N0
divider integer value bits (Register 0x107, Bits[7:0]).
If M0 × QZD > 255, the N0 feedback divider alone is not large
enough to be used during calibration. To properly calibrate
VCO0, manually force the AD9576 to operate in Loop 1 during
calibration and, following the completion of the calibration,
manually force the AD9576 back to Loop 2. Perform these
actions using the following sequence:
1. Clear the VCO0 calibration bit. Write Register 0x100,
Bit 3 = 0.
2. Issue an I/O update. Write Register 0x00F = 0x01.
3. Initiate a manual VCO0 calibration. Write Register 0x100,
Bit 3 = 1.
5. Clear the VCO0 calibration bit. Write Register 0x100,
Bit 3 = 0.
4. Issue an I/O update. Write Register 0x00F = 0x01.
6. Set Loop Mode 1. Write Register 0x101, Bits[2:1] = 1.
7. Issue an I/O update. Write Register 0x00F = 0x01.
8. Initiate a manual VCO0 calibration. Write Register 0x100,
Bit 3 = 1.
Note that, during the first VCO0 calibration sequence after a
PLL0 reset or chip level reset, the calibration controller holds
the distribution section in sync mode (the channel dividers are
held in reset and the output drivers are static) until the calibration
terminates. Therefore, no output signals appear until the VCO0
calibration sequence terminates, as indicated by a Logic 1 to
Logic 0 transition of the PLL0 calibration in progress bit
(Register 0x020, Bit 2).
9. Issue an I/O update. Write Register 0x00F = 0x01.
10. Wait for the calibration to complete, the poll until
Register 0x020, Bit 2 = 0.
11. Set Loop Mode 2. Write Register 0x101, Bits[2:1] = 2.
12. Issue an I/O update. Write Register 0x00F = 0x01.
The VCO0 calibration process requires approximately 98,500
cycles of the PFD to complete. Therefore, the calibration time
(tVCO_CAL) depends on the input frequency to the PFD (fPFD) as
follows:
Note that, in this case, the calibration feedback path consists of
the cascade of the N0 and N0A dividers. Therefore, the user
must program the N0 and N0A dividers such that
N0 × N0A = M0 × QZD
9.85104
tVCO_CAL
=
fPFD
Rev. A | Page 34 of 65
Data Sheet
AD9576
PLL0 Lock Detect
Note that, when the ×2 frequency multiplier is in use, the active
reference signal must have a duty cycle close to 50%. Otherwise,
spurious artifacts (harmonics) may propagate through the signal
path and appear at the output of PLL1.
The PLL0 lock detector is a frequency detector that evaluates
the frequency difference between the feedback and reference
inputs to the PFD. A lock condition is indicated when the
average difference between the feedback and reference inputs is
less than a magnitude of 16 ppm. The PLL0 lock detect process
requires approximately 65,500 cycles of the PFD to complete.
Therefore, the lock detect time (tLDET) depends on the input
frequency to the PFD (fPFD) as follows:
PLL1 Loop Configuration
The VCO1 frequency is a function of the PFD1 input frequency
and the values programmed into the registers associated with
the N1 feedback divider.
fVCO1 = fPFD1 × N1
6.5104
The divider value of N1 is set by programming the N1 divider
ratio bits (Register 0x201, Bits[7:0]) to a value between 4 and 255.
tLDET
=
fPFD
PLL1 INTEGER-N PLL
The overall frequency translation is as follows:
PLL1 is a fully integrated integer-N PLL consisting of six
functional elements: a reference frequency prescalar, a PFD, a
charge pump, an internal loop filter, a VCO, and a feedback divider.
PLL1 allows two independent reference clock input signals. PLL1
provides up to three outputs segregated into two groups. Each
group has a dedicated channel divider allowing the device to
produce two different output frequencies simultaneously. Figure 26
shows the functional block diagram of PLL1.
fREF
N1
R1 Qx
fOUT
=
where:
fOUT is the frequency at the output driver, OUTx (OUT8, OUT9,
or OUT10).
fREF is the frequency of the active reference (REF0, REF1, or REF2).
Qx is the channel divider (Q3 or Q4) associated with OUTx.
R1 is the divider value used to scale the input reference frequency
and is an element of the following set: {½, 1, 1.5, 2, 3, 4, 6, 8}.
Note the value of ½ is the result of selecting the ×2 reference
multiplier (see the PLL1 Reference Frequency Scaling section).
PLL1
INTEGER-N
÷N1
REF2
×2
CHARGE
PUMP
VCO1
N1 is an element of the following set: {4, 5, …, 255}.
PLL0 ACTIVE
REFERENCE
LPF
÷R1
Qx is the divide value of the channel divider and is an element
of the following set: {1, 2, …, 64}.
Figure 26. PLL1 Block Diagram
PLL1 PFD, Charge Pump, and Loop Filter
PLL1 Reference Frequency Scaling
The PFD determines the phase difference between the edges of
the reference divider output and the feedback divider output.
The circuit provides two pulse-width modulated output signals:
up and down. These up/down pulses drive the charge pump
circuit. The instantaneous phase error determines the amount
of charge delivered from the charge pump to the loop filter. The
closed-loop of the PLL typically drives the frequency and phase
difference between the two PFD input signals towards zero.
The frequency of the active input reference (REF0, REF1, or
REF2) is scalable via the PLL1 doubler enable bit (Register 0x202,
Bit 0) and the R1 divider ratio bits (Register 0x202, Bits[3:1]). This
scaling allows the user to scale the input reference frequency to
satisfy the input range of the PFD. When the PLL1 doubler
enable bit is set to Logic 0, the frequency appearing at the input
to the PFD, fPFD1, is a function of the active reference frequency
scaled by the reference input divider.
The loop filter affects the dynamic characteristics of a PLL (for
example, lock time and stability). PLL1 has a fully integrated
internal loop filter that establishes the loop dynamics for a PFD
frequency between 10 MHz and 50 MHz. The charge pump
current and loop filter components are automatically adjusted
based on the programmed N1 feedback divide value to
maintain a nearly constant loop bandwidth over a range of
feedback dividers values. Table 28 shows the PLL1 closed-loop
bandwidth as a function of the N1 divide value.
fREF
fPFD1
where:
=
R1
fREF is the frequency of the active reference (REF0, REF1, or
REF2).
R1 is the value of the R1 reference input divider value.
When the PLL1 doubler enable bit is set to Logic 1, the frequency
appearing at the input to the PFD, fPFD1, is the active reference
frequency multiplied by a factor of 2.
Table 28. PLL1 Closed-Loop Bandwidth
N1 Divide Value
4 to 23
Nominal Closed Loop Bandwidth (MHz)
fPFD1 = fREF × 2
3.5
1.75
1
where fREF is the frequency of the active reference (REF0, REF1,
24 to 47
or REF2).
48 to 255
Rev. A | Page 35 of 65
AD9576
Data Sheet
PLL1 Internal VCO
of the input clock period. For Output Group 0, if the M0 output
clock is 625 MHz, the LSB of this bit field corresponds to 800 ps
of phase delay and an initial phase offset value of 23 delays the
first edge of the Q0 divider output by 18.4 ns relative to an
initial phase offset value of 0. To guarantee the initial phase
offset of the Qx channel divider, a synchronization command
must be executed on Qx after the corresponding Qx initial
phase bit field is programmed by the user. Refer to the
Synchronization section for additional information regarding
this process.
The PLL1 internal VCO has a frequency range of 750 MHz to
825 MHz and a nominal gain of 750 MHz/V, allowing the PLL to
support 3.125% clock margining for an 800 MHz VCO
frequency and a 25 MHz PFD frequency by updating the
feedback divider on-the-fly.
PLL1 Lock Detect
The PLL1 lock detect is a phase detector that evaluates the
phase difference between the feedback and reference inputs to
PFD1. The lock detector operates at the PFD rate, which is
Each channel divider can be independently powered down
using the respective power-down bits. These bits are the Q0 PD
(Register 0x140, Bit 6), Q1 PD (Register 0x146, Bit 6), Q2 PD
(Register 0x14A, Bit 6), Q3 PD (Register 0x240, Bit 6), and Q4
PD (Register 0x244, Bit 6) bits in the serial register. When the
channel divider power-down bit is set to Logic 1, the respective
channel divider powers down, whereas Logic 0 powers up the
channel divider for normal operation.
fVCO1
fPFD1
=
N1
A lock condition is indicated when the phase error between the
feedback and reference inputs to PFD1 is less than 3.25 ns.
Typically, a lock condition for PLL1 is declared 420 µs after the
RESET
release of
, assuming a valid input clock is available.
OUTPUT DISTRIBUTION
Input Sources
The output distribution is segmented into five groups of outputs
(Output Group 0, Output Group 1, Output Group 2, Output
Group 3, and Output Group 4) with each group having several
output drivers that share a channel divider. The output groups,
corresponding channel dividers, output drivers, and input clock
source(s) are shown in Table 29.
The Q0 and QZD channel dividers are driven solely by the M0
VCO divider output clock. The Q1 and Q2 channel dividers can
be driven by the output clock from either VCO divider, M0 or
M1. The user must select which VCO divider is driving the Q1
and Q2 channel dividers using the Qx source bits (Register 0x147,
Bit 6 for the Q1 source and Register 0x14B, Bit 6 for the Q2 source).
Programming either Qx source bit to Logic 0 selects the M0 output
clock as the input clock for the channel divider, whereas Logic 1
selects the M1 output clock as the channel divider input clock.
Table 29. Distribution Output Groups
Output
Group
Channel
Divider
Output
Driver(s)
Frequency
Source(s)
0
Q0
OUT0, OUT1,
OUT2, OUT3
PLL0 (M0)
The Q3 channel divider can be driven by the output clock from
the M0 VCO divider or the output of PLL1, fVCO1. The user must
select which input is driving the Q3 channel divider using the
Q3 source bit (Register 0x241, Bit 6). Programming this bit to
Logic 0 selects the PLL1 output as the Q3 input, whereas a
Logic 1 selects the M0 output as the Q3 input.
1
2
3
Q1
Q2
Q3
OUT4, OUT5
OUT6, OUT7
OUT8, OUT9
PLL0 (M0 and M1)
PLL0 (M0 and M1)
PLL0 (M0), PLL1
output, PLL1
reference
The Q4 channel divider is driven solely by the output of PLL1, fVCO1
.
4
Q4
OUT10
PLL1 output, PLL1
reference
Synchronization
Channel Dividers
Each channel divider has a sync input that allows the divider to
be placed into a known phase, determined by its initial phase bit
field. When the sync input is Logic 1, the divider is held in reset,
which establishes the initial phase of the divider. When the sync
input is logic low, the divider is in normal operation. Coordinating
the Logic 1 to Logic 0 transition of the sync input of multiple
channel dividers to occur simultaneously results in a deterministic
initial phase alignment between the outputs of said dividers.
Provided the set of synchronized dividers share a common input
clock, the initial phase alignment is repeated at a rate equal to
the GCD between all channel divider outputs.
There are a total of six, 6-bit integer channel dividers: Q0, Q1,
Q2, Q3, Q4, and QZD. The divider ratio is programmable using
the Qx divider ratio bits, Register 0x140, Bits[5:0], Register 0x146,
Bits[5:0], Register 0x14A, Bits[5:0], Register 0x240, Bits[5:0],
Register 0x244, Bits[5:0], and Register 0x110, Bits[5:0] for Q0,
Q1, Q2, Q3, Q4, and QZD, respectively. Each channel divider can
operate in divide ratios of 1 to 64. The default divide ratio for
each channel divider is divide by 4, with the exception of QZD
which has a default value of 1.
,
The initial phase offset for each channel divider is programmable
through the Qx initial phase bit fields: Register 0x141, Bits[5:0],
Register 0x147, Bits[5:0], Register 0x14B, Bits[5:0], Register 0x241,
Bits[5:0], Register 0x245, Bits[5:0], and Register 0x110, Bits[5:0]
for Q0, Q1, Q2, Q3, Q4, and QZD, respectively. The bit fields
each have a programming range of 0 to 63 in units of half cycles
Rev. A | Page 36 of 65
Data Sheet
AD9576
As an example, assume the Q0 output is 50 MHz and the Q1
output is 100 MHz. The outputs have a GCD equal to 50 MHz;
therefore, the initial phase relationship between the Q0 and Q1
channel divider outputs repeats every 20 ns (for example, at a
50 MHz rate).
To manually synchronize a sync domain, the user must
program the associated manual sync bit to a Logic 1 followed by
a Logic 0. The following example shows the required sequence
for the PLL0 synchronization domain:
13. Set the PLL0 sync bit. Write Register 0x100, Bit 2 = 1.
14. Issue an I/O update. Write Register 0x00F = 0x01.
15. Clear the PLL0 sync bit. Write Register 0x100, Bit 2 = 0.
16. Issue an I/O update. Write Register 0x00F = 0x01.
Consider another example: assume that the Q0 output is 50 MHz,
the Q1 output is 100 MHz, and the Q2 output is 125 MHz. The
outputs have a GCD equal to 25 MHz; therefore, the initial
phase relationship between the Q0, Q1, and Q2 channel divider
outputs repeats every 40 ns (for example, at a 25 MHz rate).
Note that the M0 and M1 sync domains (and therefore the PLL0
sync domain) have mask sync bits (see the Register 0x122
description in Table 48). Setting a channel divider mask sync bit
for a particular sync domain precludes said sync domain from
affecting the operation of that channel divider. For example, if
the Q1, Q2, and Q3 source bits are all programmed to Logic 0,
Four synchronization domains exist to facilitate the synch-
ronization of multiple channel dividers. A single synchronization
domain is a grouping of channel dividers in which the sync
inputs of each channel divider are tied to a common control bit.
The channel dividers are grouped based on their selected input
source, and the four domains are as follows:
the M0 sync domain includes the Q0, Q1, Q2, and Q
ZD channel
dividers, the M1 sync domain does not include channel dividers,
and the PLL1 sync domain includes the Q3 and Q4 channel
dividers. Programming the M0 mask sync Q2 (Register 0x122,
Bit 2) to Logic 1 results in the Q2 channel divider being unaffected
by a M0 or PLL0 sync command. Programming the M1 mask
sync Q2 (Register 0x122, Bit 6) to Logic 1 has no functional
impact because Q2 is not a part of the M1 sync domain in this
configuration.
•
M0 sync domain. This domain includes all channel dividers
that are configured to use the M0 VCO divider as the input
clock source.
•
M1 sync domain. This domain includes all channel dividers
that are configured to use the M1 VCO divider as the input
clock source.
•
•
PLL0 sync domain. This domain includes consists of the
aggregate of the M0 and M1 sync domains.
PLL1 sync domain. This domain includes includes all
channel dividers that are configured to use the PLL1
output as the input clock source
Output Driver Sources
The output drivers in Output Group 0, Output Group 1, and
Output Group 2 (see Table 29) are driven by the outputs of their
respective channel divider. For example, OUT4 and OUT5 in
Output Group 1 are driven by the output of the Q1 channel
divider.
Each sync domain has an associated manual sync bit—
Register 0x120, Bit 2, Register 0x120, Bit 6, Register 0x100,
Bit 2, and Register 0x200, Bit 2 for the M0, M1, PLL0, and PLL1
sync domains, respectively. Each manual sync bit allows user
control of the divider sync inputs, but there are also automatically
generated signals that are logically OR’ed with the manual sync
bits of the individual sync domains. The actions that generate
these automatically generated sync signals are described as
follows, for the sync domains they affect:
Output Group 3 or Output Group 4 can be driven by the output
of their respective channel divider or by the PLL1 active input
reference. The user must select which source is driving the outputs
in Output Group 3 and Output Group 4. For Output Group 3,
this is accomplished by programming the OUT89 source bit
(Register 0x241, Bit 7). Programming this bit to Logic 0 selects
the Q3 output as the input for the OUT8/OUT9 output drivers,
whereas a Logic 1 selects the PLL1 active input reference as the
input to the output drivers. Note that, if the PLL1 active input
reference is selected as the source to an output group and the
PLL1 active input reference is configured for a XTAL, the PLL1
active input reference loss of reference signal gates the output
drivers of the output group.
•
•
•
M0 sync domain. Deassertion of the M0 reset bit
(Register 0x120, Bit 0) and deassertion of the M0 power-down
bit (Register 0x120, Bit 1).
M1 sync domain. Deassertion of the M1 reset bit
(Register 0x120, Bit 4) and deassertion of the M1 power-
down bit (Register 0x120, Bit 5).
The input clock source for OUT10 is selected via the OUT10
source bit (Register 0x245, Bit 6). Programming this bit to
Logic 0 selects the output of the Q4 divider as the clock source
for OUT10, whereas a Logic 1 selects the PLL1 active input
reference as the OUT10 clock source.
PLL0 sync domain. Completion of the first VCO0 calibration
routine issued after the deassertion of any chip level reset
or deassertion of the PLL0 reset bit (Register 0x100, Bit 0).
Note that this automatic sync affects both the M0 and M1
sync domains.
•
PLL1 sync domain. Deassertion of the PLL1 reset bit
(Register 0x200, Bit 0).
Note that, if none of the 3-channel output drivers, OUT8,
OUT9, or OUT10, use the PLL1 output as their input, then the
PLL1 power-down signal is automatically asserted, and PLL1 is
powered down.
Rev. A | Page 37 of 65
AD9576
Data Sheet
When OUT8, OUT9, or OUT10 is operating in the CMOS
Output Power-Down
output format, the user must also select the polarity of the
output driver via the OUTx CMOS polarity bits (Register 0x242,
Bits[3:2], Register 0x243, Bits[3:2], and Register 0x246, Bits[3:2]).
For example, the polarity of OUT8 is controlled via the OUT8
CMOS polarity bits (Register 0x242, Bits[3:2]). Table 51
contains a detailed description of the OUTx CMOS polarity bit
fields for OUT8, OUT9, and OUT10.
The eight output drivers, OUT0 through OUT7, have independent
power-down control via the corresponding OUTx PD bits in the
serial register. For example, the OUT0 output driver is powered
down via the OUT0 PD bit (Register 0x142, Bit 2). When the
corresponding OUTx PD bit is set to Logic 1, OUTx is powered
down; otherwise, it is powered on and functionally operational.
The three output drivers, OUT8, OUT9, and OUT10 have
independent power-down control via the corresponding OUTx
enable bits. For example, the OUT8 output driver is powered
down via the OUT8 enable bit (Register 0x242, Bit 0). When the
corresponding driver enable bit is set to Logic 0, the OUTx
output driver is powered down. Likewise, OUTx is powered up
when the corresponding OUTx PD bit is set to Logic 1.
Additionally, when the output format for OUT8, OUT9, or
OUT10 is configured for either LVDS or full swing CMOS, the
driver strength of the output is determined by the OUTx drive
strength bits (Register 0x242, Bit 1, Register 0x243, Bit 1, and
Register 0x246, Bit 1 for OUT8, OUT9, and OUT10, respectively).
When operating in the LVDS output format (OUTx driver
format bit = 010), programming this bit to Logic 0 results in an
output drive strength of 3.5 mA, whereas a Logic 1 produces a
drive strength of 4.5 mA.
Output Driver Format
The OUT0 through OUT7 output channels support HSTL,
LVDS, and 1.8 V CMOS outputs. The user has independent
control of the operating mode of each of the eight output
channels via the OUTx driver format bits in the serial register
(for example, Register 0x142, Bits[1:0] for OUT0). Table 49
contains a detailed description of the OUTx driver format bit
fields for OUT0 through OUT7. The differential resistive load
termination is removed for 1.8 V CMOS outputs. When an
OUT0 through OUT7 driver is configured as 1.8 V CMOS, the
positive and negative pins are in a complimentary phase
relationship (for example, 180° offset).
When operating in the full swing CMOS output format,
programming this bit to Logic 0 results in nominal output drive
strength, whereas a Logic 1 results in low output drive strength
that can be used to minimize coupling effects. The drive strength
bit only applies to the full swing CMOS format. The 1.8 V swing
CMOS output drivers only operate in a low drive strength mode.
PPRx PINS
The AD9576 makes use of four PPRx pins to configure the
device. Internal circuitry scans the PPRx pins for the presence
of resistor terminations and configures the device accordingly.
A PPRx pin scan occurs automatically as part of the power-on
reset sequence (see the Power-On Reset (POR) section) or
Use HSTL format and ac couple the output signal for an
LVPECL-compatible output.
The OUT8, OUT9, and OUT10 output channels also support
HSTL, LVDS, and 1.8 V CMOS outputs as well as HCSL and
full swing CMOS outputs. The user has independent control of the
operating mode of OUT8, OUT9, and OUT10 through the OUTx
driver format bits (Register 0x242, Bits[6:4], Register 0x243,
Bits[6:4], and Register 0x246, Bits[6:4]). Table 51 contains a
detailed description of the OUTx driver format bit fields for
OUT8, OUT9, and OUT10.
RESET
following the assertion of the
pin.
Each PPRx pin controls a specific function or functional block
within the device (see Table 30). The power-on configuration of
a functional block depends on the scanned state of the corre-
sponding PPRx pin. The scan of a PPRx pin identifies one of
eight possible states based on an external pull-up or pull-down
resistor (maximum 10% tolerance) per Table 31.
When OUT8, OUT9, or OUT10 are operating in the CMOS
output format, the user must select the output swing level via
the OUTx CMOS enable full swing bits (Register 0x242, Bit 7,
Register 0x243, Bit 7, and Register 0x246, Bit 7). For example,
OUT8 is controlled via the OUT8 CMOS enable full swing bit
(Register 0x242, Bit 7). When the OUTx CMOS enable full
swing bit is set to Logic 0, the CMOS ouput of the corresponding
driver has a 1.8 V swing. When the OUTx CMOS enable full
swing bit is set to Logic 1, the CMOS swing is determined by
the voltage applied to VDD_OUTx. Only set the OUTx CMOS
enable full swing bits to Logic 1 if the associated output format
is configured as CMOS.
Table 30. PPRx Pin Function Assignments
Mnemonic
Pin No.
Function Assignment
PPR0
24
Input receiver configurations, PLL1
source, and PLL input doubler states
PPR1
26
OUT10 configuration
PPR2, PPR3
32, 56
PLL0 frequency translation and OUT0
to OUT9 configuration
Rev. A | Page 38 of 65
Data Sheet
AD9576
Device programming consists of connecting the appropriate
value programming resistors to the PPRx pins and terminating the
resistors to VDD_x or GND (per Table 31). For example, Figure 27
shows how to program PPR0 to State 3.
For details regarding the device configuration based on the
scanned PPRx states, refer to the description of each PPRx pin
in the following sections.
PPR0—Reference Clock Input Configuration
The PPR0 pin controls the configuration of the reference clock
inputs (REF0, REF1, REF2) and the select line of the PLL1
reference input mux. Table 32 associates each PPR0 state with a
particular reference input configuration and PLL1 source
combination.
Table 31. PPRx State
PPRx State
Resistance
820 Ω
Terminus
GND
GND
GND
GND
VDD
0
1
2
3
4
5
6
7
1.8 kΩ
3.9 kΩ
8.2 kΩ
820 Ω
PPR1—OUT10 Configuration
The PPR1 pin controls the frequency, driver format, and source
of OUT10, which requires the PLL1 reference input, and therefore
REF2, if used, to be 25 MHz. Note that, if REF0/REF1 is configured
to a frequency other than 25 MHz, the PLL1 source must be
configured as REF2. Table 33 associates each PPR1 state with a
particular OUT10 configuration.
1.8 kΩ
3.9 kΩ
8.2 kΩ
VDD
VDD
VDD
AD9576
PPR2 and PPR3—REF0/REF1 Frequency and OUT0 to
OUT9 Configuration
24
PPR0
8.2kΩ
The PPR2 and PPR3 pins control the configuration of the REF0
and REF1 input frequency, PLL0, OUT0 to OUT9 driver format
and frequency, and the OUT8 to OUT9 source. Table 34 associates
each combination of PPR2 and PPR3 states with a particular
predefined frequency translation.
Figure 27. PPRx Programming Resistor Example
Table 32. PPR0—Input Receiver Formats and PLL1 Source
PPR0 State REF0/REF1 Input Configuration REF2 Input Configuration
PLL1 Source
PLL0 active reference
PLL0 active reference
PLL0 active reference
PLL0 active reference
REF2
PLL0 Doubler PLL1 Doubler
0
1
2
3
4
5
6
7
XTAL
2.5 V/3.3 V CMOS
2.5 V/3.3 V CMOS
2.5 V/3.3 V CMOS
2.5 V/3.3 V CMOS
XTAL
Enabled
Enabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
2.5 V/3.3 V CMOS
2.5 V/3.3 V CMOS
Differential/1.8 V LVCMOS
XTAL
2.5 V/3.3 V CMOS
Differential/1.8 V LVCMOS
Differential/1.8 V LVCMOS
2.5 V/3.3 V CMOS
XTAL
REF2
REF2
2.5 V/3.3 V CMOS
REF2
Table 33. PPR1—OUT10 Configuration
PPR1 State
OUT10 Frequency (MHz)
OUT10 Format
2.5 V/3.3 V CMOS
2.5 V/3.3 V CMOS
2.5 V/3.3 V CMOS
2.5 V/3.3 V CMOS
LVDS
OUT10 Source
0
1
2
3
4
5
6
7
25
PLL1 reference
PLL1 output
PLL1 output
PLL1 output
PLL1 output
PLL1 output
PLL1 output
PLL1 output
33.3 (100/3)
50
66.67 (200/3)
100
133.3 (400/3)
200
LVDS
LVDS
400
LVDS
Rev. A | Page 39 of 65
AD9576
Data Sheet
Table 34. PPR2 and PPR3—REF0/REF1 Frequency and OUT0 to OUT9 Configuration1
REF0/REF1
OUT0 to OUT3
OUT4 to OUT5
OUT6 to OUT7
OUT8 to OUT9
PPR2
State
PPR3
State
Frequency
(MHz)
Frequency
(MHz)
Frequency
(MHz)
Frequency
Frequency
(MHz)
Format
N/A
Format
N/A
(MHz)
Disabled
156.25
156.25
100
Format
N/A
Format
N/A
Source
N/A
0
0
0
0
0
1
2
3
25
25
25
25
Disabled
156.25
156.25
156.25
Disabled
156.25
156.25
156.25
Disabled
156.25
156.25
25
HSTL
LVDS
HSTL
HSTL
LVDS
HSTL
HSTL
LVDS
HSTL
HSTL
LVDS
PLL0
PLL0
2.5 V/3.3 V
CMOS
PLL1
source
0
0
0
0
1
1
4
5
6
7
0
1
25
25
25
25
25
25
156.25
156.25
156.25
156.25
156.25
156.25
LVDS
HSTL
HSTL
LVDS
LVDS
HSTL
156.25
125
LVDS
HSTL
HSTL
LVDS
LVDS
HSTL
100
100
100
100
25
HSTL
HSTL
HSTL
HSTL
HSTL
HSTL
25
50
25
25
25
25
2.5 V/3.3 V
CMOS
PLL1
source
2.5 V/3.3 V
CMOS
PLL1
125
2.5 V/3.3 V
CMOS
PLL1
source
125
2.5 V/3.3 V
CMOS
PLL1
source
125
2.5 V/3.3 V
CMOS
PLL1
source
125
25
2.5 V/3.3 V
CMOS
PLL1
source
1
1
1
2
3
4
25
25
25
156.25
156.25
156.25
HSTL
LVDS
LVDS
100
100
100
HSTL
LVDS
LVDS
50
HSTL
HSTL
LVDS
125
125
25
HSTL
HSTL
PLL0
PLL0
50
100
2.5 V/3.3 V
CMOS
PLL1
source
1
1
5
6
25
25
156.25
156.25
HSTL
LVDS
100
100
HSTL
LVDS
25
25
HSTL
HSTL
25
25
2.5 V/3.3 V
CMOS
PLL1
source
2.5 V/3.3 V
CMOS
PLL1
source
1
2
2
7
0
1
25
25
25
156.25
156.25
156.25
HSTL
LVDS
HSTL
100
HSTL
LVDS
HSTL
125
125
125
HSTL
LVDS
HSTL
312.5
312.5
25
HSTL
LVDS
HSTL
PLL0
PLL0
100
312.5
PLL1
source
2
2
25
156.25
LVDS
312.5
LVDS
125
LVDS
25
LVDS
PLL1
source
2
2
2
2
2
3
3
3
3
3
3
4
5
6
7
0
1
2
3
4
25
25
25
25
25
25
25
25
25
25
312.5
312.5
312.5
312.5
312.5
312.5
625
HSTL
LVDS
HSTL
LVDS
HSTL
LVDS
HSTL
HSTL
LVDS
HSTL
100
HSTL
LVDS
HSTL
LVDS
HSTL
LVDS
LVDS
HSTL
LVDS
HSTL
100
HSTL
LVDS
HSTL
LVDS
HSTL
LVDS
LVDS
HSTL
LVDS
HSTL
156.25
156.25
156.25
156.25
156.25
156.25
156.25
125
HSTL
LVDS
HSTL
LVDS
HSTL
LVDS
HSTL
HSTL
LVDS
HSTL
PLL0
PLL0
PLL0
PLL0
PLL0
PLL0
PLL0
PLL0
PLL0
100
100
100
125
100
125
100
156.25
156.25
100
100
100
100
312.5
312.5
312.5
156.25
156.25
156.25
100
125
100
25
PLL1
source
3
5
25
100
LVDS
312.5
LVDS
156.25
LVDS
25
LVDS
PLL1
source
3
3
4
4
4
4
4
6
7
0
1
2
3
4
25
25
25
25
25
25
25
100
100
125
125
125
125
125
HSTL
LVDS
HSTL
LVDS
HSTL
LVDS
HSTL
100
100
125
125
100
100
100
HSTL
LVDS
HSTL
LVDS
HSTL
LVDS
HSTL
100
100
125
125
100
100
25
HSTL
LVDS
HSTL
LVDS
HSTL
LVDS
HSTL
100
HCSL
HCSL
HSTL
LVDS
HSTL
LVDS
HSTL
PLL0
PLL0
PLL0
PLL0
PLL1
PLL1
100
125
125
100/3
100/3
25
PLL1
source
4
5
25
125
LVDS
100
LVDS
25
LVDS
25
LVDS
PLL1
source
4
4
6
7
25
25
25
LVDS
LVDS
25
LVDS
LVDS
125
125
LVDS
HSTL
100
25
HCSL
PLL0
100
100
2.5 V/3.3 V
CMOS
PLL1
source
5
0
25
100
HSTL
100
HSTL
125
HSTL
25
2.5 V/3.3 V
CMOS
PLL1
source
Rev. A | Page 40 of 65
Data Sheet
AD9576
REF0/REF1
OUT0 to OUT3
Frequency
OUT4 to OUT5
Frequency
OUT6 to OUT7
Frequency
OUT8 to OUT9
PPR2
State
PPR3
State
Frequency
(MHz)
Frequency
(MHz)
(MHz)
Format
(MHz)
Format
(MHz)
Format
Format
Source
5
1
25
156.25
HSTL
50
HSTL
125
HSTL
25
2.5 V/3.3 V
CMOS
PLL1
source
5
2
25
156.25
LVDS
50
LVDS
125
LVDS
25
2.5 V/3.3 V
CMOS
PLL1
source
5
3
25
25
25
25
25
25
100
HSTL
LVDS
HSTL
HSTL
LVDS
HSTL
100
100
25
HSTL
LVDS
HSTL
HSTL
LVDS
HSTL
100
100
25
HSTL
LVDS
HSTL
HSTL
LVDS
HSTL
100
100
400
400
400
25
HCSL
HCSL
LVDS
HCSL
HCSL
HSTL
PLL1
PLL1
PLL1
PLL1
PLL1
5
4
100
5
5
25
5
6
156.25
156.25
70.656
50
125
125
70.656
5
62
7
02
50
70.656
PLL1
source
62
62
62
12
22
32
25
25
25
24.576
24.576
HSTL
LVDS
HSTL
24.576
24.576
HSTL
LVDS
HSTL
24.576
24.576
HSTL
LVDS
HSTL
100
100
100
HCSL
HCSL
HCSL
PLL1
PLL1
PLL1
312.5 ×
(33/32)
156.25 ×
(33/32)
156.25 ×
(33/32)
62
42
25
312.5 ×
(33/32)
LVDS
156.25 ×
(33/32)
LVDS
156.25 ×
(33/32)
LVDS
100
HCSL
PLL1
62
62
63
52
62
73
25
148.5
148.5
HSTL
LVDS
148.5
148.5
HSTL
LVDS
HSTL
148.5
148.5
HSTL
LVDS
HSTL
100
100
100
HCSL
HCSL
HCSL
PLL1
PLL1
PLL1
25
19.44
625 × (33/32) HSTL
156.25 ×
(33/32)
156.25 ×
(33/32)
73
03
19.44
625 × (33/32) LVDS
156.25 ×
(33/32)
LVDS
156.25 ×
(33/32)
LVDS
100
HCSL
PLL1
73
73
73
13
23
33
19.44
19.44
30.72
156.25
156.25
156.25
HSTL
LVDS
HSTL
125
125
50
HSTL
LVDS
HSTL
50
HSTL
LVDS
HSTL
100
100
25
LVDS
LVDS
PLL1
PLL1
PLL0
50
125
2.5 V/3.3 V
CMOS
73
43
30.72
156.25
LVDS
50
LVDS
125
LVDS
25
2.5 V/3.3 V
CMOS
PLL0
73
73
7
53
63
7
30.72
156.25
156.25
HSTL
LVDS
125
125
HSTL
LVDS
50
50
HSTL
LVDS
100
100
HCSL
HCSL
PLL1
PLL1
30.72
Reserved
1 N/A means not applicable.
2 Frequency translation requires the PLL0 input doubler to be enabled. Only valid if PPR0 = 0, 1, 4, 5, 6, or 7.
3 PLL1 input must be 25 MHz. Only valid if PPR0 = 4, 5, 6, or 7.
sequence, which results in the configuration of the internal
registers. With a reference signal applied to the input of each
PLL, the VCO0 calibration sequence initiates, while PLL1
immediately begins locking to the reference. Assuming a valid
input reference signal, the PLLs eventually locks to the reference
signal(s), as indicated by assertion of the LD_0 pin and the
LD_1 pin. These lock signals enable the prescale dividers at the
output of each VCO, which starts the output drivers toggling
(that is, those output drivers enabled per the PPRx settings).
POWER-ON RESET (POR)
Applying power to the AD9576 causes an internal power-on
reset (POR) event. A POR event allows the device to initialize to
a known state at power-up by initiating a scan of the PPRx pins
(see the PPRx Pins section).
In general, the AD9576 follows an orderly power-on sequence
beginning with the POR circuit detecting a valid 2.5 V or 3.3 V
supply. This activates the internal LDO regulators. Detection of
valid LDO voltages by the POR circuit triggers a PPRx scan
Rev. A | Page 41 of 65
AD9576
Data Sheet
SERIAL CONTROL PORT
The AD9576 serial control port is a flexible, synchronous serial
communications port that provides a convenient interface to
many industry-standard microcontrollers and microprocessors.
The AD9576 serial control port is compatible with I²C and SPI.
The serial control port allows read/write access to the AD9576
register map.
CS
(chip select) pin is an active low control that gates read
The
CS
and write operations. Assertion (active low) of the
pin initiates
a write or read operation to the AD9576 SPI port. Any number
of data bytes can be transferred in a continuous stream. The
register address is automatically incremented or decremented
based on the setting of the address ascension bit (Register 0x000).
CS
must be deasserted at the end of the last byte transferred,
The AD9576 uses the Analog Devices unified SPI protocol (see
the Analog Devices Serial Control Interface Standard) implement-
ation, but does not support a 4-wire protocol with dedicated input
and output data pins. Rather, only a 3-wire mode with a single,
bidirectional data pin is supported. The SPI port configuration
is programmable via Register 0x000. This register is a part of
the SPI control logic rather than in the register map and is
distinct from the I2C Register 0x000.
CS
thereby ending the stream mode. When
pin goes into a high impedance state.
is high, the SDIO
Implementation Specific Details
The following product specific items are defined in the unified
SPI protocol:
•
•
•
•
Analog Devices unified SPI protocol revision: 1.0
Chip type: 0x5
Although the AD9576 supports both the SPI and I2C serial port
protocols, only one is active following power-up (as determined
by the SP0 and SP1 pins during the start-up sequence). The only
way to change the serial port protocol is to reset (or power cycle)
the device.
Product ID: 0x014F
Physical layer: 3-wire supported and 2.5 V and 3.3 V
operation supported
•
•
•
Optional single-byte instruction mode: not supported
Data link: not used
SPI/I²C PORT SELECTION
Control: not used
Because the AD9576 supports both SPI and I2C protocols, the
active serial port protocol depends on the logic state of the SP0
and SP1 pins at reset or power-on. See Table 35 for the serial
port configuration decode.
Communication Cycle—Instruction Plus Data
The unified SPI protocol consists of a two part communication
cycle. The first part is a 16-bit instruction word that is coincident
with the first 16 SCLK rising edges and a payload. The instruction
word provides the AD9576 serial control port with information
Table 35. SPI/I²C Serial Port Setup
SP1
SP0
SPI/I²C Address
SPI with PPRx load
I²C, 0111001 (0x39)
I²C, 0111010 (0x3A)
I²C, 0111011 (0x3B)
I²C, 0111100 (0x3C)
I²C, 0111101 (0x3D)
I²C, 0111110 (0x3E)
I²C, 0111111 (0x3F)
SPI
W
regarding the payload. The instruction word includes the R/
Floating
Floating
bit that indicates the direction of the payload transfer (that is, a
read or write operation). The instruction word also indicates
the starting register address of the first payload byte.
0
Floating
1
Floating
Floating
0
0
0
1
1
1
Write
0
1
If the instruction word indicates a write operation, the payload
is written into the serial control port buffer of the AD9576. Data
bits are registered on the rising edge of SCLK. Generally, it does
not matter what data is written to blank registers; however, it is
customary to use 0s. Note that the user must verify that all
reserved registers within a specific range have a default value of
0x00; however, Analog Devices makes every effort to avoid
having reserved registers with nonzero default values.
Floating
0
1
SPI SERIAL PORT OPERATION
Pin Descriptions
The SCLK (serial clock) pin serves as the serial shift clock. This
pin is an input. SCLK synchronizes serial control port read and
write operations. The rising edge SCLK registers write data bits,
and the falling edge registers read data bits. The SCLK pin
supports a maximum clock rate of 50 MHz.
Most of the serial port registers are buffered. Therefore, data
written into buffered registers does not take effect immediately.
An additional operation is needed to transfer buffered serial
control port contents to the registers that actually control the
device. This transfer is accomplished with an I/O update operation,
which is performed by writing a Logic 1 to Register 0x00F, Bit 0
(this bit is an autoclearing bit). The user can change as many
register bits as desired before executing an I/O update. The I/O
update operation transfers the buffer register contents to their
active register counterparts.
The SPI port supports only a 3-wire (bidirectional) hardware
configuration. This 3-wire mode uses the SDIO (serial data
input/output) pin for transferring data in both directions. Both
MSB first and LSB first data formats are supported and are
software programmable.
Rev. A | Page 42 of 65
Data Sheet
AD9576
Read
1. Immediately after the LSB first bit(s) is set, subsequent serial
control port operations are LSB first.
If the instruction word indicates a read operation, the next
N × 8 SCLK cycles clock out the data starting from the address
specified in the instruction word. N is the number of data bytes
read. The read back data is driven to the pin on the falling edge
and must be latched on the rising edge of SCLK. Blank registers
are not skipped over during read back.
Address Ascension
If the address ascension bits (Register 0x0000, Bit 5 and Bit 2)
are zero, the serial control port register address decrements
from the specified starting address toward Address 0x0000.
If the address ascension bits (Register 0x0000, Bit 5 and Bit 2)
are one, the serial control port register address increments from
the starting address toward Address 0x7FFF. Reserved addresses
are not skipped during multi-byte input/output operations;
therefore, write the default value to a reserved register and 0s to
unmapped registers. Note that it is more efficient to issue a new
write command than to write the default value to more than
two consecutive reserved (or unmapped) registers.
A read back operation takes data from either the serial control
port buffer registers or the active registers, as determined by
Register 0x001, Bit 5.
SPI Instruction Word (16 Bits)
W
The MSB of the 16-bit instruction word is R/ , which indicates
whether the instruction is a read or a write. The next 15 bits are
the register address (A14 to A0), which indicates the starting
register address of the read/write operation (see Table 37).
Table 36. Streaming Mode (No Addresses Skipped)
SPI MSB/LSB First Transfers
Address Ascension
Increment
Stop Sequence
0x0000 … 0x7FFF
0x7FFF … 0x0000
The AD9576 instruction word and payload can be MSB first or
LSB first. The default for the AD9576 is MSB first. The LSB first
mode can be set by writing a 1 to Register 0x0000, Bit 6 and Bit
Decrement
Table 37. Serial Control Port, 16-Bit Instruction Word
MSB
LSB
I0
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
R/W
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Table 38. Serial Control Port Timing
Parameter
Description
tDS
Setup time between data and the rising edge of SCLK
Hold time between data and the rising edge of SCLK
Period of the clock
tDH
tSCLK
tS
Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle)
Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle)
Minimum period that SCLK should be in a logic high state
tC
tHIGH
tLOW
tDV
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO (see Figure 36)
CS
DON'T CARE
DON'T CARE
SCLK
SDIO
DON'T CARE
DON'T CARE
R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N – 1) DATA
Figure 28. Serial Control Port Write—MSB First, Address Decrement, Two Bytes of Data
Rev. A | Page 43 of 65
AD9576
Data Sheet
tDS
tHIGH
tS
tC
tSCLK
tDH
tLOW
CS
SCLK
SDIO
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
R/W
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
Figure 29. Timing Diagram for Serial Control Port Write—MSB First
CS
SCLK
tDV
SDIO
DATA BIT N
DATA BIT N – 1
Figure 30. Timing Diagram for Serial Control Port Register Read—MSB First
CS
DON'T CARE
DON'T CARE
SCLK
SDIO
DON'T CARE
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA
DON'T CARE
Figure 31. Serial Control Port Write—LSB First, Address Increment, Two Bytes of Data
tS
tC
CS
tSCLK
tHIGH
tLOW
tDS
SCLK
SDIO
tDH
BIT N
BIT N + 1
Figure 32. Timing Diagram for Serial Control Port—Write
The AD9576 I2C port consists of a serial data line (SDA) and a
serial clock line (SCL). In an I2C bus system, the AD9576 is
connected to the serial bus (data bus SDA and clock bus SCL) as
a slave device; that is, no clock is generated by the AD9576. The
AD9576 uses direct 16-bit memory addressing instead of more
common 8-bit memory addressing.
I2C SERIAL PORT OPERATION
The I2C interface is popular because it requires only two pins
and easily supports multiple devices on the same bus. Its main
disadvantage is programming speed, which is 400 kbps maximum.
The AD9576 I2C port design uses the I2C fast mode; however, it
supports both the 100 kHz standard mode and 400 kHz fast mode.
The AD9576 allows up to seven unique slave devices to occupy
the I2C bus. These are accessed via a 7-bit slave address
transmitted as part of an I2C packet. Only the device with a
matching slave address responds to subsequent I2C commands.
Table 35 lists the supported device slave addresses.
The AD9576 does not strictly adhere to every requirement in
the original I2C specification. In particular, specifications such
as slew rate limiting and glitch filtering are not implemented.
Therefore, the AD9576 is I2C-compatible, but may not be fully
I2C compliant.
Rev. A | Page 44 of 65
Data Sheet
AD9576
I2C Bus Characteristics
Data Transfer Process
A summary of the various I2C abbreviations appears in Table 39.
The master initiates data transfer by asserting a start condition,
which indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
Table 39. I2C Bus Abbreviation Definitions
Abbreviation
Definition
Start
The master then sends an 8-bit address byte over the SDA line,
S
W
consisting of a 7-bit slave address (MSB first) plus an R/ bit.
Sr
P
Repeated start
Stop
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 =
write and 1 = read).
A
A
W
R
Acknowledge
No acknowledge
Write
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other
devices on the bus remain idle while the selected device waits
Read
W
for data to be read from or written to it. If the R/ bit is 0, the
The transfer of data is shown in Figure 33. One clock pulse is
generated for each data bit transferred. The data on the SDA
line must be stable during the high period of the clock. The
high or low state of the data line can change only when the
clock signal on the SCL line is low.
master (transmitter) writes to the slave device (receiver). If the
W
R/ bit is 1, the master (receiver) reads from the slave device
(transmitter).
The format for these commands is described in the Data
Transfer Format section.
SDA
Data is then sent over the serial bus in the format of nine clock
pulses, one data byte (eight bits) from either master (write
mode) or slave (read mode) followed by an acknowledge bit
from the receiving device. The number of bytes that can be
transmitted per transfer is unrestricted. In write mode, the first
two data bytes immediately after the slave address byte are the
internal memory (control registers) address bytes, with the high
address byte first. This addressing scheme gives a memory
address of up to 216 − 1 = 65,535. ꢀe data bytes aꢁer these two
memory address bytes are register data written to or read from
the control registers. In read mode, the data bytes after the slave
address byte are register data written to or read from the control
registers.
SCL
DATA LINE
STABLE;
CHANGE
OF DATA
ALLOWED
DATA VALID
Figure 33. Valid Bit Transfer
Start/stop functionality is shown in Figure 33. The start
condition is characterized by a high to low transition on the
SDA line while SCL is high. The master always generates the
start condition to initialize a data transfer. The stop condition is
characterized by a low to high transition on the SDA line while
SCL is high. The master always generates the stop condition to
terminate a data transfer. Every byte on the SDA line must be
eight bits long. Each byte must be followed by an acknowledge
bit; bytes are sent MSB first.
When all the data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts a stop
condition to end data transfer during the clock pulse following
the acknowledge bit for the last data byte from the slave device
(receiver). In read mode, the master device (receiver) receives
the last data byte from the slave device (transmitter) but does
not pull SDA low during the ninth clock pulse. This is known as
a nonacknowledge bit. By receiving the non-acknowledge bit,
the slave device knows that the data transfer is finished and
enters idle mode. The master then takes the data line low
during the low period before the 10th clock pulse, and high
during the 10th clock pulse to assert a stop condition.
The acknowledge bit (A) is the ninth bit attached to any 8-bit
data byte. An acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has been received. It is done by pulling the SDA line low
during the ninth clock pulse after each 8-bit data byte.
A
The no acknowledge bit ( ) is the ninth bit attached to any 8-bit
data byte. A no acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has not been received. It is done by leaving the SDA line
high during the ninth clock pulse after each 8-bit data byte.
After issuing a nonacknowledge bit, the AD9576 I2C state
machine goes into an idle state.
A start condition can be used in place of a stop condition.
Furthermore, a start or stop condition can occur at any time,
and partially transferred bytes are discarded.
Rev. A | Page 45 of 65
AD9576
Data Sheet
SDA
SCL
S
P
START CONDITION
STOP CONDITION
Figure 34. Start and Stop Conditions
MSB
SDA
SCL
ACK FROM
SLAVE RECEIVER
ACK FROM
SLAVE RECEIVER
3 TO 7
8
9
3 TO 7
8
9
10
P
1
2
1
2
S
Figure 35. Acknowledge Bit
MSB
SDA
SCL
ACK FROM
SLAVE RECEIVER
ACK FROM
SLAVE RECEIVER
3 TO 7
8
9
3 TO 7
8
9
10
P
1
2
1
2
S
Figure 36. Data Transfer Process (Master Write Mode, 2-Byte Transfer)
SDA
SCL
ACK FROM
NONACK FROM
MASTER RECEIVER
MASTER RECEIVER
3 TO 7
8
9
3 TO 7
8
9
10
P
1
2
1
2
S
Figure 37. Data Transfer Process (Master Read Mode, 2-Byte Transfer), First Acknowledge From Slave
Rev. A | Page 46 of 65
Data Sheet
AD9576
Data Transfer Format
The write byte format is used to write a register address to the
RAM starting from the specified RAM address.
S
Slave
address
W
A
RAM address high byte
A
RAM address low byte
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
The send byte format is used to set up the register address for subsequent reads.
Slave address RAM address high byte
S
W
A
A
RAM address low byte
A
P
P
The receive byte format is used to read the data byte(s) from RAM starting from the current address.
Slave address RAM Data 0 RAM Data 1
S
R
A
A
A
RAM Data 2
A
The read byte format is the combined format of the send byte and the receive byte.
S
Slave
address
W
A
RAM address
high byte
A
RAM address
low byte
A
Sr Slave
R
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
address
I²C Serial Port Timing
SDA
tLOW
tR
tSU; DAT
tBUF
tHD; STA
tR
tF
tSP
tF
SCL
tSU; STO
tSU; STA
tHD; STA
tHIGH
tHD; DAT
S
Sr
P
S
Figure 38. I²C Serial Port Timing
Table 40. IꢀC Timing Definitions
Parameter
fSCL
Description
Serial clock
tBUF
Bus free time between stop and start conditions
Repeated hold time start condition
Repeated start condition setup time
Stop condition setup time
tHD; STA
tSU; STA
tSU; STO
tHD; DAT
tSU; DAT
tLOW
Data hold time
Data setup time
SCL clock low period
tHIGH
SCL clock high period
tR
Minimum/maximum receive SCL and SDA rise time
Minimum/maximum receive SCL and SDA fall time
tF
tSP
Pulse width of voltage spikes that must be suppressed by the input filter
Rev. A | Page 47 of 65
AD9576
Data Sheet
CONTROL REGISTER MAP
Table 41. Register Summary
Address
Default
(Hex)
Register Name Bit 7 (MSB) Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB) (Hex)
R/W
Serial Port Configuration Registers
0x000
0x001
SPI
Soft reset
Single
LSB first
Address
ascension
Reserved
Reserved
Address
ascension
LSB first
Soft reset
0x00
0x00
R/W
R/W
Configuration A
SPI
Reserved Read buffer
registers
Reset sans
register map
Reserved
Configuration B instruction
0x003
0x004
0x005
0x006
0x00B
0x00C
0x00D
0x00F
Chip type
Reserved
Chip type
0x05
0x4F
0x01
0x11
0x00
0x56
0x04
R
Product ID1
Serial ID[3:0]
Reserved
R
Product ID2
Serial ID[11:4]
R
Revision
Device version
Device revision
R
SPI version
SPI version
Vendor ID[7:0]
Vendor ID[15:8]
R
Vendor ID
R
R
I/O update
Reserved
I/O update 0x00
R/W
Status Indicator Registers
0x020
PLL status
Reserved
PLL0
PLL1 lock
PLL0 lock
detect
0x00
0x00
R
R
calibration in detect
progress
0x021
Reference
Reserved
Reference status
Reserved
Active
reference
REF2 LOR
REF1 LOR
REF0 LOR
Chip Mode Register
0x040 Mode selection
Chip
PLL1
0x02
R/W
power-
down
reference
select
Reference Input Configuration Registers
0x080
Reference
inputs
Reserved
REF1
power-
down
REF1 format
Reserved
REF0 power-
down
REF0 format
0x00
0x00
R/W
R/W
0x081
Reserved
REF2 power-
down
REF2 format
Reference Switchover Registers
0x082
Reference
switchover
Reserved
Disable
smooth
switchover
Enable XTAL
redundancy
switchover
Enable soft Soft
0x00
0x00
R/W
R/W
reference
select
reference
select
0x083
Reference
monitor control reference
monitor
Enable
Reserved Monitored Reference
Reference monitor clock
frequency
Error window
frequency
monitor
8 kHz
operation
PLL0 Configuration Registers
0x100
0x101
0x102
PLL0 controls
Reserved
PLL0
calibration
PLL0 sync
PLL0
power-
down
PLL0 reset 0x00
R/W
R/W
R/W
PLL0
configuration
Reserved
PLL0
doubler
enable
PLL0 loop mode
N0 SDM
power-
down
0x01
0x8D
PLL0 charge
PLL0 charge pump current
pump current
0x103
0x104
PLL0 loop filter
PLL0 RPOLE2 loop filter
PLL0 RZERO loop filter
Reserved
PLL0 CPOLE1 loop filter
PLL0 loop
0xE8
0x00
R/W
R/W
filter
bypass
0x105
0x107
PLL0 input
divider
Reserved
R0 divider ratio
N0 divider integer value
0x01
0x64
R/W
R/W
PLL0 fractional
feedback divider
(integer)
Rev. A | Page 48 of 65
Data Sheet
AD9576
Address
Default
(Hex)
0x108
0x109
0x10A
0x10B
0x10C
0x10D
0x10E
0x10F
0x110
0x111
Register Name Bit 7 (MSB) Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB) (Hex)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PLL0 fractional
feedback divider
(fractional)
N0 divider fractional value
N0 divider fractional value
N0 divider fractional value
N0 divider modulus value
N0 divider modulus value
N0 divider modulus value
N0A Divider Ratio
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
PLL0 fractional
feedback divider
(modulus)
PLL0 cascaded
feedback divider
Reserved
N0A Divider Ratio[11:8]
QZD divider ratio
QZD initial phase
PLL0 zero delay
feedback divider
Reserved
Reserved
PLL0 VCO Dividers Registers
0x120
0x121
0x122
VCO dividers
control
Reserved
M1 sync
M1 power- M1 reset
down
Reserved
M0 sync
M0 power- M0 reset
down
0x20
0x44
0x00
R/W
R/W
R/W
VCO dividers
ratios
M1 divider ratio
M0 divider ratio
VCO dividers
sync mask
Reserved
Reserved
M1 mask M1 mask
sync Q2
M0 mask
sync QZD
M0 mask
sync Q3
M0 mask sync M0 mask
Q2 sync Q1
M0 mask
sync Q0
sync Q1
PLL0 Distribution Registers
0x140
Q0 divider
Q0
Q0 divider ratio
0x03
R/W
power-
down
0x141
0x142
Reserved
Q0 initial phase
0x00
0x00
R/W
R/W
Channel 0
driver config-
uration
Reserved
OUT0 power-
down
OUT0 driver format
OUT1 driver format
OUT2 driver format
OUT3 driver format
0x143
0x144
0x145
0x146
Channel 1
driver config-
uration
Reserved
Reserved
Reserved
OUT1 power-
down
0x00
0x00
0x00
0x03
R/W
R/W
R/W
R/W
Channel 2
driver config-
uration
OUT2 power-
down
Channel 3
driver config-
uration
OUT3 power-
down
Q1 divider
Reserved
Reserved
Q1
power-
down
Q1 divide ratio
0x147
0x148
Q1 source
Q1 initial phase
OUT4 power-
0x00
0x00
R/W
R/W
Channel 4
driver config-
uration
Reserved
Reserved
OUT4 driver format
OUT5 driver format
down
0x149
0x14A
Channel 5
driver config-
uration
OUT5 power-
down
0x00
0x03
R/W
R/W
Q2 Divider
Reserved
Reserved
Q2
power-
down
Q2 divide ratio
0x14B
0x14C
Q2 source
Q2 initial phase
OUT6 power-
0x00
0x00
R/W
R/W
Channel 6
driver config-
uration
Reserved
Reserved
OUT6 driver format
OUT7 driver format
down
0x14D
Channel 7
driver config-
uration
OUT7 power-
down
0x00
R/W
Rev. A | Page 49 of 65
AD9576
Data Sheet
Address
Default
(Hex)
Register Name Bit 7 (MSB) Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB) (Hex)
R/W
PLL1 Configuration Registers
0x200
PLL1 controls
PLL1 sync
PLL1
power-
down
PLL1 reset 0x00
0x10
R/W
0x201
0x202
PLL1 feedback
divider
N1 divider ratio
R/W
R/W
PLL1 input
dividers
Reserved
R1 divider ratio
PLL1
0x01
doubler
enable
PLL1 Distribution Registers
0x240
Q3 divider
Reserved
Q3
Q3 divider ratio
0x83
R/W
power-
down
0x241
0x242
OUT89
source
Q3
source
Q3 initial phase
0x00
0xC1
R/W
R/W
Channel 8
driver config-
uration
OUT8 CMOS
enable full
swing
OUT8 driver format
OUT9 driver format
OUT8 CMOS polarity
OUT8 drive OUT8
strength enable
0x243
0x244
Channel 9
driver config-
uration
OUT9 CMOS
enable full
swing
OUT9 CMOS polarity
Q4 divider ratio
OUT9 drive OUT9
0xC1
0x83
R/W
R/W
strength
enable
Q4 divider
Reserved
Q4
power-
down
0x245
0x246
Reserved
OUT10
source
Q4 initial phase
0x80
0xC1
R/W
R/W
Channel 10
driver
OUT10
CMOS
OUT10 driver format
OUT10 CMOS polarity
OUT10
drive
OUT10
enable
configuration
enable full
swing
strength
Rev. A | Page 50 of 65
Data Sheet
AD9576
CONTROL REGISTER DESCRIPTIONS
SERIAL PORT CONFIGURATION REGISTERS (REGISTER 0x000 TO REGISTER 0x00F)
Table 42. Serial Port Configuration Registers
Address Bits Bit Name
Settings Description
Mirror of Bit 0.
Reset Access
0x000
7
6
5
Soft reset
LSB first
0x0
0x0
0x0
R/W
R/W
R/W
Mirror of Bit 1.
Address
Mirror of Bit 2.
ascension
[4:3] Reserved
Reserved.
0x0
R
2
Address
ascension
This bit determines how the register address pointer is automatically 0x0
changed in a multibyte transfer.
R/W
0
1
Decrement.
Increment.
1
LSB first
This bit determines the bit order for data readback. This bit has no
effect in I2C mode.
0x0
R/W
0
1
Serial data stream starts with the LSB.
Serial data stream starts with the MSB.
0
7
Soft reset
This bit issues a chip level reset. This bit is autoclearing.
0x0
0x0
R/W
R/W
0x001
Single instruction
This bit disables streaming operation. For SPI transfers, this bit forces
each data byte to be preceded by a new instruction.
6
5
Reserved
Reserved.
0x0
0x0
R/W
R/W
Read buffer
registers
This bit specifies the data source for serial port read commands.
[4:3] Reserved
Reserved.
0x0
0x0
R
2
Reset sans
This bit issues a chip level reset, but does not reset register map values.
R/W
register map
0
1
Normal operation.
Chip held in reset.
[1:0] Reserved
[7:4] Reserved
[3:0] Chip type
[7:4] Serial ID[3:0]
Reserved.
0x0
0x0
0x5
R
R
R
R
0x003
0x004
Reserved.
These bits are the unique identifier for the type of device.
These bits are a unique identifier, when combined with chip type, for 0x4
an individual device supporting the Analog Devices serial control
interface standard.
[3:0] Reserved
Reserved.
0xF
R
R
0x005
0x006
[7:0] Serial ID[11:4]
These bits are a unique identifier, when combined with chip type, for 0x1
an individual device supporting the Analog Devices serial control
interface standard.
[7:4] Device version
[3:0] Device revision
[7:0] SPI version
These bits indicate the silicon variant of the device
These bits indicate the silicon revision of the device.
0x1
0x1
0x0
R
R
R
0x00B
0x00C
0x00D
0x00F
These bits indicate the version of the analog devices serial control
interface standard implemented on the device.
[7:0] Vendor ID[7:0]
[7:0] Vendor ID[15:8]
[7:1] Reserved
These bits are the unique vendor ID and are reflective of the Analog
Devices allocated USB vendor ID.
0x56
0x4
R
R
These bits are the unique vendor ID and are reflective of the Analog
Devices allocated USB vendor ID.
Reserved.
0x0
0x0
R
0
I/O update
This bit initiates a transfer of the buffered registers to the active
registers. This is an autoclearing bit.
R/W
Rev. A | Page 51 of 65
AD9576
Data Sheet
STATUS INDICATOR REGISTERS (REGISTER 0x020 TO REGISTER 0x021)
Table 43. Status Indicator Registers
Address Bits Bit Name
0x020 [7:3] Reserved
Settings Description
Reset Access
Reserved.
0x0
0x0
R
R
2
1
0
PLL0 calibration in
progress
This bit indicates the status of the PLL0 VCO calibration.
0
1
PLL normal operation.
VCO calibration active.
PLL1 lock detect status.
Unlocked.
PLL1 lock detect
0x0
0x0
0x0
R
R
0
1
Locked.
PLL0 lock detect
PLL0 lock detect status.
Unlocked.
0
1
Locked.
0x021
[7:6] Reserved
Reserved.
R
R
[5:4] Reference status
PLL0 active reference frequency indicator. If the reference monitor 0x0
is Inactive, this bit field indicates the relationship between the
requested reference input and the currently active reference.
00
11
Agreement.
Disagreement.
If the reference monitor is active, the following settings apply:
00
01
10
11
Valid.
Slow.
Fast.
Indeterminate fault.
3
2
1
0
Active reference
REF2 LOR
PLL0 active reference indicator.
REF0.
0x0
0x0
0x0
0x0
R
R
R
R
0
1
REF1.
Reference status indicator.
Reference present.
Loss of reference.
0
1
REF1 LOR
Reference status indicator.
Reference present.
Loss of reference.
0
1
REF0 LOR
Reference status indicator.
Loss of reference.
1
0
Reference present.
CHIP MODE REGISTER (REGISTER 0x040)
Table 44. Chip Mode Register
Address
Bits
[7:2]
1
Bit Name
Settings
Description
Reset
Access
R
0x040
Reserved
Reserved.
0x0
0x1
Chip power-down
Chip level power-down control.
R/W
0
1
Enabled.
Powered down.
0
PLL1 reference select
This bit determines the PLL1 reference input source.
0x0
R/W
0
1
PLL0 active reference.
REF2.
Rev. A | Page 52 of 65
Data Sheet
AD9576
REFERENCE INPUT CONFIGURATION REGISTERS (REGISTER 0x080 TO REGISTER 0x081)
Table 45. Reference Input Configuration Registers
Address
Bits
7
Bit Name
Settings
Description
Reset
0x0
Access
R
0x080
Reserved
Reserved.
6
REF1 power-down
Input receiver power-down control.
Normal operation.
Powered down.
0x0
R/W
0
1
[5:4]
REF1 format
Input receiver format.
CMOS (VDD_x swing).
AC-coupled differential.
XTAL.
0x0
R/W
00
01
10
11
Reserved.
3
2
Reserved
Reserved.
0x0
0x0
R
REF0 power-down
Input receiver power-down control.
Powered down.
R/W
1
0
Normal operation.
Input receiver format.
CMOS (VDD_x swing).
AC-coupled differential.
XTAL.
[1:0]
REF0 format
0x0
R/W
00
01
10
11
Reserved.
0x081
[7:3]
2
Reserved
Reserved.
0x0
0x0
R
REF2 power-down
Input receiver power-down control.
Powered down.
R/W
1
0
Normal operation.
Input receiver format.
CMOS (VDD_x swing).
AC-coupled differential.
XTAL.
[1:0]
REF2 format
0x0
R/W
00
01
10
11
Reserved.
Rev. A | Page 53 of 65
AD9576
Data Sheet
REFERENCE SWITCHOVER REGISTERS (REGISTER 0x082 TO REGISTER 0x083)
Table 46. Reference Switchover Registers
Address Bits Bit Name
0x082 [7:4] Reserved
Settings Description
Reset Access
Reserved.
0x0
0x0
R
3
Disable smooth
This bit sets the reference switchover mode.
R/W
switchover
0
1
Bounded phase transient.
Immediate.
2
1
Enable XTAL
redundancy switchover
This bit requires the reference monitor to be enabled and both
REF0 and REF1 to be configured as XTAL inputs.
0x0
0x0
R/W
R/W
Enable soft reference
select
This bit establishes the control source of the PLL0 reference
input mux select line. Not applicable when XTAL redundancy
switchover is enabled.
0
1
REF_SEL pin (Pin 3).
Soft reference select (Register 0x082, Bit 0).
0
7
Soft reference select
This bit controls the PLL0 reference input mux select line.
Applicable only when the enable soft reference select = 1.
0x0
R/W
R/W
0
1
REF0 select.
REF1 select.
0x083
Enable reference
monitor
The REF2 input clock serves as the reference monitor frequency 0x0
reference.
6
5
Reserved
Reserved.
0x0
0x0
R
Monitored frequency
This bit determines the frequency being monitored by the
reference monitor.
R/W
0
1
REF0 and REF1 input frequency is 25 MHz.
REF0 and REF1 input frequency is 19.44 MHz.
4
Reference monitor
8 kHz operation
This bit configures the reference monitor for an 8 kHz frequency
reference and overrides the reference monitor clock frequency
bit field (Register 0x083, Bits[3:2]).
0x0
R/W
R/W
[3:2] Reference monitor
clock frequency
These bits designate the reference monitor frequency reference 0x0
carrier.
00
01
10
11
10 MHz.
19.44 MHz.
25 MHz.
38.88 MHz.
[1:0] Error window
These bits set the frequency tolerance for a reference monitor
decision.
0x0
R/W
00
01
10
11
10 ppm.
25 ppm.
50 ppm.
100 ppm.
Rev. A | Page 54 of 65
Data Sheet
AD9576
PLL0 CONFIGURATION REGISTERS (REGISTER 0x100 TO REGISTER 0x111)
Table 47. PLL0 Configuration Registers
Address Bits Bit Name
0x100 [7:4] Reserved
Settings
Description
Reset Access
Reserved.
0x0
0x0
R
3
PLL0 calibration
This bit issues a manual VCO calibration on a low to high
transition.
R/W
2
PLL0 sync
This bit issues a distribution sync command to the dividers
driven by PLL0.
0x0
R/W
0
1
Normal operation.
Dividers held in sync.
PLL0 power-down control.
Normal operation.
1
0
PLL0 power-down
PLL0 reset
0x0
0x0
R/W
R/W
0
1
Powered down.
PLL0 reset control.
0
1
Normal operation.
Reset.
0x101
[7:4] Reserved
Reserved.
0x0
0x0
R
3
PLL0 doubler enable
This bit selects the PLL0 input divider path used.
R0 divider output.
R/W
0
1
×2.
[2:1] PLL0 loop mode
These bits select the PLL0 feedback path.
Loop Mode 0 (single feedback divider).
Loop Mode 1 (cascaded feedback dividers).
Loop Mode 2 (fixed delay divider).
Reserved.
0x0
0x1
R/W
R/W
00
01
10
11
0
N0 SDM power-down
N0 SDM power-down control
Normal operation.
0
1
Powered down.
0x102
0x103
[7:0] PLL0 charge pump
current
These bits control the magnitude of the PLL0 charge pump 0x8D
current.
R/W
R/W
Total current (µA) = 4 × the bit field value.
[7:6] PLL0 RPOLE2 loop filter
Internal loop filter Pole 2 resistor setting.
0x3
00
01
10
11
2000 Ω.
666 Ω.
400 Ω.
285 Ω.
[5:3] PLL0 RZERO loop filter
Internal loop filter zero resistor setting.
0x5
R/W
000
001
010
011
100
101
110
111
1500 Ω.
1875 Ω.
2250 Ω.
2650 Ω.
3000 Ω.
3375 Ω.
3750 Ω.
4125 Ω.
[2:0] PLL0 CPOLE1 loop filter
Internal loop filter Pole 1 capacitor setting.
0x0
R/W
000
001
010
011
100
101
110
111
2 pF.
8 pF.
42 pF.
48 pF.
82 pF.
88 pF.
122 pF.
128 pF.
Rev. A | Page 55 of 65
AD9576
Data Sheet
Address Bits Bit Name
Settings
Description
Reset Access
0x104
[7:1] Reserved
Reserved.
0x0
0x0
0x0
0x1
R
0
PLL0 loop filter bypass
This bit bypasses the internal loop filter.
Reserved.
R/W
R
0x105
[7:6] Reserved
[5:0] R0 divider ratio
PLL0 reference input divide ratio.
Reserved.
R/W
0
1 to 63
Divide ratio = bit field value.
0x107
[7:0] N0 divider integer value
These bits set the operating divide ratio. Divide ratio = bit
field value.
0x64
R/W
0 to 11
Invalid.
12 to 14
15 to 252
Valid if the SDM is disabled.
Valid.
253 to 255 Valid if the SDM is disabled.
These bits set the SDM fractional value, Bits[7:0].
0x108
0x109
0x10A
0x10B
[7:0] N0 divider fractional value
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
[7:0]
These bits set the SDM fractional value, Bits[15:8].
These bits set the SDM fractional value, Bits[23:16].
[7:0]
[7:0] N0 divider modulus value
These bits set the SDM modulus value, Bits[7:0]. These bits
must be greater than fractional value.
0x10C
0x10D
0x10E
[7:0]
These bits set the SDM modulus value, Bits[15:8]. These bits 0x0
must be greater than fractional value.
R/W
R/W
R/W
[7:0]
These bits set the SDM modulus value, Bits[23:16]. These
bits must be greater than fractional value.
0x0
[7:0] N0A Divider Ratio[7:0]
These bits set the operating divide ratio. Divide ratio = bit
field value.
0x0
0 to 3
Invalid.
Valid.
4 to 4095
0x10F
[7:4] Reserved
Reserved.
0x0
0x0
R
[3:0] N0A Divider Ratio[11:8]
These bits set the operating divide ratio. Divide ratio = bit
field value.
R/W
0 to 3
Invalid.
4 to 4095
Valid.
0x110
0x111
[7:6] Reserved
Reserved.
0x0
0x0
R
[5:0] QZD divider ratio
PLL0 fixed delay feedback divider ratio.
Divide ratio = bit field value + 1.
Reserved.
R/W
[7:6] Reserved
0x0
0x0
R
[5:0] QZD initial phase
PLL0 fixed delay feedback divider static phase offset.
Phase offset in units of half cycles of the input clock.
R/W
Rev. A | Page 56 of 65
Data Sheet
AD9576
PLL0 VCO DIVIDERS REGISTERS (REGISTER 0x120 TO REGISTER 0x122)
Table 48. PLL0 VCO Dividers Registers
Address Bits Bit Name
Settings Description
Reset Access
0x120
7
6
Reserved
M1 sync
Reserved.
0x0
0x0
R
This bit issues a distribution sync command to the dividers
R/W
driven by M1.
0
1
Normal operation.
Dividers held in reset.
Divider power-down control.
Normal operation.
Powered down.
5
4
M1 power-down
M1 reset
0x1
0x0
R/W
R/W
0
1
Divider reset control
Normal operation.
Divider held in reset.
Reserved.
0
1
3
2
Reserved
M0 sync
0x0
0x0
R
This bit issues a distribution sync command to the dividers
driven by M0.
R/W
0
1
Normal operation.
Dividers held in reset.
1
0
M0 power-down
M0 reset
Divider power-down control.
Normal operation.
0x0
0x0
0x4
R/W
R/W
R/W
0
1
Powered down.
Divider reset control
0
1
Normal operation.
Divider held in reset.
0x121
[7:4] M1 divider ratio
[3:0] M0 divide ratio
Sets operating divide ratio.
0 to 1
Powered down.
2 to 11
12 to 15
Divide = bit field value.
Powered down.
These bits set the operating divide ratio.
Powered down.
0x4
R/W
0 to 1
2 to 11
12 to 15
Divide = bit field value.
Powered down.
0x122
7
6
5
4
3
2
1
0
Reserved
Reserved.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R
M1 mask sync Q2
M1 mask sync Q1
M0 mask sync QZD
M0 mask sync Q3
M0 mask sync Q2
M0 mask sync Q1
M0 mask sync Q0
This bit sets the Divider Q2 ignore and M1 sync signal flag.
This bit sets the Divider Q1 ignore and M1 sync signal flag.
This bit sets the Divider QZD ignore and M0 sync signal flag.
This bit sets the Divider Q3 ignore and M0 sync signal flag.
This bit sets the Divider Q2 ignore and M0 sync signal flag.
This bit sets the Divider Q1 ignore and M0 sync signal flag.
This bit sets the Divider Q0 ignore and M0 sync signal flag.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. A | Page 57 of 65
AD9576
Data Sheet
PLL0 DISTRIBUTION REGISTERS (REGISTER 0x140 TO REGISTER 0x14D)
Table 49. PLL0 Distribution Registers
Address Bits Bit Name
Settings Description
Reset Access
0x140
7
6
Reserved
Reserved.
0x0
0x0
R
Q0 power-down
Divider power-down control.
R/W
0
1
Normal operation.
Powered down.
[5:0] Q0 divider ratio
[7:6] Reserved
These bits set the operating divide ratio. Divide ratio = bit field value + 1. 0x3
R/W
R
0x141
0x142
Reserved.
0x0
0x0
[5:0] Q0 initial phase
These bits set the divider static phase offset. The phase offset is in
units of half cycles of the input clock.
R/W
[7:3] Reserved
Reserved.
0x0
0x0
R
2
OUT0 power-down
Driver power-down control.
Normal operation.
Powered down.
R/W
0
1
[1:0] OUT0 driver format
These bits select the driver format of OUT0.
LVDS, 3.5 mA.
0x0
R/W
00
01
10
11
LVDS, 4.2 mA.
HSTL, 8 mA.
1.8 V CMOS.
0x143
0x144
0x145
0x146
[7:3] Reserved
OUT1 power-down
Reserved.
0x0
0x0
R
2
Driver power-down control.
Normal operation.
Powered down.
R/W
0
1
[1:0] OUT1 driver format
These bits select the driver format of OUT1.
LVDS, 3.5 mA.
0x0
R/W
00
01
10
11
LVDS, 4.2 mA.
HSTL, 8 mA.
1.8 V CMOS.
[7:3] Reserved
OUT2 power-down
Reserved.
0x0
0x0
R
2
Driver power-down control.
Normal operation.
Powered down.
R/W
0
1
[1:0] OUT2 driver format
These bits select the driver format of OUT2.
LVDS, 3.5 mA.
0x0
R/W
00
01
10
11
LVDS, 4.2 mA.
HSTL, 8 mA.
1.8 V CMOS.
[7:3] Reserved
OUT3 power-down
Reserved.
0x0
0x0
R
2
Driver power-down control.
Normal operation.
Powered down.
R/W
0
1
[1:0] OUT3 driver format
These bits select the driver format of OUT3.
LVDS 3.5 mA.
0x0
R/W
00
01
10
11
LVDS 4.2 mA.
HSTL 8 mA.
1.8 V CMOS.
7
6
Reserved
Reserved.
0x0
0x0
R
Q1 power-down
Divider power-down control.
Normal operation.
Powered down.
R/W
0
1
[5:0] Q1 divide ratio
These bits set the operating divide ratio. Divide ratio = bit field value + 1. 0x3
R/W
Rev. A | Page 58 of 65
Data Sheet
AD9576
Address Bits Bit Name
Settings Description
Reset Access
0x147
7
6
Reserved
Q1 source
Reserved.
0x0
0x0
R
This bit selects the divider input clock.
M0 output.
R/W
0
1
M1 output.
[5:0] Q1 initial phase
[7:3] Reserved
These bits set the divider static phase offset. The phase offset is in
units of half cycles of the input clock.
0x0
R/W
0x148
Reserved.
0x0
0x0
R
2
OUT4 power-down
Driver power-down control.
Normal operation.
Powered down.
R/W
0
1
[1:0] OUT4 driver format
These bits select the driver format of OUT4.
LVDS, 3.5 mA.
0x0
R/W
00
01
10
11
LVDS, 4.2 mA.
HSTL, 8 mA.
1.8 V CMOS.
0x149
[7:3] Reserved
OUT5 power-down
Reserved.
0x0
0x0
R
2
Driver power-down control.
Normal operation.
Powered down.
R/W
0
1
[1:0] OUT5 driver format
These bits select the driver format of OUT5.
LVDS, 3.5 mA.
0x0
R/W
00
01
10
11
LVDS, 4.2 mA.
HSTL, 8 mA.
1.8 V CMOS.
0x14A
0x14B
7
6
Reserved
Reserved.
0x0
0x0
R
Q2 power-down
Divider power-down control.
Normal operation.
Powered down.
R/W
0
1
[5:0] Q2 divide ratio
These bits set the operating divide ratio. Divide ratio = bit field value + 1. 0x3
R/W
R
7
6
Reserved
Q2 source
Reserved.
0x0
0x0
This bit selects the divider input clock.
M0 output.
R/W
0
1
M1 output.
[5:0] Q2 initial phase
[7:3] Reserved
These bits set the divider static phase offset. The phase offset is in
units of half cycles of the input clock.
0x0
R/W
0x14C
Reserved.
0x0
0x0
R
2
OUT6 power-down
Driver power-down control.
Normal operation.
Powered down.
R/W
0
1
[1:0] OUT6 driver format
These bits select the driver format of OUT6.
LVDS, 3.5 mA.
0x0
R/W
00
01
10
11
LVDS, 4.2 mA.
HSTL, 8 mA.
1.8 V CMOS.
0x14D
[7:3] Reserved
OUT7 power-down
Reserved.
0x0
0x0
R
2
Driver power-down control.
Normal operation.
Powered down.
R/W
0
1
[1:0] OUT7 driver format
These bits select the driver format of OUT7.
LVDS, 3.5 mA.
0x0
R/W
00
01
10
11
LVDS, 4.2 mA.
HSTL, 8 mA.
1.8 V CMOS.
Rev. A | Page 59 of 65
AD9576
Data Sheet
PLL1 CONFIGURATION REGISTERS (REGISTER 0x200 TO REGISTER 0x202)
Table 50. PLL1 Configuration Registers
Address Bits Bit Name
Settings Description
Reset Access
0x200
[7:3] Reserved
Reserved.
0x0
0x0
R
2
1
0
PLL1 sync
Issues a distribution sync command to dividers driven by PLL1.
R/W
0
1
Normal operation.
Dividers held in sync.
PLL1 power-down
PLL1 reset
PLL power-down control.
0x0
R/W
R/W
R/W
0
1
Normal operation.
Power down.
PLL reset control.
0x0
0
1
Normal operation.
PLL1 held in reset.
0x201
0x202
[7:0] N1 divider ratio
These bits set the operating divide ratio. Divide value = bit field value.
0x10
0 to 3
Invalid values.
4 to 255
Valid values.
[7:4] Reserved
Reserved.
0x0
0x0
R
[3:1] R1 divider ratio
PLL1 reference input divider.
R/W
0
Power down.
1
÷1.
10
÷1.5.
11
÷2.
100
101
110
111
÷3.
÷4.
÷6.
÷8.
0
PLL1 doubler enable
This bit selects the PLL1 input divider path used.
0x1
R/W
0
1
R1 divider output.
×2.
PLL1 DISTRIBUTION REGISTERS (REGISTER 0x240 TO REGISTER 0x246)
Table 51. PLL1 Distribution Registers
Address Bits Bit Name
Settings Description
Reserved. Always configure this bit to the default value.
Reset Access
0x240
7
6
Reserved
0x1
0x0
R/W
R/W
Q3 power-down
Divider power-down control.
Normal operation.
0
1
Powered down.
[5:0] Q3 divider ratio
These bits set the operating divide ratio. Divide ratio = bit field
value + 1.
0x3
0x0
R/W
R/W
0x241
7
OUT89 source
This bit selects the OUT8 and OUT9 input clock.
Q3 divider output.
0
1
PLL1 active reference.
6
OUT10 source
This bit selects the divider input clock.
PLL1 output.
0x0
0x0
R/W
R/W
0
1
M0 output.
[5:0] Q3 initial phase
These bits select the divider static phase offset. The phase offset is
in units of half cycles of the input clock.
Rev. A | Page 60 of 65
Data Sheet
AD9576
Address Bits Bit Name
Settings Description
This bit determines the full swing of the OUT8 CMOS driver. Set this
Reset Access
0x242
7
OUT8 CMOS
0x1
R/W
enable full swing
bit only if the associated output format is configured as CMOS.
0
1
1.8 V swing.
Full swing.
[6:4] OUT8 driver format
These bits select the driver format of OUT8.
0x4
R/W
000
001
010
011
100
101
110
111
Tristate.
HSTL.
LVDS.
HCSL.
CMOS (both outputs active).
CMOS (positive output only).
CMOS (negative output only).
Reserved.
[3:2] OUT8 CMOS
polarity
These bits set the polarity of the full swing CMOS output driver.
Noninverted, inverted.
Inverted, inverted.
0x0
0x0
R/W
R/W
00
01
10
11
Noninverted, noninverted.
Inverted, noninverted.
1
OUT8 drive
strength
This bit selects the drive strength of the OUT8 driver and is only
applicable when the output format is configured as LVDS or full
swing CMOS.
0
1
CMOS—nominal drive; LVDS—3.5 mA.
CMOS—low drive; LVDS—4.5 mA.
Output driver enable control.
Power down.
0
7
OUT8 enable
0x1
0x1
R/W
R/W
0
1
Enable.
0x243
OUT9 CMOS
enable full swing
This bit determines the swing of the OUT9 CMOS driver. Set this bit
only if the associated output format is configured as CMOS.
0
1
1.8 V swing.
Full swing.
[6:4] OUT9 driver
format
These bits select the driver format of OUT9.
0x4
R/W
000
001
010
011
100
101
110
111
Tristate.
HSTL.
LVDS.
HCSL.
CMOS (both outputs active).
CMOS (positive output only).
CMOS (negative output only).
Reserved.
[3:2] OUT9 CMOS
polarity
These bits set the polarity of the full swing CMOS output driver.
Noninverted, inverted.
Inverted, inverted.
0x0
R/W
00
01
10
11
Noninverted, noninverted.
Inverted, noninverted.
1
0
OUT9 drive
strength
This bit selects the drive strength of the OUT9 driver and is only applic-
able when the output format is configured as LVDS or full swing CMOS.
0x0
0x1
R/W
R/W
0
1
CMOS—nominal drive; LVDS—3.5 mA.
CMOS—low drive; LVDS—4.5 mA.
Output driver enable control.
Power down.
OUT9 enable
0
1
Enable.
Rev. A | Page 61 of 65
AD9576
Data Sheet
Address Bits Bit Name
Settings Description
Reserved. Always configure this bit to the default value.
Reset Access
0x244
7
6
Reserved
0x1
0x0
R/W
R/W
Q4 power-down
Divider power-down control.
0
1
Normal operation (default). The Q4 divider works normally.
Powered down. The Q0 divider is powered down.
[5:0] Q4 divider ratio
These bits set the operating divide ratio. Divide ratio = bit field value + 1. 0x3
R/W
R/W
R/W
0x245
7
6
Reserved
Q4 source
Reserved. Always configure this bit to the default value.
This bit selects the OUT10 input clock source.
PLL1 selected reference input.
0x1
0x0
1
0
Divider, Q4, output.
[5:0] Q4 initial phase
These bits set the divider static phase offset. The phase offset in
units of half cycles of the input clock.
0x0
0x1
R/W
R/W
0x246
7
OUT10 CMOS
This bit determines the full swing of the OUT10 CMOS driver. Only
set this bit if the associated output format is configured as CMOS.
enable full swing
0
1
1.8 V swing.
Full swing.
[6:4] OUT10 driver
format
These bits select the driver format of OUT10.
0x4
R/W
000
001
010
011
100
101
110
111
Tristate.
HSTL.
LVDS.
HCSL.
CMOS (both outputs active).
CMOS (positive output only).
CMOS (negative output only).
Reserved.
[3:2] OUT10 CMOS
polarity
These bits set the polarity of the full swing CMOS output driver.
Noninverted, inverted.
Inverted, inverted.
0x0
R/W
00
01
10
11
Noninverted, noninverted.
Inverted, noninverted.
1
0
OUT10 drive
strength
This bit selects the drive strength of the OUT10 driver and is only
applicable when the output format is configured as LVDS or full
swing CMOS.
0x0
0x1
R/W
R/W
0
1
CMOS—nominal drive; LVDS—3.5 mA.
CMOS—low drive; LVDS—4.5 mA.
Output driver enable control.
Power down.
OUT10 enable
0
1
Enable.
Rev. A | Page 62 of 65
Data Sheet
AD9576
APPLICATIONS INFORMATION
INTERFACING TO CMOS CLOCK OUTPUTS
INTERFACING TO LVDS AND HSTL CLOCK
OUTPUTS
Apply the following general guidelines when using the single-
ended 1.8 V or 3.3 V CMOS clock output drivers.
LVDS and HSTL both employ a differential output driver. The
recommended termination circuit for LVDS and HSTL drivers
Design point to point nets such that a driver has only one
receiver on the net, if possible. This allows simple termination
schemes and minimizes ringing due to possible mismatched
impedances on the net. Series termination at the source is
generally required to provide transmission line matching and/or
to reduce current transients at the driver.
appears in Figure 41.
3.3V
100ꢀ
100ꢀ
50ꢀ
10ꢀ
CMOS
5pF
The value of the series termination depends on the board
design and timing requirements (typically 10 Ω to 100 Ω).
CMOS outputs are limited in terms of the capacitive load or
trace length that they can drive. Typically, trace lengths less
than 6 inches are recommended to preserve signal rise/fall
times and signal integrity.
Figure 41. CMOS Output with Far End Termination
See the AN-586 Application Note for more information about
LVDS.
INTERFACING TO HCSL CLOCK OUTPUTS
60.4ꢀ
HCSL uses a differential open-drain architecture. The open-
drain architecture necessitates the use of an external termination
resistor. Figure 42 shows the typical method for interfacing to
HCSL drivers.
1.0 INCH
10ꢀ
CMOS
MICROSTRIP
5pF
GND
INDEPENDENT
UNCOUPLED 50ꢀ
Figure 39. Series Termination of CMOS Output
TRANSMISSION LINES
HCSL
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9576 do not supply enough current
to provide a full voltage swing with a low impedance resistive,
far end termination, as shown in Figure 40. Ensure that the
impedance of the far end termination network matches the PCB
trace impedance and provides the desired switching point. The
reduced signal swing may still meet receiver input requirements
in some applications. This can be useful when driving long
trace lengths on less critical nets.
RECEIVER
50ꢀ
50ꢀ
Figure 42. HCSL Output Termination
In some cases, the fast switching capability of HCSL drivers
results in overshoot and ringing. The alternative HCSL interface
shown in Figure 43 can mitigate this problem via a small series
resistor, typically in the 10 Ω to 30 Ω range.
INDEPENDENT
UNCOUPLED 50ꢀ
TRANSMISSION LINES
INDEPENDENT
UNCOUPLED 50ꢀ
TRANSMISSION LINES
HCSL
100ꢀ
10ꢀ TO 30ꢀ
10ꢀ TO 30ꢀ
HSTL/LVDS
DRIVER
RECEIVER
RECEIVER
50ꢀ
50ꢀ
Figure 40. LVDS or HSTL Output Termination
Figure 43. Alternate HCSL Output Termination
Rev. A | Page 63 of 65
AD9576
Data Sheet
beads with approximately 75 Ω impedance at 100 MHz are
POWER SUPPLY
suitable for use with Pin 52 and Pin 57.
The AD9576 requires a power supply of 2.5 V 5% or 3.3 V
10%. The Specifications section gives the performance expected
from the AD9576 with the power supply voltage within this
range. The absolute maximum range of −0.3 V to +3.6 V, with
respect to GND, must never be exceeded on the VDD_x pins.
The layout of the AD9576 evaluation board is a good example
of how to route power supply traces and where to place bypass
capacitors and ferrite beads.
The exposed metal pad on the AD9576 package is an electrical
connection, as well as a thermal enhancement. For the device to
function properly, the pad must be properly attached to ground
(GND). The PCB acts as a heat sink for the AD9576; therefore,
this GND connection provides a good thermal path to a larger
heat dissipation area, such as a ground plane on the PCB.
Follow good engineering practice in the layout of power supply
traces and the ground plane of the PCB. Bypass the power
supply on the PCB with adequate capacitance (>10 µF). Bypass
the AD9576 with adequate capacitors (0.1 µF) at all power pins
as close as possible to the device.
In addition to these bypass capacitors, the AD9576 evaluation
board uses six ferrite beads between the 2.5 V (or 3.3 V) source
and Pin 29, Pin 35, Pin 41, Pin 46, Pin 52, and Pin 57. Although
these ferrite beads may not be needed for every application, the
use of these ferrite beads is strongly recommended. At a
minimum, include a place for the ferrite beads (as close to the
bypass capacitors as possible) and populate the board with
0402, 0 Ω resistors. By doing so, there is a place for the ferrite
beads, if needed. Ferrite beads with low (<0.7 Ω) dc resistance
and approximately 600 Ω impedance at 100 MHz are suitable
for use with Pin 29, Pin 35, Pin 41, and Pin 46, while ferrite
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under
less than ideal operating conditions. In these application
circuits, the implementation and construction of the PCB is as
important as the circuit design. Proper RF techniques must be
used for device selection, placement, and routing, as well as for
power supply bypassing and grounding to ensure optimum
performance.
Rev. A | Page 64 of 65
Data Sheet
AD9576
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
9.10
0.30
0.25
0.18
9.00 SQ
8.90
PIN 1
INDICATOR
PIN 1
49
48
64
IONS
INDICATOR AR EA OP T
1
(SEE DETAIL
A)
0.50
BSC
6.30
6.20 SQ
6.10
EXPOSED
PAD
33
32
16
17
0.45
0.40
0.35
TOP VIEW
END VIEW
BOTTOM VIEW
0.20 MIN
7.50 REF
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
SECTION OF THIS DATA SHEET.
0.08
SEATING
PLANE
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WMMD
Figure 44. 64-Lead Lead Frame Chip Scale Package [LFCSP]
9 mm × 9 mm and 0.75 mm Package Height
(CP-64-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
AD9576BCPZ
AD9576BCPZ-REEL7
AD9576/PCBZ
−40°C to +85°C
−40°C to +85°C
64-Lead Lead Frame Chip Scale Package [LFCSP]
64-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-64-17
CP-64-17
1Z = RoHS-Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2016–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13993-0-9/18(A)
Rev. A | Page 65 of 65
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