AD9641BCPZRL7-155_技术文档

14-Bit, 80 MSPS/155 MSPS, 1.8 V

Serial Output Analog-to-Digital Converter (ADC)

Data Sheet

AD9641

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AVDD

SDIO SCLK CSB

DRVDD

JESD204A coded serial digital outputs

SNR = 73.7 dBFS at 70 MHz/80 MSPS

SPI

AD9641

SNR = 72.8 dBFS at 70 MHz and 155 MSPS

SFDR = 94 dBc at 70 MHz and 80 MSPS

SFDR = 90 dBc at 70 MHz and 155 MSPS

Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS

1.8 V supply operation

PROGRAMMING DATA

ADC

DOUT+

DOUT–

DSYNC+

DSYNC–

VIN+

VIN–

VCM

Integer 1-to-8 input clock divider

IF sampling frequencies to 250 MHz

REFERENCE

DATA RATE

MULTIPLIER

−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS

−148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS

Programmable internal ADC voltage reference

Flexible analog input range: 1.4 V p-p to 2.1 V p-p

ADC clock duty cycle stabilizer (DCS)

DUTY CYCLE

STABILIZER

CLK+

CLK–

DIVIDE-BY-1

MULTICHIP

SYNC

TO

DIVIDE-BY-8

Serial port control

User-configurable, built-in self-test (BIST) capability

Energy-saving power-down modes

AGND

SYNC

PDWN

DRGND

Figure 1.

APPLICATIONS

The ADC output data is routed directly to the JESD204A serial

output port. This output is at CML voltage levels. A CMOS or

LVDS synchronization input (DSYNC) is provided.

Communications

Diversity radio systems

Multimode digital receivers (3G and 4G)

GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMA

Smart antenna systems

General-purpose software radios

Broadband data applications

Ultrasound equipment

The flexible power-down options allow significant power savings,

when desired.

Programming for setup and control is accomplished using a 3-wire

SPI-compatible serial interface.

The AD9641 is available in a 32-lead LFCSP and is specified over

the industrial temperature range of −40°C to +85°C.

This product is protected by a U.S. patent.

GENERAL DESCRIPTION

The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital

converter (ADC) with a high speed serial output interface. The

AD9641 is designed to support communications applications

where high performance, combined with low cost, small size, and

versatility, is desired. The JESD204A high speed serial interface

reduces board routing requirements and lowers pin count

requirements for the receiving device.

PRODUCT HIGHLIGHTS

1. An on-chip PLL allows users to provide a single ADC

sampling clock. The PLL multiplies the ADC sampling clock

to produce the corresponding JESD204A data rate clock.

2. The configurable JESD204A output block coded data rate

supports up to 1.6 Gbps.

3. A proprietary differential input maintains excellent SNR

performance for input frequencies of up to 250 MHz.

4. Operation is from a single 1.8 V power supply.

5. The standard serial port interface (SPI) supports various

product features and functions, such as data formatting

(offset binary, twos complement, or Gray coding), control-

ling the clock DCS, power-down, test modes, voltage

reference mode, and serial output configuration.

The ADC core features a multistage, differential pipelined

architecture with integrated output error correction logic. The

ADC features wide bandwidth, differential sample-and-hold,

analog input amplifiers that support a variety of user-selectable

input ranges. An integrated voltage reference eases the design

considerations. A duty cycle stabilizer (DCS) is provided to

compensate for variations in the ADC clock duty cycle,

allowing the converter to maintain excellent performance.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

AD9641* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

TOOLS AND SIMULATIONS

• Visual Analog

• AD9641/AD9644-155 S-Parameter Data

• AD9641/AD9644-80 S-Parameter Data

EVALUATION KITS

• AD9641 Evaluation Board

REFERENCE MATERIALS

DOCUMENTATION

Technical Articles

Application Notes

• Improve The Design Of Your Passive Wideband ADC

Front-End Network

• AN-1142: Techniques for High Speed ADC PCB Layout

• AN-586: LVDS Outputs for High Speed A/D Converters

• MS-2210: Designing Power Supplies for High Speed ADC

• AN-742: Frequency Domain Response of Switched-

DESIGN RESOURCES

• AD9641 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

Capacitor ADCs

• AN-807: Multicarrier WCDMA Feasibility

• AN-808: Multicarrier CDMA2000 Feasibility

• AN-812: MicroController-Based Serial Port Interface (SPI)

Boot Circuit

• AN-827: A Resonant Approach to Interfacing Amplifiers to

Switched-Capacitor ADCs

DISCUSSIONS

View all AD9641 EngineerZone Discussions.

• AN-878: High Speed ADC SPI Control Software

• AN-935: Designing an ADC Transformer-Coupled Front

End

SAMPLE AND BUY

Visit the product page to see pricing options.

Data Sheet

• AD9641: 14-Bit, 80 MSPS, 1.8 V Serial Output Analog-to-

Digital Converter (ADC)

TECHNICAL SUPPORT

User Guides

Submit a technical question or find your regional support

number.

• UG-294: Evaluating the AD9644/AD9641 Analog-to-

Digital Converters

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AD9641

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Voltage Reference ....................................................................... 19

Clock Input Considerations...................................................... 19

Chip Synchronization................................................................ 20

Power Dissipation and Standby Mode .................................... 21

Digital Outputs ........................................................................... 21

Built-In Self-Test (BIST) and Output Test .................................. 25

Built-In Self-Test (BIST)............................................................ 25

Output Test Modes..................................................................... 25

Serial Port Interface (SPI).............................................................. 27

Configuration Using the SPI..................................................... 27

Hardware Interface..................................................................... 28

SPI Accessible Features.............................................................. 28

Memory Map .................................................................................. 29

Reading the Memory Map Register Table............................... 29

Memory Map Register Table..................................................... 29

Memory Map Register Descriptions........................................ 32

Applications Information.............................................................. 35

Design Guidelines ...................................................................... 35

Outline Dimensions....................................................................... 36

Ordering Guide .......................................................................... 36

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

ADC DC Specifications............................................................... 3

ADC AC Specifications ............................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Specifications .................................................................. 7

Absolute Maximum Ratings............................................................ 8

Thermal Characteristics .............................................................. 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 10

Equivalent Circuits......................................................................... 16

Theory of Operation ...................................................................... 17

ADC Architecture ...................................................................... 17

Analog Input Considerations.................................................... 17

REVISION HISTORY

1/12—Rev. A to Rev. B

Change to General Description Section........................................ 1

Changes to Table 2............................................................................ 4

Added Figure 23 to Figure 40; Renumbered Sequentially ........ 13

Changes to Clock Input Considerations Section ....................... 19

Changes to Digital Outputs and Timing Section....................... 23

Moved Figure 65 and Figure 66.................................................... 23

Added Figure 68 ............................................................................. 24

Changes to Output Test Modes Section ...................................... 25

Changes to SPI Accessible Features Section ............................... 28

Changes to Addr (Hex) 0x02, Table 17........................................ 29

Changes to Ordering Guide.......................................................... 36

8/11—Rev. 0 to Rev. A

Added Model -155......................................................... Throughout

Changes to Features.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 4............................................................................ 6

Changes to Figure 11 to Figure 14 Captions............................... 11

7/10—Revision 0: Initial Version

Rev. B | Page 2 of 36

Data Sheet

AD9641

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS diﬀerential input, DCS enabled,

unless otherwise noted.

Table 1.

AD9641-80

Typ

AD9641-155

Typ

Parameter

Temperature Min

Max

Min

Max

Unit

RESOLUTION

Full

14

Bits

ACCURACY

No Missing Codes

Offset Error

Gain Error

Full

±5°C

Full

±5°C

Guaranteed

±±

−±.5

Guaranteed

±±

−±.5

±1ꢀ

+1

±ꢀ.55

±11

+1

±ꢀ.55

mV

% FSR

LSB

−7

−7.5

Differential Nonlinearity (DNL)¹

±ꢀ.3

±ꢀ.5

±ꢀ.3

±ꢀ.5

Integral Nonlinearity (INL)¹

±1.1

±1.±

LSB

TEMPERATURE DRIFT

Offset Error

Gain Error

Full

±±

±35

ꢀ.7

±±

±35

ꢀ.7

ppm/°C

LSB rms

INPUT REFERRED NOISE

ANALOG INPUT

Input Span

Input Capacitance^±

Input Resistance

VCM OUTPUT LEVEL

POWER SUPPLIES

Supply Voltage

AVDD

±5°C

Full

1.383

ꢀ.88

1.75

6

±ꢀ

±.ꢀ87

ꢀ.9±

1.383

ꢀ.87

1.75

5

±ꢀ

±.ꢀ87

ꢀ.9±

V p-p

pF

kΩ

V

ꢀ.9

Full

1.7

1.8

1.9

1.7

1.8

1.9

V

DRVDD

Supply Current

IAVDD¹

IDRVDD¹

Full

96

36

1ꢀꢀ

4ꢀ

1±1

51

13±

54

mA

POWER CONSUMPTION

Sine Wave Input¹

Standby Power³

Power-Down Power

Full

±38

56

7

±5±

18

31ꢀ

56

7

335

18

mW

¹Measured with a low input frequency, full-scale sine wave.

^±Input capacitance refers to the effective capacitance between one differential input pin and AGND.

³Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).

Rev. B | Page 3 of 36

AD9641

Data Sheet

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS diﬀerential input, DCS enabled,

unless otherwise noted.

Table 2.

AD9641-80

AD9641-155

Parameter¹

Temperature

Min

Typ

Max

Min

Typ

Max

Unit

SIGNAL-TO-NOISE-RATIO (SNR)

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

±5°C

Full

73.8

73.7

7±.6

7±.ꢀ

71.7

71.3

dBFS

f_IN= 18ꢀ MHz

71.8

69.8

f_IN= ±±ꢀ MHz

±5°C

71.3

71.±

SIGNAL-TO-NOISE AND DISTORTION (SINAD)

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

±5°C

Full

73.7

73.6

7±.5

71.ꢀ

7ꢀ.6

7ꢀ.±

dBFS

f_IN= 18ꢀ MHz

71.4

68.7

f_IN= ±±ꢀ MHz

±5°C

71.±

7ꢀ.1

EFFECTIVE NUMBER OF BITS (ENOB)

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

f_IN= 18ꢀ MHz

f_IN= ±±ꢀ MHz

±5°C

1±.ꢀ

11.9

11.8

11.5

11.4

Bits

WORST SECOND OR THIRD HARMONIC

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

±5°C

Full

−94

−91

−9ꢀ

dBc

f_IN= 18ꢀ MHz

−8ꢀ

f_IN= ±±ꢀ MHz

±5°C

−9ꢀ

−89

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

±5°C

Full

94

91

9ꢀ

dBc

f_IN= 18ꢀ MHz

8ꢀ

f_IN= ±±ꢀ MHz

±5°C

9ꢀ

89

WORST OTHER (HARMONIC OR SPUR)

f_IN= 1ꢀ MHz

f_IN= 7ꢀ MHz

±5°C

Full

−98

−96

−98

−94

dBc

f_IN= 18ꢀ MHz

−9ꢀ

−87

f_IN= ±±ꢀ MHz

±5°C

−9ꢀ

TWO-TONE SFDR

f_IN= 3ꢀ MHz (−7 dBFS ), 33 MHz (−7 dBFS )

f_IN= 169 MHz (−7 dBFS ), 17± MHz (−7 dBFS )

ANALOG INPUT BANDWIDTH^±

±5°C

93

89

dBc

MHz

78ꢀ

¹See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

^±The analog input bandwidth parameter specifies the −3 dB input BW of the AD9641 input. The usable full-scale BW of the part with good performance is ±5ꢀ MHz.

Rev. B | Page 4 of 36

Data Sheet

AD9641

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS diﬀerential input, and DCS enabled,

unless otherwise noted.

Table 3.

Parameter

Temperature Min

Typ

Max

Unit

DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)

Logic Compliance

CMOS/LVDS/LVPECL

ꢀ.9

Internal Common-Mode Bias

Differential Input Voltage

Input Voltage Range

Input Common-Mode Range

High Level Input Current

Low Level Input Current

Input Capacitance

Full

V

Full

ꢀ.3

AGND

ꢀ.9

−1ꢀꢀ

3.6

AVDD

1.4

V p-p

V

+1ꢀꢀ

μA

pF

kΩ

4

1ꢀ

Input Resistance

8

1±

SYNC INPUT

Logic Compliance

Internal Bias

CMOS

ꢀ.9

Full

V

Input Voltage Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

AGND

1.±

AGND

−1ꢀꢀ

AVDD

ꢀ.6

V

+1ꢀꢀ

μA

pF

kΩ

1

16

Input Resistance

1±

±ꢀ

DSYNC INPUT

Logic Compliance

Internal Bias

CMOS/LVDS

ꢀ.9

Full

V

Input Voltage Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

AGND

1.±

AGND

−1ꢀꢀ

AVDD

ꢀ.6

V

+1ꢀꢀ

μA

pF

kΩ

1

16

Input Resistance

1±

±ꢀ

LOGIC INPUT (CSB)¹

Logic Compliance

CMOS

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.±±

ꢀ

−1ꢀ

4ꢀ

±.1

ꢀ.6

+1ꢀ

13±

V

μA

kΩ

pF

±6

±

Input Capacitance

LOGIC INPUT (SCLK)^±

Logic Compliance

CMOS

High Level Input Voltage

Low Level Input Voltage

High Level Input Current (VIN = 1.8 V)

Low Level Input Current

Input Resistance

Full

1.±±

ꢀ

−9±

−1ꢀ

±.1

ꢀ.6

−135

+1ꢀ

V

μA

kΩ

pF

±6

±

Input Capacitance

Rev. B | Page 5 of 36

AD9641

Data Sheet

Parameter

LOGIC INPUT/OUTPUT (SDIO)¹

Temperature Min

Typ

Max

Unit

Logic Compliance

CMOS

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.±±

ꢀ

−1ꢀ

38

±.1

ꢀ.6

+1ꢀ

1±8

V

μA

kΩ

pF

±6

5

Input Capacitance

DIGITAL OUTPUTS

Logic Compliance

Differential Output Voltage (V_OD)

Output Offset Voltage (V_OS)

Full

CML

ꢀ.8

DRVDD/±

ꢀ.6

ꢀ.75

1.1

1.ꢀ5

V

¹Pull up.

^±Pull down.

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS diﬀerential input, and DCS enabled,

unless otherwise noted.

Table 4.

AD9641-80

Temperature Min Typ

AD9641-155

Typ

Parameter

Max Min

Max

Unit

CLOCK INPUT PARAMETERS

Input Clock Rate

Conversion Rate¹

Full

64ꢀ

8ꢀ

64ꢀ

155

MHz

MSPS

ns

4ꢀ

1±.5

4ꢀ

6.45

CLK Period—Divide-by-1 Mode (t_CLK

)

CLK Pulse Width High (t_CH)

Divide-by-1 Mode, DCS Enabled

Divide-by-1 Mode, DCS Disabled

Divide-by-± ModeThrough Divide-by-8 Mode Full

Full

3.75 6.±5

5.95 6.±5

ꢀ.8

8.75 1.935 3.±±5

6.55 3.ꢀ65 3.±±5

4.515 ns

3.385 ns

ns

ꢀ.8

Aperture Delay (t_A)

Full

ꢀ.78

ꢀ.1±5

ꢀ.78

ꢀ.1±5

ns

ps rms

Aperture Uncertainty (Jitter, t_J)

DATA OUTPUT PARAMETERS

Data Output Period or UI (Unit Interval)

Data Output Duty Cycle

Data Valid Time

PLL Lock Time (t_LOCK

Wake Up Time (Standby)

Wake Up Time (Power-Down)^±

Pipeline Delay (Latency)

Data Rate (NRZ)

Full

1/(±ꢀ × f_CLK

)

1/(±ꢀ × f_CLK

)

sec

%

UI

μs

ms

CLK cycles

Gbps

ps

ps rms

ps

5ꢀ

ꢀ.8

4

5ꢀ

ꢀ.75

4

±5°C

Full

±5°C

)

5

±.5

±3

±4

±3

±4

1.6

4ꢀ

9.5

3.1

4ꢀ

Deterministic Jitter

Random Jitter at 1.6 Gbps

Random Jitter at 3.1 Gbps

Output Rise/Fall Time

5.±

5ꢀ

TERMINATION CHARACTERISTICS

Differential Termination Resistance

OUT-OF-RANGE RECOVERY TIME

±5°C

1ꢀꢀ

±

1ꢀꢀ

±

Ω

CLK cycles

¹Conversion rate is the clock rate after the divider.

^±Wake-up time is defined as the time required to return to normal operation from power-down mode.

Rev. B | Page 6 of 36

Data Sheet

AD9641

TIMING SPECIFICATIONS

Table 5.

Parameter

Test Conditions

Limit

SYNC TIMING REQUIREMENTS

t_SSYNC

t_HSYNC

SYNC to rising edge of CLK+ setup time

SYNC to rising edge of CLK+ hold time

ꢀ.3ꢀ ns typ

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

t_H

t_HIGH

t_LOW

t_{EN_SDIO}

Setup time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

Setup time between CSB and SCLK

Hold time between CSB and SCLK

SCLK pulse width high

± ns min

4ꢀ ns min

± ns min

1ꢀ ns min

SCLK pulse width low

Time required for the SDIO pin to switch from an input to an output relative to the SCLK

falling edge

t_{DIS_SDIO}

Time required for the SDIO pin to switch from an output to an input relative to the SCLK

rising edge

1ꢀ ns min

Timing Diagrams

SAMPLE

N

N – 23

ANALOG

N – 22

N + 1

INPUT

N – 21

SIGNAL

N – 1

N – 20

CLK–

CLK+

CLK–

CLK+

DOUT+

DOUT–

SAMPLE N – 23

ENCODED INTO 2

8b/10b SYMBOLS

SAMPLE N – 22

ENCODED INTO 2

8b/10b SYMBOLS

SAMPLE N – 21

ENCODED INTO 2

8b/10b SYMBOLS

Figure 2. Data Output Timing

CLK+

SYNC

t_SSYNC

t_HSYNC

Figure 3. SYNC Input Timing Requirements

Rev. B | Page 7 of 36

AD9641

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

Table 6.

The exposed paddle must be soldered to the ground plane for

the LFCSP package. Soldering the exposed paddle to the PCB

increases the reliability of the solder joints and maximizes the

thermal capability of the package.

Parameter

Rating

ELECTRICAL

AVDD to AGND

DRVDD to AGND

VIN+, VIN− to AGND

CLK+, CLK− to AGND

SYNC to AGND

VCM to AGND

CSB to AGND

SCLK to AGND

SDIO to AGND

−0.3 V to +2.0 V

−0.3 V to +2.0V

−0.3 V to AVDD + 0.2 V

−0.3 V to DRVDD + 0.2 V

Table 7. Thermal Resistance

Airflow

Velocity

(m/sec)

1, 2

1, 3

1, 4

Package Type

θ_JA

36

32

28

θ_JC

θ_JB

Unit

°C/W

32-Lead LFCSP

5 mm × 5 mm

(CP-32-12)

0

3

20

1.0

2.5

PDWN to AGND

DOUT+, DOUT− to AGND

DSYNC+, DSYNC− to AGND

ENVIRONMENTAL

¹Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.

²Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

³Per MIL-Std 883, Method 1012.1.

⁴Per JEDEC JESD51-8 (still air).

Operating Temperature Range

(Ambient)

Maximum Junction Temperature

Under Bias

Storage Temperature Range

(Ambient)

−40°C to +85°C

150°C

Typical θ_JAis specified for a 4-layer PCB with a solid ground

plane. As shown in Table 7, airflow improves heat dissipation,

which reduces θ_JA. In addition, metal in direct contact with the

package leads from metal traces, through holes, ground, and

power planes, reduces θ_JA.

−65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ESD CAUTION

Rev. B | Page 8 of 36

Data Sheet

AD9641

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD

DNC

1

2

3

4

5

6

7

8

24 PDWN

23 DNC

22 CSB

21 SCLK

20 SDIO

19 DRVDD

18 DRVDD

17 DRGND

PIN 1

INDICATOR

AVDD

CLK+

CLK–

AVDD

SYNC

AVDD

AD9641

TOP VIEW

(Not to Scale)

NOTES

1. DNC = DO NOT CONNECT.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE

PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD

MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 4. LFCSP Pin Configuration (Top View)

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

1±, 16, 18, 19

1, 3, 6, 8, ±6, ±7, 3ꢀ, 31, 3± AVDD

DRVDD

Supply

Digital Output Driver Supply (1.8 V Nominal).

Analog Power Supply (1.8 V Nominal).

Do Not Connect.

±, ±3

DNC

11, 13, 17

ꢀ

DRGND

AGND, Exposed pad Ground

Driver ground Digital Driver Supply Ground.

The exposed thermal pad on the bottom of the package provides

the analog ground for the part. This exposed pad must be connected

to ground for proper operation.

ADC Analog

±9

±8

±5

4

VIN+

VIN−

VCM

CLK+

CLK−

Input

Output

Input

Differential Analog Input Pin (+).

Differential Analog Input Pin (−).

Common-Mode Level Bias Output.

ADC Clock Input—True.

5

ADC Clock Input—Complement.

Digital Inputs

7

1ꢀ

SYNC

DSYNC+

Input

Input Clock Divider Synchronization Pin.

Active Low JESD±ꢀ4A LVDS Sync Input—True/Active Low

JESD±ꢀ4A CMOS Sync Input.

9

DSYNC−

Input

Active Low JESD±ꢀ4A LVDS Sync Input—Complement.

Digital Outputs

15

14

DOUT+

DOUT−

Output

CML Output Data—True.

CML Output Data—Complement.

SPI Control

±1

±ꢀ

±±

SCLK

SDIO

CSB

Input

SPI Serial Clock.

Input/output SPI Serial Data I/O.

Input

SPI Chip Select (Active Low).

ADC Configuration

±4

PDWN

Power-Down Input. Using the SPI interface, this input can be

configured as power-down or standby.

Rev. B | Page 9 of 36

AD9641

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN =

−1.0 dBFS, and 32k sample, T_A= 25°C, unless otherwise noted.

0

80MSPS

10.1MHz @ –1dBFS

SNR = 73.0dB (74.0dBFS)

SFDR = 95dBc

140.3MHz @ –1dBFS

SNR = 72.2dB (73.2dBFS)

SFDR = 94.0dBc

–20

–40

–60

–80

THIRD HARMONIC

–100

–120

–140

–100

–120

–140

0

10

20

30

40

0

10

20

FREQUENCY (MHz)

30

40

FREQUENCY (MHz)

Figure 5. AD9641-80 Single-Tone FFT with f_IN= 10.1 MHz

Figure 8. AD9641-80 Single-Tone FFT with f_IN= 140.1 MHz

0

80MSPS

30.1MHz @ –1dBFS

SNR = 72.7dB (73.7dBFS)

SFDR = 94dBc

180.1MHz @ –1dBFS

SNR = 71.6dB (72.6dBFS)

SFDR = 93dBc

–20

–40

–20

–40

–60

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

–140

–100

–120

–140

0

10

20

FREQUENCY (MHz)

30

40

0

10

20

FREQUENCY (MHz)

30

40

Figure 6. AD9641-80 Single-Tone FFT with f_IN= 30.1 MHz

Figure 9. AD9641-80 Single-Tone FFT with f_IN= 180.1 MHz

0

80MSPS

220.1MHz @ –1dBFS

SNR = 71.1dB (72.1dBFS)

SFDR = 92dBc

70.1MHz @ –1dBFS

SNR = 72.5dB (73.5dBFS)

SFDR = 94.0dBc

–20

–40

–60

THIRD HARMONIC

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

–140

–100

–120

–140

0

10

20

FREQUENCY (MHz)

30

40

0

10

20

FREQUENCY (MHz)

30

40

Figure 10. AD9641-80 Single-Tone FFT with f_IN= 220.1 MHz

Figure 7. AD9641-80 Single-Tone FFT with f_IN= 70.1 MHz

Rev. B | Page 1ꢀ of 36

Data Sheet

AD9641

100

95

90

85

80

75

70

65

120

100

80

SNR @ –40°C

SFDR @ –40°C

SNR @ +25°C

SFDR @ +25°C

SNR @ +85°C

SFDR @ +85°C

SFDR (dBFS)

60

40

20

0

SFDR (dBc)

SNR (dBFS)

SNR (dBc)

0

50

100

150

200

250

INPUT FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 11. AD9641-80 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN)

with f_IN= 10.1 MHz, f_S= 80 MSPS

Figure 14. AD9641-80 Single-Tone SNR/SFDR vs. Input Frequency (f_IN) and

Temperature with 2.0 V p-p Full Scale, f_S= 80 MSPS

120

100

80

0

–20

–40

SFDR (dBFS)

SFDR (dBc)

SNR (dBFS)

SNR (dBc)

–60

60

SFDR (dBc)

IMD3 (dBc)

SFDR (dBFS)

–80

IMD3 (dBFS)

40

20

–100

–120

0

–90

–78

–66

–54

–42

–30

–18

–6

INPUT AMPLITUDE (dBFS)

Figure 12. AD9641-80 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN)

with f_IN= 180 MHz, f_S= 80 MSPS

Figure 15. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN)

with f_IN1= 29.9 MHz, f_IN2= 32.9 MHz, f_S= 80 MSPS

0

100

95

–20

–40

90

SNR @ –40°C

85

80

75

70

65

SFDR @ –40°C

SNR @ +25°C

SFDR @ +25°C

SNR @ +85°C

SFDR @ +85°C

–60

–80

SFDR (dBc)

IMD3 (dBc)

SFDR (dBFS)

IMD3 (dBFS)

–100

–120

0

50

100

150

200

250

–90

–78

–66

–54

–42

–30

–18

–6

INPUT FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 16. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN)

with f_IN1= 169.1 MHz, f_IN2= 172.1 MHz, f_S= 80 MSPS

Figure 13. AD9641-80 Single-Tone SNR/SFDR vs. Input Frequency (f_IN) and

Temperature with 1.75 V p-p Full Scale, f_S= 80 MSPS

Rev. B | Page 11 of 36

AD9641

Data Sheet

0

14,000

12,000

10,000

8000

80MSPS

29.9MHz @ –7dBFS

32.9MHz @ –7dBFS

SFDR = 94.4dBc (101.4dBFS)

–20

–40

–60

6000

–80

4000

–100

–120

2000

–140

0

10

20

FREQUENCY (MHz)

30

40

N – 4 N – 3 N – 2 N – 1

N

N + 1 N + 2 N + 3 N + 4

OUTPUT CODE

Figure 17. AD9641-80 Two-Tone FFT with f_IN1= 29.9 MHz and f_IN2= 32.9 MHz

Figure 20. AD9641-80 Grounded Input Histogram

1.0

0.8

0

80MSPS

169.1MHz @ –7dBFS

172.1MHz @ –7dBFS

SFDR = 91.9dBc (98.9dBFS)

–20

–40

0.6

0.4

0.2

–60

0

–80

–0.2

–0.4

–0.6

–0.8

–1.0

–100

–120

–140

0

200

400

600

800

1000 1200 1400 1600

0

10

20

FREQUENCY (MHz)

30

40

OUTPUT CODE

Figure 18. AD9641-80 Two-Tone FFT with f_IN1= 169.1 MHz and

f_IN2= 172.1 MHz

Figure 21. AD9641-80 INL with f_IN= 30.3 MHz

0.50

0.25

0

100

SFDR

95

90

85

80

75

70

–0.25

–0.50

SNR

45

50

55

60

65

70

75

80

0

2000 4000 6000 8000 10,000 12,000 14,000 16,000

OUTPUT CODE

SAMPLE RATE (MSPS)

Figure 22. AD9641-80 DNL with f_IN= 30.3 MHz

Figure 19. AD9641-80 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 70.1 MHz

Rev. B | Page 1± of 36

Data Sheet

AD9641

0

–20

–40

–60

0

–20

–40

–60

155MSPS

140.1MHz @ –1dBFS

SNR = 70.7dB (71.7dBFS)

SFDR = 93dBc

10.1MHz @ –1dBFS

SNR = 71.0dB (72.0dBFS)

SFDR = 95dBc

SECOND HARMONIC

THIRD HARMONIC

SECOND HARMONIC

–80

–100

–120

–140

–80

–100

–120

–140

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

Figure 23. AD9641-155 Single-Tone FFT with f_IN= 10.1 MHz

Figure 26. AD9641-155 Single-Tone FFT with f_IN= 140.1 MHz

0

155MSPS

30.1MHz @ –1dBFS

SNR = 70.9dB (71.9dBFS)

SFDR = 95dBc

180.1MHz @ –1dBFS

SNR = 70.3dB (71.3dBFS)

SFDR = 92dBc

–20

–40

–60

–40

–60

THIRD HARMONIC

SECOND HARMONIC

THIRD HARMONIC

SECOND HARMONIC

–80

–100

–120

–140

–80

–100

–120

–140

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

Figure 24. AD9641-155 Single-Tone FFT with f_IN= 30.1 MHz

Figure 27. AD9641-155 Single-Tone FFT with f_IN= 180.1 MHz

0

155MSPS

70.1MHz @ –1dBFS

SNR = 70.7dB (71.7dBFS)

SFDR = 93dBc

220.1MHz @ –1dBFS

SNR = 70.2dB (71.2dBFS)

SFDR = 89dBc

–20

–40

–60

–40

–60

THIRD HARMONIC

SECOND HARMONIC

THIRD HARMONIC

–80

–100

–120

–140

–80

–100

–120

–140

SECOND HARMONIC

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

Figure 25. AD9641-155 Single-Tone FFT with f_IN= 70.1 MHz

Figure 28. AD9641-155 Single-Tone FFT with f_IN= 220.1 MHz

Rev. B | Page 13 of 36

AD9641

Data Sheet

120

100

80

100

95

SFDR (dBFS)

SNR (dBFS)

90

85

SNR @ –40°C

SFDR @ –40°C

SNR @ +25°C

SFDR @ +25°C

SNR @ +85°C

SFDR @ +85°C

60

SFDR (dBc)

80

75

70

65

40

SNR (dBc)

20

0

–90

0

50

100

150

200

250

300

–80

–70

–60

–50

–40

–30

–20

–10

0

INPUT FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 29. AD9641-155 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN)

with f_IN= 10.1 MHz, f_S= 155 MSPS

Figure 32. AD9641-155 Single-Tone SNR/SFDR vs. Input Frequency (f_IN) and

Temperature with 2.0 V p-p Full Scale, f_S= 155 MSPS

0

120

SFDR (dBFS)

–20

100

80

–40

SNR (dBFS)

SFDR (dBc)

60

–60

SFDR (dBc)

IMD3 (dBc)

40

–80

SNR (dBc)

–100

–120

SFDR (dBFS)

IMD3 (dBFS)

20

0

–90

–78

–66

–54

–42

–30

–18

–6

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

INPUT AMPLITUDE (dBFS)

Figure 33. AD9641-155 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN)

with f_IN1= 29.9 MHz, f_IN2= 32.9 MHz, f_S= 155 MSPS

Figure 30. AD9641-155 Single-Tone SNR/SFDR vs. Input Amplitude (A_IN)

with f_IN= 180 MHz, f_S= 155 MSPS

0

100

95

–20

90

–40

SNR @ –40°C

SFDR (dBc)

SFDR @ –40°C

SNR @ +25°C

SFDR @ +25°C

SNR @ +85°C

SFDR @ +85°C

85

–60

80

75

70

65

IMD3 (dBc)

–80

SFDR (dBFS)

IMD3 (dBFS)

–100

–120

0

50

100

150

200

250

300

–90

–78

–66

–54

–42

–30

–18

–6

INPUT FREQUENCY (MHz)

INPUT AMPLITUDE (dBFS)

Figure 31. AD9641-155 Single-Tone SNR/SFDR vs. Input Frequency (f_IN) and

Temperature with 1.75 V p-p Full Scale, f_S= 155 MSPS

Figure 34. AD9641-155 Two-Tone SFDR/IMD3 vs. Input Amplitude (A_IN)

with f_IN1= 169.1 MHz, f_IN2= 172.1 MHz, f_S= 155 MSPS

Rev. B | Page 14 of 36

Data Sheet

AD9641

0

–20

–40

–60

6000

155MSPS

29.9MHz @ –7dBFS

32.9MHz @ –7dBFS

SFDR = 88.7dBc (95.7dBFS)

5000

4000

3000

2000

1000

0

–80

–100

–120

–140

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

N – 5 N – 4 N – 3 N – 2 N – 1

N

N + 1 N + 2 N + 3 N + 4

OUTPUT CODE

Figure 35. AD9641-155 Two-Tone FFT with f_IN1= 29.9 MHz and f_IN2= 32.9 MHz

Figure 38. AD9641-155 Grounded Input Histogram

0

1.0

0.8

155MSPS

169.1MHz @ –7dBFS

172.1MHz @ –7dBFS

SFDR = 89.8dBc (96.8dBFS)

–20

–40

–60

0.6

0.4

0.2

0

–80

–100

–120

–140

–0.2

–0.4

–0.6

–0.8

–1.0

0

7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50

FREQUENCY (MHz)

0

2000 4000 6000

8000 10,000 12,000 14,000 16,000

OUTPUT CODE

Figure 36. AD9641-155 Two-Tone FFT with f_IN1= 169.1 MHz and

f_IN2= 172.1 MHz

Figure 39. AD9641-155 INL with f_IN= 30.3 MHz

105

0.50

0.25

0

SFDR

100

95

90

85

80

75

70

–0.25

–0.50

SNR

50

65

80

95

110

125

140

155

0

2000 4000 6000

8000 10,000 12,000 14,000 16,000

SAMPLE RATE (MSPS)

OUTPUT CODE

Figure 37. AD9641-155 Single-Tone SNR/SFDR vs. Sample Rate (f_S)

with f_IN= 70.1 MHz

Figure 40. AD9641-155 DNL with f_IN= 30.3 MHz

Rev. B | Page 15 of 36

AD9641

Data Sheet

EQUIVALENT CIRCUITS

AVDD

350Ω

30kΩ

SCLK

OR

PDWN

VIN

Figure 41. Equivalent Analog Input Circuit

Figure 45. Equivalent SCLK or PDWN Input Circuit

AVDD

30kΩ

350Ω

0.9V

CSB

15kΩ

CLK+

CLK–

Figure 42. Equivalent Clock Input Circuit

Figure 46. Equivalent CSB Input Circuit

DRVDD

AVDD

4mA

R

TERM

V

DOUT+

DOUT–

DSYNC±

OR SYNC

CM

0.9V

16kΩ

0.9V

Figure 47. Equivalent SYNC and DSYNC Input Circuit

Figure 43. Digital CML Output

DRVDD

350Ω

30kΩ

SDIO

Figure 44. Equivalent SDIO Circuit

Rev. B | Page 16 of 36

Data Sheet

AD9641

THEORY OF OPERATION

In intermediate frequency (IF) undersampling applications, any

The AD9641 can sample any f_S/2 frequency segment from dc to

250 MHz, using appropriate low-pass or band-pass filtering at

the ADC inputs with little loss in ADC performance.

shunt capacitors should be reduced because the input sample

capacitor is unbuffered. In combination with the driving source

impedance, the shunt capacitors limit the input bandwidth.

Refer to the AN-742 Application Note, Frequency Domain

Response of Switched-Capacitor ADCs; the AN-827 Application

Note, A Resonant Approach to Interfacing Amplifiers to Switched-

Capacitor ADCs; and the Analog Dialogue article, “Transformer-

Coupled Front-End for Wideband A/D Converters,” for more

information on this subject (refer to www.analog.com).

BIAS

Synchronization capability is provided to allow synchronized

timing between multiple devices.

Programming and control of the AD9641 are accomplished

using a 3-wire, SPI-compatible serial interface.

ADC ARCHITECTURE

The AD9641 architecture consists of a front-end sample-and-

hold circuit, followed by a pipelined, switched-capacitor ADC.

The quantized outputs from each stage are combined into a final

14-bit result in the digital correction logic. The pipelined architec-

ture permits the first stage to operate on a new input sample

and the remaining stages to operate on the preceding samples.

Sampling occurs on the rising edge of the clock.

S

C

FB

C

S

VIN+

C

PAR1

C

PAR2

H

S

C

Each stage of the pipeline, excluding the last, consists of a low

resolution, flash ADC connected to a switched-capacitor digital-

to-analog converter (DAC) and an interstage residue amplifier

(MDAC). The MDAC magnifies the difference between the

reconstructed DAC output and the flash input for the next stage

in the pipeline. One bit of redundancy is used in each stage to

facilitate digital correction of flash errors. The last stage consists

of a flash ADC.

S

VIN–

C

FB

C

PAR1

PAR2

S

BIAS

Figure 48. Switched-Capacitor Input

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched, and the inputs should be

differentially balanced.

The input stage contains a differential sampling circuit that can

be ac- or dc-coupled in differential or single-ended modes. The

output staging block aligns the data, corrects errors, and passes the

data to the output buffers. The output buffers are powered from

a separate supply, allowing digital output noise to be separated

from the analog core. During power-down, the output buffers go

into a high impedance state.

Input Common Mode

The analog inputs of the AD9641 are not internally dc biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that VCM = 0.5 × AVDD (or

0.9 V) is recommended for optimum performance. An on-board,

common-mode voltage reference is included in the design and

is available from the VCM pin. Using the VCM output to set the

input common mode is recommended. Optimum performance

is achieved when the common-mode voltage of the analog input

is set by the VCM pin voltage (typically, 0.5 × AVDD). The VCM

pin must be decoupled to ground by a 0.1 μF capacitor. This

decoupling capacitor should be placed close to the pin to minimize

the series resistance and inductance between the part and this

capacitor.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9641 is a differential switched-

capacitor circuit that has been designed for optimum performance

while processing a differential input signal.

The clock signal switches the input alternatively between sample

mode and hold mode (see Figure 48). When the input is switched

into sample mode, the signal source must be capable of charging

the sample capacitors and settling within 1/2 of a clock cycle.

Differential Input Configurations

Optimum performance is achieved while driving the AD9641 in a

differential input configuration. For baseband applications, the

AD8138, ADA4937-2, and ADA4938-2 differential drivers provide

excellent performance and a flexible interface to the ADC.

A small resistor in series with each input can help reduce the

peak transient current required from the output stage of the

driving source. A shunt capacitor can be placed across the

inputs to provide dynamic charging currents. This passive

network creates a low-pass filter at the ADC input; therefore,

the precise values are dependent on the application.

Rev. B | Page 17 of 36

AD9641

Data Sheet

The signal characteristics must be considered when selecting

a transformer. Most RF transformers saturate at frequencies

below a few megahertz (MHz). Excessive signal power can also

cause core saturation, which leads to distortion.

The output common-mode voltage of the ADA4938-2 is easily

set with the VCM pin of the AD9641 (see Figure 49), and the

driver can be configured in a Sallen-Key filter topology to provide

band limiting of the input signal.

15pF

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of the AD9641. For applications where

SNR is a key parameter, differential double balun coupling is the

recommended input configuration (see Figure 51). In this configu-

ration, the input is ac-coupled, and the common-mode voltage

(VCM) is provided to each input through a 33 Ω resistor. These

resistors compensate for losses in the input baluns to provide

a 50 Ω impedance to the driver.

200Ω

33Ω

5pF

15Ω

90Ω

VIN–

VIN+

AVDD

ADC

VCM

76.8Ω

VIN

ADA4938-2

0.1µF

33Ω

120Ω

15pF

200Ω

Figure 49. Differential Input Configuration Using the ADA4938-2

For baseband applications in which SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown in Figure 50. To bias the

analog input, the voltage of VCM can be connected to the

center tap of the secondary winding of the transformer.

In the double balun and transformer configurations, the value

of the input capacitors and resistors is dependent on the input

frequency and source impedance. Based on these parameters,

the value of the input resistors and capacitors may need to be

adjusted, or some components may need to be removed. Table 9

displays recommended values to set the RC network for different

input frequency ranges. However, these values are dependent on

the input signal and bandwidth and should be used only as

a starting guide.

C2

R3

R2

VIN+

R1

2V p-p

49.9Ω

C1

R1

ADC

VCM

An alternative to using a transformer-coupled input at frequencies

in the second Nyquist zone is to use the AD8376 variable gain

amplifier. An example drive circuit including a band-pass filter

is shown in Figure 52. See the AD8376 data sheet for more

information.

R2

VIN–

0.1µF

R3

C2

Figure 50. Differential Transformer-Coupled Configuration

C2

R3

0.1µF

R1

R2

VIN+

VIN–

2V p-p

33Ω

P

S

P

C1

R1

ADC

A

0.1µF

VCM

R3

C2

Figure 51. Differential Double Balun Input Configuration

Table 9. Example RC Network

Frequency Range (MHz)

R1 Series (Ω Each)

C1 Differential (pF)

R2 Series (Ω Each)

C2 Shunt (pF Each)

R3 Shunt (Ω Each)

ꢀ to 1ꢀꢀ

1ꢀꢀ to ±5ꢀ

33

15

8.±

3.9

ꢀ

8.±

Open

49.9

Open

1000pF 180nH 220nH

1µH

165Ω

VPOS

15pF

AD8376

5.1pF 3.9pF

301Ω

VCM

1nF

165Ω

1nF

1µH

68nH

AD9641

180nH 220nH

1000pF

NOTES

1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS

WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).

2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER

CENTERED AT 140MHz.

Figure 52. Differential Input Configuration Using the AD8376

Rev. B | Page 18 of 36

Data Sheet

AD9641

The RF balun configuration is recommended for clock frequencies

between 125 MHz and 640 MHz, and the RF transformer is

recommended for clock frequencies from 40 MHz to 200 MHz.

The back-to-back Schottky diodes across the transformer/balun

secondary limit clock excursions into the AD9641 to approxi-

mately 0.8 V p-p differential.

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9641.

The input full-scale range can be adjusted through the SPI port by

adjusting Bit 0 through Bit 4 of Register 0x18. These bits can be

used to change the full-scale value between 1.383 V p-p and

2.087 V p-p in 0.022 V steps, as shown in Table 17.

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9641 while

preserving the fast rise and fall times of the signal that are

critical to a low jitter performance.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9641 sample clock inputs,

CLK+ and CLK−, should be clocked with a differential signal.

The signal is typically ac-coupled into the CLK+ and CLK− pins

by means of a transformer or a passive component configuration.

These pins are biased internally (see Figure 53) and require no

external bias. If the inputs are floated, the CLK− pin is pulled low

to prevent spurious clocking.

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 56. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/

AD9520/AD9522 clock drivers offer excellent jitter performance.

AVDD

0.1µF

0.9V

CLOCK

INPUT

CLK+

ADC

CLK+

CLK–

AD95xx

PECL DRIVER

100Ω

0.1µF

CLOCK

INPUT

4pF

CLK–

240Ω

50kΩ

Figure 56. Differential PECL Sample Clock (Up to 640 MHz)

Figure 53. Equivalent Clock Input Circuit

A third option is to ac-couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 57. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/

AD9518/AD9520/AD9522 clock drivers offer excellent jitter

performance.

Clock Input Options

The AD9641 has a very flexible clock input structure. Clock input

can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of

the type of signal being used, clock source jitter is of the most

concern, as described in the Jitter Considerations section. The

minimum conversion rate of the AD9641 is 40 MSPS. At clock

rates below 40 MSPS, dynamic performance of the AD9641 can

degrade.

0.1µF

CLOCK

INPUT

CLK+

ADC

AD95xx

LVDS DRIVER

100Ω

Figure 54 and Figure 55 show two preferred methods for clocking

the AD9641 (at clock rates up to 640 MHz). A low jitter clock

source is converted from a single-ended signal to a differential

signal using either an RF balun or an RF transformer.

0.1µF

CLOCK

INPUT

CLK–

50kΩ

Figure 57. Differential LVDS Sample Clock (Up to 640 MHz)

®

Mini-Circuits

ADC

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended CMOS signal. In such applica-

tions, the CLK+ pin should be driven directly from a CMOS gate,

and the CLK− pin should be bypassed to ground with a 0.1 μF

capacitor (see Figure 58).

ADT1-1WT, 1:1Z

0.1µF

XFMR

CLOCK

INPUT

CLK+

CLK–

100Ω

50Ω

0.1µF

SCHOTTKY

DIODES:

HSMS2822

0.1µF

V

CC

OPTIONAL

100Ω

0.1µF

Figure 54. Transformer-Coupled Differential Clock (Up to 200 MHz)

0.1µF

1kΩ

AD95xx

CMOS DRIVER

CLOCK

INPUT

CLK+

ADC

50Ω*

ADC

1nF

50Ω

1nF

0.1µF

CLK–

CLOCK

INPUT

CLK+

CLK–

0.1µF

*50Ω RESISTOR IS OPTIONAL.

Figure 58. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

SCHOTTKY

DIODES:

HSMS2822

Figure 55. Balun-Coupled Differential Clock (Up to 640 MHz)

Rev. B | Page 19 of 36

AD9641

Data Sheet

Input Clock Divider

In the equation, the rms aperture jitter represents the clock input

jitter specification. IF undersampling applications are particularly

sensitive to jitter, as illustrated in Figure 59. The measured curve

in Figure 59 was taken using an ADC clock source with approxi-

mately 65 f_Sof jitter, which combines with the 125 f_Sof jitter

inherent in the AD9641 to produce the result shown.

75

The AD9641 contains an input clock divider with the ability

to divide the input clock by integer values between 1 and 8.

For divide ratios of 1, 2, or 4, the duty cycle stabilizer (DCS)

is optional. For other divide ratios, such as 3, 5, 6, 7, and 8, the

DCS must be enabled for proper part operation.

The AD9641 clock divider can be synchronized using the external

SYNC input. Bit 1 and Bit 2 of Register 0x03A allow the clock

divider to be resynchronized on every SYNC signal or only on

the first SYNC signal after the register is written. A valid SYNC

causes the clock divider to reset to its initial state. This synchro-

nization feature allows multiple parts to have their clock dividers

aligned to guarantee simultaneous input sampling.

70

0.05ps

65

0.2ps

0.5ps

1ps

1.5ps

MEASURED

60

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate

a variety of internal timing signals and, as a result, may be

sensitive to clock duty cycle. The AD9641 requires a tight

tolerance on the clock duty cycle to maintain dynamic

performance characteristics.

55

50

1

10

100

1000

INPUT FREQUENCY (MHz)

Figure 59. SNR vs. Input Frequency and Jitter

The AD9641 contains a DCS that retimes the nonsampling

(falling) edge, providing an internal clock signal with a nominal

50% duty cycle. This allows the user to provide a wide range of

clock input duty cycles without affecting the performance of the

AD9641. Noise and distortion performance are nearly flat for a

wide range of duty cycles with the DCS enabled.

The clock input should be treated as an analog signal in cases in

which aperture jitter may affect the dynamic range of the AD9641.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter, crystal-controlled oscillators make

the best clock sources. If the clock is generated from another type

of source (by gating, dividing, or another method), it should be

retimed by the original clock at the last step.

Jitter in the rising edge of the input is still of paramount concern

and is not easily reduced by the internal stabilization circuit.

The duty cycle control loop does not function for clock rates

of less than 20 MHz, nominally. The loop has a time constant

associated with it that must be considered in applications in

which the clock rate can change dynamically. A wait time of

1.5 μs to 5 μs is required after a dynamic clock frequency

increase or decrease before the DCS loop is relocked to the

input signal. During the time when the loop is not locked, the

DCS loop is bypassed, and internal device timing is dependent

on the duty cycle of the input clock signal. In such applications,

it may be appropriate to disable the DCS. In all other applications,

enabling the DCS circuit is recommended to maximize ac

performance.

Refer to the AN-501 Application Note and the AN-756 Application

Note for more information about jitter performance as it relates

to ADCs.

CHIP SYNCHRONIZATION

The AD9641 has a SYNC input that offers the user flexible

synchronization options for synchronizing the clock divider.

The clock divider sync feature is useful for guaranteeing synchro-

nized sample clocks across multiple ADCs. The input clock

divider can be enabled to synchronize on a single occurrence of

the SYNC signal or on every occurrence.

The SYNC input is internally synchronized to the sample clock;

however, to ensure that there is no timing uncertainty between

multiple parts, the SYNC input signal should be externally syn-

chronized to the input clock signal, meeting the setup and hold

times shown in Table 5. The SYNC input should be driven using

a single-ended CMOS-type signal.

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. For inputs near full scale, the degradation in

SNR from the low frequency SNR (SNR_LF) at a given input

frequency (f_INPUT) due to jitter (t_JRMS) can be calculated by

SNR_HF= −10 log[(2π × f_INPUT× t_JRMS)²+ 10 ^{(SNR /10)}

]

LF

Rev. B | Page ±ꢀ of 36

Data Sheet

AD9641

POWER DISSIPATION AND STANDBY MODE

DIGITAL OUTPUTS

JESD204A Transmit Top Level Description

As shown in Figure 60, the power dissipated by the AD9641

varies with its sample rate. The data in Figure 60 was taken

in JESD204A serial output mode, using the same operating

conditions as those used for the Typical Performance

Characteristics.

The AD9641 digital output complies with the JEDEC Standard

No. 204A (JESD204A), which describes a serial interface for

data converters. JESD204A uses 8b/10b encoding, as well as

optional scrambling. K28.5 and K28.7 comma symbols are used

for frame synchronization, and the K28.3 control symbol is used

for lane synchronization. The receiver is required to lock onto

the serial data stream and recover the clock with the use of a PLL.

For details on the output interface, users are encouraged to refer

to the JESD204A standard.

0.30

0.20

0.10

0

0.15

0.10

0.05

0

TOTAL

POWER

The JESD204A link is described according to the following

nomenclature:

I

AVDD



S = samples transmitted per single converter per

frame cycle



M = number of converters per converter device (link)

L = number of lanes per converter device (link)

N = converter resolution

N’ = total number of bits per sample

CF = number of control words per frame clock cycle per

converter device (link)

I

DRVDD

40

50

60

70

80

ENCODE FREQUENCY (MSPS)

Figure 60. Power and Current vs. Encode Frequency

The AD9641 is placed in power-down mode using Register 0x08,

Bits[1:0] or by asserting the PDWN pin high. In this state, the

ADC typically dissipates 7 mW. During power-down, the output

drivers are placed in a high impedance state. Pulling the PDWN

pin low returns the AD9641 to its normal operating mode. Low

power dissipation in power-down mode is achieved by shutting

down the reference, reference buffer, biasing networks, and clock.

Internal capacitors are discharged when entering power-down

mode and then must be recharged when returning to normal

operation.



CS = number of control bits per conversion sample

K = number of frames per multiframe

HD = high density mode

F = number of octets per frame

C = control bit (overrange, overflow, underflow)

T = tail bit

SCR = scrambling enabled

FCHK = checksum

The JESD204A block for the AD9641 is designed to support the

configurations described in Table 10.

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode (Register 0x08, Bits[1:0]).

Standby mode allows the user to keep the internal reference

circuitry powered and the JESD204A outputs running when

faster wake-up times are required.

Table 10. AD9641 JESD204A Typical Configuration

Configuration

JESD204A Link Settings

M = 1; L = 1; S = 1; F = ±

N’ = 16; CF = ꢀ

Comments

Maximum sample rate = 8ꢀ or 155 MSPS

One Converter

One JESD±ꢀ4A Link

One Lane Per Link

CS = ꢀ, 1, ±; K = N/A

SCR = ꢀ, 1; HD = ꢀ

Rev. B | Page ±1 of 36

AD9641

Data Sheet

Figure 61 shows a simplified block diagram of the JESD204A link

for the AD9641. The 8b/10b encoding works by taking eight bits of

data (an octet) and encoding them into a 10-bit symbol. By default

in the AD9641, the 14-bit converter word is broken into two octets.

Bit 13 through Bit 6 are in the first octet. The second octet contains

Bit 5 through Bit 0 and two tail bits. The MSB of the tail bits can

also be used to indicate an out-of-range condition. The tail bits

are configured using the JESD204A link control in JESD204A

Link Control Register 1, Address 0x60, Bit 6.

The two resulting octets are optionally scrambled and encoded

into their corresponding 10-bit code. The scrambler function is

controlled by the JESD204A scrambling and lane configuration

register, Address 0x06E, Bit 7. Figure 62 shows how the 14-bit

data is taken from the ADC, the tail bits are added, the two octets

are scrambled, and the octets are encoded into two 10-bit symbols.

Figure 63 illustrates the default data format.

The scrambler uses a self-synchronizing, polynomial-based

algorithm defined by the following equation: 1 + x¹⁴+ x¹⁵. The

descrambler in the receiver should be a self-synchronizing

version of the scrambler polynomial. Figure 64 shows the

corresponding receiver data path.

LINK

DSYNC

AD9641 ADC

OUTPUT

LANE

CONVERTER

INPUT

CONVERTER

SAMPLE

JESD204 A LINK

(M = 0, 1; L = 0, 1)

CONVERTER

Refer to JEDEC Standard No. 204A, April 2008, Section 5.1, for

complete transport layer and data format details. See Section 5.2

for a complete explanation of scrambling and descrambling.

Figure 61. AD9641 Transmit Link Simplified Block Diagram

DATA

FROM

ADC

FRAME

ASSEMBLER

(ADD TAIL BITS)

OPTIONAL

SCRAMBLER

14 15

8B/10B

ENCODER

TO

RECEIVER

1 + x + x

Figure 62. ADC Output Data Path

WORD 0[13:6]

SYMBOL 0[9:0]

FRAME 0

FRAME 1

WORD 0[5:0], TAIL BITS[1:0]

WORD 1[13:6]

SYMBOL 1[9:0]

SYMBOL 2[9:0]

SYMBOL 3[9:0]

TIME

WORD 1[5:0], TAIL BITS[1:0]

Figure 63. 14-Bit Data Transmission with Tail Bits

OPTIONAL

8B/10B

DECODER

FRAME

ALIGNMENT

DATA

OUT

FROM

TRANSMITTER

DESCRAMBLER

14 15

1 + x + x

Figure 64. Required Receiver Data Path

Rev. B | Page ±± of 36

Data Sheet

AD9641

Initial Frame Synchronization

A 100 Ω differential termination resistor should be placed at each

receiver input to result in a nominal 400 mV peak-to-peak swing at

the receiver (see Figure 65). Alternatively, single-ended 50 Ω

termination can be used. When single-ended termination is

used, the termination voltage should be DRVDD/2; otherwise,

ac coupling capacitors can be used to terminate to any single-

ended voltage.

The serial interface must synchronize to the frame boundaries

before data can be properly decoded. The JESD204A standard

has a synchronization routine to identify the frame boundary.

When the DSYNC pin is taken low for at least two clock cycles,

the AD9641 enters the code group synchronization mode. The

AD9641 transmits the K28.5 comma symbol until the receiver

achieves synchronization. The receiver should then deassert the

sync signal (take DSYNC high), and the AD9641 begins the initial

lane alignment sequence (when enabled through Address 0x60,

Bits[3:2]) and, subsequently, begins transmitting sample data. The

first non-K28.5 symbol corresponds to the first octet in a frame.

The AD9641 digital outputs can interface with custom ASICs and

FPGA receivers, providing superior switching performance in

noisy environments. Single point-to-point network topologies are

recommended with a single differential 100 Ω termination resistor

placed as close as possible to the receiver logic. The common

mode of the digital output automatically biases itself to half the

supply of the receiver (that is, the common-mode voltage is 0.9 V

for a receiver supply of 1.8 V) if dc-coupled connecting is used

(see Figure 66).

The DSYNC input can be driven either from a differential LVDS

source or by using a single-ended CMOS driver circuit. The

DSYNC input default to LVDS mode but can be set to CMOS

mode by setting Bit 4 in Address 0x61. If it is driven differen-

tially from an LVDS source, an external 100 Ω termination

resistor should be provided. If the DSYNC input is driven single

endedly, the CMOS signal should be connected to the DSYNC+

signal, and the DSYNC− signal should be left disconnected.

100Ω

DIFFERENTIAL

TRACE PAIR

DRVDD

DOUT + x

RECEIVER

100Ω

DOUT – x

Frame and Lane Alignment Monitoring and Correction

Frame alignment monitoring and correction is part of the

JESD204A specification. The 14-bit word requires two octets to

transmit all the data. The two octets (MSB and LSB), where

F = 2, make up a frame. During normal operating conditions,

frame alignment is monitored via alignment characters, which

are inserted under certain conditions at the end of a frame.

Table 11 summarizes the conditions for character insertion,

along with the expected characters under the various operation

modes. If lane synchronization is enabled, the replacement

character value depends on whether the octet is at the end of

a frame or at the end of a multiframe.

V

= DRVDD/2

OUTPUT SWING = 400mV p-p

CM

Figure 65. AC-Coupled Digital Output Termination Example

V

RXCM

100Ω

DIFFERENTIAL

TRACE PAIR

DRVDD

0.1µF

DOUT+x

RECEIVER

= Rx V

100Ω

OR

DOUT–x

V

OUTPUT SWING = 400mV p-p

CM

Based on the operating mode, the receiver can ensure that it is

still synchronized to the frame boundary by correctly receiving

the replace characters.

Figure 66. DC-Coupled Digital Output Termination Example

For receiver logic that is not within the bounds of the DRVDD

supply, an ac-coupled connection should be used. Place a 0.1 μF

capacitor on each output pin and derive a 100 Ω differential

termination close to the receiver side.

Digital Outputs and Timing

The AD9641 has differential digital outputs that power up

by default. The driver current is derived on-chip and sets the

output current at each output equal to a nominal 4 mA. Each

output presents a 100 Ω dynamic internal termination to reduce

unwanted reflections.

If there is no far-end receiver termination or if there is poor

differential trace routing, timing errors may result. To avoid

such timing errors, it is recommended that the trace length be

less than 8 inches and that the differential output traces be close

together and at equal lengths.

Table 11. AD9641 JESD204A Frame Alignment Monitoring and Correction Replacement Characters

Lane

Synchronization

Replacement

Character

Scrambling

Character to Be Replaced

Last Octet in Multiframe

Off

On

Off

On

Off

Last octet in frame repeated from previous frame

Last octet in frame equals D±8.7 (ꢀxFC)

Last octet in frame equals D±8.3 (ꢀx7C)

Last octet in frame equals D±8.7 (ꢀx7C)

No

Yes

K±8.7 (ꢀxFC)

K±8.3 (ꢀx7C)

K±8.7 (ꢀxFC)

K±8.3 (ꢀx7C)

K±8.7 (ꢀxFC)

Not applicable

No

Yes

Not applicable

Rev. B | Page ±3 of 36

AD9641

Data Sheet

Figure 67 shows an example of the digital output (default) data

eye and a time interval error (TIE) jitter histogram.

The lowest typical clock rate is 40 MSPS. For clock rates slower

than 60 MSPS, Bit 3 should be set to 0 in the PLL control register

(Address 0x21 in Table 17). This option sets the PLL loop band-

width to use clock rates between 40 MSPS and 60 MSPS.

Additional SPI options allow the user to further increase the output

driver voltage swing of all four outputs to drive longer trace lengths

(see Address 0x15 in Table 17). Even though this produces sharper

rise and fall times on the data edges and is less prone to bit errors,

the power dissipation of the DRVDD supply increases when this

option is used. See the Memory Map section for more details.

Setting Bit 2 in the output mode register (Address 0x14) allows

the user to invert the digital samples from their nominal state.

As shown in Figure 63, the MSB is transmitted first in the data

output serial stream.

The format of the output data is twos complement, by default.

Table 12 provides an example of this output coding format.

To change the output data format to offset binary or Gray code,

see the Memory Map section (Address 0x14 in Table 17).

WIDTH@BER1: BATHTUB

HEIGHT1: EYE DIAGRAM

PERIOD1: HISTOGRAM

0

10

1

4

3

25,000

20,000

15,000

10,000

5000

–

+

–2

–4

–6

–8

10

400

200

0

–200

–400

–10

–12

–14

10

0.781

EYE: TRANSITION BITS

OFFSET: –0.004

UIS: 8000; 639999, TOTAL: 8000; 639999

0

–600 –400 –200

0

200 400 600

610 615 620 625 630 635

TIME (ps)

–0.5

0

0.5

TIME (ps)

ULS

Figure 67. AD9641-80 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations

WIDTH@BER1: BATHTUB

HEIGHT1: EYE DIAGRAM

PERIOD1: HISTOGRAM

0

10

600

400

4

3

1

–

400k

350k

300k

250k

200k

150k

100k

–2

–4

–6

–8

10

200

0

–200

–400

–600

–10

–12

–14

10

0.75

EYE: TRANSITION BITS

OFFSET: –0.002

UIS: 8000; 1239996, TOTAL: 48000; 7439996

50k

0

–300 –200 –100

100 200 300

305 310 315 320 325 330 335

TIME (ps)

–0.5

0

0.5

0

TIME (ps)

ULS

Figure 68. AD9641-155 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations

Table 12. Digital Output Coding

Code

8191

ꢀ

(VIN+) − (VIN−), Input Span = 1.75 V p-p (V)

Digital Output Twos Complement ([D13:D0])

ꢀ1 1111 1111 1111

ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

+ꢀ.875

ꢀ.ꢀꢀ

−1

−819±

−ꢀ.ꢀꢀꢀ1ꢀ7

−ꢀ.875

11 1111 1111 1111

1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

Rev. B | Page ±4 of 36

Data Sheet

AD9641

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

The AD9641 includes built-in test features designed to enable

verification of the integrity of the channel as well as facilitate

board level debugging. A BIST (built-in self-test) feature is included

that verifies the integrity of the digital datapath of the AD9641.

Various output test options are also provided to place predictable

values on the outputs of the AD9641.

OUTPUT TEST MODES

Digital test patterns can be inserted at various points along the

signal path within the AD9641 as shown in Figure 69. The ability

to inject these signals at several locations facilitates debugging

of the JESD204A serial communication link.

Register 0x0D allows test signals generated at the output of the

ADC core to be fed directly into the input of the serial link. The

output test options available from Register 0x0D are shown in

Table 14. When an output test mode is enabled, the analog

section of the ADC is disconnected from the digital back end

blocks and the test pattern is run through the output formatting

block. Some of the test patterns are subject to output formatting,

and some are not. The seed value for the PN sequence tests can be

forced if the PN reset bits are used to hold the generator in reset

mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can

be performed with or without an analog signal (if present, the

analog signal is ignored), but they do require an encode clock.

BUILT-IN SELF-TEST (BIST)

The BIST is a thorough test of the digital portion of the selected

AD9641 signal path. When enabled, the test runs from an internal

pseudorandom noise (PN) source through the digital datapath

starting at the ADC block output. The BIST sequence runs

for 512 cycles and stops. The BIST signature value is placed in

Register 0x24 and Register 0x25. The outputs are not disconnected

during this test; therefore, the PN sequence can be observed as

it runs. The PN sequence can be continued from its last value or

reset from the beginning, based on the value programmed in

Register 0x0E, Bit 2. The BIST signature result varies based on

the channel configuration.

For more information, see the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

JESD204A TEST PATTERNS

10-BIT

SPI REGISTER 0x62 BITS [5:4] =

01 AND BITS [2:0] ≠ 000

ADC TEST PATTERNS

14-BIT

SPI REGISTER 0x0D

BITS [3:0] ≠ 0000

JESD204A TEST PATTERNS

16-BIT

SPI REGISTER 0x62 BITS [5:4] =

00 AND BITS [2:0] ≠ 000

SERIALIZER

OUTPUT

FRAME

CONSTRUCTION

SCRAMBLER

(OPTIONAL)

8-BIT/10-BIT

ENCODER

JESD204A

SAMPLE

CONSTRUCTION

ADC CORE

FRAMER

TAIL BITS

Figure 69. Block Diagram Showing Digital Test Modes

Rev. B | Page ±5 of 36

AD9641

Data Sheet

There are nine digital output test pattern options available that

can be initiated through the SPI (see Table 14 for the output bit

sequencing options). This feature is useful when validating

receiver capture and timing. Some test patterns have two serial

sequential words and can be alternated in various ways, depending

on the test pattern selected. Note that some patterns do not

adhere to the data format select option. In addition, custom

user-defined test patterns can be assigned in the user pattern

registers (Address 0x19 and Address 0x20).

A description of the PN sequence long and how it is generated

can be found in Section 5.6 of the ITU-T O.150 (05/96) standard.

The only differences are that the starting value must be a specific

value instead of all 1s (see Table 13 for the initial values) and

that the AD9641 inverts the bit stream with relation to the ITU-T

standard.

Table 13. PN Sequence

Initial

Value

First Three Output Samples

(MSB First)

Sequence

The PN sequence short pattern produces a pseudorandom bit

sequence that repeats itself every 2⁹− 1 (511) bits. A description

of the PN sequence short and how it is generated can be found

in Section 5.1 of the ITU-T O.150 (05/96) recommendation.

The only difference is that the starting value must be a specific

value instead of all 1s (see Table 13 for the initial values).

PN Sequence Short ꢀxꢀꢀ9±

PN Sequence Long ꢀx3AFF

ꢀx1±5B, ꢀx3C9A, ꢀx±66ꢀ

ꢀx3FD7, ꢀxꢀꢀꢀ±, ꢀx36Eꢀ

Register 0x62 allows patterns that are similar to those described

in Table 14 to be input at different points along the datapath.

This allows the user to provide predictable output data on the

serial link without it having been manipulated by the internal

formatting logic. Refer to Table 17 for additional information

on the test modes available in Register 0x62.

The PN sequence long pattern produces a pseudorandom bit

sequence that repeats itself every 2²³− 1 (8,388,607) bits.

Table 14. Flexible Output Test Modes from SPI Register 0x0D

Output Test Mode

Bit Sequence

Digital Output Word 1 (Default

Twos Complement Format)

Digital Output Word 2 (Default

Twos Complement Format)

Subject to Data

Format Select

Pattern Name

Off (default)

Midscale short

+Full-scale short

−Full-scale short

Checkerboard

ꢀꢀꢀꢀ

ꢀꢀꢀ1

ꢀꢀ1ꢀ

ꢀꢀ11

ꢀ1ꢀꢀ

ꢀ1ꢀ1

ꢀ11ꢀ

ꢀ111

1ꢀꢀꢀ

Not applicable

Same

Yes

No

Yes

No

ꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

ꢀ1 1111 1111 1111

1ꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ 1ꢀ1ꢀ

Not applicable

Same

ꢀ1 ꢀ1ꢀ1 ꢀ1ꢀ1 ꢀ1ꢀ1

Not applicable

ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ

User data from Register ꢀx19 to

Register ꢀx±ꢀ

PN sequence long

PN sequence short

Not applicable

One-/zero-word toggle 1111 1111 1111

User test mode

User data from Register ꢀx19 to

Yes

Register ꢀx±ꢀ

Not applicable

N

1ꢀꢀ1 to 111ꢀ

1111

Not used

Ramp output

Not applicable

N + 1

No

Rev. B | Page ±6 of 36

Data Sheet

AD9641

SERIAL PORT INTERFACE (SPI)

The AD9641 serial port interface (SPI) allows the user to configure

the converter for specific functions or operations through a

structured register space provided inside the ADC. The SPI

gives the user added flexibility and customization, depending on

the application. Addresses are accessed via the serial port and

can be written to or read from via the port. Memory is organized

into bytes that can be further divided into fields, which are docu-

mented in the Memory Map section. For detailed operational

information, see the AN-877 Application Note, Interfacing to

High Speed ADCs via SPI.

The falling edge of the CSB, in conjunction with the rising edge

of the SCLK, determines the start of the framing. An example of

the serial timing and its definitions can be found in Figure 70

and Table 5.

Other modes involving the CSB are available. The CSB can be

held low indefinitely, which permanently enables the device;

this is called streaming. The CSB can stall high between bytes to

allow for additional external timing. When CSB is tied high, SPI

functions are placed in high impedance mode.

During an instruction phase, a 16-bit instruction is transmitted.

Data follows the instruction phase, and its length is determined

by the W0 and W1 bits.

CONFIGURATION USING THE SPI

Three pins define the SPI of this ADC: the SCLK pin, the SDIO

pin, and the CSB pin (see Table 15). The SCLK (a serial clock) is

used to synchronize the read and write data presented from and

to the ADC. The SDIO (serial data input/output) is a dual-purpose

pin that allows data to be sent to and read from the internal ADC

memory map registers. The CSB (chip select bar) is an active-

low control that enables or disables the read and write cycles.

In addition to word length, the instruction phase determines

whether the serial frame is a read or write operation, allowing

the serial port to be used both to program the chip and to read

the contents of the on-chip memory. The first bit of the first byte in

a multibyte serial data transfer frame indicates whether a read

command or a write command is issued. If the instruction is

a readback operation, performing a readback causes the serial

data input/output (SDIO) pin to change direction from an input

to an output at the appropriate point in the serial frame.

Table 15. Serial Port Interface Pins

Function

SCLK Serial clock. The serial shift clock input, which is used to

synchronize serial interface reads and writes.

SDIO Serial data input/output. A dual-purpose pin that

typically serves as an input or an output, depending on

the instruction being sent and the relative position in the

timing frame.

All data is composed of 8-bit words. Data can be sent in MSB-

first mode or in LSB-first mode. MSB first is the default on

power-up and can be changed via the SPI port configuration

register. For more information about this and other features,

see the AN-877 Application Note, Interfacing to High Speed

ADCs via SPI.

CSB

Chip select bar. An active-low control that gates the read

and write cycles.

t_HIGH

t_CLK

t_DS

t_H

t_S

t_DH

t_LOW

CSB

SCLK DON’T CARE

SDIO DON’T CARE

DON’T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

D5

D4

D3

D2

D1

D0

Figure 70. Serial Port Interface Timing Diagram

Rev. B | Page ±7 of 36

AD9641

Data Sheet

HARDWARE INTERFACE

SPI ACCESSIBLE FEATURES

The pins described in Table 15 comprise the physical interface

between the user programming device and the serial port of

the AD9641. The SCLK pin and the CSB pin function as inputs

when using the SPI interface. The SDIO pin is bidirectional,

functioning as an input during write phases and as an output

during readback.

Table 16 provides a brief description of the general features that

are accessible via the SPI. These features are described in detail

in the AN-877 Application Note, Interfacing to High Speed ADCs

via SPI. The AD9641 part-specific features are described in detail in

the Reading the Memory Map Register Table section.

Table 16. Features Accessible Using the SPI

The SPI interface is flexible enough to be controlled by either

FPGAs or microcontrollers. One method for SPI configuration

is described in detail in the AN-812 Application Note, Micro-

controller-Based Serial Port Interface (SPI) Boot Circuit.

Feature Name

Description

Mode

Allows the user to set either power-down mode

or standby mode

Clock

Allows the user to access the DCS, set the

clock divider, set the clock divider phase, and

enable the sync

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK signal, the CSB signal, and the SDIO signal are typically

asynchronous to the ADC clock, noise from these signals can

degrade converter performance. If the on-board SPI bus is used

for other devices, it may be necessary to provide buffers between

this bus and the AD9641 to prevent these signals from transi-

tioning at the converter inputs during critical sampling periods.

Offset

Allows the user to digitally adjust the

converter offset

Test I/O

Full Scale

JESD±ꢀ4A

Allows the user to set test modes to have

known data on output bits

Allows the user to set the input full-scale

voltage

Allows user to configure the JESD±ꢀ4A output

Rev. B | Page ±8 of 36

Data Sheet

AD9641

MEMORY MAP

READING THE MEMORY MAP REGISTER TABLE

Default Values

After the AD9641 is reset, critical registers are loaded with

default values. The default values for the registers are given in

the memory map register table, Table 17.

Each row in the memory map register table has eight bit locations.

The memory map is roughly divided into four sections: the chip

configuration registers (Address 0x00 to Address 0x02); the transfer

register (Address 0xFF); the ADC functions registers, including

setup, control, and test (Address 0x08 to Address 0x3A); and the

JESD204A configuration registers (Address 0x60 to Address 0x78).

Logic Levels

An explanation of logic level terminology follows:



“Bit is set” is synonymous with “bit is set to Logic 1” or

“writing Logic 1 for the bit.”

The memory map register table (see Table 17) lists the default

hexadecimal value for each hexadecimal address shown. The

column with the heading Bit 7 (MSB) is the start of the default

hexadecimal value given. For example, Address 0x18, the input

span select register, has a hexadecimal default value of 0x00. This

means that Bit 0 through Bit 4 = 0, and the remaining bits are 0s.

This setting is the default reference selection setting. The default

value uses a 1.75 V p-p reference. For more information on this

function and others, see the AN-877 Application Note, Interfacing

to High Speed ADCs via SPI. This application note details the

functions controlled by Register 0x00 to Register 0xFF.



“Clear a bit” is synonymous with “bit is set to Logic 0” or

“writing Logic 0 for the bit.”

Transfer Register Map

Address 0x08 through Address 0x78 are shadowed. Writes to the

addresses do not affect part operation until a transfer command is

issued by writing 0x01 to Address 0xFF, setting the transfer bit.

This allows these registers to be updated internally and simulta-

neously when the transfer bit is set. The internal update takes

place when the transfer bit is set, and the bit autoclears.

Open Locations

All address and bit locations that are not included in Table 17

are not currently supported for this device. Unused bits of a

valid address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), this address location should

not be written.

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 17 are not currently supported for this device.

Table 17. Memory Map Registers

Default Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Chip Configuration Registers

ꢀxꢀꢀ

SPI port

configuration

ꢀ

LSB first

Soft reset

1

Soft reset

LSB first

ꢀ

ꢀx18

Nibbles are

mirrored so

LSB- or MSB-

first mode

registers

correctly,

regardless of

shift mode

ꢀxꢀ1

ꢀxꢀ±

Chip ID

8-bit chip ID[7:ꢀ]

(AD9641 = ꢀx8ꢀ)

(default)

ꢀx8ꢀ

Read only

Chip grade

Open

Speed grade ID

ꢀꢀ = 8ꢀ MSPS

Open

Speed grade

ID used to

differentiate

devices;

1ꢀ = 155 MSPS

read only

Transfer Register

ꢀxFF Transfer

Open

Transfer

ꢀxꢀꢀ

Synchronous

transfer of

data from

the master

shift register

to the slave

Rev. B | Page ±9 of 36

AD9641

Data Sheet

Default Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ADC Functions

ꢀxꢀ8

Power

modes

Open

External

power-

down pin

function

ꢀ = PDWN

1 = STNDBY

Open

Internal power-down mode

ꢀꢀ = normal operation

ꢀ1 = full power-down

1ꢀ = standby

ꢀxꢀꢀ

Determines

various

generic

modes of

chip

operation.

11 = reserved

ꢀxꢀ9

Global clock

Open

Duty cycle

stabilizer

(default)

ꢀxꢀ1

ꢀxꢀA

ꢀxꢀB

PLL status

PLL locked

Open

ꢀxꢀꢀ

Read only.

Clock divide

Input clock divider phase adjust

ꢀꢀꢀ = no delay

Clock divide ratio

ꢀꢀꢀ = divide-by-1

ꢀꢀ1 = divide-by-±

ꢀ1ꢀ = divide-by-3

ꢀ11 = divide-by-4

1ꢀꢀ = divide-by-5

1ꢀ1 = divide-by-6

11ꢀ = divide-by-7

111 = divide-by-8

Clock divide

values other

than ꢀꢀꢀ

cause the

duty cycle

stabilizer to

become

ꢀꢀ1 = 1 input clock cycle

ꢀ1ꢀ = ± input clock cycles

ꢀ11 = 3 input clock cycles

1ꢀꢀ = 4 input clock cycles

1ꢀ1 = 5 input clock cycles

11ꢀ = 6 input clock cycles

111 = 7 input clock cycles

active.

ꢀxꢀD

Test mode

User test

mode

control

ꢀ =

continuous/

repeat

pattern

1 = single

pattern

Open

Reset PN

long gen

Reset PN

short gen

Output test mode

ꢀꢀꢀꢀ = off (default)

ꢀꢀꢀ1 = midscale short

ꢀꢀ1ꢀ = positive FS

ꢀꢀ11 = negative FS

ꢀ1ꢀꢀ = alternating checkerboard

ꢀ1ꢀ1 = PN long sequence

ꢀ11ꢀ = PN short sequence

ꢀ111 = one-/zero- word toggle

1ꢀꢀꢀ = user test mode

1ꢀꢀ1 to 111ꢀ = unused

1111 = ramp output

ꢀxꢀꢀ

When this

register is

set, the

test data is

placed on

the output

pins in place

of normal

data.

ꢀxꢀE

ꢀx1ꢀ

ꢀx14

BIST enable

Offset adjust

Open

Reset BIST

sequence

Open

BIST enable

ꢀxꢀꢀ

ꢀxꢀ1

Offset adjust in LSBs from +31 to −3±

(twos complement format)

Output

mode

Output

disable

Open

Output

invert

Output format

Configures

the outputs

and the

format of

the data.

ꢀꢀ = offset binary

ꢀ1 = twos complement

(default)

ꢀ1 = Gray code

11 = offset binary

ꢀx15

ꢀx18

Output

adjust

Open

Output drive level adjust

11 = 3±ꢀ mV

ꢀꢀ = 4ꢀꢀ mV

1ꢀ = 44ꢀ mV

ꢀ1 = 5ꢀꢀ mV

ꢀxꢀꢀ

Input span

select

Open

Full scale input voltage selection

ꢀ1111 = ±.ꢀ87 V p-p

…

Full-scale

input

adjustment

in ꢀ.ꢀ±± V

steps.

ꢀꢀꢀꢀ1 = 1.77± V p-p

ꢀꢀꢀꢀꢀ = 1.75 V p-p (default)

11111 = 1.7±7 V p-p

…

1ꢀꢀꢀꢀ = 1.383 V p-p

ꢀx19

ꢀx1A

ꢀx1B

ꢀx1C

ꢀx1D

User Test

Pattern 1 LSB

User Test Pattern 1, Bits[7:ꢀ]

User Test Pattern 1, Bits[15:8]

User Test Pattern ±, Bits[7:ꢀ]

User Test Pattern ±, Bits[15:8]

User Test Pattern 3, Bits[7:ꢀ]

ꢀxꢀꢀ

User Test

Pattern 1 MSB

User Test

Pattern ± LSB

User Test

Pattern ± MSB

User Test

Pattern 3 LSB

Rev. B | Page 3ꢀ of 36

Data Sheet

AD9641

Default Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

ꢀx1E

ꢀx1F

ꢀx±ꢀ

ꢀx±1

User Test

Pattern 3 MSB

User Test Pattern 3, Bits[15:8]

User Test Pattern 4, Bits[7:ꢀ]

User Test Pattern 4, Bits[15:8]

ꢀxꢀꢀ

User Test

Pattern 4 LSB

User Test

Pattern 4 MSB

PLL control

Open

PLL low

Open

Bit 3 must

be enabled

if the ADC

clock rate is

<6ꢀ MHz.

encode

rate enable

ꢀx±4

ꢀx±5

BIST

signature LSB

BIST signature, Bits[7:ꢀ]

BIST signature, Bits[15:8]

ꢀxꢀꢀ

Read only.

BIST

Read only.

signature

MSB

ꢀx3A

Sync control

Open

Clock

divider

sync

Master sync

buffer

enable

ꢀxꢀꢀ

divider

next sync

only

enable

JESD±ꢀ4A Configuration Registers

ꢀx6ꢀ

JESD±ꢀ4A

Link Control

Register 1

Open

Serial tail

bit enable

Serial test

sample

enable

Serial lane

synchroni-

zation

Serial lane alignment

sequence mode

ꢀꢀ = disabled

ꢀ1 = enabled

Frame

Serial

transmit link

power- down

alignment

character

insertion

disable

enable

1ꢀ = reserved

11 = always on

test mode

ꢀx61

ꢀx6±

JESD±ꢀ4A

Link Control

Register ±

Local DSYNC mode

ꢀꢀ = individual mode

ꢀ1 = global mode

1ꢀ = DSYNC active mode

11 = DSYNC pin disabled

DSYNC

pin input

inverted

CMOS

DSYNC

input

ꢀ = LVDS

1 = CMOS

Open

Bypass

8b/1ꢀb

encoding

Invert

transmit

bits

Mirror serial

output bits

ꢀxꢀꢀ

JESD±ꢀ4A

Link Control

Register 3

Disable

Open

Link test generation

input selection

ꢀꢀ = 16-bit data injected

at sample input to the

link

ꢀ1 = 1ꢀ-bit data injected

at output of 8b/1ꢀb

encoder

Open

Link test generation mode

ꢀꢀꢀ = normal operation

CHKSUM

ꢀꢀ1 = alternating checkerboard

ꢀ1ꢀ = 1/ꢀ word toggle

ꢀ11 = PN sequence, long

1ꢀꢀ = PN sequence, short

1ꢀ1 = user test pattern data continuous

11ꢀ = user test pattern data single

111 = ramp output

1ꢀ = reserved

11 = reserved

ꢀx63

ꢀx64

JESD±ꢀ4A

Link Control

Register 4

Initial lane assignment sequence repeat count

ꢀxꢀꢀ

JESD±ꢀ4A

device

JESD±ꢀ4A serial device identification (DID) number

identification

number

(DID)

ꢀx65

ꢀx66

ꢀx6E

JESD±ꢀ4A

bank

identification

number

(BID)

Open

JESD±ꢀ4A serial bank identification (BID) number

JESD±ꢀ4A serial lane identification (LID) number

ꢀxꢀꢀ

ꢀx8ꢀ

JESD±ꢀ4A

lane

identification

number

(LID)

JESD±ꢀ4A

scrambler

(SCR) and

lane (L)

Enable

serial

scrambler

mode (SCR)

Open

Serial lane

control

ꢀ = one lane

per link

(L = 1)

configuration

1 = reserved

Rev. B | Page 31 of 36

AD9641

Data Sheet

Default Default

Addr

(Hex)

Register

Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

JESD±ꢀ4A number of octets per frame (F)

(bits are calculated based on the equation F = (M × ±)/L)

Bit 3

Bit 2

Bit 1

ꢀx6F

JESD±ꢀ4A

number of

octets per

frame (F)

ꢀxꢀ1

ꢀxꢀF

Read only.

ꢀx7ꢀ

JESD±ꢀ4A

number of

frames per

multiframe

(K)

Open

JESD±ꢀ4A number of frames per multiframe (K)

ꢀx71

JESD±ꢀ4A

number of

converters

per link per

converter

device (link)

(M)

Open

Number of

converters

per link

per device

ꢀ = link

ꢀxꢀꢀ

Read only.

connected to

one ADC

(M = 1)

1 = reserved

ꢀx7±

JESD ±ꢀ4A

converter

resolution (N)

and control

bits per

Number of control bits per

sample (CS)

Open

Converter resolution (N) (read only)

ꢀx4D

ꢀꢀ = no control bits

(CS = ꢀ)

ꢀ1 = one control bit

(CS = 1)

sample (CS)

1ꢀ = two control bits

(CS = ±)

11 = unused

ꢀx73

ꢀx74

JESD±ꢀ4A

total bits per

sample (N’)

Open

Total number of bits per sample (N’) (read only)

ꢀxꢀF

ꢀxꢀꢀ

Read only.

JESD±ꢀ4A

samples per

converter (S)

per frame

cycle

Open

Samples per converter per frame cycle (S) (read only)

(always 1 for the AD9641)

ꢀx75

ꢀx76

JESD±ꢀ4A

HD and CF

configuration

Enable HD

(high

density)

format

Open

Number of control words per frame clock cycle per link (CF)

(always ꢀ for the AD9641 (read only))

ꢀxꢀꢀ

JESD±ꢀ4A

Serial

Serial Reserved Field 1 (RES1)

(these registers are available for customer use)

Reserved

Field 1

(RES1)

ꢀx77

ꢀx78

JESD±ꢀ4A

Serial

Reserved

Field ±

Serial Reserved Field ± (RES±)

(these registers are available for customer use)

ꢀxꢀꢀ

(RES±)

JESD±ꢀ4A

checksum

value for

Serial checksum value for lane (FCHK)

Read only

lane (FCHK)

receives and to ignore the rest. The clock divider sync enable bit

(Address 0x3A, Bit 1) resets after it syncs.

MEMORY MAP REGISTER DESCRIPTIONS

For additional information about functions controlled in

Register 0x00 to Register 0x25, see the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal

is enabled when Bit 1 and Bit 0 are high. This is in continuous

sync mode.

Sync Control (Address 0x3A)

Bits[7:3]—Open

Bit 0—Master Sync Buffer Enable

Bit 2—Clock Divider Next Sync Only

Bit 0 must be high to enable any of the sync functions. If the

sync capability is not used, this bit should remain low to

conserve power.

If the master sync buffer enable bit (Address 0x3A, Bit 0) and

the clock divider sync enable bit (Address 0x3A, Bit 1) are high,

Bit 2 allows the clock divider to sync to the first sync pulse it

Rev. B | Page 3± of 36

Data Sheet

AD9641

JESD204A Link Control Register 1 (Address 0x60)

Bit 7—Open

Bit 2—Bypass 8b/10b Encoding

If this bit is set, the 8b/10b encoding is bypassed and the most

significant bits are set to 0.

Bit 6—Serial Tail Bit Enable

Bit 1—Invert Transmit Bits

If this bit is set, unused tail bits are padded with a pseudo random

number sequence from a 31-bit LFSR (see JESD204A 5.1.4).

Setting this bit inverts the 10 serial output bits. This effectively

inverts the output signals.

Bit 5—Serial Test Sample Enable

Bit 0—Mirror Serial Output Bits

If set, JESD204A test samples are enabled, and the transport

layer test sample sequence (as specified in JESD204A section

5.1.6.2) sent on all link lanes.

Setting this bit reverses the order of the 10b outputs.

JESD204A Link Control Register 3 (Address 0x62)

Bit 4—Serial Lane Synchronization Enable

Bit 7—Disable CHKSUM

If this bit is set, lane synchronization is enabled. Both sides

perform lane sync; frame alignment character insertion uses

either /K28.3/ or /K28.7/ control characters (see JESD204A

5.3.3.4).

Setting this bit high disables the CHKSUM configuration

parameter. (For testing purposes only.)

Bit 6—Open

Bits[5:4]—Link Test Generation Input Selection

Bits[3:2]—Serial Lane Alignment Sequence Mode

00: 16-bit test generation data injected at sample input to the link.

01: 10-bit test generation data injected at output of 8b/10b

encoder (at input to PHY).

10: reserved.

11: reserved.

00: initial lane alignment sequence disabled.

01: initial lane alignment sequence enabled.

10: reserved.

11: initial lane alignment sequence always on test mode; JESD204A

data link layer test mode where repeated lane alignment sequence is

sent on all lanes.

Bit 3—Open

Bit 1—Frame Alignment Character Insertion Disable

Bits[2:0]—Link Test Generation Mode

If Bit 1 is set, the frame alignment character insertion is

disabled per JESD204A section 5.3.3.4.

000: normal operation (test mode disabled).

001: alternating checkerboard.

010: 1/0 word toggle.

011: PN sequence, long.

100: PN sequence, short.

Bit 0—Serial Transmit Link Power-Down

If Bit 0 is set high, the serial transmit link is held in reset with its

clock gated off. The JESD204A transmitter should be powered

down when changing any of the link configuration bits.

101: continuous/repeat user test mode. The most significant bits

from the user pattern (1, 2, 3, 4) are placed on the output for one

clock cycle and then repeated. (Output User Pattern 1, 2, 3, 4,

1, 2, 3, 4, 1, 2, 3, 4….)

110: single user test mode. The most significant bits from the user

pattern (1, 2, 3, 4) are placed on the output for one clock cycle,

and then all zeros are output. (Output User Pattern 1, 2, 3, 4;

then output all zeros.)

JESD204A Link Control Register 2 (Address 0x61)

Bits[7:6]—Local DSYNC Mode

00: individual/separate mode. Each link is controlled by a

separate DSYNC pin that independently controls code group

synchronization.

01: global mode. Any DSYNC signal causes the link to begin

code group synchronization.

111: ramp output.

JESD204A Link Control Register 4 (Address 0x63)

10: DSYNC active mode. The DSYNC signal is active; force

code group synchronization.

Bits[7:0]—Initial Lane Alignment Sequence Repeat Count

Bits[7:0] specify the number of times the initial lane alignment

sequence (ILAS) is repeated. If 0 is programmed, the ILAS does

not repeat. If 1 is programmed, the ILAS repeats one time, and

so on. See Register 0x60, Bits[3:2] to enable the ILAS and for

a test mode to continuously enable the initial lane alignment

sequence.

11: DSYNC pin disabled.

Bit 5—DSYNC Pin Input Inverted

If this bit is set, the DSYNC pin of the link is inverted (active

high).

Bit 4—CMOS DSYNC Input

0: LVDS differential pair DSYNC input (default).

1: CMOS single-ended DSYNC input.

Bit 3—Open

JESD204A Device Identification (DID) Number

(Address 0x64)

Bits[7:0]—Serial Device Identification (DID) Number

Rev. B | Page 33 of 36

AD9641

Data Sheet

Bit 5—Open

JESD204A Bank Identification (BID) Number (Address 0x65)

Bits[7:4]—Open

Bits [4:0]—Converter Resolution (N).

Read only bits showing the converter resolution (reads back 13

(0xD) for 14-bit resolution).

Bits[3:0]—Serial Bank Identification (BID) Number

JESD204A Lane Identification (LID) Number (Address 0x66)

Bits[7:5]—Open

JESD204A Total Number of Bits per Sample (N’)

(Address 0x73)

Bits[4:0]—Serial Lane Identification (LID) Number for

Lane

Bits[7:5]—Reserved

Bits[4:0]—Total Number of Bits per Sample (N’)

JESD204A Scrambler (SCR) and Lane (L) Configuration

(Address 0x6E)

Read only bits showing the total number of bits per sample,

minus 1 (reads back 15 (0xF) for 16 bits per sample).

Bit 7—Enable Serial Scrambler Mode (SCR)

Setting this bit high enables the scrambler (SCR = 1).

Bits[6:1]—Open.

JESD204A Samples per Converter per Frame Cycle (S)

(Address 0x74)

Bits[7:5]—Open

Bit 0—Serial Lane Control.

Bits[4:0]—Samples per Converter per Frame Cycle (S)

0: one lane per link (L = 1).

1: 11111 = reserved.

Read only bits showing the number of samples per converter

frame cycle, minus 1 (reads back 0 (0x0) for one sample per

converter frame).

JESD204A Number of Octets per Frame (Address 0x6F,

Read Only)

JESD204A HD and CF Configuration (Address 0x75)

Bits[7:0]—Number of Octets per Frame (F)

Bit 7—High Density Format Enabled (Read Only)

The readback from this register is calculated from the following

equation: F = (M × 2)/L.

Read only bit. Always 0 in the AD9641.

Bits[6:5]—Open

Valid values for F for the AD9641 are

F = 2, with M = 1 and L = 1

Bits[4:0]—Number of Control Words per Frame Clock

Cycle per Converter Device (Link) (CF)

JESD204A Number of Frames per Multiframe (K)

(Address 0x70)

Read only bits. Reads back 0x0 for the AD9641.

JESD204A Serial Reserved Field 1 (Address 0x76)

Bits[7:5]—Open

Bits[7:0]—Serial Reserved Field 1 (RES1)

Bits[4:0]—Number of Frames per Multiframe (K)

This read/write register is available for customer use.

JESD204A Number of Converters per Converter Device

(Link) (M) (Address 0x71)

JESD204A Serial Reserved Field 2 (Address 0x77)

Bits[7:1]—Open

Bits[7:0]—Serial Reserved Field 2 (RES2)

Bit 0—Number of Converters per Converter Device (Link)

(M)

This read/write register is available for customer use.

JESD204A Serial Checksum Value for Lane (Address 0x78)

0: link connected to one ADC. Only primary input used (M = 1).

1: reserved.

Bits[7:0]—Checksum Value for Lane

This read only register is automatically calculated for the lane.

Sum (all link configuration parameters for the lane) MOD 256.

JESD204A Converter Resolution (N) and Control Bits per

Sample (CS) (Address 0x72)

Bits[7:6]—Number of Control Bits per Sample (CS)

00: no control bits sent per sample (CS = 0).

01: one control bit sent per sample—overrange bit enabled

(CS = 1).

10: two control bits sent per sample—overflow/underflow bits

enabled (CS = 2).

11: unused.

Rev. B | Page 34 of 36

Data Sheet

AD9641

APPLICATIONS INFORMATION

The copper plane should have several vias to achieve the lowest

possible resistive thermal path for heat dissipation to flow through

the bottom of the PCB. These vias should be filled or plugged to

prevent solder wicking through the vias, which can compromise

the connection.

DESIGN GUIDELINES

Before starting design and layout of the AD9641 as a system,

it is recommended that the designer become familiar with these

guidelines, which discuss the special circuit connections and

layout requirements that are needed for certain pins.

To maximize the coverage and adhesion between the ADC and

the PCB, a silkscreen should be overlaid to partition the continuous

plane on the PCB into several uniform sections. This provides

several tie points between the ADC and the PCB during the reflow

process. Using one continuous plane with no partitions guarantees

only one tie point between the ADC and the PCB. For detailed

information about packaging and PCB layout of chip scale

packages, see the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP), at www.analog.com.

Power and Ground Recommendations

When connecting power to the AD9641, it is recommended

that two separate 1.8 V supplies be used. Use one supply for

analog (AVDD), and use a separate supply for the digital outputs

(DRVDD). For both AVDD and DRVDD, several different

decoupling capacitors should be used to cover both high and

low frequencies. Place these capacitors close to the point of entry

at the PCB level and close to the pins of the part, with minimal

trace length.

A single PCB ground plane should be sufficient when using the

AD9641. With proper decoupling and smart partitioning of the

PCB analog, digital, and clock sections, optimum performance

is easily achieved.

VCM

The VCM pin should be decoupled to ground with a 0.1 μF

capacitor, as shown in Figure 50.

SPI Port

Exposed Paddle Thermal Heat Slug Recommendations

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Because the

SCLK, CSB, and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade converter

performance. If the on-board SPI bus is used for other devices,

it may be necessary to provide buffers between this bus and the

AD9641 to keep these signals from transitioning at the converter

inputs during critical sampling periods.

It is mandatory that the exposed paddle on the underside of the

ADC be connected to analog ground (AGND) to achieve the

best electrical and thermal performance. A continuous, exposed

(no solder mask) copper plane on the PCB should mate to the

AD9641 exposed paddle, Pin 0.

Rev. B | Page 35 of 36

AD9641

Data Sheet

OUTLINE DIMENSIONS

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

25

32

24

1

0.50

BSC

*

3.75

EXPOSED

PAD

3.60 SQ

3.55

17

8

16

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

*

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5

WITH EXCEPTION TO EXPOSED PAD DIMENSION.

Figure 71. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-12)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-3±-1±

AD9641BCPZ-8ꢀ

AD9641BCPZRL7-8ꢀ

AD9641BCPZ-155

AD9641BCPZRL7-155

AD9641-8ꢀKITZ

AD9641-155KITZ

−4ꢀ°C to +85°C

3±-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

Evaluation Board Kit

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D09210-0-1/12(B)

Rev. B | Page 36 of 36


型号：	AD9641BCPZRL7-155
厂家：	ADI
描述：	14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC) 转换器
文件：	总37页 (文件大小：2087K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9641BCPZRL7-155 [ADI]

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