AD96606 [ADI]
200 MHz Laser Diode Driver with Light Power Control; 200 MHz的激光二极管驱动器与光功率控制
| 型号： | AD96606 |
| 厂家： | 
ADI |
| 描述： | 200 MHz Laser Diode Driver with Light Power Control |
| 文件： | 总12页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
200 MHz Laser Diode Driver
with Light Power Control
a
AD9660
FUNCTIONAL BLOCK DIAGRAM
FEATURES
1.5 ns Rise/2.0 ns Fall Times
Output Current: 180 mA @ 3 V, 200 mA @ 2.5 V
Bias Current: 90 mA @ 3 V
Modulation Current: 60 mA @ 3 V
Offset Current: 30 mA @ 3 V
Single +5 V Power Supply
WRITE
PULSE
WRITE
CALIBRATE
OUTPUT
OUTPUT
DRIVER
WRITE
LEVEL
T/H
V:1
LASER
DIODE
SENSE
INPUT
Switching Rate: 200 MHz
Onboard Light Power Control Loops
TRANSIMPEDANCE
AMPLIFIER
PHOTO
DETECTOR
DIODE
APPLICATIONS
BIAS
LEVEL
OUTPUT
DRIVER
BIAS
T/H
V:1
Laser Printers and Copiers
Optical Disk Drives
FO Datacomm
BIAS
CAL
AD9660
GENERAL DESCRIPTION
The driver output provides up to 180 mA of current @ 3 V,
90 mA of BIAS current, 60 mA of modulation current, and
30 mA of offset current. The onboard disable circuit turns off
the output drivers and returns the light power control loops to a
safe state.
The AD9660 is a highly integrated driver for laser diode appli-
cations such as optical disk drives, printers, and copiers. The
AD9660 gets feedback from an external photo detector and in-
cludes two analog feedback loops to allow users to set “bias”
and “write” (for optical disk drives) power levels of the laser,
and switch between the two power levels at up to 200 MHz.
Output rise and fall times are typically 1.5 ns and 2.0 ns to
complement printer applications that use image enhancing tech-
niques such as pulse width modulation to achieve gray scale,
and allow disk drive applications to improve density and take
advantage of pulsed write formats. Control signals are TTL/
CMOS compatible.
The AD9660 can also be used in closed loop applications in
which the output power level follows an analog WRITE LEVEL
voltage input. By optimizing the external hold capacitor, and
the photo detector, the write loop can achieve bandwidths as
high as 25 MHz.
The AD9660 is offered in a 28-pin plastic SOIC for operation
over the commercial temperature range (0°C to +70°C).
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
(+VS = +5 V, Temperature = +25°C unless otherwise noted. Sourced currents defined
as positive.)
AD9660–SPECIFICATIONS
Test
AD9660KR
Parameter
Level Temp Min Typ
Max
Units
Conditions
ANALOG INPUTS
(WRITE LEVEL, BIAS LEVEL)
Input Voltage Range
Input Bias Current
IV
I
V
Full
+25°C –50
Full
VREF
VREF + 1.6
+50
V
µA
MHz
Analog Bandwidth
25
External Hold Cap = 20 pF
OUTPUTS
Maximum Output Current, IOUT
IOUT
I
I
I
I
I
I
I
+25°C 200
+25°C 180
+25°C 90
+25°C 60
+25°C 30
mA
mA
mA
mA
mA
V
VOUT = 2.5 V
VOUT = 3.0 V
VOUT = 3.0 V
VOUT = 3.0 V
VOUT = 3.0 V
Bias Current, IBIAS
Modulation Current, IMODULATION
Offset Current, IOFFSET
Output Compliance Range
Idle Current
+25°C
+25°C
0
3
3.0
13
mA
WRITE PULSE = LOW,
DISABLE = HIGH
SWITCHING PERFORMANCE
Maximum Pulse Rate
IV
+25°C 200 250
MHz
ns
3 dB Reduction in IOUT
Output Propagation Delay (tPD), Rising1 IV
Output Propagation Delay (tPD), Falling1 IV
Full
1.6
1.6
1.1
1.4
3.0
2.5
1.7
2.8
Full
ns
Output Current Rise Time2
Output Current Fall Time3
WRITE CAL Aperture Delay4
Disable Time5
IV
IV
V
Full
Full
1.5
2.0
13
5
ns
ns
ns
ns
+25°C
+25°C
V
HOLD NODES
(WRITE HOLD, BIAS HOLD)
Input Bias Current
I
IV
V
+25°C –200
Full
Full
200
VREF + 1.6
nA
V
pF
VHOLD = 2.5 V
Open Loop Application Only
Input Voltage Range
VREF
Minimum External Hold Cap
20
TTL INPUTS6
Logic “1” Voltage
Logic “1” Voltage
Logic “0” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
I
IV
I
IV
I
I
+25°C 2.0
V
V
V
V
µA
mA
DISABLE = LOW
While Other
TTL Inputs Are
Tested
Full
2.0
+25°C
Full
0.8
0.8
10
+25°C –10
+25°C –1.5
20
BANDGAP REFERENCE
Output Voltage VREF
Temperature Coefficient
Output Current
I
V
V
+25°C 1.55 1.75
–0.2
+25°C –0.5
1.90
1.0
V
mV/°C
mA
SENSE IN
Current Gain
Voltage
V
I
V
+25°C
+25°C 3.7
+25°C
1.85
4.0
<150
mA/mA
4.3
V
IMONITOR = 2 mA
Input Resistance
Ω
POWER SUPPLY (DISABLE = HIGH)
+VS Voltage
+VS Current
Power Dissipation
I
I
I
+25°C 4.75 5.00
5.25
150
V
mA
mW
DISABLE = HIGH
+25°C 75
+25°C
110
550
OFFSET CURRENT
OFFSET SET Voltage
I
+25°C 1.1
1.4
1.7
V
IMONITOR = 4.0 mA
NOTES
1Propagation delay measured from the 50% of the rising/falling transition of WRITE PULSE to 50% point of the rising/falling edge of the output modulation current.
2Rise time measured between the 10% and 90% points of the rising transition of the modulation current.
3Fall time measured between the 10% and 90% points of the falling transition of the modulation current.
4Aperture Delay is measured from the 50% point of the rising edge of WRITE PULSE to the time when the output modulation begins to recalibrate, WRITE CAL is
held during this test.
5Disable Time is measured from the 50% point of the rising edge of DISABLE to the 50% point of the falling transition of the output current. Fall time during disable
is similar to fall time during normal operation.
6WRITE PULSE, WRITE CAL, BIAS CAL, OFFSET PULSE are TTL compatible inputs.
Specifications subject to change without notice.
–2–
REV. 0
AD9660
ABSOLUTE MAXIMUM RATINGS1
EXPLANATION OF TEST LEVELS
Test Level
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
VREF Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
WRITE LEVEL, BIAS LEVEL . . . . . . . . . . . . . –0.5 V to +VS
TTL INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 mA
Operating Temperature
AD9660KR . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature2 . . . . . . . . . . . . . . . . +150°C
Lead Soldering Temp (10 sec) . . . . . . . . . . . . . . . . . . . +300°C
I. 100% Production Tested.
II. 100% production tested at +25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III. Sample Tested Only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. All devices are 100% production tested at +25°C, sample
1Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
tested at temperature extremes.
+V
S
2Typical thermal impedance is θJA = 45°C/W, θJC = 41°C/W.
50Ω
50Ω
WRITE
HOLD
ORDERING GUIDE
BIAS
HOLD
Model
Temperature Range Package Option
SENSE
IN
AD9660KR
0°C to +70°C
R-28
T/H
AD9660KR-REEL 0°C to +70°C
R-28 (1000/reel)
PIN ASSIGNMENTS
1mA
OFFSET
SET
WRITE CAL
WRITE PULSE
WRITE LEVEL
1
28 OFFSET PULSE
+V
S
2
27
OFFSET SET
26
GROUND
3
4
V
25 +V
S
V
REF
BANDGAP
WRITE HOLD
GROUND
5
24 OUTPUT
AD9660KR
TOP VIEW
(Not to Scale)
6
23 +V
S
100Ω
+V
S
7
22 OUTPUT
V
+V
REF
S
8
SENSE IN
GAIN
21 +V
S
450Ω
9
20
19
18
OUTPUT
POWER MONITOR
+V
S
10
1250Ω
OUTPUT
+V 11
S
TTL
INPUT
GROUND 12
17 GROUND
DISABLE
16
+V
S
BIAS HOLD
13
BIAS LEVEL 14
15 BIAS CAL
OUTPUT
Equivalent Circuits
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9660 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD9660
PIN DESCRIPTIONS
Pin
Function
OUTPUT
Analog laser diode current output. Connect to anode of laser diode, cathode connected to GROUND externally.
Analog voltage input, VREF to VREF + 1.6 V. Bias current is set proportional to the BIAS LEVEL during calibra-
BIAS LEVEL
tion as follows:
VBIAS LEVEL −VREF
IMONITOR
=
1. 85 × R
+ 50 Ω
(
)
GAIN
BIAS CAL
TTL/CMOS compatible, Bias loop T/H control signal. Logic HIGH enables calibration mode, and the bias loop
T/H immediately goes into track mode. Logic LOW disables the bias loop T/H and immediately places it in hold
mode. WRITE PULSE should be held logic LOW while calibrating. Floats logic HIGH.
BIAS HOLD
External hold capacitor for the bias loop T/H. Approximate droop in the bias current while BIAS CAL is logic
18 ×10–9 tBIAS HOLD
1
BW =
. Bandwidth of the loop is:
±∆IBIAS
=
LOW is:
2π (550 Ω) CBIAS HOLD
CBIAS HOLD
WRITE PULSE TTL/CMOS compatible, current control signal. Logic HIGH supplies IMODULATION to the laser diode. Logic
LOW turns IMODULATION off. Floats logic HIGH.
WRITE CAL
TTL/CMOS compatible, write loop T/H control signal. Logic HIGH enables calibration mode; before enabling
calibration the bias loop should be calibrated and OFFSET PULSE driven to an appropriate state. In calibration
mode, 13 ns after the WRITE PULSE goes logic HIGH, the write loop T/H goes into track mode (there is no de-
lay if WRITE PULSE is HIGH before WRITE CAL transitions to a HIGH level). The write loop T/H immedi-
ately goes into hold mode when the WRITE PULSE goes Logic LOW. WRITE CAL LOW disables the write
loop T/H and places it in hold mode. Floats logic HIGH.
WRITE LEVEL Analog voltage input, VREF to VREF +1.6 V. Write current is set proportional to the input voltage during calibra-
VWRITE LEVEL − VREF
IMONITOR
=
tion as follows:
1. 85 ×(RGAIN + 50 Ω)
WRITE HOLD External hold capacitor for the write loop T/H. Approximate droop in IMODULATION current while WRITE CAL is
−9
18 ×10
t
WRITE HOLD
±∆IMODULATED
=
logic LOW is:
. Bandwidth of the loop is:
CWRITE HOLD
1
BW =
2π (550 Ω) CBIAS HOLD
SENSE IN
GAIN
Analog current input, IMONITOR, from PIN photo detector diode. SENSE IN should be connected to the cathode
of the PIN diode, with the PIN anode connected to GROUND or a negative voltage. Voltage at SENSE IN var-
ies slightly with temperature and current, but is typically 4.0 V.
External connection for the feedback network of the transimpedance amplifier. External feedback network, RGAIN
and CGAIN, should be connected between GAIN and POWER MONITOR. See text for choosing values.
POWER
MONITOR
Output voltage monitor of the internal feedback loop. Voltage is proportional to feedback current from photo
diode.
OFFSET
Set resistor connection for the offset current source. Resistor between OFFSET CURRENT SET and +VS
CURRENT SET determines offset current level. The input voltage at this node varies slightly with temperature and current, but is
typically 1.4 V. See curves. Can also be driven with a current out DAC.
OFFSET
PULSE
TTL/CMOS compatible, OFFSET current control signal. Logic HIGH adds IOFFSET to IOUT. Logic LOW
turns off IOFFSET. Floats logic HIGH.
DISABLE
TTL/CMOS compatible, current output disable circuit. Logic LOW for normal operation; logic HIGH disables
the current outputs to the laser diode, and drives the voltage on the hold capacitors close to VREF (minimizes the
output current when the device is re-enabled). DISABLE floats logic HIGH.
VREF
Analog Voltage Output, internal bandgap voltage reference, ~1.75 V, provided to user for power level offset.
Positive Power Supply. Nominally +5 V, pin connections should be tied together externally.
Ground Reference. All grounds should be tied together externally.
+VS
GROUND
–4–
REV. 0
Typical Performance Characteristics–AD9660
6.25mV
35
30
25
20
15
10
5
20mV
2ns
–193.8mV
ML64116R
TEK 11802
O'SCOPE
OUTPUT
50Ω
0
AD9660
0
5
10
R
15
– kΩ
20
25
50Ω
OFFSET
–120V
ANTEL
ARS1
PHOTO DETECTOR
Figure 2. IOFFSET vs. ROFFSET
Figure 1. Driving ML64116R Laser @ 30 mW
THEORY OF OPERATION
current is proportional to the laser diode light power, the loops
effectively control laser power to a level proportional to the ana-
log inputs. The control loops should be periodically calibrated
independently (see Choosing CBIAS HOLD and CWRITE HOLD).
The AD9660 combines a very fast output current switch with
onboard analog light power control loops to provide the user
with a complete laser diode driver solution. The block diagram
illustrates the key internal functions. The control loops of the
AD9660, the bias loop and the write loop, adjust the output
current level, IOUT, so that the photo diode feedback current,
IMONITOR, out of SENSE IN is proportional to the analog input
voltage at BIAS LEVEL or WRITE LEVEL. Since the monitor
The offset current generator produces an open loop output cur-
rent, IOFFSET. Its level is controlled by an external set resistor or
a current out DAC (see Figure 2). While IOFFSET is not cali-
brated as the currents from the bias and write loops are, it can
be very versatile (see Offset Current below).
WRITE HOLD
AD9660
VOLT
REF
TTL
DISABLE
CIRCUIT
V
OUT
REF
DISABLE
TTL
WRITE PULSE
*
TTL
DELAY
WRITE CAL
ANALOG
WRITE LOOP
WRITE LEVEL
I
OUT
I
V:1
MODULATION
5pF
V
OUTPUT
1:10
LASER
DIODE
REF
GAIN
50
2* I
MONITOR
SENSE IN
C
R
4.0V
GAIN
GAIN
1.85:1
ANALOG
PHOTO
DETECTOR
TZA
I
MONITOR
V
POWER
MONITOR
REF
I
BIAS
V
REF
V:1
1:10
1:10
ANALOG
TTL
BIAS LEVEL
BIAS CAL
5pF
BIAS LOOP
OFFSET CURRENT
SET
I
OFFSET
BIAS HOLD
1.4V
+V
TTL
S
OFFSET PULSE
*
10ns DELAY ON RISING
EDGE; 0ns ON FALLING
Figure 3. Functional Block Diagram
–5–
REV. 0
AD9660
POWER-UP
OR LASER
NOT IN USE
DISABLE
BIAS CAL
RECALIBRATE THE BIAS LOOP
BIAS
CAL
TIME
WRITE
LOOP
CAL
WRITE LOOP
HOLD TIME
WRITE CAL
TIME
RECALIBRATE WRITE LOOP
WRITE PULSE
LASER POWER
MODULATED
BETWEEN
BIAS AND WRITE LEVELS
CALIBRATED WRITE
CALIBRATED BIAS
LASER
OUTPUT POWER
Figure 4. Normal Operating Mode
When the write loop is open (WRITE CAL logic LOW),
IMODULATION is proportional to the held voltage at WRITE HOLD.
The external hold capacitor (WRITE HOLD) determines the
droop error between calibrations. IMODULATION may be switched
on and off by WRITE PULSE when the write loop is open.
The disable circuit turns off IOUT and returns the hold capacitor
voltages to their minimum levels (minimum output current)
when DISABLE = logic HIGH. It is used during initial power-
up of the AD9660 or during time periods when the laser is inac-
tive. When the AD9660 is re-enabled the control loops must be
recalibrated.
4
Normal operation of the AD9660 involves (in order, see figure):
1. The AD9660 is enabled (DISABLE = logic LOW).
0°C CASE
3
2
1
0
2. The input voltages (BIAS LEVEL and WRITE LEVEL) are
driven to the appropriate levels to set the calibrated laser di-
ode output power levels.
25
CASE
°C
CONSTANT WRITE POWER
BIAS CALIBRATION POWER
3. The bias loop is closed for calibration (BIAS CAL = logic
HIGH), and then opened (BIAS CAL = logic LOW).
50°C CASE
4. The write loop is closed for calibration (WRITE PULSE and
WRITE CAL = logic HIGH) and then opened.
5. While both loops are open, the laser is pulsed between the
two calibrated levels by WRITE PULSE.
0
20
40
FORWARD CURRENT – mA
MOD
60
80
100
120
6. The bias and write loops are periodically recalibrated as
needed.
BIAS
7. The AD9660 is disabled when the laser will not be pulsed for
an indefinite period of time.
Figure 5. Typical Laser Diode Current-to-Optical
Power Curve
Control Loop Transfer Functions
The relationship between IMONITOR and VBIAS LEVEL is
The sections below discuss choosing the external components in
the feedback loops for a particular application.
VBIAS LEVEL −VREF
Choosing RGAIN
IMONITOR
=
The gain resistor, RGAIN, allows the user to match the feedback
loop’s transfer function to the laser diode/photo diode
combination.
1. 85 ×(RGAIN + 50 Ω)
once the bias loop is calibrated. When the bias loop is open
(BIAS CAL = logic LOW), its output current, IBIAS, is propor-
tional to the held voltage at BIAS HOLD; the external hold ca-
pacitor on this pin determines the droop error in the output bias
current between calibrations.
The user should define the maximum laser diode output power
for the intended application, PLD MAX, and the corresponding
photo diode monitor current, IMONITOR MAX. A typical laser di-
ode transfer function is illustrated in Figure 5. RGAIN should be
The relationship between IMONITOR and VWRITE LEVEL is
1. 6 V
RGAIN
=
− 50 Ω
VWRITE LEVEL −VREF
chosen as:
.
1. 85 × IMONITOR MAX
IMONITOR
=
1. 85 ×(RGAIN + 50 Ω)
once the write loop is calibrated. The current supplied by the write
loop output is referred to as the modulation current, IMODULATION
The laser diode’s output power will then vary from 0 to PLD MAX
for an input range of VREF to VREF +1.6 V @ the BIAS LEVEL
and WRITE LEVEL inputs.
.
–6–
REV. 0
AD9660
Minimum specifications for IMONITOR MAX should be used when
choosing RGAIN. Users are cautioned that laser diode/photo di-
ode combinations that produce monitor currents that are less
than IMONITOR MAX in the equation above will produce higher la-
ser output power than predicted, which may damage the laser
diode. Such a condition is possible if RGAIN is calculated using
typical instead of minimum monitor current specifications. In
that case the input range to the AD9660 BIAS LEVEL and
WRITE LEVEL inputs should be limited to avoid damaging
laser diodes.
Choosing CBIAS HOLD and CWRITE HOLD
Choosing values for the hold capacitors, CWRITE and CHOLD, is a
tradeoff between output current droop when the control loops
are open, and the time it takes to calibrate and recalibrate the
laser power when the loops are closed.
The amount of output current droop is determined by the value
of the hold capacitor and the leakage current at that node.
When either of the two control loops are open (WRITE CAL or
BIAS CAL logic LOW), the pin connections for the hold
capacitors (WRITE HOLD and BIAS HOLD) are high imped-
ance inputs. Leakage currents will range from ±200 nA; this
low current minimizes the droop in the output power level. As-
suming the worst case current of ±200 nA, the output current
will change as follows:
Although not recommended, another approach would be to
use a potentiometer for RGAIN. This allows users to optimize
the value of RGAIN for each laser diode/photo diode combina-
tion’s monitor current. The drawback to this approach is that
potentiometer’s stray inductance and capacitance may cause the
transimpedance amplifier to overshoot and degrade its settling,
and the value of CGAIN may not be optimized for the entire
potentiometer’s range.
18 ×10−9 tBIAS HOLD
±∆IBIAS
=
CBIAS HOLD
C
GAIN optimizes the response of the transimpedance amplifier
18 ×10−9 tWRITE HOLD
and should be chosen as from the table below. Choosing CGAIN
larger than the recommended value will slow the response of the
amplifier. Lower values improve TZA bandwidth but may cause
the amplifier to oscillate.
±∆IMODULATED
=
CWRITE HOLD
Table I.
To choose a value, the user will need to determine the amount
of time the loop will be in hold mode, tWRITE HOLD or tBIAS HOLD
,
Recommended
CGAIN
the maximum change in laser output power the application can
tolerate, and the laser efficiency (defined as the change in laser
output power to the change in laser diode current). As an ex-
ample, if an application requires 5 mW of laser power ±5%, and
the laser diode efficiency is 0.25 mW/mA, then
RGAIN
≥2.5 kΩ 2 pF
1.5 kΩ
1 kΩ
500 Ω
3 pF
4 pF
8 pF
mW
mA
∆IMAX = 5 mW ×(5%) / 0.25
= 1. 0 mA
The circuit in Figure 6 allows an adjustable gain with low vari-
ance in bandwidth, but requires several external components.
If the same application had a hold time requirement of 250 µs,
then the minimum value of the hold capacitor would be:
R
INTERNAL
18 ×10−9 × 250 µs
50Ω
CHOLD
=
= 4.5 nF
1. 0 mA
C
EQ
R
EQ
When determining the calibration time, the T/H and the exter-
nal hold capacitor can be modeled using the simple RC circuit
illustrated in Figure 7.
V
REF
R
EQ
+ 50Ω = (R + 50Ω)
F
EQUIVALENT
CIRCUIT
R2 R1
(1+
+
)
R1
R
F
GAIN
AD9660
R
SENSE
IN
INTERNAL
50Ω
WRITE HOLD
OR BIAS HOLD
WRITE LEVEL
OR BIAS LEVEL
R
2I PIN
C
C1
R
F
F
I
T/H
MONITOR
1:2
EXTERNAL HOLD
CAPACITOR
C
HOLD
POWER
MONITOR
R1
R2
POWER MONITOR
TZA
V
REF
V
REF
Figure 7. Circuit Model for Determining Calibration Times
R3
1.7kΩ
AD9660
Figure 6. Adjustable Gain Configuration
REV. 0
–7–
AD9660
Using this model, the voltage at the hold capacitor is
Initial calibration is required after power-up or any other time
the laser has been disabled. Disabling the AD9660 drives the
hold capacitors back down to VREF. In this case, or in any case
where the output current is more than 10% out of calibration, R
will range from 300 Ω to 550 Ω for the model above; the higher
value should be used for calculating the worst case calibration
time. Following the example above, if CHOLD were chosen as
4.5 nF, then τ = RC = 550 Ω × 4.5 nF would be 2.5 µs. For an
initial calibration error <1%, the initial calibration time should
be >5τ = 12.4 µs.
−t
τ
VC
= Vt = 0 +(Vt = ∞ − Vt = 0) 1− e
HOLD
where t0 is when the calibration begins (WRITE CAL or BIAS
CAL goes logic HIGH), Vt = 0 is the voltage on the hold cap at
t = 0, Vt = ∞ is the steady state voltage at the hold cap with the
loop closed, and τ = RCHOLD is the time constant. With this
model the error in VC
for a finite calibration time, as com-
pared to Vt = ∞, can beHeOsLtDimated from the following table and
chart:
Initial calibration time will actually be better than this calcula-
tion indicates, as a significant portion of the calibration time will
be within 10% of the final value, and the output resistance in
the AD9660’s T/H decreases as the hold voltage approaches its
final value.
Table II.
tCALIBRATION
% Final Value
Error %
Recalibration is functionally identical to initial calibration, but
the loop need only correct for droop. Because droop is assumed
to be a small percentage of the initial calibration (<10%), the
resistance for the model above will be in the range of 75 Ω to
140 Ω. Again, the higher value should be used to estimate the
worst case time needed for recalibration.
7τ
6τ
5τ
4τ
3τ
2τ
τ
99.9
99.7
99.2
98.1
95.0
86.5
63.2
0.09
0.25
0.79
1.83
4.97
13.5
36.8
Continuing with the example above, since the error during hold
time was chosen as 5%, we meet the criteria for recalibration
and τ = RC = 140 Ω × 4.5 nF = 0.63 µs. To get a final error of
1% after recalibration, the 5% droop must be corrected to
within a 20% error (20% × 5% = 1%). A 2τ recalibration time
of 1.26 µs is sufficient.
100
90
80
70
60
50
40
30
20
10
0
Continuous Recalibration
In applications where the hold capacitor is small (<500 pF) and
the WRITE PULSE signals always have a pulse width >25 ns,
the user may continuously calibrate the write loop. In such an
application, the WRITE CAL signal should be held logic
HIGH, and the WRITE PULSE signal will control write loop
calibration via the internal AND gate.
The bias loop may be continuously recalibrated whenever
WRITE PULSE is logic LOW.
0
1
2
3
4
5
CALIBRATION TIME – Time Constants =
Figure 8. Calibration Time Curve
–8–
REV. 0
AD9660
Example Calculations
• From the monitor current specification and the max power
The example below (in addition to the one included in the sec-
tions above) should guide users in choosing RGAIN, CGAIN, the
hold capacitor values, and worst case calibration times.
specified:
5 µA
mW
IMONITOR MAX = 25 mW
= 125 µA
System Requirements:
and
• Bias laser power: 4 mW Bias ± 5%
• Write laser power: 25 mW ± 0.5%
• Bias Hold Time: 1 ms
1. 6 V
RGAIN
=
− 50 Ω = 6.9 kΩ
1. 85 × IMONITOR MAX
• CGAIN would be chosen as 2 pF (see Table I).
• Write Hold Time: 1 µs
Driving the Analog Inputs
Laser diode/photo diode characteristics:
• Laser efficiency 0.5 mA/mA
• Monitor current: 5 µA/mA
The BIAS LEVEL and WRITE LEVEL inputs of the AD9660
drive the track and hold amplifiers and allow the user to adjust
the amount of output current as described above. The input
voltage range on both inputs is VREF to VREF + 1.6 V, requiring
the user to create an offset of VREF for a ground based signal.
The circuit in Figure 9 will perform the level shift and scale the
output of a DAC whose output is from ground to a positive
voltage. This solution is attractive because both the DAC and
the op amp can run off a single +5 V supply, and the op amp
doesn’t have to swing rail to rail.
• From the laser power requirements and efficiency we can
estimate:
mW
mA
∆IBIAS MAX = 4 mW ×(5%) / 0.5
= 400.0 µA
and
mW
∆IWRITE MAX = 25 mW × 0.5% / 0.5
= 250 µA
(
)
mA
R2
= V
BIAS LEVEL
V
+ V
DAC1
REF
R2
+5V
R1
• Choosing hold caps based on these:
18 ×10−9 ×1ms
AD9660
R1
V
DAC1
CBIAS HOLD
=
= 0.045 µF
= 72 pF
BIAS LEVEL
OP291
R1
R3
400 µA
DAC1
DAC2
R2
R4
and
V
V
DAC2
REF
18 ×10−9 ×1 µs
250 µA
CWRITE HOLD
=
OP291
R4
WRITE LEVEL
R3
• The bias loop initial calibration time for a <1% error:
5τ = 5 × RC = 5 × 550 Ω × 0.045 µF = 123.75 µs
R4
R3
V
+ V
DAC2
= V
WRITE LEVEL
• Bias loop recalibration for a 1% error after 5% droop (need to
correct within 20%):
REF
2τ = 2 × RC = 2 × 140 Ω × 0.045 µF = 12.6 µs
Figure 9. Driving the Analog Inputs
• The write loop initial calibration time for <0.1% error:
7τ = 7 × RC = 7 × 550 Ω × 72 pF = 277.2 ns
• Write loop re-calibration for a 0.1% error after 0.5% droop
(need to correct within 20%):
2τ = RC = 2 × 140 Ω × 72 pF = 20.2 ns
REV. 0
–9–
AD9660
Offset Current Generator
AD9660 Layout Considerations
The offset current source allows the user to inject a fixed,
uncalibrated current into the laser diode. The offset current
source is set by an external resistor connected between OFF-
SET CURRENT SET and +VS, and is controlled by OFFSET
PULSE. See Figure 2 for a transfer function of the offset cur-
rent source.
As in all high speed applications, proper layout is critical; it is
particularly important when both analog and digital signals are
involved. Analog signal paths should be kept as short as pos-
sible, and isolated from digital signals to avoid coupling in noise.
In particular, digital lines should be isolated from OUTPUT,
PIN SENSE, WRITE LEVEL, and BIAS LEVEL traces. Digi-
tal signal paths should also be kept short, and run lengths
matched to avoid propagation delay mismatch.
The offset current may be used to increase the output current
provided by the bias and/or write loops after calibration. Alter-
natively, the offset current may be added during the calibration
of the bias loop and switched off after calibration to drop the
bias current below the knee of the laser diode power curve.
This is illustrated in Figure 10.
Layout of the ground and power supply circuits is also critical.
A single, low impedance ground plane will reduce noise on the
circuit ground. Power supplies should be capacitively coupled
to the ground plane to reduce noise in the circuit. 0.1 µF sur-
face mount capacitors, placed as close as possible to the
AD9660 +VS connections meet this requirement. Multilayer
circuit boards allow designers to lay out signal traces without
interrupting the ground plane, and provide low impedance
power planes to further reduce noise.
4
0°C CASE
3
2
1
0
Minimizing the Impedance of the Output Current Path
Because of the very high current slew that the AD9660 is
capable of producing (70+ mA in 1.5 ns), the inductance of the
output current path to and from the laser diode is critical. A
good layout of the output current path will yield high quality
light pulses with rise times of about 1.5 ns and less than 5%
overshoot. A poor layout can result in significant overshoot and
ringing. The most important guideline for the layout is to mini-
mize the impedance (mostly inductance) of the output current
path to the laser. It is important to recognize that the laser cur-
rent path is a closed loop. The figure illustrates the path that
current travels: (1) from the output pins of the AD9660 to the
anode of the laser, (2) through the laser to the cathode
(ground), (3) through the return path, (4) through the 0.1 µF
bypass capacitors back to the +VS pins of the AD9660 where (5)
the current travels through the output driver circuitry of the
AD9660, and back to the output pins. The inductance of this
loop can be minimized by placing the laser as close to the
AD9660 as possible to keep the loop short, and by placing the
send and return paths on adjacent layers of the PC board to take
advantage of mutual coupling of the path inductances. This
mutual coupling effect is the most important factor in reducing
inductance in the current path.
25
CASE
°C
CONSTANT WRITE POWER
BIAS CALIBRATION POWER
50°C CASE
OPERATING
BIAS LEVEL
0
20
40
60
80
100
120
FORWARD CURRENT – mA
BIAS
OFFSET
2
BIAS1
MOD
1
WITH OFFSET CURRENT TURNED OFF,
BIAS CURRENT IS BELOW THE KNEE OF THE LASER DIODE
2
OFFSET CURRENT TURNED ON DURING BIAS-CAL
Figure 10. Laser Diode Current-to-Optical Power Curve
Illustrating Bias Below Diode Knee
–10–
REV. 0
AD9660
The best possible TZA settling will be achieved by using a
single carbon surface mount resistor (usually 5% tolerance) for
RGAIN and small surface mount capacitor for CGAIN. Because the
GAIN pin (Pin 9) is essentially connected to the inverting input
of the TZA, it is very sensitive to stray capacitance. RGAIN
should be placed between Pin 9 and Pin 10, as close as possible
to Pin 9. Small traces should be used, and the ground and +VS
planes adjacent to the trace should be removed to further mini-
mize stray capacitance.
The trace from the output pins of the AD9660 to the anode of
the laser (send trace) should be several millimeters wide and
should be as direct as possible. The return current will choose
the path of least resistance. If the return path is the ground
plane, it should have an unbroken path, under the output trace,
from the laser cathode back to the AD9660. If the return path is
not the ground plane (such as on a two layer board, or on the
+VS plane), it should still be on the board plane adjacent to the
plane of the output trace. If the current cannot return along a
path that follows the output trace, the inductance will be drasti-
cally increased and performance will be degraded.
The trace from SENSE IN to the cathode of the PIN photo-
detector should be thin and routed away from the laser anode
trace.
Optimizing the Feedback Layout
In applications where the dynamic performance of the analog
feedback loop is important, it is necessary to optimize the layout
of the gain resistor, RGAIN, as well as the monitor current path to
SENSE IN. Such applications include MOD systems which
recalibrate the write loop on pulses as short as 25 ns, and closed
loop applications.
PIN ASSIGNMENTS
MUTUAL COUPLING
REDUCES INDUCTANCE
+V PIN CONNECTIONS
S
25
24
23
22
LASER DIODE CURRENT
PATH SEGMENTS
(SEE TEXT)
1
21
20
19
5
3
2
AD9660
4
OUTPUT PIN CONNECTIONS
BYPASS CAPS
GROUND PIN
CONNECTIONS
GROUND PLANE
Figure 11. Laser Diode Current Loop
REV. 0
–11–
AD9660
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Pin Plastic SOIC
(R-28)
0.712 (18.08)
0.700 (17.78)
28
15
0.419 (10.64)
0.393 (9.98)
0.300 (7.60)
0.292 (7.40)
1
14
PIN 1
0.104 (2.64)
0.093 (2.36)
0.012 (0.30)
0.004 (0.10)
0.0500
(1.27)
BSC
0.019 (0.48)
0.04 (1.02)
0.013 (0.33)
0.009 (0.23)
SEATING
PLANE
0.014 (0.36)
0.024 (0.61)
–12–
REV. 0
相关型号：
AD9662ARQZ-REEL7
IC SPECIALTY INTERFACE CIRCUIT, PDSO16, LEAD FREE,MO-137AB,QSOP-16, Interface IC:Other
ADI
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