AD9661AKR-REEL [ADI]
Laser Diode Driver with Light Power Control; 激光二极管驱动器与光功率控制
| 型号： | AD9661AKR-REEL |
| 厂家： | 
ADI |
| 描述： | Laser Diode Driver with Light Power Control |
| 文件： | 总12页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Laser Diode Driver
with Light Power Control
a
AD9661A
and fall times are 2 ns to complement printer applications that
use image enhancing techniques such as pulse width modula-
tion to achieve gray scale and resolution enhancement. Control
signals are T T L/CMOS compatible.
FEATURES
< 2 ns Rise/ Fall Tim es
Output Current: 120 m A
Single +5 V Pow er Supply
Sw itching Rate: 200 MHz typ
Onboard Light Pow er Control Loop
T he driver output provides up to 120 mA of current into an
infrared N type laser, and the onboard disable circuit turns off
the output driver and returns the light power control loop to a
safe state.
APPLICATIONS
Laser Printers and Copiers
T he AD9661A can also be used in closed-loop applications in
which the output power level follows an analog POWER LEVEL
voltage input. By optimizing the external hold capacitor and
the photo detector, the loop can achieve bandwidths as high as
25 MHz.
GENERAL D ESCRIP TIO N
T he AD9661A is a highly integrated driver for laser diode appli-
cations such as printers and copiers. T he AD9661A gets feed-
back from an external photo detector and includes an analog
feedback loop to allow users to set the power level of the laser,
and switch the laser on and off at up to 100 MHz. Output rise
T he AD9661A is offered in a 28-pin plastic SOIC for
operation over the commercial temperature range (0°C to
+70°C).
FUNCTIO NAL BLO CK D IAGRAM
TTL
TTL
DISABLE
CIRCUIT
DISABLE
*13ns DELAY ON RISING
EDGE; 0ns ON FALLING
PULSE
HOLD
PULSE2
TTL
TTL
*
DELAY
CAL
VOLT
V
REF
REF
+5V
POWER
LEVEL
ANALOG
LASER
DIODE
PHOTO
DETECTOR
V
+ V
REF
LEVEL SHIFT IN
V1
3–120mA
LEVEL
5pF
1:10
SHIFT OUT
I
OUTPUT
OUT
LEVEL
SHIFT
CIRCUIT
LEVEL
SHIFT IN
REF
8
DAC
0–1.6V
AD9661A
GAIN
50Ω
C
R
GAIN
GAIN
SENSE IN
1.0V
ANALOG
1:1
I
I
MONITOR
MONITOR
POWER
MONITOR
V
REF
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
(+V = +5 V, Temperature = +25؇C unless otherwise noted)
AD9661A–SPECIFICATIONS
S
Test
Level Tem p
AD 9661AKR
P aram eter
Min
Typ
Max
Units
Conditions
ANALOG INPUT
Input Voltage Range, POWER LEVEL
Input Bias Current, POWER LEVEL
Analog Bandwidth, Control Loop1
Input Voltage Range, LEVEL SHIFT IN
Input Bias Current, LEVEL SHIFT IN
Analog Bandwidth, Level Shift2
Level Shift Offset
IV
I
V
IV
I
V
I
I
Full
VREF
–50
VREF + 1.6
+50
V
µA
MHz
V
µA
MHz
mV
V/V
+25°C
+25°C
Full
+25°C
Full
25
CHOLD = 33 pF, RF = 1 kΩ, CF = 2 pF
0.1
–10
1.6
0
130
1.0
+25°C
+25°C
–32
0.95
+32
1.05
Level Shift Gain
OUT PUT S
Output Current, IOUT
Output Compliance Range
Idle Current
I
IV
I
+25°C
+25°C
+25°C
+25°C
120
2.50
mA
V
mA
µA
VOUT = 2.5 V
5.25
5.0
1.0
2
PULSE = LOW, DISABLE = LOW
PULSE = LOW, DISABLE = HIGH
Disable Current
IV
SWIT CHING PERFORMANCE
Maximum Pulse Rate
V
+25°C
Full
Full
Full
Full
200
3.9
3.7
1.5
1.5
13
MHz
ns
ns
ns
ns
Output Current –3 dB
Output Propagation Delay (tPD), Rising3
Output Propagation Delay (tPD), Falling3
Output Current Rise T ime4
Output Current Fall T ime5
CAL Aperture Delay6
IV
IV
IV
IV
IV
IV
2.9
3.2
5.0
4.3
2.0
2.0
Full
+25°C
ns
ns
Disable T ime7
3
5
HOLD NODE
Input Bias Current
Input Voltage Range
Minimum External Hold Cap
I
IV
V
+25°C
Full
Full
–200
VREF
200
VREF + 1.6
nA
V
pF
VHOLD = 2.5 V
Open-Loop Application Only
25
T T L/CMOS INPUT S8
Logic “1” Voltage
Logic “1” Voltage
Logic “0” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
I
IV
I
IV
I
I
+25°C
Full
+25°C
Full
+25°C
+25°C
2.0
2.0
V
V
V
V
µA
mA
0.8
0.8
10
–10
–1.5
VHIGH = 5.0 V
VLOW = 0.8 V
BANDGAP REFERENCE
Output Voltage (VREF
T emperature Coefficient
Output Current
)
I
V
V
+25°C
+25°C
+25°C
1.6
1.8
–0.1
1.9
1.0
V
mV/°C
mA
–0.5
SENSE IN
Current Gain
Voltage
Input Resistance
I
I
V
+25°C
+25°C
+25°C
0.95
0.7
1
1.02
1.3
mA/mA
V
Ω
1.0
<150
POWER SUPPLY
+VS Voltage
+VS Current
I
I
+25°C
+25°C
4.75
60
5.00
75
5.25
95
V
mA
DISABLE = HIGH, VHOLD = VREF
VS = 5.0 V
,
NOT ES
1Based on rise time of closed-loop pulse response. See Performance Curves.
2Based on rise time of pulse response.
3Propagation delay measured from the 50% of the rising/falling transition of WRIT E PULSE to the 50% point of the rising/falling edge of the output modulation
current.
4Rise time measured between the 10% and 90% points of the rising transition of the modulation current.
5Fall time measured between the 10% and 90% points of the falling transition of the modulation current.
6Aperture Delay is measured from the 50% point of the rising edge of WRIT E PULSE to the time when the output modulation begins to recalibrate, WRIT E CAL is
held during this test.
7Disable T ime is measured from the 50% point of the rising edge of DISABLE to the 50% point of the falling transition of the output current. Fall time during disable
is similar to fall time during normal operation.
8PULSE, PULSE2, DISABLE, and CAL are T T L/CMOS compatible inputs.
Specifications subject to change without notice.
–2–
REV. 0
AD9661A
ABSO LUTE MAXIMUM RATINGS*
EXP LANATIO N O F TEST LEVELS
Test Level
+VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
POWER LEVEL, LEVEL SHIFT IN . . . . . . . . . . . 0 V to +VS
T T L/CMOS INPUT S . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Operating T emperature
AD9661AKR . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction T emperature . . . . . . . . . . . . . . . . . +150°C
Lead Soldering T emp (10 sec) . . . . . . . . . . . . . . . . . . . +300°C
I
– 100% production tested.
II – 100% production tested at +25°C, and sample tested at
specified temperatures.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V
– Parameter is a typical value only.
VI – All devices are 100% production tested at +25°C; 100%
production tested at temperature extremes for military
devices; sample tested at temperature extremes for
commercial/industrial devices.
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
O RD ERING GUID E
Model
Tem perature Range P ackage O ption
AD9661AKR
0°C to +70°C
R-28
AD9661AKR-REEL 0°C to +70°C
R-28 (1000/Reel)
+V
S
+V
S
+V
S
1mA
1mA
V
BANDGAP
TTL
INPUT
100Ω
SENSE
IN
V
REF
450Ω
1250Ω
50Ω
50Ω
OUTPUT
HOLD
T/H
Equivalent Circuits
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9661A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD9661A
P IN D ESCRIP TIO NS
P in
Function
OUT PUT
Analog laser diode current output. Connect to cathode of laser diode, anode connected to +VS externally.
POWER LEVEL
Analog voltage input, VREF to VREF + 1.6 V. Output current is set proportional to the POWER LEVEL
VPOWER LEVEL – VREF
IMONITOR
=
during calibration as follows:
RGAIN + 50 Ω
CAL
T T L/CMOS compatible, feedback loop T /H control signal. Logic LOW enables calibration mode, and
the feedback loop T /H goes into track mode 13 ns after (the aperture delay) PULSE goes logic HIGH
(there is no aperture delay if PULSE goes high before CAL transitions to a LOW level). Logic HIGH dis-
ables the T /H and immediately places it in hold mode. PULSE should be held HIGH while calibrating.
Floats logic HIGH.
HOLD
External hold capacitor for the bias loop T /H. Approximate droop in the output current while CAL is
18 ×10–9 tHOLD
±∆IOUT
=
logic HIGH is:
CHOLD
1
BW ≈
Bandwidth of the loop is:
2 π (550 Ω) CHOLD
PULSE
T T L/CMOS compatible, current control signal. Logic HIGH supplies IOUT to the laser diode. Logic
LOW turns IOUT off. Floats logic HIGH.
PULSE 2
SENSE IN
T T L/CMOS compatible, current control signal. Logic LOW supplies IOUT to the laser diode. Logic
HIGH turns IOUT off. Floats logic HIGH.
Analog current input, IMONIT OR, from PIN photo detector diode. SENSE IN should be connected to the
anode of the PIN diode, with the PIN cathode connected to +VS or another positive voltage. Voltage at
SENSE IN varies slightly with temperature and current, but is typically 1.0 V.
GAIN
External connection for the feedback network of the transimpedance amplifier. External feedback network,
RGAIN and CGAIN, should be connected between GAIN and POWER MONIT OR. See text for choosing
values.
POWER MONIT OR
DISABLE
Output voltage monitor of the internal feedback loop. Voltage is proportional to feedback current from
photo diode, IMONIT OR
.
T T L/CMOS compatible, current output disable circuit. Logic LOW for normal operation; logic HIGH
disables the current outputs to the laser diode, and drives the voltage on the hold capacitors close to VREF
(minimizes the output current when the device is re-enabled). DISABLE floats logic HIGH.
VREF
Analog Voltage output, internal bandgap voltage reference, ~1.8 V, provided to user for power level offset.
Power Supply, nominally +5 V. All +VS connections should be tied together externally.
Ground reference. All GROUND connections should be tied together externally.
+VS
GROUND
LEVEL SHIFT IN
LEVEL SHIFT OUT
Analog input to the on board level shift circuit. Input Range 0.1 V – 1.6 V.
Voltage output from on board level shift circuit. Connect to POWER LEVEL externally to use the on
board level shift circuit. Output voltage is VLEVEL SHIFT OUT = VLEVEL SHIFT IN +VREF
.
P IN ASSIGNMENTS
+V
PULSE2
DNC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
S
GROUND
OUTPUT
GROUND
OUTPUT
GROUND
OUTPUT
GROUND
OUTPUT
GROUND
V
3
REF
LEVEL SHIFT IN
4
GAIN
5
POWER MONITOR
6
AD9661AKR
(Not to Scale)
SENSE INPUT
GROUND
7
8
+V
S
9
10
11
12
13
14
GROUND
HOLD
+V
S
GROUND
CAL
POWER LEVEL
LEVEL SHIFT OUT
DISABLE
15 PULSE1
–4–
REV. 0
AD9661A
TH EO RY O F O P ERATIO N
Contr ol Loop Tr ansfer Function
T he AD9661A combines a very fast output current switch with
an onboard analog light power control loop to provide the user
with a complete laser diode driver solution. T he block diagram
illustrates the key internal functions. T he control loop of the
AD9661A adjusts the output current level, IOUT , so that the
photo diode feedback current, IMONIT OR, into SENSE IN is pro-
portional to the analog input voltage at POWER LEVEL. Since
the monitor current is proportional to the laser diode light
power, the loop effectively controls laser power to a level pro-
portional to the analog input. T he control loop should be peri-
odically calibrated (see Choosing CHOLD).
T he relationship between IMONIT OR and VPOWER LEVEL is
VPOWER LEVEL –VREF
IMONITOR
=
(RGAIN +50 Ω)
once the loop is calibrated. When the loop is open (CAL = logic
HIGH), the output current, IOUT , is proportional to the held
voltage at H OLD; the external hold capacitor on this pin
determines the droop error in the output current between
calibrations.
T he sections below discuss choosing the external components in
the feedback loop for a particular application.
T he disable circuit turns off IOUT and returns the hold capacitor
voltages to their minimum levels (minimum output current)
when DISABLE = logic HIGH. It is used during initial power
up of the AD9661A or during time periods where the laser is
inactive. When the AD9661A is re-enabled the control loop
must be recalibrated.
Choosing RGAIN
T he gain resistor, RGAIN, allows the user to match the feedback
loop’s transfer function to the laser diode/photo diode
combination.
T he user should define the maximum laser diode output power
for the intended application, PLD MAX, and the corresponding
photo diode monitor current, IMONIT OR MAX. A typical laser
diode transfer function is illustrated below. RGAIN should be
chosen as:
Normal operation of the AD9661A involves the following (in
order, see Figure 1):
1. T he AD9661A is enabled (DISABLE = logic LOW).
1.6 V
I MONITOR MAX
2. T he input voltage (POWER LEVEL) is driven to the
appropriate level to set the calibrated laser diode output
power level.
RGAIN
=
–50 Ω
4
3
2
1
0
3. T he feedback loop is closed for calibration (CAL = logic
LOW, and PULSE = logic HIGH), and then opened (CAL
= logic HIGH).
0°C CASE
4. While the feedback loop is open, the laser is pulsed on and
off by PULSE.
25°C
CONSTANT WRITE POWER
CASE
5. T he feedback loop is periodically recalibrated as needed.
50°C CASE
6. T he AD9661A is disabled when the laser will not be pulsed
for an indefinite period of time.
0
20
40
60
80
100
120
FORWARD CURRENT – mA
IOUT
Figure 2. Laser Diode Current-to-Optical Power Curve
DISABLE
POWER-UP
OR LASER
NOT IN USE
CAL
TIME
RECALIBRATE
HOLD TIME
CAL
PULSE
LASER POWER
MODULATED
CALIBRATED LEVEL
LASER
OUTPUT POWER
Figure 1. Norm al Operating Mode
REV. 0
–5–
AD9661A
T he laser diode’s output power will then vary from 0 to PLD MAX
for an input range of VREF to VREF +1.6 V @ the POWER
LEVEL input.
T o choose a value, the user will need to determine the amount
of time the loop will be in hold mode, t HOLD, the maximum
change in laser output power the application can tolerate, and
the laser efficiency (defined as the change in laser output power
to the change in laser diode current). As an example, if an ap-
plication requires 5 mW of laser power ±5%, and the laser diode
efficiency is 0.25 mW/mA, then
Minimum specifications for IMONIT OR MAX should be used when
choosing RGAIN. Users are cautioned that laser diode/photo
diode combinations that produce monitor currents that are less
than IMONIT OR MAX in the equation above will produce higher la-
ser output power than predicted, which may damage the laser
diode. Such a condition is possible if RGAIN is calculated using
typical instead of minimum monitor current specifications. In
that case the input range to the AD9661A POWER LEVEL
input should be limited to avoid damaging laser diodes.
mW
mA
∆IMAX = 5 mW ×(5%)/ 0.25
=1.0 mA
If the same application had a hold time requirement of 250 µs,
then the minimum value of the hold capacitor would be:
Another approach would be to use a potentiometer for RGAIN
.
18 ×10–9 ×250 µs
T his allows users to optimize the value of RGAIN for each laser
diode/photo diode combination’s monitor current. T he draw-
back to this approach is that potentiometers’ stray inductance
and capacitance may cause the transimpedance amplifier to
overshoot and degrade its settling, and the value of CGAIN may
not be optimized for the entire potentiometer’s range.
CHOLD
=
= 4.5 nF
1.0 mA
When determining the calibration time, the T /H and the exter-
nal hold capacitor can be modeled using the simple RC circuit
illustrated below.
CGAIN optimizes the response of the transimpedance amplifier
and should be chosen as from the table below. Choosing CGAIN
larger than the recommended value will slow the response of the
amplifier. Lower values improve T ZA bandwidth but may cause
the amplifier to oscillate.
AD9661A
R
POWER LEVEL
HOLD
T/H
EXTERNAL HOLD
CAPACITOR
C
HOLD
Table I.
POWER MONITOR
TZA
Recom m ended
RGAIN
CGAIN
2.5 kΩ
1.5 kΩ
1 kΩ
2 pF
3 pF
4 pF
8 pF
Figure 3. Circuitry Model for Determ ining Calibration Tim es
Using this model, the voltage at the hold capacitor is
500 Ω
=Vt = 0 +(Vt = –Vt = 0 ) 1– e–τt
C
V
HOLD
Choosing C H O LD
∞
Choosing values for the hold capacitor, CHOLD, is a tradeoff
between output current droop when the control loop is open,
and the time it takes to calibrate and recalibrate the laser power
when the loop is closed.
where t = 0 is when the calibration begins (CAL goes logic
LOW), Vt = 0 is the voltage on the hold cap at t = 0, Vt = ∞ is the
steady state voltage at the hold cap with the loop closed, and
τ = RC
is the time constant. With this model the error in
HOfLoDr a finite calibration time, as compared to Vt = ∞, can
T he amount of output current droop is determined by the value
of the hold capacitor and the leakage current at that node.
When the control loop is open (CAL logic HIGH), the pin con-
nection for the hold capacitor (HOLD) is a high impedance in-
put. Leakage current will range from ±200; this low current
minimizes the droop in the output power level. Assuming the
worst case current of ±200 nA, the output current will change
as follows:
VC
be HesOtLiDmated from the following table and chart:
Table II.
tCALIBRATIO N
% Final Value
Error %
7τ
6τ
5τ
4τ
3τ
2τ
τ
99.9
99.7
99.2
98.1
95.0
86.5
63.2
0.09
0.25
0.79
1.83
4.97
13.5
36.8
18 ×10–9
±∆IOUT
=
CHOLD
–6–
REV. 0
AD9661A
100
90
80
70
60
50
40
30
20
10
0
D r iving the Analog Inputs
T he POWER LEVEL input of the AD9661A drives the track
and hold amplifier and allows the user to adjust the amount of
output current as described above. T he input voltage range is
VREF to VREF + 1.6 V, requiring the user to create an offset of
VREF for a ground based signal (see below for description of the
on board level shift circuit). T he circuit below will perform the
level shift and scale the output of a DAC whose output is from
ground to a positive voltage. T his solution is especially attrac-
tive because both the DAC and the op amp can run off a single
+5 V supply, and the op amp doesn’t have to swing rail to rail.
R2
R1
V
REF + VDAC
= VPOWER LEVEL
AD9661A
0
1
2
3
4
5
TIME CONSTANTS –
R2
+5V
Figure 4. Calibration Tim e
R1
VDAC
BIAS LEVEL
OP191
Initial calibration is required after power-up or any other time
the laser has been disabled. Disabling the AD9661A drives the
hold capacitor to ≈VREF. In this case, or in any case where the
output current is more than 10% out of calibration, R will range
from 300 Ω to 550 Ω for the model above; the higher value should
be used for calculating the worst case calibration time. Following
the example above, if CH OLD were chosen as 4.5 nF, then
τ = RC = 550 Ω × 4.5 nF would be 2.48 µs. For an initial
calibration error < 1%, the initial calibration time should be
> 5 τ = 12.36 µs.
R1
DAC
R2
VREF
Figure 5. Driving the Analog Inputs
Using the Level Shift Cir cuit
T he AD9661A includes an on board level shift circuit to provide
the offset described above. T he input, LEVEL SHIFT IN, has
an input range from 0.1 V to 1.6 V. T he output, LEVEL
SHIFT OUT , has a range from VREF to VREF +1.6 V, and can
drive POWER MONIT OR. T he linearity of the level shift cir-
cuit is poor for inputs below 100 mV. Between 100 mV and
1.6 V it is about 7 bits accurate.
Initial calibration time will actually be better than this calcula-
tion indicates, as a significant portion of the calibration time will
be within 10% of the final value, and the output resistance in
the AD9660’s T /H decreases as the hold voltage approaches its
final value.
Layout Consider ations
Recalibration is functionally identical to initial calibration, but
the loop need only correct for droop. Because droop is assumed
to be a small percentage of the initial calibration (< 10%), the
resistance for the model above will be in the range of 75 Ω to
140 Ω. Again, the higher value should be used to estimate the
worst case time needed for recalibration.
As in all high speed applications, proper layout is critical; it is
particularly important when both analog and digital signals are
involved. Analog signal paths should be kept as short as
possible, and isolated from digital signals to avoid coupling in
noise. In particular, digital lines should be isolated from
OUT PUT , SENSE IN, POWER LEVEL, LEVEL SHIFT IN
POWER MONIT OR, and HOLD traces. Digital signal paths
should also be kept short, and run lengths matched to avoid
propagation delay mismatch.
Continuing with the example above, since the droop error dur-
ing hold time is < 5%, we meet the criteria for recalibration and
τ = RC = 140 Ω × 4.5 nF = 0.64 µs. T o get a final error of 1%
after recalibration, the 5% droop must be corrected to within a
20% error (20% × 5% = 1%). A 2 τ recalibration time of 1.2 µs
is sufficient.
Layout of the ground and power supply circuits is also critical.
A single, low impedance ground plane will reduce noise on the
circuit ground. Power supplies should be capacitively coupled
to the ground plane to reduce noise in the circuit. 0.1 µF
surface mount capacitors, placed as close as possible to the
AD9661A +VS connections, and the +VS connection to the laser
diode meet this requirement. Multilayer circuit boards allow
designers to lay out signal traces without interrupting the ground
plane, and provide low impedance power planes to further
reduce noise.
Continuous Recalibr ation
In applications where the hold capacitor is small (< 500 pF) and
the WRIT E PULSE signals always have a pulse width > 25 ns,
the user may continuously calibrate the feedback loop. In such
an application, the CAL signal should be held logic LOW, and
the PULSE signal will control loop calibration via the internal
AND gate. In such application, it is important to optimize the
layout for the T ZA (POWER MONIT OR, GAIN, RGAIN and
C
GAIN).
REV. 0
–7–
AD9661A
Minim izing the Im pedance of the O utput Cur r ent P ath
Because of the very high current slew that the AD9661A is
capable of producing (120+ mA in 1.5 ns), the inductance of
the output current path to and from the laser diode is critical.
A good layout of the output current path will yield high quality
light pulses with rise times of about 1.5 ns and less than 5%
overshoot. A poor layout can result in significant overshoot and
ringing. T he most important guideline for the layout is to mini-
mize the impedance (mostly inductance) of the output current
path to the laser.
O ptim izing the Feedback Layout
In applications where the dynamic performance of the analog
feedback loop is important, it is necessary to optimize the layout
of the gain resistor, RGAIN, as well as the monitor current path to
SENSE IN. Such applications include systems which recali-
brate the write loop on pulses as short as 25 ns, and closed-loop
applications.
T he best possible T ZA settling will be achieved by using a single
carbon surface mount resistor (usually 5% tolerance) for RGAIN
and small surface mount capacitor for CGAIN. Because the
GAIN pin (Pin 5) is essentially connected to the inverting input
of the T ZA, it is very sensitive to stray capacitance. RGAIN
should be placed between Pin 5 and Pin 6, as close as possible
to Pin 5. Small traces should be used, and the ground and +VS
planes adjacent to the trace should be removed to further mini-
mize stray capacitance.
It is important to recognize that the laser current path is a
closed loop. T he figure illustrates the path that current travels:
(1) from the +VS connection at the anode of the laser to the
cathode (2) from the cathode to the output pins of the
AD9661A (3) through the output drive circuit of the
AD9661A, (4) through the return path (GROUND plane in the
illustration) (5) through the bypass capacitors back to the +VS
connection of the laser diode. T he inductance of this loop can
be minimized by placing the laser as close to the AD9661A as
possible to keep the loop short, and by placing the send and re-
turn paths on adjacent layers of the PC board to take advantage
of mutual coupling of the path inductances. T his mutual cou-
pling effect is the most important factor in reducing inductance
in the current path.
T he trace from SENSE IN to the anode of the PIN photodetec-
tor should be thin and routed away from the laser cathode trace.
Exam ple Calculations
T he example below (in addition to the one included in the sec-
tions above) should guide users in choosing RGAIN, CGAIN, the
hold capacitor values, and worst case calibration times.
System Requirements:
T he trace from the output pins of the AD9661A to the cathode
of the laser should be several millimeters wide and should be as
direct as possible. T he return current will choose the path of
least resistance. If the return path is the GROUND plane, it
should have an unbroken path, under the output trace, from the
laser anode back to a the AD9661A. If the return path is not
the ground plane (such as on a two layer board, or on the +VS
plane), it should still be on the board plane adjacent to the
plane of the output trace. If the current cannot return along a
path that follows the output trace, the inductance will be drasti-
cally increased and performance will be degraded.
•
•
Laser power: 4 mW ± 2%
Hold T ime: 0.5 ms
Laser diode/photo diode characteristics:
•
•
•
Laser efficiency 0.3 mW/mA
Monitor current : 0.2 mA/mW
From the laser power requirements and efficiency we can
estimate:
mW
mA
∆IOUT MAX = 4 mW ×(2.0%)/ 0.3
= 266.6 µA.
+VS PLANE
PIN ASSIGNMENTS
2
OUTPUT PIN
CONNECTIONS
1
5
26
25
24
23
22
21
BYPASS CAPS
AD9661A
MUTUAL COUPLING
REDUCES INDUCTANCE
3
20
19
GROUND PLANE
GROUND PIN
CONNECTIONS
4
LASER DIODE CURRENT
PATH SEGMENTS (See Text)
Figure 6. Laser Diode Current Loop
–8–
REV. 0
AD9661A
•
Choosing a hold caps based on this:
•
From the monitor current specification and the max power
specified:
18 ×10–9 ×0.5 ms
CHOLD
=
= 0.034 µF
266.6 µA
0.2 mA
IMONITOR MAX = 4 mW
= 800 µA
•
•
T he initial calibration time for < 0.1% error:
mW
7 τ = 7 × RC = 7 × 550 Ω × 0.034 µF = 130.9 µs
and
Recalibration for a 0.1% error after 2% droop (need to
correct within 5%):
1. 6 V
I MONITOR MAX
RGAIN
=
– 50 Ω = 2.0 kΩ
3 τ = 3 RC = 3 × 140 Ω × 0.034 µF = 14.28 µs
•
CGAIN would be chosen from the table as 3 pF for safe
compensation.
Typical Performance Characteristics
PULSE INPUT (TTL)
LASER POWER
20mV/DIV
20ns/DIV
LASER POWER
20mV/DIV
1ns/DIV
Figure 7. Driving 78N20 Laser Diode @ 5 m W
–9–
REV. 0
AD9661A–Typical Performance Characteristics
180
4.2
160
140
120
100
80
60
40
20
10mV
20ns
0
1.7
2
2.3
2.6
2.9
V
3.2
– V
3.5
3.8
4.1
4.4
+5V
HOLD
1kΩ
33pF
10Ω
Figure 8. Typical AD9661A V/I Transfer Function
TO
SCOPE
HOLD
AD9661A
MPSH81
POWER MONITOR
1kΩ
2pF
SENSE IN
OUTPUT
GAIN
3V
2V
POWER LEVEL
LOW
HIGH
PULSEL
Figure 9. Typical AD9661A Closed-Loop Pulse Response
–10–
REV. 0
AD9661A
AD 9661A EVALUATIO N BO ARD
laser diode. A dummy load circuit for the laser diode is in-
cluded for evaluation. Power for all the boards is provided
through the banana jacks on the AD9661A DUT board.
T hese should be connected to a linear, +5 V power supply.
Schematics for the LDD Resource Board, AD9661A DUT ,
and Dummy Load are included, along with a bill of mate-
rial and layout information. Please contact Applications for
additional information.
T he AD9661A Evaluation Board is comprised of two printed
circuit boards. T he Laser Diode Driver (LDD) Resource Board
is both a digital pattern generator and an analog reference gen-
erator (see LDD Resource Board Block Diagram.) T he board is
controlled by an IBM compatible personal computer through a
standard printer cable. T he resource board interfaces to the
AD9661A DUT board, which contains the AD9661A, a level
shift circuit for the analog input, and a socket for an N type
OUTPUT
SMB
CONNECTORS
40MHz
32K x 16
CLOCK
MEMORY
OSCILLATOR
PULSE
WIDTH
MODULATOR
STANDARD PARALLEL
PRINTER CABLE
J4
(AD9560)
PULSE1 (JPUL)
P1
ADDRESS
J5
J7
J8
COUNTER
AND
RESOURCE
CONTROLLER
IBM-COMPATIBLE
PC
CAL (JCALB)
READBACK
LATCH
CENTRONICS
CONNECTOR
DISABLE (JDIS)
PULSE2 (JPULB)
WITH WINDOWS
OUTPUT
BUFFER
PARALLEL
PRINTER PORT
J6
J2
INTERFACE TO
AD9661A
UNUSED
TRIGGER
DIGITAL PATTERN GENERATOR
EVALUATION
BOARD
J3
0–2.55V
12
11
8
8
DAC 1
X1
EXTERNAL LEVEL SHIFT CIRCUIT
AD9661A
R9
LEVEL SHIFT IN
R8
0–2.55V
DAC 2
X1
17–20
1–10
20-PIN
HEADER
+5V POWER SUPPLY
GROUND
ANALOG REFERENCE
LASER DIODE DRIVER RESOURCE BOARD
Figure 10. LDD Resource Board Block Diagram
INPUT SMB CONNECTORS
FOR DIGITAL CONTROLS
5
AD9661A
DUMMY LOAD CIRCUIT/
LASER DIODE SOCKET
20
20-PIN HEADER
FOR ANALOG
CONTROLS
OPTIONAL
LEVEL SHIFT
CIRCUIT
AD9661A
EVALUATION BOARD
Figure 11. Evaluation Board Block Diagram
REV. 0
–11–
AD9661A
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-P in P lastic SO IC
(R-28)
0.712 (18.08)
0.700 (17.78)
28
15
0.419 (10.64)
0.393 (9.98)
0.300 (7.60)
0.292 (7.40)
1
14
PIN 1
0.104 (2.64)
0.093 (2.36)
0.012 (0.30)
0.004 (0.10)
0.0500
(1.27)
BSC
0.019 (0.48)
0.04 (1.02)
0.013 (0.33)
0.009 (0.23)
SEATING
PLANE
0.014 (0.36)
0.024 (0.61)
–12–
REV. 0
相关型号：
AD9662ARQZ-REEL7
IC SPECIALTY INTERFACE CIRCUIT, PDSO16, LEAD FREE,MO-137AB,QSOP-16, Interface IC:Other
ADI
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