AD9706BCPZRL7_技术文档

8-/10-/12-/14-Bit, 175 MSPS

TxDAC^®D/A Converters

AD9704/AD9705/AD9706/AD9707

FUNCTIONAL BLOCK DIAGRAM

FEATURES

1.7V TO 3.6V

Pin-compatible family

Low power member of pin-compatible

TxDAC product family

AVDD

ACOM

1.0V REF

REFIO

0.1µF

AD9707

CURRENT

SOURCE

ARRAY

OTCM

FS ADJ

1.7V

TO

Power dissipation @ 3.3 V

22 mW @ 10 MSPS

25 mW @ 25 MSPS

CLKVDD

CLKCOM

IOUTA

IOUTB

R

SET

SEGMENTED

SWITCHES

LSB

SWITCHES

3.6V

CLK+

CLK–

PIN/SPI/RESET

MODE/SDIO

LATCHES

SPI

1.7V TO

3.6V

30 mW @ 50 MSPS

Sleep mode: 3.1 mW @ 3.3 V

CMODE/SCLK

DVDD

DCOM

SLEEP/CSB

DIGITAL INPUTS (DB13 TO DB0)

Supply voltage: 1.7 V to 3.6 V

SFDR to Nyquist

Figure 1. AD9707

AD9707: 84 dBc @ 5 MHz output

AD9707: 83 dBc @ 10 MHz output

AD9707: 75 dBc @ 20 MHz output

AD9707 NSD @ 10 MHz output, 125 MSPS: −147 dBc/Hz

Differential current outputs: 1 mA to 5 mA

Data format: twos complement or straight binary

On-chip 1.0 V reference

CMOS-compatible digital interface

Edge-triggered latches

Clock input: single-ended and differential

Output common mode: adjustable 0 V to 1.2 V

Power-down mode < 2 mW @ 3.3 V (SPI® controllable)

Serial peripheral interface (SPI)

Self-calibration

32-lead LFCSP_VQ, Pb-free package

PRODUCT HIGHLIGHTS

5. CMOS Clock Input. High speed, single-ended, and

differential CMOS clock input supports 175 MSPS

conversion rate.

1. Pin Compatible. The AD970x line of TxDACs is pin-

compatible with the AD974x TxDAC line (LFCSP_VQ

package).

2. Low Power. Complete CMOS DAC operates on a single

supply of 3.6 V down to 1.7 V, consuming 25 mW (3.3 V)

and 10 mW (1.8 V). The DAC full-scale current can be

reduced for lower power operation, and sleep and power-

down modes are provided for low power idle periods.

6. SPI Control. SPI control offers a higher level of

programmability.

7. Easy Interfacing to Other Components. Adjustable output

common mode from 0 V to 1.2 V allows for easy interfacing

to other components that accept common-mode levels

greater than 0 V.

3. Self-calibration. Self-calibration enables true 14-bit INL

and DNL performance in the AD9707.

8. On-Chip Voltage Reference. The AD970x includes a 1.0 V

temperature-compensated band gap voltage reference.

4. Twos Complement/Binary Data Coding Support. Data input

supports twos complement or straight binary data coding.

9. Industry-Standard 32-Lead LFCSP_VQ Package.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9704/AD9705/AD9706/AD9707

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 29

Serial Peripheral Interface......................................................... 29

SPI Register Map ........................................................................ 31

SPI Register Descriptions.......................................................... 32

Reference Operation .................................................................. 34

Reference Control Amplifier .................................................... 34

DAC Transfer Function............................................................. 34

Analog Outputs .......................................................................... 35

Adjustable Output Common Mode......................................... 35

Digital Inputs .............................................................................. 36

Clock Input.................................................................................. 36

DAC Timing................................................................................ 36

Power Dissipation....................................................................... 36

Self-Calibration........................................................................... 38

Applications..................................................................................... 40

Output Configurations.............................................................. 40

Differential Coupling Using a Transformer ............................... 40

Single-Ended Buffered Output Using an Op Amp................ 40

Differential Buffered Output Using an Op Amp ................... 41

Evaluation Board ............................................................................ 42

General Description................................................................... 42

Evaluation Board Schematics ................................................... 43

Evaluation Board Layout........................................................... 48

Outline Dimensions....................................................................... 51

Ordering Guide .......................................................................... 51

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

DC Specifications (3.3 V)............................................................ 4

Dynamic Specifications (3.3 V).................................................. 5

Digital Specifications (3.3 V)...................................................... 6

DC Specifications (1.8 V)............................................................ 7

Dynamic Specifications (1.8 V).................................................. 8

Digital Specifications (1.8 V)...................................................... 9

Timing Diagram ........................................................................... 9

Absolute Maximum Ratings.......................................................... 10

Thermal Characteristics ............................................................ 10

ESD Caution................................................................................ 10

Pin Configurations and Function Descriptions ......................... 11

AD9707........................................................................................ 11

AD9706........................................................................................ 12

AD9705........................................................................................ 13

AD9704........................................................................................ 14

Typical Performance Characteristics ........................................... 15

AD9707........................................................................................ 15

AD9704, AD9705, and AD9706............................................... 22

Terminology .................................................................................... 28

REVISION HISTORY

7/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 52

AD9704/AD9705/AD9706/AD9707

GENERAL DESCRIPTION

The AD9704/AD9705/AD9706/AD9707 are the fourth-

generation family in the TxDAC series of high performance,

CMOS digital-to-analog converters (DACs). This pin-compatible,

8–/10–/12–/14–bit resolution family is optimized for low power

operation, while maintaining excellent dynamic performance.

The AD970x family is pin-compatible with the AD9748/AD9740/

AD9742/AD9744 family of TxDAC converters and is specifically

optimized for the transmit signal path of communication systems.

All of the devices share the same interface, LFCSP_VQ package,

and pinout, providing an upward or downward component

selection path based on performance, resolution, and cost.

The AD970x offers exceptional ac and dc performance, while

supporting update rates up to 175 MSPS.

Power dissipation of the AD970x can be reduced to 15 mW, with

a small trade-off in performance, by lowering the full-scale

current output. In addition, a power-down mode reduces the

standby power dissipation to approximately 2.2 mW.

The AD970x has an optional serial peripheral interface (SPI) that

provides a higher level of programmability to enhance performance

of the DAC. An adjustable output, common-mode feature allows

for easy interfacing to other components that require common

modes greater than 0 V.

Edge-triggered input latches and a 1.0 V temperature-compensated

band gap reference have been integrated to provide a complete,

monolithic DAC solution. The digital inputs support 1.8 V and

3.3 V CMOS logic families.

The flexible power supply operating range of 1.7 V to 3.6 V and

low power dissipation of the AD970x parts make them well-suited

for portable and low power applications.

Rev. 0 | Page 3 of 52

AD9704/AD9705/AD9706/AD9707

SPECIFICATIONS

DC SPECIFICATIONS (3.3 V)

T_MINto T_MAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I_OUTFS= 2 mA, unless otherwise noted.

Table 1.

AD9707

Typ

AD9706

Typ

AD9705

Typ

AD9704

Typ

Parameter

RESOLUTION

DC ACCURACY¹

Min

14

Max Min

Max Unit

12

10

8

Bits

Integral Nonlinearity (INL)

Precalibration

±1.4

±0.9

±1.2

±0.4

±±.0

±4.4

±0.41 ±1.48

±0.30

±0.10 ±0.3±

±0.10

±0.03 ±0.09 LSB

Integral Nonlinearity (INL)

Postcalibration

LSB

±0.02 ±0.08 LSB

LSB

Differential Nonlinearity (DNL)

Precalibration

±0.35 ±1.17

±0.13

±0.09 ±0.31

±0.03

Differential Nonlinearity (DNL)

Postcalibration

ANALOG OUTPUT

Offset Error

−0.03

−2.7

0

+0.03 −0.03

0

+0.03 −0.03

0

+0.03 −0.03

0

+0.03 % of FSR

Gain Error (With External

Reference)

−0.1

+2.7

−2.7

−0.1

+2.7

−2.7

−0.1

+2.7

−2.7

−0.1

+2.7

% of FSR

Gain Error (With Internal

Reference)

Full-Scale Output Current²

Output Compliance Range

(From OTCM to IOUTA/IOUTB)

Output Resistance

−2.7

−0.1

2

+2.7

−2.7

−0.1

2

+2.7

−2.7

−0.1

2

+2.7

−2.7

−0.1

2

+2.7

% of FSR

1

5

1

5

1

5

1

5

mA

V

−0.8

+0.8

−0.8

+0.8

−0.8

+0.8

−0.8

+0.8

200

5

200

5

200

5

200

5

MΩ

pF

Output Capacitance

REFERENCE OUTPUT

Reference Voltage

0.98

0.1

1.025 1.08

100

0.98

0.1

1.025 1.08

100

0.98

0.1

1.025 1.08

100

0.98

0.1

1.025 1.08

100

V

Reference Output Current³

nA

REFERENCE INPUT

Input Compliance Range

1.25

10

1.25

10

1.25

10

1.25

10

V

Reference Input Resistance

(Reference Powered Up)

kΩ

Reference Input Resistance

(Reference Powered Down)

1

MΩ

Small Signal Bandwidth

TEMPERATURE COEFFICIENTS

Offset Drift

0.5

MHz

0

ppm of

FSR/°C

Gain Drift (Without Internal

Reference)

±29

±40

±25

±29

±40

±25

±29

±40

±25

±29

±40

±25

ppm of

FSR/°C

Gain Drift (With Internal

Reference)

ppm of

FSR/°C

Reference Voltage Drift

POWER SUPPLY

Supply Voltages

AVDD

ppm/°C

3.3

3.±

±.7

±.±

4.7

57

3.3

3.±

±.7

±.±

4.7

57

3.3

3.±

±.7

±.±

4.7

57

3.3

3.±

±.7

±.±

4.7

57

V

DVDD

V

CLKVDD

3.3

V

Analog Supply Current (I_AVDD

)

5.2

5.1

mA

mW

mA

4

Digital Supply Current (I_DVDD

)

5.9

5.4

5.0

4.±

4

Clock Supply Current (I_CLKVDD

Power Dissipation⁴

)

4.1

50.2

0.37

48.5

0.37

4±.9

0.37

45.5

0.37

Supply Current Sleep Mode

0.4

(I_AVDD

Supply Current Power-Down

Mode (I_AVDD

)

0.7

7.5

0.7

7.5

0.7

7.5

μA

)

Rev. 0 | Page 4 of 52

AD9704/AD9705/AD9706/AD9707

AD9707

Typ

AD9706

Typ

AD9705

Typ

AD9704

Typ Max Unit

Parameter

Min

Max Min

Supply Current Clock Power-

0.±

1

0.±

1

0.±

1

0.±

1

mA

5

Down Mode (I_DVDD

Supply Current Clock Power-

Down Mode (I_CLKVDD

)

42.5

58

42.5

58

42.5

58

42.5

58

μA

)

Power Supply Rejection Ratio

(AVDD)^±

−0.2

−40

+0.03 +0.2

+85

−0.2

−40

+0.03 +0.2

+85

−0.2

−40

+0.03 +0.2

+85

−0.2

−40

+0.03 +0.2

+85

% of FSR/V

°C

OPERATING RANGE

¹Measured at IOUTA, driving a virtual ground, at 25°C only.

²Nominal full-scale current, I_OUTFS, is 32× the I_REFcurrent.

³An external buffer amplifier with input bias current < 100 nA should be used to drive any external load.

⁴Measured at f_CLOCK= 175 MSPS and f_OUT= 1.0 MHz, using differential clock.

⁵Measured at f_CLOCK= 100 MSPS and f_OUT= 1.0 MHz, using differential clock.

^±±5% power supply variation.

DYNAMIC SPECIFICATIONS (3.3 V)

T_MINto T_MAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I_OUTFS= 2 mA, differential transformer coupled output,

453 Ω differentially terminated,¹unless otherwise noted.

Table 2.

AD9707

Min Typ

AD9706

Max Min Typ

AD9705

Max Min Typ

AD9704

Max Min Typ

Parameter

Max Unit

DYNAMIC PERFORMANCE

Maximum Output Update Rate (f_CLOCK

)

175

MSPS

ns

Output Settling Time (t_ST) (to 0.1%)²

11

4

11

4

11

4

11

4

Output Propagation Delay (t_PD

)

ns

Glitch Impulse

5

pV-s

ns

Output Rise Time (10% to 90%)²

Output Fall Time (10% to 90%)²

AC LINEARITY

2.5

ns

Spurious-Free Dynamic Range

to Nyquist

f_CLOCK= 10 MSPS; f_OUT= 2.1 MHz

f_CLOCK= 25 MSPS; f_OUT= 2.1 MHz

f_CLOCK= ±5 MSPS; f_OUT= 5.1 MHz

f_CLOCK= ±5 MSPS; f_OUT= 10.1 MHz

f_CLOCK= 80 MSPS; f_OUT= 1.0 MHz

f_CLOCK= 125 MSPS; f_OUT= 15.1 MHz

f_CLOCK= 125 MSPS; f_OUT= 25.1 MHz

f_CLOCK= 175 MSPS; f_OUT= 20.1 MHz

f_CLOCK= 175 MSPS; f_OUT= 40.1 MHz

Noise Spectral Density

84

83

78

77

75

72

84

83

84

83

82

78

77

75

71

84

83

82

78

7±

75

71

70

±8

70

71

70

±8

±9

±7

dBc

74

72

±±

f_CLOCK= 175 MSPS; f_OUT= ±.0 MHz;

I_OUTFS= 2 mA

−149

−14±

10.9

−137

9.5

−127

8.0

dBc/

Hz

ENOB at I_OUTFS= 2 mA

11.3

bits

f_CLOCK= 175 MSPS; f_OUT= ±.0 MHz;

I_OUTFS= 5 mA

−157

dBc/

Hz

ENOB at I_OUTFS= 5 mA

12.5

bits

f_CLOCK= 175 MSPS; f_OUT= ±.0 MHz;

I_OUTFS= 1 mA

−145

dBc/

Hz

ENOB at I_OUTFS= 1 mA

10.±

bits

¹See Figure 71 for diagram.

²Measured single-ended into 500 Ω load.

Rev. 0 | Page 5 of 52

AD9704/AD9705/AD9706/AD9707

DIGITAL SPECIFICATIONS (3.3 V)

T_MINto T_MAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I_OUTFS= 2 mA, unless otherwise noted.

Table 3.

AD9707

Typ

AD9706

Typ

AD9705

Typ

AD9704

Typ

Parameter

Min

2.1

Max

Min

2.1

Max

Min

2.1

Max

Min

2.1

Max

Unit

DIGITAL INPUTS¹

Logic 1 Voltage

Logic 0 Voltage

Logic 1 Current

Logic 0 Current

Input Capacitance

Input Setup Time (t_S)

Input Hold Time (t_H)

Latch Pulsewidth (t_LPW

CLK INPUTS²

3

0

3

0

3

0

3

0

V

0.9

+10

10

0.9

+10

10

0.9

+10

10

0.9

+10

10

−10

ꢀA

pF

ns

5

1.3

0.7

2.8

1.3

0.7

2.8

1.3

0.7

2.8

1.3

0.7

2.8

)

Input Voltage Range

Common-Mode Voltage

Differential Voltage

0

0.75

0.5

3

2.25

0

0.75

0.5

3

2.25

0

0.75

0.5

3

2.25

0

0.75

0.5

3

2.25

V

1.5

¹Includes CLK+ pin in single-ended clock input mode.

²Applicable to CLK+ input and CLK– input when configured for differential clock input mode.

Rev. 0 | Page ± of 52

AD9704/AD9705/AD9706/AD9707

DC SPECIFICATIONS (1.8 V)

T_MINto T_MAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, I_OUTFS= 2 mA, unless otherwise noted.

Table 4.

AD9707

Typ

AD9706

Typ

AD9705

Typ

AD9704

Typ

Parameter

RESOLUTION

DC ACCURACY¹

Min

14

Max

Min

12

Max

Min

10

Max

Min

8

Max

Unit

Bits

Integral Nonlinearity (INL)

Precalibration

±1.4

±1.2

±±.03

±4.34

±0.42

±0.3±

±1.50

±1.17

±0.10

±0.09

±0.3±

±0.30

±0.03

±0.02

±0.09

±0.07

LSB

Differential Nonlinearity (DNL)

Precalibration

ANALOG OUTPUT

Offset Error

−0.03

−2.7

0

+0.03

+2.7

−0.03

−2.7

0

+0.03

+2.7

−0.03

−2.7

0

+0.03

+2.7

−0.03

−2.7

0

+0.03

+2.7

% of FSR

Gain Error (With Internal

Reference)

−0.2

Full-Scale Output Current²

Output Compliance Range

(With OTCM = AGND)

Output Resistance

1

2

5

1

2

5

1

2

5

1

2

5

mA

V

−0.8

+0.8

−0.8

+0.8

−0.8

+0.8

−0.8

+0.8

200

5

200

5

200

5

200

5

MΩ

pF

Output Capacitance

REFERENCE OUTPUT

Reference Voltage

0.98

0.1

1.025

100

1.08

1.25

0.98

0.1

1.025

100

1.08

1.25

0.98

0.1

1.025

100

1.08

1.25

0.98

0.1

1.025

100

1.08

1.25

V

Reference Output Current³

nA

REFERENCE INPUT

Input Compliance Range

V

Reference Input Resistance

(Reference Powered Up)

10

1

10

1

10

1

10

1

kΩ

Reference Input Resistance

(External Reference)

MΩ

Small Signal Bandwidth

TEMPERATURE COEFFICIENTS

Offset Drift

0.5

MHz

0

ppm of

FSR/°C

Gain Drift (Without Internal

Reference)

±30

±±0

±25

±30

±±0

±25

±30

±±0

±25

±30

±±0

±25

ppm of

FSR/°C

Gain Drift (With Internal

Reference)

ppm of

FSR/°C

Reference Voltage Drift

POWER SUPPLY

Supply Voltages

AVDD

ppm/°C

1.7

1.8

3.8

1.7

1.8

3.8

1.7

1.8

3.8

1.7

1.8

3.8

V

DVDD

V

CLKVDD

V

Analog Supply Current

4.8

1.5

4.8

1.5

4.8

1.5

4.8

1.5

mA

(I_AVDD

)

Digital Supply Current

1.3

1.2

1.3

1.1

1.3

1.0

1.3

mA

4

(I_DVDD

)

Clock Supply Current

4

(I_CLKVDD

)

Power Dissipation⁴

11.5

0.3

13.2

0.4

11.3

0.3

13.2

0.4

11.1

0.3

13.2

0.4

11.0

0.3

13.2

0.4

mW

mA

Supply Current Sleep

Mode (I_AVDD

Supply Current Power-

Down Mode (I_AVDD

Supply Current Power-

Down Mode (I_AVDD

)

5

±

5

±

5

±

5

±

μA

)

0.2

0.3

0.2

0.3

0.2

0.3

0.2

0.3

mA

)

Rev. 0 | Page 7 of 52

AD9704/AD9705/AD9706/AD9707

AD9707

AD9706

Typ

AD9705

Typ

AD9704

Typ

Parameter

Min

Typ

Max

Min

Max

Min

Max

Min

Max

Unit

Supply Current Clock

Power-Down Mode (I_DVDD

0.22

0.28

0.22

0.28

0.22

0.28

0.22

0.28

mA

4

)

Supply Current Clock

Power-Down Mode (I_CLKVDD

9.5

1±

9.5

1±

9.5

1±

9.5

1±

μA

4

)

Power Supply Rejection

Ratio (AVDD)⁵

−1

−0.1

+1

−1

−0.1

+1

−1

−0.1

+1

−1

−0.1

+1

% of

FSR/V

OPERATING RANGE

−40

+85

−40

+85

−40

+85

−40

+85

°C

¹Measured at IOUTA, driving a virtual ground, at 25°C only.

²Nominal full-scale current, I_OUTFS, is 32× the I_REFcurrent.

³An external buffer amplifier with input bias current < 100 nA should be used to drive any external load.

⁴Measured at f_CLOCK= 80 MSPS and f_OUT= 1 MHz, using differential clock.

⁵±5% power supply variation, I_OUTFS= 1 mA, at 25°C only.

DYNAMIC SPECIFICATIONS (1.8 V)

T_MINto T_MAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, I_OUTFS= 1 mA, differential transformer coupled output,

453 Ω differentially terminated,¹unless otherwise noted.

Table 5.

AD9707

Typ

AD9706

Max Min Typ

AD9705

Typ

AD9704

Min Typ

Min

Max

Min

Max

Max Unit

Parameter

DYNAMIC PERFORMANCE

Maximum Output Update Rate

80

MSPS

(f_CLOCK

)

Output Settling Time (t_ST) (to 0.1%)²

11

5.±

5

11

5.±

5

11

5.±

5

11

5.±

5

ns

Output Propagation Delay (t_PD

)

ns

Glitch Impulse

pV-s

ns

Output Rise Time (10% to 90%)²

Output Fall Time (10% to 90%)²

AC LINEARITY

2.5

ns

Spurious-Free Dynamic Range

to Nyquist

f_CLOCK= 10 MSPS; f_OUT= 2.1 MHz

f_CLOCK= 25 MSPS; f_OUT= 2.1 MHz

f_CLOCK= 25 MSPS; f_OUT= 5.1 MHz

f_CLOCK= ±5 MSPS; f_OUT= 10.1 MHz

f_CLOCK= ±5 MSPS; f_OUT= 15.1 MHz

f_CLOCK= 80 MSPS; f_OUT= 1.0 MHz

f_CLOCK= 80 MSPS; f_OUT= 15.1 MHz

f_CLOCK= 80 MSPS; f_OUT= 30.1 MHz

Noise Spectral Density

8±

87

82

77

82

77

±0

8±

82

79

7±

82

77

59

85

84

82

78

74

82

77

59

70

±8

70

±9

70

±8

±0

dBc

74

72

±±

f_CLOCK= 80 MSPS; f_OUT= 10 MHz;

I_OUTFS= 1 mA

−141.0

−139.4

10.2

−135.1

9.5

−12±.3

8.0

dBc/

Hz

ENOB at I_OUTFS= 1 mA

10.5

bits

f_CLOCK= 80 MSPS; f_OUT= 10 MHz;

I_OUTFS= 2 mA

−145.7

dBc/

Hz

ENOB at I_OUTFS= 2 mA

10.3

Bits

¹See Figure 71 for diagram.

²Measured single-ended into 500 Ω load.

Rev. 0 | Page 8 of 52

AD9704/AD9705/AD9706/AD9707

DIGITAL SPECIFICATIONS (1.8 V)

T_MINto T_MAX, AVDD = 1.8 V, DVDD = 1.8 V, CLKVDD = 1.8 V, I_OUTFS= 1 mA, unless otherwise noted.

Table 6.

AD9707

Typ

AD9706

Typ

AD9705

Typ

AD9704

Typ

Parameter

Min

1.2

Max

Min

1.2

Max

Min

1.2

Max

Min

1.2

Max

Unit

DIGITAL INPUTS¹

Logic 1 Voltage

Logic 0 Voltage

1.8

0

1.8

0

1.8

0

1.8

0

V

0.5

Logic 1 Current

Logic 0 Current

−10

+10

−10

+10

−10

+10

−10

+10

ꢀA

pF

ns

Input Capacitance

Input Setup Time (t_S)

Input Hold Time (t_H)

Latch Pulsewidth (t_LPW

CLK INPUTS²

5

2.4

0.4

±.2

2.4

0.4

±.2

2.4

0.4

±.2

2.4

0.4

±.2

)

Input Voltage Range

Common-Mode Voltage

Differential Voltage

0

0.4

0.5

1.8

1.3

0

0.4

0.5

1.8

1.3

0

0.4

0.5

1.8

1.3

0

0.4

0.5

1.8

1.3

V

0.9

1.5

0.9

1.5

0.9

1.5

0.9

1.5

¹Includes CLK+ pin in single-ended clock input mode.

²Applicable to CLK+ input and CLK– input when configured for differential clock input mode.

TIMING DIAGRAM

DBO TO DB13

t_S

t_H

CLOCK

t_LPW

t_ST

t_PD

IOUTA

OR

IOUTB

0.1%

Figure 2. Timing Diagram

Rev. 0 | Page 9 of 52

AD9704/AD9705/AD9706/AD9707

ABSOLUTE MAXIMUM RATINGS

Table 7.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

With

Parameter

AVDD

Respect to Rating

ACOM

−0.3 V to +3.9 V

DVDD

DCOM

−0.3 V to +3.9 V

CLKVDD

ACOM

CLKCOM

DCOM

−0.3 V to +3.9 V

−0.3 V to +0.3 V

ACOM

DCOM

AVDD

CLKCOM

DVDD

−0.3 V to +0.3 V

−3.9 V to +3.9 V

THERMAL CHARACTERISTICS¹

Table 8. Thermal Resistance

AVDD

DVDD

CLKVDD

DCOM

ACOM

−3.9 V to +3.9 V

−0.3 V to DVDD + 0.3 V

−1.0 V to AVDD + 0.3 V

−0.3 V to AVDD + 0.3 V

Package Type

θ_JA

Unit

32-Lead LFCSP_VQ

32.5

°C/W

CLOCK, SLEEP

Digital Inputs, MODE

IOUTA, IOUTB

REFIO, REFLO, FS ADJ,

OTCM

¹Thermal impedance measurements were taken on a 4-layer board in still air,

in accordance with EIA/JESD51-7.

ACOM

CLK+, CLK–, CMODE

JunctionTemperature

CLKCOM

−0.3 V to CLKVDD + 0.3 V

150°C

Storage Temperature

Range

−±5°C to +150°C

Lead Temperature

(10 sec)

300°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. 0 | Page 10 of 52

AD9704/AD9705/AD9706/AD9707

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AD9707

DB7

DB6

DVDD

DB5

DB4

1

2

3

4

5

6

7

24 FS ADJ

23 REFIO

22 ACOM

21 IOUTA

20 IOUTB

19 OTCM

18 AVDD

PIN 1

INDICATOR

AD9707

TOP VIEW

(Not to Scale)

DB3

DB2

DB1

8

17 PIN/SPI/RESET

Figure 3. AD9707 Pin Configuration

Table 9. AD9707 Pin Function Descriptions

Pin No.

Mnemonic

DB13 (MSB)

DB12 to DB1

Description

27

28 to 32,

Most Significant Data Bit (MSB).

Data Bit 12 to Data Bit 1.

1, 2, 4 to 8

9

DB0 (LSB)

Least Significant Data Bit (LSB).

25

SLEEP/CSB

In pin mode, active high powers down chip.

In SPI mode, this pin is the serial port chip select (active low).

23

REFIO

Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference

output when internal reference activated. Requires a 0.1 μF capacitor to ACOM when internal reference activated.

24

22

20

21

18

19

17

FS ADJ

ACOM

IOUTB

IOUTA

AVDD

Full-Scale Current Output Adjust.

Analog Common.

Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.

DAC Current Output. Full-scale current is sourced when all data bits are 1s.

Analog Supply Voltage (1.7 V to 3.± V).

Adjustable Output Common Mode. Refer to the Theory of Operation section for details.

Selects SPI mode or pin mode operation. Active high for pin mode operation. Active low for SPI mode

operation. Pulse high to reset SPI registers to default values.

OTCM

PIN/SPI/RESET

1±

15

MODE/SDIO

In pin mode, this selects the input data format. Connect to DCOM for straight binary, DVDD for twos complement.

In SPI mode, this pin acts as SPI data input/output.

In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver

(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver.

In SPI mode, this pin is the serial data clock input.

CMODE/SCLK

14

13

12

11

10, 2±

3

CLKCOM

CLK−

CLK+

CLKVDD

DCOM

DVDD

Clock Common.

Differential Clock Input.

Clock Supply Voltage (1.7 V to 3.± V).

Digital Common.

Digital Supply Voltage (1.7 V to 3.± V).

Rev. 0 | Page 11 of 52

AD9704/AD9705/AD9706/AD9707

AD9706

DB5

1

2

3

4

5

6

7

24 FS ADJ

23 REFIO

22 ACOM

21 IOUTA

20 IOUTB

19 OTCM

18 AVDD

PIN 1

INDICATOR

DB4

DVDD

DB3

DB2

DB1

AD9706

TOP VIEW

(Not to Scale)

DB0 (LSB)

NC

8

17 PIN/SPI/RESET

NC = NO CONNECT

Figure 4. AD9706 Pin Configuration

Table 10. AD9706 Pin Function Descriptions

Pin No.

Mnemonic

DB11 (MSB)

DB10 to DB1

Description

27

28 to 32,

Most Significant Data Bit (MSB).

Data Bit 10 to Data Bit 1.

1, 2, 4 to ±

7

DB0 (LSB)

Least Significant Data Bit (LSB).

25

SLEEP/CSB

In pin mode, active high powers down chip.

In SPI mode, this pin is the serial port chip select (active low).

Full-Scale Current Output Adjust.

Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference

output when internal reference activated. Requires a 0.1 μF capacitor to ACOM when internal reference activated.

24

23

FS ADJ

REFIO

22

21

20

19

18

17

ACOM

IOUTA

IOUTB

OTCM

AVDD

PIN/SPI/RESET

Analog Common.

DAC Current Output. Full-scale current is sourced when all data bits are 1s.

Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.

Adjustable Output Common Mode. Refer to the Theory of Operation section for details.

Analog Supply Voltage (1.7 V to 3.± V).

Selects SPI mode or pin mode operation. Active high for pin mode operation. Active low for SPI mode operation.

Pulse high to reset SPI registers to default values.

1±

15

MODE/SDIO

In pin mode, this selects the input data format. Connect to DCOM for straight binary, DVDD for twos complement.

In SPI mode, this pin acts as SPI data input/output.

CMODE/SCLK In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver

(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver.

In SPI mode, this pin is the serial data clock input.

14

13

12

11

10, 2±

8, 9

3

CLKCOM

CLK−

CLK+

CLKVDD

DCOM

NC

Clock Common.

Differential Clock Input.

Clock Supply Voltage (1.7 V to 3.± V).

Digital Common.

No Connect.

Digital Supply Voltage (1.7 V to 3.± V).

DVDD

Rev. 0 | Page 12 of 52

AD9704/AD9705/AD9706/AD9707

AD9705

DB3

DB2

DVDD

1

2

3

4

5

6

7

24 FS ADJ

23 REFIO

22 ACOM

21 IOUTA

20 IOUTB

19 OTCM

18 AVDD

PIN 1

INDICATOR

AD9705

DB1

DB0 (LSB)

NC

TOP VIEW

(Not to Scale)

NC

8

17 PIN/SPI/RESET

NC = NO CONNECT

Figure 5. AD9705 Pin Configuration

Table 11. AD9705 Pin Function Descriptions

Pin No.

Mnemonic

Description

27

DB9 (MSB)

Most Significant Data Bit (MSB).

Data Bit 8 to Data Bit 1.

28 to 32, DB8 to DB1

1, 2, 4

5

DB0 (LSB)

Least Significant Data Bit (LSB).

25

SLEEP/CSB

In pin mode, active high powers down chip.

In SPI mode, this pin is the serial port chip select (active low).

24

23

FS ADJ

REFIO

Full-Scale Current Output Adjust.

Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference

output when internal reference activated. Requires a 0.1 μF capacitor to ACOM when internal reference activated.

22

21

20

19

18

17

ACOM

IOUTA

IOUTB

OTCM

AVDD

PIN/SPI/RESET

Analog Common.

DAC Current Output. Full-scale current is sourced when all data bits are 1s.

Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.

Adjustable Output Common Mode. Refer to the Theory of Operation section for details.

Analog Supply Voltage (1.7 V to 3.± V).

Selects SPI mode or pin mode operation. Active high for pin mode operation. Active low for SPI mode

operation. Pulse high to reset SPI registers to default values.

1±

15

MODE/SDIO

In pin mode, this selects the input data format. Connect to DCOM for straight binary, DVDD for twos complement.

In SPI mode, this pin acts as SPI data input/output.

In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver

(drive CLK+ and float CLK–). Connect to CLKVDD for differential receiver.

In SPI mode, this pin is the serial data clock input.

CMODE/SCLK

14

13

12

11

10, 2±

± to 9

3

CLKCOM

CLK−

CLK+

CLKVDD

DCOM

NC

Clock Common.

Differential Clock Input.

Clock Supply Voltage (1.7 V to 3.± V).

Digital Common.

No Connect.

Digital Supply Voltage (1.7 V to 3.± V).

DVDD

Rev. 0 | Page 13 of 52

AD9704/AD9705/AD9706/AD9707

AD9704

DB1

1

2

3

4

5

6

7

24 FS ADJ

23 REFIO

22 ACOM

21 IOUTA

20 IOUTB

19 OTCM

18 AVDD

PIN 1

INDICATOR

DB0 (LSB)

DVDD

NC

AD9704

NC

TOP VIEW

(Not to Scale)

NC

8

17 PIN/SPI/RESET

NC = NO CONNECT

Figure 6. AD9704 Pin Configuration

Table 12. AD9704 Pin Function Descriptions

Pin No.

Mnemonic

Description

27

DB7 (MSB)

Most Significant Data Bit (MSB).

Data Bit ± to Data Bit 1.

28 to 32, DB± to DB1

1

2

DB0 (LSB)

Least Significant Data Bit (LSB).

25

SLEEP/CSB

In pin mode, active high powers down chip.

In SPI mode, this pin is the serial port chip select (active low).

24

23

FS ADJ

REFIO

Full-Scale Current Output Adjust.

Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.0 V reference

output when internal reference activated. Requires a 0.1 μF capacitor to ACOM when internal reference activated.

22

21

20

19

18

17

ACOM

IOUTA

IOUTB

OTCM

AVDD

PIN/SPI/RESET

Analog Common.

DAC Current Output. Full-scale current is sourced when all data bits are 1s.

Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.

Adjustable Output Common Mode. Refer to the Theory of Operation section for details.

Analog Supply Voltage (1.7 V to 3.± V).

Selects SPI mode or pin mode operation. Active high for pin mode operation. Active low for SPI mode

operation. Pulse high to reset SPI registers to default values.

1±

15

MODE/SDIO

In pin mode, this selects the input data format. Connect to DCOM for straight binary, DVDD for twos complement.

In SPI mode, this pin acts as SPI data input/output.

In pin mode, this pin selects the clock input type. Connect to CLKCOM for single-ended clock receiver

(drive CLK+ and float CLK−). Connect to CLKVDD for differential receiver.

In SPI mode, this pin is the serial data clock input.

CMODE/SCLK

14

13

12

11

10, 2±

4 to 9

3

CLKCOM

CLK−

CLK+

CLKVDD

DCOM

NC

Clock Common.

Differential Clock Input.

Clock Supply Voltage (1.7 V to 3.± V).

Digital Common.

No Connect.

Digital Supply Voltage (1.7 V to 3.± V).

DVDD

Rev. 0 | Page 14 of 52

AD9704/AD9705/AD9706/AD9707

TYPICAL PERFORMANCE CHARACTERISTICS

AD9707

VDD = 3.3 V, I_OUTFS= 2 mA, unless otherwise noted.

95

10MSPS

90

85

80

75

70

65

60

55

50

45

65MSPS

85

80

175MSPS

75

70

65

125MSPS

60

55

50

45

1

10

100

0

5

10 15 20 25 30 35 40 45 50 55 60 65

f_OUT(MHz)

Figure 7. SFDR vs. f_OUT

Figure 10. SFDR vs. f_OUT@ 125 MSPS

95

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

0

1

2

3

4

5

10

20

30

40

50

60

70

80

f_OUT(MHz)

Figure 8. SFDR vs. f_OUT@ 10 MSPS

Figure 11. SFDR vs. f_OUT@ 175 MSPS

95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

45

5mA

2mA

1mA

0

5

10

15

20

25

30

35

10

20

30

40

50

60

70

80

f_OUT(MHz)

Figure 9. SFDR vs. f_OUT@ 65 MSPS

Figure 12. SFDR vs. f_OUTand I_OUTFS@ 175 MSPS

Rev. 0 | Page 15 of 52

AD9704/AD9705/AD9706/AD9707

95

90

85

80

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

OTCM = 0

75

1mA

70

OTCM = 0.3V

2mA

5mA

65

60

55

50

45

OTCM = 1.2V

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

f_OUT(MHz)

Figure 13. SFDR vs. f_OUTand OTCM @ 175 MSPS

Figure 16. NSD vs. f_OUTand I_OUTFS@ 175 MSPS

95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

45

65MSPS

75MSPS

125MSPS

175MSPS

125MSPS

–10

–8

–6

A

–4

(dBFS)

–2

0

10

20

30

40

50

60

70

80

LOWER f_OUT(MHz)

OUT

Figure 14. Single-Tone SFDR vs. A_OUT@ f_OUT= f_CLOCK/5

Figure 17. Dual-Tone IMD vs. f_OUT@ 0 dBFS

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

95

90

85

80

75

70

65

60

55

50

45

25°C

125MSPS

85°C

65MSPS

175MSPS

–40°C

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

f_OUT(MHz)

LOWER f_OUT(MHz)

Figure 15. NSD vs. f_OUTand f_CLOCK@ 0 dBFS

Figure 18. Dual-Tone IMD vs. f_OUTand Temperature @ 0 dBFS

Rev. 0 | Page 1± of 52

AD9704/AD9705/AD9706/AD9707

0.6

1.0

0.5

0.4

0.3

0.2

0.1

0

–0.5

–1.0

–1.5

–0.1

–0.2

0

5000

10000

15000

0

5000

10000

16384

CODE

Figure 19. Typical Uncalibrated INL

Figure 22. Typical Calibrated DNL

95

0.6

0.4

90

85

80

75

70

65

60

55

50

45

0.2

25°C

85°C

0

–40°C

–0.2

–0.4

–0.6

–0.8

0

10

20

30

40

50

60

70

80

0

5000

10000

16384

f_OUT(MHz)

CODE

Figure 20. Typical Uncalibrated DNL

Figure 23. SFDR vs. Temperature @ 175 MSPS

0.6

0.4

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

f_CLOCK= 78MSPS

f_OUT= 15.0MHz

SFDR = 79dBc

0.2

AMPLITUDE = 0dBFS

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

5000

10000

15000

1

6

11

16

21

26

31

36

CODE

FREQUENCY (MHz)

Figure 21. Typical Calibrated INL

Figure 24. Single-Tone SFDR

Rev. 0 | Page 17 of 52

AD9704/AD9705/AD9706/AD9707

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

f_CLOCK= 78MSPS

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

f_OUT3= 15.8MHz

f_OUT4= 16.2MHz

SFDR = 69dBc

–20

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

SFDR = 74dBc

AMPLITUDE = 0dBFS

–30

–40

AMPLITUDE = 0dBFS

–50

–60

–70

–80

–90

–100

–110

1

6

11

16

21

26

31

36

1

6

11

16

21

26

31

36

FREQUENCY (MHz)

Figure 25. Dual-Tone SFDR

Figure 26. Four-Tone SFDR

Rev. 0 | Page 18 of 52

AD9704/AD9705/AD9706/AD9707

VDD = 1.8 V, I_OUTFS= 1 mA, unless otherwise noted.

95

10MSPS

90

85

80

75

70

65

60

55

50

45

65MSPS

85

80

80MSPS

75

70

65

60

55

50

45

1

10

100

0

5

10

15

20

25

30

35

40

35

40

f_OUT(MHz)

Figure 27. SFDR vs. f_OUT

Figure 30. SFDR vs. f_OUT@ 80 MSPS

95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

45

1mA

2mA

5

10

15

20

25

30

0

1

2

3

4

5

f_OUT(MHz)

Figure 31. SFDR vs. f_OUTand I_OUTFS@ 65 MSPS

Figure 28. SFDR vs. f_OUT@ 10 MSPS

95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

45

1mA

2mA

5

10

15

20

25

30

35

0

5

10

15

20

25

30

35

f_OUT(MHz)

Figure 32. SFDR vs. f_OUTand I_OUTFS@ 80 MSPS

Figure 29. SFDR vs. f_OUT@ 65 MSPS

Rev. 0 | Page 19 of 52

AD9704/AD9705/AD9706/AD9707

95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

80MSPS

65MSPS

75

70

25MSPS

65

65MSPS

60

55

50

45

80MSPS

35

0

5

10

15

20

25

30

40

–10

–8

–6

A

–4

(dBFS)

–2

0

LOWER f_OUT(MHz)

OUT

Figure 33. Single-Tone SFDR vs. A_OUT@ f_OUT= f_CLOCK/5

Figure 36. Dual-Tone IMD vs. f_OUT@ I_OUTFS= 2 mA and 0 dBFS

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

95

90

85

80

–40°C

80MSPS, 1mA

65MSPS, 1mA

75

85°C

70

65

25°C

60

55

50

45

80MSPS, 2mA

65MSPS, 2mA

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

LOWER f_OUT(MHz)

f_OUT(dBFS)

Figure 34. NSD vs. f_OUT, f_CLOCK, and I_OUTFS@ 0 dBFS

Figure 37. Dual-Tone IMD vs. f_OUTand Temperature @ 80 MSPS,

I_OUTFS= 1 mA and 0 dBFS

95

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

25°C

–40°C

65MSPS

25MSPS

80MSPS

80°C

35

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

40

LOWER f_OUT(MHz)

Figure 35. Dual-Tone IMD vs. f_OUT@ I_OUTFS= 1 mA and 0 dBFS

Figure 38. Dual-Tone IMD vs. f_OUTand Temperature @ 80 MSPS,

_OUTFS= 2 mA and 0 dBFS

I

Rev. 0 | Page 20 of 52

AD9704/AD9705/AD9706/AD9707

1.0

0.5

–10

f_CLOCK= 78MSPS

f_OUT= 15.0MHz

SFDR = 80dBc

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

AMPLITUDE = 0dBFS

0.0

–0.5

–1.0

–1.5

1

6

11

16

21

26

31

36

0

5000

10000

16384

FREQUENCY (MHz)

CODE

Figure 39. Typical Uncalibrated INL

Figure 42. Single-Tone SFDR

0.6

0.4

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

f_CLOCK= 78MSPS

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

SFDR = 77dBc

AMPLITUDE = 0dBFS

0.2

0

–0.2

–0.4

–0.6

–0.8

1

6

11

16

21

26

31

36

0

5000

10000

16384

FREQUENCY (MHz)

CODE

Figure 40. Typical Uncalibrated DNL

Figure 43. Dual-Tone SFDR

95

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

f_CLOCK= 78MSPS

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

f_OUT3= 15.8MHz

f_OUT4= 16.2MHz

SFDR = 77dBc

90

85

80

75

70

65

60

55

50

45

–40°C

AMPLITUDE = 0dBFS

85°C

25°C

0

5

10

15

20

25

30

35

40

1

6

11

16

21

26

31

36

f_OUT(MHz)

FREQUENCY (MHz)

Figure 41. SFDR vs. Temperature @ 80 MSPS

Figure 44. Four-Tone SFDR

Rev. 0 | Page 21 of 52

AD9704/AD9705/AD9706/AD9707

AD9704, AD9705, AND AD9706

VDD = 3.3 V, I_OUTFS= 2 mA, unless otherwise noted.

–115

0.01

AD9704

–120

–125

–130

AD9705

–135

0

–140

–145

AD9706

–150

AD9707

–155

–160

–0.01

0.01

0

200

400

600

800

1024

0

10

20

30

40

50

60

70

80

CODE

f_OUT(MHz)

Figure 45. AD9704, AD9705, AD9706 NSD vs. f_OUT@ 0 dBFS

Figure 48. AD9705 Typical Uncalibrated INL

0.03

0.02

0.01

0

–0.01

–0.02

–0.01

0

200

400

600

800

1024

0

50

100

150

200

256

CODE

Figure 46. AD9704 Typical Uncalibrated INL

Figure 49. AD9705 Typical Uncalibrated DNL

0.01

0

0.3

0.2

0.1

0

–0.01

–0.02

–0.03

–0.1

–0.2

–0.3

–0.4

–0.5

0

50

100

150

200

256

0

1000

2000

3000

4096

CODE

Figure 47. AD9704 Typical Uncalibrated DNL

Figure 50. AD9706 Typical Uncalibrated INL

Rev. 0 | Page 22 of 52

AD9704/AD9705/AD9706/AD9707

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

0.01

0

f_CLOCK= 78MSPS

f_OUT= 15.0MHz

SFDR = 75dBc

AMPLITUDE = 0dBFS

–0.01

–0.02

–0.03

–0.04

1

6

11

16

21

26

31

36

0

1000

2000

3000

4096

FREQUENCY (MHz)

CODE

Figure 54. AD9705 Single-Tone SFDR

Figure 51. AD9706 Typical Uncalibrated DNL

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

f_CLOCK= 78MSPS

f_OUT= 15.0MHz

f_CLOCK= 78MSPS

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

SFDR = 73dBc

–20

–30

SFDR = 67dBc

AMPLITUDE = 0dBFS

–40

–50

–60

–70

–80

–90

–100

–110

1

6

11

16

21

26

31

36

1

6

11

16

21

26

31

36

FREQUENCY (MHz)

Figure 52. AD9704 Single-Tone SFDR

Figure 55. AD9705 Dual-Tone SFDR

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

f_CLOCK= 78MSPS

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

SFDR = 67dBc

f_CLOCK= 78MSPS

f_OUT1= 15.0MHz

SFDR = 77dBc

AMPLITUDE = 0dBFS

1

6

11

16

21

26

31

36

1

6

11

16

21

26

31

36

FREQUENCY (MHz)

Figure 53. AD9704 Dual-Tone SFDR

Figure 56. AD9706 Single-Tone SFDR

Rev. 0 | Page 23 of 52

AD9704/AD9705/AD9706/AD9707

–10

f_CLOCK= 78MSPS

–20

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

SFDR = 77dBc

–30

AMPLITUDE = 0dBFS

–40

–50

–60

–70

–80

–90

–100

–110

1

6

11

16

21

26

31

36

FREQUENCY (MHz)

Figure 57. AD9706 Dual-Tone SFDR

Rev. 0 | Page 24 of 52

AD9704/AD9705/AD9706/AD9707

VDD = 1.8 V, I_OUTFS= 1 mA, unless otherwise noted.

–115

0.08

0.06

0.04

0.02

0

–120

–125

–130

–135

–140

–145

–150

–155

–160

AD9704

AD9705

AD9706

–0.02

–0.04

–0.06

–0.08

AD9707

0

5

10

15

20

f_OUT(MHz)

25

30

35

40

0

200

400

600

800

1024

4096

CODE

Figure 58. AD9704, AD9705, AD9706 NSD vs. f_OUT@ 0 dBFS

Figure 61. AD9705 Typical Uncalibrated INL

0.04

0.02

0

0.03

0.02

0.01

0

–0.02

–0.04

–0.06

–0.08

–0.10

–0.12

–0.01

–0.02

200

400

600

800

0

50

100

150

200

256

CODE

Figure 59. AD9704 Typical Uncalibrated INL

Figure 62. AD9705 Typical Uncalibrated DNL

0.3

0.2

0.01

0

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.01

–0.02

–0.03

1000

2000

3000

0

50

100

150

200

256

CODE

Figure 63. AD9706 Typical Uncalibrated INL

Figure 60. AD9704 Typical Uncalibrated DNL

Rev. 0 | Page 25 of 52

AD9704/AD9705/AD9706/AD9707

0.1

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

f_CLOCK= 78MSPS

f_OUT= 15.0MHz

SFDR = 73dBc

0

AMPLITUDE = 0dBFS

–0.1

–0.2

–0.3

–0.4

0

1000

2000

3000

4096

1

6

11

16

21

26

31

36

CODE

FREQUENCY (MHz)

Figure 64. AD9706 Typical Uncalibrated DNL

Figure 67. AD9705 Single-Tone SFDR

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

f_CLOCK= 78MSPS

f_OUT= 15.0MHz

f_CLOCK= 78MSPS

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

SFDR = 71dBc

–20

–30

SFDR = 67dBc

AMPLITUDE = 0dBFS

–40

–50

–60

–70

–80

–90

–100

–110

1

6

11

16

21

26

31

36

6

11

16

21

26

31

36

FREQUENCY (MHz)

Figure 65. AD9704 Single-Tone SFDR

Figure 68. AD9705 Dual-Tone SFDR

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

f_CLOCK= 78MSPS

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

SFDR = 67dBc

f_CLOCK= 78MSPS

f_OUT= 15.0MHz

SFDR = 73dBc

AMPLITUDE = 0dBFS

1

6

11

16

21

26

31

36

6

11

16

21

26

31

36

FREQUENCY (MHz)

Figure 66. AD9704 Dual-Tone SFDR

Figure 69. AD9706 Single-Tone SFDR

Rev. 0 | Page 2± of 52

AD9704/AD9705/AD9706/AD9707

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

f_CLOCK= 78MSPS

f_OUT1= 15.0MHz

f_OUT2= 15.4MHz

SFDR = 73dBc

AMPLITUDE = 0dBFS

1

6

11

16

21

26

31

36

FREQUENCY (MHz)

Figure 70. AD9706 Dual-Tone SFDR

Rev. 0 | Page 27 of 52

AD9704/AD9705/AD9706/AD9707

TERMINOLOGY

Linearity Error (Also Called Integral Nonlinearity or INL)

INL is defined as the maximum deviation of the actual analog

output from the ideal output, determined by a straight line

drawn from zero to full scale.

Power Supply Rejection

Power supply rejection is the maximum change in the full-scale

output as the supplies are varied from nominal to minimum

and maximum specified voltages.

Differential Nonlinearity (DNL)

Settling Time

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input code.

Settling time is the time required for the output to reach and

remain within a specified error band about its final value,

measured from the start of the output transition.

Monotonicity

A digital-to-analog converter is monotonic if the output either

increases or remains constant as the digital input increases.

Glitch Impulse

Asymmetrical switching times in a DAC give rise to undesired

output transients that are quantified by a glitch impulse. It is

specified as the net area of the glitch in picovolt-seconds (pV-s).

Offset Error

The deviation of the output current from the ideal of zero is

called the offset error. For IOUTA, 0 mA output is expected

when the inputs are all 0s. For IOUTB, 0 mA output is expected

when all inputs are set to 1.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels (dB), between the rms

amplitude of the output signal and the peak spurious signal over

the specified bandwidth.

Gain Error

Gain error is the difference between the actual and ideal output

span. The actual span is determined by the output when all inputs

are set to 1, minus the output when all inputs are set to 0. The

ideal gain is calculated using the measured VREF. Therefore,

the gain error does not include effects of the reference.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured input signal.

It is expressed as a percentage or in decibels (dB).

Multitone Power Ratio

Output Compliance Range

Multitone power ratio is the spurious-free dynamic range

containing multiple carrier tones of equal amplitude. It is

measured as the difference between the rms amplitude of

a carrier tone to the peak spurious signal in the region of

a removed tone.

Output compliance range is the range of allowable voltage at the

output of a current output DAC. Operation beyond the maximum

compliance limits can cause either output stage saturation or

breakdown, resulting in nonlinear performance.

Temperature Drift

Noise Spectral Density (NSD)

Temperature drift is specified as the maximum change from the

ambient (25°C) value to the value at either T_MINor T_MAX. For offset

and gain drift, the drift is reported in ppm of full-scale range (FSR)

per °C. For reference drift, the drift is reported in ppm per °C.

Noise spectral density is the average noise power normalized to

a 1 Hz bandwidth, with the DAC converting and producing an

output tone.

1.7V TO 3.6V

AVDD

ACOM

1.0V REF

0.1µF

AD9707

REFIO

CURRENT

SOURCE

ARRAY

MINI-CIRCUITS

OTCM

ADT9-1T

FS ADJ

R

16kΩ

SET

1.7V TO 3.6V

SPECTRUM ANALYZER

AGILENT OR

RHODE AND SCHWARZ

ADTL1-12

IOUTA

IOUTB

CLKVDD

CLKCOM

0Ω

SEGMENTED

SWITCHES

LSB

SWITCHES

10kΩ

ADT1-1WT

CLK+

CLK–

1.7V

TO

9:1

453Ω

50Ω

LATCHES

R

OTCM

0Ω

SPI

DVDD

DCOM

3.6V

10kΩ

0.1µF

SLEEP/CSB

DIGITAL

DATA

CLOCK

OUTPUT

DIGITAL DATA SOURCE DPG,

SONY/TEK OR ROHDE AND SCHWARZ

LOW JITTER RF SOURCE

AGILENT OR ROHDE AND SCHWARZ

Figure 71. Basic AC Characterization Test Setup

Rev. 0 | Page 28 of 52

AD9704/AD9705/AD9706/AD9707

THEORY OF OPERATION

Figure 72 shows a simplified block diagram of one of the

AD970x parts, the AD9707 The AD970x consists of a DAC,

digital control logic, and full-scale output current control. The

DAC contains a PMOS current source array capable of providing

a nominal full-scale current (I_OUTFS) of 2 mA and a maximum of

5 mA. The array is divided into 31 equal currents that make up the

five most significant bits (MSBs). The next four bits, or middle

bits, consist of 15 equal current sources whose value is 1/16 of an

MSB current source. The remaining LSBs are binary weighted frac-

tions of the current sources of the middle bits. Implementing the

middle and lower bits with current sources, instead of an R-2R

ladder, enhances the AD970x dynamic performance for multitone

or low amplitude signals and helps maintain the high output

impedance of the DAC (that is, >200 Mꢀ).

The external resistor, in combination with both the reference

control amplifier and voltage reference, V_REFIO, sets the reference

current, I_REF, which is replicated to the segmented current sources

with the proper scaling factor. The full-scale current, I_OUTFS, is

32 × I_REF

.

The AD970x provides the option of setting the output common

mode to a value other than ACOM via the output common mode

(OTCM) pin. This facilitates interfacing the output of the AD970x

directly to components that require common-mode levels greater

than 0 V.

SERIAL PERIPHERAL INTERFACE

The AD970x serial port is a flexible, synchronous serial commu-

nications port allowing easy interface to many industry-standard

microcontrollers and microprocessors. The serial I/O is compatible

with most synchronous transfer formats, including the Motorola

SPI and Intel® SSR protocols. The interface allows read/write

access to all registers that configure the AD970x. Single or multiple

byte transfers are supported, as well as MSB first or LSB first

transfer formats. The serial interface port of the AD970x is

configured as a single pin I/O.

All of these current sources are switched to one of the two

output nodes (IOUTA or IOUTB) via PMOS differential current

switches. The switches are based on the architecture pioneered

in the AD9764 family, with further refinements made to reduce

distortion contributed by the switching transient. This switch

architecture also reduces various timing errors and provides

matching complementary drive signals to the inputs of the

differential current switches.

General Operation of the Serial Interface

The analog and digital sections of the AD970x have separate power

supply inputs (AVDD and DVDD) that can operate independently

over a 1.7 V to 3.6 V range. The digital section, which is capable

of operating at a rate of up to 175 MSPS, consists of edge-triggered

latches and segment decoding logic circuitry. The analog section

includes the PMOS current sources, the associated differential

switches, a 1.0 V band gap voltage reference, and a reference

control amplifier.

There are two phases to a communication cycle with the AD970x.

Phase 1 is the instruction cycle, which is the writing of an instruc-

tion byte into the AD970x, coincident with the first eight SCLK

rising edges. The instruction byte provides the AD970x serial port

controller with information regarding the data transfer cycle, which

is Phase 2 of the communication cycle. The Phase 1 instruction

byte defines whether the upcoming data transfer is read or write,

the number of bytes in the data transfer, and the starting register

address for the first byte of the data transfer. The first eight

SCLK rising edges of each communication cycle are used to write

the instruction byte into the AD970x.

The DAC full-scale output current is regulated by the reference

control amplifier and can be set from 1 mA to 5 mA via an external

resistor, R_SET, connected to the full-scale adjust (FS ADJ) pin.

1.7V TO 3.6V

AVDD

ACOM

1.0V REF

REFIO

0.1µF

AD9707

OTCM

CURRENT

SOURCE

ARRAY

FS ADJ

1.7V

TO

CLKVDD

CLKCOM

IOUTA

R

SET

SEGMENTED

SWITCHES

LSB

SWITCHES

3.6V

IOUTB

SPI

CLK+

CLK–

PIN/SPI/RESET

MODE/SDIO

LATCHES

1.7V TO

3.6V

CMODE/SCLK

DVDD

DCOM

SLEEP/CSB

DIGITAL INPUTS (DB13 TO DB0)

Figure 72. Simplified Block Diagram

Rev. 0 | Page 29 of 52

AD9704/AD9705/AD9706/AD9707

A logic high on Pin 17 (PIN/SPI/RESET), followed by a logic

low, resets the SPI port timing to the initial state of the

instruction cycle. This is true regardless of the present state of

the internal registers or the other signal levels present at the

inputs to the SPI port. If the SPI port is in the midst of an

instruction cycle or a data transfer cycle, none of the present

data is written.

CSB—Chip Select. Active low input starts and gates a communica-

tion cycle. It allows more than one device to be used on the same

serial communications lines. The SDIO pin goes to a high imped-

ance state when this input is high. Chip select should stay low

during the entire communication cycle.

SDIO—Serial Data I/O. This pin is used as a bidirectional data

line to transmit and receive data.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD970x

and the system controller. Phase 2 of the communication cycle

is a transfer of one, two, three, or four data bytes, as determined

by the instruction byte. Using one multibyte transfer is the

preferred method. Single byte data transfers are useful to reduce

CPU overhead when register access requires one byte only.

Registers change immediately upon writing to the last bit of

each transfer byte.

MSB/LSB Transfers

The AD970x serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by the DATADIR bit (Register 0x00,

Bit 6). The default is MSB first (DATADIR = 0).

When DATADIR = 0 (MSB first), the instruction and data bytes

must be written from most significant bit to least significant bit.

Multibyte data transfers in MSB first format start with an

instruction byte that includes the register address of the most

significant data byte. Subsequent data bytes should follow in

order from high address to low address. In MSB first mode, the

serial port internal byte address generator decrements for each

data byte of the multibyte communication cycle.

Instruction Byte

The instruction byte contains the information shown in the

following bit map:

MSB

7

LSB

0

±

5

4

3

2

1

When DATADIR = 1 (LSB first), the instruction and data bytes

must be written from least significant bit to most significant bit.

Multibyte data transfers in LSB first format start with an instruction

byte that includes the register address of the least significant data

byte followed by multiple data bytes. The serial port internal byte

address generator increments for each byte of the multibyte

communication cycle.

R/W

N1

N0

A4

A3

A2

A1

A0

W

R/ , Bit 7 of the instruction byte, determines whether a read or

a write data transfer occurs after the instruction byte write. Logic 1

indicates a read operation. Logic 0 indicates a write operation.

N1 and N0, Bit 6 and Bit 5 of the instruction byte, determine the

number of bytes to be transferred during the data transfer cycle.

The bit decodes are shown in Table 13.

The AD970x serial port controller data address decrements

from the data address written toward 0x00 for multibyte I/O

operations if the MSB first mode is active. The serial port

controller address increments from the data address written

toward 0x1F for multibyte I/O operations if the LSB first mode

is active.

A4, A3, A2, A1, and A0, which are Bit 4, Bit 3, Bit 2, Bit 1, and

Bit 0 of the instruction byte, respectively, determine which register

is accessed during the data transfer portion of the communication

cycle. For multibyte transfers, this address is the starting byte

address. The remaining register addresses are generated by the

AD970x, based on the DATADIR bit (Register 0x00, Bit 6).

Notes on Serial Port Operation

Table 13. Byte Transfer Count

The AD970x serial port configuration is controlled by

Register 0x00, Bit 7. It is important to note that the configuration

changes immediately upon writing to the last bit of the register.

For multibyte transfers, writing to this register can occur during

the middle of communication cycle. Care must be taken to

compensate for this new configuration for the remaining bytes

of the current communication cycle.

N1

N0

Description

0

1

0

1

0

1

Transfer 1 byte

Transfer 2 bytes

Transfer 3 bytes

Transfer 4 bytes

Serial Interface Port Pin Descriptions

SCLK—Serial Clock. The serial clock pin is used to synchronize

data to and from the AD970x and to run the internal state

machines. The SCLK maximum frequency is 20 MHz. All data

input to the AD970x is registered on the rising edge of SCLK.

All data is driven out of the AD970x on the falling edge of SCLK.

The same considerations apply to setting the software reset,

SWRST (Register 0x00, Bit 5). All registers are set to their default

values except Register 0x00, which remains unchanged.

Use of single byte transfers is recommended when changing

serial port configurations or initiating a software reset to

prevent unexpected device behavior.

Rev. 0 | Page 30 of 52

AD9704/AD9705/AD9706/AD9707

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SDO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

A0 A1 A2 A3 A4 N0 N1 R/W

D0

D1 D2

0

D4 D5 D6 D7

N N N

0

N

D1 D2

D4 D5 D6 D7

N N N

0

R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5

D3 D2 D1 D0

0 0 0 0

N

D0

Figure 73. Serial Register Interface Timing, MSB First Write

Figure 76. Serial Register Interface Timing, LSB First Read

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

t_DS

t_SCLK

CSB

SCLK

SDIO

SDO

CSB

t_PWH

t_PWL

R/W N1 N0 A4 A3 A2 A1 A0

D7

D6 D5

D3 D2 D1 D0

0 0 0

N

0

SCLK

t_DS

t_DH

INSTRUCTION BIT 7

D6 D5

D3 D2 D1 D0

0 0 0

N

INSTRUCTION BIT 6

SDIO

D7

Figure 77. Timing Diagram for SPI Register Write

Figure 74. Serial Register Interface Timing, MSB First Read

CSB

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CSB

SCLK

SDIO

SCLK

t

DNV

t

DV

I1

I0

D7

D6

D5

SDIO

A0 A1 A2 A3 A4 N0 N1 R/W D0₀D1₀D2₀

D4_ND5_ND6_ND7_N

Figure 78. Timing Diagram for SPI Register Read

Figure 75. Serial Register Interface Timing, LSB First Write

SPI REGISTER MAP

Table 14.

Name

Addr Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPI CTL

DATA

0x00

0x02

0x0D

0x0E

SDIODIR

DATADIR SWRST

LNGINS

DCLKPOL

PDN

SLEEP

CLKOFF

EXREF

DATAFMT

DESKEW

VER[3]

CLKDIFF

VER[2]

CALCLK

VER[0]

VERSION

CALMEM

VER[1]

CALMEM[1]

CALMEM[0]

DIVSEL[2]

SMEMRD

DIVSEL[1]

DIVSEL[0]

UNCAL

MEMRDWR 0x0F

MEMADDR 0x10

CALSTAT

CALEN

SMEMWR

MEMADDR[5] MEMADDR[4] MEMADDR[3] MEMADDR[2] MEMADDR[1] MEMADDR[0]

MEMDATA[5] MEMDATA[4] MEMDATA[3] MEMDATA[2] MEMDATA[1] MEMDATA[0]

CALDACFS

MEMDATA

TRIM

0x11

0x14

Rev. 0 | Page 31 of 52

AD9704/AD9705/AD9706/AD9707

SPI REGISTER DESCRIPTIONS

Table 15. SPI CTL—Register 0x00

Bit Name

Bit

Direction (I/O)

Default Description

SDIODIR

7

I

1

0: SDIO pin configured for input only during data transfer (4-wire interface)

1: SDIO pin configured for input or output during data transfer (3-wire interface)

0: Serial data uses MSB first format

DATADIR

±

I

0

1: Serial data uses LSB first format

SWRST

5

4

I

0

1: Initiate a software reset; this bit is set to 0 upon reset completion

0: Use 1 byte preamble (5 address bits)

1: Use 2 byte preamble (13 address bits)

1: All analog and digital circuitry off, except serial interface

1: DAC output current off

LNGINS

PDN

3

2

1

0

I

0

SLEEP

CLKOFF

EXREF

1: Disables internal master clock.

0: Internal bandgap reference

1: External reference

Table 16. DATA—Register 0x02

Bit Name

Bit

Direction (I/O) Default Description

DATAFMT

7

I

0

0: Unsigned binary input data format

1: Twos complement input data format

0: Data latched on DATACLK rising edge always

1: Data latched on DATACLK falling edge (only active in DESKEW mode)

0: DESKEW mode disabled

DCLKPOL

DESKEW

4

3

1: DESKEW mode enabled (adds a register in digital data path to remove

skew in received data; one clock cycle of latency is introduced)

0: Single-ended clock input

CLKDIFF

CALCLK

2

0

I

0

1: Differential clock input

0: Calibration clock disabled

1: Calibration clock enabled

Table 17. VERSION—Register 0x0D

Bit Name

Bit

Direction (I/O) Default

Description

VER[3:0]

[3:0]

O

Hardware version identifier

Table 18. CALMEM—Register 0x0E

Bit Name Bit Direction (I/O) Default

CALMEM[1:0] [5:4]

Description

O

00

Calibration memory

00: Uncalibrated

01: Self-calibration

10: Not Used

11: User input

DIVSEL[2:0]

[2:0]

I

000

Calibration clock divide ratio from DAC clock rate

000: /25±

001: /128

:

110: /4

111: /2

Rev. 0 | Page 32 of 52

AD9704/AD9705/AD9706/AD9707

Table 19. MEMRDWR—Register 0x0F

Bit Name

CALSTAT

CALEN

Bit

7

Direction (I/O)

Default

Description

O

I

0

1: Calibration cycle complete

±

1: Initiate device self-calibration

SMEMWR

SMEMRD

UNCAL

3

I

1: Write to static memory (calibration coefficients)

1: Read from static memory (calibration coefficients)

1: Reset calibration coefficients to default (uncalibrated)

2

I

0

I

Table 20. MEMADDR—Register 0x10

Bit Name

Bit

Direction (I/O)

Default

Description

MEMADDR[5:0]

[5:0]

I/O

000000

Address of static memory to be accessed

Table 21. MEMDATA—Register 0x11

Bit Name

Bit

Direction (I/O)

Default

Description

MEMDATA[5:0]

[5:0]

I/O

111111

Data for static memory access

Table 22. TRIM—Register 0x14

Bit Name

Bit

Direction (I/O)

Default

Description

CALDACFS

4

I

0

0: Calibration DAC full-scale uses AVDD

1: Calibration DAC full-scale uses AVDD/2

Rev. 0 | Page 33 of 52

AD9704/AD9705/AD9706/AD9707

The control amplifier allows a 5:1 adjustment span of I_OUTFS

from 1 mA to 5 mA by setting I_REFbetween 31.25 μA and

156.25 μA (R_SETbetween 6.4 kꢀ and 32 kꢀ). The wide adjustment

span of I_OUTFSprovides several benefits. The first relates directly

to the power dissipation of the AD970x, which is proportional

to I_OUTFS(see the Power Dissipation section). The second benefit

relates to the ability to adjust the output over a 14 dB range, which

is useful for controlling the transmitted power.

REFERENCE OPERATION

The AD970x contains an internal 1.0 V band gap reference.

The internal reference can be disabled by writing a Logic 1 to

Register 0x00, Bit 0 (EXREF) in the SPI.

To use the internal reference, decouple the REFIO pin to ACOM

with a 0.1 μF capacitor, enable the internal reference, and write

a Logic 0 to Register 0x00, Bit 0 in the SPI. (Note that this is the

default configuration.) The internal reference voltage is present

at REFIO. If the voltage at REFIO is to be used anywhere else in

the circuit, an external buffer amplifier with an input bias

current of less than 100 nA should be used. An example of the

use of the internal reference is shown in Figure 79.

The small signal bandwidth of the reference control amplifier is

approximately 500 kHz. This allows the device to be used for

low frequency, small signal multiplying applications.

DAC TRANSFER FUNCTION

The AD970x provides complementary current outputs, IOUTA

and IOUTB. IOUTA provides a near full-scale current output,

I_OUTFS, when all bits are high (that is, DAC CODE = 2^N− 1,

where N = 8, 10, 12, or 14 for the AD9704, AD9705, AD9706,

and AD9707, respectively); while IOUTB, the complementary

output, provides no current. The current output appearing at

IOUTA and IOUTB is a function of both the input code and I_OUTFS

and can be expressed as

AD9704/AD9705/

AD9706/AD9707

DAC

V

BG

1.0V

REFIO

FSADJ

–

+

CURRENT

SCALING

x32

0.1µF

I_OUTFS

R

SET

I

REF

IOUTA = (DAC CODE/2^N) × I_OUTFS

(1)

(2)

AVSS

Figure 79. Internal Reference Configuration

IOUTB = ((2^N− 1) − DAC CODE)/2^N× I_OUTFS

REFIO serves as either an input or an output, depending on

whether the internal or an external reference is used. Table 23

summarizes the reference operation.

where DAC CODE = 0 to 2^N− 1 (that is, decimal representation).

I_OUTFSis a function of the reference current, I_REF, which is

nominally set by a reference voltage, V_REFIO, and an external

resistor, R_SET. It can be expressed as

Table 23. Reference Operation

Reference

Mode

REFIO Pin

Register Setting

I_OUTFS= 32 × I_REF

where

_REF= V_REFIO/R_SET

(3)

Internal

Connect 0.1 μF capacitor

Register 0x00, Bit 0 = 0

(default)

External

Apply external reference

Register 0x00, Bit 0 = 1

(for power saving)

I

(4)

An external reference can be used in applications requiring

tighter gain tolerances or lower temperature drift. Also, a variable

external voltage reference can be used to implement a method

for gain control of the DAC output. The external reference is

applied to the REFIO pin. Note that the 0.1 μF compensation

capacitor is not required. The internal reference can be directly

overdriven by the external reference, or the internal reference

can be powered down. The input impedance of REFIO is 10 kꢀ

when powered up and 1 Mꢀ when powered down.

The two current outputs typically drive a resistive load directly

or via a transformer. If dc coupling is required, IOUTA and

IOUTB should be connected to matching resistive loads, R_LOAD

that are tied to analog common, ACOM. The single-ended

,

voltage output appearing at the IOUTA and IOUTB nodes is

V

_IOUTA= IOUTA × R_LOAD

_IOUTB= IOUTB × R_LOAD

(5)

(6)

Note: To achieve the maximum output compliance of 1 V at the

nominal 2 mA output current, R_LOADmust be set to 500 Ω.

REFERENCE CONTROL AMPLIFIER

The AD970x contains a control amplifier that regulates the full-

scale output current, I_OUTFS. The control amplifier is configured

as a V-I converter, as shown in Figure 79. The output current,

I

_REF, is determined by the ratio of the V_REFIOand an external

resistor, R_SET, as stated in Equation 4. I_REFis mirrored to the

segmented current sources with the proper scale factor to set

I_OUTFS, as stated in Equation 3.

Rev. 0 | Page 34 of 52

AD9704/AD9705/AD9706/AD9707

Also note that the full-scale value of V_IOUTAand V_IOUTBshould

not exceed the specified output compliance range to maintain

specified distortion and linearity performance.

Performing a differential-to-single-ended conversion via a

transformer also provides the ability to deliver twice the

reconstructed signal power to the load (assuming no source

termination). Because the output currents of IOUTA and

IOUTB are complementary, they become additive when

processed differentially.

V

_DIFF= (IOUTA – IOUTB) × R_LOAD

(7)

Substituting the values of IOUTA, IOUTB, I_REF, and V_DIFFcan be

expressed as

When the AD970x is being used at its nominal operating point

of 2 mA output current, and 0.5 V output swing is desired,

V

_DIFF= {(2 × DAC CODE – (2^N− 1))/2^N} ×

(32 × V_REFIO/R_SET) × R_LOAD

(8)

R_LOADmust be set to 250 ꢀ. A properly selected transformer

allows the AD970x to provide the required power and voltage

levels to different loads.

Equation 7 and Equation 8 highlight some of the advantages of

operating the AD970x differentially. First, the differential operation

helps cancel common-mode error sources associated with IOUTA

and IOUTB, such as noise, distortion, and dc offsets. Second,

the differential code dependent current and subsequent voltage,

The output impedance of IOUTA and IOUTB is determined by

the equivalent parallel combination of the PMOS switches

associated with the current sources and is typically 200 MΩ in

parallel with 5 pF. It is also slightly dependent on the output

voltage (that is, V_IOUTAand V_IOUTB) due to the nature of a PMOS

device. As a result, maintaining IOUTA and/or IOUTB at a

virtual ground via an I-V op amp configuration results in the

optimum dc linearity. Note that the INL/DNL specifications for

the AD970x are measured with IOUTA maintained at a virtual

ground via an op amp.

V_DIFF, is twice the value of the single-ended voltage output

(that is, V_IOUTAor V_IOUTB), thus providing twice the signal power

to the load.

Note that the gain drift temperature performance for a single-

ended output (V_IOUTAand V_IOUTB) or differential output (V_DIFF

of the AD970x can be enhanced by selecting temperature

)

tracking resistors for R_LOADand R_SET, because of their ratiometric

relationship, as shown in Equation 8.

IOUTA and IOUTB also have a negative and positive voltage

compliance range that must be adhered to in order to achieve

optimum performance. The absolute maximum negative output

compliance range of −1 V is set by the breakdown limits of the

CMOS process. Operation beyond this maximum limit can result

in a breakdown of the output stage and affect the reliability of

the AD970x.

ANALOG OUTPUTS

The complementary current outputs in each DAC, IOUTA, and

IOUTB can be configured for single-ended or differential opera-

tion. IOUTA and IOUTB can be converted into complementary

single-ended voltage outputs, V_IOUTAand V_IOUTB, via a load

resistor, R_LOAD, as described in the DAC Transfer Function

section by Equation 5 through Equation 8. The differential

voltage, V_DIFF, existing between V_IOUTAand V_IOUTB, can also be

converted to a single-ended voltage via a transformer or a

differential amplifier configuration. The ac performance of the

AD970x is optimum and is specified using a differential

transformer-coupled output in which the voltage swing at

IOUTA and IOUTB is limited to 0.5 V.

The positive output compliance range is slightly dependent on

the full-scale output current, I_OUTFS. It degrades slightly from its

nominal 1.0 V for an I_OUTFS= 2 mA to 0.8 V for an I_OUTFS= 1 mA.

The optimum distortion performance for a single-ended or

differential output is achieved when the maximum full-scale

signal at IOUTA and IOUTB does not exceed 0.5 V.

ADJUSTABLE OUTPUT COMMON MODE

The AD970x provides the ability to set the output common

mode to a value other than ACOM via Pin 19 (OTCM). This

extends the compliance range of the outputs and facilitates

interfacing the output of the AD970x to components that

require common-mode levels other than 0 V. The OTCM pin

demands dynamically changing current and should be driven

by a low source impedance to prevent a common-mode signal

from appearing on the DAC outputs. For optimum performance,

set the voltage on OTCM equal to the center of the output

swing on IOUTA and IOUTB.

The distortion and noise performance of the AD970x can be

enhanced when it is configured for differential operation. The

common-mode error sources of both IOUTA and IOUTB can

be significantly reduced by the common-mode rejection of a

transformer or differential amplifier. These common-mode

error sources include even-order distortion products and noise.

The enhancement in distortion performance becomes more

significant as the frequency content of the reconstructed waveform

increases and/or its amplitude increases. This is due to the first

order cancellation of various dynamic common-mode distortion

mechanisms, digital feedthrough, and noise.

Rev. 0 | Page 35 of 52

AD9704/AD9705/AD9706/AD9707

Table 24. Clock Mode Selection

Note that setting OTCM to a voltage greater than ACOM allows

the peak of the output signal to be closer to the positive supply

rail. To prevent distortion in the output signal due to limited

available headroom, the common-mode level must be chosen

such that the following expression is satisfied:

SPI Disabled

CMODE Pin

SPI Enabled

Register 0x02, Bit 2

Clock Input Mode

Single-ended

Differential

CLKCOM

CLKVDD

0

1

In differential input mode, the clock input functions as a high

impedance differential pair. The common-mode level of the

CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and the

differential voltage can be as low as 0.5 V p-p. This mode can be

used to drive the clock with a differential sine wave because the

high gain bandwidth of the differential inputs converts the sine

wave into a single-ended square wave internally.

AVDD − V_OTCM> 1.8 V

(10)

DIGITAL INPUTS

The AD9707, AD9706, AD9705, and AD9704 have data inputs

of 14, 12, 10, and 8 bits, respectively; and each has a clock input.

The parallel data inputs can follow standard positive binary or

twos complement coding. IOUTA produces a full-scale output

current when all data bits are at Logic 1. IOUTB produces a

complementary output with the full-scale current split between

the two outputs as a function of the input code.

DAC TIMING

Input Clock and Data Timing Relationship

Dynamic performance in a DAC is dependent on the relation-

ship between the position of the clock edges and the time at

which the input data changes. The AD970x is rising-edge

triggered and so exhibits dynamic performance sensitivity when

the data transition is close to this edge. In general, the goal

when applying the AD970x is to make the data transition close

to the falling clock edge. This becomes more important as the

sample rate increases. Figure 81 shows the relationship of SFDR

to clock placement with different sample rates.

DVDD

DIGITAL

INPUT

Figure 80. Equivalent Digital Input

The digital interface is implemented using an edge-triggered

master/slave latch. The DAC output updates on the rising edge

of the clock and is designed to support a clock rate as high as

175 MSPS. The clock can be operated at any duty cycle that meets

the specified latch pulsewidth. The setup and hold times can

also be varied within the clock cycle, as long as the specified

minimum times are met, although the location of these transition

edges may affect digital feedthrough and distortion performance.

Best performance is typically achieved when the input data

transitions on the falling edge of a 50% duty cycle clock.

95

90

85

80MSPS

80

75

125MSPS

70

65

60

55

CLOCK INPUT

50

45

A configurable clock input allows the device to be operated in

a single-ended or a differential clock mode. The mode selection

can be controlled either by the CMODE pin, if the device is in pin

mode; or through SPI Register 0x02, Bit 2 (CLKDIFF), if the SPI

is enabled. Connecting CMODE to CLKCOM selects the single-

ended clock input. In this mode, the CLK+ input is driven with

rail-to-rail swings, and the CLK− input is left floating. If CMODE

is connected to CLKVDD, the differential receiver mode is selected.

In this mode, both inputs are high impedance. Table 24 gives a

summary of clock mode control. There is no significant perform-

ance difference between the clock input modes.

–4

–3

–2

–1

0

1

DATA EDGE WITH RESPECT TO RISING CLOCK EDGE (ns)

Figure 81. SFDR vs. Clock Placement

POWER DISSIPATION

The power dissipation, P_D, of the AD970x is dependent on

several factors that include

•

The power supply voltages (AVDD, CLKVDD, and

DVDD)

The full-scale current output, I_OUTFS

The update rate, f_CLOCK

•

The reconstructed digital input waveform

Rev. 0 | Page 3± of 52

AD9704/AD9705/AD9706/AD9707

10

Power dissipation is directly proportional to the analog supply

current, I_AVDD, and the digital supply current, I_DVDD. I_AVDDis equal

to a fixed current plus I_OUTFS, as shown in Figure 82. I_DVDDis

proportional to f_CLOCKand increases with increasing analog

output frequencies. Figure 84 shows I_DVDDas a function of full-

scale sine wave output ratios (f_OUT/f_CLOCK) for various update rates

with DVDD = 3.3 V. I_CLKVDDis directly proportional to f_CLOCK

and is higher for differential clock operation than for single-

ended operation, as shown in Figure 86. This difference in clock

current is due primarily to the differential clock receiver, which is

disabled in single-ended clock mode.

9

8

175MSPS

7

6

5

125MSPS

75MSPS

4

3

25MSPS

10MSPS

2

1

0

10

0.01

0.1

/f_CLOCK

1

9

8

f_OUT

Figure 84. I_DVDDvs. f_OUT/f_CLOCKRatio @ DVDD = 3.3 V

7

6

5

2.5

2.0

1.5

1.0

0.5

0

80MSPS

4

3

2

1

0

50MSPS

1

2

3

4

5

I

(mA)

OUTFS

25MSPS

10MSPS

Figure 82. I_AVDDvs. I_OUTFS@ AVDD = 3.3 V

6

5

4

3

2

1

0

0.01

0.1

1

f_OUT/f

CLOCK

Figure 85. I_DVDDvs. f_OUT/f_CLOCKRatio @ DVDD = 1.8 V

5

4

3

2

1

0

DIFF

SE

1.00

1.25

1.50

(mA)

1.75

2.00

I

OUTFS

Figure 83. I_AVDDvs. I_OUTFS@ AVDD = 1.8 V

0

50

100

150

200

f_CLOCK(MSPS)

Figure 86. I_CLKVDDvs. f_CLOCK@ CLKVDD = 3.3 V

Rev. 0 | Page 37 of 52

AD9704/AD9705/AD9706/AD9707

1.4

SELF-CALIBRATION

1.2

1.0

0.8

0.6

The AD970x has a self-calibration feature that improves the

DNL of the device. Performing a self-calibration on the device

improves device performance in low frequency applications.

The device performance in applications where the analog

output frequencies are above 1 MHz are generally influenced

more by dynamic device behavior than by DNL, and in these

cases, self-calibration is unlikely to provide any benefits for

single-tones, as shown in Figure 88. Figure 89 shows that self-

calibration is helpful up to 20 MHz for two-tone IMD spaced

10 kHz apart.

0.4

0.2

0

10

20

30

40

50

60

70

80

90

88

f

(MSPS)

CLOCK

Figure 87. I_CLKVDDvs. f_CLOCK(Differential Clock Mode) @ CLKVDD = 1.8 V

CALIBRATED

86

84

82

80

78

Sleep and Power-Down Operation (Pin Mode)

The AD970x has a sleep mode that turns off the output current

and reduces the total power consumed by the device. This mode

is activated by applying a Logic 1 to the SLEEP/CSB pin. The

SLEEP/CSB pin logic threshold is equal to 0.5 × AVDD. This

digital input also contains an active pull-down circuit.

The AD970x takes less than 50 ns to power down and approxi-

mately 5 μs to power back up.

UNCALIBRATED

Sleep and Power-Down Operation (SPI Mode)

0

0.2

0.4

0.6

0.8

The AD970x offers three power-down functions that can be

controlled through the SPI. These power-down modes can be

used to minimize the power dissipation of the device. The

power-down functions are controlled through SPI Register 0x00,

Bit 1 to Bit 3. Table 25 summarizes the power-down functions

that can be controlled through the SPI. The power-down mode

can be enabled by writing a Logic 1 to the corresponding bit in

Register 0x00.

f_OUT(MHz)

Figure 88. AD9707 SFDR vs. f_OUT@ 175 MSPS and I_OUTFS= 2 mA

88

87

86

85

84

83

82

81

80

79

78

CALIBRATED

Table 25. Power-Down Mode Selection

UNCALIBRATED

Power-Down

Mode

(Reg. 0x00)

Bit #

Functional Description

Turn off clock

Turn off output current

Turn off output current and

internal voltage reference

Clock Off

Sleep

Power Down

1

2

3

0

5

10

15

20

LOWER f_OUT(MHz)

Figure 89. IMD vs. f_OUT@ 175 MSPS and I_OUTFS= 2 mA

Rev. 0 | Page 38 of 52

AD9704/AD9705/AD9706/AD9707

To perform a device self-calibration, the following procedure

can be used.

To read the calibration coefficients

1. Enable the calibration clock by setting the CALCLK bit

(Register 0x02, Bit 0).

The calibration clock frequency is equal to the DAC clock

divided by the division factor chosen by the DIVSEL value. The

frequency of the calibration clock must be set to under 10 MHz

for reliable calibrations. Best results are obtained by setting

DIVSEL[2:0] (Register 0x0E, Bit 2 to Bit 0) to produce the

lowest frequency calibration clock frequency that your system

requirements allow.

2. Write the address of the first coefficient (0x00) to

Register 0x10.

3. Set the SMEMRD bit (Register 0x0F, Bit 2) by writing 0x04

to Register 0x0F.

4. Read the value of the first coefficient by reading the

contents of Register 0x11.

1. Enable the calibration clock by setting the CALCLK bit

(Register 0x02, Bit 0).

5. Clear the SMEMRD bit by writing 0x00 to Register 0x0F.

2. Enable self-calibration by writing 0x40 to Register 0x0F.

6. Repeat Step 2 through Step 5 for each of the remaining 32

coefficients by incrementing the address by one each read.

3. Wait approximately 4500 calibration clock cycles. Each

calibration clock cycle is between 2 and 256 DAC clock

cycles, depending on the value of DIVSEL[2:0].

7. Disable the calibration clock by clearing the CALCLK Bit

(Register 0x02, Bit 0).

4. Check if the self-calibration has completed by reading the

CALSTAT bit (Register 0x0F, Bit 7). A Logic 1 indicates the

calibration has completed.

To write the calibration coefficients to the device:

1. Enable the calibration clock by setting the CALCLK bit

(Register 0x02, Bit 0).

5. When the self-calibration has completed, write 0x00 to

Register 0x0F.

2. Set the SMEMWR bit (Register 0x0F, Bit 3) by writing 0x08

to Register 0x0F.

6. Disable the calibration clock by clearing the CALCLK Bit

(Register 0x02, Bit 0).

3. Write the address of the first coefficient (0x00) to

Register 0x10.

The AD970x devices allow reading and writing of the calibration

coefficients. There are 33 coefficients in total. The read/write

feature of the coefficients could be useful for improving the results

of the self-calibration routine by averaging the results of several

calibration results and loading the averaged results back into the

device. The reading and writing routines follow.

4. Write the value of the first coefficient to Register 0x11.

5. Repeat Step 2 and Step 3 for each of the remaining 32

coefficients by incrementing the address by one each write.

6. Clear the SMEMWR bit by writing 0x00 to Register 0x0F.

7. Disable the calibration clock by clearing the CALCLK bit

(Register 0x02, Bit 0).

Rev. 0 | Page 39 of 52

AD9704/AD9705/AD9706/AD9707

APPLICATIONS

A differential resistor, R_DIFF, can be inserted in applications where

the output of the transformer is connected to the load, R_LOAD, via

a passive reconstruction filter or cable. R_DIFF, as reflected by the

transformer, is chosen to provide a source termination that

results in a low VSWR. Note that approximately half the signal

OUTPUT CONFIGURATIONS

The following sections illustrate some typical output configura-

tions for the AD970x. Unless otherwise noted, it is assumed that

I

_OUTFSis set to a nominal 2 mA. For applications requiring the

optimum dynamic performance, a differential output configuration

is suggested. A differential output configuration can consist of

either an RF transformer or a differential op amp configuration.

The transformer configuration provides the optimum high

frequency performance and is recommended for any application

that allows ac coupling. The differential op amp configuration is

suitable for applications requiring dc coupling, signal gain,

and/or a low output impedance.

power is dissipated across R_DIFF

.

SINGLE-ENDED BUFFERED OUTPUT

USING AN OP AMP

An op amp can be used to perform a single-ended current-

to-voltage conversion, as shown in Figure 91.. Thue AD970x is

configured with a pair of series resistors, R_S, off each output.

The feedback resistor, R_FB, determines the peak single-ended

output voltage by the formula

A single-ended output is suitable for applications where low

cost and low power consumption are primary concerns.

I_FS

2

V_OUT= R_FB

×

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to-

single-ended signal conversion, as shown in Figure 90. The

distortion performance of a transformer typically exceeds that

available from standard op amps, particularly at higher frequencies.

Transformer coupling provides excellent rejection of common-

mode distortion (that is, even-order harmonics) over a wide

frequency range. It also provides electrical isolation and can

deliver voltage gain without adding noise. Transformers with

different impedance ratios can also be used for impedance

matching purposes. The main disadvantages of transformer

coupling are the low frequency roll-off, lack of power gain, and

the higher output impedance.

The common-mode voltage of the output is determined by the

formula

R

V_CM= V_REF× (1+ ^FB) − V_OUT

R_B

The maximum and minimum voltages out of the amplifier are

R_FB

R_B

V_MAX= V_REF× (1+

)

V_MIN= V_MAX− I_FS× R_FB

respectively.

C

F

22

IOUTB

AD9704/AD9705

AD9706/AD9707

R

FB

B

R

LOAD

+5V

AD9704/AD9705

AD9706/AD9707

R

S

21

IOUTA

OPTIONAL R

DIFF

V

ADA4841

OUT

23

REFIO

Figure 90. Differential Output Using a Transformer

C

R

S

20

19

IOUTB

OTCM

The center tap on the primary side of the transformer must be

connected to a voltage that keeps the voltages on IOUTA and

IOUTB within the output common voltage range of the device.

It should be noted that the dc component of the DAC output

current is equal to I_FS/2 and flows out of both IOUTA and

IOUTB. The center tap of the transformer should provide a

path for this dc current. In many applications, AGND provides

the most convenient voltage for the transformer center tap. The

complementary voltages appearing at IOUTA and IOUTB (that

is, V_IOUTAand V_IOUTB) swing symmetrically around AGND and

should be maintained with the specified output compliance

range of the AD970x.

Figure 91. Single-Supply Single-Ended Buffer

Rev. 0 | Page 40 of 52

AD9704/AD9705/AD9706/AD9707

C

F

DIFFERENTIAL BUFFERED OUTPUT

USING AN OP AMP

R

FB

B

A dual op amp (see the circuit shown in Figure 92) can be used

in a differential version of the single-ended buffer shown in

Figure 91. The same R-C network is used to form a 1-pole

differential, low-pass filter to isolate the op amp inputs from the

high frequency images produced by the DAC outputs. The feed-

back resistors, R_FB, determine the peak differential output

voltage by the formula

AD9704/AD9705

AD9706/AD9707

R

S

21

IOUTA

ADA4841

23

REFIO

V

C

OUT

OTCM

IOUTB

19

20

R

S

V_OUT= R_FB× I_FS

C

F

The maximum and minimum voltages out of the amplifier are

R

FB

B

R_FB

R_B

V_MAX= V_REF× (1+

)

Figure 92. Single-Supply Differential Buffer

V_MIN=V_MAX−V_OUT

respectively. The common-mode voltage of the output is

determined by the formula

V _OUT

2

V_CM= V_MAX

−

Rev. 0 | Page 41 of 52

AD9704/AD9705/AD9706/AD9707

EVALUATION BOARD

The AD970x board allows the user the flexibility to operate the

part in various configurations. Possible output configurations

include transformer coupled, resistor terminated, and single and

differential outputs. The digital inputs are designed to be driven

from various data pattern generators, with the on-board option

to add a resistor network for proper load termination. Provisions

are also made to operate the AD970x with either the internal or

external reference, or to exercise the power-down feature.

GENERAL DESCRIPTION

The TxDAC family evaluation boards allow for easy setup and

testing of any TxDAC products. Careful attention to layout and

circuit design, combined with a prototyping area, allows the user

to evaluate the AD970x easily and effectively in any application

where a low power, high resolution, high speed conversion is

required.

Rev. 0 | Page 42 of 52

AD9704/AD9705/AD9706/AD9707

EVALUATION BOARD SCHEMATICS

5 1 0 6 - 9 2 0 5

1

1 0

R 9

R1

2

9

R 8

R2

3

8

R 7

R3

4

7

R 6

R4

5

6

R 5

R5

6

5

R 4

R6

7

4

R 3

R7

8

3

R 2

R8

9

2

R 1

R9

10

1

RCOM

1 0

R 9

R1

2

9

R 8

R2

3

8

R 7

R3

4

7

R 6

R4

5

6

R 5

R5

6

5

R 4

R6

7

4

R 3

R7

8

3

R 2

R8

9

2

R 1

R9

10

1

RIBBON R A

Figure 93. Digital Inputs

Rev. 0 | Page 43 of 52

AD9704/AD9705/AD9706/AD9707

0 - 5 2 5 0 9 2 6

3 0 0 6 R C

3

0 6 0 R C

RC0805

J P 9

Y A 6 E R V 3 , 2 3 B E A 6 Y E R

3 0 0 6 R C

RC0805

3 0 0 6 R C

J P 8

Y A 6 E R V 3 , 2 3 B E A 6 Y E R

RC0805

J P 7

Y A 6 E R V 3 , 2 3 B E A 6 Y E R

3 0 0 6 R C

R 7

Figure 94. Output Signal Conditioning

Rev. 0 | Page 44 of 52

AD9704/AD9705/AD9706/AD9707

5 3 0 6 - 9 2 0 5

0 6 C 0 R 3

2

A

B

1

3

0

J P 2

2

B

A

1

3

J P 2

3

0 6 C 0 C 3

2

A

B

1

3

0

J P 3

6 0 3 C R

0 6 C 0 C 3

JP16

JP21

Figure 95. Clock

Rev. 0 | Page 45 of 52

AD9704/AD9705/AD9706/AD9707

5 4 0 6 - 9 2 0 5

3 6 0 R C 0

J P 5

J P 4

J P 1

3 6 0 R C 0

Figure 96. SPI

Rev. 0 | Page 4± of 52

AD9704/AD9705/AD9706/AD9707

0 7 7 2 6 - 5 9 0

6 0 3 C R

0 3 0 6 C R

6 0 3 C C

0 3 0 6 C C

2

1

P

Figure 97. Power Supplies

Rev. 0 | Page 47 of 52

AD9704/AD9705/AD9706/AD9707

EVALUATION BOARD LAYOUT

Figure 98. Assembly—Primary Side

Figure 99. Assembly—Secondary Side

Rev. 0 | Page 48 of 52

AD9704/AD9705/AD9706/AD9707

Figure 100. Layer 1—Primary Side

Figure 101. Layer 4—Secondary Side

Rev. 0 | Page 49 of 52

AD9704/AD9705/AD9706/AD9707

Figure 102. Layer 2—Ground Plane

Figure 103. Layer 3—Power Plane

Rev. 0 | Page 50 of 52

AD9704/AD9705/AD9706/AD9707

OUTLINE DIMENSIONS

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

3.25

3.10 SQ

2.95

EXPOSED

PAD

(BOTTOM VIEW)

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

3.50 REF

0.80 MAX

0.65 TYP

12° MAX

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 104. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

−40°C to +85°C

Package Description

32-Lead LFCSP_VQ

Evaluation Board

Package Option

CP-32-2

AD9704BCPZ¹

AD9704BCPZRL7¹

AD9705BCPZ¹

AD9705BCPZRL7¹

AD970±BCPZ¹

AD970±BCPZRL7¹

AD9707BCPZ¹

AD9707BCPZRL7¹

AD9704-EB

CP-32-2

AD9705-EB

AD970±-EB

AD9707-EB

¹Z = Pb-free part.

Rev. 0 | Page 51 of 52

AD9704/AD9705/AD9706/AD9707

NOTES

registered trademarks are the property of their respective owners.

D05926-0-7/06(0)

Rev. 0 | Page 52 of 52


型号：	AD9706BCPZRL7
厂家：	ADI
描述：	8-/10-/12-/14-Bit, 175 MSPS TxDAC D/A Converters 8位/ 10位/ 12位/ 14位， 175 MSPS TxDAC系列D / A转换器转换器
文件：	总52页 (文件大小：2134K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9706BCPZRL7 [ADI]

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AD9707BCPZ

AD9707BCPZRL7

AD9707BRUZ