AD9778BSVZ [ADI]
Dual 14-Bit, 1 GSPS, Digital-to-Analog Converter;
| 型号： | AD9778BSVZ |
| 厂家： | 
ADI |
| 描述： | Dual 14-Bit, 1 GSPS, Digital-to-Analog Converter 转换器 |
| 文件： | 总56页 (文件大小：1029K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, 12-/14-/16-Bit,
1.0 GSPS D/A Converter
AD9776/AD9778/AD9779
GENERAL DESCRIPTION
FEATURES
DAC output sample rate: 1 GSPS
1.8 V/3.3 V single supply operation
Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,
full operating conditions
SFDR = 78 dBc to fOUT = 100 MHz
Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF
CMOS data input interface with adjustable setup and hold
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator/coarse complex modulator
allows carrier placement anywhere in DAC bandwidth
Auxiliary DACs allow control of external VGA and offset control
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high
dynamic range DACs that provide a sample rate of 1 GSPS, thus
permitting multicarrier generation up to its Nyquist frequency.
They include features optimized for direct conversion transmit
applications, including complex digital modulation, and gain
and offset compensation. The DAC outputs are optimized to
interface seamlessly with analog quadrature modulators such as
the AD8349. A serial peripheral interface (SPI) provides for
programming/readback of many internal parameters. The
output current can be programmed over a range of 10 mA to
30 mA. The devices are manufactured on an advanced 0.18 μm
CMOS process and operate from 1.8 V and 3.3 V supplies for
a total power consumption of 1.0 W. They are enclosed in
100-lead TQFP packages.
100-lead, exposed paddle TQFP package
PRODUCT HIGHLIGHTS
APPLICATIONS
Wireless infrastructure
Digital high or low IF synthesis
Internal digital upconversion capability
Transmit diversity
Wideband communications systems
point-to-point wireless, LMDS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs can be easily configured for various
single-ended or differential circuit topologies.
Multicarrier WCDMA
Multicarrier GSM
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD9776/AD9778/AD9779
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 3
Driving the DACCLK Input ..................................................... 33
Full-Scale Current Generation ................................................. 36
Power Dissipation....................................................................... 37
Power-Down and Sleep Modes................................................. 38
Interleaved Data Mode .............................................................. 39
Timing Information................................................................... 39
Evaluation Board Operation......................................................... 45
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 22
Theory of Operation ...................................................................... 23
Serial Peripheral Interface......................................................... 23
MSB/LSB Transfers..................................................................... 24
SPI Register Map............................................................................. 25
Interpolation Filter Architecture .................................................. 29
Modifying the Evaluation Board to Use the AD8349 On-
Board Quadrature Modulator................................................... 47
Evaluation Board Schematics ................................................... 48
Outline Dimensions....................................................................... 55
Ordering Guide .......................................................................... 55
Interpolation Filter Minimum and Maximum Bandwidth
Specifications .............................................................................. 33
REVISION HISTORY
7/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 56
AD9776/AD9778/AD9779
FUNCTIONAL BLOCK DIAGRAM
DELAY LINE
SYNC_O
SYNC_I
CLOCK GENERATION/DISTRIBUTION
CLOCK
MULTIPLIER
2×/4×/8×
CLK+
CLK–
DELAY LINE
DATACLK_OUT
DATA
ASSEMBLER
1
SYNC
IOUT1_P
IOUT1_N
16-BIT
IDAC
P1D(15:0)
P2D(15:0)
I LATCH
2×
2×
2×
2×
2×
n × fDAC/8
n = 1 TO 7
COMPLEX
MODULATOR
IOUT2_P
IOUT2_N
Q LATCH
16-BIT
QDAC
2×
1
SYNC
DIGITAL CONTROLLER
10
10
GAIN
GAIN
VREF
RSET
REFERENCE
AND BIAS
SERIAL
PERIPHERAL
INTERFACE
POWER-ON
RESET
10
10
AUX1_P
AUX1_N
GAIN
GAIN
AUX2_P
AUX2_N
Figure 1.
Rev. 0 | Page 3 of 56
AD9776/AD9778/AD9779
SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 1. AD9776, AD9778, and AD9779 DC Specifications
AD9776
Typ
AD9778
Typ
AD9779
Typ
Parameter
Min
Max
Min
Max
Min
Max
Unit
RESOLUTION
12
14
16
Bits
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error (with Internal
Reference)
0.1
0.6
0.65
1
2.1
3.ꢀ
LSB
LSB
–0.001
0
2
+0.001
–0.001
0
2
+0.001
–0.001
0
2
+0.001 % FSR
% FSR
Full-Scale Output Current1
Output Compliance Range
Output Resistance
8.66
–1.0
20.2
10
31.66
+1.0
8.66
–1.0
20.2
10
31.66
+1.0
8.66
–1.0
20.2
10
31.66
+1.0
mA
V
MΩ
Gain DAC Monotonicity
Guaranteed
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
AUX DAC OUTPUTS
Resolution
Full-Scale Output Current1
Output Compliance Range
(Source)
0.04
100
30
0.04
100
30
0.04
100
30
ppm/°C
ppm/°C
ppm/°C
10
10
10
Bits
+1.998 mA
–1.998
0
+1.998
1.6
–1.998
0
+1.998
1.6
–1.998
0
1.6
V
Output Compliance Range
(Sink)
0.8
1.6
0.8
1.6
0.8
1.6
V
Output Resistance
1
1
1
MΩ
Aux DAC Monotonicity
Guaranteed
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
1.2
5
1.2
5
1.2
5
V
kΩ
3.13
1.ꢀ0
3.3
1.8
3.4ꢀ
1.90
3.13
1.ꢀ0
3.3
1.8
3.4ꢀ
1.90
3.13
1.ꢀ0
3.3
1.8
3.4ꢀ
1.90
V
V
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
3.13
1.ꢀ0
3.3
1.8
3.4ꢀ
1.90
3.13
1.ꢀ0
3.3
1.8
3.4ꢀ
1.90
3.13
1.ꢀ0
3.3
1.8
3.4ꢀ
1.90
V
V
POWER CONSUMPTION
1× Mode, fDAC = 100 MSPS,
IF = 1 MHz
2× Mode, fDAC = 320 MSPS,
IF = 16 MHz, PLL Off
2× Mode, fDAC = 320 MSPS,
IF = 16 MHz, PLL On
4× Mode, fDAC/4 Mod,
fDAC = 500 MSPS,
250
498
588
5ꢀ2
300
250
498
588
5ꢀ2
300
250
498
588
5ꢀ2
300
mW
mW
mW
mW
IF = 13ꢀ.5 MHz, Q DAC Off
Rev. 0 | Page 4 of 56
AD9776/AD9778/AD9779
AD9776
Typ
AD9778
Typ
AD9779
Typ
Parameter
Min
Max
Min
Max
Min
Max
Unit
8× Mode, fDAC/4 Mod,
980
980
980
mW
fDAC = 1 GSPS, IF = 262.5 MHz
Power-Down Mode
2
3.ꢀ
2
3.ꢀ
2
3.ꢀ
mW
Power Supply Rejection Ratio—
AVDD33
OPERATING RANGE
–0.3
–40
+0.3
–0.3
–40
+0.3
–0.3
–40
+0.3
% FSR/V
+25
+85
+25
+85
+25
+85
°C
1 Based on a 10 kΩ external resistor.
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, unless otherwise noted.
Table 2. AD9776, AD9778, and AD9779 Digital Specifications
Parameter
Min
Typ
Max
Unit
LVDS RECEIVER INPUTS
(SYNC_I+, SYNC_I–), SYNC_I+ = VIA, SYNC_I– = VIB
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH − VIDTHL
Receiver Differential Input Impedance, RIN
LVDS Input Rate
825
–100
15ꢀ5
+100
mV
mV
mV
Ω
MSPS
ns
20
1
80
120
125
Set-Up Time, Sync_I to DAC Clock
Hold Time, Sync_I to DAC Clock
–0.2
1
ns
LVDS DRIVER OUTPUTS
(SYNC_O+, SYNC_O–), SYNC_O+ = VOA, SYNC_O– = VOB, 100 Ω Termination
Output Voltage High, VOA or VOB
Output Voltage Low, VOA or VOB
Output Differential Voltage, |VOD|
Output Offset Voltage, VOS
Output Impedance, Single-Ended, RO
Maximum Clock Rate
825
1025
150
1150
80
15ꢀ5
mV
mV
mV
mV
Ω
200
100
250
1250
120
1
GHz
DAC CLOCK INPUT (CLK+, CLK–)
Peak-to-Peak Voltage at CLK+ and CLK–2
Common-Mode Voltage
400
300
800
400
1
1600
500
mV
mV
GSPS
Maximum Clock Rate3
SERIAL PERIPHERAL INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
40
12.5
12.5
MHz
ns
ns
Minimum Pulse Width Low
INPUT DATA
Set-Up Time, Input Data To DATACLK (All Modes)
Hold Time, Input Data To DATACLK (All Modes)
3.0
–0.ꢀ8
ns
ns
1 Guaranteed at 25°C. Can drift above 120 ꢀ at temperatures above 25°C.
2 When using the PLL, a minimum 1 V swing is recommended.
3 Typical maximum clock rate when DVDD18 = CVDD18 = 1.9 V.
Rev. 0 | Page 5 of 56
AD9776/AD9778/AD9779
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 3. AD9776, AD9778, and AD9779 AC Specifications
AD9776
AD9778
Max Min Typ
AD9779
Max Min Typ
Parameter
Min
Typ
Max Unit
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 100 MSPS, fOUT = 20 MHz
fDAC = 200 MSPS, fOUT = 50 MHz
fDAC = 400 MSPS, fOUT = ꢀ0 MHz
fDAC = 800 MSPS, fOUT = ꢀ0 MHz
82
81
80
85
82
81
80
85
82
82
80
8ꢀ
dBc
dBc
dBc
dBc
TWO-TONE INTERMODULATION DISTORTION
(IMD)
fDAC = 200 MSPS, fOUT = 50 MHz
fDAC = 400 MSPS, fOUT = 60 MHz
fDAC = 400 MSPS, fOUT = 80 MHz
fDAC = 800 MSPS, fOUT = 100 MHz
8ꢀ
80
ꢀ5
ꢀ5
8ꢀ
85
81
80
91
85
81
81
dBc
dBc
dBc
dBc
NOISE SPECTRAL DENSITY (NSD) Eight-Tone,
500 kHz Tone Spacing
fDAC = 200 MSPS, fOUT = 80 MHz
fDAC = 400 MSPS, fOUT = 80 MHz
fDAC = 800 MSPS, fOUT = 80 MHz
–152
–155
–15ꢀ.5
–155
–159
–160
–158
–160
–161
dBm/Hz
dBm/Hz
dBm/Hz
WCDMA ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 100 MHz
fDAC = 491.52 MSPS, fOUT = 200 MHz
ꢀ6
69
ꢀ8
ꢀ3
ꢀ9
ꢀ4
dBc
dBc
WCDMA SECOND ADJACENT CHANNEL
LEAKAGE RATIO (ACLR), SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 100 MHz
fDAC = 491.52 MSPS, fOUT = 200 MHz
ꢀꢀ.5
ꢀ6
80
ꢀ8
81
ꢀ8
dBc
dBc
Rev. 0 | Page 6 of 56
AD9776/AD9778/AD9779
ABSOLUTE MAXIMUM RATINGS
Table 4.
Thermal Resistance
100-lead, thermally enhanced TQFP Package θJA = 27.4°C/W
(with no airflow movement).
With
Respect
to
Parameter
Rating
AVDD33
AGND
DGND
CGND
−0.3 V to +3.6 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
DVDD33, DVDD18, CVDD18
AGND
DGND
CGND
DGND
CGND
AGND
CGND
AGND
DGND
−0.3 V to +1.98 V
AGND
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
DGND
CGND
I120, VREF, IPTAT
IOUT1-P, IOUT1-N, IOUT2-P
AGND
AGND
−0.3 V to AVDD33 + 0.3 V
−1.0 V to AVDD33 + 0.3 V
,
IOUT2-N, Aux1-P, Aux1-N, Aux2-P,
Aux2-N
P1D15 to P1D0,
P2D15 to P2D0
DGND
−0.3 V to DVDD33 + 0.3 V
DATACLK, TXENABLE
CLK+, CLK−, RESET, IRQ,
PLL_LOCK, SYNC_O+,
DGND
CGND
−0.3 V to DVDD33 + 0.3 V
−0.3 V to CVDD18 + 0.3 V
SYNC_O−, SYNC_I+, SYNC_I–
RESET, IRQ, PLL_LOCK,
SYNC_O+, SYNC_O–,
SYNC_I+, SYNC_I–, CSB,
SCLK, SDIO, SDO
DGND
–0.3 V to DVDD33 + 0.3 V
Junction Temperature
Storage Temperature
+125°C
−65°C to +150°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page ꢀ of 56
AD9776/AD9778/AD9779
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CVDD18
CVDD18
CGND
I120
PIN 1
2
VREF
3
IPTAT
AGND
IRQ
ANALOG DOMAIN
DIGITAL DOMAIN
4
CGND
5
CLK+
6
CLK–
RESET
CSB
7
CGND
8
CGND
SCLK
SDIO
9
CVDD18
CVDD18
CGND
AD9776
TOP VIEW
(Not to Scale)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SDO
PLL_LOCK
DGND
SYNC_O+
SYNC_O–
DVDD33
DVDD18
NC
AGND
SYNC_I+
SYNC_I–
DGND
DVDD18
P1D<11>
P1D<10>
P1D<9>
P1D<8>
P1D<7>
DGND
NC
NC
NC
P2D<0>
DGND
DVDD18
P2D<1>
P2D<2>
DVDD18
P1D<6>
P1D<5>
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC = NO CONNECT
Figure 2. AD9776 Pin Configuration
Table 5. AD 9776 Pin Function Description
Pin No. Mnemonic
Description
Pin No. Mnemonic
Description
1
2
3
4
5
6
ꢀ
8
CVDD18
CVDD18
CGND
1.8 V Clock Supply
1.8 V Clock Supply
Clock Common
19
20
21
22
23
24
25
26
2ꢀ
28
29
30
31
32
33
34
35
36
P1D <9>
P1D <8>
P1D <ꢀ>
DGND
DVDD18
P1D <6>
P1D <5>
P1D <4>
P1D <3>
P1D <2>
P1D <1>
P1D <0>
NC
Port 1, Data Input D9
Port 1, Data Input D8
Port 1, Data Input Dꢀ
Digital Common
1.8 V Digital Supply
Port 1, Data Input D6
Port 1, Data Input D5
Port 1, Data Input D4
Port 1, Data Input D3
Port 1, Data Input D2
Port 1, Data Input D1
Port 1, Data Input D0
No Connect
CGND
Clock Common
CLK+1
Differential Clock Input
Differential Clock Input
Clock Common
CLK–1
CGND
CGND
CVDD18
CVDD18
CGND
Clock Common
9
1.8 V Clock Supply
1.8 V Clock Supply
Clock Common
10
11
12
13
14
15
16
1ꢀ
18
AGND
Analog Common
SYNC_I+
SYNC_I–
DGND
DVDD18
P1D <11>
P1D <10>
Differential Synchronization Input
Differential Synchronization Input
Digital Common
1.8 V Digital Supply
Port 1, Data Input D11 (MSB)
Port 1, Data Input D10
DGND
DVDD18
NC
NC
NC
Digital Common
1.8 V Digital Supply
No Connect
No Connect
No Connect
Rev. 0 | Page 8 of 56
AD9776/AD9778/AD9779
Pin No. Mnemonic
Description
Pin No. Mnemonic
Description
DATACLK
DVDD33
TXENABLE
P2D <11>
P2D <10>
P2D <9>
DVDD18
DGND
P2D <8>
P2D <ꢀ>
P2D <6>
P2D <5>
P2D <4>
P2D <3>
P2D <2>
P2D <1>
DVDD18
DGND
P2D <0>
NC
NC
NC
NC
DVDD18
DVDD33
SYNC_O–
SYNC_O+
DGND
PLL_LOCK
SDO
SDIO
3ꢀ
38
39
40
41
42
43
44
45
46
4ꢀ
48
49
50
51
52
53
54
55
56
5ꢀ
58
59
60
61
62
63
64
65
66
6ꢀ
68
69
ꢀ0
ꢀ1
ꢀ2
ꢀ3
Data Clock Output
3.3 V Digital Supply
Transmit Enable
Port 2, Data Input D11 (MSB)
Port 2, Data Input D10
Port 2, Data Input D9
1.8 V Digital Supply
Digital Common
Port 2, Data Input D8
Port 2, Data Input Dꢀ
Port 2, Data Input D6
Port 2, Data Input D5
Port 2, Data Input D4
Port 2, Data Input D3
Port 2, Data Input D2
Port 2, Data Input D1
1.8 V Digital Supply
Digital Common
Port 2, Data Input D0
No Connect
No Connect
No Connect
No Connect
1.8 V Digital Supply
3.3 V Digital Supply
Differential Synchronization Output
Differential Synchronization Output
Digital Common
PLL Lock Indicator
SPI Port Data Output
SPI Port Data Input/Output
SPI Port Clock
ꢀ4
ꢀ5
ꢀ6
ꢀꢀ
ꢀ8
ꢀ9
80
81
82
83
VREF
I120
Voltage Reference Output
120 μA Reference Current
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
Analog Common
Differential DAC Current Output,
Channel 2
Differential DAC Current Output,
Channel 2
Analog Common
Auxiliary DAC Voltage Output,
Channel 2
Auxiliary DAC Voltage Output,
Channel 2
Analog Common
Auxiliary DAC Voltage Output,
Channel 1
Auxiliary DAC Voltage Output,
Channel 1
Analog Common
Differential DAC Current Output,
Channel 1
Differential DAC Current Output,
Channel 1
AVDD33
AGND
AVDD33
AGND
AVDD33
AGND
AGND
OUT2_P
84
OUT2_N
85
86
AGND
AUX2_P
8ꢀ
AUX2_N
88
89
AGND
AUX1_N
90
AUX1_P
91
92
AGND
OUT1_N
93
OUT1_P
94
95
96
9ꢀ
98
99
100
AGND
AGND
AVDD33
AGND
AVDD33
AGND
Analog Common
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
SCLK
CSB
RESET
IRQ
AGND
IPTAT
SPI Port Chip Select Bar
Reset, Active High
Interrupt Request
Analog Common
Reference Current
AVDD33
1 The combined differential clock input at the CLK+ and CLK– pins are referred
to as DACCLK.
Rev. 0 | Page 9 of 56
AD9776/AD9778/AD9779
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CVDD18
I120
PIN 1
2
CVDD18
CGND
VREF
3
IPTAT
AGND
IRQ
ANALOG DOMAIN
4
CGND
5
CLK+
6
CLK–
DIGITAL DOMAIN
RESET
CSB
7
CGND
8
CGND
SCLK
9
CVDD18
CVDD18
CGND
SDIO
AD9778
TOP VIEW
(Not to Scale)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SDO
PLL_LOCK
DGND
SYNC_O+
SYNC_O–
DVDD33
DVDD18
NC
AGND
SYNC_I+
SYNC_I–
DGND
DVDD18
P1D<13>
P1D<12>
P1D<11>
P1D<10>
P1D<9>
DGND
NC
P2D<0>
P2D<1>
P2D<2>
DGND
DVDD18
P2D<3>
P2D<4>
DVDD18
P1D<8>
P1D<7>
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC = NO CONNECT
Figure 3. AD9778 Pin Configuration
Table 6. AD 9778 Pin Function Description
Pin No. Mnemonic
Description
Pin No. Mnemonic
Description
1
2
3
4
5
6
ꢀ
8
CVDD18
CVDD18
CGND
1.8 V Clock Supply
1.8 V Clock Supply
Clock Common
Clock Common
Differential Clock Input
Differential Clock Input
Clock Common
Clock Common
1.8 V Clock Supply
21
22
23
24
25
26
2ꢀ
28
29
30
31
32
33
34
35
36
3ꢀ
38
39
40
P1D <9>
DGND
Port 1, Data Input D9
Digital Common
DVDD18
P1D <8>
P1D <ꢀ>
P1D <6>
P1D <5>
P1D <4>
P1D <3>
P1D <2>
P1D <1>
DGND
1.8 V Digital Supply
Port 1, Data Input D8
Port 1, Data Input Dꢀ
Port 1, Data Input D6
Port 1, Data Input D5
Port 1, Data Input D4
Port 1, Data Input D3
Port 1, Data Input D2
Port 1, Data Input D1
Digital Common
CGND
CLK+1
CLK–1
CGND
CGND
CVDD18
CVDD18
CGND
9
10
11
12
13
14
15
16
1ꢀ
18
19
20
1.8 V Clock Supply
Clock Common
Analog Common
AGND
SYNC_I+
SYNC_I–
DGND
DVDD18
P1D <13>
P1D <12>
P1D <11>
P1D <10>
Differential Synchronization Input
Differential Synchronization Input
Digital Common
1.8 V Digital Supply
Port 1, Data Input D13 (MSB)
Port 1, Data Input D12
Port 1, Data Input D11
Port 1, Data Input D10
DVDD18
P1D <0>
NC
1.8 V Digital Supply
Port 1, Data Input D0
No Connect
NC
No Connect
DATACLK
DVDD33
TXENABLE
P2D <13>
Data Clock Output
3.3 V Digital Supply
Transmit Enable
Port 2, Data Input D13 (MSB)
Rev. 0 | Page 10 of 56
AD9776/AD9778/AD9779
Pin No. Mnemonic
Description
Pin No. Mnemonic
Description
41
42
43
44
45
46
4ꢀ
48
49
50
51
52
53
54
55
56
5ꢀ
58
59
60
61
62
63
64
65
66
6ꢀ
68
69
ꢀ0
ꢀ1
ꢀ2
ꢀ3
ꢀ4
ꢀ5
P2D <12>
P2D <11>
DVDD18
DGND
Port 2, Data Input D12
Port 2, Data Input D11
1.8 V Digital Supply
Digital Common
ꢀ6
ꢀꢀ
ꢀ8
ꢀ9
80
81
82
83
AVDD33
AGND
AVDD33
AGND
AVDD33
AGND
AGND
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
Analog Common
Differential DAC Current Output,
Channel 2
Differential DAC Current Output,
Channel 2
Analog Common
Auxiliary DAC Voltage Output,
Channel 2
Auxiliary DAC Voltage Output,
Channel 2
Analog Common
P2D <10>
P2D <9>
P2D <8>
P2D <ꢀ>
P2D <6>
P2D <5>
P2D <4>
P2D <3>
DVDD18
DGND
Port 2, Data Input D10
Port 2, Data Input D9
Port 2, Data Input D8
Port 2, Data Input Dꢀ
Port 2, Data Input D6
Port 2, Data Input D5
Port 2, Data Input D4
Port 2, Data Input D3
1.8 V Digital Supply
Digital Common
OUT2_P
84
OUT2_N
85
86
AGND
AUX2_P
8ꢀ
AUX2_N
P2D <2>
P2D <1>
P2D <0>
NC
Port 2, Data Input D2
Port 2, Data Input D1
Port 2, Data Input D0
No Connect
88
89
AGND
AUX1_N
Auxiliary DAC Voltage Output,
Channel 1
Auxiliary DAC Voltage Output,
Channel 1
Analog Common
Differential DAC Current Output,
Channel 1
NC
No Connect
90
AUX1_P
DVDD18
DVDD33
SYNC_O–
SYNC_O+
DGND
PLL_LOCK
SDO
SDIO
SCLK
CSB
RESET
IRQ
1.8 V Digital Supply
3.3 V Digital Supply
Differential Synchronization Output
Differential Synchronization Output
Digital Common
91
92
AGND
OUT1_N
93
OUT1_P
Differential DAC Current Output,
Channel 1
PLL Lock Indicator
94
95
96
9ꢀ
98
99
100
AGND
AGND
AVDD33
AGND
AVDD33
AGND
Analog Common
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
SPI Port Data Output
SPI Port Data Input/Output
SPI Port Clock
SPI Port Chip Select Bar
Reset, Active High
Interrupt Request
Analog Common
Reference Current
Voltage Reference Output
120 μA Reference Current
AVDD33
AGND
IPTAT
VREF
I120
1 The combined differential clock input at the CLK+ and CLK– pins are referred
to as DACCLK.
Rev. 0 | Page 11 of 56
AD9776/AD9778/AD9779
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CVDD18
I120
PIN 1
2
CVDD18
CGND
VREF
3
IPTAT
AGND
IRQ
ANALOG DOMAIN
4
CGND
5
CLK+
6
CLK–
DIGITAL DOMAIN
RESET
CSB
7
CGND
8
CGND
SCLK
SDIO
9
CVDD18
CVDD18
CGND
AD9776
TOP VIEW
(Not to Scale)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SDO
PLL_LOCK
DGND
SYNC_O+
SYNC_O–
DVDD33
DVDD18
NC
AGND
SYNC_I+
SYNC_I–
DGND
DVDD18
P1D<11>
P1D<10>
P1D<9>
P1D<8>
P1D<7>
DGND
NC
NC
NC
P2D<0>
DGND
DVDD18
P2D<1>
P2D<2>
DVDD18
P1D<6>
P1D<5>
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC = NO CONNECT
Figure 4. AD9779 Pin Configuration
Table 7. AD9779 Pin Function Descriptions
Pin No. Mnemonic
Description
Pin No. Mnemonic
Description
1
2
3
4
5
6
ꢀ
8
CVDD18
CVDD18
CGND
1.8 V Clock Supply
1.8 V Clock Supply
Clock Common
Clock Common
Differential Clock Input
Differential Clock Input
Clock Common
Clock Common
1.8 V Clock Supply
1.8 V Clock Supply
Clock Common
Analog Common
Differential Synchronization Input
Differential Synchronization Input
Digital Common
1.8 V Digital Supply
Port 1, Data Input D15 (MSB)
Port 1, Data Input D14
Port 1, Data Input D13
20
21
22
23
24
25
26
2ꢀ
28
29
30
31
32
33
34
35
36
3ꢀ
38
P1D <12>
P1D <11>
DGND
Port 1, Data Input D12
Port 1, Data Input D11
Digital Common
CGND
DVDD18
P1D <10>
P1D <9>
P1D <8>
P1D <ꢀ>
P1D <6>
P1D <5>
P1D <4>
P1D <3>
DGND
DVDD18
P1D <2>
P1D <1>
P1D <0>
DATACLK
DVDD33
1.8 V Digital Supply
Port 1, Data Input D10
Port 1, Data Input D9
Port 1, Data Input D8
Port 1, Data Input Dꢀ
Port 1, Data Input D6
Port 1, Data Input D5
Port 1, Data Input D4
Port 1, Data Input D3
Digital Common
1.8 V Digital Supply
Port 1, Data Input D2
Port 1, Data Input D1
Port 1, Data Input D0 (LSB)
Data Clock Output
3.3 V Digital Supply
CLK+1
CLK–1
CGND
CGND
CVDD18
CVDD18
CGND
9
10
11
12
13
14
15
16
1ꢀ
18
19
AGND
SYNC_I+
SYNC_I–
DGND
DVDD18
P1D <15>
P1D <14>
P1D <13>
Rev. 0 | Page 12 of 56
AD9776/AD9778/AD9779
Pin No. Mnemonic
Description
Pin No. Mnemonic
Description
39
40
41
42
43
44
45
46
4ꢀ
48
49
50
51
52
53
54
55
56
5ꢀ
58
59
60
61
62
63
64
65
66
6ꢀ
68
69
ꢀ0
ꢀ1
ꢀ2
ꢀ3
ꢀ4
TXENABLE
P2D <15>
P2D <14>
P2D <13>
DVDD18
DGND
P2D <12>
P2D <11>
P2D <10>
P2D <9>
P2D <8>
P2D <ꢀ>
P2D <6>
P2D <5>
DVDD18
DGND
P2D <4>
P2D <3>
P2D <2>
P2D <1>
P2D <0>
DVDD18
DVDD33
SYNC_O–
SYNC_O+
DGND
Transmit Enable
ꢀ5
ꢀ6
ꢀꢀ
ꢀ8
ꢀ9
80
81
82
83
I120
AVDD33
AGND
AVDD33
AGND
AVDD33
AGND
120 μA Reference Current
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
Analog Common
Differential DAC Current Output,
Channel 2
Differential DAC Current Output,
Channel 2
Analog Common
Auxiliary DAC Voltage Output,
Channel 2
Auxiliary DAC Voltage Output,
Channel 2
Analog Common
Port 2, Data Input D15 (MSB)
Port 2, Data Input D14
Port 2, Data Input D13
1.8 V Digital Supply
Digital Common
Port 2, Data Input D12
Port 2, Data Input D11
Port 2, Data Input D10
Port 2, Data Input D9
Port 2, Data Input D8
Port 2, Data Input Dꢀ
Port 2, Data Input D6
Port 2, Data Input D5
1.8 V Digital Supply
Digital Common
Port 2, Data Input D4
Port 2, Data Input D3
Port 2, Data Input D2
Port 2, Data Input D1
Port 2, Data Input D0 (LSB)
1.8 V Digital Supply
3.3 V Digital Supply
Differential Synchronization Output
Differential Synchronization Output
Digital Common
AGND
OUT2_P
84
OUT2_N
85
86
AGND
AUX2_P
8ꢀ
AUX2_N
88
89
AGND
AUX1_N
Auxiliary DAC Voltage Output,
Channel 1
Auxiliary DAC Voltage Output,
Channel 1
Analog Common
Differential DAC Current Output,
Channel 1
90
AUX1_P
91
92
AGND
OUT1_N
93
OUT1_P
Differential DAC Current Output,
Channel 1
94
95
96
9ꢀ
98
99
100
AGND
AGND
AVDD33
AGND
AVDD33
AGND
Analog Common
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
Analog Common
3.3 V Analog Supply
PLL_LOCK
SPI_SDO
SPI_SDIO
SCLK
SPI_CSB
RESET
IRQ
AGND
IPTAT
VREF
PLL Lock Indicator
SPI Port Data Output
SPI Port Data Input/Output
SPI Port Clock
SPI Port Chip Select Bar
Reset, Active High
Interrupt Request
Analog Common
Reference Current
Voltage Reference Output
AVDD33
1 The combined differential clock input at the CLK+ and CLK– pins are referred
to as DACCLK.
Rev. 0 | Page 13 of 56
AD9776/AD9778/AD9779
TYPICAL PERFORMANCE CHARACTERISTICS
100
90
80
70
60
50
4.0
3.0
2.0
fDATA = 160MSPS
fDATA = 200MSPS
1.0
0
–1.0
–2.0
–3.0
–4.0
–5.0
–6.0
fDATA = 250MSPS
0
20
40
60
80
100
0
10k
20k
30k
40k
50k
60k
70k
80k
fOUT (MHz)
CODE
Figure 8. AD9779 In-Band SFDR vs. fOUT, 2× Interpolation
Figure 5. AD9779 Typical INL
100
1.0
0.5
fDATA = 200MSPS
fDATA = 100MSPS
90
80
70
60
50
0
fDATA = 150MSPS
–0.5
–1.0
–1.5
–2.0
0
20
40
60
80
100
0
10k
20k
30k
40k
50k
60k
70k
80k
fOUT (MHz)
CODE
Figure 9. AD9779 In-Band SFDR vs. fOUT, 4× Interpolation
Figure 6. AD9779 Typical DNL
100
100
90
80
70
60
50
fDATA = 100MSPS
fDATA = 50MSPS
90
80
70
60
50
fDATA = 160MSPS
fDATA = 250MSPS
fDATA = 125MSPS
fDATA = 200MSPS
0
10
20
30
40
50
0
20
40
60
80
100
fOUT (MHz)
fOUT (MHz)
Figure 10. AD9779 In-Band SFDR vs. fOUT, 8× Interpolation
Figure 7. AD9779 In-Band SFDR vs. fOUT, 1x Interpolation
Rev. 0 | Page 14 of 56
AD9776/AD9778/AD9779
100
90
80
70
60
50
100
90
80
70
60
50
PLL OFF
PLL ON
fDATA = 160MSPS
fDATA = 200MSPS
fDATA = 250MSPS
0
20
40
60
80
100
0
10
20
30
40
fOUT (MHz)
fOUT (MHz)
Figure 11. AD9779 Out-of-Band SFDR vs. fOUT, 2× Interpolation
Figure 14. AD9779 In-Band SFDR, 4× Interpolation,
fDATA = 100 MSPS, PLL On/Off
100
90
100
90
80
70
60
50
0dBFS
–3dBFS
80
–6dBFS
fDATA = 150MSPS
70
fDATA = 100MSPS
60
fDATA = 200MSPS
50
0
20
40
60
80
100
0
20
40
60
80
fOUT (MHz)
fOUT (MHz)
Figure 12. AD9779 Out-of-Band SFDR vs. fOUT, 4× Interpolation
Figure 15. AD9779 In-Band SFDR vs. Digital Full-Scale Input
100
90
100
10mA
90
80
70
60
50
20mA
fDATA = 50MSPS
80
70
60
50
fDATA = 100MSPS
30mA
fDATA = 125MSPS
0
10
20
30
40
50
0
20
40
60
80
fOUT (MHz)
fOUT (MHz)
Figure 13. AD9779 Out-of-Band SFDR vs. fOUT, 8× Interpolation
Figure 16. AD9779 In-Band SFDR vs. Output Full-Scale Current
Rev. 0 | Page 15 of 56
AD9776/AD9778/AD9779
100
100
90
80
70
60
50
fDATA = 160MSPS
fDATA = 200MSPS
90
80
70
60
50
fDATA = 250MSPS
fDATA = 75MSPS
fDATA = 100MSPS
fDATA = 50MSPS
fDATA = 125MSPS
0
20
40
60
80
100
120
fOUT (MHz)
fOUT (MHz)
Figure 20. AD9779 Third Order IMD vs. fOUT, 8× Interpolation
Figure 17. AD9779 Third Order IMD vs. fOUT, 1× Interpolation
100
100
fDATA = 160MSPS
90
80
70
60
50
90
80
PLL OFF
fDATA = 200MSPS
70
PLL ON
fDATA = 250MSPS
60
50
0
20
40
60
80
100 120 140 160 180 200
0
20 40 60 80 100 120 140 160 180 200 220
fOUT (MHz)
fOUT (MHz)
Figure 21. AD9779 Third Order IMD vs. fOUT, 4× Interpolation,
fDATA = 100 MSPS, PLL On vs. PLL Off
Figure 18. AD9779 Third Order IMD vs. fOUT, 2× Interpolation
100
100
95
90
80
70
60
50
90
85
80
fDATA = 150MSPS
75
70
65
60
fDATA = 100MSPS
fDATA = 200MSPS
55
50
0
40
80
120 160 200 240 280 320 360 400
fOUT (MHz)
0
40
80
120 160 200 240 280 320 360 400
fOUT (MHz)
Figure 19. AD9779 Third Order IMD vs. fOUT, 4× Interpolation
Figure 22. AD9779 Third Order IMD vs. fOUT, over 50 Parts,4× Interpolation,
fDATA = 200 MSPS
Rev. 0 | Page 16 of 56
AD9776/AD9778/AD9779
–150
–154
–158
–162
–166
–170
REF 0dBm
*ATTEN 20dB
*PEAK
Log
10dB/
EXT REF
DC COUPLED
fDAC = 400MSPS
fDAC = 200MSPS
LGAV
51
S2
FC
AA
W1
S3
fDAC = 800MSPS
£(f):
FTUN
SWP
0
20
40
60
80
100
START 1.0MHz
*RES BW 20kHz
STOP 400.0MHz
SWEEP 1.203s (601 pts)
fOUT (MHz)
VBW 20kHz
Figure 26. AD9779 Noise Spectral Density vs. fDAC, Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
Figure 23. AD9779 Single Tone, 4× Interpolation, fDATA = 100 MSPS,
fOUT = 30 MHz
–150
–154
REF 0dBm
*ATTEN 20dB
*PEAK
Log
10dB/
EXT REF
DC COUPLED
fDAC = 200MSPS
–158
fDAC = 400MSPS
LGAV
51
–162
S2
FC
AA
W1
S3
fDAC = 800MSPS
£(f):
FTUN
SWP
–166
–170
0
20
40
60
80
100
START 1.0MHz
*RES BW 20kHz
STOP 400.0MHz
SWEEP 1.203s (601 pts)
fOUT (MHz)
VBW 20kHz
Figure 27. AD9779 Noise Spectral Density vs. fDAC
,
Figure 24. AD9779 Two-Tone Spectrum, 4× Interpolation, fDATA = 100 MSPS,
fOUT = 30,35 MHz
Single-Tone Input at –6 dBFS
–55
–60
–65
–70
–75
–80
–85
–90
–142
–146
–150
0dBFS – PLL ON
–3dBFS
–3dBFS
–154
0dBFS
0dBFS
–158
–6dBFS
–6dBFS
–162
–166
–170
0
20
40
fOUT (MHz)
60
80
0
20 40 60 80 100 120 140 160 180 200 220 240 260
fOUT (MHz)
Figure 25. AD9779 Noise Spectral Density vs. Digital Full-Scale of Single-Tone
Input, fDATA = 200 MSPS, 2× Interpolation
Figure 28. AD9779 ACLR for First Adjacent Band WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF
Rev. 0 | Page 1ꢀ of 56
AD9776/AD9778/AD9779
REF –25.28dBm
*ATTEN 4dB
REF –30.28dBm
*ATTEN 4dB
*AVG
Log
*AVG
Log
10dB/
10dB/
EXT REF
EXT REF
PAVG
10
PAVG
10
W1 S2
W1 S2
CENTER 143.88MHz
*RES BW 30kHz
SPAN 50MHz
SWEEP 162.2ms (601 pts)
CENTER 151.38MHz
*RES BW 30kHz
SPAN 50MHz
SWEEP 162.2ms (601 pts)
VBW 300kHz
VBW 300kHz
LOWER
UPPER
TOTAL CARRIER POWER –12.61dBm/15.3600MHz
REF CARRIER POWER –17.87dBm/3.84000MHz
RMS RESULTS FREQ OFFSET REF BW
dBc dBm
dBc dBm
LOWER
dBm
UPPER
dBc dBm
CARRIER POWER 5.000MHz
3.840MHz –76.75 –89.23 –77.42 –89.91
3.840MHz –80.94 –93.43 –80.47 –92.96
3.840MHz –79.95 –92.44 –78.96 –91.45
FREQ OFFSET INTEG BW dBc
–12.49dBm/
3.84000MHz
10.00MHz
15.00MHz
1 –17.87dBm
2 –20.65dBm
3 –18.26dBm
4 –18.23dBm
5.000MHz
10.00MHz
15.00MHz
3.840MHz –67.70 –85.57 –67.70 –85.57
3.840MHz –70.00 –97.87 –69.32 –87.19
3.840MHz –71.65 –99.52 –71.00 –88.88
Figure 29. AD9779 WCDMA Signal, 4× Interpolation,
fDATA =122.88 MSPS, fDAC/4 Modulation
Figure 32. AD9779 Multicarrier WCDMA Signal, 4× Interpolation,
fDAC =122.88 MSPS, fDAC/4 Modulation
–55
1.5
–60
–65
–70
–75
–80
–85
–90
1.0
0.5
0dBFS – PLL ON
0
–6dBFS
–0.5
–1.0
–1.5
–3dBFS
0dBFS
0
20 40 60 80 100 120 140 160 180 200 220 240 260
fOUT (MHz)
0
2k
4k
6k
8k
10k 12k 14k 16k 18k 20k
CODE
Figure 30. AD9779 ACLR for Third Adjacent Band WCDMA, 4× Interpolation,
Figure 33. AD778 Typical INL
f
DATA = 122.88 MSPS, On-Chip Modulation Translates Baseband Signal to IF
–55
0.6
–60
–65
0.4
0.2
0
–70
0dBFS – PLL ON
–0.2
–0.4
–0.6
–0.8
–1.0
–75
–6dBFS
–80
–3dBFS
–85
0dBFS
–90
0
20 40 60 80 100 120 140 160 180 200 220 240 260
fOUT (MHz)
0
2k
4k
6k
8k
10k
12k 14k 16k 18k
CODE
Figure 31. AD9779 ACLR for Second Adjacent Band WCDMA, 4×
Interpolation, fDATA = 122.88 MSPS. On-Chip Modulation Translates
Baseband Signal to IF
Figure 34. AD9778 Typical DNL
Rev. 0 | Page 18 of 56
AD9776/AD9778/AD9779
100
90
80
70
60
50
REF –25.39dBm
*ATTEN 4dB
*AVG
Log
10dB/
4× 150MSPS
4× 200MSPS
4
×
100MSPS
PAVG
10
W1 S2
0
40
80
120 160 200 240 280 320 360 400
fOUT (MHz)
CENTER 143.88MHz
*RES BW 30kHz
SPAN 50MHz
SWEEP 162.2ms (601 pts)
VBW 300kHz
LOWER
UPPER
RMS RESULTS FREQ OFFSET REF BW
dBc dBm
dBc dBm
CARRIER POWER 5.000MHz
3.884MHz –76.49 –89.23 –76.89 –89.63
3.840MHz –80.13 –92.87 –80.02 –92.76
3.840MHz –80.90 –93.64 –79.53 –92.27
–12.74dBm/
3.84000MHz
10.00MHz
15.00MHz
Figure 35. AD9778 IMD, 4× Interpolation
Figure 38. AD9778 ACLR, fDATA = 122.88 MSPS, 4× Interpolation,
fDAC/4 Modulation
–150
100
90
80
70
60
50
–154
fDATA = 200MSPS
fDAC = 200MSPS
fDATA = 160MSPS
–158
fDAC = 400MSPS
fDATA = 250MSPS
–162
fDAC = 800MSPS
–166
–170
0
20
40
60
80
100
0
20
40
60
80
100
fOUT (MHz)
fOUT (MHz)
Figure 39. AD9778 Noise Spectral Density vs. fDAC Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
Figure 36. AD9778 In-Band SFDR, 2× Interpolation
–150
–60
–70
–154
fDAC = 200MSPS
fDAC = 400MSPS
–158
–162
–166
–170
1ST ADJ CHAN
3RD ADJ CHAN
fDAC = 800MSPS
–80
–90
2ND ADJ CHAN
0
25
50
75
100 125 150 175 200 225 250
fOUT (MHz)
0
20
40
60
80
100
fOUT (MHz)
Figure 37. AD9778 ACLR, Single-Carrier WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, Amplitude = –3 dBFS
Figure 40. AD9778 Noise Spectral Density vs. fDAC Single-Tone Input
at –6 dBFS, fDATA = 200 MSPS
Rev. 0 | Page 19 of 56
AD9776/AD9778/AD9779
0.4
100
90
80
70
60
50
0.3
0.2
fDATA = 160MSPS
0.1
0
fDATA = 250MSPS
–0.1
–0.2
–0.3
–0.4
fDATA = 200MSPS
0
20
40
60
80
100
0
512
1024
1536
2048 2560
CODE
3072
3584 4096
fOUT (MHz)
Figure 41. AD9776 Typical INL
Figure 44. AD9776 In-Band SFDR, 2× Interpolation
0.20
0.15
0.10
0.05
0
–55
–60
–65
–70
–75
–80
–85
–90
1ST ADJ CHAN
3RD ADJ CHAN
–0.05
–0.10
–0.15
–0.20
2ND ADJ CHAN
0
512
1024 1536
2048 2560
CODE
3072
3584 4096
0
25
50
75
100 125 150 175 200 225 250
fOUT (MHz)
Figure 42. AD9776 Typical DNL
Figure 45. AD9776, Single Carrier WCDMA, 4× Interpolation,
fDATA = 122.88 MSPS, Amplitude = –3 dBFS
100
95
90
85
80
75
70
65
60
55
50
REF –25.29dBm
*ATTEN 4dB
*AVG
Log
10dB/
4
×
100MSPS
150MSPS
4× 200MSPS
4
×
PAVG
10
W1 S2
0
40
80
120 160 200 240 280 320 360 400
fOUT (MHz)
CENTER 143.88MHz
*RES BW 30kHz
SPAN 50MHz
SWEEP 162.2ms (601 pts)
VBW 300kHz
LOWER
UPPER
RMS RESULTS FREQ OFFSET REF BW
dBc dBm
dBc dBm
CARRIER POWER 5.000MHz
3.884MHz –75.00 –87.67 –75.30 –87.97
3.840MHz –78.05 –90.73 –77.99 –90.66
3.840MHz –77.73 –90.41 –77.50 –90.17
–12.67dBm/
3.84000MHz
10.00MHz
15.00MHz
Figure 46. AD9776 ACLR, fDATA = 122.88 MSPS, 4× Interpolation,
fDAC/4 Modulation
Figure 43. AD9776 IMD, 4× Interpolation
Rev. 0 | Page 20 of 56
AD9776/AD9778/AD9779
–150
–154
–158
–162
–166
–170
–150
–154
–158
–162
–166
–170
fDAC = 200MSPS
fDAC = 200MSPS
fDAC = 400MSPS
fDAC = 400MSPS
fDAC = 800MSPS
fDAC = 800MSPS
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
fOUT (MHz)
fOUT (MHz)
Figure 48. AD9776 Noise Spectral Density vs. fDAC
Single-Tone Input at –6 dBFS, fDATA = 200 MSPS
,
Figure 47. AD9776 Noise Spectral Density vs. fDAC, Eight-Tone Input
with 500 kHz Spacing, fDATA = 200 MSPS
Rev. 0 | Page 21 of 56
AD9776/AD9778/AD9779
TERMINOLOGY
Linearity Error (Integral Nonlinearity or INL)
In-Band Spurious Free Dynamic Range (SFDR)
The difference, in decibels, between the peak amplitude of the
output signal and the peak spurious signal between dc and the
frequency equal to half the input data rate.
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero scale to full scale.
Differential Nonlinearity (DNL)
Out-of-Band Spurious Free Dynamic Range (SFDR)
The difference, in decibels, between the peak amplitude of the
output signal and the peak spurious signal within the band that
starts at the frequency of the input data rate and ends at the
Nyquist frequency of the DAC output sample rate. Normally,
energy in this band is rejected by the interpolation filters. This
specification therefore defines how well the interpolation filters
work and the effect of other parasitic coupling paths to the DAC
output.
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.
Gain Error
Signal-to-Noise Ratio (SNR)
The difference between the actual and ideal output span. The
actual span is determined by the difference between the output
when all inputs are set to 1 and the output when all inputs are
set to 0.
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Output Compliance Range
Interpolation Filter
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits can
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around fDAC (output data rate) can be greatly suppressed.
Temperature Drift
Adjacent Channel Leakage Ratio (ACLR)
The ratio in dBc between the measured power within a channel
relative to its adjacent channel.
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree Celsius. For reference drift, the drift is
reported in ppm per degree Celsius.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect of
wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band around its final value, measured from the
start of the output transition.
Rev. 0 | Page 22 of 56
AD9776/AD9778/AD9779
ported, as well as MSB-first or LSB-first transfer formats. The
serial interface ports can be configured as a single pin I/O (SDIO)
or two unidirectional pins for input/output (SDIO/SDO).
THEORY OF OPERATION
The AD9776/AD9778/AD9779 combine many features that
make them very attractive DACs for wired and wireless
communications systems. The dual digital signal path and dual
DAC structure allow an easy interface with common quadra-
ture modulators when designing single sideband transmitters.
The speed and performance of the parts allow wider band-
widths and more carriers to be synthesized than in previously
available DACs. The digital engine uses a breakthrough filter
architecture that combines the interpolation with a digital
quadrature modulator. This allows the parts to do digital
quadrature frequency upconversion. They also have features
that allow simplified synchronization with incoming data and
between multiple parts.
General Operation of the Serial Interface
There are two phases to a communication cycle with the
AD977x. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the device, coincident with the first
eight SCLK rising edges. The instruction byte provides the
serial port controller with information regarding the data
transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming
data transfer is a read or write, the number of bytes in the data
transfer, and the starting register address for the first byte of the
data transfer. The first eight SCLK rising edges of each commu-
nication cycle are used to write the instruction byte into the
device.
The serial port configuration is controlled by Reg. 0x00,
Bits <6: 7>. It is important to note that the configuration
changes immediately upon writing to the last bit of the byte.
For multibyte transfers, writing to this register might occur
during the middle of a communication cycle. Care must be
taken to compensate for this new configuration for the
remaining bytes of the current communication cycle.
A logic high on the CSB pin followed by a logic low resets the
SPI port timing to the initial state of the instruction cycle.
From this state, the next eight rising SCLK edges represent the
instruction bits of the current I/O operation, regardless of the
state of the internal registers or the other signal levels at the
inputs to the SPI port. If the SPI port is in the midst of an
instruction cycle or a data transfer cycle, none of the present
data is written.
The same considerations apply to setting the software reset,
RESET (Reg. 0x00, Bit 5) or pulling the RESET pin (Pin 70)
high. All registers are set to their default values, except
Reg. 0x00 and Reg. 0x04, which remain unchanged.
The remaining SCLK edges are for Phase 2 of the communi-
cation cycle. Phase 2 is the actual data transfer between the
device and the system controller. Phase 2 of the communication
cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the
instruction byte. Using one multibyte transfer is preferred.
Single-byte data transfers are useful to reduce CPU overhead
when register access requires only one byte. Registers change
immediately upon writing to the last bit of each transfer byte.
Use of only single-byte transfers when changing serial port
configurations or initiating a software reset is recommended to
prevent unexpected device behavior.
As described in this section, all serial port data is transferred
to/from the device in synchronization to the SCLK pin. If
synchronization is lost, the device has the ability to asynchro-
nously terminate an I/O operation, putting the serial port
controller into a known state and thereby regaining synchro-
nization.
Instruction Byte
The instruction byte contains the information shown in
Table 8.
Table 8. SPI Instruction Byte
MSB
SERIAL PERIPHERAL INTERFACE
LSB
I0
I7
I6
I5
I4
I3
I2
I1
66
SPI_SDO
R/W
N1
N0
A4
A3
A2
A1
A0
SPI
PORT
67
SPI_SDI
68
SPI_SCLK
R/W, Bit 7 of the instruction byte, determines whether a read or
a write data transfer occurs after the instruction byte write.
Logic high indicates a read operation. Logic 0 indicates a write
operation.
69
SPI_CSB
Figure 49. SPI Port
The serial port is a flexible, synchronous serial communications
port allowing easy interface to many industry-standard micro-
controllers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola SPI® and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9776/
AD9778/AD9779. Single or multiple byte transfers are sup-
N1 and N0, Bits 6 and 5 of the instruction byte, determine the
number of bytes to be transferred during the data transfer cycle.
The bit decodes are shown in Table 9.
A4, A3, A2, A1, and A0—Bits 4, 3, 2, 1, and 0, respectively, of
the instruction byte—determine which register is accessed
Rev. 0 | Page 23 of 56
AD9776/AD9778/AD9779
during the data transfer portion of the communications cycle.
For multibyte transfers, this address is the starting byte address.
The remaining register addresses are generated by the device
based on the LSB-first bit (Reg. 0x00, Bit 6).
When LSB first = 1 (LSB first) the instruction and data bit must
be written from LSB to MSB. Multibyte data transfers in LSB-
first format start with an instruction byte that includes the
register address of the least significant data byte followed by
multiple data bytes. The serial port internal byte address gener-
ator increments for each byte of the multibyte communication
cycle.
Table 9. Byte Transfer Count
N0
N1
Description
0
0
1
1
0
1
0
1
Transfer one byte
Transfer two bytes
Transfer three bytes
Transfer four bytes
The serial port controller data address decrements from the
data address written toward 0x00 for multibyte I/O operations if
the MSB-first mode is active. The serial port controller address
increments from the data address written toward 0x1F for
multibyte I/O operations if the LSB-first mode is active.
Serial Interface Port Pin Descriptions
Serial Clock (SCLK)
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
The serial clock pin is used to synchronize data to and from the
device and to run the internal state machines. SCLK’s maxi-
mum frequency is 40 MHz. All data input is registered on the
rising edge of SCLK. All data is driven out on the falling edge of
SCLK.
CSB
SCLK
SDIO
SDO
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5
N
D3 D2 D1 D0
0 0 0
N
0
Chip Select (CSB)
D7 D6 D5
D3 D2 D1 D0
0 0 0
N
N
0
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should stay
low during the entire communication cycle.
Figure 50. Serial Register Interface Timing MSB First
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
Serial Data I/O (SDIO)
Data is always written into the device on this pin. However, this
pin can be used as a bidirectional data line. The configuration
of this pin is controlled by Register 0x00, Bit 7. The default is
Logic 0, which configures the SDIO pin as unidirectional.
A0 A1 A2 A3 A4 N0 N1 R/W D0 D1 D2
D4 D5 D6 D7
N N N
0
0
0
N
N
D0 D1 D2
D4 D5 D6 D7
N N N
0
0
0
Serial Data Out (SDO)
Figure 51. Serial Register Interface Timing LSB First
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the device
operates in a single bidirectional I/O mode, this pin does not
output data and is set to a high impedance state.
tDS
tSCLK
CSB
tPWH
tPWL
MSB/LSB TRANSFERS
SCLK
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register Bit LSB first
(Reg. 0x00, Bit 6). The default is MSB first (LSB first = 0).
tDS
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
SDIO
Figure 52. Timing Diagram for SPI Register Write
When LSB first = 0 (MSB first) the instruction and data bit
must be written from MSB to LSB. Multibyte data transfers in
MSB-first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes should follow from high address to low address. In
MSB-first mode, the serial port internal byte address generator
decrements for each data byte of the multibyte communication
cycle.
CSB
SCLK
tDV
SDIO
SDO
DATA BIT n
DATA BIT n–1
Figure 53. Timing Diagram for SPI Register Read
Rev. 0 | Page 24 of 56
AD9776/AD9778/AD9779
SPI REGISTER MAP
Table 10.
Register
Name
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Def.
Comm
0x00 00
SDIO
Bidirectional
LSB/MSB First
Software
Reset
Power-Down
Mode
Auto Power-
Down Enable
PLL Lock
Indicator
(Read Only)
0x00
Digital
Control
0x01 01
Filter Interpolation Factor <1:0>
Filter Modulation Mode <3:0>
Zero
Stuffing
Enable
0x00
0x02 02
0x03 03
0x04 04
0x05 05
Data Format Dual/Interleaved Real Mode
Data Bus Mode
Data Clock
Delay Enable
Inverse Sinc
Enable
DATACLK TxEnable Q First
Invert Invert
Reserved
0x00
0x00
0x00
Sync
Control
Data Clock Delay Mode <1:0> Data Clock Divide Ratio <1:0>
Data Clock Delay <3:0>
Output Sync Pulse Divide <2:0>
Sync Out
Delay <4>
Sync Out Delay <3:0>
Input Sync Pulse Frequency Ratio <2:0> Sync Input 0x00
Delay <4>
0x06 06
0x0ꢀ 0ꢀ
Sync Input Delay <3:0>
Input Sync Pulse Timing Error Tolerance <3:0>
DAC Clock Offset <4:0>
0x00
0x00
Sync Receiver Sync Driver
Sync
Enable
Enable
Triggering
Edge
PLL Control 0x08 08
0x09 09
PLL Band Select <5:0>
PLL VCO AGC Gain
<1:0>
0xCF
PLL Enable
PLL VCO Divider Ratio <1:0>
PLL Loop Divide Ratio <1:0> PLL Bias Setting <2:0>
PLL Loop Bandwidth Adjustment <4:0>
0x3ꢀ
0x38
Misc
0x0A 10
PLL Control Voltage Range <2:0> (Read Only)
Control
I DAC
Control
Register
0x0B 11
0x0C 12
I DAC Gain Adjustment<ꢀ:0>
0xF9
I DAC Sleep I DAC Power
Down
I DAC Gain Adjustment 0x01
<9:8>
Aux DAC1 0x0D 13
Control
Auxiliary DAC1 Data <ꢀ:0>
0x00
Register
0x0E 14
Auxiliary DAC1 Auxiliary DAC1 Auxiliary DAC1
Auxiliary DAC1 Data 0x00
<9:8>
Sign
Current
Power-Down
Direction
Q DAC
Control
Register
0x0F 15
0x10 16
Q DAC Gain Adjustment <ꢀ;0>
0xF9
Q DAC Sleep Q DAC Power-
Down
Q DAC Gain Adjustment 0x01
<9:8>
Aux DAC2 0x11 1ꢀ
Control
Auxiliary DAC2 Data <ꢀ:0>
0x00
Register
0x12 18
Auxiliary DAC2 Auxiliary DAC2 Auxiliary DAC2
Auxiliary DAC2 Data 0x00
<9:8>
Sign
Current
Power-Down
Direction
0x13 19 to
Reserved
to
24
0x18
Interrupt
Register
0x19 25
Sync Delay IRQ
Sync Delay
IRQ Enable
Internal 0x00
Sync
Loopback
0x1A 26 to
Reserved
to
31
0x1F
Rev. 0 | Page 25 of 56
AD9776/AD9778/AD9779
Table 11. SPI Register Description
Address
Register Name
Hex Decimal Name
Function
Default
Comm Register
00
00
00
00
ꢀ
6
5
4
SDIO Bidirectional
0: Use SDIO pin as input data only
1: Use SDIO as both input and output data
0: First bit of serial data is MSB of data byte
1: First bit of serial data is LSB of data byte
Bit must be written with a 1, then 0 to soft reset
SPI register map
0
LSB/MSB First
0
0
Software Reset
Power-Down Mode
0: All circuitry is active
1: Disable all digital and analog circuitry, only SPI
port is active
00
00
01
3
Auto Power-Down Enable
PLL Lock (Read Only)
Controls auto power-down mode, see Power-
Down and Sleep Modes section
0: PLL is not locked
1: PLL is locked
0
1
0
Digital Control
Register
ꢀ:6
Filter Interpolation Factor
00:1× interpolation
01:2× interpolation
10:4× interpolation
11:8× interpolation
00
01
01
5:2
0
Filter Modulation Mode
Zero Stuffing
See Table 19 for filter modes
0: Zero stuffing off
1: Zero stuffing on
0000
0
02
02
02
ꢀ
6
5
Data Format
0: Signed binary
1: Unsigned binary
0: Both input data ports receive data
1: Data port 1 only receives data
0: Enable Q path for signal processing
0
0
0
Dual/Interleaved Data Bus
Mode
Real Mode
1: Disable Q path data (internal Q channel clocks
disabled, I and Q modulators disabled)
02
02
3
2
Inverse Sinc Enable
DATACLK Invert
0: Inverse sinc filter disabled
1: Inverse sinc filter enabled
0: Output DATACLK same phase as internal
capture clock
0
0
1: Output DATACLK opposite phase as internal
capture clock
02
02
1
0
TxEnable Invert
Q First
Inverts the function of TxEnable Pin 39, see
Interleaved Data Mode section
0: First byte of data is always I data at beginning
of transmit
0
1: First byte of data is always Q data at beginning
of transmit
Sync Control Register
03
03
ꢀ:6
5:4
Data Clock Delay Mode
Extra Data Clock Divide Ratio Data Clock Output Divider (see Table 22 for
Divider Ratio)
00: Manual, no error correction
00
00
03
04
04
04
05
05
3:0
ꢀ:4
3:1
0
ꢀ:4
3:1
Reserved
Data Clock Delay
Output Sync Pulse Divide
Sync Out Delay
Sync Out Delay
000
0000
000
Sets delay of DACCLK in to DATACLK out
Sets frequency of Sync_O pulses
Sync Output Delay, Bit 4
Sync Output Delay, Bit <3:0>
Input Sync Pulse Frequency Divider, see the
Sync Pulse Receiver (Slave Devices) section
0
000
Input Sync Pulse Frequency
05
0
Sync Input Delay
Sync Input Delay, Bit 4
0
Rev. 0 | Page 26 of 56
AD9776/AD9778/AD9779
Address
Register Name
Hex Decimal Name
Function
Default
Sync Control Register
06
ꢀ:4
Sync Input Delay
See Multi-DAC Synchronization section for
details on using these registers to synchronize
multiple DACs.
0
06
3:0
Input Sync Pulse Timing Error
Tolerance
0
0ꢀ
0ꢀ
0ꢀ
0ꢀ
ꢀ
6
5
4:0
Sync Receiver Enable
Sync Driver Enable
Sync Triggering Edge
Sync_I to Input Data
Sampling Clock Offset
0
0
0
0
PLL Control
08
08
09
ꢀ:2
1:0
ꢀ
PLL Band Select
VCO AGC Gain Control
PLL Enable
VCO frequency range vs. PLL band select value
(see Table 1ꢀ)
Lower number (low gain) is generally better for
performance.
0: PLL off, DAC rate clock supplied by outside
source
110011
11
0
1: PLL on, DAC rate clock synthesized internally
from external reference clock via PLL clock
multiplier
09
09
6:5
4:3
PLL VCO Divide Ratio
PLL Loop Divide Ratio
FVCO/fDAC
00 × 1
01 × 2
10 × 4
11 × 8
fDAC/fREF
00 × 2
01 × 4
10 × 8
11 × 16
09
0A
2:0
ꢀ:5
PLL Bias Setting
Always set to 111
111
Misc Control
PLL Control Voltage Range
000 to 111, proportional to voltage at PLL loop
filter output, readback only
0A
4:0
ꢀ:0
ꢀ
PLL Loop Bandwidth
Adjustment
See PLL Loop Filter Bandwidth section for details
I DAC Control Register 0B
I DAC Gain Adjustment
(ꢀ:0) LSB slice of 10-bit gain setting word
for I DAC
0: I DAC on
1: I DAC off
0: I DAC on
1: I DAC off
(9:8) MSB slice of 10-bit gain setting word
for I DAC
11111001
0C
0C
0C
I DAC Sleep
0
6
I DAC Power-Down
0
1:0
ꢀ:0
ꢀ
I DAC Gain Adjustment
Aux DAC1 Gain Adjustment
Aux DAC1 Sign
01
Aux DAC1 Control
Register
0D
0E
0E
0E
0E
(ꢀ:0) LSB slice of 10-bit gain setting word for Aux 00000000
DAC1
0: Positive
1: Negative
0: Source
1: Sink
0: Aux DAC1 on
1: Aux DAC1 off
(9:8) MSB slice of 10 bit gain setting word for Aux 00
DAC1
6
Aux DAC1 Current Direction
Aux DAC1 Power-Down
Aux DAC1 Gain Adjustment
0
0
5
1:0
Rev. 0 | Page 2ꢀ of 56
AD9776/AD9778/AD9779
Address
Register Name
Hex Decimal Name
Function
Default
Q DAC Control
Register
0F
10
10
10
11
12
12
12
12
ꢀ:0
Q DAC Gain Adjustment
(ꢀ:0) LSB slice of 10-bit gain setting word for Q
DAC
0: Q DAC on
1: Q DAC off
0: Q DAC on
1: Q DAC off
(9:8) MSB slice of 10-bit gain setting word for Q
DAC
11111001
ꢀ
Q DAC Sleep
0
0
6
Q DAC Power-Down
1:0
ꢀ:0
ꢀ
Q DAC Gain Adjustment
Aux DAC2 Gain Adjustment
Aux DAC2 Sign
Aux DAC2 Control
Register
(ꢀ:0) LSB slice of 10-bit gain setting word for Aux 00000000
DAC2
0: Positive
1: Negative
0: Source
1: Sink
0: Aux DAC 2 on
1: Aux DAC 2 off
6
Aux DAC2 Current Direction
Aux DAC2 Power-Down
Aux DAC2 Gain Adjustment
0
5
0
1:0
(9:8) MSB slice of 10-bit gain setting word for
Aux DAC2
00
Interrupt Register
19
19
19
19
19
19
19
ꢀ
6
5
3
2
1
0
0
0
0
0
0
0
0
Sync Delay IRQ
Readback , must write 0 to clear
Sync Delay IRQ Enable
Internal Sync Loopback
Rev. 0 | Page 28 of 56
AD9776/AD9778/AD9779
INTERPOLATION FILTER ARCHITECTURE
Table 14. Halfband Filter 3
The AD9776/AD9778/AD9779 can provide up to 8× interpola-
tion or disable the interpolation filters entirely. It is important
to note that the input signal should be backed off by approxima-
tely 0.01 dB from full scale to avoid overflowing the interpola-
tion filters. The coefficients of the low-pass filters and the
inverse sinc filter are given in Table 12, Table 13, Table 14,and
Table 15. Spectral plots for the filter responses are shown in
Figure 54, Figure 55, and Figure 56.
Lower Coefficient
Upper Coefficient
Integer Value
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(ꢀ)
H(8)
H(15)
H(14)
H(13)
H(12)
H(11)
H(10)
H(9)
–39
0
2ꢀ3
0
–1102
0
4964
8192
Table 12. Halfband Filter 1
Lower Coefficient
Upper Coefficient
H(55)
H(54)
H(53)
H(52)
H(51)
H(50)
H(49)
H(48)
H(4ꢀ)
H(46)
H(45)
H(44)
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(3ꢀ)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
Integer Value
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(ꢀ)
H(8)
–4
0
13
0
–34
0
ꢀ2
0
–138
0
245
0
–408
0
650
0
–1003
0
1521
0
–2315
0
36ꢀ1
0
–6642
0
Table 15. Inverse Sinc Filter
Lower Coefficient
Upper Coefficient
Integer Value
H(1)
H(2)
H(3)
H(4)
H(5)
H(9)
H(8)
H(ꢀ)
H(6)
2
–4
10
–35
401
H(9)
10
0
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(1ꢀ)
H(18)
H(19)
H(20)
H(21)
H(22)
H(23)
H(24)
H(25)
H(26)
H(2ꢀ)
H(28)
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 54. 2× Interpolation, Low-Pass Response to 4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
10
20ꢀ55
32ꢀ68
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
Table 13. Halfband Filter 2
Lower Coefficient
Upper Coefficient
Integer Value
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(ꢀ)
H(8)
H(9)
H(10)
H(11)
H(12)
H(23)
H(22)
H(21)
H(20)
H(19)
H(18)
H(1ꢀ)
H(16)
H(15)
H(14)
H(13)
–2
0
1ꢀ
0
–ꢀ5
0
238
0
–660
0
2530
4096
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 55. 4× Interpolation, Low-Pass Response to 4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
Rev. 0 | Page 29 of 56
AD9776/AD9778/AD9779
10
10
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–4
–3
–2
–1
0
1
2
3
4
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
fOUT (× Input Data Rate)
Figure 56. 8× Interpolation, Low-Pass Response to 4× Input Data Rate
(Dotted Lines Indicate 1 dB Roll-Off)
Figure 59. Interpolation/Modulation Combination of –3fDAC/8 Filter
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
With the interpolation filter and modulator combined, the
incoming signal can be placed anywhere within the Nyquist
region of the DAC output sample rate. When the input signal is
complex, this architecture allows modulation of the input signal
to positive or negative Nyquist regions (see Table 16).
The Nyquist regions of up to 4× the input data rate can be seen
in Figure 57.
–8 –7 –6 –5 –4 –3 –2 –1
1
2
3
4
5
6
7
8
–4×
–3×
–2×
–1×
DC
1×
2×
3×
4×
–4
–3
–2
–1
0
1
2
3
4
Figure 57. Nyquist Zones
fOUT (× Input Data Rate)
Figure 54, Figure 55, and Figure 56 show the low-pass response
of the digital filters with no modulation used. By turning on the
modulation feature, the response of the digital filters can be
tuned to anywhere within the DAC bandwidth. As an example,
Figure 58 to Figure 64 show the nonshifted mode filter res-
ponses (refer to Table 16 for shifted/nonshifted mode filter
responses).
Figure 60. Interpolation/Modulation Combination of –2fDAC/8 Filter
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 61. Interpolation/Modulation Combination of –1fDAC/8 Filter
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 58. Interpolation/Modulation Combination of 4fDAC/8 Filter
Rev. 0 | Page 30 of 56
AD9776/AD9778/AD9779
10
0
Shifted mode filter responses allow the pass band to be centered
around 0.5, 1.5, 2.5, and 3.5 fDATA. Switching to the shifted
mode response does not modulate the signal. Instead, the pass
band is simply shifted. For example, picture the response shown
in Figure 64 and assume the signal in-band is a complex signal
over the bandwidth 3.2 fDATA to 3.3 fDATA. If the even mode filter
response is then selected, the pass band becomes centered at
3.5 fDATA. However, the signal remains at the same place in the
spectrum. The shifted mode capability allows the filter pass
band to be placed anywhere in the DAC Nyquist bandwidth.
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
The AD9776/AD9778/AD9779 are dual DACs with internal
complex modulators built into the interpolating filter response.
In dual channel mode, the devices expect the real and the
imaginary components of a complex signal at Digital Input
Port 1 and Digital Input Port 2 (I and Q respectively). The DAC
outputs then represent the real and imaginary components of
the input signal, modulated by the complex carrier fDAC/2,
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 62. Interpolation/Modulation Combination of fDAC/8 Filter
10
0
f
DAC/4, or fDAC/8.
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
With Reg. 2, Bit 6 set, the device accepts interleaved data on
Port 1 in the I, Q, I, Q ... sequence. Note that in interleaved
mode, the channel data rate at the beginning of the I and the Q
data paths are now half the input data rate because of the inter-
leaving. The maximum input data rate is still subject to the
maximum specification of the device. This limits the synthesis
bandwidth available at the input in interleaved mode.
With Reg. 0x02, Bit 5 (real mode) set, the Q channel and the
internal I and Q digital modulation are turned off. The output
spectrum at the I DAC then represents the signal at Digital
Input Port 1, interpolated by 1×, 2×, 4×, or 8×.
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 63. Interpolation/Modulation Combination of
2fDAC/8 Filter in Odd Mode
The general recommendation is that if the desired signal is
within 0.4 × fDATA, the odd filter mode should be used. Outside
of this, the even filter mode should be used. In any situation, the
10
0
total bandwidth of the signal should be less than 0.8 × fDATA
.
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–4
–3
–2
–1
0
1
2
3
4
fOUT (× Input Data Rate)
Figure 64. Interpolation/Modulation Combination of
3fDAC/8 Filter in Odd Mode
Rev. 0 | Page 31 of 56
AD9776/AD9778/AD9779
Table 16. Interpolation Filter Modes, (Reg. 0x01, Bits <5:2>)
Nyquist
Zone
Pass
Filter
Mode
<5:2>
Interpolation
Factor <7:6>
Modulation
DC
Band
F_Low1
–0.05
0.0125
0.0ꢀ5
0.13ꢀ5
0.2
0.2625
0.325
0.38ꢀ5
–0.55
–0.48ꢀ5
–0.425
–0.3625
–0.3
–0.23ꢀ5
–0.1ꢀ5
–0.1125
–0.1
0.025
0.15
0.2ꢀ5
–0.6
–0.4ꢀ5
–0.35
–0.225
–0.2
0.05
–0.ꢀ
–0.45
Center1
0
0.0625
0.125
0.18ꢀ5
0.25
0.3125
0.3ꢀ5
0.43ꢀ5
–0.5
–0.43ꢀ5
–0.3ꢀ5
–0.3125
–0.25
–0.18ꢀ5
–0.125
–0.0625
0
0.125
0.25
0.3ꢀ5
–0.5
–0.3ꢀ5
–0.25
–0.125
0
F_High1
+0.05
0.1125
0.1ꢀ5
0.23ꢀ5
0.3
0.3625
0.425
0.48ꢀ5
–0.45
–0.38ꢀ5
–0.343
–0.2625
–0.2
–0.13ꢀ5
–0.0ꢀ5
–0.0125
+0.1
0.225
0.35
0.4ꢀ5
–0.4
–0.2ꢀ5
–0.15
–0.025
0.2
0.45
–0.3
–0.05
Comments
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
4
4
4
4
4
4
4
4
2
2
2
2
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x0ꢀ
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x0ꢀ
0x00
0x01
0x02
0x03
1
In 8× interpolation; BW (min)
= 0.03ꢀ5 × fDAC BW (max) =
0.1 × fDAC
DC shifted
F/8
F/8 shifted
F/4
F/4 shifted
3F/8
3F/8 shifted
F/2
F/2 shifted
–3F/8
–3F/8 shifted
–F/4
–F/4 shifted
–F/8
–F/8 shifted
DC
DC shifted
F/4
F/4 shifted
F/2
F/2 shifted
–F/4
–F/4 shifted
DC
2
3
4
5
6
ꢀ
8
–8
–ꢀ
–6
–5
–4
–3
–2
-1
1
In 4× interpolation; BW (min)
= 0.0ꢀ5 × fDAC BW (max) =
0.2 × fDAC
2
3
4
–4
–3
–2
–1
1
2
–2
–1
In 2× interpolation; BW (min)
= 0.15 × fDAC BW (max) =
0.4 × fDAC
DC shifted
F/2
F/2 shifted
0.25
–0.5
–0.25
1 Frequency normalized to fDAC
.
Rev. 0 | Page 32 of 56
AD9776/AD9778/AD9779
10
0
INTERPOLATION FILTER MINIMUM AND
MAXIMUM BANDWIDTH SPECIFICATIONS
–10
–20
–30
–40
–50
–60
–70
–80
The AD977x uses a novel interpolation filter architecture that
allows DAC IF frequencies to be generated anywhere in the
spectrum. Figure 65 shows the traditional choice of DAC IF
output bandwidth placement. Note that there are no possible
filter modes in which the carrier can be placed near 0.5 × fDATA
1.5 × fDATA, 2.5 × fDATA, etc.
,
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–4
–3
–2
–1
fOUT (× Input Data Rate),
ASSUMING 8× INTERPOLATION
0
1
2
3
4
Figure 67. Shifted Bandwidths Accessible with the Filter Architecture
With this filter architecture, a signal placed anywhere in the
spectrum is possible. However, the signal bandwidth is limited
by the input sample rate of the DAC and the specific placement
of the carrier in the spectrum. The bandwidth restriction
resulting from the combination of filter response and input
sample rate is often referred to as the synthesis bandwidth, since
this is the largest bandwidth that the DAC can synthesize.
–4
–3
–2
–1
fOUT (× Input Data Rate),
ASSUMING 8× INTERPOLATION
0
1
2
3
4
The maximum bandwidth condition exists if the carrier is
placed directly in the center of one of the filter pass bands. In
this case, the total 0.1 dB bandwidth of the interpolation filters
is equal to 0.8 × fDATA. As Table 16 shows, the synthesis band-
width as a fraction of DAC output sample rate drops by a factor
of 2 for every doubling of interpolation rate. The minimum
bandwidth condition exists, for example, if a carrier is placed at
0.25 × fDATA. In this situation, if the nonshifted filter response is
Figure 65. Traditional Bandwidth Options for TxDAC Output IF
The filter architecture not only allows the interpolation filter
pass bands to be centered in the middle of the input Nyquist
zones (as explained in this section), but also allows the
possibility of a 3 × fDAC/8 modulation mode. With all of these
filter combinations, a carrier of given bandwidth can be placed
anywhere in the spectrum and fall into a possible pass band of
the interpolation filters. The possible bandwidths accessible
with the filter architecture are shown in Figure 66 and
Figure 67. Note that the shifted and nonshifted filter modes
are all accessible by programming the filter mode for the
particular interpolation rate.
enabled, the high end of the filter response cuts off at 0.4 × fDATA
,
thus limiting the high end of the signal bandwidth. If the shifted
filter response is enabled instead, then the low end of the filter
response cuts off at 0.1 × fDATA, thus limiting the low end of the
signal bandwidth. The minimum bandwidth specification that
applies for a carrier at 0.25 × fDATA is therefore 0.3 × fDATA. The
minimum bandwidth behavior is repeated over the spectrum
for carriers placed at ( n 0.25) × fDATA, where n is any integer.
10
0
–10
–20
–30
–40
–50
–60
–70
–80
DRIVING THE DACCLK INPUT
The DACCLK input requires a low jitter differential drive
signal. It is a PMOS input differential pair powered from the
1.8 V supply, therefore,
it is important to maintain the specified 400 mV input
common-mode voltage. Each input pin can safely swing from
200 mV p-p to 1 V p-p about the 400 mV common-mode
voltage. While these input levels are not directly LVDS-
compatible, DACCLK can be driven by an offset ac-coupled
LVDS signal, as shown in Figure 68.
–4
–3
–2
–1
fOUT (× Input Data Rate),
ASSUMING 8× INTERPOLATION
0
1
2
3
4
Figure 66. Nonshifted Bandwidths Accessible with the Filter Architecture
Rev. 0 | Page 33 of 56
AD9776/AD9778/AD9779
0.1μF
lation rate of the DAC, and the ratio N3/N2 determines the
ratio of reference clock/input data rate. The VCO runs
optimally over the range of 1.0 GHz to 2.0 GHz, so that N1
keeps the speed of the VCO within this range, although the
DAC sample rate can be lower. The loop filter components
are entirely internal and no external compensation is
necessary.
LVDS_P_IN
CLK+
50Ω
50Ω
V
= 400mV
CM
LVDS_N_IN
CLK–
0.1μF
Figure 68. LVDS DACCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to DACCLK, as shown in Figure 68. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS to LVDS translator, then ac-coupled, as
described in this section. Alternatively, it can be transformer-
coupled and clamped, as shown in Figure 69.
2. PLL Disabled (Reg. 0x09, Bit 7 = 0). The PLL enable switch
shown in Figure 71 is connected to the reference clock
input. The differential reference clock input is the same as
the DAC output sample rate. N3 determines the
interpolation rate.
0x0A (7:5)
ADC
PLL CONTROL
0.1μF
VOLTAGE RANGE
50Ω
0x0A (4:0)
LOOP FILTER
BANDWIDTH
TTL OR CMOS
CLK INPUT
CLK+
0x08 (7:2)
VCO RANGE
REFERENCE CLOCK
(Pins 5 and 6)
INTERNAL
LOOP
FILTER
PHASE
DETECTION
VCO
CLK–
50Ω
BAV99ZXCT
HIGH SPEED
DUAL DIODE
÷N
÷N
1
2
0x09 (4:3)
PLL LOOP
DIVIDE RATIO DIVIDE RATIO
0x09 (6:5)
PLL VCO
DAC
INTERPOLATION
RATE
V
= 400mV
CM
Figure 69. TTL or CMOS DACCLK Drive Circuit
÷N
DATACLK OUT (Pin 37)
3
A simple bias network for generating VCM is shown in
Figure 70. It is important to use CVDD18 and CGND for the
clock bias circuit. Any noise or other signal that is coupled onto
the clock is multiplied by the DAC digital input signal and can
degrade the DAC’s performance.
0x01 (7:6)
0x09 (7)
PLL ENABLE
INTERNAL DAC SAMPLE
RATE CLOCK
Figure 71. Internal Clock Architecture
Table 17. VCO Frequency Range vs. PLL Band Select Value
Typical PLL Lock Ranges
V
= 400mV
CM
CVDD18
1kΩ
VCO Frequency Range in MHz
1nF
Typ at 25°C
fLOW fHIGH
Auto Mode
21ꢀ0
Typ over Temp
PLL Band
Select
0.1μF
1nF
287Ω
fLOW
fHIGH
CGND
111111 (63)
111110 (62)
111101 (61)
111100 (60)
111011 (59)
111010 58)
111001 (5ꢀ)
111000 (56)
110111 (55)
110110 (54)
110101 (53)
110100 (52)
110011 (51)
110010 (50)
110001 (49)
110000 (48)
101111 (4ꢀ)
101110 (46)
101101 (45)
101100 (44)
Figure 70. DACCLK VCM Generator Circuit
2056
2002
1982
1964
194ꢀ
192ꢀ
190ꢀ
1894
18ꢀ2
1852
1841
1816
1ꢀ96
1ꢀ89
1ꢀ64
1ꢀ46
1ꢀ38
1ꢀ14
1ꢀ00
2105
2048
2029
2010
1992
19ꢀ1
1951
1936
1913
1892
1881
1855
1835
1828
1803
1ꢀ84
1ꢀꢀ6
1ꢀ52
1ꢀ3ꢀ
2138
2081
2061
2043
2026
2006
1986
19ꢀ2
1952
1931
1920
1895
18ꢀ4
186ꢀ
1844
1826
1815
1ꢀ94
1ꢀꢀ9
Internal PLL Clock Multiplier/Clock Distribution
2113
2093
20ꢀ5
205ꢀ
203ꢀ
2016
2003
1981
1960
1948
1923
1903
1895
18ꢀ1
1853
1842
1820
1804
The internal clock structure on the devices allows the user to
drive the differential clock inputs with a clock at 1× or an
integer multiple of the input data rate or at the DAC output
sample rate. An internal PLL provides input clock multipli-
cation and provides all the internal clocks required for the
interpolation filters and data synchronization.
The internal clock architecture is shown in Figure 71. The
reference clock is the differential clock at Pins 5 and 6. This
clock input can be run differentially or singled-ended by
driving Pin 5 with a clock signal and biasing Pin 6 to the
midswing point of the signal at Pin 5. The clock architecture
can be run in the following configurations:
1. PLL Enabled (Reg. 0x09, Bit 7 = 1). The PLL enable switch
shown in Figure 71 is connected to the junction of the N1
dividers (PLL VCO divide ratio) and N2 dividers (PLL
loop divide ratio). Divider N3 determines the interpo-
Rev. 0 | Page 34 of 56
AD9776/AD9778/AD9779
VCO Frequency Ranges
Typical PLL Lock Ranges
VCO Frequency Range in MHz
Because the PLL band covers greater than a 2× frequency range,
there can be two options for the PLL band select: one at the low
end of the range and one at the high end of the range. Under
these conditions, the VCO phase noise is optimal when the user
selects the band select value corresponding to the high end of
the frequency range. Figure 72 shows how the VCO bandwidth
and the optimal VCO frequency varies with the band select
value.
Typ at 25°C
Typ over Temp
PLL Band
Select
fLOW
fHIGH
fLOW
fHIGH
101011 (43)
101010 (42)
101001 (41)
101000 (40)
100111 (39)
100110 (38)
100101 (3ꢀ)
100100 (36)
100011 (35)
100010 (34)
100001 (33)
100000 (32)
011111 (31)
011110 (30)
011101 (29)
011100 (28)
011011 (2ꢀ)
011010 (26)
011001 (25)
011000 (24)
010111 (23)
010110 (22)
010101 (21)
010100 (20)
010011 (19)
010010 (18)
010001 (1ꢀ)
010000 (16)
001111 (15)
001110 (14)
001101 (13)
001100 (12)
001011 (11)
001010 (10)
001001 (9)
001000 (8)
000111 (ꢀ)
000110 (6)
000101 (5)
000100 (4)
000011 (3)
000010 (2)
000001 (1)
000000 (0)
1689
165ꢀ
1641
1610
159ꢀ
1568
1553
1525
1511
1484
14ꢀ0
1441
1429
1403
1390
1362
1352
1325
1314
1290
12ꢀ6
1253
1239
1183
1204
1151
11ꢀ1
1148
113ꢀ
1116
1106
1086
10ꢀ5
1055
1045
102ꢀ
1016
998
1ꢀ90
1ꢀ5ꢀ
1ꢀ38
1ꢀ0ꢀ
1689
1661
1641
1613
1595
15ꢀ0
1552
1525
1509
1485
1469
1443
1429
1405
1390
1368
1351
1331
1313
1255
12ꢀ5
1221
1240
1218
1204
1184
11ꢀ1
1152
1138
1119
110ꢀ
1090
10ꢀ6
1059
1046
101ꢀ
989
1ꢀ26
1695
16ꢀ9
1649
1635
160ꢀ
1592
1562
1548
1519
1506
14ꢀ4
1463
1433
1422
1391
1380
1352
1340
1315
1302
12ꢀꢀ
1264
1205
122ꢀ
11ꢀ2
1193
11ꢀ0
1159
113ꢀ
112ꢀ
1106
1095
10ꢀ5
1065
104ꢀ
1034
1016
1005
9ꢀꢀ
1ꢀ64
1ꢀ34
1ꢀ14
1684
1666
1639
161ꢀ
1592
15ꢀ2
1549
1528
1504
148ꢀ
1464
144ꢀ
1423
140ꢀ
1385
1369
1350
1332
1313
1295
1240
1259
120ꢀ
1224
1204
1189
11ꢀ0
115ꢀ
1138
1124
1106
1093
10ꢀ6
1062
1046
1032
1004
9ꢀ6
PLL Loop Filter Bandwidth
The loop filter bandwidth of the PLL is programmed via SPI
Reg. 0x0A, Bits <4:0>. Changing these values switches
capacitors on the internal loop filter. No external loop filter
components are required. This loop filter has a pole at 0 (P1),
and then a zero- (Z1) pole (P2) combination. Z1 and P2 occur
within a decade of each other. The location of the zero pole is
determined by Bit <4:0>. For a setting of 00000, the zero pole
occurs near 10 MHz. By setting Bits <4:0> to 11111, the Z1/P2
combination can be lowered to approximately 1 MHz. The
relationship between Bits <4:0> and the position of the zero
pole between 1 MHz and 10 MHz is linear. The internal compo-
nents are not low tolerance, however, and can drift by as much
as 30ꢁ.
For optimal performance, the bandwidth adjustment
(Reg. 0x0A, Bits <4:0>) should be set to 11111 for all
operating modes with PLL enabled. The PLL bias settings
(Reg. 0x09, Bits <2:0>) should be set to 111. The PLL control
voltage (Reg. 0x0A, Bits <7:5>) is read back and is proportional
to the dc voltage at the internal loop filter output. With the PLL
bias settings given in this section, the readback from the PLL
control voltage should typically be 010 or possibly 001 or 011.
Anything outside of this range indicates that the PLL is not
operating correctly.
60
56
52
48
44
40
36
32
28
24
20
16
12
8
98ꢀ
960
933
949
908
883
859
962
936
911
923
898
8ꢀ3
950
925
899
4
0
F
(MHz)
VCO
Figure 72. Typical PLL Band Select vs. Frequency at 25°C
Rev. 0 | Page 35 of 56
AD9776/AD9778/AD9779
35
30
25
20
15
10
5
60
56
52
48
44
40
36
32
28
24
20
16
12
8
4
0
0
0
200
400
600
800
1000
DAC GAIN CODE
F
(MHz)
VCO
Figure 75. IFS vs. DAC Gain Code
Figure 73. Typical PLL Band Select vs. Frequency over Temperature
Auxiliary DACS
The AD977x has an autosearch feature that can be used to
determine the optimal settings for the PLL. To enable the
autosearch mode, set Reg. 0x08, Bits <7:2> to 11111b, and read
back the value from Reg. 0x08, Bits <7:2>. Autosearch mode is
intended to find the optimal PLL settings only, after which the
same settings should be applied in manual mode. It is not
recommended that the PLL be set to autosearch mode during
regular operation.
Two auxiliary DACs are provided on the AD977x. The full-scale
output current on these DACs is derived from the 1.2 V band
gap reference and external resistor. The gain scale from the
reference amplifier current IREFERENCE to the auxiliary DAC refer-
ence current is 16.67 with the auxiliary DAC gain set to full
scale (10-bit values, SPI Reg. 0x0C, 0x0D, 0x10, and 0x11), this
gives a full-scale current of approximately 2 mA for auxiliary
DAC1 and auxiliary DAC2. The auxiliary DAC outputs are not
differential. Only one side of the auxiliary DAC (P or N) is
active at one time. The inactive side goes into a high impedance
state (>100 kΩ). In addition, the P or N outputs can act as
current sources or sinks. The control of the P and N side
for both auxiliary DACs is via Reg. 0x0E and 0x10,
FULL-SCALE CURRENT GENERATION
Internal Reference
Full-scale current on the I DAC and Q DAC can be set from
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is
used to set up a current in an external resistor connected to
I120 (Pin 75). A simplified block diagram of the reference
circuitry is shown in Figure 74. The recommended value for the
external resistor is 10 kΩ, which sets up an IREFERENCE in the
resistor of 120 μA, which in turn provides a DAC output full-
scale current of 20 mA. Because the gain error is a linear
function of this resistor, a high precision resistor improves gain
matching to the internal matching specification of the devices.
Internal current mirrors provide a current-gain scaling, where
I DAC or Q DAC gain is a 10-bit word in the SPI port register
(Reg. 0x0A, 0x0B, 0x0E, and 0x0F). The default value for the
DAC gain registers gives an IFS of approximately 20 mA, where
Bits <7:6>. When sourcing current, the output compliance
voltage is 0 V to 1.6 V; when sinking current, the output
compliance voltage is 0.8 V to 1.6 V.
The auxiliary DACs can be used for local oscillator (LO) cancel-
lation when the DAC output is followed by a quadrature modu-
lator. A typical DAC-to-quadrature modulator interface is shown
in Figure 76. Often, the input common-mode voltage for the
modulator is much higher than the output compliance range of
the DAC, so that ac coupling is necessary. If the required com-
mon-mode input voltage on the quadrature modulator matches
that of the DAC, then the ac coupling capacitors can be removed.
The input referred dc offset voltage of the quadrature modulator
(and the DAC output offset voltage mismatch) can result in LO
feedthrough on the modulator output, thus degrading system
performance. If the configuration of Figure 76 is used, the auxi-
liary DACs can be used to compensate for this dc offset, thus
reducing LO feedthrough. A low-pass or band-pass filter is
recommended when spurious signals from the DAC (distortion
and DAC images) at the quadrature modulator inputs can affect
the system performance. This filter should be placed at the
quadrature modulator inputs.
I
FS is equal to
1.2V
R
27
12
6
⎛
⎜
⎞
⎛
⎜
⎝
⎞
⎠
×
+
×DAC gain ×32
⎟
⎟
1024
⎝
⎠
AD9779
I DAC GAIN
I DAC
1.2V BAND GAP
VREF
I120
DAC FULL-SCALE
REFERENCE
CURRENT
CURRENT
SCALING
0.1μF
10kΩ
Q DAC
Q DAC GAIN
Figure 74. Reference Circuitry
Rev. 0 | Page 36 of 56
AD9776/AD9778/AD9779
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
AUX
8× INTERPOLATION, fDAC/4,
DAC1
f
DAC/2
,
,
4
×
INTERPOLATION,
f
f
DAC/4,
DAC/2
MODULATION OFF
fDAC/8
,
MODULATION OFF
AUX1_P
AUX1_N
8
×
INTERPOLATION,
QUAD MOD
4
×
INTERPOLATION,
ZERO STUFFING
ZERO STUFFING
I INPUTS
2×
INTERPOLATION,
IOUT1_P
IOUT1_N
ZERO STUFFING
IDAC
1×
INTERPOLATION,
ZERO STUFFING
QUAD MOD
Q INPUTS
1× INTERPOLATION
IOUT2_P
IOUT2_N
2×
INTERPOLATION,
fDAC/2,
QDAC
MODULATION OFF
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
Figure 78. Power Dissipation, Dual DAC Mode
AUX2_P
AUX2_N
AUX
DAC2
0.4
0.3
0.2
0.1
0
Figure 76. Typical Use of Auxiliary DACs
8× INTERPOLATION
4× INTERPOLATION
POWER DISSIPATION
Figure 77 to Figure 85 show the power dissipation of the 1.8 V
and 3.3 V digital and clock supplies in single DAC and dual
DAC modes. In addition to this, the power dissipation/current
of the 3.3 V supply (mode and speed independent) in single
DAC mode is 102 mW/31 mA. In dual DAC mode, this is
182 mW/51 mA.
2
1
×
×
INTERPOLATION
INTERPOLATION
0.7
8×
INTERPOLATION
0.6
0.5
0.4
0.3
0.2
0.1
0
4
×
INTERPOLATION
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
4×
INTERPOLATION,
8
×
INTERPOLATION,
ZERO STUFFING
ZERO STUFFING
Figure 79. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode,
Does Not Include Zero Stuffing
2×
INTERPOLATION,
ZERO STUFFING
0.08
2
×
INTERPOLATION
1×
INTERPOLATION,
ZERO STUFFING
0.06
1× INTERPOLATION
8× INTERPOLATION
4× INTERPOLATION
0.04
0.02
0
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
2× INTERPOLATION
Figure 77. Power Dissipation, I Data Only, Single DAC Mode
1× INTERPOLATION
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
Figure 80. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode,
Includes Modulation Modes, Does Not Include Zero Stuffing
Rev. 0 | Page 3ꢀ of 56
AD9776/AD9778/AD9779
0.075
0.075
0.050
0.025
0
ALL INTERPOLATION MODES
ALL INTERPOLATION MODES
0.050
0.025
0
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
Figure 81. Digital 3.3 V Supply, I Data Only, Real Mode, Includes Modulation
Modes and Zero Stuffing
Figure 84. Digital 3.3 V Supply, I and Q Data, Dual DAC Mode
0.16
0.8
8
×
INTERPOLATION, f
/8,
/4,
/2,
DAC
DAC
DAC
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
f
f
0.7
0.6
NO MODULATION
4× INTERPOLATION
0.5
0.4
0.3
0.2
0.1
0
2× INTERPOLATION
1
×
INTERPOLATION,
NO MODULATION
0
200
400
600
800
1000
1200
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
fDAC (MSPS)
Figure 85. Power Dissipation of Inverse Sinc Filter
Figure 82. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC
Mode, Does Not Include Zero Stuffing
POWER-DOWN AND SLEEP MODES
The AD977x has a variety of power-down modes, so that the
digital engine, main TxDACs, or auxiliary DACs can be
powered down individually or together. Via the SPI port, the
main TxDACs can be placed in sleep or power-down mode. In
sleep mode, the TxDAC output is turned off, thus reducing
power dissipation. The reference remains powered on, however,
so that recovery from sleep mode is very fast. With the power-
down mode bit set (Reg. 0x00, Bit 4), all analog and digital
circuitry, including the reference, is powered down. The SPI
port remains active in this mode. This mode offers more
substantial power savings than sleep mode, but the turn on
time is much longer. The auxiliary DACs also have the
capability to be programmed into sleep mode via the SPI port.
0.125
8
×
INTERPOLATION, f
/8,
/4,
/2,
DAC
DAC
DAC
f
f
NO MODULATION
0.100
0.075
0.050
0.025
0
4× INTERPOLATION
2× INTERPOLATION
1
×
INTERPOLATION,
NO MODULATION
0
25
50
75
100 125 150 175 200 225 250
fDATA (MSPS)
Figure 83. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC
Mode, Does Not Include Zero Stuffing
Rev. 0 | Page 38 of 56
AD9776/AD9778/AD9779
The auto power-down enable bit (Reg. 0x00, Bit 3) controls the
power-down function for the digital section of the devices. The
auto power-down function works in conjunction with the
TXENABLE pin (Pin 39) according to the following:
INTERLEAVED
INPUT DATA
I1
Q1
I2
Q2
TxENABLE
TxENABLE CAN REMAIN
HIGH OR TOGGLE FOR
I/Q SYNCHRONIZATION
FLUSHING
INTERPOLATION
FILTERS
POWER
DOWN DIGITAL
SECTION
TXENABLE (Pin 39) =
0: autopower-down enable =
Figure 86. TxEnable Function
0: Flush data path with 0s
1: Flush data for multiple DACCLK cycles; then
automatically place the digital engine in power-down
state. DACs, reference, and SPI port are not affected.
The TxEnable function can be inverted by changing the status
of Reg. 0x02, Bit 1. The other bit that controls IQ ordering is the
Q-first bit (Reg. 0x02, Bit 0). With the Q-first bit reset to the
default of 0, the IQ pairing that is latched is the I1Q1, I2Q2, etc.
With IQ first set to 1, the first I data is discarded and the pairing
is I2Q1, I3Q2, etc. Note that with IQ-first set, the I data is still
routed to the internal I channel, the Q data is routed to the
internal Q channel, and only the pairing changes.
or TXENABLE (Pin 39) =
1: Normal operation
If the TxEnable invert bit (Reg. 0x02, Bit 1) is set, the function
of this TXENABLE pin is inverted.
INTERLEAVED DATA MODE
TIMING INFORMATION
The TxEnable bit is dual function. In dual port mode, it is
simply used to power down the digital section of the devices. In
interleaved mode, the IQ data stream is synchronized to
TxEnable. Therefore, to achieve IQ synchronization, TxEnable
should be held low until an I data word is present at the inputs
to Data Port 1. If a DATACLK rising edge occurs while
TxEnable is at a high logic level, IQ data becomes synchronized
to the DATACLK output. TxEnable can remain high and
the input IQ data remains synchronized. To be backwards-
compatible with previous DACs from ADI, such as the AD9777
and AD9786, the user can also toggle TxEnable once during
each data input cycle, thus continually updating the synchroni-
zation. If TxEnable is brought low and held low for multiple
DACCLK cycles, then the devices flush the data in the interpo-
lation filters, and shut down the digital engine after the filters
are flushed. The amount of DACCLK cycles it takes to go into
this power-down mode is then a function of the length of the
equivalent 2×, 4×, or 8× interpolation filter. The timing of
TxEnable, I/Q select, filter flush, and digital power-down are
shown in Figure 86.
Figure 87 to Figure 89 show some of the various timing
possibilities when the PLL is enabled. The combination of the
settings of N2 and N3 means that the reference clock frequency
can be a multiple of the actual input data rate. Figure 87 to
Figure 89 show, respectively, what the timing looks like when
N2/N3 = 1 and 2.
In interleaved mode, set-up and hold times of DATACLK out to
data in are the same as those shown in Figure 87 to Figure 89. It
is recommended that any toggling of TxEnable occurs concur-
rently with the digital data input updating. In this way, timing
margins between DATACLK, TxEnable, and digital input data
are optimized.
Figure 89 shows the timing specifications when PLL is disabled.
The reference clock is at the DAC output sample rate. In the
example shown in Figure 89, if PLL is disabled, the interpola-
tion is 4×. The set-up and hold time for the input data are with
respect to the rising edge of DATACLK out. Note that if
Reg. 0x02, Bit 2 is set, DATACLK out is inverted so the latching
clock edge becomes DATACLK out falling edge.
REFERENCE CLOCK
tD
DATACLK OUT
tS
tH
INPUT DATA
Figure 87. Timing Specifications, PLL Enabled, Reference Clock = 1× Input Sample Rate1
Rev. 0 | Page 39 of 56
AD9776/AD9778/AD9779
REFERENCE CLOCK
tD
DATACLK OUT
tS
tH
INPUT DATA
Figure 88. Timing Specifications, PLL Enabled, Reference Clock = 2× Input Sample Rate1
REFERENCE CLOCK
tD
DATACLK OUT
INPUT DATA
tS
tH
tS = 3ns MIN
tH = 0.78ns MIN
tD = 5.0ns TYP
(DATACLK DELAY DISABLED)
Figure 89. Timing Specifications, PLL Disabled, 4× Interpolation
1 For an in-depth description of how TxDAC timing specifications are specified, please read Analog Devices, application note ANꢀ48, “Set-up and Hold Measurements in
High Speed CMOS Input DACs.”
TEK RUN: 5.00GS/s
SAMPLE
Using Data Delay to Meet Timing Requirements
To meet strict timing requirements at input data rates of up to
250 MSPS, the AD977x has a fine timing feature. Fine timing
adjustments can be made by programming values into the data
clock delay register (Reg. 0x04, Bit <7:4>). This register can be
used to add delay between the DACCLK in and the DATACLK
out. Figure 90 shows the default delay present when DATACLK
delay is disabled. The disable function bit is found in Reg. 0x02,
Bit 4. Figure 91 shows the delay present when DATACLK delay
is enabled and set to 0000. Figure 92 indicates the delay when
DATACLK delay is enabled and set to 1111. Note that the set-up
and hold times specified for data to DATACLK are defined for
DATACLK delay disabled.
Δ: 4.76nS
@: 35.52nS
2
1
CH1 1.00VΩ
CH2 500mVΩ
M2.00ns
CH1
420mV
TEK RUN: 5.00GS/s
SAMPLE
Figure 91. Delay from DACCLK to DATACLK Out with DATACLK Delay = 0000
Δ: 4.48nS
@: 40.28nS
TEK RUN: 5.00GS/s
SAMPLE
Δ: 7.84nS
@: 32.44nS
2
2
1
CH1 1.00VΩ
CH2 500mVΩ
M2.00ns
CH1
420mV
1
Figure 90. Delay from DACCLK to DATACLK with DATACLK Delay Disabled
CH1 1.00VΩ
CH2 500mVΩ
M2.00ns
CH1
420mV
Figure 92. Delay from DACCLK to DATACLK Out with DATACLK Delay = 1111
Rev. 0 | Page 40 of 56
AD9776/AD9778/AD9779
The difference between the minimum delay shown in Figure 91
and the maximum delay shown in Figure 92 is the range
programmable via the DATACLK delay register. The delay
(in absolute time) when programming DATACLK delay
between 0000 and 1111 is a linear extrapolation between these
two figures. The typical delays per increment over temperature
are shown in Table 18.
Manual Input Timing Correction
Correction of input timing can be achieved manually. The
correction function is controlled by Reg. 0x03, Bits <7:6>. The
function is programmed as shown in Table 21.
Table 21.
Reg. 0x03, Bits <7:6>
Function
00
01
10
11
Error check disabled
Reserved
Reserved
Table 18. Data Delay Line Typical Delays Over Temperature
Delays
–40°C
+25°C +85°C Unit
Delay Between Disabled and
Enabled
3ꢀ0
416
432
ps
Reserved
Necessary corrections can be made by adjusting DATACLK
delay and the DATACLK invert bit (Reg. 2, Bit 2). When doing
initial timing verification, the user should set input data timing
error tolerance (Reg. 0x03, Bit <3:0>) to 1111. DATACLK delay
can then be swept to find the range over which the timing is
valid. The final value for data delay should be the value that
corresponds to the middle of the valid timing range. If a valid
timing range is not found during this sweep, the user should
invert the DATACLK invert bit and repeat the process. If a valid
timing window is still not found, then the input data timing
error tolerance should be decremented by 1, and the procedure
should be repeated.
Average Delay per Increment
1ꢀ1
183
19ꢀ
ps
The frequency of DATACLK out depends on several program-
mable settings. Interpolation, zero stuffing, and interleaved/
dual port mode all have an effect on the DACCLK frequency.
The divisor function between DACCLK and DATACLK is equal
to the values shown in Table 19.
Table 19.
Interpolation Zero Stuffing
Input Mode
Dual port
Dual port
Dual port
Dual port
Interleaved
Interleaved
Interleaved
Interleaved
Dual port
Dual port
Dual port
Dual port
Interleaved
Interleaved
Interleaved
Interleaved
Divisor
1
2
4
8
1
2
4
8
1
2
4
8
1
2
4
8
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
1
2
4
8
Multi-DAC Synchronization
invalid
1
2
4
2
4
8
16
1
2
4
8
Sync Pulse Generation (Master Devices)
In applications where multiple devices are used and need to be
synchronized, the AD977x provides a flexible synchronization
engine. There are two options for multi-DAC synchronization.
In the first situation, one device can be used as a master and the
rest of the devices can be used as slaves. The second option is
that all devices operate as slaves. Both operations have the same
timing restrict-ions and there are no performance tradeoffs for
either mode. The following text describes the master mode. The
differential input clock drives the master device and the master
in turn generates SYNC_O+ and SYNC_O–. These two signals
use LVDS levels to generate a differential synchronization
signal, which in turn is used to synchronize all the slave devices.
SYNC_O+ and SYNC_O– must loop back to the sync inputs
(SYNC_I+ and SYNC_I–) of the master for multiple device
synchronization. The master mode is enabled by writing the
sync driver enable bit (Reg. 0x07, Bit 6) to a Logic 1. The
SYNC_O signal speed can be an integer divisor of the DACCLK
speed, according to Reg. 0x04, Bits <3:1>. Enabling a device in
slave mode is accomplished by writing the sync receiver enable
bit (Reg. 0x07, Bit 7) to a Logic 1. The timing of the DAC input
clock and the sync output signals on the master device are
shown in Figure 93.
In addition to this divisor function, DATACLK can be divided
by up to an additional factor of 4, according to the state of the
DATACLK divide register (Reg. 0x03, Bit <5:4>) (see Table 20).
Table 20.
Reg. 0x03, Bit <5:4>
Divider Ratio
00
01
10
11
1
2
4
1
The maximum divisor resulting from the combination of the
values in Table 19, and the DATACLK divide register is 32.
Rev. 0 | Page 41 of 56
AD9776/AD9778/AD9779
SYNC TRIGGERING EDGE
0x07 (5)
1–RISING EDGE
0–FALLING EDGE
SYNC OUT DELAY
0x04 (0); 0x05 (7:4)
(~180ps/increment)
DACCLK
LVDS DAC
SYNC OUT (/1)
LVDS DAC
SYNC OUT (/4)
LVDS DAC
SYNC OUT (/16)
SYNC OUT DIVISOR IS CONTROLLED BY:
0x04 (3:1)
000 fDAC/32
001 fDAC/16
010 fDAC/8
011 fDAC/4
100 fDAC/2
101 fDAC/1
110 UNDEFINED
111 UNDEFINED
Figure 93. DACCLK/Sync Output Timing
EQUALIZATION/FREQUENCY DIVISION
The sync output pulse must then be distributed from the master
to all the slave devices. This might require that the user imple-
ment circuitry outside of the device that splits the LVDS signal.
The splitter delivers the SYNC_O signal from the master to the
multiple slave device SYNC_I pins. A block diagram of this
implementation is shown in Figure 94. The equalization from
the CLK source and SYNC_O to the DACCLK and sync inputs
of the multiple AD977x devices is critical. For the multichip
synchronization to operate correctly at maximum specified
DAC sample rates, the DACCLK inputs must be phase aligned
to 100 ps. The SYNC_I inputs must also be phase aligned to
100 ps. At lower DAC sample rates, this timing alignment can
be relaxed.
CLOCK
SOURCE
SYNC_IN
SLAVE
DACCLK
DAC
EQUALIZATION
SYNC_IN
DACCLK
SLAVE
DAC
SYNC_IN
DACCLK
SLAVE
DAC
Figure 95. Implementation of Sync Signal Distribution in Slave Mode
LVDS DRIVER AND DELAY
EQUALIZATION
CLOCK
SYNC OUT
SOURCE
SYNC IN
MASTER
DAC
DACCLK
EQUALIZATION
SYNC IN
DACCLK
SLAVE
DAC
SYNC IN
DACCLK
SLAVE
DAC
Figure 94. Implementation of Sync Signal Distribution in Master/Slave Mode
Rev. 0 | Page 42 of 56
AD9776/AD9778/AD9779
Sync Pulse Receiver (Slave Devices)
Internal Synchronization in Slave Devices
The following description of SYNC_I on the slave devices also
applies to the SYNC_I on the master device. The timing for
SYNC_I on the master must match that of the slave devices.
The SYNC_I pulses, referred to in Figure 94 and shown in more
detail in Figure 96 are not restricted by their duty cycle. The
only restriction is that each sync pulse remains high for at least
one DACCLK cycle. However, the slave DAC receiving the sync
pulse must know the speed of the input sync pulse.
The internal timing functions in the slave device are shown in
Figure 96. The duty cycle of the SYNC_I signal is not restricted
to 50ꢁ. The minimum restriction on duty cycle for SYNC_I is
that it stays high for at least one full DACCLK cycle. Figure 96
shows two possible SYNC_I signals: one with a 50ꢁ duty cycle
and another one with a minimum duty cycle. More details on
SYNC_I timing restriction are given in the SYNC_I Timing
Restrictions section.
The ratio of DACCLK to the SYNC_I speed is determined by
the values of the input sync pulse frequency (Reg. 0x05,
Bits <3:1>), as shown in Table 22.
DACCLK samples SYNC_I and generates the internal sync signal
(SYNC_I_int). The period of SYNC_I_int is always DACCLK/32.
If the rate of SYNC_I is greater than DACCLK/32, the extra
pulses are stripped off. Figure 96 shows that the SYNC_I period
= DACCLK/16, so that every other SYNC_I pulse is stripped.
DACCLK_SMP is an internal signal, equal in frequency to the
DACCLK/interpolation rate. DACCLK_SMP is synthesized by
DACCLK, but synchronized by SYNC_I. Note that there is also
a programmable delay (sync input delay) between SYNC_I_int
and DACCLK_SMP. This programmable delay adds even more
flexibility to the timing interface. Figure 96 shows that the
interpolation is set to 8× (DACCLK_SMP rate is 1/8 that of
DACCLK).
Table 22.
Reg. 0x05, Bits <3:1>
Divider Ratio
DACCLK/32 (default)
DACCLK/16
DACCLK/8
DACCLK/4
DACCLK/2
Undefined
Undefined
Undefined
000
001
010
011
100
101
110
111
DACCLK_ext
DACCLK_int
(Prop, Delay)
SYNC_I_ext_min_dutycycle
SYNC_I_ext_50%dutycycle
SYNC_I_int (Post SYNC DELAY)
SYNC_I_int (Post SYNC DELAY)
SYNC_stripped (Post Edge Detector)
DCLK_SMP
SYNC INPUT DELAY
0x06 (7:4)
(~100ps/increment)
DCLK_OUT
DATA CLOCK OFFSET
DATA CLOCK DELAY
0x04 (7:4)
0x07 (4:0)
(1 DACCLK cycle/increment)
Figure 96. Internal and External Timing for Master or Slave Device
Rev. 0 | Page 43 of 56
AD9776/AD9778/AD9779
0x05 (0), 0x06 (7:4)
EDGE DETECTOR, DETECTS
ON ONE OUT OF EVERY
32 DACCLK EDGES
SYNC
INPUT
DELAY
D
Q
FF1
LVDS DIFFERENTIAL
SYNC INPUT
PROGRAMMABLE
DELAY
DACCLK
(Internal
Delayed)
IRQ, 0x19 (6)
IRQ ENABLE, 0x19 (2)
0x06 (3:0)
PROGRAMMABLE
D
DELAY
FF2
CLK
Q
D
REGISTERED
SYNC_I_int
FF3
CLK
Q
Figure 97. Simplified Internal Synchronization Logic
SYNC_I Timing Restrictions
circuit shown in Figure 95 uses the DACCLK to properly
register SYNC_I. The delay is programmable by Reg. 0x06, Bits
<3:0>. IRQ is registered in Reg. 0x19, Bit 6.
The AD977x can register timing errors for the SYNC_I signals.
The block diagram for this synchronization logic is shown in
Figure 94, which is very similar to the data input synchro-
nization circuit shown in Figure 95. The difference is that the
Rev. 0 | Page 44 of 56
AD9776/AD9778/AD9779
EVALUATION BOARD OPERATION
The AD977x evaluation board is designed to optimize the DAC
performance and the speed of the digital interface while
remaining user friendly. To operate the board, the user needs a
power source, a clock source, and a digital data source. The user
also needs a spectrum analyzer or an oscilloscope to look at the
DAC output. The diagram in Figure 98 illustrates the test setup.
A sine or square wave clock works well as a clock source. The dc
offset on the clock is not a problem, since the clock is ac-
coupled on the evaluation board before the DACCLK inputs.
All necessary connections to the evaluation board are shown in
more detail in Figure 99.
The evaluation board comes with software that allows the user
to program the SPI port. Via the SPI port, the devices can be
programmed into any of its various operating modes. When
first operating the evaluation board, it is useful to start with a
simple configuration, that is, a configuration in which the SPI
port settings are as close as possible to the default settings. The
default software window is shown in Figure 100. The arrows
indicate which settings need to be changed for an easy first time
evaluation. Note that this implies that the PLL is not being used
and that the clock being used is at the speed of the DAC output
sample rate. For a more detailed description of how to use the
PLL, see the PLL Loop Filter Bandwidth section.
CLOCK
GENERATOR
ADAPTER
CABLES
CLKIN
SPI PORT
SPECTRUM
ANALYZER
DIGITAL
PATTERN
GENERATOR
AD9779
EVALUATION
BOARD
CLOCK IN
1.8V POWER SUPPLY
3.3V POWER SUPPLY
DATACLK OUT
Figure 98. Typical Test Setup
AUX33
DVDD18
DVDD33
CVDD18
AVDD33
J2
5V Supply
P4 Digital Input Connector
J1 CLOCK IN
MODULATOR
OUTPUT
JP4
JP15
JP8
S5 OUTPUT 1
+5V
JP14
AD9779
AD8349
JP3
JP16
GND
JP2
JP17
S6 OUTPUT 2LOCAL OSC
INPUT
S7 DCLKOUT
ANALOG
DEVICES
AD9779/8/6
REV D
SPI PORT
Figure 99. AD977x Evaluation Board Showing all Connections
Rev. 0 | Page 45 of 56
AD9776/AD9778/AD9779
1. SET INTEROPOLATION RATE
2. SET INTEROPOLATION FILTER MODE
3. SET INPUT DATA FORMAT
4. SET DATACLK POLARITY TO MATCH INPUT TIMING
Figure 100. SPI Port Software Window
The default settings for the evaluation board allow the user to
view the differential outputs through a transformer that
and common-mode transformers are installed on each DAC
output, so that the pairs can be set up in either order. As an
example, for the frequency range of dc to 30 MHz, it is
recommended that the transformer is placed right after the
DAC. Above DAC output frequencies of 30 MHz, it is
recommended that the common-mode transformer is placed
right after the DAC outputs, followed by the transformer.
converts the DAC output signal to a single-ended signal. On the
evaluation board, these transformers are designated T1A, T2A,
T3A, and T4A. There are also four common-mode transformers
on the board that are designated T1B, T2B, T3B, and T4B. The
recommended operating setup is to place the transformer and
common-mode transformer in series. A pair of transformers
Rev. 0 | Page 46 of 56
AD9776/AD9778/AD9779
MODIFYING THE EVALUATION BOARD TO USE
THE AD8349 ON-BOARD QUADRATURE
MODULATOR
The evaluation board contains an Analog Devices AD8349
quadrature modulator. The AD977x and AD8349 provide an
easy-to-interface DAC/modulator combination that can be
easily evaluated on the evaluation board. To route the DAC
output signal to the quadrature modulator, the following
jumper settings must be made:
Unsoldered: JP14, JP15, JP16, JP17
Soldered: JP2, JP3, JP4, JP8
The DAC output area of the evaluation board is shown in
Figure 101. The jumpers that need to be changed to use the
AD8349 are circled. Also circled are the 5 V and GND
connections for the AD8349.
Figure 101. Photo of Evaluation Board, DAC Output Area
Rev. 0 | Page 4ꢀ of 56
AD9776/AD9778/AD9779
EVALUATION BOARD SCHEMATICS
Figure 102. Evaluation Board, Rev. D, Power Supply Decoupling and SPI Interface
Rev. 0 | Page 48 of 56
AD9776/AD9778/AD9779
R10
50Ω
T2B
T1B
R7
T3A
T4A
S6
1
JP16
JP17
0Ω
1
3
6
4
1
3
6
4
3
2
1
4
6
3
2
1
4
6
2
R8
0Ω
P
S
P
S
R11
50Ω
ADTL1-12
T2A
ADTL1-12
T1A
TC1-1T
T3B
TC1-1T
T4B
R9
50Ω
R6
JP14
JP15
0Ω
6
4
1
6
4
1
4
6
3
1
4
6
3
1
2
3
2
3
R5
0Ω
2
S
P
S
P
1
R11
50Ω
S5
TC1-1T
TC1-1T
ADTL1-12
ADTL1-12
DGND;5
JP3
JP2
C62
0.1μF
C33
1nF
C34
1nF
D2N
D2P
DPWR33
JP4
JP8
C40
0.1μF
D1P
D1N
C61
1nF
C37
0.1μF
C38
0.1μF
R63
10Ω
C35
1nF
C18
1nF
C60
0.1μF
C24
1nF
C25
1nF
CR1
VAL
C39
0.1μF
C9
0.1μF
6.3V
C59
1nF
C10
0.1μF
CR2
C36
1nF
VAL
C8
C1
4.7μF
C2
4.7μF
10μF
R56
10Ω
VOLT
R64
1KΩ
R64
1KΩ
VOLT
C27
1nF
AVDD33
C58
C11
1nF
0.1μF
DVDD33
DVDD18
C57
0.1μF
C3
4.7μF
VOLT
C56
1nF
C29
1nF
C55
0.1μF
C12
0.1μF
C31
1nF
C30
1nF
C14
0.1μF
C13
0.1μF
+
C6
4.7μF
C4
4.7μF
C5
4.7μF
VOLT
VOLT
DVDD33
CVDD18
DVDD18
CLK_N
CLK_P
JP7
P2D15
R59
1
2
3
6
5
4
S16
S15
S2
22Ω
1
1
2
2
R58
22Ω
DPWR33
1
DPWR33
2
U11
U10
Q
U10
R26
22Ω
4
10
PRE
R32
S7
1
C84
0.1μF
25Ω
4
5
3
2
1
3
1
2
5
11
13
12
9
JP18
PRE
Y
GND
A
NC
J
J
Q
2
6
7
JP13
VCC
K
Q_
K
Q_
DPWR33
R26
22Ω
CLR
CLR
14
74LCX112
15
74LCX112
C78
SN74LVC1G34
4.7μF
VOLT
C7
4.7μF
VOLT
C15
1nF
C32
0.1μF
Figure 103. Evaluation Board, Rev. D, Circuitry Local to Devices
Rev. 0 | Page 49 of 56
AD9776/AD9778/AD9779
C80
2.1pF
R15
20Ω
C53
0.1μF
D1N
C64
17.2pF
C50
17.2pF
R20
40Ω
R17
150Ω
L10
55nH
AUX1_N
R4
150Ω
R19
300Ω
C81
4.5pF
JP13
AUX1_P
R12
150Ω
C63
17.2pF
L11
55nH
C52
17.2pF
R21
40Ω
R22
147.5Ω
D1P
R16
20Ω
MODULATED OUTPUT
J4
C47
100pF
1
VDDM
2
2
+
C41
10μF
10V
C72
0.1μF
C72
0.1μF
DGND2
DGND2
2
DGND2
VDDM
R14
1kΩ
JP1
2
DGND2
C51
0.1μF
LOCAL OSC OUTPUT
J5
C74
T4
100pF
1
1
2
3
5
2
2
S
P
4
DGND2
DGND2
C75
100pF
2
ETC1-1-13
DGND2
C83
2.1pF
R24
20Ω
C54
0.1μF
D2N
C44
17.2pF
C65
17.2pF
R60
40Ω
JP9
R25
150Ω
L10
55nH
JP10
AUX2_N
2
R2
150Ω
R27
300Ω
C82
4.5pF
JP13
DGND2
AUX2_P
R3
150Ω
C43
17.2pF
L11
55nH
C79
17.2pF
R61
40Ω
R62
147.5Ω
D2P
R23
20Ω
Figure 104. Evaluation Board, Rev. D, AD8349 Quadrature Modulator
CLK_P
CVDD18
C19
T2
0.1μF
C16
R28
R30
4
5
3
2
1
DNB
25Ω
1kΩ
R13
VAL
P
S
C17
0.1μF
R29
25Ω
R31
300Ω
C23
0.1μF
ETC1-1-13
CLK_N
Figure 105. Evaluation Board, Rev. D, DAC Clock Interface
Rev. 0 | Page 50 of 56
AD9776/AD9778/AD9779
P4
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
P4
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
P4
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
P4
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
P4
CSB
SD1
E1
E2
E3
E4
E5
E6
E7
E8
E9
SCLK
SD0
P2D0
P2D2
P2D4
P2D6
P2D8
P2D10
P2D12
P2D14
P2D1
P2D3
P2D5
P2D7
P2D9
P2D11
P2D13
P2D15
E10
E11
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
P1D0
P1D2
P1D4
P1D6
P1D8
P1D10
P1D12
P1D14
P1D1
P1D3
P1D5
P1D7
P1D9
P1D11
P1D13
P1D15
PKG_TYPE = MOLEX110
VAL
PKG_TYPE = MOLEX110
VAL
PKG_TYPE = MOLEX110
PKG_TYPE = MOLEX110
VAL
PKG_TYPE = MOLEX110
VAL
VAL
DGND
BLK
DGND1
BLK
Figure 106. Evaluation Board, Rev. D, Digital Input Buffers
1
J2
2
U2
1
2
3
4
CVDD18_IN
JP19
P2
1
C86
1μF
C85
1μF
ADP3339-1-8
2
VAL
CNTERM_2P
U3
4
1
2
3
DVDD18_IN
JP20
C89
1μF
C88
1μF
ADP3339-1-8
U4
4
1
2
3
DVDD33_IN
AVDD33_IN
DPWR33_IN
JP21
JP22
JP23
C92
1μF
C91
1μF
ADP3339-3-3
U7
4
1
2
3
C93
1μF
C94
1μF
ADP3339-3-3
U8
4
1
2
3
C96
1μF
C97
1μF
ADP3339-3-3
Figure 107. Evaluation Board, On-Board Voltage Regulators
Rev. 0 | Page 51 of 56
AD9776/AD9778/AD9779
Figure 108. Evaluation Board, Rev. D, Top Silk Screen
Figure 109. Evaluation Board, Rev. D, Top Layer
Rev. 0 | Page 52 of 56
AD9776/AD9778/AD9779
Figure 110. Evaluation Board, Rev. D, Layer 2
Figure 111. Evaluation Board, Rev. D, Layer 3
Rev. 0 | Page 53 of 56
AD9776/AD9778/AD9779
Figure 112. Evaluation Board, Rev. D, Bottom Layer
Figure 113. Evaluation Board, Rev. D, Bottom Silkscreen
Rev. 0 | Page 54 of 56
AD9776/AD9778/AD9779
OUTLINE DIMENSIONS
16.00 BSC SQ
1.20
MAX
0.75
0.60
0.45
14.00 BSC SQ
100
1
76
75
76
75
100
1
PIN 1
9.50 SQ
TOP VIEW
(PINS DOWN)
EXPOSED
PAD
BOTTOM VIEW
(PINS UP)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
50
51
25
25
26
49
50
26
3.5°
0°
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
VIEW A
0.15
0.05
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
Figure 114. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9ꢀꢀ6BSVZ1
AD9ꢀꢀ6BSVZRL1
AD9ꢀꢀ8BSVZ1
AD9ꢀꢀ8BSVZRL1
AD9ꢀꢀ9BSVZ1
AD9ꢀꢀ9BSVZRL1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
100-lead TQFP_EP
100-lead TQFP_EP
100-lead TQFP_EP
100-lead TQFP_EP
100-lead TQFP_EP
100-lead TQFP_EP
Package Option
SV-100-3
SV-100-3
SV-100-3
SV-100-3
SV-100-3
SV-100-3
AD9ꢀꢀ6-EB
AD9ꢀꢀ8-EB
AD9ꢀꢀ9-EB
Evaluation Board
Evaluation Board
Evaluation Board
1 Z = Pb-free part.
Rev. 0 | Page 55 of 56
AD9776/AD9778/AD9779
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05361-0-7/05(0)
Rev. 0 | Page 56 of 56
相关型号：
AD9778BSVZRL
DUAL, PARALLEL, WORD INPUT LOADING, 14-BIT DAC, PQFP100, LEAD FREE, MS-026AED-HD, TQFP-100
ROCHESTER
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