AD9912 [ADI]
1 GSPS Direct Digital Synthesizer w/ 14-bit DAC; 1 GSPS直接数字频率合成W / 14位DAC
| 型号： | AD9912 |
| 厂家： | 
ADI |
| 描述： | 1 GSPS Direct Digital Synthesizer w/ 14-bit DAC |
| 文件： | 总3页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 GSPS Direct Digital
Synthesizer w/ 14-bit DAC
AD9912
Preliminary Technical Data
FEATURES
APPLICATIONS
1 GSPS internal clock speed (up to 400 MHz out directly)
Integrated 1 GSPS 14-bit DAC
48-bit frequency tuning word
Differential HSTL Comparator
Flexible System Clock Input accepts either crystal or external
reference clock.
Agile LO frequency synthesis
Low jitter, fine tune clock generation
Test and measurement equipment
Wireless Base Stations, Controllers
Secure Communications
Fast frequency hopping
On-chip Low-Noise PLL REFCLK Multiplier
2 Spur Reduction Channels
Low Jitter clock doubler for frequencies up to 750 MHz
Single-ended CMOS Comparator; frequencies < 50MHz
Programmable output divider for CMOS output
Serial I/O control
Excellent Dynamic Performance
Software controlled power-down
64-lead LFCSP package
GENERAL DESCRIPTION
The AD9912 is a direct digital synthesizer (DDS) featuring an
integrated 14-bit DAC. The AD9912 features a 48–bit
frequency tuning word (FTW) which can synthesize
frequencies in step sizes no larger than 4 uHz. Absolute
frequency accuracy can be achieved by adjusting the DAC
system clock.
Phase Noise @ 95MHz using Vectron VCC6 87.5MHz
Oscillator:
100 Hz Offset: -103 dBc/Hz
10 kHz Offset: -133 dBc/Hz
1 MHz Offset: -136 dBc/Hz
The AD9912 also features an integrated system clock PLL,
which allows reference clocks as low as 25 MHz.
The AD9912 operates over an industrial temperature range,
spanning -40°C to +85°C.
Figure 1: Basic Block Diagram
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved
AD9912
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVDD_I/O
DVSS
DVDD
DVSS
DVDD
DVSS
DVDD
DVSS
S1
1
2
3
4
5
6
7
8
9
48 DAC_RSET
47 AVDD3
46 AVDD3
45 AVDD
PIN 1
INDICATOR
44 N/C
43 AVSS
42 AVDD
41 FDBK_IN
40 FDBK_INB
39 AVSS
AD9912
TOP VIEW
S2 10
AVDD 11
N/C 12
38 OUT_CMOS
37 AVDD3
36 AVDD
(Not to Scale)
N/C 13
AVDD3 14
N/C 15
35 OUT
34 OUTB
N/C 16
33 AVSS
Figure 2: 64-Lead LFCSP Pin Configuration
Table 2: Pin Function Descriptions
Pin No.
Input/
Pin
Mnemonic
Description
Output
Type
1
I
I
I
Power DVDD_I/O
Power DVSS
Power DVDD
3.3V I/O Digital Supply
Digital Ground: Connect to Ground
1.8V Digital Supply
2, 4, 6, 8
3, 5, 7
9, 10, 54,
55
I/O
3.3V
CMOS
S1, S2, S3, S4
Configurable startup strapping pins: These pins are configured under program control
(see “Default Power-up Frequency Options for 1 GHz System Clock”on Page 21. After
power-up, these pins become outputs.
11, 19, 23-
26, 29, 30,
36, 42, 45,
53
I
Power AVDD
Analog Supply: Connect to a nominal 1.8V Supply
Rev. PrB | Page 2 of 3
Preliminary Technical Data
AD9912
12, 13,
15-18, 20,
21, 22, 44
N/C
No Connect
No Connect: These excess, unused pins should be left floating.
Analog Supply: Connect to a nominal 3.3V supply
14, 37, 46,
47, 49
I
Power AVDD3
27
28
31
I
I
SYSCLK
SYSCLKB
LOOP_FILTER
System Clock Input. Can be LVPECL or Crystal input, depending on CLKMODESEL pin.
Complementary System Clock: Complementary signal to the input provided on pin 27
System Clock Multiplier Loop Filter: When using the frequency multiplier to drive the
System Clock, an external loop filter must be constructed and attached to this pin.
32
I
1.8V
CMOS
CLKMODESEL
Clock Mode Select. Set to GND when using a crystal. Pull up to 1.8V when using either an
oscillator or external clock source. (See the SysClk Inputs section for details on the use of
this pin).
33, 39, 43,
52
I
GND
AVSS
Analog Ground: Connect to Ground. NOTE: Pin 43 is a ground shield connection.
34
35
38
40
O
O
O
I
1.8V
HSTL
OUTB
Complementary HSTL Output: See spec table and the OUTPUT DRIVERS AND
MULTIPLIER section, under sub heading Primary (Differential) Driver, for details
HSTL Output: See specification table and the CLOCK DRIVERS section
1.8V
HSTL
OUT
3.3V
CMOS
OUT_CMOS
FDBK_INB
CMOS Output: See specification table and the CLOCK DRIVERS section
Complementary Feedback input: In standard operating mode, this pin is connected to
the filtered IOUTB output . This internally biased input is typically AC-coupled, and when
configured as such, can accept any differential signal.
41
48
50
51
I
FDBK_IN
DAC_RSET
IOUT
Feedback Input: In standard operating mode, this pin is connected to the filtered IOUT
output
O
O
O
DAC output current setting resistor. Connect a resistor from this pin to GND . See the
“DAC Output” section.
DAC output: Output signal should be filtered and sent back on chip through FDBK_INB
input
Complimentary DAC output: Output signal should be filtered and sent back on chip
through FDBK_IN input
IOUTB
56, 57
58
No Connect
PWRDOWN
No Connect: These should be left floating.
I
I
3.3V
CMOS
Power Down: When this active high pin is asserted, the device goes into full power
down mode.
59
60
61
3.3V
CMOS
RESET
Chip Reset: When this active high pin is asserted, the chip goes into reset. Note: upon
power up, a 10 us reset pulse is automatically generated when the power supplies reach
a threshold and stabilize.
I/O Update: A logic transition from 0 to 1 on this pin transfers data from the I/O port
registers to the control registers (see the Write subsection of the General Operation of
Serial Control Port section).
I
I
3.3V
CMOS
IO_UPDATE
CSB
3.3V
CMOS
Chip Select: Active low. When programming a device, this pin must be held low. In
systems where more than one AD9549 is present this enables individual programming
of each AD9549
62
63
64
O
I/O
O
3.3V
CMOS
3.3V
CMOS
SDO
SDIO
SCLK
Serial Data Output: When the device is in three wire mode, data is read on this pin
Serial Data Input/Output: When the device is in three-wire mode, data is written via this
pin. In 2 wire mode, data reads and writes both occur on this pin
Serial Programming Clock: data clock for serial programming.
3.3V
CMOS
Rev. PrB| Page 3 of 3
PR06763-0-6/07(PrB)
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