AD9920A [ADI]
12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator; 12位CCD信号处理器， V型驱动器和精确定时发生器
| 型号： | AD9920A |
| 厂家： | 
ADI |
| 描述： | 12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator |
| 文件： | 总2页 (文件大小：62K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit CCD Signal Processor with V-Driver
and Precision Timing Generator
AD9920A
FEATURES
GENERAL DESCRIPTION
Integrated 19-channel V-driver
1.8 V AFETG core
24 programmable vertical clock signals
The AD9920A is a highly integrated charge-coupled device (CCD)
signal processor for digital still camera applications. It includes a
complete analog front end (AFE) with analog-to-digital conversion,
Correlated double sampler (CDS) with −3 dB, 0 dB,
+3 dB, and +6 dB gain
12-bit, 40.5 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with ~400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and
system support
On-chip sync generator with external sync input
On-chip 1.8 V low dropout (LDO)
combined with a full-function programmable timing generator
and 19-channel vertical driver (V-driver). The timing generator
is capable of supporting up to 26 vertical clock signals to control
advanced CCDs. The on-chip V-driver supports up to 19 channels
for use with 6-field CCDs. A Precision Timing™ core allows adjust-
ment of high speed clocks with approximately 400 ps resolution
at 40.5 MHz operation. The AD9920A also contains six GPOs
that can be used for shutter and system functions.
The analog front end includes black level clamping, variable
gain CDS, and a 12-bit ADC. The timing generator provides all
the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control.
105-lead 8 mm × 8 mm CSP_BGA package
APPLICATIONS
The AD9920A is specified over an operating temperature range
of −25°C to +85°C.
Digital still cameras
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9920A
–3dB, 0dB, +3dB, +6dB
VREF
12
12-BIT
ADC
CDS
VGA
CCDIN
DOUT
DCLK
6dB TO 42dB
CLAMP
3V INPUT
LDO
REG
1.8V OUTPUT
INTERNAL CLOCKS
RG
HL
PRECISION
TIMING
GENERATOR
HORIZONTAL
DRIVERS
SL
8
INTERNAL
REGISTERS
SCK
H1 TO H8
XV1 TO XV24
SDATA
19
V1A TO V6 (3-LEVEL)
V7 TO V15 (2-LEVEL)
VERTICAL
24
GPO5
GPO6
VERTICAL
DRIVER
TIMING
SYNC
GENERATOR
CONTROL
SUBCK
6
XSUBCK
XSUBCNT
GPO1 TO GPO4,
GPO7, GPO8
HD
VD
CLI CLO SYNC/RSTB
Figure 1.
For more information about the AD9920A, contact Analog Devices via email at afe.ccd@analog.com.
Rev. Sp0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD9920A
NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06878F-0-7/07(Sp0)
Rev. Sp0 | Page 2 of 2
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