AD9920ABBCZ [ADI]
12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator; 12位CCD信号处理器， V型驱动器和精确定时发生器
| 型号： | AD9920ABBCZ |
| 厂家： | 
ADI |
| 描述： | 12-Bit CCD Signal Processor with V-Driver and Precision Timing Generator |
| 文件： | 总112页 (文件大小：1187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit CCD Signal Processor with V-Driver
and Precision Timing Generator
AD9920A
FEATURES
GENERAL DESCRIPTION
Integrated 19-channel V-driver
1.8 V AFETG core
24 programmable vertical clock signals
The AD9920A is a highly integrated charge-coupled device (CCD)
signal processor for digital still camera applications. It includes a
complete analog front end (AFE) with analog-to-digital conversion,
Correlated double sampler (CDS) with −3 dB, 0 dB,
+3 dB, and +6 dB gain
12-bit, 40.5 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with ~400 ps resolution
On-chip 3 V horizontal and RG drivers
General-purpose outputs (GPOs) for shutter and
system support
On-chip sync generator with external sync input
On-chip 1.8 V low dropout (LDO) regulator
105-ball, 8 mm × 8 mm CSP_BGA package
combined with a full-function programmable timing generator
and 19-channel vertical driver (V-driver). The timing generator
is capable of supporting up to 24 vertical clock signals to control
advanced CCDs. The on-chip V-driver supports up to 19 channels
for use with six-field CCDs. A Precision Timing® core allows adjust-
ment of high speed clocks with approximately 400 ps resolution
at 40.5 MHz operation. The AD9920A also contains six GPOs
that can be used for shutter and system functions.
The analog front end includes black level clamping, variable
gain CDS, and a 12-bit ADC. The timing generator provides all
the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate
pulses, substrate clock, and substrate bias control.
APPLICATIONS
The AD9920A is specified over an operating temperature range
of −25°C to +85°C.
Digital still cameras
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9920A
–3dB, 0dB, +3dB, +6dB
CDS
VREF
12
12-BIT
ADC
VGA
CCDIN
D0 TO D11
DCLK
6dB TO 42dB
CLAMP
LDOIN
LDO
REG
LDOOUT
INTERNAL CLOCKS
RG
HL
PRECISION
TIMING
GENERATOR
HORIZONTAL
DRIVERS
SL
8
INTERNAL
REGISTERS
SCK
H1 TO H8
XV1 TO XV24
SDATA
19
V1A TO V6 (3-LEVEL)
V7 TO V16 (2-LEVEL)
VERTICAL
24
GPO5
GPO6
VERTICAL
DRIVER
TIMING
SYNC
GENERATOR
CONTROL
SUBCK
6
XSUBCK
XSUBCNT
GPO1 TO GPO4,
GPO7, GPO8
HD
VD
CLI CLO
SYNC/RST
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.
AD9920A
TABLE OF CONTENTS
Features .............................................................................................. 1
V-Driver Slew Rate Control...................................................... 60
Shutter Timing Control............................................................. 60
Substrate Clock Operation (SUBCK)...................................... 60
Field Counters............................................................................. 63
General-Purpose Outputs (GPOs) .......................................... 64
GP Lookup Table (LUT)............................................................ 68
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Digital Specifications ................................................................... 5
Analog Specifications................................................................... 5
Timing Specifications .................................................................. 7
Vertical Driver Specifications ..................................................... 8
Absolute Maximum Ratings.......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 14
Equivalent Circuits......................................................................... 15
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
H-Counter Behavior in Slave Mode......................................... 17
High Speed Precision Timing Core........................................... 18
Digital Data Outputs.................................................................. 22
Horizontal Clamping and Blanking......................................... 23
Horizontal Timing Sequence Example.................................... 30
Vertical Timing Generation...................................................... 32
Vertical Sequences (VSEQ)....................................................... 34
Vertical Timing Example........................................................... 51
Internal Vertical Driver Connections (18-Channel Mode).. 53
Internal Vertical Driver Connections (19-Channel Mode).. 54
Complete Exposure/Readout Operation Using Primary
Counter and GPO Signals......................................................... 69
SG Control Using GPO ............................................................. 71
Manual Shutter Operation Using Enhanced SYNC Modes.. 73
Analog Front End Description and Operation ...................... 77
Applications Information.............................................................. 79
Power-Up Sequence for Master Mode..................................... 79
Power-Up Sequence for Slave Mode........................................ 81
Power-Down Sequence for Master and Slave Modes............ 83
Additional Restrictions in Slave Mode.................................... 84
Vertical Toggle Position Placement Near Counter Reset...... 85
Standby Mode Operation.......................................................... 86
CLI Frequency Change.............................................................. 86
Circuit Layout Information........................................................... 88
Typical 3 V System ..................................................................... 88
External Crystal Application .................................................... 88
Circuit Configurations .............................................................. 89
Serial Interface ................................................................................ 93
Serial Interface Timing.............................................................. 93
Layout of Internal Registers...................................................... 94
Updating New Register Values ................................................. 95
Complete Register Listing ............................................................. 96
Outline Dimensions..................................................................... 112
Ordering Guide ........................................................................ 112
Output Polarity of Vertical Transfer Clocks and Substrate
Clock ............................................................................................ 55
Rev. B | Page 2 of 112
AD9920A
REVISION HISTORY
6/10—Rev. A to Rev. B
Changes to Figure 96 ......................................................................75
Changes to Figure 100 ....................................................................77
Changes to Figure 102 ....................................................................80
Changes to Power-Up Sequence for Slave Mode Section..........81
Changes to Figure 103 ....................................................................82
Changes to Power-Down Sequence for Master and
Slave Modes Section........................................................................83
Added Table 48; Renumbered Tables Sequentially.....................86
Changes to Figure 108 ....................................................................88
Changes to Figure 109 ....................................................................89
Changes to Figure 110 ....................................................................90
Changes to Figure 111 ....................................................................91
Changes to Figure 112 ....................................................................92
Changes to Layout of Internal Registers Section
Changes to Figure 1...........................................................................1
Changes to Figure 9, Figure 10, Figure 12, and Figure 13 .........15
Moved Terminology Section..........................................................16
Changes to Figure 15 ......................................................................17
Moved Generating HBLK Line Alternation Section..................24
Moved Figure 32..............................................................................25
Moved Figure 33..............................................................................27
Changes to Vertical Sequences (VSEQ) Section .........................34
Changes to Special Vertical Sequence Alternation
(SVSA) Mode Section.....................................................................38
Added Table 18; Renumbered Tables Sequentially.....................44
Deleted Figure 77; Renumbered Figures Sequentially ...............61
Changes to SUBCK Low Speed Operation Section
and Table 43 .....................................................................................61
Changes to Figure 81 ......................................................................62
Changes to Table 45 ........................................................................64
Changes to Scheduled Toggles Section and Figure 85 ...............66
Changes to Figure 86, ShotTimer Sequences Section,
and Figure 115 .................................................................................94
Changes to Table 53 ........................................................................97
Changes to Table 57 ........................................................................99
Changes to Table 59 ......................................................................101
Changes to Table 61 ......................................................................105
Changes to Table 63 ......................................................................108
Updated Outline Dimensions......................................................112
and Figure 87 ...................................................................................67
Changes to Complete Exposure/Readout Operation
Using Primary Counter and GPO Signals Section .....................69
Changes to Triggered Control of GPO5 Section.........................71
6/09—Revision A: Initial Version
Rev. B | Page 3 of 112
AD9920A
SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
−25
−65
+85
+150
°C
°C
POWER SUPPLY VOLTAGE INPUTS
AVDD
TCVDD
CLIVDD
RGVDD
HVDD1 and HVDD2
DVDD
DRVDD
IOVDD
AFE analog supply
Timing core supply
CLI input supply
RG, HL driver supply
H1 to H8 driver supplies
Digital logic supply
Parallel data output driver supply
Digital I/O supply
1.6
1.6
1.6
2.1
2.1
1.6
1.6
1.6
1.8
1.8
3.0
3.0
3.0
1.8
3.0
3.0
2.0
2.0
3.6
3.6
3.6
2.0
3.6
3.6
V
V
V
V
V
V
V
V
V-DRIVER POWER SUPPLY VOLTAGES
VDVDD
VH1, VH2
VL1, VL2
VM1, VM2
VLL
VH1, VH2 to VL1, VL2, VLL
VMM1
LDO2
LDOIN
Output Voltage
Output Current
V-driver/logic supply
V-driver high supply
V-driver low supply
V-driver midsupply
SUBCK low supply
1.6
3.0
3.6
V
V
V
V
V
V
V
11.0
−8.5
−1.5
−11.0
15.0
−7.5
0.0
16.5
−5.5
+1.5
−5.5
23.5
VDVDD
−7.5
SUBCK midsupply
LDO supply input
VLL
0.0
2.5
1.8
60
3.0
1.9
100
3.6
2.05
V
V
mA
POWER SUPPLY CURRENTS—40.5 MHz
OPERATION
AVDD
TCVDD
CLIVDD
RGVDD
HVDD1 and HVDD23
DVDD
DRVDD
1.8 V
1.8 V
3 V
27
5
mA
mA
mA
mA
mA
mA
mA
1.5
10
59
9.5
6
3.3 V, 20 pF RG load, 20 pF HL load
3.3 V, 480 pF total load on H1 to H8
1.8 V
3 V, 10 pF load on each data output pin
(D0 to D11)
IOVDD
3 V, depends on load and output
frequency of digital I/O
2
mA
POWER SUPPLY CURRENTS—STANDBY
MODE OPERATION
Standby1 Mode
Standby2 Mode
20
5
mA
mA
Standby3 Mode
1.5
mA
MAXIMUM CLOCK RATE (CLI)
MINIMUM CLOCK RATE (CLI)
40.5
MHz
MHz
10
1 VMM must be greater than VLL and less than VDVDD.
2 LDO should be used only for the AD9920A 1.8 V supplies, not for external circuitry.
3 The total power dissipated by the HVDD (or RGVDD) can be approximated using the following equation:
Total HVDD Power = (CL × HVDD × Pixel Frequency) × HVDD
Rev. B | Page 4 of 112
AD9920A
DIGITAL SPECIFICATIONS
IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD1 and HVDD2 = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments Min
VDD − 0.6
Typ
Max
Unit
LOGIC INPUTS (IOVDD)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
V
V
μA
μA
pF
0.6
10
10
10
LOGIC OUTPUTS (IOVDD, DRVDD)
High Level Output Voltage
Low Level Output Voltage
VOH
VOL
IOH = 2 mA
IOL = 2 mA
VDD − 0.5
VDD − 0.5
V
V
0.5
0.5
RG and H-DRIVER OUTPUTS (HVDD1,
HVDD2, and RGVDD)
High Level Output Voltage
Low Level Output Voltage
Maximum H1 to H8 Output Current
Maximum HL and RG Output Current
Maximum Load Capacitance
CLI INPUT
VOH
VOL
Maximum current
Maximum current
Programmable
Programmable
Each output
V
V
mA
mA
pF
30
17
60
With CLO oscillator disabled
High Level Input Voltage
Low Level Input Voltage
VIHCLI
VILCLI
CLIVDD/2 + 0.5
V
V
CLIVDD/2 − 0.5
ANALOG SPECIFICATIONS
AVDD = 1.8 V, fCLI = 40.5 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CDS1
Test Conditions/Comments
Min
Typ
Max
Unit
DC Restore
AVDD − 0.5 V
Limit is the lower of AVDD + 0.3 V or 2.2 V
VGA gain = 6.3 dB (Code 15, default value)
1.21
1.3
0.5
1.44
0.8
V
V
Allowable CCD Reset Transient
CDS Gain Accuracy
−3 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
+6 dB CDS Gain
−3.1
−0.6
2.7
−2.6
−0.1
3.2
−2.1
+0.4
3.7
dB
dB
dB
dB
5.2
5.7
6.2
Maximum Input Range Before
Saturation
−3 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
1.4
1.0
0.7
0.5
V p-p
V p-p
V p-p
V p-p
+6 dB CDS Gain
Allowable OB Pixel Amplitude1
0 dB CDS Gain (Default)
+6 dB CDS Gain
−100
−50
+200
+100
mV
mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
1024
Guaranteed
Steps
Low Gain
Maximum Gain
VGA Code 15, default
VGA Code 1023
6.3
42.4
dB
dB
Rev. B | Page 5 of 112
AD9920A
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Minimum Clamp Level
Maximum Clamp Level
ADC
1024
Steps
Measured at ADC output
Code 0
Code 1023
0
255
LSB
LSB
Resolution
Differential Nonlinearity (DNL)2
12
Bits
LSB
0.5
No Missing Codes
Guaranteed
Integral Nonlinearity (INL)2
Full-Scale Input Voltage
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
SYSTEM PERFORMANCE
Gain Accuracy
3.0
2.0
LSB
V
1.4
0.4
V
V
Includes entire signal chain
0 dB CDS gain
Low Gain
VGA Code 15
5.7
6.2
6.7
dB
Gain = (0.0358 × code) + 5.76 dB
Maximum Gain
Peak Nonlinearity, 1 V Input Signal2
Total Output Noise2
VGA Code 1023
6 dB VGA gain, 0 dB CDS gain applied
AC-grounded input, 6 dB VGA gain
applied
Measured with step change on supply
41.8
42.3
0.1
0.6
42.8
0.3
dB
%
LSB rms
Power Supply Rejection (PSR)2
40
dB
1 Input signal characteristics are defined as shown in Figure 2.
2 See the Terminology section.
MAXIMUM INPUT LIMIT = LESSER OF
2.2V OR AVDD + 0.3V
+1.8V TYP (AVDD)
800mV
MAXIMUM
+1.3V TYP (AVDD – 0.5V)
DC RESTORE VOLTAGE
500mV TYP
RESET TRANSIENT
1V MAXIMUM INPUT SIGNAL RANGE
(0dB CDS GAIN)
200mV MAX
OPTICAL BLACK PIXEL
0V (AVSS)
MINIMUM INPUT LIMIT
(AVSS – 0.3V)
Figure 2. Input Signal Characteristics
Rev. B | Page 6 of 112
AD9920A
TIMING SPECIFICATIONS
CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, fCLI = 40.5 MHz, unless otherwise noted.
Table 4.
Test Conditions/
Comments
Parameter
Symbol Min
Typ
Max
Unit
MASTER CLOCK
See Figure 18
CLI Clock Period
CLI High/Low Pulse Width
Delay from CLI Rising Edge to Internal
Pixel Position 0
tCONV
24.7
ns
ns
ns
0.8 × tCONV/2 tCONV/2 1.2 × tCONV/2
6
tCLIDLY
SLAVE MODE SPECIFICATIONS
VD Falling Edge to HD Falling Edge
HD Falling Edge to CLI Rising Edge
HD Falling Edge to CLO Rising Edge
CLI Rising Edge to SHPLOC
AFE
See Figure 105
tVDHD
tHDCLI
tHDCLO
tCLISHP
0
3
3
3
VD period − tCONV ns
Only valid if OSC_RST = 0
Only valid if OSC_RST = 1
Internal sample edge
tCONV − 2
tCONV − 2
tCONV − 2
ns
ns
ns
SHPLOC Sample Edge to SHDLOC
Sample Edge
SHDLOC Sample Edge to SHPLOC
Sample Edge
AFE Pipeline Delay
AFE CLPOB Pulse Width
DATA OUTPUTS
See Figure 23
See Figure 23
See Figure 26
tS1
tS2
0.8 × tCONV/2 tCONV/2 tCONV − tS2
0.8 × tCONV/2 tCONV/2 tCONV − tS1
16
ns
ns
Cycles
Pixels
2
20
Output Delay from DCLK Rising Edge
See Figure 25
tOD
1
ns
Pipeline Delay from SHP/SHD
Sampling to Data Output
16
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
Must not exceed CLI
frequency
fSCLK
40.5
MHz
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
TIMING CORE SETTING RESTRICTIONS
tLS
10
10
10
10
ns
ns
ns
ns
tLH
tDS
tDH
Inhibited Region for SHP Edge
Location1
See Figure 23
tSHPINH
50
62
Edge
location
Inhibited Region for SHP or SHD with
Respect to H-Clocks2, 3, 4
See Figure 23 and
Figure 24
RETIME = 0, MASK = 0
RETIME = 0, MASK = 1
RETIME = 1, MASK = 0
RETIME = 1, MASK = 1
tSHDINH
tSHDINH
tSHPINH
tSHPINH
tDOUTINH
HxNEGLOC − 14
HxPOSLOC − 14
HxNEGLOC − 14
HxPOSLOC − 14
SHDLOC + 1
HxNEGLOC − 2
HxPOSLOC − 2
HxNEGLOC − 2
HxPOSLOC − 2
SHDLOC + 12
Edge
location
Edge
location
Edge
location
Edge
location
Inhibited Region for DOUTPHASE Edge See Figure 23
Location
Edge
location
1 Applies only to slave mode operation. The inhibited area for SHP is needed to meet the timing requirement for tCLISHP for proper H-counter reset operation.
2 When the HBLKRETIME bits (Address 0x35, Bits[3:0]) are enabled, the inhibit region for the SHD location changes to the inhibit region for the SHP location.
3 When the HBLK masking polarity registers (V-sequence Register 0x18[24:21]) are set to 0, the H-edge reference becomes HxNEGLOC.
4 The H-clock signals that have SHP/SHD inhibit regions depend on the HCLK mode: Mode 1 = H1; Mode 2 = H1, H2; Mode 3 = H1, H3; and 3-Phase Mode = Phase 1,
Phase 2, and Phase 3.
Rev. B | Page 7 of 112
AD9920A
VERTICAL DRIVER SPECIFICATIONS
VH1, VH2 = 12 V; VM1, VM2, VMM = 0 V; VL1, VL2, VLL = −6 V; CL shown in load model; TA = 25°C.
Table 5.
Parameter
Symbol Test Conditions/Comments
Min
Typ
Max
Unit
V1A TO V13
Simplified load conditions, 3000 pF to
ground + 30 Ω in series, SRSW = VSS
Delay Time, VL to VM and VM to VH tPLM, tPMH
Delay Time, VM to VL and VH to VM tPML, tPHM
40
40
150
315
250
165
ns
ns
ns
ns
ns
ns
Rise Time, VL to VM
Rise Time, VM to VH
Fall Time, VM to VL
Fall Time, VH to VM
Output Currents
At −7.25 V
tRLM
tRMH
tFML
tFHM
10
−22
22
mA
mA
mA
mA
Ω
At −0.25 V
At +0.25 V
At +14.75 V
RON
−10
35
V14, V15, V16
Simplified load conditions, 3000 pF to
ground + 30 Ω in series
Delay Time, VL to VM
Delay Time, VM to VL
Rise Time, VL to VM
Fall Time, VM to VL
Output Currents
At −7.25 V
tPLM
tPML
tRLM
tFML
45
45
345
280
ns
ns
ns
ns
10
−7
mA
mA
Ω
At −0.25 V
RON
55
SUBCK OUTPUT
Delay Time, VLL to VH
Delay Time, VH to VLL
Delay Time, VLL to VMM
Delay Time, VMM to VH
Delay Time, VH to VMM
Delay Time, VMM to VLL
Rise Time, VLL to VH
Rise Time, VLL to VMM
Rise Time, VMM to VH
Fall Time, VH to VLL
Fall Time, VH to VMM
Fall Time, VMM to VLL
Output Currents
At −7.25 V
Simplified load conditions, 1000 pF to ground
tPLH
tPHL
tPLM
tPMH
tPHM
tPML
tRLH
tRLM
tRMH
tFHL
tFHM
tFML
50
50
50
50
50
50
50
55
50
55
100
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
−12
12
mA
mA
mA
mA
Ω
At −0.25 V
At +0.25 V
At +14.75 V
RON
−20
35
SRCTL INPUT RANGE
Valid only when SRSW is high
0.8
VDVDD
V
Rev. B | Page 8 of 112
AD9920A
V-DRIVER
INPUT
50%
50%
tRLM, tRMH, tRLH
tPML, tPHM, tPHL
90%
90%
V-DRIVER
OUTPUT
tPLM
,
tPMH, tPLH
tFML, tFHM, tFHL
10%
10%
Figure 3. Definition of V-Driver Timing Specifications
Rev. B | Page 9 of 112
AD9920A
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
Rating
AVDD to AVSS
−0.3 V to +2.2 V
TCVDD to TCVSS
−0.3 V to +2.2 V
HVDD1, HVDD2 to HVSS1, HVSS2
RGVDD to RGVSS
−0.3 V to +3.9 V
−0.3 V to +3.9 V
DVDD to DVSS
−0.3 V to +2.2 V
THERMAL RESISTANCE
DRVDD to DRVSS/LDOVSS
IOVDD to IOVSS
VDVDD to VDVSS
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
CLIVDD to TCVSS
Table 7. Thermal Resistance
Package Type
VH1, VH2 to VL1, VL2, VLL
VH1, VH2 to VDVSS
VL1, VL2 to VDVSS
VM1, VM2 to VDVSS
VLL to VDVSS
−0.3 V to +25.0 V
−0.3 V to +17.0 V
−17.0 V to +0.3 V
−6.0 V to +3.0 V
−17.0 V to +0.3 V
VLL − 0.3 V to VDVDD + 0.3 V
VLx − 0.3 V to VHx + 0.3 V
−0.3 V to RGVDD + 0.3 V
−0.3 V to HVDDx + 0.3 V
−0.3 V to VDVDD + 0.3 V
θJA
Unit
CSP_BGA (BC-105-1)
40.3
°C/W
ESD CAUTION
VMM to VDVSS
V1A to V16 to VDVSS
RG and HL Outputs to RGVSS
H1 to H8 Outputs to HVSSx
VDR_EN, XSUBCNT, SRCTL, SRSW
to VDVSS
Digital Outputs to IOVSS
Digital Inputs to IOVSS
SCK, SL, SDATA to DVSS
REFT, REFB, CCDIN to AVSS
Junction Temperature
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
150°C
Lead Temperature
(Soldering, 10 sec)
350°C
Rev. B | Page 10 of 112
AD9920A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A1 CORNER
INDEX AREA
11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
BOTTOM VIEW
(Not to Scale)
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
AVDD
AVSS
DVDD
DVSS
Type1 Description
L6
P
P
P
P
Analog Supply.
Analog Supply Ground.
Digital Logic Supply.
Digital Logic Ground.
CLI Input Supply.
J7, K8
A10
A9
L5
CLIVDD
TCVDD
TCVSS
DRVDD
DRVSS/LDOVSS
HVDD1
HVSS1
HVDD2
HVSS2
HVDD2
HVSS2
RGVDD
RGVSS
LDOIN
LDOOUT
IOVDD
IOVSS
VDVDD
VDVSS
VM1
P
K6
K4
A2
B2
E1
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Analog Timing Core Supply.
Analog Timing Core Ground.
Data Driver Supply.
Data Driver and LDO Ground.
H-Driver Supply.
H-Driver Ground.
H-Driver Supply.
H-Driver Ground.
H-Driver Supply.
E2
G1
G2
J1
J2
L3
K3
B1
C1
H11
G11
C11
C10
E3
H-Driver Ground.
RG, HL Driver Supply.
RG, HL Driver Ground.
LDO 3.3 V Input.
LDO Output Voltage.
Digital I/O Supply.
Digital I/O Ground.
V-Driver Logic Supply (3 V).
V-Driver Ground.
P
P
P
V-Driver Midsupply.
D3
C3
J3
H3
F3
VL1
VH1
VH2
VL2
P
P
P
P
V-Driver Low Supply.
V-Driver High Supply.
V-Driver High Supply.
V-Driver Low Supply.
V-Driver Midsupply.
VM2
P
G3
J4
L7
K7
C2
L8
L9
D11
E10
VMM
VLL
CCDIN
CCDGND
SRCTL
REFT
REFB
VD
HD
P
P
V-Driver Midsupply for SUBCK Output.
V-Driver Low Supply for SUBCK Output.
CCD Signal Input.
AI
AI
AI
AO
AO
DIO
DIO
CCD Ground.
Slew Rate Control Pin. Tie to VDVSS if not used.
Voltage Reference Top Bypass.
Voltage Reference Bottom Bypass.
Vertical Sync Pulse.
Horizontal Sync Pulse.
Rev. B | Page 11 of 112
AD9920A
Pin No.
E11
K9
K10
L10
B11
K11
C9
Mnemonic
SYNC/RST
SL
SDATA
SCK
VDR_EN
XSUBCNT
SRSW
LEGEN
CLI
Type1 Description
DO
DI
DI
SYNC Pin (Internal Pull-Up Resistor)/External Reset Input (Active Low).
3-Wire Serial Load Pulse (Internal Pull-Up Resistor).
3-Wire Serial Data.
DI
3-Wire Serial Clock.
DI
Enable V-Outputs When High.
DI
XSUBCNT Input to SUBCK Buffer.
DI
DI
Slew Rate Control Enable. Tie to ground to disable.
Legacy Mode Enable Bar. Tie to ground for legacy 18-channel mode.
J6
J5
DI
Reference Clock Input.
K5
CLO
GPO1
GPO2
GPO3
GPO4
GPO7
GPO8
D0
D1
D2
D3
D4
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
VO3
VO3
VO3
VO3
VO3
VO3
Clock Output for Crystal.
General-Purpose Output.
General-Purpose Output.
General-Purpose Output.
General-Purpose Output.
General-Purpose Output.
General-Purpose Output.
Data Output (LSB).
Data Output.
Data Output.
Data Output.
Data Output.
Data Output.
Data Output.
Data Output.
Data Output.
Data Output.
Data Output.
Data Output (MSB).
Data Clock Output.
CCD Horizontal Clock.
CCD Horizontal Clock.
CCD Horizontal Clock.
CCD Horizontal Clock.
CCD Horizontal Clock.
CCD Horizontal Clock.
CCD Horizontal Clock.
CCD Horizontal Clock.
CCD Horizontal Clock.
CCD Reset Gate Clock.
F10
H9
G10
F11
H10
J11
B9
C6
C7
A8
A7
B7
D5
D6
D7
D8
B6
A6
A5
B4
A4
A3
B3
D1
D2
F1
D9
D10
D11
DCLK
H1
H2
H3
H4
H5
H6
H7
H8
HL
RG
V1A
V1B
V2A
V2B
V3A
V3B
F2
H1
H2
K1
K2
L2
L4
G9
G6
G5
E9
J9
F6
CCD Vertical Transfer Clock. Three-level output (XV1 + XV16).
CCD Vertical Transfer Clock. Three-level output (XV1 + XV17).
CCD Vertical Transfer Clock. Three-level output (XV2 + XV18).
CCD Vertical Transfer Clock. Three-level output (XV2 + XV19).
CCD Vertical Transfer Clock. Three-level output (XV3 + XV20).
CCD Vertical Transfer Clock. Three-level output. LEGEN is low, XV3 + XV21. LEGEN is high,
XV23 + XV21.
F5
E5
V4
V5
VO3
VO3
CCD Vertical Transfer Clock. Three-level output (XV4 + XV22).
CCD Vertical Transfer Clock. Three-level output. LEGEN is low, XV5 + XV23. LEGEN is high,
XV5 + GPO5.
D10
V6
VO3
CCD Vertical Transfer Clock. Three-level output. LEGEN is low, XV6 + XV24. LEGEN is high,
XV6 + GPO6.
F9
F7
V7
V8
VO2
VO2
CCD Vertical Transfer Clock. Two-level output (XV7).
CCD Vertical Transfer Clock. Two-level output (XV8).
Rev. B | Page 12 of 112
AD9920A
Pin No.
D9
C4
C5
B5
E6
E7
C8
J8
Mnemonic
V9
V10
V11
V12
V13
V14
V15
V16
Type1 Description
VO2
VO2
VO2
VO2
VO2
VO2
VO2
VO2
CCD Vertical Transfer Clock. Two-level output (XV9).
CCD Vertical Transfer Clock. Two-level output (XV10).
CCD Vertical Transfer Clock. Two-level output (XV11).
CCD Vertical Transfer Clock. Two-level output (XV12).
CCD Vertical Transfer Clock. Two-level output (XV13).
CCD Vertical Transfer Clock. Two-level output (XV14).
CCD Vertical Transfer Clock. Two-level output (XV15).
CCD Vertical Transfer Clock. Two-level output (XV24). Available only when LEGEN is high
(19-channel mode).
G7
SUBCK
NC
VO3
CCD Substrate Clock Output.
Not Internally Connected.
A1, A11, B8,
B10, J10, L1,
L11
1 AI = analog input; AO = analog output; DI = digital input; DO = digital output; DIO = digital input/output; P = power; VO2 = vertical driver output, two-level;
VO3 = vertical driver output, three-level.
Rev. B | Page 13 of 112
AD9920A
TYPICAL PERFORMANCE CHARACTERISTICS
400
3.0
2.5
2.0
1.5
1.0
0.5
0
3.3V, 2.0V
350
300
250
200
150
100
50
3.0V, 1.8V
2.7V, 1.6V
–0.5
–1.0
0
18
32
40
0
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
4.0k
FREQUENCY (MHz)
ADC OUTPUT CODE
Figure 5. AFETG Power vs. Frequency (V-Driver Not Included);
Figure 7. Typical System Integral Nonlinearity (INL) Performance
AVDD = TCVDD = DVDD = 1.8 V, All Other Supplies at 2.7 V, 3.0 V, or 3.3 V
1.0
0.8
50
45
40
35
0.6
0.4
0.2
30
–3dB CDS GAIN
0
25
20
15
10
5
0dB CDS GAIN
+3dB CDS GAIN
+6dB CDS GAIN
–0.2
–0.4
–0.6
–0.8
–1.0
0
0
0.5k
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
4.0k
0
10
20
30
40
50
60
ADC OUTPUT CODE
TOTAL GAIN — CDS + VGA (dB)
Figure 6. Typical Differential Nonlinearity (DNL) Performance
Figure 8. Output Noise vs. Total Gain (CDS + VGA)
Rev. B | Page 14 of 112
AD9920A
EQUIVALENT CIRCUITS
IOVDD
AVDD
330Ω
R
DIGITAL
INPUTS
CCDIN
AVSS
AVSS
IOVSS
Figure 9. CCDIN
Figure 12. Digital Inputs
HVDD OR
RGVDD
DVDD
DRVDD
DATA
RG, HL, H1 TO H8
THREE-
STATE
D0 TO D11
OUTPUT
THREE-STATE
DVSS
DRVSS
HVSS OR
RGVSS
Figure 10. Digital Data Outputs
Figure 13. H1 to H8, HL, RG Drivers
VDVDD
VDVDD
3.5k
Ω
3.5k
Ω
XSUBCNT
VDR_EN
R
VDVSS
VDVSS
Figure 11. XSUBCNT
Figure 14. VDR_EN
Rev. B | Page 15 of 112
AD9920A
TERMINOLOGY
Differential Nonlinearity (DNL)
Power Supply Rejection (PSR)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. It is often
specified in terms of resolution for which no missing codes are
guaranteed. No missing codes guaranteed to 12-bit resolution
indicates that all 4096 codes, each for its respective input, must
be present over all operating conditions.
The PSR is measured with a step change applied to the supply
pins. The PSR specification is calculated from the change in the
data outputs for a given step change in the supply voltage.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage using the relationship
1 LSB = (ADC Full Scale/2n Codes)
where n is the bit resolution of the ADC.
For the AD9920A, 1 LSB = 0.244 mV.
Integral Nonlinearity (INL)
INL is defined as the maximum deviation of the actual analog
output from the ideal output, determined by a straight line
drawn from zero scale to full scale.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9920A from a true straight
line. The point used as zero scale occurs 0.5 LSB before the first
code transition. Positive full scale is defined as a level 1 LSB and
0.5 LSB beyond the last code transition. The deviation is measured
from the middle of each particular output code to the true straight
line. The error is then expressed as a percentage of the 2 V ADC
full-scale signal. The input signal is always appropriately amplified
to fill the ADC full-scale range.
Rev. B | Page 16 of 112
AD9920A
THEORY OF OPERATION
Figure 15 shows the typical system block diagram for the AD9920A
in master mode. The CCD output is processed by the AD9920A
AFE circuitry, which consists of a CDS, black level clamp, and
ADC. The digitized pixel information is sent to the digital image
processor chip, which performs the postprocessing and com-
pression. To operate the CCD, all CCD timing parameters are
programmed into the AD9920A from the system microprocessor
through the 3-wire serial interface. From the master clock, CLI,
provided by the image processor or external crystal, the AD9920A
generates the CCD horizontal and vertical clocks and the internal
AFE clocks. External synchronization is provided by a sync pulse
from the microprocessor, which resets the internal counters and
resyncs the VD and HD outputs.
The AD9920A includes programmable general-purpose outputs
(GPOs) that can trigger mechanical shutter and strobe (flash)
circuitry.
Figure 16 and Figure 17 show the maximum horizontal and
vertical counter dimensions for the AD9920A. All internal
horizontal and vertical clocking is controlled by these counters,
which specify line and pixel locations. Maximum HD length is
16,384 pixels per line, and maximum VD length is 8192 lines
per field.
MAXIMUM COUNTER DIMENSIONS
14-BIT HORIZONTAL = 16,384 PIXELS MAXIMUM
V1A TO V16, SUBCK
H1 TO H8, HL,
RG, VSUB
13-BIT VERTICAL = 8192 LINES MAXIMUM
D0 TO D11
CCDIN
DIGITAL
IMAGE
PROCESSING
ASIC
DCLK
HD, VD
CLI
CCD
AD9920A
AFETG
V-DRIVER
GPO1 TO GPO8
SERIAL
INTERFACE
MICROPROCESSOR
SYNC
Figure 16. Vertical and Horizontal Counters
Figure 15. Typical System Block Diagram, Master Mode
H-COUNTER BEHAVIOR IN SLAVE MODE
Alternatively, the AD9920A can be operated in slave mode. In
this mode, the VD and HD are provided externally from the
image processor, and all AD9920A timing is synchronized with
VD and HD.
In the AD9920A, the internal H-counter holds at its maximum
count of 16,383 instead of rolling over. This feature allows the
AD9920A to be used in applications that contain a line length
greater than 16,384 pixels. Although no programming values
for the vertical and horizontal signals are available beyond 8191,
the H, RG, and AFE clocking continues to operate, sampling the
remaining pixels on the line.
The H-drivers for H1 to H8, HL, and RG are included in the
AD9920A, allowing these clocks to be directly connected to the
CCD. An H-driver voltage of up to 3.6 V is supported. V1A to
V16 and SUBCK vertical clocks are included as well, allowing
the AD9920A to provide all horizontal and vertical clocks
necessary to clock data out of a CCD.
MAXIMUM VD LENGTH IS 8192 LINES
VD
MAXIMUM HD LENGTH IS 16,384 PIXELS
HD
CLI
Figure 17. Maximum VD/HD Dimensions
Rev. B | Page 17 of 112
AD9920A
divides the master clock period into 64 steps or edge positions.
Using a 40.5 MHz CLI frequency, the edge resolution of the
Precision Timing core is approximately 0.4 ns. If a 1× system clock
is not available, it is possible to use a 2× reference clock by pro-
gramming the CLIDIVIDE register (AFE Register Address 0x0D).
The AD9920A then internally divides the CLI frequency by 2.
HIGH SPEED PRECISION TIMING CORE
The AD9920A generates high speed timing signals using the
flexible Precision Timing core. This core is the foundation for
generating the timing used for both the CCD and the AFE; it
includes the reset gate (RG), horizontal drivers (H1 to H8, HL),
and SHP/SHD sample clocks. A unique architecture makes it
routine for the system designer to optimize image quality by
providing precise control over the horizontal CCD readout
and the AFE correlated double sampling.
High Speed Clock Programmability
Figure 19 shows when the high speed clocks RG, H1 to H8, HL,
SHP, and SHD are generated. The RG pulse has programmable
rising and falling edges and can be inverted using the polarity
control. Horizontal Clock H1 has programmable rising and falling
edges and polarity control. In HCLK Mode 1, H3, H5, and H7
are equal to H1. H2, H4, H6, and H8 are always inverses of H1.
The high speed timing of the AD9920A operates the same
way in either master or slave mode configuration. For more
information on synchronization and pipeline delays, see
the Power-Up Sequence for Master Mode section.
The edge location registers are each six bits wide, allowing the
selection of all 64 edge locations. Figure 23 shows the default
timing locations for all of the high speed clock signals.
Timing Resolution
The Precision Timing core uses a 1× master clock input as a
reference (CLI). This clock should be the same as the CCD pixel
clock frequency. Figure 18 illustrates how the internal timing core
POSITION
CLI
P[0]
P[16]
P[32]
P[48]
P[64] = P[0]
...
tCLIDLY
...
1 PIXEL
PERIOD
tCONV
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
t
= 6 ns TYP).
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
CLIDLY
Figure 18. High Speed Clock Resolution from CLI, Master Clock Input
1
CCD
2
SIGNAL
3
5
4
RG
6
8
H1, H3, H5, H7
H2, H4, H6, H8
7
HL
PROGRAMMABLE CLOCK POSITIONS:
1
SHP SAMPLE LOCATION.
2
SHD SAMPLE LOCATION.
3
RG RISING EDGE.
4
RG FALLING EDGE.
5
H1 RISING EDGE.
6
H1 FALLING EDGE.
7
HL RISING EDGE.
8
HL FALLING EDGE.
Figure 19. High Speed Clock Programmable Locations (HCLKMODE = 0x01)
Rev. B | Page 18 of 112
AD9920A
Table 10 shows a comparison of the different programmable
H-Driver and RG Outputs
settings for each HCLK mode. Figure 20 and Figure 21 show the
settings for HCLK Mode 2 and HCLK Mode 3, respectively.
In addition to the programmable timing positions, the AD9920A
features on-chip output drivers for the RG, HL, and H1 to H8
outputs. These drivers are powerful enough to drive the CCD
inputs directly. The H-driver and RG current can be adjusted for
optimum rise/fall time for a particular load by using the drive
strength control registers (Address 0x36 and Address 0x37). The
3-bit drive setting for each H1 to H8 output is adjustable in
4.3 mA increments: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 17.3 mA, 5 = 21.6 mA, 6 = 25.9 mA, and 7 = 30.2 mA.
It is recommended that all H1 to H8 outputs on the AD9920A be
used together for maximum flexibility in drive strength settings.
A typical CCD with H1 and H2 inputs should have only the
AD9920A H1, H3, H5, and H7 outputs connected together to
drive the CCD H1 and should have only the AD9920A H2, H4,
H6, and H8 outputs connected together to drive the CCD H2.
In 3-phase HCLK mode, only six of the HCLK outputs are used,
with two outputs driving each of the three phases:
The 3-bit drive settings for the HL and RG outputs are also
adjustable in 4.3 mA increments, but with a maximum drive
strength of 17.3 mA: 0 = off, 1 = 4.3 mA, 2 = 8.6 mA, 3 = 12.9 mA,
4 = 4.3 mA, 5 = 8.6 mA, 6 = 12.9 mA, and 7 = 17.3 mA.
•
•
•
H1 and H2 are connected to CCD Phase 1.
H5 and H6 are connected to CCD Phase 2.
H7 and H8 are connected to CCD Phase 3.
As shown in Figure 19, when HCLK Mode 1 is used, the H2,
H4, H6, and H8 outputs are inverses of the H1, H3, H5, and H7
outputs. Using the HCLKMODE register (Address 0x24,
Bits[4:0]), it is possible to select a different configuration.
Table 9. Timing Core Register Parameters for H1, H2, HL, RG, SHP, and SHD
Parameter
Length (Bits)
Range
Description
Positive Edge
Negative Edge
Sampling Location
Drive Strength
6
6
6
3
0 to 63 edge location
0 to 63 edge location
0 to 63 edge location
0 to 7 current steps
Positive edge location for H1, H2, HL, H3P1, and RG.
Negative edge location for H1, H2, HL, H3P1, and RG.
Sampling location for internal SHP and SHD signals.
Drive current for H1 to H8, HL, and RG outputs (4.3 mA per step).
Table 10. HCLK Modes, Selected by Address 0x24, Bits[4:0]
HCLKMODE
Register Value
Description
Mode 1
0x01
H1 edges are programmable with H3 = H5 = H7 = H1, H2 = H4 = H6 = H8 = inverse of H1.
Mode 2
0x02
H1 edges are programmable with H3 = H5 = H7 = H1.
H2 edges are programmable with H4 = H6 = H8 = H2.
Mode 3
0x04
0x10
H1 edges are programmable with H3 = H1 and H2 = H4 = inverse of H1.
H5 edges are programmable with H7 = H5 and H6 = H8 = inverse of H5.
3-Phase Mode
H1 edges are programmable using Address 0x33 and H2 = H1 (Phase 1).
H5 edges are programmable using Address 0x31 and H6 = H5 (Phase 2).
H7 edges are programmable using Address 0x30 and H8 = H7 (Phase 3).
Invalid Selection
All other values Invalid register settings. Do not use.
Rev. B | Page 19 of 112
AD9920A
1
2
H1, H3, H5, H7
H2, H4, H6, H8
4
3
H1 TO H8 PROGRAMMABLE LOCATIONS:
1
H1 RISING EDGE.
2
H1 FALLING EDGE.
3
H2 RISING EDGE.
4
H2 FALLING EDGE.
Figure 20. HCLK Mode 2 Operation
1
2
H1, H3
H2, H4
3
4
H5, H7
H6, H8
H1 TO H8 PROGRAMMABLE LOCATIONS:
1
2
3
4
H1 RISING EDGE.
H1 FALLING EDGE.
H5 RISING EDGE.
H5 FALLING EDGE.
Figure 21. HCLK Mode 3 Operation
2
1
H1, H2
4
3
H5, H6
5
6
H7, H8
H1 TO H8 PROGRAMMABLE LOCATIONS:
1
H1 FALLING EDGE.
H1 RISING EDGE.
H5 FALLING EDGE.
H5 RISING EDGE.
H7 RISING EDGE.
H7 FALLING EDGE.
2
3
4
5
6
Figure 22. 3-Phase HCLK Mode Operation
Rev. B | Page 20 of 112
AD9920A
POSITION
CLI
P[0]
P[16]
P[32]
P[48]
P[64] = P[0]
RGr[0]
H1r[0]
RGf[16]
RG
H1
H2
H1f[32]
tSHDINH
tSHDINH
tS2
tS1
CCD
SIGNAL
SHPLOC[32]
tSHPINH
SHP
62
50
SHDLOC[0]
1
SHD
12
DOUTPHASEP
tDOUTINH
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
2. CERTAIN POSITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS.
3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE.
4. THE t
5. THE t
AREA FROM 50 TO 62 ONLY APPLIES IN SLAVE MODE.
AREA WILL APPLY TO EITHER H1 RISING OR FALLING EDGE, DEPENDING ON THE VALUE OF THE
SHPINH
SHDINH
H1HBLK MASKING POLARITY.
6. THE t
AREA CAN ALSO BE CHANGED TO A t AREA IF THE H1HBLKRETIME BIT = 1.
SHDINH
SHPINH
Figure 23. High Speed Timing Default Locations
TAP POSITION
PHASE 1
P[0]
P[16]
P[32]
P[48]
P[64] = P[0]
SHDINH/SHPINH
SHDINH/SHPINH
PHASE 2
PHASE 3
SHDINH/SHPINH
RGr[0]
HLr[0]
RGf[16]
RG
HL
HLf[32]
tS1
CCD
SIGNAL
SHPLOC[32]
SHP
SHD
SHDLOC[0]
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN USING 3-PHASE HBLK MODE.
2. THE RISING EDGE OF EACH HCLK PHASE HAS AN ASSOCIATED SHDINH.
3. WHEN THE HBLK RETIME BITS (0x35 [3:0]) ARE ENABLED, THE INHIBITED AREA BECOMES SHPINH.
4. WHEN THE HBLK MASK LEVEL FOR PHASE 1, 2, OR 3 IS CHANGED TO LOW, THE INHIBIT AREA IS
REFERENCED TO THE HCLK FALLING EDGE, INSTEAD OF THE HCLK RISING EDGE.
Figure 24. High Speed Timing Typical Locations, 3-Phase HCLK Mode
Rev. B | Page 21 of 112
AD9920A
Normally, the data output and DCLK signals track in phase,
based on the contents of the DOUTPHASE registers. The DCLK
output phase can also be held fixed with respect to the data out-
puts by setting the DCLKMODE register high (Address 0x39,
Bit 16). In this mode, the DCLK output remains at a fixed phase
equal to a delayed version of CLI, and the data output phase
remains programmable.
DIGITAL DATA OUTPUTS
The AD9920A data output and DCLK phase are programmable
using the DOUTPHASE registers (Address 0x39, Bits[13:0]).
DOUTPHASEP (Bits[5:0]) selects any edge location from 0 to
63, as shown in Figure 25. DOUTPHASEN (Bits[13:8]) does
not actually program the phase of the data outputs but is used
internally and should always be programmed to a value of
DOUTPHASEP plus 32 edges. For example, if DOUTPHASEP
is set to 0, DOUTPHASEN should be set to 32 (0x20).
The pipeline delay through the AD9920A is shown in Figure 26.
After the CCD input is sampled by SHD, there is a 16-cycle
delay until the data is available.
P[48]
P[0]
P[64] = P[0]
P[16]
P[32]
PIXEL
PERIOD
DCLK
tOD
DOUT
NOTES
1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 64 DIFFERENT LOCATIONS.
3. DCLK CAN BE INVERTED WITH RESPECT TO DOUT BY USING THE DCLKINV REGISTER.
Figure 25. Digital Output Phase Adjustment Using DOUTPHASEP Register
CLI
t
CLIDLY
N + 15 N + 16 N + 17
N
N + 1
N + 2
N + 5
N + 6
N + 7
N + 8
N + 9 N + 10 N + 11 N + 12 N + 13 N + 14
N + 3
N + 4
CCDIN
SAMPLE PIXEL N
SHD
(INTERNAL)
ADC DOUT
(INTERNAL)
N – 17 N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10
tDOUTINH
N – 9
N – 8
N – 7
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
N + 1
DCLK
DOUT
PIPELINE LATENCY = 16 CYCLES
N – 17 N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N – 9 N – 8 N – 7
N – 6
N – 5
N – 4
N – 3
N – 2
N – 1
N
N + 1
NOTES
1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.
2. HIGHER VALUES OF SHD AND/OR DOUTPHASE SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
3. RECOMMENDED VALUE FOR DOUTPHASE IS TO USE SHPLOC OR UP TO 15 EDGES FOLLOWING SHPLOC.
Figure 26. Digital Data Output Pipeline Delay
Rev. B | Page 22 of 112
AD9920A
CLPOB and PBLK Masking Areas
HORIZONTAL CLAMPING AND BLANKING
Additionally, the AD9920A allows the CLPOB and PBLK signals
to be disabled in certain lines in the field without changing any
of the existing CLPOB pattern settings.
The horizontal clamping and blanking pulses of the AD9920A are
fully programmable to suit a variety of applications. Individual
control is provided for CLPOB, PBLK, and HBLK in the different
regions of each field. This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout to
accommodate different image transfer timing and high speed
line shifts.
To use CLPOB (or PBLK) masking, the CLPMASKSTART
(PBLKMASKSTART) and CLPMASKEND (PBLKMASKEND)
registers are programmed to specify the start and end lines in
the field where the CLPOB (PBLK) patterns are ignored. The
three sets of start and end registers allow up to three CLPOB
(PBLK) masking areas to be created.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 27. These two signals are programmed inde-
pendently using the registers shown in Table 11. The start polarity
for the CLPOB (or PBLK) signal is CLPOBPOL (PBLKPOL), and
the first and second toggle positions of the pulse are CLPOBTOG1
(PBLKTOG1) and CLPOBTOG2 (PBLKTOG2). Both signals
are active low and should be programmed accordingly.
The CLPOB and PBLK masking registers are not specific to a
certain V-sequence; they are always active for any existing field
of timing. During operation, to disable the CLPOB masking
feature, these registers must be set to the maximum value of
0x1FFF or a value greater than the programmed VD length.
Note that to disable CLPOB (or PBLK) masking during power-up,
it is recommended that CLPMASKSTART (PBLKMASKSTART)
be set to 8191 and that CLPMASKEND (PBLKMASKEND) be
set to 0. This prevents any accidental masking caused by register
update events.
A separate pattern for CLPOB and PBLK can be programmed
for each vertical sequence. As described in the Vertical Timing
Generation section, several V-sequences can be created, each
containing a unique pulse pattern for CLPOB and PBLK.
Figure 57 shows how the sequence change positions divide the
readout field into regions. By assigning a different V-sequence
to each region, the CLPOB and PBLK signals can change with
each change in the vertical timing.
Table 11. CLPOB and PBLK Pattern Registers
Length
Register
(Bits)
Range
Description
CLPOBPOL
1
High/low
Starting polarity of CLPOB for each V-sequence.
PBLKPOL
1
High/low
Starting polarity of PBLK for each V-sequence.
CLPOBTOG1
CLPOBTOG2
PBLKTOG1
13
13
13
13
13
13
13
13
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 line location
0 to 8191 line location
0 to 8191 line location
0 to 8191 line location
First CLPOB toggle position within line for each V-sequence.
Second CLPOB toggle position within line for each V-sequence.
First PBLK toggle position within line for each V-sequence.
Second PBLK toggle position within line for each V-sequence.
CLPOB masking area—starting line within field (maximum of three areas).
CLPOB masking area—ending line within field (maximum of three areas).
PBLK masking area—starting line within field (maximum of three areas).
PBLK masking area—ending line within field (maximum of three areas).
PBLKTOG2
CLPMASKSTART
CLPMASKEND
PBLKMASKSTART
PBLKMASKEND
Rev. B | Page 23 of 112
AD9920A
HD
2
3
CLPOB
PBLK
1
ACTIVE
ACTIVE
PROGRAMMABLE SETTINGS:
1
2
3
START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW).
FIRST TOGGLE POSITION.
SECOND TOGGLE POSITION.
Figure 27. Clamp and Preblank Pulse Placement
NO CLPOB SIGNAL
FOR LINES 6 TO 8
NO CLPOB SIGNAL
FOR LINE 600
VD
0
1
2
597 598
HD
CLPOB
CLPMASKSTART1 = 6
CLPMASKEND1 = 9
CLPMASKSTART2 = 600
CLPMASKEND2 = 601
Figure 28. CLPOB Masking Example
Individual HBLK Patterns
HBLK Mode 0 Operation
The HBLK programmable timing shown in Figure 29 is similar to
the timing of CLPOB and PBLK; however, there is no start polarity
control. Only the toggle positions are used to designate the start
and stop positions of the blanking period. Additionally, separate
masking polarity controls for each H-clock phase designate the
polarity of the horizontal clock signals during the blanking period.
Setting HBLKMASK_H1 high sets H1—and, therefore, H3, H5,
and H7—low during the blanking, as shown in Figure 30. As with
the CLPOB and PBLK signals, HBLK registers are available in
each V-sequence, allowing different blanking signals to be used
with different vertical timing sequences.
There are six toggle positions available for HBLK. Normally, only
two of the toggle positions are used to generate the standard
HBLK interval. However, the additional toggle positions can be
used to generate special HBLK patterns, as shown in Figure 31.
The pattern in this example uses all six toggle positions to gen-
erate two extra groups of pulses during the HBLK interval. By
changing the toggle positions, different patterns can be created.
Separate toggle positions are available for even and odd lines. If
alternation is not needed, the same values should be loaded into
the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines.
Multiple repeats of the HBLK signal are enabled by setting the
HBLKLEN and HBLKREP registers along with the six toggle
positions (four are shown in Figure 32).
The AD9920A supports two modes of HBLK operation. HBLK
Mode 0 supports basic operation and pixel mixing HBLK oper-
ation. HBLK Mode 1 supports advanced HBLK operation.
Generating HBLK Line Alternation
The following sections describe each mode in detail. Register
parameters are described in detail in Table 12.
HBLK Mode 0 provides the ability to alternate different HBLK
toggle positions on even and odd lines. HBLK line alternation
can be used alone or in conjunction with V-pattern odd/even
alternation (see the Generating Line Alternation for V-Sequences
and HBLK section). Separate toggle positions are available for
even and odd lines. If even/odd line alternation is not needed,
the same values should be loaded into the registers for even
(HBLKTOGE) and odd (HBLKTOGO) lines.
Rev. B | Page 24 of 112
AD9920A
HD
HBLKSTART
HBLKEND
BLANK
BLANK
HBLK
BASIC HBLK PULSE IS GENERATED USING HBLKSTART AND HBLKEND REGISTERS
Figure 29. Typical Horizontal Blanking Pulse Placement (HBLK_MODE = 0)
HD
HBLK
H1/H3/H5/H7
THE POLARITY OF H1/H3/H5/H7 DURING BLANKING IS PROGRAMMABLE
(H2/H4/H6/H8 AND HL ARE SEPARATELY PROGRAMMABLE)
H1/H3/H5/H7
H2/H4/H6/H8
Figure 30. HBLK Masking Polarity Control
HBLKTOGE2
HBLKTOGE5
HBLKTOGE6
HBLKEND
HBLKTOGE4
HBLKTOGE3
HBLKTOGE1
HBLKSTART
HBLK
H1/H3
H2/H4
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS
Figure 31. Using Multiple Toggle Positions for HBLK (HBLK_MODE = 0)
HBLKTOGE2
HBLKTOGE1 HBLKTOGE3
HBLKTOGE4
HBLKSTART
HBLKEND
HBLK
HBLKLEN
HBLKREP = 3
H1/H3
H2/H4
HBLKREP NUMBER 1
HBLKREP NUMBER 2
HBLKREP NUMBER 3
H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS
Figure 32. HBLK Repeating Pattern Using HBLK_MODE = 0
Rev. B | Page 25 of 112
AD9920A
Table 12. HBLK Pattern Registers
Length
(Bits)
Register
Range
Description
HBLK_MODE
2
0 to 1 HBLK modes
Enables different HBLK toggle position operations.
0 = normal mode; six toggle positions available for even and odd lines.
If even/odd alternation is not needed, set toggles for even and odd lines to the
same value. In addition to the six toggle positions, the HBLKSTART, HBLKEND,
HBLKLEN, and HBLKREP registers can be used to generate HBLK patterns. If even/
odd alternation is not needed, set toggles for even and odd lines to the same value.
1 = advanced HBLK mode; divides HBLK interval into six repeat areas.
Uses HBLKSTARTA/B/C and RAxHxREPA/B/C registers; the latter, depending on the
mode of operation, are stored in the HBLKTOGO1 to HBLKTOGO6 and HBLKTOGE1
to HBLKTOGE6 registers (Address 0x19 to Address 0x1E; see Table 63).
2 = test mode only; do not access.
3 = test mode only; do not access.
HBLKSTART
HBLKEND
HBLKLEN
13
13
13
13
1
1
1
1
0 to 8191 pixel location Start location for HBLK in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixel location End location for HBLK in HBLK Mode 0 and HBLK Mode 1.
0 to 8191 pixels
0 to 8191 repetitions
High/low
High/low
High/low
HBLK length in HBLK Mode 0 and HBLK Mode 1.
Number of HBLK repetitions in HBLK Mode 0 and HBLK Mode 1.
Masking polarity for H1/H3/H5/H7 during HBLK.
Masking polarity for H2/H4/H6/H8 during HBLK.
Masking polarity for HL during HBLK.
HBLKREP
HBLKMASK_H1
HBLKMASK_H2
HBLKMASK_HL
HBLKMASK_H3P
HBLKTOGO1
HBLKTOGO2
HBLKTOGO3
HBLKTOGO4
HBLKTOGO5
HBLKTOGO6
HBLKTOGE1
HBLKTOGE2
HBLKTOGE3
HBLKTOGE4
HBLKTOGE5
HBLKTOGE6
High/low
Masking polarity for H3P during 3-phase mode during HBLK.
13
13
13
13
13
13
13
13
13
13
13
13
0 to 8191 pixel location First HBLK toggle position for odd lines in HBLK Mode 0.
0 to 8191 pixel location Second HBLK toggle position for odd lines in HBLK Mode 0.
0 to 8191 pixel location Third HBLK toggle position for odd lines in HBLK Mode 0.
0 to 8191 pixel location Fourth HBLK toggle position for odd lines in HBLK Mode 0.
0 to 8191 pixel location Fifth HBLK toggle position for odd lines in HBLK Mode 0.
0 to 8191 pixel location Sixth HBLK toggle position for odd lines in HBLK Mode 0.
0 to 8191 pixel location First HBLK toggle position for even lines in HBLK Mode 0.
0 to 8191 pixel location Second HBLK toggle position for even lines in HBLK Mode 0.
0 to 8191 pixel location Third HBLK toggle position for even lines in HBLK Mode 0.
0 to 8191 pixel location Fourth HBLK toggle position for even lines in HBLK Mode 0.
0 to 8191 pixel location Fifth HBLK toggle position for even lines in HBLK Mode 0.
0 to 8191 pixel location Sixth HBLK toggle position for even lines in HBLK Mode 0.
0 to 15 HCLK pulses for HBLK Repeat Area 0. Number of H1 repetitions for HBLKSTARTA/B/C in
RA0H1REPA/B/C 12
each A, B, and C
HBLK Mode 1 for even lines; odd lines defined using HBLKALT_PAT.
Bits[3:0]: RA0H1REPA. Number of H1 pulses following HBLKSTARTA.
Bits[7:4]: RA0H1REPB. Number of H1 pulses following HBLKSTARTB.
Bits[11:8]: RA0H1REPC. Number of H1 pulses following HBLKSTARTC.
RA1H1REPA/B/C 12
RA2H1REPA/B/C 12
RA3H1REPA/B/C 12
RA4H1REPA/B/C 12
RA5H1REPA/B/C 12
RA0H2REPA/B/C 12
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
HBLK Repeat Area 1. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 2. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 3. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 4. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 5. Number of H1 repetitions for HBLKSTARTA/B/C.
0 to 15 HCLK pulses for HBLK Repeat Area 0. Number of H2 repetitions for HBLKSTARTA/B/C in
each A, B, and C
HBLK Mode 1 for even lines; odd lines defined using HBLKALT_PAT.
Bits[3:0]: RA0H2REPA. Number of H2 pulses following HBLKSTARTA.
Bits[7:4]: RA0H2REPB. Number of H2 pulses following HBLKSTARTB.
Bits[11:8]: RA0H2REPC. Number of H2 pulses following HBLKSTARTC.
RA1H2REPA/B/C 12
RA2H2REPA/B/C 12
RA3H2REPA/B/C 12
RA4H2REPA/B/C 12
RA5H2REPA/B/C 12
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
HBLK Repeat Area 1. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 2. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 3. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 4. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 5. Number of H2 repetitions for HBLKSTARTA/B/C.
Rev. B | Page 26 of 112
AD9920A
Length
(Bits)
Register
Range
Description
HBLKSTARTA
HBLKSTARTB
HBLKSTARTC
HBLKALT_PAT0
13
13
13
3
0 to 8191 pixel location HBLK Repeat Area Start Position A for HBLK Mode 1. Set to 8191 if not used.
0 to 8191 pixel location HBLK Repeat Area Start Position B for HBLK Mode 1. Set to 8191 if not used.
0 to 8191 pixel location HBLK Repeat Area Start Position C for HBLK Mode 1. Set to 8191 if not used.
0 to 5 even repeat area HBLK Mode 1, Repeat Area 0 pattern for odd lines. Selected from previously
defined even line repeat areas.
HBLKALT_PAT1
HBLKALT_PAT2
HBLKALT_PAT3
HBLKALT_PAT4
HBLKALT_PAT5
3
3
3
3
3
0 to 5 even repeat area HBLK Mode 1, Repeat Area 1 pattern for odd lines.
0 to 5 even repeat area HBLK Mode 1, Repeat Area 2 pattern for odd lines.
0 to 5 even repeat area HBLK Mode 1, Repeat Area 3 pattern for odd lines.
0 to 5 even repeat area HBLK Mode 1, Repeat Area 4 pattern for odd lines.
0 to 5 even repeat area HBLK Mode 1, Repeat Area 5 pattern for odd lines.
1 PIXEL
1 PIXEL
1 PIXEL
1 PIXEL
B1
A1
PHASE 1
A2
B2
PHASE 2
PHASE 3
B3
A3
INTERNAL
DIGITAL
CLOCK
A
MASTER
BLANKING
SIGNAL
B
MASK LEVEL = HIGH
H1/H2
H5/H6
H7/H8
MASK LEVEL = LOW
MASK LEVEL = HIGH
BLANKING
Figure 33. Example of Correct HBLK Behavior
Figure 33 shows the desired HBLK behavior for all three phases
when the internal digital clock is located before the Phase 3 rising
edge. Figure 34 shows the effect of changing the internal clock
phase (changing SHDLOC) to a different location. This causes
incorrect blanking on Phase 1 and Phase 2.
HBLK Fine Retime Control
An additional set of register bits is available for use during
3-phase HCLK mode to provide fine adjustment of each HCLK
phase during the HBLK interval. The fine retime bits (Address 0x35,
Bits[23:20]) allow for the adjustment of the correct number of
HCLK cycles during the HBLK interval.
Figure 35 shows how the fine retime bits for Phase 1 and Phase 2
are used to generate the correct blanking behavior, matching the
result shown in Figure 33.
Figure 33 through Figure 35 show the different settings that can
be used based on the location of the HBLK toggle positions, the
location of the internal digital clock, and the masking polarity
of the different HCLK phases. By using the fine retime bits, the
exact pulse behavior for each HCLK phase can be generated.
Rev. B | Page 27 of 112
AD9920A
1 PIXEL
1 PIXEL
1 PIXEL
1 PIXEL
1 PIXEL
A1
B1
PHASE 1
PHASE 2
PHASE 3
B2
A2
A3
B3
INTERNAL
DIGITAL
CLOCK
A
B
MASTER
BLANKING
SIGNAL
MASK LEVEL = HIGH
H1/H2
H5/H6
H7/H8
MASK LEVEL = LOW
MASK LEVEL = HIGH
BLANKING
Figure 34. Incorrect HBLK Behavior Caused by Internal Clock Position
1 PIXEL
1 PIXEL
1 PIXEL
1 PIXEL
1 PIXEL
FINE RETIME
B1
FINE RETIME
PHASE 1
A1
FINE RETIME
FINE RETIME
A3
PHASE 2
PHASE 3
A2
B2
B3
INTERNAL
DIGITAL
CLOCK
A
B
MASTER
BLANKING
SIGNAL
MASK LEVEL = HIGH
H1/H2
H5/H6
MASK LEVEL = LOW
MASK LEVEL = HIGH
H7/H8
BLANKING
Figure 35. Fine Retime on Phase 2 to Achieve Correct HBLK
Rev. B | Page 28 of 112
AD9920A
HBLK Mode 1 Operation
Increasing H-Clock Width During HBLK
HBLK Mode 1 allows more advanced HBLK pattern operation.
If multiple areas of HCLK pulses that are unevenly spaced from
one another are needed, HBLK Mode 1 can be used. Using a
separate set of registers, HBLK Mode 1 can divide the HBLK
region into up to six repeat areas (see Table 12).
The AD9920A allows the H1 to H8 pulse width to be increased
during the HBLK interval. As shown in Figure 36, the H-clock fre-
quency can be reduced by a factor of 1/2, 1/4, 1/6, 1/8, 1/10, 1/12,
and so on, up to 1/30. To enable this feature, the HCLK_WIDTH
register (Address 0x35, Bits[7:4]) is set to a value between 1 and 15.
When this register is set to 0, the wide HCLK feature is disabled.
The reduced frequency occurs for only the H1 to H8 pulses that
are located within the HBLK area.
As shown in Figure 37, each repeat area shares a common
group of toggle positions: HBLKSTARTA, HBLKSTARTB, and
HBLKSTARTC. However, the number of toggles following a start
position can be unique in each repeat area by using the RAxH1REP
and RAxH2REP registers; these registers, depending on the mode
of operation, are stored in the HBLKTOGO1 to HBLKTOGO6
and HBLKTOGE1 to HBLKTOGE6 registers (Address 0x19 to
Address 0x1E; see Table 63).
The HCLK_WIDTH register is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.
Table 13. HCLK Width Register
Register
Length (Bits)
Description
HCLK_WIDTH
4
Controls the H1 to H8 pulse widths during HBLK as a fraction of pixel rate
0 = same frequency as pixel rate; 1 = 1/2 pixel frequency (doubles the HCLK pulse width);
2 = 1/4 pixel frequency; 3 = 1/6 pixel frequency; 4 = 1/8 pixel frequency;
5 = 1/10 pixel frequency; 15 = 1/30 pixel frequency
HBLK
H1/H3
H2/H4
1/f
PIX
2 × (1/f
)
PIX
H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLK_WIDTH REGISTER.
Figure 36. Generating Wide H-Clock Pulses During HBLK Interval
CREATE UP TO THREE GROUPS OF TOGGLES
(A, B, C) COMMON IN ALL REPEAT AREAS
HD
CHANGE NUMBER OF A, B, C PULSES IN ANY
REPEAT AREA USING RAxHxREPx REGISTERS
MASK A, B, C PULSES IN ANY REPEAT
AREA BY SETTING RAxHxREPx = 0
A
B
C
H1
H2
REPEAT AREA 0
REPEAT AREA 3
REPEAT AREA 1 REPEAT AREA 2
REPEAT AREA 4 REPEAT AREA 5
HBLKEND
HBLKSTART
Figure 37. HBLK Mode 1 Registers
Rev. B | Page 29 of 112
AD9920A
HD
HBLKLEN
HBLK
HBLKSTARTA
HBLKSTARTB
ALL RAxHxREPA/B/C REGISTERS = 2 TO CREATE TWO HCLK PULSES
HBLKSTARTC
H1
H2
RA0H1REPB
RA0H1REPC
RA0H2REPC
RA1H1REPA
RA1H1REPB
RA0H1REPA
RA0H2REPA
RA1H1REPC
HBLKSTART
RA1H2REPA RA1H2REPB
RA1H2REPC
RA0H2REPB
HBLKEND
REPEAT AREA 0
REPEAT AREA 1
HBLKREP = 2
TO CREATE TWO REPEAT AREAS
Figure 38. HBLK Mode 1 Operation
As shown in Figure 38, setting the RAxH1REPA/B/C or
RAxH2REPA/B/C register to 0 masks HCLK groups from
appearing in a particular repeat area. Figure 37 shows only two
repeat areas being used, although six are available. It is possible
to program a separate number of repeat area repetitions for H1
and H2, but generally the same value is used for both H1 and
H2. Figure 37 shows an example of RA0H1REPA/B/C =
RA0H2REPA/B/C = RA1H1REPA/B/C = RA1H2REPA/B/C = 2.
Figure 40 shows the basic sequence to be used during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the HBLK time. HBLK
is used during the vertical shift interval.
Because PBLK is used to isolate the CDS input (see the Analog
Preblanking section), the PBLK signal should not be used
during CLPOB operation. The change in the offset behavior
that occurs during PBLK affects the accuracy of the CLPOB
circuitry.
Furthermore, HBLK Mode 1 allows a different HBLK pattern on
even and odd lines. The HBLKSTARTA/B/C registers, as well as
the RAxH1REPA/B/C and RAxH2REPA/B/C registers, define
operation for the even lines. For separate control of the odd lines,
the HBLKALT_PAT registers specify up to six repeat areas on
the odd lines by reordering the repeat areas used for the even
lines. New patterns are not available, but the order of the pre-
viously defined repeat areas on the even lines can be changed
for the odd lines to accommodate advanced CCD operation.
The HBLK, CLPOB, and PBLK parameters are programmed
in the V-sequence registers. More elaborate clamping schemes,
such as adding a separate sequence to clamp in the entire shield
OB lines, can be used. This requires configuring a separate
V-sequence for clocking out the OB lines.
The CLPMASK registers are also useful for disabling the CLPOB
on a few lines without affecting the setup of the clamping
sequences. It is important that CLPOB be used only during
valid OB pixels. During other portions on the frame timing,
such as vertical blanking or SG line timing, the CCD does not
output valid OB pixels. Any CLPOB pulse that occurs during
this time causes errors in clamping operation and changes in
the black level of the image.
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 39 shows an example CCD layout. The horizontal register
contains 28 dummy pixels that occur on each line clocked from
the CCD. In the vertical direction, there are 10 optical black
(OB) lines at the front of the readout and two at the back of the
readout. The horizontal direction has four OB pixels in the
front and 48 OB pixels in the back.
Rev. B | Page 30 of 112
AD9920A
2 VERTICAL
OB LINES
V
EFFECTIVE IMAGE AREA
10 VERTICAL
OB LINES
H
48 OB PIXELS
4 OB PIXELS
HORIZONTAL CCD REGISTER
28 DUMMY PIXELS
Figure 39. Example CCD Configuration
OPTICAL BLACK
OPTICAL BLACK
HD
CCD OUTPUT
VERTICAL SHIFT
DUMMY
EFFECTIVE PIXELS
OPTICAL BLACK
VERTICAL SHIFT
SHP
SHD
H1/H3/H5/H7
H2/H4/H6/H8
HBLK
PBLK
CLPOB
NOTES
1. PBLK ACTIVE (LOW) SHOULD NOT BE USED DURING CLPOB ACTIVE (LOW).
Figure 40. Horizontal Sequence Example
Rev. B | Page 31 of 112
AD9920A
2. The V-pattern groups are used to build the V-sequences
where additional information is added.
VERTICAL TIMING GENERATION
The AD9920A provides a flexible solution for generating vertical
CCD timing and can support multiple CCDs and different system
architectures. The vertical transfer clocks are used to shift each
line of pixels into the horizontal output register of the CCD. The
AD9920A allows these outputs to be individually programmed
into various readout configurations by using a four-step process.
3. The readout for an entire field is constructed by dividing
the field into regions and then assigning a sequence to each
region. Each field can contain up to nine different regions
to accommodate the various steps of the readout, such as
high speed line shifts and unique vertical line transfers.
The total number of V-patterns, V-sequences, and fields is
programmable but limited by the number of registers.
4. The mode registers allow the different fields to be combined
in any order for various readout configurations.
Figure 41 shows an overview of how the vertical timing is
generated in four steps.
1. The individual pulse patterns for XV1 to XV24 are created
by using the vertical pattern group registers.
CREATE THE VERTICAL PATTERN GROUPS,
UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.
BUILD THE V-SEQUENCES BY ADDING START POLARITY,
1
2
LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,
GROUP A/B/C/D INFORMATION, AND HBLK/CLPOB PULSES.
XV1
XV2
XV1
XV2
XV3
XV3
VPAT0
V-SEQUENCE 0
(VPAT0, 1 REP)
XV23
XV24
XV23
XV24
XV1
XV2
XV1
XV2
XV3
V-SEQUENCE 1
(VPAT1, 2 REP)
XV3
VPAT1
XV23
XV24
XV23
XV24
XV1
XV2
XV3
V-SEQUENCE 2
(VPAT1, N REP)
XV23
XV24
USE THE MODE REGISTERS TO CONTROL WHICH FIELDS
ARE USED AND IN WHAT ORDER (MAXIMUM OF SEVEN
FIELDS CAN BE COMBINED IN ANY ORDER).
BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS
AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH
(MAXIMUM OF NINE REGIONS IN EACH FIELD).
4
3
FIELD1
FIELD2
FIELD4
FIELD1
FIELD3
FIELD1
FIELD3
FIELD5
REGION 0: USE V-SEQUENCE 2
REGION 1: USE V-SEQUENCE 0
REGION 2: USE V-SEQUENCE 3
REGION 3: USE V-SEQUENCE 0
FIELD2
FIELD4
REGION 4: USE V-SEQUENCE 2
FIELD2
FIELD3
Figure 41. Summary of Vertical Timing Generation
Rev. B | Page 32 of 112
AD9920A
The VSTART position is actually an offset value for each toggle
position. The actual pixel location for each toggle, measured
from the HD falling edge (Pixel 0), is equal to the VSTART
value plus the toggle position.
Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns
for each XV1 to XV24 output signal. Table 14 summarizes the
registers available for generating each V-pattern group. The first,
second, third, and fourth toggle positions (VTOG1, VTOG2,
VTOG3, and VTOG4) are the pixel locations within the line
where the pulse transitions. All toggle positions are 13-bit
values, allowing their placement anywhere in the first 8191
pixels of the line.
When the selected V-output is designated as a VSG pulse, either
the VTOG1/VTOG2 or VTOG3/VTOG4 pair is selected using
V-Sequence Address 0x03, VSGPATSEL. All four toggle positions
are not simultaneously available for VSG pulses.
All unused V-channels must have their toggle positions
programmed to either 0 or maximum value. This prevents
unpredictable behavior because the default values of the
V-pattern group registers are unknown.
More registers are included in the vertical sequence registers to
specify the output pulses. VPOL specifies the start polarity for
each signal; VSTART specifies the start position of the V-pattern
group within the line; VLEN designates the total length of the
V-pattern group, which determines the number of pixels between
each of the pattern repetitions when repetitions are used.
Table 14. Vertical Pattern Group Registers
Register
VTOG1
VTOG2
VTOG3
VTOG4
Length (Bits)
Description
13
13
13
13
First toggle position within the line for each XV1 to XV24 output, relative to VSTART value.
Second toggle position, relative to VSTART value.
Third toggle position, relative to VSTART value.
Fourth toggle position, relative to VSTART value.
START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS.
HD
4
XV1
XV2
1
1
2
3
2
3
XV24
1
2
3
PROGRAMMABLE SETTINGS:
1
START POLARITY (LOCATED IN V-SEQUENCE REGISTERS).
2
3
4
FIRST TOGGLE POSITION.
SECOND TOGGLE POSITION (THIRD AND FOURTH TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS).
TOTAL PATTERN LENGTH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGISTERS).
Figure 42. Vertical Pattern Group Programmability
Rev. B | Page 33 of 112
AD9920A
Generally, the same number of repetitions is programmed into
both registers. If a different number of repetitions is required on
odd and even lines, separate values can be used for each register
(see the Generating Line Alternation for V-Sequences and HBLK
section). The VSTARTA, VSTARTB, VSTARTC, and VSTARTD
registers specify where in the line the V-pattern group starts.
The VMASK_EVEN and VMASK_ODD registers are used in
conjunction with the FREEZE/RESUME registers to enable
optional masking of the V-outputs. One or more of the
VERTICAL SEQUENCES (VSEQ)
The vertical sequences are created by selecting one of the V-pattern
groups and adding repeats, start position, horizontal clamping, and
blanking information. The V-sequences are programmed using
the registers shown in Table 15. Figure 43 shows an example of
how these registers are used to generate the V-sequences.
The VPATSELA, VPATSELB, VPATSELC, and VPATSELD
registers select which V-pattern is used in a given V-sequence.
Having four groups available allows each vertical output to be
mapped to a different V-pattern. The user can add repetitions to
the selected V-pattern group for high speed line shifts or for line
binning by using the VREP registers for odd and even lines.
FREEZE1/RESUME1, FREEZE2/RESUME2, FREEZE3/
RESUME3, and FREEZE4/RESUME4 registers can be enabled.
The line length (in pixels) is programmable using the HDLEN
registers. Each V-sequence can have a different line length to
accommodate various image readout techniques. The maximum
number of pixels per line is 8192. The last line of the field is
programmed separately using the HDLASTLEN register, which
is located in the field register section (see Table 64).
1
HD
2
3
4
4
XV1 TO XV24
CLPOB
VREPA_3
V-PATTERN GROUP
VREPA_ 2
5
6
HBLK
PROGRAMMABLE SETTINGS FOR EACH VERTICAL SEQUENCE:
1
START POSITION IN THE LINE OF THE SELECTED V-PATTERN GROUP.
HD LINE LENGTH.
V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP.
NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED).
START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS.
MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL.
2
3
4
5
6
Figure 43. V-Sequence Programmability
Rev. B | Page 34 of 112
AD9920A
Table 15. Summary of V-Sequence Registers (see Table 11 and Table 12 for the CLPOB, PBLK, and HBLK Register Summary)
Length
(Bits)
Register
Description
HOLD
4
Use in conjunction with VMASK_EVEN and VMASK_ODD.
1 = Enable HOLD function instead of FREEZE/RESUME function.
CONCAT_GRP
VREP_MODE
4
Combines toggle positions of Group A, Group B, Group C, and Group D when enabled. Only Group A settings
for start, polarity, length, and repetition are used when this mode is selected.
0 = disable.
1 = enable the addition of all toggle positions from VPATSELA/B/C/D.
2 to 15 = test mode only; do not use.
2
Selects line alternation for V-output repetitions. Two separate controls: one for Group A and the other for
Group B, Group C, and Group D.
0 = disable alternation. Group A uses VREPA_1, Groups B/C/D use VREP_EVEN for all lines.
1 = two-line. Group A alternates VREPA_1 and VREPA_2. Groups B/C/D alternate VREP_EVEN and VREP_ODD.
2 = three-line. Group A alternates VREPA_1, VREPA_2, and VREPA_3. Groups B/C/D follow a VREP_EVEN,
VREP_ODD, VREP_ODD, VREP_EVEN, VREP_ODD, VREP_ODD pattern.
3 = four-line. Group A alternates VREPA_1, VREPA_2, VREPA_3, and VREPA_4. Groups B/C/D follow two-line
alternation.
LASTREPLEN_EN
4
Enable a separate pattern length to be used during the last repetition of the V-sequence. One bit for each
group (A, B, C, and D); Group A is the LSB. Set bit high to enable. Recommended value is enabled.
HDLENE
HDLENO
VPOL
14
14
24
24
HD line length for even lines in the V-sequence.
HD line length for odd lines in the V-sequence.
Group A start polarity bits for each XV1 to XV24 signal.
GROUPSEL_0
Assigns each XV1 to XV12 signal to Group A, Group B, Group C, or Group D. Two bits for each signal.
Bits[1:0] are for XV1.
Bits[3:2] are for XV2.
Bits[23:22] are for XV12.
0 = assign to Group A.
1 = assign to Group B.
2 = assign to Group C.
3 = assign to Group D.
GROUPSEL_1
24
Assigns each XV13 to XV24 signal to Group A, Group B, Group C, or Group D. Two bits for each signal.
Bits[1:0] are for XV13.
Bits[3:2] are for XV14.
Bits[23:22] are for XV24.
0 = assign to Group A.
1 = assign to Group B.
2 = assign to Group C.
3 = assign to Group D.
VPATSELA
VPATSELB
VPATSELC
VPATSELD
VSTARTA
VSTARTB
VSTARTC
VSTARTD
VLENA
5
Selected V-pattern for Group A.
5
Selected V-pattern for Group B.
5
Selected V-pattern for Group C.
5
Selected V-pattern for Group D.
13
13
13
13
13
13
13
13
13
13
13
13
Start position for the selected V-pattern Group A.
Start position for the selected V-pattern Group B.
Start position for the selected V-pattern Group C.
Start position for the selected V-pattern Group D.
Length of selected V-pattern Group A.
VLENB
Length of selected V-pattern Group B.
VLENC
Length of selected V-pattern Group C.
VLEND
Length of selected V-pattern Group D.
VREPA_1
VREPA_2
VREPA_3
VREPA_4
Number of repetitions for the V-pattern Group A for first lines (even).
Number of repetitions for the V-pattern Group A for second lines (odd).
Number of repetitions for the V-pattern Group A for third lines.
Number of repetitions for the V-pattern Group A for fourth lines.
Rev. B | Page 35 of 112
AD9920A
Length
(Bits)
Register
Description
VREPB_ODD
VREPC_ODD
VREPD_ODD
VREPB_EVEN
VREPC_EVEN
VREPD_EVEN
FREEZE1
13
13
13
13
13
13
13
Number of repetitions for the V-pattern Group B for odd lines.
Number of repetitions for the V-pattern Group C for odd lines.
Number of repetitions for the V-pattern Group D for odd lines.
Number of repetitions for the V-pattern Group B for even lines.
Number of repetitions for the V-pattern Group C for even lines.
Number of repetitions for the V-pattern Group D for even lines.
Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL0_EVEN, Bits[12:0] register when special VSEQALT_EN mode is enabled.
FREEZE2
13
13
13
13
13
13
13
13
13
13
13
Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL1_EVEN, Bits[12:0] register when special VSEQALT_EN mode is enabled.
FREEZE3
Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL0_ODD, Bits[12:0] register when special VSEQALT_EN mode is enabled.
FREEZE4
Pixel location where the V-outputs freeze or hold (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL1_ODD, Bits[12:0] register when special VSEQALT_EN mode is enabled.
RESUME1
Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL0_EVEN, Bits[17:13] register when special VSEQALT_EN mode is enabled.
RESUME2
Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL1_EVEN, Bits[17:13] register when special VSEQALT_EN mode is enabled.
RESUME3
Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL0_ODD, Bits[17:13] register when special VSEQALT_EN mode is enabled.
RESUME4
Pixel location where the V-outputs resume operation (see VMASK_EVEN and VMASK_ODD). Also used as
VALTSEL1_ODD, Bits[17:13] register when special VSEQALT_EN mode is enabled.
LASTREPLEN_A
LASTREPLEN_B
LASTREPLEN_C
LASTREPLEN_D
Separate length for last repetition of vertical pulses for Group A. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENA register.
Separate length for last repetition of vertical pulses for Group B. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENB register.
Separate length for last repetition of vertical pulses for Group C. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLENC register.
Separate length for last repetition of vertical pulses for Group D. Must be enabled using LASTREPLEN_EN.
Should be programmed to a value equal to the VLEND register.
VSEQALT_EN
1
Special V-sequence alternation mode is enabled when this register is programmed high.
VALTSEL0_EVEN
18
Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Group A, Group B,
Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi-
mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.)
VALTSEL1_EVEN
VALTSEL0_ODD
VALTSEL1_ODD
SPC_PAT_EN
18
18
18
3
Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Group A, Group B,
Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi-
mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.)
Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Group A, Group B,
Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi-
mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.)
Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Group A, Group B,
Group C, and Group D into unique merged patterns. Setting is used to specify one segment, with up to a maxi-
mum of 18 segments. (The FREEZE/RESUME registers function as VALTSEL when VSEQALT_EN is enabled.)
Enable special V-pattern to be inserted into one repetition of a VPATA series.
SPC_PAT_EN, Bit 0: set to 1 to enable VPATB to be used as special pattern insertion.
SPC_PAT_EN, Bit 1: set to 1 to enable VPATC to be used as special pattern insertion.
SPC_PAT_EN, Bit 2: set to 1 to enable VPATD to be used as special pattern insertion.
SEQ_ALT_INC
SEQ_ALT_RST
1
1
0 = normal operation.
1 = automatically increments the sequence number at the end of the line, unless a sequence change
position boundary is reached.
0 = normal operation.
1 = automatically resets the sequence number back to the sequence defined for that particular region in the
active field register.
Rev. B | Page 36 of 112
AD9920A
HD
XV1
XV8
XV1 TO XV8 USE
V-PATTERN GROUP A
XV9, XV10 USE
V-PATTERN GROUP B
XV9
XV10
Figure 44. Using Separate Group A and Group B Patterns
HD
V-PATTERN GROUP A
V-PATTERN GROUP B
V-PATTERN GROUP C
V-PATTERN GROUP D
XV1
XV24
Figure 45. Combining Multiple V-Patterns Using CONCAT_GRP = 1
HD
V-PATTERN GROUP A
V-PATTERN GROUP B
XV1
XV10
GROUP A REP 1
GROUP A REP 2
GROUP A REP 3
Figure 46. Combining Group A and Group B Patterns with Repetition
Group A/Group B/Group C/Group D Selection
If additional flexibility is needed, some outputs can be set to
Group B, Group C, or Group D in the GROUPSEL registers. In
this case, those selected outputs use the V-pattern group specified
by the VPATSELB, VPATSELC, or VPATSELD registers. Figure 44
shows an example where the V9 and V10 outputs use a separate
V-pattern Group B to perform special CCD timing.
The AD9920A has the flexibility to use four different V-pattern
groups in a vertical sequence. In general, the vertical outputs
use the same V-pattern group during a particular sequence. It
is possible to assign some of the outputs to a different V-pattern
group, which can be useful in certain CCD readout modes.
Another application of the Group A, Group B, Group C, and
Group D registers is to combine up to four different V-pattern
groups together for more complex patterns. This is accom-
plished by setting the CONCAT_GRP register (Address 0x00,
Bits[13:10]) equal to 0x01. This setting combines the toggle
positions from the V-pattern groups specified by registers
VPATSELA, VPATSELB, VPATSELC, and VPATSELD for a
maximum of up to 16 toggle positions. Example timing for the
CONCAT_GRP = 1 feature is shown in Figure 45.
The GROUPSEL registers are used to select the group (A, B, C,
or D) for each V-output. In general, only a single V-pattern
group is needed for the vertical outputs; therefore, Group A
should be selected for all outputs by default (GROUPSEL_0,
GROUPSEL_1 = 0x00). In this configuration, all outputs use
the V-pattern group specified by the VPATSELA register.
Rev. B | Page 37 of 112
AD9920A
If only two groups are needed (up to eight toggle positions) for
the specified timing, the VPATSELB, VPATSELC, and VPATSELD
registers can be programmed to the same value. If only three
groups are needed, VPATSELC and VPATSELD can be
programmed to the same value. Following this approach
conserves register memory if the four separate V-patterns are
not needed.
Table 16. VALTSEL Bit Settings for Even and Odd Lines
Parameter
VALTSEL Bit Settings
VALTSEL0_EVEN
VALTSEL1_EVEN
VALTSEL0_ODD
VALTSEL1_ODD
Resulting Pattern for Even Lines
Resulting Pattern for Odd Lines
0
0
0
0
A
A
0
1
0
1
B
B
1
0
1
0
C
C
1
1
1
1
D
D
Note that when CONCAT_GRP is enabled, the Group A
settings are used only for start position, polarity, length, and
repetitions. All toggle positions for Group A, Group B, Group C,
and Group D are combined together and applied using the
settings in the VSTARTA, VPOL, VLENA, and VREPA registers.
When the entire pattern is divided, program VALTSEL0 (even
and odd), Bits[17:0] and VALTSEL1 (even and odd), Bits[17:0]
so that the segments are concatenated in the desired order. If
separate odd and even lines are not required, set the odd and
even registers to the same value.
Special Vertical Sequence Alternation (SVSA) Mode
The AD9920A has additional flexibility for combining four
different V-pattern groups in a random sequence that can be
programmed for specific CCD requirements. This mode of
operation allows custom vertical sequences for CCDs that
require more complex vertical timing patterns. For example,
using the special vertical sequence alternation mode, it is
possible to support random pattern concatenation, with
additional support for odd/even line alternation.
Figure 49 illustrates the process of using six vertical pattern
segments that are concatenated into a small, merged pattern.
Program the register VREPA_1 to specify the number of segments
that are concatenated into each merged pattern. The maximum
number of segments that can be concatenated to create a merged
pattern is 18. Program VLENA, VLENB, VLENC, and VLEND
to be of equal length. Finally, program HBLK to generate the
proper H-clock timing using the procedure described in the
HBLK Mode 1 Operation section.
Figure 47 illustrates four common and repetitive vertical pattern
segments, A through D, that are derived from the complete
vertical pattern. Figure 48 illustrates how each group can be
concatenated together in an arbitrary order.
It is important to note that because the FREEZE/RESUME registers
are used to specify the VALTSEL registers, it is impossible to use
both the FREEZE/RESUME functions and the SVSA mode.
To enable the SVSA mode, write the VSEQALT_EN bit,
Address 0x00, Bit 6 in the V-sequence registers, equal to 0x01.
This enables the FREEZE/RESUME registers to function as
VALTSEL registers.
Table 17. VALTSEL Register Locations
Function of FREEZE/
RESUME Registers When
VSEQALT_EN = 1
Register Location
To create SVSA timing, divide the complete vertical timing
pattern into four common and repetitive segments. Identify the
related segments as VPATA, VPATB, VPATC, or VPATD. Up to
four toggle positions for each segment can be programmed using
the V-pattern registers.
VALTSEL0_EVEN, Bits[12:0]
VSEQ register FREEZE1, Bits[12:0]
VALTSEL0_EVEN, Bits[17:13] VSEQ register RESUME1, Bits[17:13]
VALTSEL1_EVEN, Bits[12:0] VSEQ register FREEZE2, Bits[12:0]
VALTSEL1_EVEN, Bits[17:13] VSEQ register RESUME2, Bits[17:13]
VALTSEL0_ODD, Bits[12:0] VSEQ register FREEZE3, Bits[12:0]
VALTSEL0_ODD, Bits[17:13] VSEQ register RESUME3, Bits[17:13]
VALTSEL1_ODD, Bits[12:0] VSEQ register FREEZE4, Bits[12:0]
VALTSEL1_ODD, Bits[17:13] VSEQ register RESUME4, Bits[17:13]
Table 16 shows how the segments are specified using a 2-bit
representation. Each bit from VALTSEL0 and VALTSEL1 is
combined to produce four values, corresponding to Pattern A,
Pattern B, Pattern C, and Pattern D.
Rev. B | Page 38 of 112
AD9920A
V-PATTERN A
V-PATTERN B
V-PATTERN C
V-PATTERN D
XV1
XV2
XV3
XV23
VLENA
NOTES
VLENB
VLENC
VLEND
1. EACH SEGMENT MUST BE THE SAME LENGTH.
VLENA = VLENB = VLENC = VLEND.
Figure 47. Vertical Timing Divided into Four Segments: VPATA, VPATB, VPATC, and VPATD
HD
COMBINED
V-PATTERN
B
C
B
D
A
B
A
A
A
B
B
D
A
C
C
A
NOTES
1. ABLE TO CONCATENATE PATTERNS TOGETHER ARBITRARILY.
2. EACH PATTERN CAN HAVE UP TO FOUR TOGGLES PROGRAMMED.
3. CAN CONCATENATE UP TO 18 PATTERNS INTO A MERGED PATTERN.
4. ODD AND EVEN LINES CAN HAVE A DIFFERENT PATTERN CONCATENATION
SPECIFIED BY VALTSEL EVEN AND ODD REGISTERS.
Figure 48. Concatenating Each VPAT Group in an Arbitrary Order
HD
A
C
B
D
D
A
XV1 TO XV23
SEGMENT 1
SEGMENT 2
SEGMENT 3
SEGMENT4
SEGMENT 5
SEGMENT 6
XV1
XV2
XV3
XV23
VPATA
VPATC
VPATB
VPATD
VPATD
VPATA
VALTSEL0_EVEN
VALTSEL1_EVEN
0
0
0
1
1
0
1
1
1
1
0
0
NOTES
1. SIX V-PATTERN SEGMENTS CONCATENATED INTO A MERGED PATTERN.
2. COMMON AND REPETITIVE VTP SEGMENTS DERIVED FROM THE COMPLETE VTP PATTERN.
3. VALTSEL REGISTERS SPECIFY SEGMENT ORDER TO CREATE THE CONCATENATED MERGED PATTERN.
Figure 49. Example of Special V-Sequence Alternation Mode Using VALTSEL Registers to Specify Segment Order
Rev. B | Page 39 of 112
AD9920A
Using the LASTREPLEN_EN Register
to be programmed on odd and even lines. Only the number of
repeats can be different in odd and even lines if the V-pattern
group remains the same. There are separate controls for the
assigned Group A, Group B, Group C, and Group D patterns.
All groups can support odd and even line alternation. Group A
uses the VREPA_1 and VREPA_2 registers; Group B, Group C,
and Group D use the corresponding VREPx_ODD and
VREPx_EVEN registers. Using the additional VREPA_3 and
VREPA_4 registers, Group A can also support three-line and
four-line alternation.
The LASTREPLEN_EN register (Address 0x00, Bits[19:16] in the
V-sequence registers) is used to enable a separate pattern length
to be used in the final repetition of several pulse repetitions. If a
different last length is not required, it is still recommended that
the LASTREPLEN_EN register bits be set high (enabled) and that
the LASTREPLEN_A, LASTREPLEN_B, LASTREPLEN_C, and
LASTREPLEN_D registers be set to a value equal to the VLENA,
VLENB, VLENC, and VLEND register values, respectively.
Generating Line Alternation for V-Sequences and HBLK
As described in the Generating HBLK Line Alternation section,
the HBLK signal can be alternated for odd and even lines. Figure 50
shows an example of V-pattern group repetition alternation and
HBLK Mode 0 alternation used together.
During low resolution readout, some CCDs require a different
number of vertical clocks on alternate lines. The AD9920A can
support this requirement by using the VREP registers. These
registers allow a different number of V-pattern group repetitions
HD
VREPA_1 = 2
VREPA_2 = 5
VREPA_1 = 2
(OR VREPB/C/D_EVEN = 2)
(OR VREPB/C/D_ODD = 5)
(OR VREPB/C/D_EVEN = 2)
XV1
XV2
XV24
TOGE1
TOGE2
TOGO1
TOGO2
TOGE1
TOGE2
HBLK
NOTES
1. THE NUMBER OF REPEATS FOR V-PATTERN GROUPS A/B/C/D CAN BE ALTERNATED ON ODD AND EVEN LINES.
2. GROUP A ALSO SUPPORTS 3- AND 4-LINE ALTERNATION USING THE ADDITIONAL VREPA_3 AND VREPA_4 REGISTERS.
3. THE HBLK TOGGLE POSITIONS CAN BE ALTERNATED BETWEEN ODD AND EVEN LINES TO GENERATE DIFFERENT HBLK PATTERNS.
Figure 50. Odd/Even Line Alternation of V-Pattern Group Repetitions and HBLK Toggle Positions
Rev. B | Page 40 of 112
AD9920A
Vertical Masking Using the FREEZE/RESUME Registers
Four sets of FREEZE/RESUME registers are provided, allowing
the vertical outputs to be interrupted up to four times in the
same line.
As shown in Figure 51 and Figure 52, the FREEZE/RESUME
registers are used to temporarily mask the V-outputs. The pixel
locations to begin the masking (FREEZE) and end the masking
(RESUME) create an area in which the vertical toggle positions
are ignored. At the pixel location specified in the FREEZE register,
the V-outputs are held static at their current dc state, high or low.
The V-outputs are held until the pixel location specified by the
RESUME register is reached, at which point the signals continue
with any remaining toggle positions, if any exist.
When masking is enabled, each group (Group A, Group B,
Group C, and Group D) uses the same FREEZE/RESUME
positions.
Note that the FREEZE/RESUME registers are also used as the
VALTSEL0 and VALTSEL1 registers during special vertical
alternation mode (see the Special Vertical Sequence Alternation
(SVSA) Mode section).
HD
XV1
NO MASKING AREA
XV24
Figure 51. No FREEZE/RESUME
V-MASKING AREA
HD
XV1
FREEZE
RESUME
XV24
NOTES
1. ALL TOGGLE POSITIONS WITHIN THE FREEZE/RESUME MASKING AREA ARE IGNORED. H-COUNTER CONTINUES TO COUNT DURING MASKING.
2. FOUR SEPARATE MASKING AREAS ARE AVAILABLE, USING FREEZE1/RESUME1, FREEZE2/RESUME2, FREEZE3/RESUME3, AND
FREEZE4/RESUME4 REGISTERS.
Figure 52. Using FREEZE/RESUME
Rev. B | Page 41 of 112
AD9920A
Hold Area Using the FREEZE/RESUME Registers
masking function in that the V-outputs continue from where
they stopped rather than continuing from where they would
have been. The hold area temporarily stops the pixel counter
for the V-outputs, whereas vertical masking allows the counter
to continue in the masking area.
The FREEZE/RESUME registers can also be used to create a
hold area in which the V-outputs are temporarily held and later
continued, starting at the point where they were held. As shown
in Figure 53, the hold area function is different from the vertical
HD
HOLD AREA
FOR GROUP A
FREEZE
RESUME
XV1
XV8
XV9
XV10
NOTES
1. WHEN HOLD = 1 FOR ANY V-SEQUENCE GROUP, THE FREEZE AND RESUME REGISTERS ARE USED TO SPECIFY THE HOLD AREA.
2. IN THIS EXAMPLE, XV1 TO XV10 ARE ASSIGNED TO GROUP A. HOLD BIT FOR GROUP A = 1.
3. H-COUNTER FOR GROUP A (XV1 TO XV10) STOPS DURING HOLD AREA.
Figure 53. Hold Area for Group A
Rev. B | Page 42 of 112
AD9920A
Special Pattern Insertion
has been added into the middle of the sequence. Figure 55
shows more detail on how to set the registers to achieve the
desired timing.
Additional flexibility is available using the SPC_PAT_EN
register bits, which allow a Group B, Group C, or Group D
pattern to be inserted into a series of Group A repetitions. This
feature is useful when a different pattern is needed at the start,
middle, or end of a sequence.
Note that VREPB is used to specify which repetition number
has the special pattern inserted instead of VPATA. VPATB
always has priority over VPATC or VPATD if more than one
SPC_PAT_EN bit is enabled (that is, SPC_PAT_EN, Bit 0 has
priority over SPC_PAT_EN, Bit 1 and Bit 2).
Figure 54 shows an example of a sweep region using VPATA
with multiple repetitions where a single repetition of VPATB
VD
SCP1
SCP2
HD
LINE 0
LINE 1
LINE
2
LINE 24
LINE 25
XV1 TO XVx
REGION 0
REGION 1: SWEEP REGION
REGION 2
PATTERN B INSERTED DURING PATTERN A REPETITIONS
Figure 54. Special Pattern Insertion Example
HD
REP N
REP 1
REP 2
REP 3
REP 4
REP 5
XV1
V-PATTERN A
REGISTER SETTINGS: DESCRIPTION:
V-PATTERN B
V-PATTERN A
SPC_PAT_EN[0] = 1
VREPA = N
VREPB = 4
V-PATTERN B IS USED AS SPECIAL PATTERN
TOTAL NUMBER OF REPS USED FOR SEQUENCE (N REPS)
REP 4 USES V-PATTERN B INSTEAD OF V-PATTERN A
NOTES
1. VSTARTB MUST BE SET EQUAL TO VSTARTA.
Figure 55. Special Pattern Insertion Registers
Rev. B | Page 43 of 112
AD9920A
that line the sequence number automatically increments to
Sequence 3. In the same way, at the end of that line, the
sequence number automatically increments to Sequence 4.
Sequence Line Alternation
To support the timing requirements of some advanced CCDs
in a memory-efficient manner, the AD9920A can automatically
increment the sequence number at the end of a given line through
the use of the SEQ_ALT_INC register (V-Sequence Register 0x09,
Bit 20). It can also reset the sequence number to the sequence
defined in the field register through the SEQ_ALT_RST register
(V-Sequence Register 0x09, Bit 21). Combining these two registers
allows the user to create a loop of sequences for a given region.
See Figure 56 for an example of how to use these two functions
together. The example in Figure 56 uses the register settings
listed in Table 18.
Because SEQ_ALT_INC = 0 and SEQ_ALT_RST = 1 for
Sequence 4, the AD9920A automatically resets the sequence
number to the sequence defined for that region in the field register,
which in this case is Sequence 2. The AD9920A continues to loop
in this fashion between Sequence 2, Sequence 3, and Sequence 4
until it reaches the next sequence change position.
It is important to note that the sequence number can increment
only at the end of a line and cannot be used to create more complex
patterns within one line. This is distinctly different from the special
vertical sequence alternation mode, which allows the user to
concatenate multiple sequences within one line (see the Special
Vertical Sequence Alternation (SVSA) Mode section).
With these settings, at Sequence Change Position 0 (SCP0),
the AD9920A steps into Sequence 2. Because the Sequence 2
SEQ_ALT_INC = 1 and the SEQ_ALT_RST = 0, at the end of
Table 18. Register Settings for the Example in Figure 56
Field Registers
Sequence 2 Registers
Sequence 3 Registers
Sequence 4 Registers
SEQ_ALT_INC = 0
SEQ_ALT_RST = 1
Sequence 6 Registers
SEQ_ALT_INC = 0
SEQ_ALT_RST = 0
SCP0 = 0, SEQ0 = 2
SCP1 = 6, SEQ1 = 6
SEQ_ALT_INC = 1
SEQ_ALT_RST = 0
SEQ_ALT_INC = 1
SEQ_ALT_RST = 0
VD
HD
ACTIVE
SEQUENCE #
2
3
4
2
3
4
6
6
SCP0
SCP1
Figure 56. Example Output Using SEQ_ALT_INC and SEQ_ALT_RST Functions
Rev. B | Page 44 of 112
AD9920A
Complete Field: Combining V-Sequences
The HDLASTLEN register specifies the number of pixels in the
last line of the field.
After the V-sequences are created, they are combined to create
different readout fields. A field consists of up to nine regions;
within each region, a different V-sequence can be selected.
Figure 57 shows how the sequence change positions (SCPs)
designate the line boundary for each region and how the SEQ
registers then select which V-sequence is used in each region.
Registers to control the VSG outputs are also included in the
field registers. Table 19 summarizes the registers used to create
the various fields.
The SGMASK register is used to enable or disable each individual
VSG output. There are two bits for each VSG output to enable
separate masking in SGACTLINE1 and SGACTLINE2.
Setting a masking bit high masks the output; setting it low
enables the output. The VSGPATSEL register assigns one of
the eight SG patterns to each VSG output. The individual SG
patterns are created separately using the SG pattern registers.
The SGACTLINE1 register specifies which line in the field
contains the VSG outputs. The optional SGACTLINE2 register
allows VSG pulses to be output on a different line. Separate
masking is not available for SGACTLINE1 and SGACTLINE2,
unless separate sequences are assigned to SGACTLINE1 and
SGACTLINE2. Note that to ensure proper SUBCK operation
when using both SGACTLINE1 and SGACTLINE2, SGACTLINE2
must be programmed to occur before SGACTLINE1.
The SEQ registers, one for each region, select which of the
V-sequences are active in each region. The MULT_SWEEP
registers, one for each region, are used to enable sweep mode
and/or multiplier mode in any region. The SCP registers create
the line boundaries for each region. The VDLEN register specifies
the total number of lines in the field. The HDLEN registers specify
the total number of pixels per line.
Table 19. Field Registers (CLPOB, PBLK Masking Shown in Table 11)
Register
Length (Bits)
Range
Description
SEQ
MULT_SWEEP
5
2
0 to 31 V-sequence number Selected V-sequence for each region in the field.
0 to 3
Enable multiplier mode and/or sweep mode for each region.
0 = multiplier off, sweep off.
1 = multiplier off, sweep on.
2 = multiplier on, sweep off.
3 = multiplier on, sweep on.
SCP
VDLEN
HDLASTLEN
VSGPATSEL
13
13
13
24
0 to 8191 line number
0 to 8191 lines
0 to 8191 pixels
High/low
Sequence change position for each region.
Total number of lines in each field.
Length in pixels of the last HD line in each field.
VSGPATSEL selects which two V-pattern toggle positions are used by each
V-output. Each bit represents one V-output: Bit 0 = XV1 output, Bit 23 =
XV24 output.
0 = use TOG1 and TOG2.
1 = use TOG3 and TOG4.
SGMASK
24
High/low, each VSG
Set high to mask each individual VSG output.
Bit 0: XV1 mask.
Bit 23: XV24 mask.
SGACTLINE1
SGACTLINE2
13
13
0 to 8191 line number
0 to 8191 line number
Selects the line in the field where the VSG signals are active.
Selects a second line in the field to repeat the VSG signals. If this register is
not used, set it equal to SGACTLINE1 or to the maximum value.
Rev. B | Page 45 of 112
AD9920A
SCP0
SCP1
SCP2
SCP3
SCP4
SCP5
SCP8
VD
REGION 0
REGION 1
REGION 2
REGION 3
REGION 4
REGION 8
HD
XV1 TO XVx
SEQ0
SEQ1
SEQ8
SEQ2
SEQ3
SEQ4
SGACTLINE1
VSG
FIELD SETTINGS:
1. SEQUENCE CHANGE POSITIONS (SCP0 TO SCP8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD.
2. SEQ0 TO SEQ8 SELECT THE DESIRED V-SEQUENCE FOR EACH REGION.
3. SGACTLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD CONTAINS THE SENSOR GATE PULSE(S).
Figure 57. Complete Field Divided into Regions
VD
HD
SCP1
SCP2
LINE 0
LINE 1
LINE
2
LINE 24
LINE 25
XV1 TO XVx
REGION 0
REGION 1: SWEEP REGION
REGION 2
Figure 58. Example of Sweep Region for High Speed Vertical Shift
Figure 58 shows an example of the sweep mode operation. The
number of vertical pulses needed depends on the vertical reso-
lution of the CCD. The toggle positions for the XV1 to XV24
signals are generated using the V-pattern registers (see Table 14).
A single pulse is created using the polarity and toggle position
registers. The number of repetitions is then programmed to match
the number of vertical shifts required by the CCD. Repetitions
are programmed into the V-sequence registers using the VREP
registers (see Table 15). This produces a pulse train of the appro-
priate length. Normally, the pulse train is truncated at the end
of the HD line length, but when sweep mode is enabled for this
region, the HD boundaries are ignored.
Sweep Mode Operation
The AD9920A contains an additional mode of vertical timing
operation called sweep mode. This mode is used to generate a
large number of repetitive pulses that span across multiple HD
lines. An example of where this mode is needed is at the start of
the CCD readout operation. At the end of the image exposure
before the image is transferred by the sensor gate pulses, the
vertical interline CCD registers should be free of all charge. This
can be accomplished by quickly shifting out any charge using a
long series of pulses from the vertical outputs. Depending on
the vertical resolution of the CCD, up to 3000 clock cycles
might be needed to shift the charge out of each vertical CCD
line. This operation spans across multiple HD line lengths.
Normally, the AD9920A vertical timing must be contained
within one HD line length, but when sweep mode is enabled,
the HD boundaries are ignored until the region is finished. To
enable sweep mode within any region, program the appropriate
SWEEP register to high.
In Figure 58, the sweep region occupies 23 HD lines. After the
sweep mode region is complete, normal sequence operation
resumes in the next region. When using sweep mode, be sure to
set the region boundaries (using the sequence change positions)
to the appropriate lines to prevent the sweep operation from
overlapping with the next V-sequence.
Rev. B | Page 46 of 112
AD9920A
Multiplier Mode
To calculate the exact toggle position, which is counted in pixels
after the start position, use the following equation:
To generate very wide vertical timing pulses, a vertical region
can be configured into a multiplier region. This mode uses the
V-pattern registers in a slightly different manner. Multiplier
mode can be used to support unusual CCD timing requirements,
such as vertical pulses that are wider than the 13-bit V-pattern
toggle position counter. In general, the 13-bit toggle position
counter can be used with the sweep mode feature to support
very wide pulses; however, multiplier mode can be used to
generate even wider pulses.
Multiplier Mode Toggle Position = VTOG × VLEN
Because the VTOG register is multiplied by VLEN, the resolu-
tion of the toggle position placement is reduced. If VLEN = 4,
the toggle position precision is reduced to four-pixel increments
instead of to single-pixel increments. Table 20 summarizes how
the V-pattern group registers are used in multiplier mode opera-
tion. In multiplier mode, the VREP registers must always be
programmed to the same value as the highest toggle position.
The start polarity and toggle positions are still used in the same
manner as in the standard V-pattern group programming, but
VLEN is used differently. Instead of using the pixel counter
(HD counter) to specify the toggle position locations (VTOG1,
VTOG2, VTOG3, and VTOG4) of the V-pattern group, the
VLEN is multiplied by the VTOG position to allow very long
pulses to be generated.
Figure 59 illustrates this operation. The first toggle position is 2,
and the second toggle position is 9. In nonmultiplier mode, this
causes the V-sequence to toggle at Pixel 2 and then at Pixel 9
within a single HD line. However, in multiplier mode, toggle
positions are multiplied by the value of VLEN (in this case, 4);
therefore, the first toggle occurs at Pixel 8, and the second toggle
occurs at Pixel 36. Sweep mode is also enabled to allow the
toggle positions to cross the HD line boundaries.
Table 20. Multiplier Mode Register Parameters
Register
MULT_SWEEPx
VPOL
Length (Bits) Range
Description
1
High/low
High enables multiplier mode.
Starting polarity of XV1 to XV24 signals in each V-pattern group.
Toggle positions for XV1 to XV24 signals in each V-pattern group.
1
High/low
VTOG
13
0 to 8191 pixel
location
VLEN
VREP
13
13
0 to 8191 pixels Used as multiplier factor for toggle position counter.
0 to 8191 pixel
location
With VREP_MODE = 0, VREP_EVEN must be set to the same value as the highest VTOG
value. VREP_ODD and VREPA can be set to 0.
START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE V-SEQUENCE REGISTERS
HD
5
5
3
VLEN
1
1
2
2
3
3
4
4
1
5
2
6
3
7
4
8
1
9
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
PIXEL
NUMBER
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
4
4
XV1 TO XV24
1
2
2
MULTIPLIER MODE V-PATTERN GROUP PROPERTIES:
1
START POLARITY (STARTPOL = 0).
2
FIRST, SECOND, AND THIRD TOGGLE POSITIONS (VTOG1 = 2, VTOG2 = 9).
3
LENGTH OF VPAT COUNTER (VLEN = 4); THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES.
4
TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VTOG × VLEN).
5
IF SWEEP REGION IS ENABLED, THE V-PULSES MAY ALSO CROSS THE HD BOUNDARIES, AS SHOWN ABOVE.
Figure 59. Example of Multiplier Region for Wide Vertical Pulse Timing
Rev. B | Page 47 of 112
AD9920A
Note that only two of the four V-pattern toggle positions are
available when a vertical signal is selected to be a VSG pulse.
Vertical Sensor Gate (Shift Gate) Patterns
In an interline CCD, the vertical sensor gate (VSG) pulses are
used to transfer the pixel charges from the light-sensitive image
area into light-shielded vertical registers. From the light-shielded
vertical registers, the image is clocked out line-by-line using the
vertical transfer pulses (XV signals) in conjunction with the high
speed horizontal clocks. The AD9920A has 24 vertical signals,
and each signal can be assigned as a VSG pulse instead of as an
XV pulse.
The SGACTLINE1 and SGACTLINE2 registers are used to
select which line in the field is the VSG line. The VSG active
line location is used to reference when the substrate clocking
(SUBCK) signal begins to operate in each field. For more infor-
mation, see the Substrate Clock Operation (SUBCK) section.
Also located in the field registers, the SGMASK register selects
which individual VSG pulses are active in a given field. Therefore,
all SG patterns to be preprogrammed into the V-pattern registers
and the appropriate pulses for the different fields can be enabled
separately.
Table 21 summarizes the VSG control registers, which are
mainly located in the field register space (see Table 19). The
VSGSELECT register (Address 0x1C in the fixed address space)
determines which vertical outputs are assigned as VSG pulses.
When a signal is selected to be a VSG pulse, only the starting
polarity and two of the V-pattern toggle positions are used. The
VSGPATSEL register in the V-sequence registers is used to assign
either TOG1 and TOG2 or TOG3 and TOG4 to the VSG signal.
The AD9920A is an integrated AFETG and V-driver, so the
connections between the AFETG and V-driver are fixed, as
shown in Figure 65 and Figure 66. The VSGSELECT register
must be programmed to 0xFF8000.
Table 21. VSG Control Registers (also see Field Registers in Table 19)
Register
Length (Bits) Range
Description
VSGSELECT
(Located in Fixed
Address Space, 0x1C)
24
High/low
Selection of VSG signals from XV signals. Set to 1 to make signal a VSG.
The recommended setting for this register is 0xFF8000.
Bit 0: XV1 selection (0 = XV pulse; 1 = VSG pulse).
Bit 1: XV2 selection.
Bit 23: XV24 selection.
VSGPATSEL
24
High/low
When VSG signal is selected using the VSGSELECT register, VSGPATSEL
selects which V-pattern toggle positions are used. When this register is
set to 0, Toggle 1 and Toggle 2 are used. When this register is set to 1,
Toggle 3 and Toggle 4 are used.
Bit 0: XV1 selection (0 = use TOG1, TOG2; 1 = use TOG3, TOG4).
Bit 1: XV2 selection.
Bit 23: XV24 selection.
SGMASK
24
High/low, each VSG
Set high to mask each individual VSG output.
Bit 0: XV1 mask.
Bit 23: XV24 mask.
SGACTLINE1
SGACTLINE2
13
13
0 to 8191 line number
0 to 8191 line number
Selects the line in the field where the VSG signals are active.
Selects a second line in the field to repeat the VSG signals. If this register
is not used, set it equal in value to SGACTLINE1 or to the maximum value.
VD
4
HD
1
2
VSG PATTERN
3
PROGRAMMABLE SETTINGS FOR EACH PATTERN:
1
START POLARITY OF PULSE (FROM VPOL IN SEQUENCE REGISTERS).
FIRST TOGGLE POSITION (FROM V-PATTERN REGISTERS).
SECOND TOGGLE POSITION (FROM V-PATTERN REGISTERS).
2
3
4
ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (FROM FIELD REGISTERS).
Figure 60. Vertical Sensor Gate Pulse Placement
Rev. B | Page 48 of 112
AD9920A
The other two registers (Address 0x2B and Address 0x2C) are
used to select which of the programmed fields are used and in
which order. Up to seven fields can be used in a single write to
the mode register. The AD9920A starts with the field timing
specified by FIELD1, and on the next VD switches to the timing
specified by FIELD2, and so on. After completing the total
number of fields specified by the mode register, the AD9920A
repeats by starting at the first field. This continues until a new
write to the mode register occurs. Figure 61 shows example
mode register settings for different field configurations.
Mode Registers
The mode registers are used to select the field timing of the
AD9920A. Typically, all of the field, V-sequence, and V-pattern
information is programmed into the AD9920A at startup. During
operation, the mode registers allow the user to select any combi-
nation of field timing to meet the requirements of the system.
The advantage of using the mode registers in conjunction with
preprogrammed timing is that it greatly reduces the system pro-
gramming requirements during camera operation. Only a few
register writes are required when the camera operating mode is
changed; the vertical timing information does not need to be
changed with each camera mode change.
Note that only a write to Address 0x2C properly resets the field
counter. Therefore, when changing the values in any of the mode
registers, it is recommended that all three registers be updated
together in the same field (VD period).
A basic still camera application can require six fields of vertical
timing—one for draft mode operation, one for autofocusing,
and four for still image readout. All of the register timing informa-
tion for the six fields is loaded at startup. Then, during camera
operation, the mode registers select which field timing is active,
depending on how the camera is being used.
Caution
The mode registers are SCK updated by default. If they are
configured as VD-updated registers by writing Address 0xB4 =
0x03FF and Address 0xB5 = 0xFC00, the new mode informa-
tion is updated on the second VD falling edge after the write
occurs, rather than on the first VD falling edge. See Figure 63
for an example.
Table 22 shows how the mode registers are used. The mode
register (Address 0x2A) specifies how many total fields are used.
Any value from 1 to 7 can be selected using these three bits.
Table 22. Mode Registers
Address Name
Length (Bits) Description
0x2A
0x2B
MODE
FIELD1
FIELD2
FIELD3
FIELD4
FIELD5
FIELD6
FIELD7
3
5
5
5
5
5
5
5
Total number of fields to cycle through. Set from 1 to 7.
Selected field (from FIELD registers in configurable memory) for the first field to cycle through.
Selected field (from FIELD registers in configurable memory) for the second field to cycle through.
Selected field (from FIELD registers in configurable memory) for the third field to cycle through.
Selected field (from FIELD registers in configurable memory) for the fourth field to cycle through.
Selected field (from FIELD registers in configurable memory) for the fifth field to cycle through.
Selected field (from FIELD registers in configurable memory) for the sixth field to cycle through.
Selected field (from FIELD registers in configurable memory) for the seventh field to cycle through.
0x2C
Rev. B | Page 49 of 112
AD9920A
EXAMPLE 1:
TOTAL FIELDS = 3, FIRST FIELD = FIELD1, SECOND FIELD = FIELD2, THIRD FIELD = FIELD3
MODE SETTINGS:
0x2A = 0x03
0x2B = 0x820
0x2C = 0x00
FIELD2
FIELD3
FIELD1
EXAMPLE 2:
TOTAL FIELDS = 1, FIRST FIELD = FIELD3
MODE SETTINGS:
0x2A = 0x01
0x2B = 0x03
0x2C = 0x00
FIELD3
EXAMPLE 3:
TOTAL FIELDS = 4, FIRST FIELD = FIELD5, SECOND FIELD = FIELD1, THIRD FIELD = FIELD4, FOURTH FIELD = FIELD2
MODE SETTINGS:
0x2A = 0x04
0x2B = 0x11025
0x2C = 0x00
FIELD2
FIELD1
FIELD4
FIELD5
Figure 61. Using the Mode Registers to Select Field Timing
VD
MODE WRITE MODE UPDATE
A
REGISTER WRITE
2
MODE FIELD NUMBER
4 (DRAFT)
4 (DRAFT)
0
(STILL FIRST FIELD)
1 (STILL SECOND FIELD)
EXAMPLE MODE REGISTER CHANGE:
REGISTER WRITE A––WRITE TO MODE REGISTERS 0x2A, 0x2B, 0x2C TO SPECIFY
CHANGE FROM DRAFT MODE (FIELD4) TO STILL MODE (FIELD1/2/3).
ALSO WRITE TO VGA GAIN OR ANY NEW REGISTER VALUES NEEDED
FOR STILL FRAME OPERATION, SUCH AS NEW FIELD INFORMATION.
Figure 62. Update of Mode Register, SCK Updated (Default Setting)
VD
MODE WRITE
A
MODE UPDATE
B
REGISTER WRITE
2
MODE FIELD NUMBER
4 (DRAFT)
4 (DRAFT)
0
(STILL FIRST FIELD)
1 (STILL SECOND FIELD)
EXAMPLE MODE REGISTER CHANGE:
REGISTER WRITE A––WRITE TO MODE REGISTERS 0x2A, 0x2B, 0x2C TO SPECIFY
CHANGE FROM DRAFT MODE (FIELD4) TO STILL MODE (FIELD1/2/3).
REGISTER WRITE B––WRITE TO VGA GAIN OR ANY NEW REGISTER VALUES NEEDED
FOR STILL FRAME OPERATION, SUCH AS NEW FIELD INFORMATION.
NOTES
1. NEW MODE INFORMATION IS UPDATED AT SECOND VD FALLING EDGE AFTER
SERIAL WRITE A.
Figure 63. Update of Mode Register, VD Updated
Rev. B | Page 50 of 112
AD9920A
Region 1 consists of only two lines and uses standard single-line
vertical shift timing. The timing of this region area is the same
as the timing in Region 3.
VERTICAL TIMING EXAMPLE
To better understand how the AD9920A vertical timing genera-
tion is used, consider the example CCD timing chart in Figure 64.
This example illustrates a CCD using a general three-field read-
out technique. As shown in Figure 64, each readout field must be
divided into separate regions to perform each step of the readout.
The sequence change positions (SCPs) determine the line bound-
aries for each region, and the SEQ registers assign a particular
V-sequence to each region. The V-sequences contain the specific
timing information required in each region: V1 to V6 pulses
(using V-pattern groups), HBLK/CLPOB timing, and VSG
patterns for the SG active lines.
Region 2 is the sensor gate line in which the VSG pulses transfer
the image into the vertical CCD registers. This region may require
the use of the second V-pattern group for the SG active line.
Region 3 also uses the standard single-line vertical shift timing,
the same timing as Region 1. Four regions are required in each
of the three fields.
The timing for Region 1 and Region 3 is essentially the same,
reducing the complexity of the register programming. Other
registers must be used during the actual readout operation.
These include the mode registers, shutter control registers
(PRIMARY_ACTION, SUBCK, and GPO for MSHUT and
VSUB control), and AFE gain registers.
This timing example requires four regions for each of the three
fields, labeled Region 0, Region 1, Region 2, and Region 3. Because
the AD9920A allows many individual fields to be programmed,
FIELD1, FIELD2, and FIELD3 can be used to meet the require-
ments of this timing example. The four regions for each field are
very similar in this example, but the individual registers for each
field allow flexibility to accommodate other timing charts.
Important Note Regarding Signal Polarities
When programming the AD9920A to generate the V1 to V24
and SUBCK signals, the external V-driver circuit usually inverts
these signals. Carefully check the timing signals that are required
at the input and output of the V-driver circuit being used, and
adjust the polarities of the AD9920A outputs accordingly.
Region 0 is a high speed, vertical shift region. Sweep mode can be
used to generate this timing operation with the desired number
of high speed vertical pulses needed to clear any charge from
the CCD vertical registers.
Rev. B | Page 51 of 112
AD9920A
N
3
N –
2 1
1 8
1 5
1 2
9
6
3
1
4
N –
N –
2 0
1 7
1 4
1 1
8
5
2
2
5
N –
N –
1 6
1 3
1 0
7
4
1
Figure 64. CCD Timing Example—Dividing Each Field into Regions
Rev. B | Page 52 of 112
AD9920A
INTERNAL VERTICAL DRIVER CONNECTIONS (18-CHANNEL MODE)
AD9920A
V-DRIVER
+3V
VH,VL
XV16 (XSG1)
XV1
G9
G6
G5
V1A
V1B
XV17 (XSG2)
XV18 (XSG3)
V2A
V2B
XV2
E9
J9
XV19 (XSG4)
XV20 (XSG5)
XV3
V3A
V3B
V4
3-LEVEL OUTPUTS
F6
F5
XV21 (XSG6)
XV4
XV22 (XSG7)
XV5
E5
V5
V6
XV23 (XSG8)
XV6
D10
INTERNAL
TIMING
GENERATOR
XV24 (XSG9)
F9
F7
XV7
XV8
XV9
V7
V8
D9
V9
C4
C5
B5
XV10
XV11
V10
V11
V12
2-LEVEL OUTPUTS
XV12
XV13
E6
E7
V13
V14
XV14
XV15
C8
J8
2-LEVEL OUTPUT,
REDUCED DRIVE
V15
V16
XSUBCK
G7
SUBCK
K11
XSUBCNT (LOGIC INPUT)
J6
LEGEN
Figure 65. Internal AFETG to V-Driver Connections, Legacy Mode (18-Channel Mode)
Rev. B | Page 53 of 112
AD9920A
INTERNAL VERTICAL DRIVER CONNECTIONS (19-CHANNEL MODE)
AD9920A
V-DRIVER
+3V
VH,VL
XV16 (XSG1)
G9
G6
G5
V1A
V1B
V2A
V2B
V3A
XV1
XV17 (XSG2)
XV18 (XSG3)
XV2
XV19 (XSG4)
XV3
E9
J9
XV20 (XSG5)
3-LEVEL OUTPUTS
XV23
F6
F5
XV21 (XSG6)
V3B
V4
XV4
XV22 (XSG7)
XV5
E5
V5
V6
GPO5 (XSG8)
XV6
D10
INTERNAL
TIMING
GENERATOR
GPO6 (XSG9)
F9
F7
XV7
XV8
XV9
V7
V8
D9
V9
2-LEVEL OUTPUTS
C4
C5
B5
XV10
XV11
V10
V11
V12
XV12
XV13
E6
E7
V13
V14
XV14
2-LEVEL OUTPUT,
REDUCED DRIVE
C8
J8
XV15
XV24
V15
V16
XSUBCK
G7
SUBCK
K11
XSUBCNT (LOGIC INPUT)
J6
LEGEN
+3V
Figure 66. Internal AFETG to V-Driver Connections (19-Channel Mode)
Rev. B | Page 54 of 112
AD9920A
OUTPUT POLARITY OF VERTICAL TRANSFER CLOCKS AND SUBSTRATE CLOCK
Table 23. V1A Output Polarity
Vertical Driver Input
Table 29. V4 Output Polarity
Vertical Driver Input
LEGEN
LEGEN
XV1
L
L
H
H
XV16 (XSG1)
V1A Output
XV4
L
L
H
H
XV22 (XSG7)
V4 Output
X
X
X
X
L
H
L
VH
VM
VL
X
X
X
X
L
H
L
VH
VM
VL
H
VL
H
VL
Table 24. V1B Output Polarity
Vertical Driver Input
Table 30. V5 Output Polarity
Vertical Driver Input
LEGEN
XV23
(XSG8)
GPO5
(XSG8)
XV1
L
L
H
H
XV17 (XSG2)
V1B Output
LEGEN
XV5
L
L
H
H
L
L
H
H
V5 Output
X
X
X
X
L
H
L
VH
VM
VL
L
L
L
L
H
H
H
H
L
H
L
H
X
X
X
X
X
X
X
X
L
H
L
H
VH
VM
VL
H
VL
VL
Table 25. V2A Output Polarity
Vertical Driver Input
VH
VM
VL
LEGEN
XV2
L
L
H
H
XV18 (XSG3)
V2A Output
VL
X
X
X
X
L
H
L
VH
VM
VL
Table 31. V6 Output Polarity
Vertical Driver Input
H
VL
XV24
(XSG9)
GPO6
(XSG9)
LEGEN
XV6
L
L
H
H
L
L
H
H
V6 Output
Table 26. V2B Output Polarity
Vertical Driver Input
L
L
L
L
H
H
H
H
L
H
L
H
X
X
X
X
X
X
X
X
L
H
L
H
VH
VM
VL
LEGEN
XV2
L
L
H
H
XV19 (XSG4)
V2B Output
X
X
X
X
L
H
L
VH
VM
VL
VL
VH
VM
VL
H
VL
VL
Table 27. V3A Output Polarity
Vertical Driver Input
Table 32. V7 Output Polarity
Vertical Driver Input
LEGEN
XV3
L
L
H
H
XV20 (XSG5)
V3A Output
X
X
X
X
L
H
L
VH
VM
VL
LEGEN
XV7
L
H
V7 Output
X
X
VM
VL
H
VL
Table 33. V8 Output Polarity
Vertical Driver Input
Table 28. V3B Output Polarity
Vertical Driver Input
LEGEN
XV8
L
H
V8 Output
XV21
(XSG6)
X
X
VM
VL
LEGEN
XV3
L
L
H
H
X
XV23
V3B Output
L
L
L
L
H
H
H
H
X
X
X
X
L
L
H
L
H
L
VH
VM
VL
Table 34. V9 Output Polarity
Vertical Driver Input
VL
LEGEN
XV9
L
H
V9 Output
VH
VM
VL
X
X
VM
VL
X
X
X
L
H
H
H
L
H
VL
Rev. B | Page 55 of 112
AD9920A
Table 35. V10 Output Polarity
Table 40. V15 Output Polarity
Vertical Driver Input
Vertical Driver Input
LEGEN
LEGEN
XV10
V10 Output
XV15
V15 Output
X
X
L
H
VM
VL
X
X
L
H
VM
VL
Table 36. V11 Output Polarity
Vertical Driver Input
Table 41. V16 Output Polarity
Vertical Driver Input
LEGEN
LEGEN
XV11
V11 Output
XV24
V16 Output
X
X
L
H
VM
VL
L
H
H
X
L
H
VL
VM
VL
Table 37. V12 Output Polarity
Vertical Driver Input
Table 42. SUBCK Output Polarity
Vertical Driver Input
LEGEN
XV12
V12 Output
LEGEN
XSUBCK
XSUBCNT
SUBCK Output
X
X
L
H
VM
VL
X
X
X
X
L
L
H
H
L
H
L
VH
VH
VMM
VLL
Table 38. V13 Output Polarity
Vertical Driver Input
H
LEGEN
XV13
V13 Output
X
X
L
H
VM
VL
Table 39. V14 Output Polarity
Vertical Driver Input
LEGEN
XV14
V14 Output
X
X
L
H
VM
VL
Rev. B | Page 56 of 112
AD9920A
XV1
XV16 (XSG1)
VH
V1A
VM
VL
Figure 67. XV1, XV16, and V1A Output Polarities
Figure 68. XV1, XV17, and V1B Output Polarities
Figure 69. XV2, XV18, and V2A Output Polarities
XV1
XV17 (XSG2)
VH
V1B
VM
VL
XV2
XV18 (XSG3)
VH
V2A
VM
VL
XV2
XV19 (XSG4)
VH
V2B
VM
VL
Figure 70. XV2, XV19, and V2B Output Polarities
Rev. B | Page 57 of 112
AD9920A
XV3
XV20 (XSG5)
VH
V3A
VM
VL
Figure 71. XV3, XV20, and V3A Output Polarities
XV3
XV21 (XSG6)
VH
V3B
VM
VL
LEGEN
Figure 72. XV3, XV21, and V3B Output Polarities (
= Low)
XV23
XV21 (XSG6)
VH
V3B
VM
VL
LEGEN
Figure 73. XV23, XV21, and V3B Output Polarities (
= High)
XV4
XV22 (XSG7)
VH
V4
VM
VL
Figure 74. XV4, XV22, and V4 Output Polarities
Rev. B | Page 58 of 112
AD9920A
XV5
XV23 (XSG8)
VH
V5
VM
VL
LEGEN
LEGEN
LEGEN
Figure 75. XV5, XV23, and V5 Output Polarities (
Figure 76. XV5, GPO5, and V5 Output Polarities (
Figure 77. XV6, GPO6, and V6 Output Polarities (
= Low)
= High)
= High)
XV5
GPO5 (XSG8)
VH
V5
VM
VL
XV6
GPO6 (XSG9)
VH
V6
VM
VL
XV7, XV8, XV9, XV10,
XV11, XV12, XV13,
XV14, XV15
VM
V7, V8, V9, V10, V11,
V12, V13, V14, V15
VL
Figure 78. Two-Level V-Driver Output Polarities
LEGEN
XV24
VM
V16
VL
Figure 79. XV24 and V16 Output Polarities
Rev. B | Page 59 of 112
AD9920A
XSUBCNT
XSUBCK
VH
SUBCK
VMM
VLL
Figure 80. XSUBCNT, XSUBCK, and SUBCK Output Polarities
V-DRIVER SLEW RATE CONTROL
SUBSTRATE CLOCK OPERATION (SUBCK)
The AD9920A allows the user to moderate the slew rates of the
V-driver outputs when transitioning to VM and VL (this feature
does not affect transitions to VH). This feature minimizes cou-
pling from V-driver activity that occurs while the AD9920A is
clocking valid image pixel data out of the CCD.
The CCD image exposure time is controlled by the substrate
clock signal (SUBCK), which pulses the CCD substrate to clear
out accumulated charge. The AD9920A supports three types of
electronic shuttering: normal, high precision, and low speed.
Along with the SUBCK pulse placement, the AD9920A can
accommodate different readout configurations to further
suppress the SUBCK pulses during multiple field readouts.
There are both coarse and fine mechanisms for controlling the
slew rate of the V1A to V13 outputs. If SRSW = VDD and
SRCTL = VDD, the V1A to V13 switches have roughly 10%
of their normal drive strength (that is, when SRSW = VSS).
If SRSW = VDD and SRCTL < VDD, the voltage applied to
SRCTL controls the slew rate for V1A to V13 transitions from
VM to VL and from VL to VM. For values from 800 mV to
VDD, V1A to V13 transition at a fraction of their maximum
slew rate that is roughly proportional to the voltage applied to
SRCTL. (It is not recommended that voltages less than 800 mV
be applied to SRCTL.)
The SUBCK signal is a programmable string of pulses, each
occupying a line following the primary sense gate active line,
SGACTLINE1 (see Table 43). The SUBCK signal has program-
mable pulse width, line placement, and number of pulses to
accurately control the exposure time.
SUBCK Normal Operation
By default, the AD9920A operates in the normal SUBCK
configuration, in which the SUBCK signal is pulsing in every
VD field (see Figure 81). The SUBCK pulse occurs once per
line, and the total number of repetitions within the field
determines the length of the exposure time. The SUBCK
pulse polarity and toggle positions within a line are program-
mable using the SUBCK_POL and SUBCK_TOG1 registers
(see Table 43). The number of SUBCK pulses per field is
programmed in the SUBCKNUM register (Address 0x75).
The user must tune this voltage for the specific system to
determine the optimal setting that ensures maximum charge
transfer efficiency and minimizes any coupling from V-driver
activity into the image. V14, V15, and V16 are permanently
weak compared with V1A to V13 and are not affected by the
slew rate control function. Note that the slew rate control
feature is intended only for use with CCDs that require V-driver
activity outside the normal horizontal clock blanking region.
As shown in Figure 81, the SUBCK pulses always begin in the line
following the SG active line, which is specified in the SGACTLINE
registers for each field. The SUBCK_POL, SUBCK_TOG1,
SUBCK_TOG2, SUBCKNUM, and SUBCKSUPPRESS registers
are updated at the start of the line after the sensor gate line, as
described in the Updating New Register Values section.
SHUTTER TIMING CONTROL
The AD9920A supports the generation of electronic shuttering
(SUBCK) and also features flexible general-purpose outputs
(GPOs) to control mechanical shuttering, CCD substrate bias
switching, and strobe circuitry. In the following sections, the
terms sense gate (SG) and vertical sense gate (VSG) are used
interchangeably.
Rev. B | Page 60 of 112
AD9920A
If the PRIMARY_ACTION register is used while the
SUBCK High Precision Operation
SUBCKMASK_NUM and SGMASK_NUM registers are set to
0, the behavior of the SUBCK and VSG signals is not different
from the normal shutter or high precision shutter operations.
Therefore, the primary field counter can be used for other tasks
(described in the General-Purpose Outputs (GPOs) section)
without disrupting normal activity. In addition, a secondary
field counter is available that has no effect on the SUBCK and
VSG signals. These counters are described in detail in the Field
Counters section.
High precision shuttering is used in the same manner as normal
shuttering, but it uses an additional register to control the last
SUBCK pulse. In this mode, the SUBCK still pulses once per line,
but the last SUBCK in the field has an additional SUBCK pulse,
whose location is determined by the SUBCKHP_TOG registers,
as shown in Figure 82. Finer resolution of the exposure time is
possible using this mode. Leaving the SUBCKHP_TOG registers
set to their maximum value (0xFFFFFF) disables the last SUBCK
pulse (default setting).
SUBCKSUPPRESS Register
SUBCK Low Speed Operation
By default, the SUBCK pulses begin in the line following
SGACTLINE1. For applications where the SUBCK pulse should
be suppressed for one or more lines following the VSG line, the
SUBCKSUPPRESS register can be programmed. This register
setting delays the start of the SUBCK pulses until the specified
number of lines following SGACTLINE1.
Normal and high precision shutter operations are used when
the exposure time is less than one field. For exposure times greater
than one field, the low speed (LS) shutter features can be used.
The AD9920A includes a field counter (primary field counter)
to regulate long exposure times. The primary field counter
(Address 0x70) must be activated to serve as the trigger for the
LS operation. The durations of the LS exposure and read are
specified by the SGMASK_NUM and SUBCKMASK_NUM
registers (Address 0x74), respectively. As shown in Figure 83,
this mode suppresses the SUBCK and VSG outputs for up to
8192 fields (VD periods).
Read After Exposure
To read the CCD data after exposure, the SG should resume
normal activity while the SUBCK remains null. By default, the
AD9920A generates the VSG pulses in every field. When only
a single exposure and a single frame read are desired, as in the
case of preview mode, the VSG and SUBCK pulses can operate
in every field.
To activate an LS shutter operation, trigger the start of the
exposure by writing to the PRIMARY_ACTION register bits
according to the desired effect (see Table 59). When the primary
counter is activated, the next VD period becomes the first active
period of the exposure for which the VSG and SUBCK masks
are applied.
Other applications require that a greater number of frames be
read, in which case SUBCK must be masked until the readout is
finished. The SUBCKMASK_NUM register specifies the total
number of fields (exposure and read) to mask SUBCK. A two-field
CCD frame read mode typically requires two additional fields of
SUBCK masking (SUBCKMASK_NUM = 2). A three-field,
6-phase CCD requires three additional fields of SUBCK mask-
ing after the read begins (SUBCKMASK_NUM = 3).
Optionally, if the SUBCKMASK_SKIP1 register is enabled,
the AD9920A ignores the first VSG and SUBCK masks in the
subsequent fields. This is generally desired so that the exposure
time begins in the field after the exposure operation is initiated.
Figure 83 shows operation with SUBCKMASK_SKIP1 = 1. The
same functionality can also be achieved using the PRIMARY_
DELAY register along with the PRIMARY_ACTION register.
Note that the SUBCKMASK_SKIP1 register setting allows
SUBCK pulses at the beginning of the field of exposure.
Table 43. SUBCK and Exposure/Read Register Parameters
Register
Length (Bits) Range
Description
SGMASK_NUM
SUBCKMASK_NUM 13
13
0 to 8191 number of fields Exposure duration (number of fields to suppress VSG) for LS operation.
0 to 8191 number of fields Exposure plus readout duration (number of fields to suppress SUBCK) for LS.
SUBCKMASK_SKIP1
SUBCKSUPPRESS
SUBCKNUM
SG_SUPPRESS
SUBCK_TOG1
1
On/off
0 to 8191 lines
Suppress SG/SUBCK masks for one field (default = 0). Typically set to 1.
Number of lines to suppress the start of SUBCK pulses after SGACTLINE1.
13
13
1
14
14
1
1 to 8191 number of pulses Total number of SUBCK pulses per field, at one pulse per line.
On/off
0 to 16383 pixel locations
0 to 16383 pixel locations
Low/high
Suppress the SG and allow SUBCK to finish at SUBCKNUM.
SUBCK Toggle Position 1.
SUBCK Toggle Position 2.
SUBCK_TOG2
SUBCK_POL
SUBCK start polarity.
SUBCKHP_TOG1
SUBCKHP_TOG2
14
14
0 to 16383 pixel locations
0 to 16383 pixel locations
High precision SUBCK Toggle Position 1. Selectable as SG or VD updated.
High precision SUBCK Toggle Position 2. Selectable as SG or VD updated.
Rev. B | Page 61 of 112
AD9920A
VD
HD
VSG
tEXP
tEXP
SUBCK
SUBCK PROGRAMMABLE SETTINGS:
1. PULSE POLARITY USING THE SUBCK_POL REGISTER.
2. NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER (SUBCKNUM = 3 IN THIS EXAMPLE).
3. PIXEL LOCATION OF PULSE WITHIN THE LINE AND PULSE WIDTH PROGRAMMED USING THE SUBCK_TOG1 TOGGLE POSITION REGISTER.
Figure 81. Normal SUBCK Operation
VD
HD
VSG
tEXP
tEXP
SUBCK
NOTES
1. SECOND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE.
2. LOCATION OF SECOND PULSE IS FULLY PROGRAMMABLE USING THE SUBCKHP TOGGLE POSITION REGISTERS.
Figure 82. High Precision SUBCK Operation
TRIGGER
EXPOSURE
(0x70)
VD
VSG
tEXP
SUBCK
NOTES
1. SUBCK CAN BE SUPPRESSED FOR MULTIPLE FIELDS BY PROGRAMMING THE EXPOSURE REGISTER TO BE GREATER THAN 0.
2. THIS EXAMPLE USES EXPOSURE = 1.
3. TRIGGER REGISTER MUST ALSO BE USED TO START THE LOW SPEED EXPOSURE.
4. VD/HD OUTPUTS CAN ALSO BE SUPPRESSED USING THE VDHD_MASK REGISTER = 1.
Figure 83. Low Speed SUBCK Operation (SUBCKMASK_SKIP1 = 1)
Rev. B | Page 62 of 112
AD9920A
•
•
•
•
ShotTimer with RapidShot
Manual exposure
Manual readout
FIELD COUNTERS
The AD9920A contains three field counters (primary, secondary,
and mode). When these counters are active, they increment with
each VD cycle. The mode counter is the field counter used with
the mode register to control the vertical timing signals (see the
Mode Registers section).
Force to idle
The primary counter regulates the expose and read actions
by regulating the SUBCK and VSG signals. In addition, if the
RapidShot feature is used with the primary counter, the SUBCK
and VSG masking automatically repeats as necessary for multiple
expose/read cycles. The secondary counter has no effect on the
SUBCK or VSG signal. Both counters can be used to regulate
the general-purpose signals described in the General-Purpose
Outputs (GPOs) section.
The primary and secondary counters are more flexible and are
generally used for shuttering signal applications. Both the primary
and secondary counters have several modes of operation that
are selected by Address 0x70. These modes are as follows:
•
•
•
Normal (single count)
RapidShot (repeating count)
ShotTimer (delayed count)
Table 44. Primary/Secondary Field Counter Registers (Address 0x70, Address 0x71, and Address 0x72)
Register
Length (Bits) Description
PRIMARY_ACTION
3
0 = idle, no counter action. GPO signals can still be controlled using polarity or by setting the
appropriate GP_PROTOCOL register to 1.
SECOND_ACTION
3
1 = activate counter. Single cycle of counter from 1 to counter maximum value and then return to
idle state.
2 = RapidShot. After reaching the maximum counter value, the counter wraps and repeats until reset.
3 = ShotTimer. Active single cycle of counter after added delay of n fields (use the corresponding
DELAY register).
4 = ShotTimer with RapidShot. Same as RapidShot (SECOND_ACTION register = 2) but with an added
delay of n fields between each repetition.
5 = manual exposure. Primary counter stays in exposure until manual readout or reset to idle.
This mode keeps the SUBCK and VSG pulses masked indefinitely.
6 = manual readout. Primary counter switches to readout (VSG pulses becomes active).
7 = force to idle.
PRIMARY_MAX
SECOND_MAX
VDHD_MASK
13
12
3
Primary counter maximum value.
Secondary counter maximum value.
Mask VD/HD during counter operation.
PRIMARY_DELAY
13
ShotTimer. Number of fields to delay before the next primary count (exposure) starts. If using
ShotTimer with RapidShot, the delay value is used between each repetition.
PRIMARY_SKIP
1
When using ShotTimer with RapidShot, use the primary delay value only before the first count (exposure).
SECOND_DELAY
13
ShotTimer. Number of fields to delay before the next secondary count starts. If using ShotTimer with
RapidShot, the delay value is used between each repetition.
SECOND_SKIP
1
When using ShotTimer with RapidShot, use the secondary delay value only before the first count.
Rev. B | Page 63 of 112
AD9920A
3. Program the counter parameters (Address 0x71 to
Address 0x72).
4. Activate the counter (Address 0x70).
GENERAL-PURPOSE OUTPUTS (GPOs)
The AD9920A provides programmable outputs to control a
mechanical shutter, the strobe/flash, the CCD bias select signal,
or any other external component with general-purpose (GP)
signals. Eight GP signals, with up to four toggles each, are
available to be programmed and assigned to special GPO pins.
These pins are bidirectional and allow visibility (as an output)
and external control (as an input) of HBLK, PBLK, CLPOB, and
OUT_CONTROL. The GPO registers are described in Table 45.
For Protocol 1 (no counter association), skip Step 3 and Step 4.
With these four steps, the GP signals can be programmed to
accomplish many common tasks. Careful protocol selection and
application of the field counters yields efficient results to allow
the GP signals smooth integration with concurrent operations.
Note that the SUBCK and VSG masks are linked to the primary
counter; however, if their parameters are 0, the GPO can use the
primary counter without expose/read activity.
Note that GPO5 and GPO6 are used to control the SG signals
for the V5 and V6 outputs of the AD9920A. See the SG Control
Using GPO section for more information.
The secondary counter is independent and can be used simul-
taneously with the primary counter. Some applications may
require the use of both primary and secondary field counters
with different GPO protocols, start times, and durations. Such
operations are easily handled by the AD9920A.
GP Toggles
When configured as an output, each GPO output can deliver a
signal that is the result of programmable toggle positions. The
GP signals are independent and can be linked to a specific VD
period or to a range of VD periods via the primary or secondary
field counters through the GP protocol register (Address 0x73).
As a result of their associations with the field counters, the GP
toggles inherit the characteristics of the field counters, such as
RapidShot and ShotTimer.
Several simple examples of GPO applications using only one
GPO and one field counter follow. These examples can be used
as building blocks for more complex GPO activity. In addition,
specific GPO signals can be passed through a four-input lookup
table (LUT) to realize combinational logic between them. For
example, GP1 and GP2 can be sent through an XOR lookup
table, and the result can be delivered on GP1, GP2, or both. In
addition, GP1 or GP2 can deliver its original toggles.
To program the GP toggles, complete the following steps:
1. Program the toggle positions (Address 0x7C to
Address 0xAB).
2. Program the GP protocol (Address 0x73).
Table 45. GPO Registers
Register
Length (Bits) Range
Description
GP1_PROTOCOL
GP2_PROTOCOL
GP3_PROTOCOL
GP4_PROTOCOL
GP5_PROTOCOL
GP6_PROTOCOL
GP7_PROTOCOL
GP8_PROTOCOL
MANUAL_TRIG
GP[1:8]_POL
3
3
3
3
3
3
3
3
8
8
8
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
0 to 7
On/off
Low/high
On/off
0 = idle
1 = no counter association; use MANUAL_TRIG bits to enable each GP signal.
2 = test only.
3 = test only.
4 = link to mode counter (from vertical timing generation).
5 = link to primary counter (also allows GP signals to repeat with RapidShot).
6 = link to secondary counter (also allows GP signals to repeat with RapidShot).
7 = keep on.
Manual trigger for each GP signal. For use with Protocol 1.
Starting polarity for GP signals. Only updated when GPx_PROTOCOL = 0.
1 = select GP toggles visible at GPO1 to GPO4, GPO7, and GPO8 when output is
enabled (default).
SEL_GP[1:8]
0 = select vertical signals visible at GPO4 to GPO8 when output is enabled.
GPO4: XSUBCK.
GPO5: XV21.
GPO6: XV22.
GPO7: XV23.
GPO8: XV24.
GPO_OUTPUT_EN
8
On/off
1 = enable GPO1 to GPO4, GPO7, and GPO8 outputs (one bit per output).
0 = disable GPO1 to GPO4, GPO7, and GPO8 outputs; pins are high-Z (default).
GPx_USE_LUT
LUT_FOR_GP12
LUT_FOR_GP34
LUT_FOR_GP56
8
4
4
4
On/off
Send GP signals through a programmable lookup table (LUT).
Desired logic to be realized on GPO1 combined with GPO2.
Desired logic to be realized on GPO3 combined with GPO4.
Desired logic to be realized on GPO5 combined with GPO6.
Logic setting
Logic setting
Logic setting
Rev. B | Page 64 of 112
AD9920A
Register
Length (Bits) Range
Description
LUT_FOR_GP78
4
Logic setting
Desired logic to be realized on GPO7 combined with GPO8.
Example logic settings for LUT_FOR_GPxy:
0x06 = GPy XOR GPx (see Figure 89).
0x07 = GPy NAND GPx.
0x08 = GPy AND GPx.
0x0E = GPy OR GPx.
GPx_TOGx_FD
GPx_TOGx_LN
GPx_TOGx_PX
GPO_INT_EN
13
13
13
1
0 to 8191 fields Field of activity, relative to primary and secondary counter for corresponding toggle.
0 to 8191 lines Line of activity for corresponding toggle.
0 to 8191 pixels Pixel of activity for corresponding toggle.
On/off
When set to 1, internal signals are viewable on GPO1 to GPO3. Also, set the
SEL_GPx bit low to output internal signals.
GPO1 = internal clock.
GPO2 = CLPOB.
GPO3 = delayed sample clock.
Rev. B | Page 65 of 112
AD9920A
Single-Field Toggles
Scheduled Toggles
Single-field toggles occur in the next field only. There can be up to
four toggles in the field. The mode is set with GP_PROTOCOL
equal to 1, and the toggles are triggered in the next field by
writing to the MANUAL_TRIG register (Register 0x70, Bits[13:6]).
In this mode, the field toggle settings must be set to a value of 1.
Two consecutive fields do not have activity. If toggles are required
to repeat in the next field, the MANUAL_TRIG register can be
written to in consecutive fields.
Scheduled toggles are programmed to occur during upcoming
fields. For example, there can be one toggle in Field 1, two
toggles in Field 3, and a last toggle in Field 4. The mode is set
with GP_PROTOCOL = 5 or GP_PROTOCOL = 6. Mode 5
tells the GPO to obey the primary field counter, and Mode 6
tells the GPO to obey the secondary field counter.
Note that for GP_PROTOCOL = 5 or GP_PROTOCOL = 6, at
least one toggle must be programmed in Field 1 for the AD9920A
to output the proper pattern on the GPO pins. If no toggle is
programmed in Field 1, all subsequent toggle positions are
ignored when GP_PROTOCOL = 5 or GP_PROTOCOL = 6.
This restriction applies only to GP_PROTOCOL = 5 or
GP_PROTOCOL = 6.
Preparation
The GP toggle positions can be programmed any time prior to
use. For example,
0x7C
0x7D
0x7E
0x7F
0x80
0x81
← 0x000A001
← 0x0002000
← 0x000000F
← 0x00C4002
← 0x0004000
← 0x00000B3
Preparation
The GP toggle positions can be programmed any time prior to
use. For example,
0x7C
0x7D
0x7E
← 0x00C4001
← 0x0004000
← 0x00000B3
Details
A) Field 0:
0x70
0x73
← 0x0000040
← 0x0000001
Details
B) Field 1:
0x73
← 0x0000000
A) Field 0:
0x70
0x73
← 0x0000008
← 0x0000006
VD
1
2
VD
1
A
REGISTER WRITE
GP1_PROTOCOL
A
B
REGISTER WRITE
GP1_PROTOCOL
GPO1
0
0
6
1
0
1
0
SECONDARY
COUNT
2
0
(IDLE)
GPO1
NOTES
1. THE FIELD TOGGLE POSITION MUST BE SET TO 1 WHEN
GP PROTOCOL IS 1.
CAUTION! THE GP_PROTOCOL MUST BE RESET BEFORE
USING AGAIN.
CAUTION! THE PRIMARY COUNTER REGULATES THE SUBCK
AND VSG ACTIVITY. LINK A GPO TO THE PRIMARY COUNTER
ONLY IF SUBCK AND VSG ACTIVITY WILL OCCUR DURING
EXPOSURE/READ.
Figure 85. Scheduled Toggles Using GP_PROTOCOL = 6
Figure 84. Single-Field Toggles Using GP_PROTOCOL = 1
Rev. B | Page 66 of 112
AD9920A
RapidShot Sequences
ShotTimer Sequences
RapidShot technology provides continuous repetition of
scheduled toggles.
ShotTimer technology provides internal delay of scheduled
toggles. The delay is in terms of fields.
Preparation
Preparation
The GP toggle positions can be programmed any time prior to
use. For example,
The GP toggle positions can be programmed any time prior to
use. For example,
0x71
0x7C
0x7D
0x7E
0x7F
0x80
0x81
0x73
← 0x0004000
← 0x000A001
← 0x0002000
← 0x000000F
← 0x00C4002
← 0x0004000
← 0x00000B3
← 0x0000006
0x71
0x72
0x7C
0x7D
0x7E
0x73
← 0x0004000
← 0x000C000
← 0x000A001
← 0x0002000
← 0x000000F
← 0x0000006
Details
A) Field 0:
0x70
← 0x0000018
Details
A) Field 0:
B) Field 2:
0x70
0x70
← 0x0000010
← 0x0000007
2
VD
1
A
REGISTER WRITE
GP1_PROTOCOL
1
2
3
4
5
VD
0
6
1
A
B
REGISTER WRITE
GP1_PROTOCOL
SECONDARY
COUNT
0 (IDLE)
2
3
1
2
0
0
6
1
GPO1
SECONDARY
COUNT
0 (IDLE)
2
1
2
1
0
Figure 87. ShotTimer Toggle Operation Using GP_PROTOCOL = 6
GPO1
TERMINATED
AT VD EDGE
CAUTION! THE FIELD COUNTER MUST BE FORCED INTO IDLE
STATE TO TERMINATE REPETITIONS.
Figure 86. RapidShot Toggle Operation Using GP_PROTOCOL = 6
Rev. B | Page 67 of 112
AD9920A
GP LOOKUP TABLE (LUT)
Table 46. LUT Results Based on GP1 and GP2 Values
The AD9920A is equipped with a lookup table for each pair
of consecutive GP signals when configured as outputs. GPO1 is
always combined with GPO2, GPO3 is always combined with
GPO4, GPO5 is always combined with GPO6, and GPO7 is
always combined with GPO8. The external GPO outputs from
each pair can output the result of the LUT or the original GP
internal signal.
GP2 GP1 LUT: XOR LUT: NAND LUT: AND LUT: OR
0
0
1
1
0
1
0
1
0
1
1
0
1
1
1
0
0
0
0
1
0
1
1
1
LUT_FOR_GP12[11:8] = 0x06
GP2_USE_LUT = 1 GP1_USE_LUT = 0
GP1_USE_LUT
GP1
GP2
0
GPO1
GPO2
GP1
1
GPO1
LUT
NOTES
GP2
1
1. LOGIC COMBINATION (XOR) OF PROGRAMMED TOGGLES
GP1 AND GP2.
GPO2
Figure 89. LUT Example for GP1 XOR GP2
0
Field Counter and GPO Limitations
GP2_USE_LUT
The following is a summary of the known limitations of the
field counters and GPO signals.
Figure 88. Internal LUT for GPO1 and GPO2 Signals
Address 0x7B configures the behavior of the LUT and which
signals receive the result. Each 4-bit LUT_FOR_GPxy register
can realize any logic combination of GPx and GPy. For example,
Table 46 shows how the register values of LUT_FOR_GP12,
Bits[11:8], are determined. XOR, NAND, AND, and OR results
are shown, but any 4-bit combination is possible. A simple
example of XOR gating is shown in Figure 89.
•
The field counter trigger (PRIMARY_ACTION and
SECOND_ACTION registers, Address 0x70) is
automatically reset at the start of every VD period.
Therefore, there must be one VD period between
sequential programming to that address.
If GPx_PROTOCOL = 1, it must be manually reset to
GPx_PROTOCOL = 0 one VD period before it can be
used again. If manual toggles are desired in sequential
fields, the MANUAL_TRIG register should be used in
conjunction with GPx_PROTOCOL = 1.
•
Rev. B | Page 68 of 112
AD9920A
Write to the mode registers to configure the next five fields.
The first two fields during exposure are the same as the
current draft mode fields, and the following three fields are
the still image frame readout fields. The register settings
for the draft mode field and the three readout fields are
previously programmed. Note that if the mode registers are
changed to VD updated, only one field of exposure should
be included (the second one) because the mode settings are
delayed an extra field.
COMPLETE EXPOSURE/READOUT OPERATION
USING PRIMARY COUNTER AND GPO SIGNALS
Figure 90 illustrates a typical expose/read cycle while exercising
the GPO signals. Using a three-field CCD with an exposure time
that is greater than one field but less than two fields in duration
requires a total of five fields for the entire exposure/readout
operation. Other exposure times and CCD field configurations
require modification of these example settings.
Note that if the mode registers are changed to be VD updated,
as shown in the Mode Registers section and in Figure 63, the
mode update is delayed by one additional field. This should be
accounted for in selecting the number of fields to cycle and in
determining which VD location to write to the mode registers.
2. VD/HD falling edge updates the serial writes from 1.
3. GP3 (VSUB) output turns on at the field/line/pixel specified.
In Figure 90, VSUB Example 1 and Example 2 use
GP3TOG1_FD = 1.
4. GP1 (STROBE) output turns on and off at the location
specified.
5. GP2 (MSHUT) output turns off at the location specified.
6. The next VD falling edge automatically starts the first
read field.
7. The next VD falling edge automatically starts the second
read field.
1. The primary counter is used to control the masking
of VSG and SUBCK during exposure/readout. The
PRIMARY_MAX register (Address 0x71) should be set
equal to the total number of fields used for exposure and
readout. In this example, PRIMARY_MAX = 5.
The SUBCK masking should not occur immediately at
the next VD edge (Step 2) because this would define an
exposure time that begins in the previous field. Write to
the PRIMARY_DELAY register (Address 0x72) to delay
the masking of VSG and SUBCK pulses in the first
exposure field. In this example, PRIMARY_DELAY = 1.
8. The next VD falling edge automatically starts the third
read field.
9. Write to the mode register to reconfigure the single draft
mode field timing. Note that if the mode registers are changed
to VD updated, this write should occur one field earlier.
10. VD/HD falling edge updates the serial writes from 9.
VSG outputs return to draft mode timing. SUBCK output
resumes operation. GP2 (MSHUT) output returns to the
on position (active or open). GP3 (VSUB) output returns
to the off position (inactive).
Write to the SUBCKMASK_NUM register (Address 0x74) to
specify the number of fields to mask SUBCK while the CCD
data is read. In this example, SUBCKMASK_NUM = 4.
Write to the SGMASK_NUM register (Address 0x74) to
specify the number of fields to mask VSG outputs during
exposure. In this example, SGMASK_NUM = 1.
Write to the PRIMARY_ACTION register (Address 0x70)
to trigger the GP1 (STROBE), GP2 (MSHUT), and GP3
(VSUB) signals and to start the expose/read operation.
Rev. B | Page 69 of 112
AD9920A
9 0 8 - 8 7 0 6
Figure 90. Complete Exposure/Readout Operation Using Primary Counter and GPO Signals
Rev. B | Page 70 of 112
AD9920A
A serial write to the GP5_PROTOCOL register is used to set
SG CONTROL USING GPO
the protocol of GPO5 equal to 1 (no counter association). The
manual trigger bit for GPO5 (Address 0x70, Bit 10) is then
written on the field previous to the field that requires the GPO5
(SG) signal. At the end of the readout, the GP5_PROTOCOL
register can be reset to 0 (idle).
The AD9920A uses two of the GPO signals to generate the SG
signals for the three-level outputs V5 and V6. Because GPO5
and GPO6 are used as inputs to the vertical driver, they must
be properly initialized at power-up to avoid incorrect V-driver
output levels. During different CCD timing modes, the GPO
signals can be controlled in several ways to produce the proper
SG signal operation.
Triggered Control of GPO5
Figure 93 shows the 19-channel mode, again with GPO5 used
to control the SG signal for the V5 output. In this configuration,
however, the secondary counter (scheduled toggles) method is
used. A serial write to the GP5_PROTOCOL register is used to
set the protocol of GPO5 equal to 6 (link to secondary counter).
At the start of the exposure, the field toggle location for GPO5 is
programmed to the desired field count value to trigger the GPO5
signal. Then, the secondary counter is triggered. The secondary
counter automatically increments and generates the GPO pulse
in the proper field location during readout. At the end of the
readout, the GPO5 protocol is automatically reset to idle.
GPO5/GPO6 Power-Up Settings
GPO5 and GPO6 should be programmed with a polarity of
high at power-up by setting the GP5_POL and GP6_POL bits
(Address 0x7A, Bits[5:4]) equal to 11. This setting provides the
correct polarity in the V-driver, because the XSG signals should
be active low at the V-driver inputs. At power-up, the GPO5
and GPO6 outputs should also be enabled, by setting Register
Address 0x7A, Bits[21:20] and Bits[13:12] all equal to 1, so that
there is a defined state at all times.
Manual Control of GPO5
The advantage of using the secondary counter is that no serial
writes are required during exposure or readout, unlike the manual
control method. The disadvantage is that more information must
be programmed before the start of exposure, such as the exact
field location where the GPO pulse is needed, taking into
account the length of the exposure and readout fields.
Figure 91 shows an example exposure/readout sequence of the
AD9920A used in 18-channel mode without any GPO signals
used for SG control. Figure 92 shows the 19-channel mode,
with GPO5 used to control the SG signal for the V5 output. In
this configuration, the GPO manual control method is used.
SERIAL
1
6
WRITES
2
3
4
5
7
VD
STILL IMAGE READOUT
VSG
7
tEXP
SUBCK
OPEN
OPEN
MECHANICAL
SHUTTER
CLOSED
STILL IMAGE
FIRST FIELD
STILL IMAGE
SECOND FIELD
STILL IMAGE
THIRD FIELD
DRAFT IMAGE DRAFT IMAGE
DRAFT IMAGE
CCD
OUT
Figure 91. Exposure/Readout Operation Without Using GPO for SG Signal
Rev. B | Page 71 of 112
AD9920A
SERIAL
WRITES
7
1
5
2
3
4
6
8
VD
STILL IMAGE READOUT
VSG
(XSG1 TO XSG7)
8
GPO5
(XSG8 FOR V5)
tEXP
SUBCK
OPEN
OPEN
MECHANICAL
SHUTTER
CLOSED
STILL IMAGE
FIRST FIELD
STILL IMAGE
SECOND FIELD
STILL IMAGE
THIRD FIELD
DRAFT IMAGE DRAFT IMAGE
DRAFT IMAGE
CCD
OUT
Figure 92. Using GPO5 Manual Trigger Mode for SG Signal
SERIAL
WRITES
1
6
2
3
4
5
7
VD
STILL IMAGE READOUT
VSG
(XSG1 TO XSG7)
7
GPO5
(XSG8 FOR V5)
SECONDARY
COUNT
0 (IDLE)
1
2
3
4
5
0
tEXP
SUBCK
MECHANICAL
SHUTTER
OPEN
OPEN
CLOSED
STILL IMAGE
FIRST FIELD
STILL IMAGE
SECOND FIELD
STILL IMAGE
THIRD FIELD
DRAFT IMAGE DRAFT IMAGE
DRAFT IMAGE
CCD
OUT
Figure 93. Using GPO5 with Secondary Counter to Control SG Signal
Rev. B | Page 72 of 112
AD9920A
Shutter Operation in SLR Mode
MANUAL SHUTTER OPERATION USING
ENHANCED SYNC MODES
The following steps are shown in Figure 99.
The AD9920A also supports an external signal to control exposure,
using the SYNC input. Generally, the SYNC input is used as an
asynchronous reset signal during master mode operation. When
the enhanced SYNC mode is enabled, the SYNC input provides
additional control of the exposure operation.
1. To turn on VSUB, write to the appropriate GP registers to
trigger VSUB and start the manual exposure (PRIMARY_
ACTION = 5). This change takes effect after the next VD.
SUBCK is suppressed during the exposure and readout
phases.
2. To turn on MSHUT during the interval between the next
VD and SYNC, write to the appropriate GP register. When
MSHUT is in the on position, it has line and pixel control.
This change takes effect on the SYNC falling edge because
there is an internal VD.
Normal SYNC Mode (Mode 1)
By default, the SYNC input is used in master mode to synchronize
the internal counters of the AD9920A with external timing. The
horizontal, vertical, and field designator signals are reset by the
rising edge of the SYNC pulse. Figure 94 shows how this mode
operates, highlighting the behavior of the mode field designator.
3. If the mode register is programmed to cycle through
multiple fields (5, 7, 3, 5, 7, 3, …, in this example), the
internal field designator increments. If the mode register
is not required to increment, set up the mode register such
that it outputs only one field. This prevents the mode
counter from incrementing during the SYNC interval.
4. Write to the manual readout trigger to begin the manual
readout (PRIMARY_ACTION = 6). Write to the appropriate
GP registers to trigger MSHUT to toggle low at the end of
the exposure. This change takes effect on the SYNC rising
edge during readout. Because VD register update is disabled,
the trigger takes effect on the SYNC rising edge. The MSHUT
falling edge is aligned with the SYNC rising edge. Because
the MSHUT falling edge is aligned with VD, it may be
necessary to insert a dummy VD to delay the readout.
Enhanced SYNC Modes (Mode 2 and Mode 3)
The enhanced SYNC modes can be used to accommodate unique
synchronization requirements during exposure operations. In
SYNC Mode 2, the V and VSG outputs are suspended and the
VD output is masked. The V-outputs are held at the dc value
established by the V-Sequence 0 start polarities. There is no SCP
operation, but the H-counter is still enabled. Finally, the AFE
sampling clocks, HD, H/RG, CLPOB, and HBLK, are operational
and use V-Sequence 0 behavior. See Figure 95 for more details.
To enable the enhanced SYNC modes, set the ENH_SYNC_EN
register (Address 0x13, Bit 3) to 1.
SYNC Mode 3 uses all the features of Mode 2, but the V-outputs
are continuous through the SYNC pulse interval. VD control
pulses are masked during the SYNC interval, and the HD pulse
can also be masked, if required (see Figure 96).
Because the internal exposure counter (the primary counter) is
not used during manual SYNC mode operation and the VD
register update is disabled, control is lost on the fine placement
of the GP signals for VSUB, MSHUT, and STROBE edges while
SYNC is low.
It is important to note that in both enhanced modes, the SYNC
pulse resets the counters at both the falling edge and the rising
edge of the SYNC pulse.
Serial Registers for Enhanced SYNC Modes
Register Update and Field Designator
SYNC Mode 2 and SYNC Mode 3 are controlled using the
registers listed in Table 47. These registers are located at
Address 0x13, Bits[6:3].
When using SYNC Mode 2 or SYNC Mode 3, VD-updated
registers, such as PRIMARY_ACTION, are not updated during
the SYNC interval, and the SCP0 function is ignored and held
at 0 (see Figure 97).
Table 47. Registers for Enhanced SYNC Modes
Length
(Bits)
When using either SYNC Mode 2 or SYNC Mode 3, both the
rising and falling edges increment the internal field designator;
therefore, the new register data takes effect and VTP information is
updated to new SEQ0 data. However, this does not occur if the
mode register is creating an output of one field. In that case, the
region, sequence, and group information does not change (see
Figure 98).
Register
Description
ENH_SYNC_EN
1
High active to enable masking
(default low)
High active to enable masking
(default high)
High active to enable masking
(default high)
High active to enable masking
(default low)
SYNC_MASK_V
SYNC_MASK_VD
SYNC_MASK_HD
1
1
1
Rev. B | Page 73 of 112
AD9920A
SYNC
VD
FIELD
DESIGNATOR
7
3
5
SUSPEND
HD
H1 TO H4, RG, XV1
TO XV24,
VSG, SUBCK
NOTES
1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0.
2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).
3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x13).
4. THE SYNC RISING EDGE CAUSES THE INTERNAL FIELD DESIGNATOR TO INCREMENT.
5. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUT_CONTROL = LOW.
6. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL THE SYNC RESET EDGE.
Figure 94. Normal SYNC (Default Mode 1)
2
1
SYNC
3
VD
HD
VDLEN
4
SCP
5
XV1 TO XV24
1
2
3
4
5
FALLING EDGE RESYNCS THE CIRCUIT TO THE LINE/PIXEL NUMBER 0. VD AND HD INTERNALLY RESYNC.
RISING EDGE RESETS COUNTERS.
VD IS DISABLED DURING SYNC. THE REGISTER IS PROGRAMMABLE.
SCP, HBLK, AND CLPOB ARE HELD AT SEQ0 VALUE.
XV1 TO XV24 SIGNALS ARE HELD AT THE V-OUTPUT START POLARITY.
Figure 95. Enhanced SYNC Mode 2 with Vertical Signals Held at VTP Start Value
Rev. B | Page 74 of 112
AD9920A
SYNC
1
2
VD
HD
VDLEN
SCP
3
XV1 TO XV24
1
2
3
SYNC_MASK_VD REGISTER ENABLES MASKING OF VD DURING SYNCSUSPEND WHEN SET HIGH (DEFAULT).
SYNC_MASK_HD REGISTER ENABLES MASKING OF HD DURING SYNCSUSPEND WHEN SET HIGH (DEFAULT).
V-OUTPUT PULSES CONTINUE IN SEQUENCE.
Figure 96. Enhanced SYNC Mode 3
SYNC
VD
1
1
1
1
1
1
1
VD REGISTERS ARE UPDATED HERE.
NOTES
1. VD-UPDATED REGISTERS (FOR EXAMPLE, PRIMARY_ACTION) ARE DISABLED DURING THE SYNC INTERVAL.
Figure 97. Register Update Behavior
SYNC
VD
FIELD
DESIGNATOR
5
7
3
5
7
1
1
1
FIELD DESIGNATOR IS INCREMENTED ON BOTH SYNC EDGES.
Figure 98. Enhanced SYNC Mode Effect on Field Designator
Rev. B | Page 75 of 112
AD9920A
4
SYNC
1
2
VD
3
FIELD
DESIGNATOR
3
5
7
3
5
7
3
5
7
V-OUTPUTS
MSHUT
VSUB
5
5
DUMMY
FIELD
READOUT READOUT
ODD EVEN
DRAFT
EXPOSURE
DRAFT
SHUTTER OPERATION IN SLR MODE
1
REFER TO STEP 1.
2
REFER TO STEP 2.
3
REFER TO STEP 3.
4
REFER TO STEP 4.
5
SUBCK OUTPUT IS SUPPRESSED DURING EXPOSURE AND READOUT WHEN EXPOSURE TRIGGER IS USED.
Figure 99. Enhanced SYNC Mode—Manual Shutter Operation, SLR Mode
Rev. B | Page 76 of 112
AD9920A
ANALOG FRONT END DESCRIPTION AND OPERATION
0.1µF 0.1µF
AVDD
REFB REFT
0.4V 1.4V
AD9920A
DC RESTORE
0.5V
FIXED
DELAY
1
0
CLI
DOUTPHASE
0
1
SHP
PBLK
DCLK
INTERNAL
V
DCBYP
REF
DCLK
MODE
SHP
SHD
DOUTDELAY
2V
DCLKINV
12
FULL
SCALE
6dB
VGA
1
S1
0.1µF
CCDIN
12-BIT
ADC
OUTPUT
DATA
LATCH
D0 TO D11
CDS
–3dB, 0dB,
+3dB, +6dB
PBLK
PBLK
OPTICAL BLACK
CLAMP
1
S2
DAC
CDS GAIN
REGISTER
CLPOB PBLK
DIGITAL
FILTER
BLANK TO
ZERO OR
CLAMP LEVEL
DOUTPHASE
SHP SHD
CLAMP LEVEL
REGISTER
CLPOB PBLK
VD
HD
PRECISION
V-H
CLI
TIMING
TIMING
GENERATOR
GENERATION
1
S1 IS NORMALLY CLOSED; S2 IS NORMALLY OPEN.
Figure 100. Analog Front End Functional Block Diagram
The AD9920A signal processing chain is shown in Figure 100.
Each processing step is essential for achieving a high quality
image from the raw CCD pixel data.
Note that because the CDS input is shorted during PBLK, the
CLPOB pulse should not be used during the same active time as
the PBLK pulse.
DC Restore
Correlated Double Sampler (CDS)
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.3 V (AVDD − 0.5 V), making it compatible
with the 1.8 V core supply voltage of the AD9920A. The dc
restore switch is active during the SHP sample pulse time.
The CDS circuit samples each CCD pixel twice to extract the
video information and to reject low frequency noise. The timing
shown in Figure 23 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and data level of the CCD signal, respectively. The place-
ment of the SHP and SHD sampling edges is determined by the
setting of the SHPLOC and SHDLOC registers located at
Address 0x38. Placement of these two clock signals is critical
for achieving the best performance from the CCD.
The dc restore circuit can be disabled when the optional PBLK
signal is used to isolate large-signal swings from the CCD input
(see the Analog Preblanking section). Bit 6 of AFE Register
Address 0x00 controls whether the dc restore is active during
the PBLK interval.
The CDS gain is variable in four steps by using AFE Register
Address 0x04: −3 dB, 0 dB, +3 dB, and +6 dB. Improved noise
performance results from using the +3 dB setting, but the input
range is reduced (see the Analog Specifications section).
Analog Preblanking (PBLK)
During certain CCD blanking or substrate clocking intervals, the
CCD input signal to the AD9920A may increase in amplitude
beyond the recommended input range. The PBLK signal can be
used to isolate the CDS input from large-signal swings. While
PBLK is active (low), the CDS input is internally shorted to
ground. It is recommended that PBLK be used to protect the
CDS input during the horizontal blanking and/or when the
SUBCK output is toggled.
Rev. B | Page 77 of 112
AD9920A
Variable Gain Amplifier (VGA)
Note that if the CLPOB loop is disabled, higher VGA gain
settings reduce the dynamic range because the uncorrected
offset in the signal path is gained up.
The VGA stage provides a gain range of approximately 6 dB to
42 dB, programmable with 10-bit resolution through the serial
digital interface. A gain of 6 dB is needed to match a 1 V input
signal with the ADC full-scale range of 2 V. When compared with
1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB.
The CLPOB pulse should be aligned with the CCD optical black
pixels. It is recommended that the CLPOB pulse duration be at
least 20 pixels wide. Shorter pulse widths can be used, but the
ability of the loop to track low frequency variations in the black
level is reduced. See the Horizontal Timing Sequence Example
section for timing examples.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain is calculated for any gain register value by
Gain (dB) = (0.0358 × Code) + 5.76 dB
Digital Data Outputs
where Code is the range of 0 to 1023.
The AD9920A digital output data is latched using the rising
edge of the DOUTPHASE register value, as shown in Figure 100.
Output data timing is shown in Figure 25 and Figure 26. It is
also possible to leave the output latches transparent so that the
data outputs are valid immediately from the ADC. Programming
Bit 1 in AFE Register Address 0x01 to 1 sets the output latches
to transparent. The data outputs can also be disabled (three-
stated) by setting Bit 0 in AFE Register Address 0x01 to 1.
42
36
30
24
18
12
6
The DCLK output can be used for external latching of the
data outputs. By default, the DCLK output tracks the values
of the DOUTPHASE registers. By setting the DCLKMODE
register, the DCLK output can be held at a fixed phase, and the
DOUTPHASE register values are ignored. The DCLK output
can also be inverted with respect to the data output, using the
DCLKINV register bit.
0
127
255
383
511
639
767
895
1023
VGA GAIN REGISTER CODE
Figure 101. VGA Gain Curve
Analog-to-Digital Converter (ADC)
The switching of the data outputs can couple noise back into
the analog signal path. To minimize switching noise, it is
recommended that the DOUTPHASE registers be set to the
same edge as the SHP sampling location or up to 15 edges after
the SHP sampling location. Other settings can produce good
results, but experimentation is necessary. It is recommended
that the DOUTPHASE location not occur between the SHD
sampling location and 15 edges after the SHD location. For
example, if SHDLOC = 0, DOUTPHASE should be set to an
edge location of 16 or greater. If adjustable phase is not required
for the data outputs, the output latch can be left transparent
using Bit 1 in AFE Register Address 0x01.
The AD9920A uses a high performance ADC architecture
optimized for high speed and low power. Differential non-
linearity (DNL) performance is typically better than 0.5 LSB.
The ADC uses a 2 V input range. See Figure 6, Figure 7, and
Figure 8 for typical linearity and noise performance plots for
the AD9920A.
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD black level. During the optical black (shielded) pixel interval
on each line, the ADC output is compared with a fixed black
level reference, which is selected by the user in the CLAMPLEVEL
register. The value can be programmed from 0 LSB to 255 LSB
in 1023 steps.
The data output coding is normally straight binary, but the
coding can be changed to gray coding by setting Bit 2 in AFE
Register Address 0x01 to 1.
The resulting error signal is filtered to reduce noise, and the
correction value is applied to the ADC input through a DAC.
Normally, the optical black clamp loop is turned on once per
horizontal line, but this loop can be updated more slowly to suit
a particular application. If external digital clamping is used during
the postprocessing, the AD9920A optical black clamping can be
disabled using Bit 2 in AFE Register Address 0x00. When the
loop is disabled, the CLAMPLEVEL register can still be used to
provide fixed offset adjustment.
Rev. B | Page 78 of 112
AD9920A
APPLICATIONS INFORMATION
7. Load the required registers to configure vertical timing,
horizontal timing, high speed timing, and shutter timing.
RST
POWER-UP SEQUENCE FOR MASTER MODE
When the AD9920A is powered up, the following sequence is
recommended (refer to Figure 102 for each step). Note that a
SYNC signal is required for master mode operation. If an external
SYNC pulse is not available, it is possible to generate an internal
SYNC event by writing to the SWSYNC register.
8. Reset the internal timing core (TGCORE_ ). If a 2× clock
is used for CLI, the CLIDIVIDE register (Address 0x0D)
RST
should be set to 1 before TGCORE_
is written
(Address 0x14 = 0x01). Wait at least 100 μs before
performing Step 9.
1. Turn on the 3 V and 1.8 V power supplies for the
AD9920A and start master clock CLI.
9. Bring the VDR_EN pin high. If driving VDR_EN with
a GPO, write to the appropriate GPO polarity bit in
Address 0x7A to set the VDR_EN signal high (updated at
the next VD). Note that IOVDD must be at the same
voltage as VDVDD if GPO is used for VDR_EN.
10. Enable the AD9920A outputs (OUT_CONTROL register,
Address 0x11 = 0x01). OUT_CONTROL is a VD-updated
register; therefore, the outputs become active after the next
VD falling edge.
RST
RST
2. The SYNC/
default. It must be brought high before any register writes
RST
pin is configured as the
pin by
are performed. Configure the SYNC/
pin for SYNC
functionality by writing Register 0x12 = 0x00, and then
perform a software reset by writing Register 0x10 to 0x01.
3. Make sure that VDR_EN is low. If driving VDR_EN with a
GPO, set the appropriate bit in the GPO_OUTPUT_EN
register (Address 0x7A, Bits[23:16]) to 1 to configure it as
an output and make sure that the appropriate bit in the
GP_STBY3 register (Address 0x27, Bits[15:8]) is set to 0.
4. Power up the V-driver supplies.
11. Enable master mode operation by setting Register 0x20 =
0x01.
12. Generate a SYNC event. SYNC should be high at power-
up. Bring the SYNC input low for a minimum of 100 ns,
and then bring SYNC high again. This resets the internal
counters and starts VD/HD operation. The first VD/HD
edge allows VD-updated register updates (including updates
of OUT_CONTROL) to occur, enabling all outputs. If a
hardware SYNC is not available, the SWSYNC register
(Address 0x13, Bit 24) can be used to initiate a SYNC event.
5. Define the standby status of the AD9920A vertical outputs.
Write to the Standby2 and Standby3 polarity registers
(Address 0x25 and Address 0x26 = 0x1FF8000).
Write 0xFF8000 to Address 0x1C to configure the XV and
VSG signals. Write 0x100000 to Register 0xD1. When using
3-phase HCLK mode, enable this mode before Step 6 by
setting Address 0x24 = 0x10.
Note that VDR_EN must remain high to achieve proper vertical
outputs during normal operation.
6. Place the AFE into normal operation and enable clamping
(Address 0x00 = 0x04). If using CLO to drive a crystal, set
RST
OSC_
= 1. Wait at least 500 μs before performing Step 8.
Rev. B | Page 79 of 112
AD9920A
4
1
VH SUPPLY
+3V SUPPLIES
+1.8V SUPPLY
POWER
SUPPLIES
0V
VM SUPPLY
VL SUPPLY
CLI
(INPUT)
SERIAL
WRITES
8
9
2
3
5
6
7
10
11
500µs
100µs
SYNC/RST
12
VD
(INPUT)
HD
(INPUT)
LOW BY
DEFAULT
XV1 TO XV24
XSUBCK
(INTERNAL)
CLOCKS ACTIVE WHEN OUT_CONTROL
REGISTER UPDATED AT VD/HD EDGE
H2, H4, H6, H8
HIGH-Z BY
DEFAULT
H-CLOCKS
VDR_EN
H1, H3, H5, H7, RG
VDD
0V
V-DRIVER OUTPUTS ACTIVE
WHEN VDR_EN IS HIGH
VH
V1 TO V16
(V-DRIVER OUTPUT)
VM
VL (SUBCK ONLY)
Figure 102. Recommended Power-Up Sequence and Synchronization, Master Mode
Rev. B | Page 80 of 112
AD9920A
6. Place the AFE into normal operation and enable clamping
(Address 0x00 = 0x04). If using CLO to drive a crystal, set
POWER-UP SEQUENCE FOR SLAVE MODE
When the AD9920A is used in slave mode, the VD/HD inputs
are used to synchronize the internal counters. For more detail
on the counter reset operation, see Figure 103.
RST
OSC_
= 1. Wait at least 500 μs before performing Step 8.
7. Load the required registers to configure vertical timing,
horizontal timing, high speed timing, and shutter timing.
1. Turn on the 3 V and 1.8 V power supplies for the
AD9920A, and start master clock CLI.
2. Reset the internal AD9920A registers.
RST
8. Reset the internal timing core (TGCORE_
If a 2× clock is used for CLI, the CLIDIVIDE register
RST
).
(Address 0x0D) should be set to 1 before TGCORE_
is
RST
RST
RST
If the SYNC/
pin is functioning as
RST
, apply a rising
pin is function-
written (Address 0x14 = 0x01). Wait at least 100 μs before
performing Step 9.
edge to the SYNC/
pin. If the SYNC/
ing as SYNC, tie this pin high. Then perform a software
reset by writing Register 0x10 to 0x01.
9. Bring the VDR_EN pin high. If driving VDR_EN with
a GPO, write to the appropriate GPO polarity bit
(Address 0x7A) to set the VDR_EN signal high (updated at
the next VD). Note that IOVDD must be at the same
voltage as VDVDD if GPO is used for VDR_EN.
10. Enable the AD9920A outputs (OUT_CONTROL register,
Address 0x11 = 0x01). OUT_CONTROL is a VD-updated
register; therefore, the outputs become active after the next
VD falling edge.
11. Enable slave mode operation by setting Register 0x0E = 0x100.
12. Start VD and HD timing to synchronize the internal
counters and begin operation. VD-updated registers are
updated at the first VD falling edge.
3. Make sure that VDR_EN is low. If driving VDR_EN with a
GPO, set the appropriate bit in the GPO_OUTPUT_EN
register (Address 0x7A, Bits[23:16]) to 1 to configure it as
an output and make sure that the appropriate bit in the
GP_STBY3 register (Address 0x27, Bits[15:8]) is set to 0.
4. Power up the V-driver supplies.
5. Define the standby status of the AD9920A vertical outputs.
Write to the Standby2 and Standby3 polarity registers
(Address 0x25 and Address 0x26 = 0x1FF8000).
Write 0xFF8000 to Address 0x1C to configure the XV
and VSG signals. Write 0x100000 to Register 0xD1. When
using 3-phase HCLK mode, enable this mode before Step 6
by setting Address 0x24 = 0x10.
Note that VDR_EN must remain high to achieve proper vertical
outputs during normal operation.
Rev. B | Page 81 of 112
AD9920A
4
1
VH SUPPLY
+3V SUPPLIES
+1.8V SUPPLY
POWER
SUPPLIES
0V
VM SUPPLY
VL SUPPLY
CLI
(INPUT)
SERIAL
WRITES
2
3
5
6
7
8
9
10
11
500µs
100µs
SYNC/RST
12
VD
(INPUT)
HD
(INPUT)
LOW BY
DEFAULT
XV1 TO XV24
XSUBCK
(INTERNAL)
CLOCKS ACTIVE WHEN OUT_CONTROL
REGISTER UPDATED AT VD/HD EDGE
H2, H4, H6, H8
HIGH-Z BY
DEFAULT
H1, H3, H5, H7, RG
H-CLOCKS
VDR_EN
VDD
0V
V-DRIVER OUTPUTS ACTIVE
VH WHEN VDR_EN IS HIGH
V1 TO V16
(V-DRIVER OUTPUT)
VM
VL (SUBCK ONLY)
Figure 103. Recommended Power-Up Sequence and Synchronization, Slave Mode
Rev. B | Page 82 of 112
AD9920A
3. Write 0x03 to the AFE standby register (Address 0x00) to
place the AD9920A into Standby3 mode.
4. Power down the V-driver supplies.
POWER-DOWN SEQUENCE FOR MASTER AND
SLAVE MODES
1. Write 0 to the appropriate bit in the GPO_OUTPUT_EN
register (Address 0x7A) to set the appropriate VDR_EN
control signal low.
5. Power down the 3 V and 1.8 V supplies.
2. The next VD edge updates Address 0x7A, causing the
VDR_EN signal to go low and disabling the V-driver
outputs. If operating in slave mode, turn off VD and HD
after VDR_EN switches low.
4
VH SUPPLY
5
+3V SUPPLIES
+1.8V SUPPLIES
POWER
SUPPLIES
0
V
VM SUPPLY
VL SUPPLY
1
2
3
SERIAL
WRITES
VD
HD
VDR_EN
0V
VM
VL (SUBCK)
V1 TO V15
XSUBCK
H-CLOCKS
Figure 104. Recommended Power-Down Sequence, Master or Slave Mode
Rev. B | Page 83 of 112
AD9920A
•
•
There is an inhibit area for SHPLOC to meet the timing
requirement tCLISHP (see Figure 105, Figure 23, and Figure 24).
This restriction is necessary to guarantee a stable reset of
the H-counter in slave mode.
When operating the part in slave mode and using a crystal
oscillator to generate CLI, it can be very difficult to meet
the tHDCLI specification because there is no phase control
over the oscillator output. Special care must be taken to
meet the critical tHDCLI specification when operating in this
condition.
ADDITIONAL RESTRICTIONS IN SLAVE MODE
When operating in slave mode, note the following restrictions:
•
The HD falling edge should be located in the same CLI
clock cycle as the VD falling edge or later than the VD
falling edge. The HD falling edge should not be located
within one cycle prior to the VD falling edge.
•
If possible, all start-up serial writes should be performed
with VD and HD disabled. This prevents unknown
behavior caused by partial updating of registers before all
information is loaded. See the Power-Up Sequence for
Master Mode section.
VD
tVDHD
HD
tHDCLI
tCONV
CLI
tCLISHP
tCLIDLY
SHPLOC
INTERNAL
tSHPINH
SHDLOC
INTERNAL
HD
INTERNAL
H-COUNTER
RESET
35.5 CYCLES
H-COUNTER
(PIXEL COUNTER)
X
X X X X X X X X X X X X X X X X
X
X
X
X
X
X
X
X
X
X
0
X X X X X X X X X
1
2
X
NOTES:
1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, AND THEN LATCHED BY SHPLOC (INTERNAL SAMPLING EDGE).
2. INTERNAL H-COUNTER IS ALWAYS RESET 35.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE AT SHDLOC (INTERNAL SAMPLING EDGE).
3. DEPENDING ON THE VALUE OF SHPLOC, H-COUNTER RESET CAN OCCUR 36 OR 37 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHPLOC = 32, SHDLOC = 0 IS SHOWN. IN THIS CASE, THE H-COUNTER RESET OCCURS 36 CLI RISING EDGES AFTER HD FALLING EDGE.
5. HD FALLING EDGE SHOULD OCCUR COINCIDENT WITH THE VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER THE VD FALLING EDGE. HD FALLING
EDGE SHOULD NOT OCCUR WITHIN ONE CYCLE IMMEDIATELY BEFORE THE VD FALLING EDGE.
Figure 105. External VD/HD and Internal H-Counter Synchronization, Slave Mode
0
60
100 103
112
PIXEL NO.
HD
1
2
H1
3
4
CLPOB
MASTER MODE
SLAVE MODE
1
HBLKTOG1
HBLKTOG2
CLPOBTOG1
CLPOBTOG2
60
(60 – 36) = 24
(100 – 36) = 64
(103 – 36) = 67
(112 – 36) = 76
2
3
4
100
103
112
Figure 106. Example of Slave Mode Register Settings to Obtain Desired Toggle Positions
Rev. B | Page 84 of 112
AD9920A
Figure 107 shows this restriction for slave mode. The last 36 pixels
before the counters are reset cannot be used. In slave mode, the
counter reset is delayed with respect to VD/HD placement, so
the inhibited area is different than it is in master mode.
VERTICAL TOGGLE POSITION PLACEMENT NEAR
COUNTER RESET
An additional consideration during the reset of the internal
counters is the vertical toggle position placement. There is a
region of 36 pixels prior to the internal counter reset in which
no toggles can take place.
It is recommended that Pixel Location 0 not be used for any of
the toggle positions for the VSG and SUBCK pulses.
VD
HD
H-COUNTER
RESET
NO TOGGLE POSITIONSALLOWED IN THIS AREA
H-COUNTER
(PIXEL COUNTER)
X
X
X
X
X
X
N-35 N-34 N-33 N-32
N-13 N-12 N-11 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1
N
0
1
2
NOTE:
TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 36 PIXELS OF PIXEL 0 LOCATION.
Figure 107. Toggle Position Inhibited Area, Slave Mode
Rev. B | Page 85 of 112
AD9920A
When returning from Standby3 mode to normal operation, the
timing core must be reset at least 500 μs after the STANDBY
register is written to. This allows sufficient time for the crystal
circuit to settle.
STANDBY MODE OPERATION
The AD9920A contains three standby modes to optimize the
overall power dissipation in a particular application. Bits[1:0]
of Address 0x00 control the power-down state of the device.
The vertical outputs can also be programmed to hold a specific
value during the Standby3 mode by using Address 0x26. This
register is useful during power-up if different polarities are
required by the V-driver and CCD to prevent damage when VH
and VL areas are applied. The polarities for Standby1 mode and
Standby2 mode are also programmable, using Address 0x25, and
OUT_CONTROL = low uses the same polarities programmed
for Standby1 and Standby2 modes in Address 0x25. The GPO
polarities are programmable using Address 0x27.
Table 48. Power States Set by Standby Register
Standby Register,
Bits[1:0]
Description
00
01
10
11
Normal operation (full power)
Standby1 mode
Standby2 mode
Standby3 mode (lowest power)
Table 49 and Table 50 summarize the operation of each power-
down mode. The OUT_CONTROL register takes priority over
the Standby1 and Standby2 modes in determining the digital
output states, but Standby3 mode takes priority over OUT_
CONTROL. Standby3 has the lowest power consumption and
even shuts down the crystal oscillator circuit between CLI and
CLO. Therefore, if CLI and CLO are being used with a crystal
to generate the master clock, this circuit is powered down, and
there is no clock signal.
Note that the GPO outputs are high-Z by default at power-up
until Address 0x7A is used to select them as outputs.
CLI FREQUENCY CHANGE
If the input clock CLI is interrupted or changed to a different
frequency, the timing core must be reset for proper operation.
After the CLI clock has settled to the new frequency, or the
previous frequency is resumed, write 0 and then 1 to the
RST
TGCORE_
register (Address 0x14). This guarantees
that the timing core operates properly.
Table 49. Standby Mode Operation for HCLKMODE = 0x1, 0x2, or 0x4
(Standby Polarities for XV, XSUBCK, and GPO Outputs Are Programmable)
I/O Block
Standby3 (Default)1, 2
OUT_CONTROL = Low2
Standby23, 4
Off
Off
Off
Standby13, 4
Only REFT, REFB on
On
On
Running
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Running
AFE
Timing Core
CLO Oscillator
CLO
H1
H2
H3
H4
H5
H6
H7
H8
HL
RG
VD
Off
Off
Off
Low
No change
No change
No change
No change
Low
High
Low
High
Low
High
Low
High
Low
Low
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Low
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
VDHDPOL value
VDHDPOL value
Low
Low
VDHDPOL value
VDHDPOL value
Running
Low
Low
Low
HD
Low
Running
DCLK
D0 to D11
XV1 to XV24
XSUBCK
Low
Low
Low
Low
Running
Low
Low
Low
Low
Low
Low
GPO1 to GPO4,
Low
Low
Low
Low
GPO7, and GPO8
1 To exit Standby3 or Standby2 mode, write 00 to the standby register (Address 0x00, Bits[1:0]) and then reset the timing core after 500 μs to guarantee proper settling of the
oscillator and external crystal.
2 Standby3 mode takes priority over OUT_CONTROL for determining the output polarities.
3 These polarities assume OUT_CONTROL = high because OUT_CONTROL = low takes priority over Standby1 and Standby2.
4 Standby1 and Standby2 set H and RG drive strength to minimum value (4.3 mA).
Rev. B | Page 86 of 112
AD9920A
Table 50. Standby Mode Operation for HCLKMODE = 0x10
(Standby Polarities for XV, XSUBCK, and GPO Outputs Are Programmable)
I/O Block
Standby3 (Default)1, 2
OUT_CONTROL = Low2
Standby23, 4
Off
Off
Off
Standby13, 4
AFE
Timing Core
CLO Oscillator
CLO
H1
H2
H3
H4
H5
H6
H7
H8
HL
RG
VD
Off
Off
Off
Low
No change
No change
No change
No change
Low
Low
Low
Low
Low
Low
Low
Low
Low
Only REFT, REFB on
On
On
Low
Running
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Low
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
VDHDPOL value
VDHDPOL value
Low
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Running
Low
VDHDPOL value
VDHDPOL value
Running
Low
Low
Low
HD
Low
Running
DCLK
D0 to D11
XV1 to XV24
XSUBCK
Low
Low
Low
Low
Running
Low
Low
Low
Low
Low
Low
GPO1 to GPO4,
Low
Low
Low
Low
GPO7, and GPO8
1 To exit Standby3 or Standby2 mode, write 00 to the standby register (Address 0x00, Bits[1:0]) and then reset the timing core after 500 μs to guarantee proper settling of the
oscillator and external crystal.
2 Standby3 mode takes priority over OUT_CONTROL for determining the output polarities.
3 These polarities assume OUT_CONTROL = high because OUT_CONTROL = low takes priority over Standby1 and Standby2.
4 Standby1 and Standby2 set H and RG drive strength to minimum value (4.3 mA).
Rev. B | Page 87 of 112
AD9920A
CIRCUIT LAYOUT INFORMATION
The PCB layout is critical in achieving good image quality from
the AD9920A. All of the supply pins, particularly the AVDD,
TCVDD, RGVDD, and HVDD pins, must be decoupled to
ground with good quality, high frequency chip capacitors. The
decoupling capacitors should be located as close as possible to
the supply pins and should have a very low impedance path to a
continuous ground plane. If possible, there should be a 4.7 μF
or larger value bypass capacitor for each main supply—AVDD,
HVDD, and DRVDD—although this is not necessary for each
individual pin. In most applications, the supply for RGVDD and
HVDD is shared, which can be done as long as the individual
supply pins are separately bypassed with 0.1 μF capacitors. A
separate 3 V supply can also be used for DRVDD, but this supply
pin should still be decoupled to the same ground plane as the
rest of the chip. A separate ground for DRVSS is not recommended.
Similarly, a CCD with H1, H2, H3, and H4 inputs should have
the following:
•
•
•
•
H1 and H3 connected to CCD H1
H2 and H4 connected to CCD H2
H5 and H7 connected to CCD H3
H6 and H8 connected to CCD H4
TYPICAL 3 V SYSTEM
The AD9920A typical circuit connections for a 3 V system are
shown in Figure 110 and Figure 112. This application uses an
external 3.3 V supply, which is connected to the LDO input of
the AD9920A. The LDO provides 1.8 V to the AVDD, TCVDD,
and DVDD pins.
EXTERNAL CRYSTAL APPLICATION
The AD9920A contains an on-chip oscillator for driving an
external crystal. Figure 108 shows an example application using
a typical 27 MHz crystal. There is an internal feedback resistor
(typical value ≈ 7 MΩ). However, in the event that the internal
resistance is too high and prevents proper crystal operation, an
external resistor can be added in parallel. The value of this
external resistor is typically between 1 MΩ and 2 MΩ. For the
exact value of this resistor and other necessary external resistors
and capacitors, it is best to consult the crystal manufacturer.
The analog bypass pins (REFT and REFB) should be carefully
decoupled to ground as close as possible to their respective pins.
The analog input (CCDIN) capacitor should be located close to
the pin.
The H1 to H8, HL, and RG traces should be designed to have
low inductance to minimize distortion of the signals. The com-
plementary signals, H1/H3/H5/H7 and H2/H4/H6/H8, should
be routed as close together and as symmetrically as possible to
minimize mutual inductance. Heavier PCB traces are recom-
mended because of the large transient current demand on H1
to H8 by the CCD. If possible, physically locating the AD9920A
closer to the CCD reduces the inductance on these lines. The
routing path should be as direct as possible from the AD9920A
to the CCD.
Note that a 2× crystal is not recommended for use with the
CLO oscillator circuit. The crystal frequency should not exceed
40.5 MHz.
~7MΩ
AD9920A
Note that it is recommended that all H1 to H8 outputs on the
AD9920A be used together for maximum flexibility in drive
strength settings. A typical CCD with H1 and H2 inputs should
have only the AD9920A H1, H3, H5, and H7 outputs connected
together to drive CCD H1, and only the AD9920A H2, H4, H6,
and H8 outputs connected together to drive CCD H2.
~375Ω
J5
K5
CLI
CLO
USER DEFINED
XTAL
5pF TO 20pF
5pF TO 20pF
Figure 108. Crystal Application Using CLI/CLO
Rev. B | Page 88 of 112
AD9920A
CIRCUIT CONFIGURATIONS
3
6
SERIAL INTERFACE
GENERAL-PURPOSE OUTPUTS
NOTE: ONE GPO IS NEEDED TO DRIVE VDR_EN (PIN B11)
(FROM ASIC/DSP)
OPTIONAL CLOCK OSCILLATOR OUTPUT
(FOR CRYSTAL APPLICATION)
HORIZONTAL SYNC IN/OUT
VERTICAL SYNC IN/OUT
MASTER CLOCK INPUT (3V LOGIC)
0.1µF
EXTERNAL RESET IN
(TIE TO IOVDD IF RESET IS NOT USED)
DCLK OUTPUT
0.1µF
12
0.1µF
DATA OUTPUTS
ANALOG OUTPUT FROM CCD
RG TO CCD
HL TO CCD
H7, H8 TO CCD
H6
H5
H4
H3
H2
H1
H2
H1
D8
D7
D6
D5
D4
D3
H5, H6 TO CCD
A5
A6
B6
B7
A7
A8
C7
C6
B9
B11
F2
F1
H3, H4 TO CCD
H1, H2 TO CCD
D2
D1
DVSS
TCVSS
RGVSS
HVSS1
HVSS2
HVSS2
IOVSS
DRVSS/LDOVSS
VDVSS
D2
D1
A9
K4
K3
E2
G2
J2
(LSB) D0
VDR_EN
GPO OUTPUT
GPO OUTPUT
(OR GND, IF NOT USED)
SRSW
SRCTL
G11
B2
C10
C9
C2
J6
ANALOG CONTROL INPUT
(OR GND, IF NOT USED)
LEGEN
AD9920A
NOT DRAWN TO SCALE
CLIVDD
LDOIN
CCDGND
+3V CLI SUPPLY
L5
B1
C1
K7
LDOOUT
DRVDD
IOVDD
AVSS
AVSS
A2
+3V SUPPLY
J7
0.1µF
K8
H11
0.1µF
NC
NC
NC
A1
DVDD
TCVDD
AVDD
0.1µF
+1.8V SUPPLY
A10
K6
L6
A11
L1
L11
B8
0.1µF
0.1µF
NC
NC
NC
NC
B10
RGVDD
HVDD1
HVDD2
L3
E1
G1
J1
J10
+3V H, RG SUPPLY
0.1µF
0.1µF
4.7µF
6.3V
HVDD2
VH SUPPLY
VL SUPPLY
+3V SUPPLY
1.0µF
25V
0.1µF
25V
4.7µF
10V
0.1µF
10V
0.1uF
18
VERTICAL OUTPUT (TO CCD)
SUBCK OUTPUT (TO CCD)
XSUBCNT INPUT (FROM GPO OR TIE TO +3V)
Figure 109. Typical 1.8 V Circuit Configuration in Legacy Mode (18-Channel Mode)
Rev. B | Page 89 of 112
AD9920A
3
6
SERIAL INTERFACE
(FROM ASIC/DSP)
GENERAL-PURPOSE OUTPUTS
NOTE: ONE GPO IS NEEDED TO DRIVE VDR_EN (PIN B11)
OPTIONAL CLOCK OSCILLATOR OUTPUT
(FOR CRYSTAL APPLICATION)
HORIZONTAL SYNC IN/OUT
VERTICAL SYNC IN/OUT
MASTER CLOCK INPUT (3V LOGIC)
EXTERNAL RESET IN
(TIE TO IOVDD IF RESET IS NOT USED)
DCLK OUTPUT
0.1µF
0.1µF
12
DATA OUTPUTS
0.1µF
ANALOG OUTPUT FROM CCD
RG TO CCD
HL TO CCD
H7, H8 TO CCD
H6
H5
H4
H3
H2
H1
H2
H1
D8
D7
D6
D5
D4
D3
H5, H6 TO CCD
H3, H4 TO CCD
H1, H2 TO CCD
A5
A6
B6
B7
A7
A8
C7
C6
B9
B11
F2
F1
D2
D1
DVSS
TCVSS
RGVSS
HVSS1
HVSS2
HVSS2
IOVSS
DRVSS/LDOVSS
VDVSS
D2
D1
A9
K4
K3
E2
G2
J2
(LSB) D0
VDR_EN
GPO OUTPUT
GPO OUTPUT
(OR GND, IF NOT USED)
SRSW
SRCTL
G11
B2
C10
C9
C2
J6
ANALOG CONTROL INPUT
(OR GND, IF NOT USED)
LEGEN
AD9920A
NOT DRAWN TO SCALE
CLIVDD
LDOIN
CCDGND
+3V CLI SUPPLY
+3V LDO INPUT
L5
B1
C1
K7
LDOOUT
+1.8V LDO OUT TO
AVDD, TCVDD, DVDD
0.1µF
0.1µF
DRVDD
IOVDD
AVSS
AVSS
A2
J7
+3V SUPPLY
0.1µF
K8
H11
0.1µF
NC
NC
NC
A1
DVDD
TCVDD
AVDD
+1.8V LDO OUT
A10
K6
L6
A11
L1
L11
B8
0.1µF
0.1µF
NC
NC
0.1µF
NC
NC
B10
RGVDD
HVDD1
HVDD2
HVDD2
L3
E1
G1
J1
J10
+3V H, RG SUPPLY
0.1µF
0.1µF
4.7µF
6.3V
VH SUPPLY
VL SUPPLY
+3V SUPPLY
0.1µF
25V
1.0µF
25V
0.1µF
10V
4.7µF
10V
0.1uF
18
VERTICAL OUTPUT (TO CCD)
SUBCK OUTPUT (TO CCD)
XSUBCNT INPUT (FROM GPO OR TIE TO +3V)
Figure 110. Typical 3 V Circuit Configuration in Legacy Mode (18-Channel Mode)
Rev. B | Page 90 of 112
AD9920A
3
6
SERIAL INTERFACE
(FROM ASIC/DSP)
GENERAL-PURPOSE OUTPUTS
NOTE: ONE GPO IS NEEDED TO DRIVE VDR_EN (PIN B11)
OPTIONAL CLOCK OSCILLATOR OUTPUT
(FOR CRYSTAL APPLICATION)
HORIZONTAL SYNC IN/OUT
VERTICAL SYNC IN/OUT
MASTER CLOCK INPUT (3V LOGIC)
0.1µF
EXTERNAL RESET IN
(TIE TO IOVDD IF RESET IS NOT USED)
DCLK OUTPUT
0.1µF
12
0.1µF
DATA OUTPUTS
ANALOG OUTPUT FROM CCD
RG TO CCD
HL TO CCD
H7, H8 TO CCD
H6
H5
H4
H3
H2
H1
H2
H1
D8
D7
D6
D5
D4
D3
H5, H6 TO CCD
A5
A6
B6
B7
A7
A8
C7
C6
B9
B11
F2
F1
H3, H4 TO CCD
H1, H2 TO CCD
D2
D1
DVSS
TCVSS
RGVSS
HVSS1
HVSS2
HVSS2
IOVSS
DRVSS/LDOVSS
VDVSS
D2
D1
A9
K4
K3
E2
G2
J2
(LSB) D0
VDR_EN
GPO OUTPUT
GPO OUTPUT
(OR GND, IF NOT USED)
SRSW
SRCTL
G11
B2
C10
C9
C2
J6
ANALOG CONTROL INPUT
(OR GND, IF NOT USED)
LEGEN
+3V
AD9920A
NOT DRAWN TO SCALE
CLIVDD
LDOIN
CCDGND
+3V CLI SUPPLY
L5
B1
C1
K7
LDOOUT
DRVDD
IOVDD
AVSS
AVSS
A2
+3V SUPPLY
J7
0.1µF
K8
H11
0.1µF
NC
NC
NC
A1
DVDD
TCVDD
AVDD
0.1µF
+1.8V SUPPLY
A10
K6
L6
A11
L1
L11
B8
0.1µF
0.1µF
NC
NC
NC
NC
B10
RGVDD
HVDD1
HVDD2
HVDD2
L3
E1
G1
J1
J10
+3V H, RG SUPPLY
0.1µF
0.1µF
4.7µF
6.3V
VH SUPPLY
VL SUPPLY
+3V SUPPLY
0.1µF
25V
1.0µF
25V
0.1µF
10V
4.7µF
10V
0.1uF
19
VERTICAL OUTPUT (TO CCD)
SUBCK OUTPUT (TO CCD)
XSUBCNT INPUT (FROM GPO OR TIE TO +3V)
Figure 111. Typical 1.8 V Circuit Configuration in 19-Channel Mode
Rev. B | Page 91 of 112
AD9920A
3
6
SERIAL INTERFACE
(FROM ASIC/DSP)
GENERAL-PURPOSE OUTPUTS
NOTE: ONE GPO IS NEEDED TO DRIVE VDR_EN (PIN B11)
OPTIONAL CLOCK OSCILLATOR OUTPUT
(FOR CRYSTAL APPLICATION)
HORIZONTAL SYNC IN/OUT
VERTICAL SYNC IN/OUT
MASTER CLOCK INPUT (3V LOGIC)
EXTERNAL RESET IN
(TIE TO IOVDD IF RESET IS NOT USED)
DCLK OUTPUT
0.1µF
0.1µF
12
0.1µF
DATA OUTPUTS
ANALOG OUTPUT FROM CCD
RG TO CCD
HL TO CCD
H7, H8 TO CCD
H6
H5
H4
H3
H2
H1
H2
H1
D8
D7
D6
D5
D4
D3
H5, H6 TO CCD
H3, H4 TO CCD
H1, H2 TO CCD
A5
A6
B6
B7
A7
A8
C7
C6
B9
B11
F2
F1
D2
D1
DVSS
TCVSS
RGVSS
HVSS1
HVSS2
HVSS2
IOVSS
DRVSS/LDOVSS
VDVSS
D2
D1
A9
K4
K3
E2
G2
J2
(LSB) D0
VDR_EN
GPO OUTPUT
GPO OUTPUT
(OR GND, IF NOT USED)
SRSW
SRCTL
G11
B2
C10
C9
C2
J6
ANALOG CONTROL INPUT
(OR GND, IF NOT USED)
LEGEN
+3V
AD9920A
NOT DRAWN TO SCALE
CLIVDD
LDOIN
CCDGND
+3V CLI SUPPLY
+3V LDO INPUT
L5
B1
C1
K7
LDOOUT
+1.8V LDO OUT TO
AVDD, TCVDD, DVDD
0.1µF
0.1µF
0.1µF
DRVDD
IOVDD
AVSS
AVSS
A2
J7
+3V SUPPLY
0.1µF
K8
H11
0.1µF
NC
NC
NC
A1
DVDD
TCVDD
AVDD
+1.8V LDO OUT
A10
K6
L6
A11
L1
L11
B8
0.1µF
NC
NC
0.1µF
NC
NC
B10
RGVDD
HVDD1
HVDD2
HVDD2
L3
E1
G1
J1
J10
+3V H, RG SUPPLY
4.7µF
6.3V
0.1µF 0.1µF
VH SUPPLY
VL SUPPLY
+3V SUPPLY
0.1µF
1.0µF
25V
25V
0.1µF
10V
4.7µF
10V
0.1uF
19
VERTICAL OUTPUT (TO CCD)
SUBCK OUTPUT (TO CCD)
XSUBCNT INPUT (FROM GPO OR TIE TO +3V)
Figure 112. Typical 3 V Circuit Configuration in 19-Channel Mode
Rev. B | Page 92 of 112
AD9920A
SERIAL INTERFACE
Figure 114 shows a more efficient way to write to the registers,
using the AD9920A address auto-increment capability. Using
this method, the lowest desired address is written first, followed
by multiple 28-bit data-words. Each new 28-bit data-word is
automatically written to the next highest register address. By
eliminating the need to write each 12-bit address, faster register
loading is achieved. Continuous write operations can be used
starting with any register location.
SERIAL INTERFACE TIMING
The internal registers of the AD9920A are accessed through a
3-wire serial interface. Each register consists of a 12-bit address
and a 28-bit data-word. Both the 12-bit address and 28-bit data-
word are written starting with the LSB. To write to each register,
a 40-bit operation is required, as shown in Figure 113. Although
many registers are fewer than 28 bits wide, all 28 bits must be
written for each register. For example, if the register is only 20 bits
wide, the upper eight bits are don’t care bits and must be filled
with 0s during the serial write operation. If fewer than 28 data
bits are written, the register is not updated with new data.
12-BIT ADDRESS
28-BIT DATA
SDATA
SCK
A0
A1
A2
A3
A4
A5
tDS
A6
A8
A9 A10 A11 D0
D1
D2
D3
D25 D26 D27
A7
tDH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
38
39
40
tLS
tLH
SL
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 40 BITS MUST BE WRITTEN: 12 BITS FOR ADDRESS AND 28 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS <28 BITS, 0s MUST BE USED TO COMPLETE THE 28-BIT DATA LENGTH.
4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE
PARTICULAR REGISTER WRITTEN TO. SEE THE UPDATING NEW REGISTER VALUES SECTION FOR MORE INFORMATION.
Figure 113. Serial Write Operation
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
SDATA
A0
A1
A2
A10 A11 D0
D1
D26 D27 D0
D1
D26 D27 D0
A3
D1
D2
SCK
SL
70
71
1
2
3
4
11
12
13
14
39
40
41
42
67
68
69
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 28-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 28-BIT DATA-WORD (ALL 28 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
Figure 114. Continuous Serial Write Operation
Rev. B | Page 93 of 112
AD9920A
Each V-sequence occupies 40 register addresses, and each field
occupies 16 register addresses.
LAYOUT OF INTERNAL REGISTERS
The AD9920A address space is divided into two register areas, as
illustrated in Figure 115. In the first address space, Address 0x00 to
Address 0xFF contain the registers for the AFE, miscellaneous,
VD/HD, I/O and CP, timing core, shutter and GPO, and update
control functions. The second address space, beginning at
Address 0x400, consists of the V-pattern groups, V-sequences,
and field registers. This set of registers is configurable; the user
can decide how many V-pattern groups, V-sequences, and fields
are used in a particular design. Therefore, the addresses for
these registers vary, depending on the number of V-patterns
and V-sequences chosen.
The starting address for the V-sequences is equal to 0x400 plus
the number of V-pattern groups multiplied by 48. The starting
address for the fields is equal to the starting address of the
V-sequences plus the number of V-sequences multiplied by 40.
The V-pattern, V-sequence, and field registers must always
occupy a continuous block of addresses.
Figure 116 shows an example in which three V-pattern groups,
four V-sequences, and two fields are used. The starting address
for the V-pattern groups is always 0x400. Because VPATNUM = 3,
the V-pattern groups occupy 144 address locations. The start of
the V-sequence registers is 0x490 (that is, 0x400 + 144). With
SEQNUM = 4, the V-sequences occupy 160 address locations.
Therefore, the field registers begin at 0x530 (that is, 0x490 + 160).
Address 0x28 specifies the total number of V-pattern groups
and V-sequences used. The starting address for the V-pattern
groups is always 0x400. The starting address for the V-sequences
is based on the number of V-pattern groups used, with each
V-pattern group occupying 48 register addresses. The starting
address for the field registers depends on both the number of
V-pattern groups and the number of V-sequences.
The AD9920A address space contains many unused addresses.
Undefined addresses between Address 0x00 and Address 0xFF
should not be written to; otherwise, the AD9920A may operate
incorrectly. Continuous register writes should be performed
carefully so that undefined registers are not written to.
FIXED REGISTER AREA
ADDR 0x00
CONFIGURABLE REGISTER AREA
VPAT START 0x400
AFE REGISTERS
MISCELLANEOUS REGISTERS
V-PATTERN GROUPS
VD/HD REGISTERS
I/O, STBY POL REGISTERS
VSEQ START
FIELD START
MAX 0xFFF
MEMORY, MODE REGISTERS
TIMING CORE REGISTERS
V-SEQUENCES
TEST REGISTERS
SHUTTER AND GPO REGISTERS
UPDATE CONTROL REGISTERS
EXTRA REGISTERS
FIELDS
INVALID DO NOT ACCESS
ADDR 0xFF
Figure 115. Layout of AD9920A Registers
ADDR 0x400
3 V-PATTERN GROUPS
(48 × 3 = 144 REGISTERS)
ADDR 0x490
ADDR 0x530
4 V-SEQUENCES
(40 × 4 = 160 REGISTERS)
2 FIELDS
(16 × 2 = 32 REGISTERS)
ADDR 0x550
MAX 0xFFF
UNUSED MEMORY
Figure 116. Example Register Configuration
Rev. B | Page 94 of 112
AD9920A
delays the VD-updated register updates to any HD line in the
field. Note that the field registers are not affected by the update
register.
UPDATING NEW REGISTER VALUES
The AD9920A internal registers are updated at different times,
depending on the particular register. Table 51 summarizes the
four register update types: SCK, VD, SG line, and SCP. Tables in
the Complete Register Listing section contain an update type
column that identifies when each register is updated.
SG Line-Updated Registers
A few of the shutter registers are updated at the HD falling edge
at the start of the SG active line. These registers control the
SUBCK signal so that the SUBCK output is not updated until
the SG line occurs.
Table 51. Register Update Locations
Update Type Description
SCP-Updated Registers
SCK
When the 28th data bit (D27) is clocked in, the
register is immediately updated.
At the next SCP where they are used, the V-pattern group and
V-sequence registers are updated. For example, in Figure 117
this field has selected Region 1 to use VSEQ3 for the vertical
outputs. This means that a write to any of the VSEQ3 registers
or to any of the V-pattern group registers that are referenced by
VSEQ3, updates at SCP1. If multiple writes are done to the same
register, the last one done before SCP1 is the one that is updated.
Likewise, register writes to any VSEQ5 registers are updated at
SCP2, and register writes to any VSEQ8 registers are updated
at SCP3.
VD
Register is updated at the next VD falling edge.
VD-updated registers can be delayed further by
using the update register at Address 0x17. Field
registers are not affected by the update register.
Register is updated at the HD falling edge at the
start of the SG active line.
SG Line
SCP
Register is updated at the next SCP when the
register is used.
SCK-Updated Registers
As soon as the 28th data bit (D27) is clocked in, some registers
are immediately updated. These registers are used for functions
that do not require gating with the next VD boundary, such as
power-up and reset functions.
Caution
It is recommended that the registers in the configurable address
area not be written within 36 pixels of any HD falling edge where
a sequence change position (SCP) occurs. See Figure 107 for an
example of what this inhibit area looks like in master and slave
modes. This restriction applies to the V-pattern, V-sequence,
and field registers. As shown in Figure 117, writing to these
registers before the VD falling edge typically avoids loading
these registers during SCP locations.
VD-Updated Registers
More registers are updated at the next VD falling edge. By
updating these values at the next VD edge, the current field is
not corrupted, and the new register values are applied to the
next field. The VD update can be further delayed past the VD
falling edge by using the update register (Address 0x17). This
SCK
VD
SG
UPDATED
SCP
UPDATED
UPDATED UPDATED
SERIAL
WRITE
VD
HD
SGLINE
VSG
USE VSEQ2
USE VSEQ3
REGION 1
USE VSEQ5
REGION 2
USE VSEQ8
REGION 3
XV1 TO XV24
REGION 0
SCP0
SCP0
SCP1
SCP2
SCP3
Figure 117. Register Update Locations (See Table 51 for Definitions)
Rev. B | Page 95 of 112
AD9920A
COMPLETE REGISTER LISTING
When an address contains fewer than 28 data bits, all remaining bits must be written as 0s.
Table 52. AFE Registers
Default
Update
Type
Data
Bits
Default
Value
Address
Name
Description
0x00
[1:0]
0x03
SCK
STANDBY
Standby modes.
0 = normal operation (full power).
1 = Standby1 mode.
2 = Standby2 mode.
3 = Standby3 mode (lowest power).
0 = disable OB clamp.
1 = enable OB clamp.
[2]
[3]
[4]
[5]
[6]
[0]
[1]
0x01
CLPENABLE
CLPSPEED
FASTUPDATE
PBLK_LVL
0
0
0
0
0
0
0 = select normal OB clamp settling.
1 = select fast OB clamp settling.
0 = ignore CDS gain.
1 = very fast clamping when CDS gain is updated.
0 = blank data outputs to 0 during PBLK.
1 = blank data outputs to programmed clamp level during PBLK.
0 = enable input dc restore circuit during PBLK.
1 = disable input dc restore circuit during PBLK.
DCBYP
0x01
SCK
DOUTDISABLE
DOUTLATCH
0 = data outputs are driven.
1 = data outputs are three-stated.
0 = latch data outputs using DOUTPHASE register setting.
1 = output latch is transparent.
1 = enable gray coding of digital data output.
Set to 0.
[2]
[3]
0
0
GRAYEN
Test
0x02
0x03
0x04
[0]
0
VD
VD
VD
Test
Do not access, or set to 0.
[23:0]
[2:0]
0xFFFFFF
0
Test
Do not access, or set to 0xFFFFFF.
CDSGAIN
CDS gain setting.
0 = −3 dB.
4 = 0 dB.
6 = +3 dB.
7 = +6 dB.
All other values are invalid.
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
[9:0]
0x0F
VD
VD
VD
VD
VD
VD
SCK
SCK
VD
VGAGAIN
CLAMPLEVEL
Test
VGA gain. 6 dB to 42 dB (0.035 dB per step).
Optical black clamp level. 0 LSB to 255 LSB (0.25 LSB per step).
Do not access, or set to 0.
[9:0]
0x1EC
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[0]
0
0
0
0
0
0
0
Test
Do not access, or set to 0.
Test
Do not access, or set to 0.
Test
Do not access, or set to 0.
UNUSED
Test
Do not access, or set to 0.
Do not access, or set to 0.
CLIDIVIDE
0 = do not divide CLI frequency.
1 = divide CLI frequency by 2.
Do not access, or set to 0.
[7:1]
[7:0]
[8]
0
0
0
0
Test
0x0E
0x0F
SCK
VD
Test
VDHD_IE
Test
Set to 0.
VD/HD input enable. Set to 1 to enable VD/HD inputs for slave mode.
Set to 0.
[27:0]
Rev. B | Page 96 of 112
AD9920A
Table 53. Miscellaneous Registers
Default
Data
Bits
Default
Value
Update
Type
Address
Name
Description
0x10
[0]
[0]
[0]
0
SCK
VD
SW_RST
Software reset. Bit self-clears to 0 when a reset occurs.
1 = reset Address 0x00 to Address 0xFF back to default values.
0x11
0x12
0
OUT_CONTROL
RST_SYNC_EN
0 = make all outputs dc inactive.
1 = enable outputs at next VD edge.
0x01
SCK
0 = configure SYNC/RST as SYNC pin.
1 = configure SYNC/RST as RST pin (default configuration is RST).
Test mode only. Must be set to 0.
[4:1]
[0]
0
Test
0x13
0x01
SCK
SYNCENABLE
SYNCPOL
SYNCSUSPEND
1 = external synchronization enable. Configure SYNC/RST pin as an input.
[1]
[2]
0
0
SYNC active polarity.
Suspend clocks during SYNC active pulse.
0 = don’t suspend.
1 = suspend.
[3]
[4]
[5]
[6]
0
0
0x01
0x01
0
0
0
0
0
0
0
ENH_SYNC_EN
SYNC_MASK_HD
SYNC_MASK_VD
SYNC_MASK_V
Test
1 = enable enhanced sync/shutter operations.
1 = mask HD during SYNCSUSPEND.
1 = mask VD during SYNCSUSPEND.
1 = mask XV outputs during SYNCSUSPEND.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
1 = enable SYNC to use only one edge to reset.
[7]
[12:8]
[13]
[14]
[15]
[16]
[17]
Test
Test
SYNC_EDGE_EN
SYNC_RST_SHUTEN 1 = enable reset of the shutter control after SYNC operation occurs.
GPO_RST_SYNC
SYNC_CNT_INC
1 = reset shutter and GPO control at SYNC operation.
1 = increment field counter by 1 when SYNC occurs.
0 = reset to 0.
[19:18]
[23:20]
[24]
0
0
0
0
0
UNUSED
Test
SWSYNC
REG_RST_SHUT
TGCORE_RST
Set unused bits to 0.
Test mode only. Must be set to 0.
1 = initiate software SYNC event (self-clears to 0 after SYNC).
1 = force shutter control to reset until REG_RST_SHUT = 0.
[25]
0x14
0x15
[0]
SCK
SCK
Timing core reset bar.
0 = reset TG core.
1 = resume operation.
[0]
0
OSC_RST
CLO oscillator reset bar.
0 = oscillator in power-down state.
1 = resume oscillator operation.
0x16
0x17
[27:0]
[12:0]
0x01
0
SCK
SCK
Test
Test mode only. Must be set to 1.
Update
Serial update line. Sets the line (HD) within the field to update the
VD-updated registers.
[13]
0
PREVENTUP
Prevents the update of the VD-updated registers.
0 = normal update.
1 = prevent update of VD-updated registers.
0x18
0x19
0x1A
0x1B
0x1C
0x1D
[27:0]
[27:0]
[27:0]
[27:0]
[23:0]
[23:0]
[24]
0
SCK
SCK
SCK
SCK
SCK
SCK
Test
Test mode only. Set to 0.
0
Test
Test mode only. Set to 0.
0
Test
Test mode only. Set to 0.
0x0A
Test
Test mode only. Set to 0x0A.
1 = each bit selects XV pulses for use as VSG pulses.
0
0
0
VSGSELECT
VSGMASK_CTL
VSGMASK_CTL_EN
VSG masking. Overrides settings in field registers when enabled.
0 = disable VSGMASK_CTL bits. VSG masking is controlled by field registers.
1 = enable VSGMASK_CTL bits to control VSG masking.
0x1E
0x1F
[27]
[0]
[1]
0
SCK
SCK
UNUSED
Do not access, or set to 0.
0x01
0x01
HCNT14_EN
PBLK_MASK_EN
1 = enable 14-bit H-counter.
1 = disable clamp operation if PBLK is active at the same time as CLPOB.
Rev. B | Page 97 of 112
AD9920A
Table 54. VD/HD Registers
Default
Update Type
Address
0x20
Data Bits
[0]
Default Value
Name
Description
0
0
0
0
SCK
VD
MASTER
VDHDPOL
HDRISE
VDRISE
VD/HD master or slave mode. 0 = slave mode, 1 = master mode.
VD/HD active polarity. 0 = low, 1 = high.
Rising edge location for HD. Minimum value is 36 pixels.
Rising edge location for VD.
0x21
[0]
0x22
[12:0]
[25:13]
VD
Table 55. I/O Registers
Default
Default Update
Data
Bits
Address
Value
Type
Name
Description
0x23
[0]
[1]
[2]
[3]
0
SCK
OSC_NVR
Oscillator normal voltage range. Set to match CLIVDD supply voltage.
0 = 1.8 V.
1 = 3.3 V.
XV output normal voltage range. Set to match VDVDD supply voltage.
0 = 1.8 V.
1 = 3.3 V.
I/O normal voltage range. Set to match IOVDD supply voltage.
0 = 1.8 V.
1 = 3.3 V.
0
0
0
XV_NVR
IO_NVR
DATA_NVR
Data pin normal voltage range. Set to match DRVDD supply voltage.
0 = 1.8 V I/O.
1 = 3.3 V I/O.
[4]
[5]
[6]
0
0
0
Test
Test
Test
Test use only. Set to 0.
Test use only. Set to 0.
Test use only. Set to 0.
0x24
0x25
[4:0]
0x01
SCK
SCK
HCLKMODE
Selects HCLK output configuration. Should be written to desired value.
Note that all other settings are invalid.
0x01 = Mode 1.
0x02 = Mode 2.
0x04 = Mode 3.
0x10 = 3-phase HCLK mode.
Test use only. Set to 0.
[5]
0
0
Test
[24:0]
VT_STBY12
Bits[23:0]: Standby1 and Standby2 polarity for XV[23:0].
Bit 24: Standby1 and Standby2 polarity for XSUBCK.
Settings also apply when OUT_CONTROL = low.
0x26
0x27
[24:0]
[7:0]
0
0
0
SCK
SCK
VT_STBY3
Bits[23:0]: Standby3 polarity for XV[23:0].
Bit 24: Standby3 polarity for XSUBCK.
GP_STDBY12
GP_STDBY3
Standby1 and Standby2 polarity for GPO outputs.
Settings also apply when OUT_CONTROL = low.
Standby3 polarity for GPO outputs.
[15:8]
Table 56. Memory Configuration and Mode Registers
Address
Data Bits
Default Value
Update Type
Name
Description
0x28
[4:0]
[9:5]
0
0
0
0
0
0
0
0
0
SCK
VPATNUM
SEQNUM
UNUSED
Mode
Total number of V-pattern groups.
Total number of V-sequences.
0x29
0x2A
0x2B
[27]
SCK
SCK
SCK
Do not access, or set to 0.
[2:0]
Total number of fields in the mode register.
Selected first field in the mode register.
Selected second field in the mode register.
Selected third field in the mode register.
Selected fourth field in the mode register.
Selected fifth field in the mode register.
[4:0]
[9:5]
[14:10]
[19:15]
[24:20]
FIELD1
FIELD2
FIELD3
FIELD4
FIELD5
Rev. B | Page 98 of 112
AD9920A
Address
Data Bits
[4:0]
[9:5]
Default Value
Update Type
Name
Description
0x2C
0
0
0
0
0
SCK
FIELD6
FIELD7
Selected sixth field in the mode register.
Selected seventh field in the mode register.
Do not access, or set to 0.
0x2D
0x2E
0x2F
[27]
SCK
SCK
SCK
UNUSED
UNUSED
UNUSED
[27]
Do not access, or set to 0.
[27]
Do not access, or set to 0.
Table 57. Timing Core Registers
Default
Value
Update
Type
Address
Data Bits
Name
Description
0x30
[5:0]
0
SCK
H1POSLOC
H1 rising edge location in HCLK Mode 1, Mode 2, and Mode 3.
Phase 3 (H7/H8) rising edge location in 3-phase mode.
H1 falling edge location in HCLK Mode 1, Mode 2, and Mode 3.
Phase 3 (H7/H8) falling edge location in 3-phase mode.
Test use only. Set to 1.
[13:8]
0x20
H1NEGLOC
[16]
0x01
0
Test
0x31
[5:0]
SCK
H2POSLOC
H2 rising edge location in HCLK Mode 2.
H5 rising edge location in HCLK Mode 3.
Phase 2 (H5/H6) rising edge location in 3-phase mode.
H2 falling edge location in HCLK Mode 2.
H5 falling edge location in HCLK Mode 3.
Phase 2 (H5/H6) falling edge location in 3-phase mode.
Test use only. Set to 1.
[13:8]
0x20
H2NEGLOC
[16]
0x01
0
0x20
0x01
0
0x20
0x01
0
0x10
0x01
0
Test
0x32
0x33
0x34
0x35
[5:0]
[13:8]
[16]
SCK
SCK
SCK
SCK
HLPOSLOC
HLNEGLOC
Test
HL rising edge location.
HL falling edge location.
Test use only. Set to 1.
[5:0]
[13:8]
[16]
H3P1POSLOC
H3P1NEGLOC
Test
Phase 1 (H1/H2) rising edge location in 3-phase mode.
Phase 1 (H1/H2) falling edge location in 3-phase mode.
Test use only. Set to 1.
[5:0]
[13:8]
[16]
RGPOSLOC
RGNEGLOC
Test
RG rising edge location.
RG falling edge location.
Test use only. Set to 1.
[0]
H1HBLKRETIME
Retime H1 HBLK to internal clock. Enabling retime adds one half cycle
delay to HBLK position.
0 = no retime.
1 = retime.
[1]
[2]
[3]
[7:4]
[8]
0
0
0
0
0
0
0
0
0
0
0
H2HBLKRETIME
HLHBLKRETIME
H3PHBLKRETIME Retime H3 HBLK to internal clock.
HCLK_WIDTH
Test
HLHBLK
Retime H2 HBLK to internal clock.
Retime HL HBLK to internal clock.
Enables wide H-clocks during HBLK interval. Set to 0 to disable.
Test use only. Set to 0.
1 = enable HBLK for HL.
Test use only. Set to 0.
Adds one additional retime operation to H1 HBLK signal.
Adds one additional retime operation to H2 HBLK signal.
Adds one additional retime operation to HL HBLK signal.
Adds one additional retime operation to H3P HBLK signal
(3-phase mode).
[9]
[19:10]
[20]
[21]
[22]
[23]
Test
H1FINERETIME
H2FINERETIME
HLFINERETIME
H3PFINERETIME
Rev. B | Page 99 of 112
AD9920A
Default
Value
Update
Type
Address
Data Bits
Name
Description
0x36
[2:0]
0x01
SCK
H1DRV
H1 drive strength.
0 = off.
1 = 4.3 mA.
2 = 8.6 mA.
3 = 12.9 mA.
4 = 17.3 mA.
5 = 21.6 mA.
6 = 25.9 mA.
7 = 30.2 mA.
[6:4]
0x1
0x1
0x1
0x1
H2DRV
H3DRV
H4DRV
HLDRV
H2 drive strength (same range as H1DRV).
H3 drive strength (same range as H1DRV).
H4 drive strength (same range as H1DRV).
HL drive strength.
0 = off.
[10:8]
[14:12]
[18:16]
1 = 4.3 mA.
2 = 8.6 mA.
3 = 12.9 mA.
4 = 4.3 mA.
5 = 8.6 mA.
6 = 12.9 mA.
7 = 17.3 mA.
[22:20]
[2:0]
[6:4]
0x1
0x1
0x1
0x1
0x1
0x1
0x1
0
RGDRV
RG drive strength (same range as HLDRV).
0x37
SCK
H5DRV
H6DRV
H7DRV
H8DRV
Test
Test
H5 drive strength (same range as H1DRV).
H6 drive strength (same range as H1DRV).
H7 drive strength (same range as H1DRV).
H8 drive strength (same range as H1DRV).
Test use only. Set to 1.
[10:8]
[14:12]
[18:16]
[22:20]
[5:0]
[13:8]
[21:16]
[5:0]
Test use only. Set to 1.
0x38
0x39
SCK
SCK
SHDLOC
SHPLOC
SHPWIDTH
DOUTPHASEP
DOUTPHASEN
SHD sampling edge location.
SHP sampling edge location.
SHP width (controls input dc restore switch active time).
DOUT phase control, positive edge. Specifies location of DOUT.
DOUT phase control, negative edge. Always set to DOUTPHASEP +
32 edges to maintain 50% duty cycle of internal DOUTPHASE clocking.
0x20
0x10
0
[13:8]
0x20
[16]
0
DCLKMODE
DCLK mode.
0 = DCLK tracks DOUT.
1 = DCLK phase is fixed.
Test use only. Set to 0.
Invert DCLK output.
0 = no inversion.
[18:17]
[19]
0
0
Test
DCLKINV
1 = inversion of DCLK.
[22:20]
[27]
0
0
0
0
0
0
0
Test
Test use only. Set to 0.
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
SCK
SCK
SCK
SCK
SCK
SCK
Test
Do not access, or set to 0.
Do not access, or set to 0.
Do not access, or set to 0.
Do not access, or set to 0.
Do not access, or set to 0.
Do not access, or set to 0.
[27]
UNUSED
Test
[27]
[27]
UNUSED
Test
[27]
[27]
UNUSED
Table 58. Test Registers—Do Not Access
Address
Data Bits
Default Value
Update Type
Name
Description
0x40 to 0x6F
Test registers. Do not access.
Rev. B | Page 100 of 112
AD9920A
Table 59. Shutter and GPO Registers
Data
Address Bits
Default
Value
Update
Type
Name
Description
0x70
[2:0]
[5:3]
0
0
VD
PRIMARY_ACTION
SECOND_ACTION
Select action for primary and secondary counters.
0 = idle (do nothing): autoreset on VD.
1 = activate counter (primary: automatic exposure/read).
2 = RapidShot: wrap/repeat counter.
3 = ShotTimer: delay start of count.
4 = ShotTimer with RapidShot.
5 = SLR exposure (manual).
6 = SLR read (manual).
7 = force to idle.
[13:6]
0
MANUAL_TRIG
1: manual trigger for GP signals when Protocol 1 is selected.
Bit 6: GP1 manual trigger.
Bit 13: GP8 manual trigger.
0x71
0x72
[12:0]
0
0
0
0
VD
VD
PRIMARY_MAX
SECOND_MAX
VDHD_MASK
Primary counter maximum value.
Secondary counter maximum value.
Mask VD/HD during counter operation.
[24:13]
[27:25]
[12:0]
PRIMARY_DELAY
Number of fields to delay before the next primary count (exposure)
starts. For ShotTimer with RapidShot, the delay value is used between
each repetition.
[13]
0
0
PRIMARY_SKIP
For ShotTimer with RapidShot, use the primary delay value only before
the first count (exposure).
Number of fields to delay before the next secondary count (exposure)
starts. For ShotTimer with RapidShot, the delay value is used between
each repetition.
[26:14]
SECOND_DELAY
[27]
0
SECOND_SKIP
For ShotTimer with RapidShot, use the secondary delay value only
before the first count (exposure).
0x73
[2:0]
[5:3]
[8:6]
0
0
0
VD
GP1_PROTOCOL
GP2_PROTOCOL
GP3_PROTOCOL
Selects protocol for each general-purpose signal.
0 = idle.
1 = no counter association. Use MANUAL_TRIG bits to enable each GP
signal.
[11:9]
0
0
0
0
0
GP4_PROTOCOL
GP5_PROTOCOL
GP6_PROTOCOL
GP7_PROTOCOL
GP8_PROTOCOL
2 = test use only.
3 = test use only.
4 = link to mode counter.
5 = link to primary counter.
6 = link to secondary counter.
7 = keep on.
[14:12]
[17:15]
[20:18]
[23:21]
0x74
0x75
[12:0]
[25:13]
[26]
0
0
0x01
VD
VD/SG
VD/SG
SGMASK_NUM
SUBCKMASK_NUM
Exposure duration (number of fields to mask SG) for LS operation.
Exposure + readout duration (number of fields to mask SUBCK) for LS.
SUBCKTOG_UPDATE 0 = SUBCK HP toggles and the registers involved in SUBCK masking
(Register 0x78 and Register 0x74, Bits[27:13]) are updated at SG line.
1 = updated at update line (VD updated).
SUBCKMASK_SKIP1
Test
SUBCKSUPPRESS
SUBCKNUM
SG_SUPPRESS
SUBCK_POL
[27]
0
0
0
0
0
0
0
0
0
0
0
0
VD/SG
VD/SG
Skip the SUBCK mask for the first exposure field only.
Test purpose only. Must be set to 0.
Number of lines after VSG line to begin SUBCK pulses.
Number of SUBCK pulses per field. Must be set less than VDLEN.
Suppress the SG and allow SUBCK to finish at SUBCKNUM.
SUBCK start polarity.
[0]
[13:1]
[26:14]
[27]
0x76
0x77
0x78
0x79
[0]
[1]
VD/SG
VD/SG
VD/SG
VD
TESTMODE
Test use only. Must be set to 0.
[13:0]
[27:14]
[13:0]
[27:14]
[25:0]
SUBCK_TOG1
SUBCK_TOG2
SUBCKHP_TOG1
SUBCKHP_TOG2
TESTMODE
SUBCK Toggle Position 1.
SUBCK Toggle Position 2.
High precision SUBCK Toggle Position 1.
High precision SUBCK Toggle Position 2.
Test use only. Must be set to 0.
Rev. B | Page 101 of 112
AD9920A
Data
Address Bits
Default
Value
Update
Type
Name
Description
0x7A
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
0
0
0
0
0
0
0
0
VD
GP1_POL
GP2_POL
GP3_POL
GP4_POL
GP5_POL
GP6_POL
GP7_POL
GP8_POL
SEL_GP1
GP1 low/high start polarity.
GP2 low/high start polarity.
GP3 low/high start polarity.
GP4 low/high start polarity.
GP5 low/high start polarity.
GP6 low/high start polarity.
GP7 low/high start polarity.
GP8 low/high start polarity.
0x01
1 = GP1 signal is selected for GPO1 output.
0 = internal signal is selected.
[9]
0x01
0x01
SEL_GP2
SEL_GP3
1 = GP2 signal is selected for GPO2 output.
0 = internal signal is selected.
1 = GP3 signal is selected for GPO3 output.
0 = internal signal is selected.
[10]
[11]
[12]
[13]
[14]
[15]
[23:16]
[24]
0x01
0x01
0x01
0x01
0x01
0
SEL_GP4
SEL_GP5
SEL_GP6
SEL_GP7
SEL_GP8
GPO_OUTPUT_EN
GPO5_OVERRIDE
1 = GP4 signal is selected for GPO4 output. 0 = XSUBCK is selected.
1 = GP5 signal is selected for GPO5 output. 0 = XV21 is selected.
1 = GP6 signal is selected for GPO6 output. 0 = XV22 is selected.
1 = GP7 signal is selected for GPO7 output. 0 = XV23 is selected.
1 = GP8 signal is selected for GPO8 output. 0 = XV24 is selected.
1 = GPO enabled. 0 = GPO is high-Z (default).
0
1 = when GPO5 is configured as an input, this register overrides the
internal OUT_CONT.
[25]
[26]
[27]
[7:0]
0
0
0
0
GPO6_OVERRIDE
GPO7_OVERRIDE
GPO8_OVERRIDE
GPx_USE_LUT
1 = when GPO6 is configured as an input, this register overrides the
internal HBLK.
1 = when GPO7 is configured as an input, this register overrides the
internal CLPOB.
1 = when GPO8 is configured as an input, this register overrides the
internal PBLK.
0x7B
VD
Enable LUT for each GPO signal.
1 = enable.
0 = disable (use normal GP signal).
[11:8]
0000
LUT_FOR_GP12
LUT_FOR_GP34
LUT_FOR_GP56
LUT_FOR_GP78
GP1_TOG1_FD
GP1_TOG1_LN
GP1_TOG1_PX
GP1_TOG2_FD
GP1_TOG2_LN
GP1_TOG2_PX
GP1_TOG3_FD
GP1_TOG3_LN
GP1_TOG3_PX
GP1_TOG4_FD
GP1_TOG4_LN
GP1_TOG4_PX
GP2_TOG1_FD
GP2_TOG1_LN
GP2_TOG1_PX
GP2_TOG2_FD
GP2_TOG2_LN
GP2_TOG2_PX
Two-input lookup table results.
Examples: {LUT_FOR_GP12} Å [GP2:GP1].
{0110} = GP2 XOR GP1; {1110} = GP2 OR GP1.
{0111} = GP2 NAND GP1; {1000} = GP2 AND GP1.
[15:12] 0000
[19:16] 0000
[23:20] 0000
0x7C
0x7D
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VD
VD
VD
VD
VD
VD
VD
VD
VD
General-Purpose Signal 1, first toggle position, field location.
General-Purpose Signal 1, first toggle position, line location.
General-Purpose Signal 1, first toggle position, pixel location.
General-Purpose Signal 1, second toggle position, field location.
General-Purpose Signal 1, second toggle position, line location.
General-Purpose Signal 1, second toggle position, pixel location.
General-Purpose Signal 1, third toggle position, field location.
General-Purpose Signal 1, third toggle position, line location.
General-Purpose Signal 1, third toggle position, pixel location.
General-Purpose Signal 1, fourth toggle position, field location.
General-Purpose Signal 1, fourth toggle position, line location.
General-Purpose Signal 1, fourth toggle position, pixel location.
General-Purpose Signal 2, first toggle position, field location.
General-Purpose Signal 2, first toggle position, line location.
General-Purpose Signal 2, first toggle position, pixel location.
General-Purpose Signal 2, second toggle position, field location.
General-Purpose Signal 2, second toggle position, line location.
General-Purpose Signal 2, second toggle position, pixel location.
[25:13]
[12:0]
[25:13]
Rev. B | Page 102 of 112
AD9920A
Data
Address Bits
Default
Value
Update
Type
Name
Description
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
GP2_TOG3_FD
GP2_TOG3_LN
GP2_TOG3_PX
GP2_TOG4_FD
GP2_TOG4_LN
GP2_TOG4_PX
GP3_TOG1_FD
GP3_TOG1_LN
GP3_TOG1_PX
GP3_TOG2_FD
GP3_TOG2_LN
GP3_TOG2_PX
GP3_TOG3_FD
GP3_TOG3_LN
GP3_TOG3_PX
GP3_TOG4_FD
GP3_TOG4_LN
GP3_TOG4_PX
GP4_TOG1_FD
GP4_TOG1_LN
GP4_TOG1_PX
GP4_TOG2_FD
GP4_TOG2_LN
GP4_TOG2_PX
GP4_TOG3_FD
GP4_TOG3_LN
GP4_TOG3_PX
GP4_TOG4_FD
GP4_TOG4_LN
GP4_TOG4_PX
GP5_TOG1_FD
GP5_TOG1_LN
GP5_TOG1_PX
GP5_TOG2_FD
GP5_TOG2_LN
GP5_TOG2_PX
GP5_TOG3_FD
GP5_TOG3_LN
GP5_TOG3_PX
GP5_TOG4_FD
GP5_TOG4_LN
GP5_TOG4_PX
GP6_TOG1_FD
GP6_TOG1_LN
GP6_TOG1_PX
GP6_TOG2_FD
GP6_TOG2_LN
GP6_TOG2_PX
GP6_TOG3_FD
GP6_TOG3_LN
General-Purpose Signal 2, third toggle position, field location.
General-Purpose Signal 2, third toggle position, line location.
General-Purpose Signal 2, third toggle position, pixel location.
General-Purpose Signal 2, fourth toggle position, field location.
General-Purpose Signal 2, fourth toggle position, line location.
General-Purpose Signal 2, fourth toggle position, pixel location.
General-Purpose Signal 3, first toggle position, field location.
General-Purpose Signal 3, first toggle position, line location.
General-Purpose Signal 3, first toggle position, pixel location.
General-Purpose Signal 3, second toggle position, field location.
General-Purpose Signal 3, second toggle position, line location.
General-Purpose Signal 3, second toggle position, pixel location.
General-Purpose Signal 3, third toggle position, field location.
General-Purpose Signal 3, third toggle position, line location.
General-Purpose Signal 3, third toggle position, pixel location.
General-Purpose Signal 3, fourth toggle position, field location.
General-Purpose Signal 3, fourth toggle position, line location.
General-Purpose Signal 3, fourth toggle position, pixel location.
General-Purpose Signal 4, first toggle position, field location.
General-Purpose Signal 4, first toggle position, line location.
General-Purpose Signal 4, first toggle position, pixel location.
General-Purpose Signal 4, second toggle position, field location.
General-Purpose Signal 4, second toggle position, line location.
General-Purpose Signal 4, second toggle position, pixel location.
General-Purpose Signal 4, third toggle position, field location.
General-Purpose Signal 4, third toggle position, line location.
General-Purpose Signal 4, third toggle position, pixel location.
General-Purpose Signal 4, fourth toggle position, field location.
General-Purpose Signal 4, fourth toggle position, line location.
General-Purpose Signal 4, fourth toggle position, pixel location.
General-Purpose Signal 5, first toggle position, field location.
General-Purpose Signal 5, first toggle position, line location.
General-Purpose Signal 5, first toggle position, pixel location.
General-Purpose Signal 5, second toggle position, field location.
General-Purpose Signal 5, second toggle position, line location.
General-Purpose Signal 5, second toggle position, pixel location.
General-Purpose Signal 5, third toggle position, field location.
General-Purpose Signal 5, third toggle position, line location.
General-Purpose Signal 5, third toggle position, pixel location.
General-Purpose Signal 5, fourth toggle position, field location.
General-Purpose Signal 5, fourth toggle position, line location.
General-Purpose Signal 5, fourth toggle position, pixel location.
General-Purpose Signal 6, first toggle position, field location.
General-Purpose Signal 6, first toggle position, line location.
General-Purpose Signal 6, first toggle position, pixel location.
General-Purpose Signal 6, second toggle position, field location.
General-Purpose Signal 6, second toggle position, line location.
General-Purpose Signal 6, second toggle position, pixel location.
General-Purpose Signal 6, third toggle position, field location.
General-Purpose Signal 6, third toggle position, line location.
[25:13]
[12:0]
[25:13]
Rev. B | Page 103 of 112
AD9920A
Data
Address Bits
[12:0]
Default
Value
Update
Type
Name
Description
0x9E
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
GP6_TOG3_PX
GP6_TOG4_FD
GP6_TOG4_LN
GP6_TOG4_PX
GP7_TOG1_FD
GP7_TOG1_LN
GP7_TOG1_PX
GP7_TOG2_FD
GP7_TOG2_LN
GP7_TOG2_PX
GP7_TOG3_FD
GP7_TOG3_LN
GP7_TOG3_PX
GP7_TOG4_FD
GP7_TOG4_LN
GP7_TOG4_PX
GP8_TOG1_FD
GP8_TOG1_LN
GP8_TOG1_PX
GP8_TOG2_FD
GP8_TOG2_LN
GP8_TOG2_PX
GP8_TOG3_FD
GP8_TOG3_LN
GP8_TOG3_PX
GP8_TOG4_FD
GP8_TOG4_LN
GP8_TOG4_PX
GP_LN_MODE
UNUSED
General-Purpose Signal 6, third toggle position, pixel location.
General-Purpose Signal 6, fourth toggle position, field location.
General-Purpose Signal 6, fourth toggle position, line location.
General-Purpose Signal 6, fourth toggle position, pixel location.
General-Purpose Signal 7, first toggle position, field location.
General-Purpose Signal 7, first toggle position, line location.
General-Purpose Signal 7, first toggle position, pixel location.
General-Purpose Signal 7, second toggle position, field location.
General-Purpose Signal 7, second toggle position, line location.
General-Purpose Signal 7, second toggle position, pixel location.
General-Purpose Signal 7, third toggle position, field location.
General-Purpose Signal 7, third toggle position, line location.
General-Purpose Signal 7, third toggle position, pixel location.
General-Purpose Signal 7, fourth toggle position, field location.
General-Purpose Signal 7, fourth toggle position, line location.
General-Purpose Signal 7, fourth toggle position, pixel location.
General-Purpose Signal 8, first toggle position, field location.
General-Purpose Signal 8, first toggle position, line location.
General-Purpose Signal 8, first toggle position, pixel location.
General-Purpose Signal 8, second toggle position, field location.
General-Purpose Signal 8, second toggle position, line location.
General-Purpose Signal 8, second toggle position, pixel location.
General-Purpose Signal 8, third toggle position, field location.
General-Purpose Signal 8, third toggle position, line location.
General-Purpose Signal 8, third toggle position, pixel location.
General-Purpose Signal 8, fourth toggle position, field location.
General-Purpose Signal 8, fourth toggle position, line location.
General-Purpose Signal 8, fourth toggle position, pixel location.
1 = outputs specified GP pulse on every line.
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[7:0]
0xAC
0xAD
0xAE
0xAF
VD
VD
VD
VD
[27]
Do not access, or set to 0.
[27]
UNUSED
Do not access, or set to 0.
[27]
UNUSED
Do not access, or set to 0.
Table 60. Update Control Registers
Data
Address Bits
Default
Value
Update
Type
Name
Description
0xB0
[15:0]
0x5803
SCK
AFE_UPDT_SCK
Each bit corresponds to one address location.
Bit 0: 1 = update Address 0x00 on SL rising edge.
Bit 1: 1 = update Address 0x01 on SL rising edge.
Bit 15: 1 = update Address 0x0F on SL rising edge.
0xB1
[15:0]
0xA7FC
SCK
AFE_UPDT_VD
Each bit corresponds to one address location.
Bit 0: 1 = update Address 0x00 on VD rising edge.
Bit 1: 1 = update Address 0x01 on VD rising edge.
Bit 15: 1 = update Address 0x0F on VD rising edge.
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[27:0]
[27:0]
0xD8FD
0x2702
0xFFF9
0x0006
0xFFFF
0000
SCK
SCK
SCK
SCK
SCK
SCK
MISC_UPDT_SCK
MISC_UPDT_VD
VDHD_UPDT_SCK
VDHD_UPDT_VD
TC_UPDT_SCK
TC_UPDT_VD
Test
Enable SCK update of miscellaneous registers, Address 0x10 to Address 0x1F.
EnableVD update of miscellaneous registers, Address 0x10 to Address 0x1F.
Enable SCK update of VD/HD registers, Address 0x20 to Address 0x2F.
Enable VD update of VD/HD registers, Address 0x20 to Address 0x2F.
Enable SCK update of timing core registers, Address 0x30 to Address 0x3F.
Enable VD update of timing core registers, Address 0x30 to Address 0x3F.
Test register. Do not access, or write to 0x04.
0x04
0
UNUSED
Do not access, or write to 0x00.
Rev. B | Page 104 of 112
AD9920A
Data
Address Bits
Default
Value
Update
Type
Name
Description
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
0
0
0
0
0
0
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
Do not access, or write to 0x00.
Do not access, or write to 0x00.
Do not access, or write to 0x00.
Do not access, or write to 0x00.
Do not access, or write to 0x00.
Do not access, or write to 0x00.
Table 61. Extra Registers
Address Data Bits Default Value Update Name
Description
0xC0
0xC1
0xC2
0xC3
[27:0]
[27:0]
[27:0]
[7:0]
0
0
0
0
0
VD
VD
VD
SCK
Test
Test
Test
Do not access, or write to 0x00.
Do not access, or write to 0x00.
Do not access, or write to 0x00.
GPO_MASK_HIGH 1 = masks GPO[x] to high. Takes priority over normal operation.
GPO_MASK_LOW 1 = masks GPO[x] to low. Takes priority over normal operation and
GPO_MASK_HIGH.
[15:8]
0xC4
0xC5
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
[19:0]
[20]
0
VD
Test
Test register. Do not access, or set to 0.
Test register. Do not access, or set to 0x1516.
Unused register. Do not access, or set to 0.
Unused register. Do not access, or set to 0.
Test register. Do not access, or set to 0.
Test register. Do not access, or set to 0xFFFF.
Test register. Do not access, or set to 0.
Test register. Do not access, or set to 0.
Unused register. Do not access, or set to 0.
Unused register. Do not access, or set to 0.
Unused register. Do not access, or set to 0.
Unused register. Do not access, or set to 0.
Test register. Do not access, or set to 0.
Test use only. Set to 0.
Must be set to 1 to start the device.
Test register. Do not access, or set to 0.
Test register. Do not access, or set to 0.
Test use only. Set to 0.
1 = allow observation of internal signals at GPO1 to GPO3 outputs
(must also set SEL_GPx bits low).
0x1516
SCK
Test
0
UNUSED
UNUSED
Test
0
0
SCK
SCK
SCK
SCK
0xFFFF
Test
0
0
0
0
0
0
0
0
0
0
0
0
0
Test
Test
UNUSED
UNUSED
UNUSED
UNUSED
Test
SCK
SCK
Test
STARTUP
Test
0xD2
0xD3
0xD4
[27:0]
[27:0]
[0]
SCK
SCK
SCK
Test
Test
GPO_INT_EN
[1]
Note that GPO4 to GPO8 continue to output normal GP toggles.
GPO1: internal clock.
GPO2: CLPOB.
GPO3: delayed sample clock.
Test use only. Set to 0.
Test use only. Set to 0.
Test use only. Set to 0xA10.
Test use only. Set to 0.
[9:2]
0
Test
Test
Test
Test
0xD5
0xD6
0xD7
0xD8
[27:0]
[27:0]
[27:0]
[27:0]
0
SCK
SCK
SCK
SCK
0xA10
0
0x888
DOUT_STRENGTH Controls drive strength of data output drivers.
0x888 = normal drive strength.
0x848 = weak drive strength.
0x808 = weaker drive strength.
0xD9
0xDA
0xDB
0xDC
0xDD
[27:0]
[27:0]
[27:0]
[27:0]
[27:0]
0
0
SCK
SCK
SCK
SCK
SCK
Test
Test
Test
Test
Test
Test use only. Set to 0.
Test use only. Set to 0.
Test use only. Set to 0.
Test use only. Set to 0xF7F.
Test use only. Set to 0x14.
0xF7F
0x14
Rev. B | Page 105 of 112
AD9920A
Address Data Bits Default Value Update Name
Description
0xDE
0xDF
[27:0]
[27:0]
0
0
SCK
SCK
Test
Test
Test use only. Set to 0.
Test use only. Set to 0.
Table 62. V-Pattern Group (VPAT) Register Map (Default Values Are Undefined)
Address
Data Bits
Default Value
Update Type
Name
Description
0x00
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SCP
XV1TOG1
XV1TOG2
XV1TOG3
XV1TOG4
XV2TOG1
XV2TOG2
XV2TOG3
XV2TOG4
XV3TOG1
XV3TOG2
XV3TOG3
XV3TOG4
XV4TOG1
XV4TOG2
XV4TOG3
XV4TOG4
XV5TOG1
XV5TOG2
XV5TOG3
XV5TOG4
XV6TOG1
XV6TOG2
XV6TOG3
XV6TOG4
XV7TOG1
XV7TOG2
XV7TOG3
XV7TOG4
XV8TOG1
XV8TOG2
XV8TOG3
XV8TOG4
XV9TOG1
XV9TOG2
XV9TOG3
XV9TOG4
XV10TOG1
XV10TOG2
XV10TOG3
XV10TOG4
XV11TOG1
XV11TOG2
XV11TOG3
XV11TOG4
XV12TOG1
XV12TOG2
XV1 Toggle Position 1.
XV1 Toggle Position 2.
XV1 Toggle Position 3.
XV1 Toggle Position 4.
XV2 Toggle Position 1.
XV2 Toggle Position 2.
XV2 Toggle Position 3.
XV2 Toggle Position 4.
XV3 Toggle Position 1.
XV3 Toggle Position 2.
XV3 Toggle Position 3.
XV3 Toggle Position 4.
XV4 Toggle Position 1.
XV4 Toggle Position 2.
XV4 Toggle Position 3.
XV4 Toggle Position 4.
XV5 Toggle Position 1.
XV5 Toggle Position 2.
XV5 Toggle Position 3.
XV5 Toggle Position 4.
XV6 Toggle Position 1.
XV6 Toggle Position 2.
XV6 Toggle Position 3.
XV6 Toggle Position 4.
XV7 Toggle Position 1.
XV7 Toggle Position 2.
XV7 Toggle Position 3.
XV7 Toggle Position 4.
XV8 Toggle Position 1.
XV8 Toggle Position 2.
XV8 Toggle Position 3.
XV8 Toggle Position 4.
XV9 Toggle Position 1.
XV9 Toggle Position 2.
XV9 Toggle Position 3.
XV9 Toggle Position 4.
XV10 Toggle Position 1.
XV10 Toggle Position 2.
XV10 Toggle Position 3.
XV10 Toggle Position 4.
XV11 Toggle Position 1.
XV11 Toggle Position 2.
XV11 Toggle Position 3.
XV11 Toggle Position 4.
XV12 Toggle Position 1.
XV12 Toggle Position 2.
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
Rev. B | Page 106 of 112
AD9920A
Address
Data Bits
[12:0]
Default Value
Update Type
Name
Description
0x17
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SCP
XV12TOG3
XV12TOG4
XV13TOG1
XV13TOG2
XV13TOG3
XV13TOG4
XV14TOG1
XV14TOG2
XV14TOG3
XV14TOG4
XV15TOG1
XV15TOG2
XV15TOG3
XV15TOG4
XV16TOG1
XV16TOG2
XV16TOG3
XV16TOG4
XV17TOG1
XV17TOG2
XV17TOG3
XV17TOG4
XV18TOG1
XV18TOG2
XV18TOG3
XV18TOG4
XV19TOG1
XV19TOG2
XV19TOG3
XV19TOG4
XV20TOG1
XV20TOG2
XV20TOG3
XV20TOG4
XV21TOG1
XV21TOG2
XV21TOG3
XV21TOG4
XV22TOG1
XV22TOG2
XV22TOG3
XV22TOG4
XV23TOG1
XV23TOG2
XV23TOG3
XV23TOG4
XV24TOG1
XV24TOG2
XV24TOG3
XV24TOG4
XV12 Toggle Position 3.
XV12 Toggle Position 4.
XV13 Toggle Position 1.
XV13 Toggle Position 2.
XV13 Toggle Position 3.
XV13 Toggle Position 4.
XV14 Toggle Position 1.
XV14 Toggle Position 2.
XV14 Toggle Position 3.
XV14 Toggle Position 4.
XV15 Toggle Position 1.
XV15 Toggle Position 2.
XV15 Toggle Position 3.
XV15 Toggle Position 4.
XV16 Toggle Position 1.
XV16 Toggle Position 2.
XV16 Toggle Position 3.
XV16 Toggle Position 4.
XV17 Toggle Position 1.
XV17 Toggle Position 2.
XV17 Toggle Position 3.
XV17 Toggle Position 4.
XV18 Toggle Position 1.
XV18 Toggle Position 2.
XV18 Toggle Position 3.
XV18 Toggle Position 4.
XV19 Toggle Position 1.
XV19 Toggle Position 2.
XV19 Toggle Position 3.
XV19 Toggle Position 4.
XV20 Toggle Position 1.
XV20 Toggle Position 2.
XV20 Toggle Position 3.
XV20 Toggle Position 4.
XV21 Toggle Position 1.
XV21 Toggle Position 2.
XV21 Toggle Position 3.
XV21 Toggle Position 4.
XV22 Toggle Position 1.
XV22 Toggle Position 2.
XV22 Toggle Position 3.
XV22 Toggle Position 4.
XV23 Toggle Position 1.
XV23 Toggle Position 2.
XV23 Toggle Position 3.
XV23 Toggle Position 4.
XV24 Toggle Position 1.
XV24 Toggle Position 2.
XV24 Toggle Position 3.
XV24 Toggle Position 4.
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
[25:13]
Rev. B | Page 107 of 112
AD9920A
Table 63. V-Sequence (VSEQ) Registers (Default Values Are Undefined)
Data
Address Bits
Default Update
Value
Type
Name
Description
0x00
[0]
[1]
[5:2]
[6]
[9:7]
X
X
X
X
X
SCP
CLPOBPOL
PBLKPOL
HOLD
VSEQALT_EN
SPC_PAT_EN
CLPOB start polarity.
PBLK start polarity.
1 = enable HOLD function for each VPAT group (A, B, C, D).
Special V-sequence alternation enable.
1 = enable use of special vertical pattern insertion into VPATA sequence.
Bit 0: Use VPATB as the special pattern.
Bit 1: Use VPATC as the special pattern.
Bit 2: Use VPATD as the special pattern.
[13:10]
[15:14]
X
X
CONCAT_GRP
VREP_MODE
Combine multiple VPAT groups together in one sequence. Set register
equal to 0x01 to enable.
Defines V-alternation repetition mode.
00 = single-pattern alternation for all groups.
01 = two-pattern alternation for all groups.
10 = three-pattern alternation for Group A; Groups B/C/D follow pattern
{0, 1, 1, 0, 1, 1…}.
11 = four-pattern alternation for Group A; two-pattern for Groups B/C/D.
[19:16]
[21:20]
X
X
LASTREPLEN_EN
HBLK_MODE
Enable a separate pattern length to be used during the last repetition of
the V-sequence. One bit for each group (A, B, C, and D); Group A is the LSB.
Set bit high to enable. Recommended value is enabled.
Selection of HBLK modes.
00 = HBLK Mode 0 (normal six-toggle operation).
01 = HBLK Mode 1.
10 = test use only; do not access.
11 = test use only; do not access.
Test use only. Set to 0.
1 = enable SUBCK masking feature.
HD line length for even lines.
HD line length for odd lines.
[23:22]
[24]
X
X
X
X
X
Test
SUBCK_MASK
HDLENE
0x01
0x02
0x03
[13:0]
[13:0]
[23:0]
SCP
SCP
SCP
HDLENO
VSGPATSEL
Select which two toggle positions are used by each V-output
when they are configured as VSG pulses (in Miscellaneous Register 0x1C).
0 = use Toggle 1, Toggle 2.
1 = use Toggle 3, Toggle 4.
0x04
0x05
[12:0]
X
X
X
X
SCP
SCP
LASTREPLEN_A
LASTREPLEN_B
LASTREPLEN_C
LASTREPLEN_D
Last repetition length for Group A. Must be enabled using LASTREPLEN_EN
register. Set equal to VLENA register.
Last repetition length for Group B. Must be enabled using LASTREPLEN_EN
register. Set equal to VLENB register.
[25:13]
[12:0]
Last repetition length for Group C. Must be enabled using LASTREPLEN_EN
register. Set equal to VLENC register.
Last repetition length for Group D. Must be enabled using LASTREPLEN_EN
register. Set equal to VLEND register.
[25:13]
0x06
0x07
[23:0]
[23:0]
X
X
SCP
SCP
VPOL
Starting polarities for each V-output signal.
GROUPSEL_0
Select to which group each V1 to V12 signal is assigned.
00 = Group A.
01 = Group B.
10 = Group C.
11 = Group D.
Bits[1:0]: V1.
Bits[3:2]: V2.
Bits[23:22]: V12.
Rev. B | Page 108 of 112
AD9920A
Data
Address Bits
Default Update
Value
Type
Name
Description
0x08
[23:0]
X
SCP
GROUPSEL_1
Select to which group each V13 to V24 signal is assigned.
00 = Group A.
01 = Group B.
10 = Group C.
11 = Group D.
Bits[1:0]: V13.
Bits[3:2]: V14.
Bits[23:22]: V24.
0x09
[4:0]
[9:5]
[14:10]
[19:15]
[20]
X
X
X
X
X
X
SCP
VPATSELA
VPATSELB
VPATSELC
VPATSELD
SEQ_ALT_INC
SEQ_ALT_RST
Selected VPAT group for Group A, from VPAT Group 0 to Group 31.
Selected VPAT group for Group B, from VPAT Group 0 to Group 31.
Selected VPAT group for Group C, from VPAT Group 0 to Group 31.
Selected VPAT group for Group D, from VPAT Group 0 to Group 31.
1 = increment sequence number on next line.
[21]
1 = reset sequence number to sequence defined for that particular region
in the field register.
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[20:13]
[21]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
SCP
VSTARTA
VLENA
Start position of selected V-pattern Group A.
Length of selected V-pattern Group A.
VREPA_1
VREPA_2
Number of repetitions for V-pattern Group A for first lines.
Number of repetitions for V-pattern Group A for second lines.
Number of repetitions for V-pattern Group A for third lines.
Number of repetitions for V-pattern Group A for fourth lines.
Start position of selected V-pattern Group B.
VREPA_3
VREPA_4
VSTARTB
VLENB
Length of selected V-pattern Group B.
VREPB_ODD
VREPB_EVEN
VSTARTC
Number of repetitions for V-pattern Group B for odd lines.
Number of repetitions for V-pattern Group B for even lines.
Start position of selected V-pattern Group C.
VLENC
Length of selected V-pattern Group C.
VREPC_ODD
VREPC_EVEN
VSTARTD
Number of repetitions for V-pattern Group C for odd lines.
Number of repetitions for V-pattern Group C for even lines.
Start position of selected V-pattern Group D.
VLEND
Length of selected V-pattern Group D.
VREPD_ODD
VREPD_EVEN
FREEZE1
RESUME1
FREEZE2
RESUME2
FREEZE3
RESUME3
FREEZE4
RESUME4
HBLKSTART
HBLKEND
HBLKLEN
Number of repetitions for V-pattern Group D for odd lines.
Number of repetitions for V-pattern Group D for even lines.
Holds the V-outputs at their current levels.
Resumes the operation of V-outputs to finish the pattern.
Holds the V-outputs at their current levels.
Resumes the operation of V-outputs to finish the pattern.
Holds the V-outputs at their current levels.
Resumes the operation of V-outputs to finish the pattern.
Holds the V-outputs at their current levels.
Resumes the operation of V-outputs to finish the pattern.
Start location for HBLK in HBLK Mode 0 and HBLK Mode 1.
End location for HBLK in HBLK Mode 0 and HBLK Mode 1.
HBLK length in HBLK Mode 0 and Mode 1.
Number of HBLK repetitions in HBLK Mode 0 and HBLK Mode 1.
Masking polarity for H1/H3/H5/H7 during HBLK.
Masking polarity for H2/H4/H6/H8 during HBLK.
Masking polarity for HL during HBLK.
HBLKREP
HBLKMASK_H1
HBLKMASK_H2
HBLKMASK_HL
HBLKMASK_H3P
HBLKTOGO1
HBLKTOGO2
[22]
[23]
[24]
Masking polarity for H3P during 3-phase mode during HBLK.
First HBLK toggle position for odd lines, or RA0H1REPA/B/C in HBLK Mode 1.
Second HBLK toggle position for odd lines, or RA1H1REPA/B/C.
0x19
[12:0]
[25:13]
SCP
Rev. B | Page 109 of 112
AD9920A
Data
Address Bits
Default Update
Value
Type
Name
Description
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[16:13]
[20:17]
[2:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
SCP
HBLKTOGO3
HBLKTOGO4
HBLKTOGO5
HBLKTOGO6
HBLKTOGE1
Third HBLK toggle position for odd lines, or RA2H1REPA/B/C.
Fourth HBLK toggle position for odd lines, or RA3H1REPA/B/C.
Fifth HBLK toggle position for odd lines, or RA4H1REPA/B/C.
Sixth HBLK toggle position for odd lines, or RA5H1REPA/B/C.
First HBLK toggle position for even lines, or RA0H2REPA/B/C.
Second HBLK toggle position for even lines, or RA1H2REPA/B/C.
Third HBLK toggle position for even lines, or RA2H2REPA/B/C.
Fourth HBLK toggle position for even lines, or RA3H2REPA/B/C.
Fifth HBLK toggle position for even lines, or RA4H2REPA/B/C.
Sixth HBLK toggle position for even lines, or RA5H2REPA/B/C.
HBLK repeat area Start Position A for HBLK Mode 1. Set to 8191 if not used.
HBLK repeat area Start Position B for HBLK Mode 1. Set to 8191 if not used.
HBLK repeat area Start Position C for HBLK Mode 1. Set to 8191 if not used.
1 = enable FREEZE/RESUME for each VPAT group (A, B, C, D); even lines.
1 = enable FREEZE/RESUME for each VPAT group (A, B, C, D); odd lines.
HBLK Mode 1, Repeat Area 0 pattern for odd lines.
HBLK Mode 1, Repeat Area 1 pattern for odd lines.
HBLK Mode 1, Repeat Area 2 pattern for odd lines.
HBLK Mode 1, Repeat Area 3 pattern for odd lines.
HBLK Mode 1, Repeat Area 4 pattern for odd lines.
HBLK Mode 1, Repeat Area 5 pattern for odd lines.
CLPOB Toggle Position 1.
SCP
SCP
SCP
SCP
SCP
SCP
HBLKTOGE2
HBLKTOGE3
HBLKTOGE4
HBLKTOGE5
HBLKTOGE6
HBLKSTARTA
HBLKSTARTB
HBLKSTARTC
VMASK_EVEN
VMASK_ODD
HBLKALT_PAT0
HBLKALT_PAT1
HBLKALT_PAT2
HBLKALT_PAT3
HBLKALT_PAT4
HBLKALT_PAT5
CLPOBTOG1
CLPOBTOG2
PBLKTOG1
0x21
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SCP
[6:4]
[10:8]
[14:12]
[18:16]
[22:20]
[12:0]
[25:13]
[12:0]
[25:13]
[11:0]
[23:12]
[11:0]
0x22
0x23
0x24
0x25
0x26
0x27
SCP
SCP
SCP
SCP
SCP
SCP
CLPOB Toggle Position 2.
PBLK Toggle Position 1.
PBLK Toggle Position 2.
PBLKTOG2
HBLK2OFF_A_E
HBLK2OFF_A_O
HBLK2OFF_B_E
HBLK2OFF_B_O
HBLK2OFF_C_E
HBLK2OFF_C_O
HBLKCNT_START
HCLK Offset A for even lines. Used during HBLK Mode 1.
HCLK Offset A for odd lines. Used during HBLK Mode 1.
HCLK Offset B for even lines. Used during HBLK Mode 1.
HCLK Offset B for odd lines. Used during HBLK Mode 1.
HCLK Offset C for even lines. Used during HBLK Mode 1.
HCLK Offset C for odd lines. Used during HBLK Mode 1.
[23:12]
[11:0]
[23:12]
[12:0]
Start position for HBLK counter.
For HBLK operation, HBLKCNT_START should be set equal to the value of
HBLKSTART; if HBLK interval is not needed, set to 8191.
[13]
X
HBLKEND[13]
MSB for HBLKEND register (V-Sequence Register 0x17, Bits[25:13]).
Rev. B | Page 110 of 112
AD9920A
Table 64. Field Registers (Default Values Are Undefined)
Default
Address Data Bits Value
Update Type Name
Description
0x00
[4:0]
[9:5]
[14:10]
[19:15]
[24:20]
[4:0]
X
X
X
X
X
X
X
X
X
VD
SEQ0
SEQ1
SEQ2
SEQ3
Selected V-sequence for first region in the field.
Selected V-sequence for second region in the field.
Selected V-sequence for third region in the field.
Selected V-sequence for fourth region in the field.
Selected V-sequence for fifth region in the field.
Selected V-sequence for sixth region in the field.
Selected V-sequence for seventh region in the field.
Selected V-sequence for eighth region in the field.
Selected V-sequence for ninth region in the field.
SEQ4
0x01
VD
SEQ5
SEQ6
SEQ7
SEQ8
[9:5]
[14:10]
[19:15]
[21:20]
MULT_SWEEP0
Enables multiplier mode and/or sweep mode for Region 0.
0 = multiplier off/sweep off.
1 = multiplier off/sweep on.
2 = multiplier on/sweep off.
3 = multiplier on/sweep on.
[23:22]
[25:24]
[12:0]
[14:13]
[16:15]
[18:17]
[20:19]
[22:21]
[24:23]
[25]
MULT_SWEEP1
MULT_SWEEP2
HDLASTLEN
MULT_SWEEP3
MULT_SWEEP4
MULT_SWEEP5
MULT_SWEEP6
MULT_SWEEP7
MULT_SWEEP8
HDLASTLEN_13
SCP0
Enables multiplier mode and/or sweep mode for Region 1.
Enables multiplier mode and/or sweep mode for Region 2.
HD last line length. Line length of last line in the field.
Enables multiplier mode and/or sweep mode for Region 3.
Enables multiplier mode and/or sweep mode for Region 4.
Enables multiplier mode and/or sweep mode for Region 5.
Enables multiplier mode and/or sweep mode for Region 6.
Enables multiplier mode and/or sweep mode for Region 7.
Enables multiplier mode and/or sweep mode for Region 8.
HD last line length bit [13] when 14-bit H-counter is enabled.
V-Sequence Change Position 0.
0x02
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
VD
0x03
0x04
0x05
0x06
0x07
0x08
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[23:0]
VD
VD
VD
VD
VD
VD
SCP1
V-Sequence Change Position 1.
SCP2
SCP3
V-Sequence Change Position 2.
V-Sequence Change Position 3.
SCP4
SCP5
V-Sequence Change Position 4.
V-Sequence Change Position 5.
SCP6
SCP7
V-Sequence Change Position 6.
V-Sequence Change Position 7.
SCP8
VDLEN
V-Sequence Change Position 8.
VD field length (number of lines in the field).
SG Active Line 1.
SGACTLINE1
SGACTLINE2
SGMASK
SG Active Line 2. Set to SG Active Line 1 or maximum if not used.
Masking of VSG outputs during SG active line.
CLPOB Mask Region 1 start position. Set to 8191 to disable.
CLPOB Mask Region 1 end position. Set to 0 to disable.
CLPOB Mask Region 2 start position. Set to 8191 to disable.
CLPOB Mask Region 2 end position. Set to 0 to disable.
CLPOB Mask Region 3 start position. Set to 8191 to disable.
CLPOB Mask Region 3 end position. Set to 0 to disable.
0x09
0x0A
VD
VD
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
CLPMASKSTART1
CLPMASKEND1
CLPMASKSTART2
CLPMASKEND2
CLPMASKSTART3
CLPMASKEND3
0x0B
0x0C
0x0D
0x0E
0x0F
VD
VD
VD
VD
VD
PBLKMASKSTART1 PBLK Mask Region 1 start position. Set to 8191 to disable.
PBLKMASKEND1 PBLK Mask Region 1 end position. Set to 0 to disable.
PBLKMASKSTART2 PBLK Mask Region 2 start position. Set to 8191 to disable.
PBLKMASKEND2 PBLK Mask Region 2 end position. Set to 0 to disable.
PBLKMASKSTART3 PBLK Mask Region 3 start position. Set to 8191 to disable.
PBLKMASKEND3 PBLK Mask Region 3 end position. Set to 0 to disable.
[25:13]
Rev. B | Page 111 of 112
AD9920A
OUTLINE DIMENSIONS
8.10
8.00 SQ
7.90
A1 BALL
CORNER
11 10
9
8
7
6
5
4
3
2 1
A
B
C
D
E
F
BALL A1
PAD CORNER
6.50
BSC SQ
G
H
J
0.65
BSC
K
L
BOTTOM VIEW
TOP VIEW
DETAIL A
*
1.40
1.31
1.16
DETAIL A
0.91 MIN
0.25 MIN
COPLANARITY
0.10
0.45
0.40
0.35
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT TO JEDEC STANDARDS MO-225
WITH THE EXCEPTION TO PACKAGE HEIGHT.
Figure 118. 105-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-105-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9920ABBCZ
AD9920ABBCZRL
Temperature Range
−25°C to +85°C
−25°C to +85°C
Package Description
105-Ball CSP_BGA
105-Ball CSP_BGA
Package Option
BC-105-1
BC-105-1
1 Z = RoHS Compliant Part.
©2009–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06878-0-6/10(B)
Rev. B | Page 112 of 112
相关型号：
AD9928BBCZ
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ADI
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