AD9923ABBCZRL_技术文档

CCD Signal Processor with V-Driver and

Precision Timing™ Generator

AD9923A

FEATURES

GENERAL DESCRIPTION

Integrated 15-channel V-driver

12-bit, 36 MHz analog-to-digital converter (ADC)

Similar register map to the AD9923

5-field, 10-phase vertical clock support

Complete on-chip timing generator

Precision Timing core with <600 ps resolution

Correlated double sampler (CDS)

The AD9923A is a complete 36 MHz front-end solution for

digital still cameras and other CCD imaging applications.

Similar to the AD9923 product, the AD9923A includes the

analog front end (AFE), a fully programmable timing generator

(TG), and a 15-channel vertical driver (V-driver). A Precision

Timing core allows adjustment of high speed clocks with

approximately 600 ps resolution at 36 MHz operation.

6 dB to 42 dB 10-bit variable gain amplifier (VGA)

Black level clamp with variable level control

On-chip 3 V horizontal and RG drivers

2-phase and 4-phase H-clock modes

Electronic and mechanical shutter support

On-chip driver for external crystal

The on-chip V-driver supports up to 15 channels for use with

5-field, 10-phase CCDs.

The analog front end includes black level clamping, CDS, VGA,

and a 12-bit ADC. The timing generator and V-driver provide

all the necessary CCD clocks: RG, H-clocks, vertical clocks, sensor

gate pulses, substrate clock, and substrate bias control. The

internal registers are programmed using a 3-wire serial

interface.

On-chip sync generator with external sync input

8 mm × 8 mm CSP_BGA package with 0.65 mm pitch

APPLICATIONS

Digital still cameras

Packaged in an 8 mm × 8 mm CSP_BGA, the AD9923A is

specified over an operating temperature range of −25°C to +85°C.

.

FUNCTIONAL BLOCK DIAGRAM

REFT

REFB

–3dB, 0dB, +3dB, +6dB

CDS

+6dB TO +42dB

VGA

AD9923A

VREF

12

12-BIT

ADC

D0 TO D11

DCLK

CCDIN

CLAMP

RG

HL

INTERNAL CLOCKS

HORIZONTAL

DRIVERS

4

H1 TO H4

PRECISION

TIMING

GENERATOR

SL

13

INTERNAL

REGISTERS

SDI

SCK

XV1 TO

XV13

8

V1, V2, V3,

V4, V5A, V5B,

V6, V7A, V7B,

V8, V9, V10,

VERTICAL

TIMING

CONTROL

15

V-DRIVER

SYNC

GENERATOR

XSG1 TO

XSG8

V11, V12, V13

2

XSUBCK,

XSUBCNT

3

SUBCK

VSUB, MSHUT,

STROBE

HD

VD

SYNC CLI

CLO

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9923A

TABLE OF CONTENTS

Features .............................................................................................. 1

Precision Timing High Speed Timing Generation ................. 14

Horizontal Clamping and Blanking......................................... 18

Vertical Timing Generation...................................................... 25

Vertical Timing Example........................................................... 39

Vertical Driver Signal Configuration........................................... 41

Shutter Timing Control............................................................. 45

SUBCK: Normal Operation...................................................... 46

Example of Exposure and Readout of Interlaced Frame....... 53

FG_TRIG Operation.................................................................. 55

Analog Front End Description/Operation ............................. 56

Standby Mode Operation.......................................................... 61

Circuit Layout Information....................................................... 63

Serial Interface Timing.............................................................. 66

Layout of Internal Registers...................................................... 67

Updating New Register Values ................................................. 68

Complete Register Listing......................................................... 69

Outline Dimensions....................................................................... 85

Ordering Guide .......................................................................... 85

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Specifications..................................................................................... 3

Digital Specifications ................................................................... 4

H-Driver Specifications............................................................... 4

Vertical Driver Specifications ..................................................... 4

Analog Specifications................................................................... 5

Timing Specifications .................................................................. 6

Absolute Maximum Ratings............................................................ 7

Package Thermal Characteristics ............................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Equivalent Circuits......................................................................... 11

Terminology .................................................................................... 12

Theory of Operation ...................................................................... 13

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 2 of 88

AD9923A

SPECIFICATIONS

Table 1.

Parameter

Conditions/Comments

Min

Typ

Max

Unit

TEMPERATURE RANGE

Operating

Storage

−25

−65

+85

+150 °C

°C

AFETG POWER SUPPLY VOLTAGES

AVDD

AFE analog supply

Timing Core Analog Supply

RG Driver

HL, H1 to H4 Drivers

Data Output Drivers

Digital

2.7

3.0

3.6

V

TCVDD

RGVDD

HVDD

DRVDD

DVDD

V-DRIVER POWER SUPPLY

VOLTAGES

VDD1, VDD2

VH1, VH2

VL1, VL2

VM1, VM2

VLL

VMM

V-Driver Logic

+2.7

+3.0

+3.6

V

V-Driver High Supply

V-Driver Low Supply

V-Driver Mid Supply

SUBCK Low Supply

SUBCK Mid Supply

+11.5 +15.0 +16.5

−8.5

−1.5

−8.5

−4.0

−7.5

0.0

−7.5

0.0

−5.5

+1.5

−5.5

+1.5

AFETG POWER DISSIPATION

Total

36 MHz, 3.0 V supply, 400 pF total H-load, 20 pF RG load

335

105

1

mW

Standby 1 Mode

Standby 2 Mode

Standby 3 Mode

Power from HVDD Only¹

Power from RGVDD Only

Power from AVDD Only

Power from TCVDD Only

Power from DVDD Only

Power from DRVDD Only

V-DRIVER POWER DISSIPATION²

1

130

10

75

40

75

5

VH1, VH2 = +15 V; VL1, VL2 = −7.5 V; VM1, VM2 = 0 V; VDD1, VDD2 =

3.3 V; all V-driver inputs tied low

VH1, VH2

VL1, VL2

VM1, VM2

VDD1, VDD2

5

2.5

0

mW

MHz

0.5

MAXIMUM CLOCK RATE (CLI)

36

¹The total power dissipated by the HVDD supply can be approximated using the equation

Total HVDD Power = [C_LOAD× HVDD × Pixel Frequency] × HVDD

Reducing the H-load and/or using a lower HVDD supply reduces the power dissipation. C_LOADis the total capacitance seen by all H-outputs.

²V-driver power dissipation depends on the frequency of operation and the load they are driving. All inputs to the V-driver were tied low for the

measurements in Table 1.

Rev. 0 | Page 3 of 88

AD9923A

DIGITAL SPECIFICATIONS

DRVDD = 2.7 V to 3.6 V, C_L= 20 pF, T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter

Conditions/Comments

Symbol

Min

Typ

Max

Unit

LOGIC INPUTS

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

V_IH

V_IL

I_IH

I_IL

C_IN

2.1

V

μA

pF

0.6

10

LOGIC OUTPUTS

High Level Output Voltage

Low Level Output Voltage

Powered by DVDD, DRVDD

At I_OH= 2 mA

At I_OL= 2 mA

V_OH

V_OL

DVDD − 0.5, DRVDD − 0.5

V

0.5

H-DRIVER SPECIFICATIONS

HVDD = RGVDD = 2.7 V to 3.6 V, C_L= 20 pF, T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter

Conditions/Comments

RG, HL, and H1 to H4 powered by RGVDD, HVDD

At maximum current

Programmable

Min

Typ Max Unit

RG and H-DRIVER OUTPUTS

High Level Output Voltage

Low Level Output Voltage

Maximum Output Current

Maximum Load Capacitance

RGVDD − 0.5, HVDD − 0.5

V

0.5

V

30

100

mA

pF

For each output

VERTICAL DRIVER SPECIFICATIONS

VDD1 = VDD2 = 3.3 V, VH1 = VH2 = 15 V, VM1 = VM2 = VMM = 0 V, VL1 = VL2 = VLL = −7.5 V, 25°C.

Table 4.

Parameter

Conditions/Comments

Symbol

Min

Typ

Max

Unit

V-DRIVER OUTPUTS

Delay Time

Simplified load conditions, 3000 pF to ground

VL to VM and VM to VH

VM to VL and VH to VM

Rise Time

Rising edges

Falling edges

t_PLM, t_PMH

t_PML, t_PHM

35

ns

VL to VM

VM to VH

t_RLM

t_RMH

125

260

ns

Fall Time

VM to VL

VH to VM

t_FML

t_FHM

220

125

ns

Output Currents

@ −7.25 V

@ −0.25 V

@ +0.25 V

@ +14.75 V

R_ON

+10

−22

+22

−10

mA

Ω

35

SUBCK OUTPUT

Delay Time

VLL to VH

Simplified load conditions, 1000 pF to ground

t_PLH

t_PHL

t_PLM

25

30

25

ns

VH to VLL

VLL to VMM

Rev. 0 | Page 4 of 88

AD9923A

Parameter

VMM to VH

Conditions/Comments

Symbol

t_PMH

Min

Typ

25

Max

Unit

ns

VH to VMM

VMM to VLL

t_PHM

t_PML

30

25

ns

Rise Time

VLL to VH

VLL to VMM

VMM to VH

t_RLH

t_RLM

t_RMH

40

45

30

ns

Fall Time

VH to VLL

VH to VMM

VMM to VLL

Output Currents

@ −7.25 V

@ −0.25 V

@ +0.25 V

@ +14.75 V

R_ON

t_FHL

t_FHM

t_FML

40

90

25

ns

20

12

20

mA

Ω

35

V-DRIVER

50%

INPUT

t_RLM, t_RMH, t_RLH

t_PML

,

t_PHM

,

t_PHL

90%

V-DRIVER

OUTPUT

t_PLM

,

t_PMH, t_PLH

t_FML, t_FHM, t_FHL

10%

Figure 2. Definition of V-Driver Timing Specifications

ANALOG SPECIFICATIONS

AVDD = 3.0 V, f_CLI= 36 MHz, typical timing specifications, T_MINto T_MAX, unless otherwise noted.

Table 5.

Parameter

Conditions/Comments

Input characteristics definition¹

Min

Typ

Max

Unit

CDS

Allowable CCD Reset Transient

CDS Gain Accuracy

0.5

1.2

V

VGA gain = 6 dB (Code 15, default value)

Default

−3 dB CDS Gain

0 dB CDS Gain

+3 dB CDS Gain

+6 dB CDS Gain

−3

0

+3

+5.5

−2.5

+0.5

+3.5

+6

−2

+1

+4

+6.5

dB

Maximum Input Range Before Saturation

0 dB CDS Gain

−3 dB CDS Gain

Default setting

1.0

1.4

0.5

V p-p

+6 dB CDS Gain

Maximum CCD Black Pixel Amplitude

0 dB CDS Gain (Default)

+6 dB CDS Gain

Positive offset definition¹

−100

−50

+200 mV

+100 mV

VARIABLE GAIN AMPLIFIER (VGA)

Gain Control Resolution

Gain Monotonicity

1024

Guaranteed

Steps

Gain Range

Minimum Gain (VGA Code 15)

Maximum Gain (VGA Code 1023)

6

42

dB

Rev. 0 | Page 5 of 88

AD9923A

Parameter

Conditions/Comments

Min

Typ

Max

Unit

BLACK LEVEL CLAMP

Measured at ADC output

Clamp Level Resolution

Minimum Clamp Level (Code 0)

Maximum Clamp Level (Code 1023)

ANALOG-TO-DIGITAL CONVERTER (ADC)

Resolution

Differential Nonlinearity (DNL)

No Missing Codes

Full-Scale Input Voltage

VOLTAGE REFERENCE

1024

0

255

Steps

LSB

12

−1.0

Bits

LSB

0.5

Guaranteed

2.0

+1.0

V

Reference Top Voltage (REFT)

Reference Bottom Voltage (REFB)

SYSTEM PERFORMANCE

Gain Accuracy

Low Gain (VGA Code 15)

Maximum Gain (VGA Code 1023)

Peak Nonlinearity, 500 mV Input Signal

Total Output Noise

2.0

1.0

V

Includes entire signal chain

Default CDS gain (0 dB)

6.0

42.0

6.5

42.5

0.1

1.0

50

7.0

43.0

dB

%

LSB rms

dB

12 dB gain applied

AC-grounded input, 6 dB gain applied

Measured with step change on supply

Power Supply Rejection (PSR)

¹Input signal characteristics are defined as shown in Figure 3.

1V MAX

INPUT SIGNAL RANGE

(0dB CDS GAIN)

500mV TYP

RESET TRANSIENT

200mV MAX

OPTICAL BLACK PIXEL

Figure 3. Signal Characteristics

TIMING SPECIFICATIONS

C_L= 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f_CLI= 36 MHz, unless otherwise noted.

Table 6.

Parameter

Conditions/Comments

Symbol Min Typ Max

Unit

MASTER CLOCK, CLI

CLI Clock Period

CLI High/Low Pulse Width

Delay from CLI Rising Edge to Internal Pixel Position 0

AFE CLPOB Pulse Width^{1, 2}

t_CONV

27.8

ns

11.2 13.9 16.6

6

2

t_CLIDLY

20

Pixels

Allowable Region for HD Falling Edge to CLI Rising Edge

SHP Inhibit Region

AFE SAMPLE LOCATION¹

Only valid in slave mode t_HDCLI

Only valid in slave mode t_SHPINH

4

30

t_CONV− 2

39

ns

Edge location

SHP Sample Edge to SHD Sample Edge

DATA OUTPUTS

t_S1

11.6 13.9

ns

Output Delay from DCLK Rising Edge¹

Inhibited Area for DOUTPHASE Edge Location

Pipeline Delay from SHP/SHD Sampling to Data Output

SERIAL INTERFACE

t_OD

8

SHD

16

ns

SHD + 11 Edge location

Cycles

Maximum SCK Frequency

SL to SCK Setup Time

SCK to SL Hold Time

SDATA Valid to SCK Rising Edge Setup

SCK Falling Edge to SDATA Valid Hold

SCK Falling Edge to SDATA Valid Read

f_SCLK

t_LS

t_LH

t_DS

t_DH

t_DV

36

10

MHz

ns

¹Parameter is programmable.

²Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.

Rev. 0 | Page 6 of 88

AD9923A

ABSOLUTE MAXIMUM RATINGS

Table 7.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

To

Rating

AVDD

TCVDD

HVDD

RGVDD

DVDD

DRVDD

AVSS

TCVSS

HVSS

RGVSS

DVSS

DRVSS

−0.3 V to +3.9 V

VDD1, VDD2

VH1, VH2

VL1, VL2

VM1, VM2

VSS1, VSS2 −0.3 V to +6 V

VL1, VL2 −0.3 V to +25 V

VSS1, VSS2 −0.3 V to +17 V

VSS1, VSS2 −17 V to +0.3 V

VSS1, VSS2 −6 V to +6 V

PACKAGE THERMAL CHARACTERISTICS

Thermal Resistance

CSP_BGA package: θ_JA= 40.3°C/W

ESD CAUTION

VLL

VMM

VSS1, VSS2 −17 V to +0.3 V

VSS1, VSS2 −6 V to + VH

VDR_EN

V1 to V15

VSS1, VSS2 −0.3 V to +6 V

VSS1, VSS2 VL − 0.3 V to VH + 0.3 V

RG Output

H1 to H4 Output

Digital Outputs

Digital Inputs

SCK, SL, SDATA

REFT/REFB, CCDIN

Junction Temperature

Lead Temperature, 10 sec

RGVSS

HVSS

DVSS

AVSS

−0.3 V to RGVDD + 0.3 V

−0.3 V to HVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

−0.3 V to AVDD + 0.3 V

150°C

350°C

Rev. 0 | Page 7 of 88

AD9923A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD9923A

TOP VIEW

(Not to Scale)

A1 CORNER

INDEX AREA

1

2

3

4

5

6

7

8

9 10 11

A

B

C

D

E

F

G

H

J

K

L

Figure 4. 105-Lead CSPBGA Package Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

A7

Mnemonic

AVDD

AVSS

Type¹

P

Description

Analog Supply for AFE.

Analog Ground for AFE.

Analog Supply for Timing Core.

Analog Ground for Timing Core.

Digital Logic Power Supply 1.

Digital Logic Ground 1.

Digital Logic Power Supply 2.

Digital Logic Ground 2.

H1 to H4, HL Driver Supply.

H1 to H4, HL Driver Ground.

RG Driver Supply.

A1, A4, B2, B3, B4, B5, B6, B7

P

B8

B9

E1

F2

K8, L7, L8

K9

D9

D10

B10

A10

L4

L5

J4

K5

TCVDD

TCVSS

DVDD1

DVSS1

DVDD2

DVSS2

HVDD

HVSS

RGVDD

RGVSS

DRVDD

DRVSS

VDD1

VSS1

P

RG Driver Ground.

Data Output Driver Supply.

Data Output Driver Ground.

V-Driver Logic Supply 1.

V-Driver Logic Ground 1.

V-Driver Logic Supply 2.

V-Driver Logic Ground 2.

V-Driver High Supply 1.

V-Driver High Supply 2.

V-Driver Low Supply 1.

V-Driver Low Supply 2.

V-Driver Mid Supply 1.

L10

K10

F9

D1

E9

VDD2

VSS2

VH1

VH2

VL1

P

C1

C9

VL2

VM1

P

D3

F3

E3

A6

A5

A3

A2

C3

C2

B1

G7

E5

VM2

VLL

VMM

CCDIN

CCDGND

REFT

REFB

SL

SCK

SDI

P

V-Driver Mid Supply 2.

SUBCK Driver Low Supply.

SUBCK Driver Mid Supply.

CCD Signal Input.

AI

AO

DI

CCD Signal Ground.

Voltage Reference Top Bypass.

Voltage Reference Bottom Bypass.

3-Wire Serial Load Pulse.

3-Wire Serial Clock.

3-Wire Serial Data Input.

External System Synchronization Input.

Reset Bar, Active Low Pulse.

SYNC

RSTB

Rev. 0 | Page 8 of 88

AD9923A

Pin No.

A8

A9

F11

E11

D11

C11

B11

C10

K6

Mnemonic

CLI

CLO

H1

H2

H3

H4

HL

RG

VSUB

MSHUT

STROBE

SUBCK

DCLK

D0

D1

D2

D3

D4

Type¹

DI

Description

Reference Clock Input (Master Clock).

Clock Output for Crystal.

CCD Horizontal Clock 1.

CCD Horizontal Clock 2.

CCD Horizontal Clock 3.

CCD Horizontal Clock 4.

CCD Last Horizontal Clock.

CCD Reset Gate Clock.

CCD Substrate Bias.

Mechanical Shutter Pulse.

Strobe Pulse.

CCD Substrate Clock (E Shutter).

Data Clock Output.

Data Output (LSB).

Data Output.

Data Output (MSB).

Vertical Sync Pulse. Input in slave mode, output in master mode.

Horizontal Sync Pulse. Input in slave mode, output in master mode.

CCD Vertical Transfer Clock.

DO

DIO

VO3

VO2

VO3

VO2

VO3

VO2

VO3

VO2

VO3

VO2

DI

F5

G5

G6

F1

G1

H3

H2

H1

J3

J2

J1

K3

K2

K1

L3

L2

D2

E2

C8

G10

E7

G9

C4

C5

D5

D6

D7

D8

D9

D10

D11

VD

HD

V1

V2

V3

V4

V5A

V5B

V6

V7A

V7B

V8

F10

C6

C7

G11

H11

H10

F6

V9

V10

V11

V12

V13

VDR_EN

TEST0

TEST1

TEST3

NC

F7

E10

K11

J5

J7

J8

V-Driver Output Enable pin.

DI

Test Input. Must be tied to VSS1 or VSS2.

Test Input. Must be tied to VDD1 or VDD2.

No Connect.

A11, E6, H9, J6, J9, J10, J11, K4, K7, L1, L6,

L9, L11, G2, G3

¹AI = analog input, AO = analog output, DI = digital input, DO = digital output, DIO = digital input/output, P = power, VO2 = Vertical Driver Output 2 level, VO3 =

Vertical Driver Output 3 level.

Rev. 0 | Page 9 of 88

AD9923A

TYPICAL PERFORMANCE CHARACTERISTICS

450

5

4

400

3.3V

350

3

3.0V

300

2

250

2.7V

1

200

150

100

50

0

–1

–2

–3

0

18

27

36

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

FREQUENCY (MHz)

Figure 5. Power vs. Sample Rate

Figure 7. Typical INL Performance

0.6

55

50

45

40

35

30

25

20

15

10

5

+6dB

0.4

0.2

+3dB

–3dB

0

–0.2

–0.4

–0.6

0dB

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

0

100 200 300 400 500 600 700 800 900 1000

GAIN CODE

Figure 6. Typical DNL Performance

Figure 8. Output Noise vs. VGA Gain

Rev. 0 | Page 10 of 88

AD9923A

EQUIVALENT CIRCUITS

HVDD OR RGVDD

RG, HL,

H1 TO H4

AVDD

R

THREE-STATE

OUTPUT

AVSS

HVSS OR RGVSS

Figure 12. HL, H1 to H4, and RG Drivers

Figure 9. CCDIN, CCDGND

DVDD

DRVDD

VDVDD

3.5kΩ

DATA

VDR_EN

R

THREE-STATE

D[0:11]

VDVSS

Figure 13. VDR_EN Input

DVSS

Figure 10. Digital Data Outputs

DVDD

DRVSS

330Ω

DVSS

Figure 11. Digital Inputs

Rev. 0 | Page 11 of 88

AD9923A

TERMINOLOGY

Differential Nonlinearity (DNL)

Total Output Noise

An ideal ADC exhibits code transitions that are exactly 1 LSB

apart. DNL is the deviation from this ideal value. Therefore,

every code must have a finite width. No missing codes guaranteed

to 12-bit resolution indicates that all 4096 codes, respectively,

must be present over all operating conditions.

The rms output noise is measured using histogram techniques.

The standard deviation of the ADC output codes is calculated

in LSB, and represents the rms noise level of the total signal

chain at the specified gain setting. The output noise can be

converted to an equivalent voltage, using the relationship

1 LSB = (ADC full scale/2ⁿcodes)

Integral Nonlinearity (INL)

The deviation of each code measured from a true straight line

between the zero and full-scale values. The point used as zero

scale occurs 0.5 LSB before the first code transition. Positive full

scale is defined as a level 1.5 LSB beyond the last code transition.

The deviation is measured from the middle of each output code

to the true straight line.

where n is the bit resolution of the ADC and 1 LSB is 0.488 mV.

Power Supply Rejection (PSR)

The PSR is measured with a step change applied to the supply

pins. The PSR specification is calculated from the change in the

data outputs for a given step change in the supply voltage.

Peak Nonlinearity

Peak nonlinearity, a full signal chain specification, refers to the

peak deviation of the AD9923A output from a true straight line.

The point used as zero scale occurs 0.5 LSB before the first code

transition. Positive full scale is defined as a level 1.5 LSB beyond

the last code transition. The deviation is measured from the

middle of each output code to the true straight line. The error is

expressed as a percentage of the 2 V ADC full-scale signal. The

input signal is always appropriately gained up to fill the full-scale

range of the ADC.

Rev. 0 | Page 12 of 88

AD9923A

THEORY OF OPERATION

Figure 14 shows the typical system block diagram for the

AD9923A in master mode. The CCD output is processed by

the AD9923A AFE circuitry, which consists of a CDS, VGA,

black level clamp, and ADC. The digitized pixel information is

sent to the digital image processor chip that performs the post-

processing and compression. To operate the CCD, CCD timing

parameters are programmed into the AD9923A from the system

microprocessor through the 3-wire serial interface. The AD9923A

generates the CCD horizontal, vertical, and the internal AFE

clocks from the system Master Clock CLI. The CLI is provided

by the image processor or external crystal. External synchroniza-

tion is provided by a sync pulse from the microprocessor, which

resets internal counters and resyncs the VD and HD outputs.

Figure 15 and Figure 16 show the maximum horizontal and

vertical counter dimensions for the AD9923A. Internal hori-

zontal and vertical clocking is controlled by these counters to

specify line and pixel locations. The maximum HD length is

8192 pixels per line, and the maximum VD length is 4096 lines

per field.

V1 TO V13, SUBCK

HL, H1 TO H4, RG, VSUB

D[0:11]

CCDIN

DIGITAL

DCLK

HD, VD

CLI

CCD

AD9923A

AFETG +

V-DRIVER

IMAGE

PROCESSING

ASIC

MSHUT

STROBE

SERIAL

INTERFACE

Alternatively, the AD9923A can be operated in slave mode, in

which the VD and HD are provided externally from the image

processor. In this mode, the AD9923A timing is synchronized

with VD and HD.

MICRO-

PROCESSOR

SYNC

Figure 14. Typical System Block Diagram, Master Mode

MAXIMUM

The H-drivers for HL, H1 to H4, and RG are included in the

AD9923A, allowing these clocks to be directly connected to the

CCD. An H-driver voltage, HVDD, of up to 3.3 V is supported.

An external V-driver is required for the vertical transfer clocks,

the sensor gate pulses, and the substrate clock.

COUNTER

DIMENSIONS

13-BIT HORIZONTAL = 8192 PIXELS MAX

12-BIT VERTICAL = 4096 LINES MAX

The AD9923A also includes programmable MSHUT and

STROBE outputs that can be used to trigger mechanical shutter

and strobe (flash) circuitry.

Figure 15. Vertical and Horizontal Counters

MAX VD LENGTH IS 4096 LINES

VD

MAX HD LENGTH IS 8192 PIXELS

HD

CLI

Figure 16. Maximum VD/HD Dimensions

Rev. 0 | Page 13 of 88

AD9923A

The edge location registers are six bits wide, but there are only

48 valid edge locations available. Therefore, the register values

are mapped into four quadrants, each of which contains 12 edge

locations. Table 10 shows the correct register values for the

corresponding edge locations. Figure 20 shows the default

timing locations for high speed clock signals.

PRECISION TIMING

HIGH SPEED TIMING GENERATION

The AD9923A generates high speed timing signals using the

flexible Precision Timing core. This core is the foundation for

generating the timing used for both the CCD and the AFE. It

consists of the reset gate (RG), horizontal drivers (H1 to H4 and

HL), and sample clocks (SHP and SHD). A unique architecture

makes it routine for the system designer to optimize image

quality by providing precise control over the horizontal CCD

readout and the AFE-correlated double sampling.

H-Driver and RG Outputs

In addition to the programmable timing positions, the

AD9923A features on-chip output drivers for the RG and H1 to

H4 outputs. These drivers are powerful enough to directly drive

the CCD inputs. The H-driver and RG current can be adjusted for

optimum rise/fall times in a particular load by using the H1 to

H4, HL, and RGDRV registers (Address 0x36). The 3-bit drive

setting for each output can be adjusted in 4.1 mA increments,

with the minimum setting of 0 equal to 0 mA or three-state, and

the maximum setting of 7 equal to 30.1 mA.

The high speed timing of the AD9923A operates the same in

master and slave modes. For more information on synchroniza-

tion and pipeline delays, see the Power-Up and Synchronization

in Slave Mode section.

Timing Resolution

The Precision Timing core uses a 1× master clock input (CLI) as

a reference. The frequency of this clock should match the CCD

pixel clock frequency. Figure 17 illustrates how the internal

timing core divides the master clock period into 48 steps, or

edge positions. Using a 36 MHz CLI frequency, the edge

resolution of the Precision Timing core is approximately 0.6 ns.

If a 1× system clock is not available, a 2× reference clock can be

used by programming the CLIDIVIDE register (Address 0x30).

The AD9923A then internally divides the CLI frequency by 2.

As shown in Figure 18, Figure 19, and Figure 20, the H2 and H4

outputs are inverses of H1 and H3 outputs, respectively. The

H1/H2 crossover voltage is approximately 50% of the output

swing. The crossover voltage is not programmable.

Digital Data Outputs

The AD9923A data output and DCLK phase are programmable

using the DOUTPHASE register (Address 0x38, Bits[5:0]). Any

edge from 0 to 47 can be programmed, as shown in Figure 21.

Normally, the DOUT and DCLK signals track in phase, based

on the DOUTPHASE register contents. The DCLK output

phase can also be held fixed with respect to the data outputs by

setting the DCLKMODE register to high (Address 0x38, Bit[8]).

In this mode, the DCLK output remains at a fixed phase equal

to a delayed version of CLI, and the data output phase remains

programmable. For more detail, see the Analog Front End

Description/Operation section.

The AD9923A includes a master clock output (CLO) which is

the inverse of CLI. This output is intended to be used as a

crystal driver. A crystal can be placed between the CLI and

CLO pins to generate the master clock for the AD9923A. For

more information on using a crystal, see Figure 80.

High Speed Clock Programmability

Figure 18 shows how the RG, HL, H1 to H4, SHP, and SHD

high speed clocks are generated. The RG pulse has programmable

rising and falling edges and can be inverted using the polarity

control. The HL, H1, and H3 horizontal clocks have program-

mable rising and falling edges and polarity control. The H2 and

H4 clocks are inverses of the H1 and H3 clocks, respectively.

Table 9 summarizes the high speed timing registers and their

parameters. Figure 19 shows the typical 2-phase, H-clock

operation, in which H3 and H4 are programmed for the same

edge location as H1 and H2.

There is a fixed output delay from the DCLK rising edge to the

DOUT transition, called t_OD. This delay can be programmed to

four values between 0 ns and 12 ns, using the DOUTDELAY

register (Address 0x38, Bits[10:9]). The default value is 8 ns.

The pipeline delay through the AD9923A is shown in Figure 22.

After the CCD input is sampled by SHD, there is a 16-cycle

delay before the data is available.

Table 9. Timing Core Register Parameters for HL, H1 to H4, RG, SHP/SHD

Length

(Bits)

Parameter

Polarity

Positive Edge

Negative Edge

Sampling

Location

Range

Description

1

6

High/low

Polarity control for HL, H1, H3, and RG (0 = no inversion, 1 = inversion)

Positive edge location for HL, H1, H3, and RG (H2/H4 are inverses of H1/H3, respectively)

Negative edge location for HL, H1, H3, and RG (H2/H4 are inverses of H1/H3, respectively)

Sampling location for internal SHP and SHD signals

0 to 47 edge location

Drive Strength

3

0 to 7 current steps

Drive current for HL, H1 to H4, and RG outputs (4.1 mA per step)

Rev. 0 | Page 14 of 88

AD9923A

Table 10. Precision Timing Edge Locations

Quadrant

Edge Location (Decimal)

Register Value (Decimal)

0 to 11

16 to 27

32 to 43

48 to 59

Register Value (Binary)

I

II

III

IV

0 to 11

000000 to 001011

010000 to 011011

100000 to 101011

110000 to 111011

12 to 23

24 to 35

36 to 47

POSITION

P[0]

P[12]

P[24]

P[36]

P[48] = P[0]

CLI

t_CLIDLY

1 PIXEL

PERIOD

NOTES

1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCK.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (t = 6ns TYP).

CLIDLY

Figure 17. High Speed Clock Resolution from CLI Master Clock Input

3

4

CCD

SIGNAL

1

5

7

2

RG

HL

6

8

H1

H2

9

10

H3

H4

PROGRAMMABLE CLOCK POSITIONS:

1

RG RISING EDGE.

RG FALLING EDGE.

SHP SAMPLE LOCATION.

SHD SAMPLE LOCATION.

HL RISING EDGE POSITION.

HL FALLING EDGE POSITION.

H1 RISING EDGE POSITION.

H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1).

2

3

4

5

6

7

8

9

H3 RISING EDGE POSITION.

H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3).

10

Figure 18. High Speed Clock Programmable Locations

Rev. 0 | Page 15 of 88

AD9923A

CCD

SIGNAL

RG

HL/H1/H3

H2/H4

NOTES

1. USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING.

Figure 19. 2-Phase H-Clock Operation

POSITION

P[0]

P[12]

P[24]

P[36]

P[48] = P[0]

PIXEL

PERIOD

RGr[0]

Hr[0]

RGf[12]

RG

Hf[24]

HL/H1/H3

H2/H4

SHP[24]

t_S1

CCD

SIGNAL

SHD[48]

NOTES

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.

2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN.

Figure 20. High Speed Timing Default Locations

Rev. 0 | Page 16 of 88

AD9923A

P[36]

P[0]

P[48] = P[0]

P[12]

P[24]

PIXEL

PERIOD

DCLK

t_OD

DOUT

NOTES

1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.

3. OUTPUT DELAY (t_OD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.

Figure 21. Digital Output Phase Adjustment

CLI

t_CLIDLY

N+12 N+13 N+14 N+15 N+16 N+17

N

N+1

N+4

N+5

N+6

N+7

N+8

N+9 N+10 N+11

N+2

N+3

CCDIN

SAMPLE PIXEL N

SHD

(INTERNAL)

ADC DOUT

(INTERNAL)

N

N–4

N–3

N–2

N–1

N–15 N–14 N–13 N–12 N–11 N–10

t_DOUTINH

N–9

N–8

N–7

N–6

N–5

N–17 N–16

DCLK

PIPELINE LATENCY = 16 CYCLES

N–12 N–11 N–10 N–9 N–8 N–7

N

N–4

N–3

N–2

N–1

D[0:11]

N–17 N–16

N–6

N–5

N–14 N–13

N–15

NOTES

1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.

2. HIGHER VALUES OF SHD AND/OR DOUTPHASE SHIFT DOUT TRANSITION TO THE RIGHT WITH RESPECT TO CLI LOCATION.

3. INHIBIT TIME FOR DOUT PHASE IS DEFINED BYt_DOUTINH, WHICH IS EQUAL TO SHDLOC PLUS 11 EDGES. IT IS RECOMMENDED THAT

THE 12 EDGE LOCATIONS FOLLOWING SHDLOC NOT BE USED FOR THE DOUTPHASE LOCATION.

4. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE THE SHPLOC EDGE OR THE 11 EDGES FOLLOWING SHPLOC.

5. RECOMMENDED VALUE FOR t_OD(DOUT DLY) IS 4ns.

6. THE DOUT LATCH CAN BE BYPASSED USING REGISTER 0x01, BIT [1] = 1 SO THAT THE ADC DATA OUTPUTS APPEAR DIRECTLY AT

THE DATA OUTPUT PINS. THIS CONFIGURATION IS RECOMMENDED IF THE ADJUSTABLE DOUT PHASE IS NOT REQUIRED.

Figure 22. Digital Data Output Pipeline Delay

Rev. 0 | Page 17 of 88

AD9923A

CLPOB and PBLK Masking Area

HORIZONTAL CLAMPING AND BLANKING

The AD9923A allows the CLPOB and/or PBLK signals to be

disabled during certain lines in the field without changing the

existing CLPOB and/or PBLK pattern settings.

The AD9923A horizontal clamping and blanking pulses are

fully programmable to suit a variety of applications. Individual

controls are provided for CLPOB, PBLK, and HBLK during

different regions of each field. This allows dark pixel clamping

and blanking patterns to be changed at each stage of the readout

to accommodate different image transfer timing and high speed

line shifts.

To use CLPOB masking, the CLPMASKSTART and CLPMASKEND

registers are programmed to specify the starting and ending lines

in the field where the CLPOB patterns are ignored. There are three

sets of CLPMASKSTART and CLPMASKEND registers,

allowing up to three CLPOB masking areas to be created.

Individual CLPOB and PBLK Patterns

The AFE horizontal timing consists of CLPOB and PBLK, as

shown in Figure 23. These two signals are independently

programmed using the registers in Table 11. SPOL is the start

polarity for the signal, and TOG1 and TOG2 are the first and

second toggle positions of the pulse. Both signals are active low

and should be programmed accordingly.

CLPOB masking registers are not specific to a given V-sequence;

they are active for any existing field of timing. To disable the

CLPOB masking feature, set these registers to the maximum

value, 0xFFF (default value).

To use PBLK masking, the PBLKMASKSTART and

PBLKMASKEND registers are programmed to specify the

starting and ending lines in the field where the PBLK patterns

are ignored. There are three sets of PBLKMASKSTART and

PBLKMASKEND registers, allowing the creation of up to three

PBLK masking areas.

A separate pattern for CLPOB and PBLK can be programmed

for each V-sequence. As described in the Vertical Timing

Generation section, several V-sequences can be created, each

containing a unique pulse pattern for CLPOB and PBLK.

Figure 46 shows how the sequence change positions divide the

readout field into regions. A different V-sequence can be

assigned to each region, allowing the CLPOB and PBLK signals

to change with each change in the vertical timing. Unused CLPOB

and PBLK toggle positions should be set to 8191.

PBLK masking registers are not specific to a given V-sequence;

they are active for any existing field of timing. To disable the

PBLK masking feature, set these registers to the maximum

value, 0xFFF (default value).

Table 11. CLPOB and PBLK Pattern Registers

Register

Length (Bits) Range

Description

CLPOBPOL

PBLKPOL

1

High/low

Starting polarity of CLPOB for each V-sequence

Starting polarity of PBLK for each V-sequence

CLPOBTOG1

CLPOBTOG2

PBLKTOG1

PBLKBTOG2

CLPMASKSTART

CLPMASKEND

13

12

0 to 8191 pixel location First CLPOB toggle position within the line for each V-sequence

0 to 8191 pixel location Second CLPOB toggle position within the line for each V-sequence

0 to 8191 pixel location First PBLK toggle position within the line for each V-sequence

0 to 8191 pixel location Second PBLK toggle position within the line for each V-sequence

0 to 4095 line location

CLPOB masking area—starting line within the field (maximum of three areas)

CLPOB masking area—ending line within the field (maximum of three areas)

PBLK masking area—starting line within the field (maximum of three areas)

PBLK masking area—ending line within the field (maximum of three areas)

PBLKMASKSTART 12

PBLKMASKEND 12

HD

2

3

CLPOB

PBLK

1

ACTIVE

PROGRAMMABLE SETTINGS:

1

2

3

START POLARITY (CLAMP AND BLANK REGIONS ARE ACTIVE LOW).

FIRST TOGGLE POSITION.

SECOND TOGGLE POSITION.

Figure 23. Clamp and Preblank Pulse Placement

Rev. 0 | Page 18 of 88

AD9923A

NO CLPOB SIGNAL

FOR LINES 6 TO 8

NO CLPOB SIGNAL

FOR LINE 600

VD

0

1

2

597 598

HD

CLPOB

CLPMASKSTART1 = 6

CLPMASKEND1 = 8

CLPMASKSTART2 = CLPMASKEND2 = 600

Figure 24. CLPOB Masking Example

NO PBLK SIGNAL

FOR LINES 6 TO 8

NO PBLK SIGNAL

FOR LINE 703

VD

0

1

2

700 701

HD

PBLK

PBLKMASKSTART1 = 6 PBLKMASKEND1 = 8

PBLKMASKSTART2 = PBLKMASKEND2 = 703

Figure 25. PBLK Masking Example

Rev. 0 | Page 19 of 88

AD9923A

Generating Special HBLK Patterns

Individual HBLK Patterns

There are six toggle positions available for HBLK. Normally,

only two of the toggle positions are used to generate the

standard HBLK interval. However, additional toggle positions

can be used to generate special HBLK patterns, as shown in

Figure 28. The pattern in this example uses all six toggle

positions to generate two extra groups of pulses during the

HBLK interval. By changing the toggle positions, different

patterns can be created.

The HBLK programmable timing shown in Figure 26 is similar

to CLPOB and PBLK; however, there is no start polarity control.

Only the toggle positions are used to designate the start and end

positions of the blanking period. Additionally, there is a polarity

control register, HBLKMASK, that designates the polarity of the

horizontal clock signals during the blanking period. Setting

HBLKMASK high sets H1 = H3 = high and H2 = H4 = low

during blanking, as shown in Figure 27. As with CLPOB and

PBLK registers, HBLK registers are available in each V-sequence,

allowing different blanking signals to be used with different

vertical timing sequences.

Table 12. HBLK Pattern Registers

Length

(Bits)

Register

HBLKMASK

HBLKALT

Range

Description

1

3

High/low

Masking polarity for H1, H3, HL (0 = mask low, 1 = mask high)

Enables different odd/even alternation of HBLK toggle positions

0 to 7 alternation

modes

0: disable alternation (HBLKTOGE1 to HBLKTOGE6 registers are used for each line)

1: TOGE1 and TOGE2 odd lines, TOGE3 to TOGE6 even lines

2: TOGE1 and TOGE2 even lines, TOGE3 to TOGE6 odd lines

3: TOGE1 to TOGE6 even lines, TOGO1 to TOGE6 odd lines (FREEZE/RESUME not

available)

4 to 7: HBLKSTART, HBLKEND, HBLKLEN, and HBLKREP registers are used for each line

HBLK first toggle position (for even lines only when HBLKALT = 3)

HBLKTOGE1 13

HBLKTOGE2 13

HBLKTOGE3 13

HBLKTOGE4 13

HBLKTOGE5 13

HBLKTOGE6 13

0 to 8191 pixel

location

0 to 8191 pixel

location

HBLK second toggle position (for even lines only when HBLKALT = 3)

HBLK third toggle position (for even lines only when HBLKALT = 3)

HBLK fourth toggle position (for even lines only when HBLKALT = 3)

Fifth toggle position, even lines (HBLKSTART when HBLKALT = 4 to 7)

Sixth toggle position, even lines (HBLKEND when HBLKALT = 4 to 7)

0 to 8191 pixel

location

0 to 8191 pixel

location

0 to 8191 pixel

location

0 to 8191 pixel

location

HBLKLEN

HBLKREP

13

8

0 to 8191 pixels

HBLK pattern length, only used when HBLKALT = 4 to 7

0 to 255 repetitions

Number of HBLK pattern repetitions, only used when HBLKALT = 4 to 7

First toggle position for odd lines when HBLKALT = 3 (usually VREPA_3)

HBLKTOGO1 13

HBLKTOGO2 13

HBLKTOGO3 13

HBLKTOGO4 13

HBLKTOGO5 13

HBLKTOGO6 13

0 to 8191 pixel

location

0 to 8191 pixel

location

Second toggle position for odd lines when HBLKALT = 3 (usually VREPA_4)

Third toggle position for odd lines when HBLKALT = 3 (usually FREEZE1)

Fourth toggle position for odd lines when HBLKALT = 3 (usually RESUME1)

Fifth toggle position for odd lines when HBLKALT = 3 (usually FREEZE2)

Sixth toggle position for odd lines when HBLKALT = 3 (usually RESUME2)

0 to 8191 pixel

location

0 to 8191 pixel

location

0 to 8191 pixel

location

0 to 8191 pixel

location

Rev. 0 | Page 20 of 88

AD9923A

HD

HBLKTOGE1

HBLKTOGE2

BLANK

HBLK

BASIC HBLK PULSE IS GENERATED USING HBLKTOGE1 AND HBLKTOGE2 REGISTERS (HBLKALT = 0)

Figure 26. Typical Horizontal Blanking (HBLK) Pulse Placement

...

HD

HBLK

HL/H1/H3

THE POLARITY OF HL/H1/H3 DURING BLANKING ARE INDEPENDENTLY PROGRAMMABLE

(H2/H4 IS OPPOSITE POLARITY OF H1/H3)

H1/H3

H2/H4

Figure 27. HBLK Masking Polarity Control

HBLKTOGE2

HBLKTOGE4

HBLKTOGE3

HBLKTOGE6

HBLKTOGE5

HBLKTOGE1

HBLK

HL/H1/H3

H2/H4

SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS (HBLKALT = 0)

Figure 28. Using Multiple Toggle Positions for HBLK (HBLKALT = 0)

Rev. 0 | Page 21 of 88

AD9923A

lines. There are also six additional toggle positions, HBLKTOGO1

to HBLKTOGE6, for odd lines. These registers are normally

used for VPAT Group A, VPAT Group B, and freeze/resume

functions, but when HBLKALT = 3, these registers become the

odd line toggle positions for HBLK.

Generating HBLK Line Alternation

The AD9923A can alternate different HBLK toggle positions on

odd and even lines. This feature can be used in conjunction with

V-pattern odd/even alternation, or on its own. When 1 is written

to the HBLKALT register, HBLKTOGE1 and HBLKTOGE2 are

used on odd lines, and HBLKTOGE3 to HBLKTOGE6 are used

on even lines. Writing 2 to the HBLKALT register gives the oppo-

site result: HBLKTOGE1 and HBLKTOGE2 are used on even

lines, and HBLKTOGE3 to HBLKTOGE6 are used on odd lines.

When 3 is written to the HBLKALT register, all six even toggle

positions, HBLKTOGE1 to HBLKTOGE6, are used on even

Another HBLK feature is enabled by writing 4, 5, 6, or 7 to

HBLKALT. In these modes, the HBLK pattern is generated using

a different set of registers—HBLKSTART, HBLKEND, HBLKLEN,

and HBLKREP—along with four toggle positions. This allows

for multiple repeats of the HBLK signal, as shown in Figure 32.

ODD LINE

HD

EVEN LINE

HBLKTOGE4

HBLKTOGE3

HBLKTOGE6

HBLKTOGE5

HBLKTOGE2

HBLKTOGE1

HBLK

HL/H1/H3

H2/H4

ALTERNATING H-BLANK PATTERN USING HBLKALT = 1 MODE

Figure 29. HBLK Odd/Even Alternation Using HBLKALT = 1

ODD LINE

HBLKTOGE4

HBLKTOGE3

EVEN LINE

HD

HBLKTOGE6

HBLKTOGE5

HBLKTOGE2

HBLKTOGE1

HBLK

HL/H1/H3

H2/H4

ALTERNATING H-BLANK PATTERN USING HBLKALT = 2 MODE

Figure 30. HBLK Odd/Even Alternation Using HBLKALT = 2

Rev. 0 | Page 22 of 88

AD9923A

ODD LINE

HBLKTOGO2

HBLKTOGO1

EVEN LINE

HBLKTOGE2

HBLKTOGE1

HD

HBLKTOGO4

HBLKTOGO3

HBLKTOGE4

HBLKTOGE3

HBLK

HL/H1/H3

H2/H4

ALTERNATING H-BLANK PATTERN USING HBLKALT = 3 MODE.

(FREEZE/RESUME FUNCTION NOT AVAILABLE IN THIS MODE.)

Figure 31. HBLK Odd/Even Alternation Using HBLKALT = 3

HBLKTOGE2

HBLKTOGE1 HBLKTOGE3

HBLKTOGE4

HBLKSTART

HBLKEND

HBLK

HBLKLEN

HBLKREP = 3

HL/H1/H3

H2/H4

HBLKREP NUMBER 1

HBLKREP NUMBER 2

HBLKREP NUMBER 3

H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS

Figure 32. HBLK Repeating Pattern Using HBLKALT = 4 to 7

Rev. 0 | Page 23 of 88

AD9923A

be used, such as adding a separate sequence to clamp during the

entire line of OB pixels. This requires configuring a separate

V-sequence for reading the OB lines.

Increasing H-Clock Width During HBLK

The AD9923A allows the H1 to H4 pulse width to be increased

during the HBLK interval. The H-clock pulse width can in-

crease by reducing the H-clock frequency (see Table 13).

The CLPMASKSTART and CLPMASKEND registers can be used

to disable the CLPOB on a few lines without affecting the setup of

the clamp sequences.

The HBLKWIDTH register (Register 0x35, Bits[6:4]) is a 3-bit

register that allows the H-clock frequency to be reduced by 1/2,

1/4, 1/6, 1/8, 1/10, 1/12, or 1/14. The reduced frequency only

occurs for H1 to H4 pulses that are located within the HBLK area.

Horizontal Timing Sequence Example

2 VERTICAL

OB LINES

Figure 33 shows an example of a CCD layout. The horizontal

register contains 28 dummy pixels that occur on each line

clocked from the CCD. In the vertical direction, there are 10

optical black (OB) lines at the front of the readout and two at

the back of the readout. The horizontal direction has four OB

pixels in the front and 48 OB pixels in the back.

V

EFFECTIVE IMAGE AREA

10 VERTICAL

OB LINES

Figure 34 shows the basic sequence layout to use during the

effective pixel readout. The 48 OB pixels at the end of each line

are used for CLPOB signals. PBLK is optional and it is often

used to blank the digital outputs during the noneffective CCD

pixels. HBLK is used during the vertical shift interval.

H

48 OB PIXELS

4 OB PIXELS

HORIZONTAL CCD REGISTER

28 DUMMY PIXELS

The HBLK, CLPOB, and PBLK parameters are programmed in

the V-sequence registers. More elaborate clamping schemes can

Figure 33. CCD Configuration Example

Table 13. HBLK Width Register

Register

Length (Bits)

Range

Description

HBLKWIDTH

3

1× to 1/14× pixel rate

Controls H1 to H4 width during HBLK as a fraction of pixel rate

0: same frequency as the pixel rate

1: 1/2 pixel frequency, that is, doubles the H1 to H4 pulse width

2: 1/4 pixel frequency

3: 1/6 pixel frequency

4: 1/8 pixel frequency

5: 1/10 pixel frequency

6: 1/12 pixel frequency

7: 1/14 pixel frequency

OPTICAL BLACK

HD

CCDIN

VERTICAL SHIFT

DUMMY

EFFECTIVE PIXELS

OPTICAL BLACK

VERT. SHIFT

SHP

SHD

HL/H1/H3

H2/H4

HBLK

PBLK

CLPOB

Figure 34. Horizontal Sequence Example

Rev. 0 | Page 24 of 88

AD9923A

3. Construct the readout for an entire field by dividing the field

into regions and assigning a sequence to each region. Each

field can contain up to nine regions to accommodate different

steps, such as high speed line shifts and unique vertical line

transfers, of the readout. The total number of V-patterns,

V-sequences, and fields are programmable and limited by the

number of registers. High speed line shifts and unique vertical

transfers are examples of the different steps required for

readout.

VERTICAL TIMING GENERATION

The AD9923A provides a very flexible solution for generating

vertical CCD timing; it can support multiple CCDs and different

system architectures. The 13-phase vertical transfer clocks, XV1 to

XV13, are used to shift lines of pixels into the horizontal output

register of the CCD. The AD9923A allows these outputs to be

individually programmed into various readout configurations,

using a four-step process as shown in Figure 35.

1. Use the vertical pattern group registers to create the individual

pulse patterns for XV1 to XV13.

4. Use the MODE register to combine fields in any order for

various readout configurations.

2. Use the V-pattern groups to build the sequences and add more

information.

CREATE THE VERTICAL PATTERN GROUPS,

UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT.

BUILD THE V-SEQUENCES BY ADDING START POLARITY,

LINE START POSITION, NUMBER OF REPEATS, ALTERNATION,

GROUP A/B INFORMATION, AND HBLK/CLPOB PULSES.

1

2

XV1

XV2

XV1

XV2

XV3

VPAT 0

V-SEQUENCE 0

(VPAT0, 1 REP)

XV11

XV12

XV11

XV12

XV1

XV2

XV1

XV2

XV3

V-SEQUENCE 1

(VPAT1, 2 REP)

XV3

VPAT 1

XV11

XV12

XV11

XV12

XV1

XV2

XV3

V-SEQUENCE 2

(VPAT1, N REP)

XV11

XV12

USE THE MODE REGISTER TO CONTROL WHICH FIELDS

ARE USED, AND IN WHAT ORDER (MAXIMUM OF SEVEN

FIELDS MAY BE COMBINED IN ANY ORDER).

BUILD EACH FIELD BY DIVIDING IT INTO DIFFERENT

REGIONS AND ASSIGNING A V-SEQUENCE TO EACH

(MAXIMUM OF NINE REGIONS IN EACH FIELD).

3

4

FIELD 0

FIELD 1

FIELD 4

FIELD 2

FIELD 0

REGION 0: USE V-SEQUENCE 2

REGION 1: USE V-SEQUENCE 0

REGION 2: USE V-SEQUENCE 3

FIELD 3

FIELD 5

REGION 3: USE V-SEQUENCE 0

FIELD 2

FIELD 1

FIELD 4

REGION 4: USE V-SEQUENCE 2

FIELD 1

FIELD 2

Figure 35. Summary of Vertical Timing Generation

Rev. 0 | Page 25 of 88

AD9923A

start polarity for each signal, VSTART specifies the start

position of the VPAT group, and VLEN designates the total

length of the VPAT group, which determines the number of

pixels between each pattern repetition, if repetitions are used.

Vertical Pattern (VPAT) Groups

A vertical pattern (VPAT) group defines the individual pulse

pattern for each XV1 to XV13 output signal. Table 14 summarizes

the registers that are available for generating each VPAT group.

The first, second, third, fourth, fifth, and sixth toggle positions

(XVTOG1, XVTOG2, XVTOG3, XVTOG4, XVTOG5,

XVTOG6) are the pixel locations where the pulse transitions. All

toggle positions are 13-bit values that can be placed anywhere in

the horizontal line.

To achieve the best possible noise performance, ensure that

VSTART + VLEN < the end of the H-blank region.

Toggle positions programmed to either Pixel 0 or Pixel 8191 are

ignored. The toggle positions of unused XV-channels must be

programmed to either Pixel 0 or Pixel 8191. This prevents unpre-

dictable behavior because the default values of the V-pattern

group registers are unknown.

More registers are included in the vertical sequence registers to

specify the output pulses: XV1POL to XV13POL specifies the

Table 14. Vertical Pattern Group Registers

Register

XVTOG1

XVTOG2

XVTOG3

XVTOG4

XVTOG5

XVTOG6

Length (Bits)

Range

Description

13

0 to 8191 pixel location

First toggle position within line for each XV1 to XV12 output

Second toggle position

Third toggle position

Fourth toggle position

Fifth toggle position

Sixth toggle position

START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS.

HD

4

XV1

XV2

1

2

3

2

3

1

XV12

2

3

PROGRAMMABLE SETTINGS:

1

START POLARITY (LOCATED IN V-SEQUENCE REGISTERS).

FIRST TOGGLE POSITION.

SECOND TOGGLE POSITION (A TOTAL OF SIX TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS).

TOTAL PATTERN LENGTH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGISTERS).

2

3

4

Figure 36. Vertical Pattern Group Programmability

Rev. 0 | Page 26 of 88

AD9923A

Generating Line Alternation for V-Sequences and HBLK

Vertical Sequences (VSEQ)

section). The VSTARTA and VSTARTB registers specify the pixel

location where the V-pattern group starts. The VMASK register is

used in conjunction with the FREEZE/RESUME registers to enable

optional masking of the XV outputs. Either or both of the

FREEZE1/RESUME1 and FREEZE2/RESUME2 registers can be

enabled.

A vertical sequence (VSEQ) is created by selecting one of the

V-pattern groups and adding repeats, a start position, and

horizontal clamping and blanking information. Each VSEQ is

programmed using the registers shown in Table 15. Figure 37

shows how each register is used to generate a V-sequence.

The VPATSELA and VPATSELB registers select the V-pattern

group that is used in a given V-sequence. Having two groups

available allows each vertical output to be mapped to a different

V-pattern group. The selected V-pattern group can have

repetitions added for high speed line shifts or line binning by

using the VREP registers for odd and even lines. Generally, the

same number of repetitions is programmed into both registers.

If a different number of repetitions is required on odd and even

lines, separate values can be used for each register (see the

The line length (in pixels) is programmable using the HDLEN

registers. Each V-sequence can have a different line length to

accommodate various image readout techniques. The maximum

number of pixels per line is 8192. Note that the last line of the

field can be programmed separately using the HDLAST register,

located in the field register (see Table 16).

1

HD

2

3

4

XV1 TO XV13

VREP 3

V-PATTERN GROUP

VREP 2

5

CLPOB

PBLK

6

HBLK

PROGRAMMABLE SETTINGS FOR EACH VERTICAL SEQUENCE:

1

START POSITION IN THE LINE OF SELECTED V-PATTERN GROUP.

2

HD LINE LENGTH.

3

V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP.

NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED).

START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS.

MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL.

4

5

6

Figure 37. V-Sequence Programmability

Rev. 0 | Page 27 of 88

AD9923A

1

Table 15. V-Sequence Registers

Length

(Bits)

Register

HOLD

Range

Description

1

2

On/off

Use in conjunction with VMASK. 1 = hold instead of FREEZE/RESUME.

VMASK

0 to 3 mask mode

Enables the masking of XV1 to XV13 outputs at the locations specified by

the FREEZE/RESUME registers.

0 = no mask.

1 = enable FREEZE1/RESUME1.

2 = enable FREEZE2/RESUME2.

3 = enable both FREEZE1/RESUME1 and FREEZE2/RESUME2.

HD line length in each V-sequence.

Start polarity for each XV1 to XV13 output.

HDLEN

13

1

0 to 8191 pixels

High/low

XV1POL to

XV13POL

GROUPSEL

12

1b for each XV output

Assigns each XV1 to XV13 output to either V-Pattern Group A or

V-Pattern Group B.

0 = assigns to VPATSELA.

1 = assigns to VPATSELB.

TWO_GROUP

VPATSELA

1

5

High/low

When high, all XV outputs combine Group A and Group B.

Selected V-pattern for Group A.

0 to 31 V-pattern number

VPATSELB

Selected V-pattern for Group B. If SPVTP_ENABLE = 1, VPATSELB is used

for second VTP inserted in SPVTP_ACTLINE.

VPATA_MODE

2

0 to 3 repetition mode

Selects alternation repetition mode for Group A only.

0 = disable alternation, use VREPA_1 for all lines.

1 = 2-line. Alternate VREPA_1 and VREPA_2 (same as odd/even).

2 = 3-line. Alternate VREPA_1, VREPA_2, and VREPA_3.

3 = 4-line. Alternate VREPA_1, VREPA_2, VREPA_3, and VREPA_4.

Start position for the selected V-Pattern Group A.

VSTARTA

VSTARTB

13

0 to 8191 pixel location

Start position for the selected V-Pattern Group B. If SPVTP_ENABLE = 1,

VSTARTB is used for start position of VPATSELB in SPVTP_ACTLINE.

VLENA

13

12

0 to 8191 pixels

0 to 4095 repeats

Length of selected V-Pattern Group A.

Length of selected V-Pattern Group B.

VLENB

VREPB_ODD

Number of repetitions for the V-Pattern Group B for odd lines.

If no alternation is required for Group B, set VREPB_ODD equal to

VREPB_EVEN.

VREPB_EVEN

12

0 to 4095 repeats

Number of repetitions for the V-Pattern Group B for even lines.

If no alternation is required for Group B, set VREPB_EVEN equal to

VREPB_ODD.

VREPA_1

12

13

12

1

0 to 4095 repeats

Number of repetitions for the V-Pattern Group A for first lines (odd).

Number of repetitions for the V-Pattern Group A for second lines (even).

Number of repetitions for the V-Pattern Group A for third lines.

Number of repetitions for the V-Pattern Group A for fourth lines.

Pixel location where the XV outputs freeze or hold (see VMASK).

Pixel location where the XV outputs resume operation (see VMASK).

Pixel location where the XV outputs freeze or hold (see VMASK).

Pixel location where the XV outputs resume operation (see VMASK).

Active line for second VTP insertion.

VREPA_2

0 to 4095 repeats

VREPA_3

0 to 4095 repeats

VREPA_4

0 to 4095 repeats

FREEZE1

0 to 8191 pixel location

0 to 4095 line location

High/low

RESUME1

FREEZE2

RESUME2

SPVTP_ACTLINE

SPVTP_ENABLE

When high, second VTP is inserted into SPVTP_ACTLINE.

¹See Table 11 and Table 12 for CLPOB, PBLK, and HBLK registers.

Rev. 0 | Page 28 of 88

AD9923A

If Group B flexibility is needed, the outputs set to 1 in the

Group A/Group B Selection

GROUPSEL register use the V-pattern group selected by the

VPATSELB register. For example, Figure 38 shows outputs

XV12 and XV13 using a separate V-Pattern Group B to perform

special CCD timing.

The AD9923A has the flexibility to use two V-pattern groups in

a vertical sequence. In general, all vertical outputs use the same

V-pattern group during a sequence, but some outputs can be

assigned to a different V-pattern group. This is useful during

certain CCD readout modes.

Another application of the Group A and Group B registers is to

combine two VPAT groups for more complex patterns. This is

achieved by setting the TWO_GROUP register to 1. Figure 39

shows an example of this timing. When TWO_GROUP = 1,

the Group A and Group B toggle positions are both used. In

addition, length, starting polarity, and number of repetitions

are all determined by the appropriate registers for Group A

when TWO_GROUP = 1. Figure 40 shows the more complex

operation of combining Group A and Group B with repetition.

The GROUPSEL register is used to select Group A or Group B

for each XV output (the LSB is XV1, the MSB is XV13). Setting

each bit to 0 selects Group A; setting each bit to 1 selects Group B.

If only a single V-pattern group is needed for the vertical

outputs, Group A is used by default (GROUPSEL = 0), and the

outputs use the V-pattern group specified by the VPATSELA

register.

HD

OPTIONAL HOLD AREA

FOR GROUP A

XV1 TO XV11 USE

V-PATTERN GROUP A

XV1

XV11

XV12, XV13 USE

V-PATTERN GROUP B

XV12

XV13

Figure 38. Using Separate Group A and Group B Patterns

HD

V-PATTERN GROUP A

V-PATTERN GROUP B

XV1

XV13

Figure 39. Combining Group A and Group B Patterns

HD

V-PATTERN GROUP A V-PATTERN GROUP B

XV1

XV13

GROUP A REP 1

GROUP A REP 2

GROUP A REP 3

Figure 40. Combining Group A and Group B Patterns, with Repetition

Rev. 0 | Page 29 of 88

AD9923A

registers. Group A can also support three-line and four-line

alternation by using the VREPA_3 and VREPA_4 registers.

Generating Line Alternation for V-Sequences and HBLK

During low resolution readout, some CCDs require a different

number of vertical clocks on alternate lines. The AD9923A can

support such CCDs by using different VREP registers. This

allows a different number of VPAT repetitions to be programmed

on odd and even lines.

Additionally, the HBLK signal can be alternated for odd and

even lines. When the HBLKALT = 1, the HBLKTOGE1 and

HBLKTOGE2 positions are used on odd lines, and the

HBLKTOGE3 to HBLKTOGE6 positions are used on even

lines. This allows the HBLK interval to be adjusted on odd

and even lines if needed.

Note that only the number of repeats is different in odd and

even lines, but the VPAT group remains the same. There are

separate controls for the assigned Group A and Group B patterns.

Both Group A and Group B can support odd and even line

alternation. Group A uses the VREPA_1 and VREPA_2 regis-

ters; Group B uses the VREPB_ODD and VREPB_EVEN

Figure 41 shows an example of simultaneous VPAT repetition

alternation and HBLK alternation. Both types of alternation can

be used separately.

HD

VREPA_1 = 2

VREPA_2 = 5

VREPA_1 = 2

(OR VREPB_ODD = 2)

(OR VREPB_EVEN = 5)

(OR VREPB_ODD = 2)

XV1

XV2

XV13

HBLKTOGE1

HBLKTOGE2

HBLKTOGE3

HBLKTOGE4

HBLKTOGE1

HBLKTOGE2

HBLK

NOTES

1. THE NUMBER OF REPEATS FOR V-PATTERN GROUP A OR GROUP B CAN BE ALTERNATED ON ODD AND EVEN LINES.

2. GROUP A ALSO SUPPORTS 3-LINE AND 4-LINE ALTERNATION USING THE ADDITIONAL VREPA_3 AND VREPA_4 REGISTERS.

3. THE HBLK TOGGLE POSITIONS CAN ALSO BE ALTERNATED BETWEEN ODD AND EVEN LINES TO GENERATE DIFFERENT HBLK PATTERNS

FOR ODD/EVEN LINES. SEE THE HORIZONTAL CLAMPING AND BLANKING SECTION FOR MORE INFORMATION ON HBLK.

Figure 41. Odd/Even Line Alternation of VPAT Repetitions and HBLK Toggle Positions

Rev. 0 | Page 30 of 88

AD9923A

which point the signals continue with any remaining toggle

positions.

Masking Using Freeze/Resume Registers

As shown in Figure 42 and Figure 43, the FREEZE/RESUME

registers are used to temporarily mask the XV outputs. The

pixel locations to start (FREEZE) and end (RESUME) the

masking create an area in which the vertical toggle positions are

ignored. At the pixel location specified in the FREEZE register,

the XV outputs are held static at their current dc state, high or

low. The XV outputs are held until the internal pixel counter

reaches the pixel location specified by the RESUME register, at

Two sets of FREEZE/RESUME registers are provided, allowing

the vertical outputs to be interrupted twice in the same line. The

FREEZE and RESUME positions are enabled using the VMASK

register.

It is not recommended to use FREEZE/RESUME at the same

time as the SWEEP function.

HD

XV1

NO MASKING AREA

XV13

Figure 42. Not Using FREEZE/RESUME

MASKING AREA

FOR GROUP A

HD

XV1

FREEZE

RESUME

XV13

NOTES

1. ALL TOGGLE POSITIONS WITHIN THE FREEZE-RESUME MASKING AREA ARE IGNORED. H-COUNTER CONTINUES TO COUNT DURING MASKING.

2. TWO SEPARATE MASKING AREAS ARE AVAILABLE FOR EACH GROUP A, USING FREEZE1/RESUME1 AND FREEZE2/RESUME2 REGISTERS.

Figure 43. Using FREEZE/RESUME

Rev. 0 | Page 31 of 88

AD9923A

because the XV outputs continue from where they stopped (as

opposed to having the pixel counter run continuously), with

any toggle positions that fall between the FREEZE and

RESUME locations being ignored. Signals assigned to Group B

are not affected by the hold area.

Hold Area Using FREEZE/RESUME Registers

The FREEZE/RESUME registers can also be used to create a

hold area, in which the XV outputs are temporarily held and

then later resume at the point where they were held. As shown

in Figure 44, this is different than using the VMASK register,

HD

HOLD AREA

FOR GROUP A

FREEZE

RESUME

XV1

XV11

XV12

XV13

NOTES

1. WHEN HOLD = 1 FOR ANY V-SEQUENCE, THE FREEZE AND RESUME REGISTERS ARE USED TO SPECIFY THE HOLD AREA FOR GROUP A.

2. ABOVE EXAMPLE: ALL XV-OUTPUTS ARE ASSIGNED TO GROUP A.

3. H-COUNTER FOR GROUP A (XV1 TO XV13) STOPS DURING HOLD AREA.

Figure 44. Hold Area for Group A

HD

XV1

HOLD AREA

FOR GROUP A

FREEZE

RESUME

XV11

XV12

XV13

NO HOLD

AREA FOR

GROUP B

NOTES

1. ABOVE EXAMPLES: XV12 AND XV13 ARE ASSIGNED TO GROUP B.

2. GROUP B DOES NOT USE HOLD AREA.

Figure 45. Group B Does Not Use Hold Area

Rev. 0 | Page 32 of 88

AD9923A

register specifies the number of pixels in the last line of the

Complete Field: Combining V-Sequences

field. HDLEN, VDLEN, HDLAST registers are ignored when

the part is in slave mode. The VPATSECOND register is used to

add a second V-pattern group to the XV1 to X12 outputs during

the sensor gate (VSG) line.

After the V-sequences are created, they are combined to create

different readout fields. A field consists of up to nine regions.

Within each region, a different V-sequence can be selected.

Figure 46 shows how the sequence change position (SCP)

registers designate the line boundary for each region and how

the VSEQSEL registers select the V-sequence for each region.

Registers to control the VSG outputs are also included in the

field registers. Table 16 summarizes the registers used to create

the different fields.

The SGMASK register is used to enable or disable each VSG

output. There are two bits for each VSG output to enable

separate masking during SGACTLINE1 and SGACTLINE2.

Setting a masking bit high disables, or masks, the output; setting it

low enables the output. The SGPATSEL register assigns one of the

eight SG patterns to each VSG output. Each SG pattern is created

separately using the SG pattern registers. The SGACTLINE1

register specifies which line in the field contains the VSG

outputs. The optional SGACTLINE2 register allows the same

VSG pulses to repeat on a different line, although separate

masking is available for SGACTLINE1 and SGACTLINE2.

The VSEQSEL registers, one for each region, select which

V-sequences are active during each region. The SWEEP

registers can enable the sweep mode during any region.

The MULTI registers are used to enable the multiplier mode

during any region. The SCP registers create the line boundaries

for each region. The VDLEN register specifies the total number

of lines in the field. The total number of pixels per line (HDLEN)

is specified in the V-sequence registers, and the HDLAST

Table 16. Field Registers

Length

(Bits)

Register

Range

Description

VSEQSEL

5

0 to 31 V-sequence

number

Selected V-sequence for each region in the field.

SWEEP

MULTI

SCP

VDLEN

HDLAST

1

12

13

High/low

Enables sweep mode for each region when set high.

Enables multiplier mode for each region when set high.

0 to 4095 line number Sequence change position (SCP) for each region.

0 to 4095 lines

0 to 8191 pixels

0 to 31 V-pattern

group number

Total number of lines in each field.

Length in pixels of the last HD line in each field.

Start position of the second V-pattern group applied during VSG line.

Selected V-pattern group for the second pattern applied during VSG line.

VSTARTSECOND 13

VPATSECOND

5

SGMASK

16

High/low, each VSG

Set high to mask each VSG output. Two bits for each VSG output: one for SGLINE1,

and one for SGLINE2.

[0] Masking for VSG1 on SGLINE1.

[1] Masking for VSG1 on SGLINE2.

[2] Masking for VSG2 on SGLINE1.

[3] Masking for VSG2 on SGLINE2.

[15] Masking for VSG8 on SGLINE1.

[16] Masking for VSG8 on SGLINE2.

SGPATSEL

24

0 to 7 pattern

number, each VSG

Selects the VSG pattern number for each VSG output. VSG1[2:0], VSG2[5:3],

VSG3[8:6], VSG4[11:9], VSG5[14:12], VSG6[17:15], VSG7[20:18], VSG8[23:21].

SGACTLINE1

SGACTLINE2

12

0 to 4095 line number Selects the line in the field where the VSG is active.

0 to 4095 line number Selects a second line in the field to repeat the VSG signals.

Rev. 0 | Page 33 of 88

AD9923A

SCP 0

SCP 1

SCP 2

SCP 3

SCP 4

SCP 5

SCP 8

VD

HD

REGION 0

REGION 1

REGION 2

REGION 3

REGION 4

REGION 8

XV1 TO XV13

VSG

VSEQSEL0

VSEQSEL1

SGACTLINE

VSEQSEL8

VSEQSEL2

VSEQSEL3

VSEQSEL4

FIELD SETTINGS:

1. SEQUENCE CHANGE POSITIONS (SCP1 TO SCP8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD.

2. VSEQSEL0 TO VSEQSEL8 SELECTS THE DESIRED V-SEQUENCE FOR EACH REGION.

3. SGLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD CONTAINS THE SENSOR-GATE PULSE(S).

Figure 46. Complete Field Is Divided into Regions

Second V-Pattern Group During VSG Active Line and

Special V-Pattern Insertion

Table 17. Special Second V-Pattern Insertion

Length

Register

(Bits)

Range

Description

Most CCDs require additional vertical timing during the sensor

gate line. The AD9923A can output a second V-pattern group

for XV1 to XV13 during the line when the VSG1 to VSG8

sensor gates are active. Figure 47 shows a typical VSG line,

which includes two sets of V-pattern groups for XV1 to XV13.

At the start of the VSG line, the V-pattern group is selected

using the appropriate VSEQSEL register. The second V-pattern

group, unique to the VSG line, is selected using the VPATSECOND

register, located in the field registers. The start position of the

second VPAT group uses the VSTARTSECOND register. For

more information, see Table 16.

SPXV_EN

1

0 or 1

0 = off, 1= enable special

second V-pattern insertion.

Active line for special

SPXV_ACT 12

Line 0 to

Line 4095

0 to 31

V-pattern

number

0 to 8191

pixel

location

second V-pattern insertion.

VPATSELB

VSTARTB

5

Selected V-pattern for

special second V-pattern

insertion if SPXV_EN = 1.

Start position for selected

V-pattern for special

second V-pattern

13

insertion if SPXV_EN = 1.

In addition to inserting a second V-pattern into the VSG line,

the AD9923A can insert a second V-pattern into any other

single line in each sequence. To enable this function in a par-

ticular sequence, set the SPXV_EN register in the appropriate

set of sequence registers to 1. The SPXV_ACT register determines

the active line for the special second V-pattern. The VPATSELB

and VSTARTB registers control both the V-pattern used and the

starting pixel location of the special second V-pattern. For more

information, see Table 17.

Sweep Mode Operation

The AD9923A contains an additional mode of vertical timing

operation called sweep mode. This mode is used to generate a

large number of repetitive pulses that span across multiple HD

lines. Normally, the vertical timing of the AD9923A must be

contained within one HD line length, but when sweep mode is

enabled, the HD boundaries are ignored until the region is

finished. This is useful, for example, in CCD readout operations.

Depending on the vertical resolution of the CCD, up to 3000 clock

cycles, spanning across several HD line lengths, can be required

to shift charge out of the vertical interline CCD registers. These

registers must be free of all charge at the end of the image

exposure before the image is transferred. This can be accom-

plished in sweep mode by quickly shifting out any charge using

a long series of pulses from the XV1 to XV13 outputs. To enable

sweep mode in any region, program the appropriate SWEEP

register to high.

To avoid undesired behavior, do not use the special second

V-pattern in the VSG line; use the existing VPATSECOND and

VSTARTSECOND registers to insert a second V-pattern into

the VSG line. It is recommended that VPATSECOND and

VSTARTSECOND registers are used to create complex timing in

the sensor gate line and not the GROUPB registers. Additionally,

given that the special second V-pattern insertion uses some of the

Group B registers, the user cannot use the special second V-pattern

insertion function and Group B in the same sequence.

Rev. 0 | Page 34 of 88

AD9923A

START POSITION FOR SECOND VPAT GROUP

USES VSTARTSECOND REGISTER

HD

VSG

XV1

XV2

XV13

SECOND VPAT GROUP

Figure 47. Example of Second VPAT Group During Sensor Gate Line

VD

HD

SCP 1

SCP 2

LINE 0

LINE 1

LINE

2

LINE 24

LINE 25

XV1 TO XV13

REGION 0

REGION 1: SWEEP REGION

REGION 2

Figure 48. Example of Sweep Region for High Speed Vertical Shift

Figure 48 shows an example of sweep mode operation. The

number of required vertical pulses depends on the vertical

resolution of the CCD. The XV1 to XV13 output signals are

generated using the V-pattern registers (shown in Table 14).

A single pulse is created using the polarity and toggle position

registers. The number of repetitions is then programmed to

match the number of vertical shifts required by the CCD.

Repetitions are programmed in the V-sequence registers using

the VREP registers. This produces a pulse train of the appropriate

length. Normally, the pulse train is truncated at the end of the

HD line length, but with sweep mode enabled, the HD

boundaries are ignored. In Figure 48, the sweep region occupies

23 HD lines. After the sweep mode region is complete, normal

sequence operation resumes in the next region. When using

sweep mode, set the region boundaries, using the sequence

change position registers, to the appropriate lines to prevent the

sweep operation from overlapping with the next V-sequence.

The start polarity and toggle positions are used in the same

manner as the standard VPAT group programming, but the

VLEN register is used differently. Instead of using the pixel

counter (HD counter) to specify the toggle position locations

(XVTOG1, XVTOG2, XVTOG3, XVTOG4, XVTOG5, and

XVTOG6) of the VPAT group, the VLEN value is multiplied by

the XVTOG value to allow very long pulses to be generated. To

calculate the exact toggle position, counted in pixels after the

start position, use the following equation:

Multiplier Mode Toggle Position = XVTOG × VLEN

Because the XVTOG value is multiplied by the VLEN value, the

resolution of the toggle position placement is reduced.

If VLEN = 4, the toggle position accuracy is reduced to four

pixel steps, instead of single pixel steps. Table 18 summarizes

how the VPAT group registers are used in multiplier mode

operation. In multiplier mode, the VREP registers should be

programmed to the value of the highest toggle position.

Multiplier Mode

To generate very wide vertical timing pulses, a vertical region

can be configured into a multiplier region. This mode uses the

V-pattern registers in a slightly different manner. Multiplier mode

can be used to support unusual CCD timing requirements, such

as vertical pulses that are wider than the 13-bit V-pattern toggle

position counter.

The example shown in Figure 49 illustrates this operation. The

first toggle position is 2, and the second toggle position is 9. In

nonmultiplier mode, this causes the V-sequence to toggle at

Rev. 0 | Page 35 of 88

AD9923A

Pixel 2 and Pixel 9 within a single HD line. However, in

multiplier mode the toggle positions are multiplied by

VLEN = 4; therefore, the first toggle occurs at pixel count = 8,

and the second toggle occurs at pixel count = 36. Sweep mode is

also enabled to allow the toggle positions to cross the HD line

boundaries.

The MULTI function only applies to signals assigned to Group A.

It cannot be used at the same time as the TWOGROUP function or

if any signals are assigned to Group B.

Table 18. Multiplier Mode Register Parameters

Length

(Bits)

Register

MULTI

XVPOL

XVTOG

VLEN

Range

Description

1

13

12

High/low

0 to 8191 pixel location

0 to 8191 pixels

0 to 4095

High enables multiplier mode

Starting polarity of XV1 to XV13 signals in each VPAT group

Toggle positions for XV1 to XV13 signals in each VPAT group

Used as multiplier factor for toggle position counter

VREPE/VREPO should be set to the value of the highest XVTOG value

VREP

START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE V-SEQUENCE REGISTERS

HD

5

3

VLEN

1

2

3

4

1

5

2

6

3

7

4

8

1

9

2

3

4

1

2

3

4

1

2

3

4

1

2

3

4

1

2

3

4

1

2

3

4

1

2

3

4

1

2

3

4

PIXEL

NUMBER

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

4

XV1 TO XV13

1

2

MULTIPLIER MODE V-PATTERN GROUP PROPERTIES:

1

START POLARITY (ABOVE: STARTPOL = 0).

FIRST AND SECOND TOGGLE POSITIONS (ABOVE: XVTOG1 = 2, XVTOG2 = 9).

LENGTH OF VPAT COUNTER (ABOVE: VPATLEN = 4); THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES.

TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (XVTOG × VPATLEN).

2

3

4

5

IF SWEEP REGION IS ENABLED, THE V-PULSES MAY ALSO CROSS THE HD BOUNDRIES, AS SHOWN ABOVE.

Figure 49. Example of Multiplier Region for Wide Vertical Pulse Timing

Rev. 0 | Page 36 of 88

AD9923A

and SGACTLINE2 registers. Additionally, any of the VSG1 to

VSG8 pulses can be individually disabled using the SGMASK

register. The individual masking allows all SG patterns to be

preprogrammed, and the appropriate pulses for each field can

be separately enabled. For maximum flexibility, the SGPATSEL,

SGMASK, and SGACTLINE registers are separately programmable

for each field. More detail is given in the Complete Field:

Combining V-Sequences section.

Vertical Sensor Gate (Shift Gate) Patterns

In an interline CCD, the vertical sensor gates (VSG) are used to

transfer the pixel charges from the light sensitive image area

into the light shielded vertical registers. From the light shielded

vertical registers, the image is then read line-by-line using the

XV1 to XV13 vertical transfer pulses in conjunction with the

high speed horizontal clocks.

Table 19 summarizes the VSG pattern registers. The AD9923A

has eight VSG outputs, VSG1 to VSG8. Each output can be

assigned to one of eight programmed patterns by using the

SGPATSEL register. Each pattern is generated in a similar

manner as the V-pattern groups, with a programmable start

polarity (SGPOL), first toggle position (SGTOG1), and second

toggle position (SGTOG2). The active line where the VSG1 to

VSG8 pulses occur is programmable using the SGACTLINE1

Additionally, there is the SGMASK_BYP register (Address 0x59)

that overrides SG masking in the field registers. The SGMASK_BYP

register allows sensor gate masking to be changed without

modifying the field register values. The SGMASK_BYP register

is SCK updated; therefore, the new SG-masking values update

immediately.

Table 19. VSG Pattern Registers¹

Length

(Bits)

Register

SGPOL

Range

Description

Sensor gate starting polarity for SG patterns 0 to 7.

1

High/low

SGTOG1

13

0 to 8191 pixel First toggle position for SG patterns 0 to 7.

location

0 to 8191 pixel

location

High/low for

each VSG

SGTOG2

13

8

Second toggle position for SG patterns 0 to 7.

SGMASK_BYP

SGMASK Bypass. This register overrides the SGMASK values in each field register. One bit

for each output, where Bit[0] is for VSG1 output and Bit 7 is for VSG8 output.

0 = active.

1 = mask output.

SGMASK_BYP_EN

1

0 or 1

1: enables SGMASK bypass.

¹See field registers in Table 16.

VD

4

HD

1

2

3

VSG PATTERNS

PROGRAMMABLE SETTINGS FOR EACH PATTERN:

1

START POLARITY OF PULSE.

2

FIRST TOGGLE POSITION.

3

SECOND TOGGLE POSITION.

4

ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (PROGRAMMABLE IN THE FIELD REGISTER, NOT FOR EACH PATTERN).

Figure 50. Vertical Sensor Gate Pulse Placement

Rev. 0 | Page 37 of 88

AD9923A

Table 20 shows how the MODE register bits are used. Unlike

other registers, the MODE register uses 10 address bits as data

bits to increase the total register size to 38 bits. The address

MSBs, A11 and A10, are 1 and 0, respectively, and are used to

specify the MODE register write. The three MSBs, D37, D36,

and D35 are used to specify the number of fields used. A value

from 1 to 7 can be selected using these three bits. The remaining

register bits are divided into five-bit sections to select which

programmed fields are used and in which order. Up to seven

fields can be used in a single MODE write. The AD9923A starts

with the field timing specified by the first field bit, and switches

to the timing specified by the second field bit on the next VD,

and so on.

MODE Register

The MODE register is a single register that selects the field timing

of the AD9923A. Typically, all field, V-sequence, and V-pattern

group information is programmed into the AD9923A at startup.

During operation, the MODE register allows the user to select

any combination of field timing to meet the current requirements

of the system. Using the MODE register in conjunction with

preprogrammed timing greatly reduces the system programming

requirements during camera operation. Only a few register writes

are required when the camera operating mode is changed rather

than having to rewrite the vertical timing information with each

camera mode change.

A basic still camera application can require five fields of vertical

timing—one for draft mode operation, one for autofocusing, and

three for still image readout. The register timing information for

the five fields is loaded at startup. Depending on how the camera

is being used, the MODE register selects which field timing is

active during camera operation.

After completing the number of fields specified in Bit D37 to

Bit D35, the timing generator of the AD9923A repeats itself by

starting at the first field. This continues until a new write to the

MODE register occurs. Figure 51 shows MODE register settings

for various field configurations.

Table 20. Mode Register Contents—VD Updated

Data Bits

Address (Binary)

Default Value

Description

12b10_xx_xxxx_xxxx

[37:0]

[37:35]

[34:30]

[29:25]

[24:20]

[19:15]

[14:10]

[9:5]

0

A11, A10 must be set to 0x10; remaining A9:A0 bits used for D37:D28

Number of fields (maximum of seven)

Selected field for Field 7

Selected field for Field 5

Selected field for Field 6

Selected field for Field 4

Selected field for Field 3

Selected field for Field 2

[4:0]

Selected field for Field 1

EXAMPLE 1:

TOTAL FIELDS = 3, FIRST FIELD = FIELD 0, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 2

MODE REGISTER CONTENTS = 0x9800000820

FIELD 1

FIELD 2

FIELD 0

EXAMPLE 2:

TOTAL FIELDS = 1, FIRST FIELD = FIELD 3

MODE REGISTER CONTENTS = 0x8800000003

FIELD 3

EXAMPLE 3:

TOTAL FIELDS = 4, FIRST FIELD = FIELD 5, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 4, FOURTH FIELD = FIELD 2

MODE REGISTER CONTENTS = 0xA000011025

FIELD 2

FIELD 1

FIELD 4

FIELD 5

Figure 51. Using the Mode Register to Select Field Timing

Rev. 0 | Page 38 of 88

AD9923A

number of high speed vertical pulses needed to clear any charge

from the vertical registers of the CCD.

VERTICAL TIMING EXAMPLE

To better understand how the AD9923A vertical timing

generation is used, consider the example CCD timing chart

in Figure 52. It illustrates a CCD using a general three-field

readout technique. As described in the Complete Field:

Combining V-Sequences section, each readout field should

be divided into separate regions to perform each step of the

readout. The sequence change position (SCP) registers deter-

mine the line boundaries for each region. Then, the VSEQSEL

registers assign a V-sequence to each region. Each V-sequence

contains specific timing information required for each region:

XV1 to XV6 pulses (using VPAT groups), HBLK/CLPOB timing,

and VSG patterns for the SG active lines.

Region 1

Region 1 consists of two lines and uses standard, single line,

vertical shift timing. The timing of this region is the same as the

timing of Region 3.

Region 2

Region 2 is the sensor gate line, where the VSG pulses transfer

the image into the vertical CCD registers. This region might

require use of the second V-pattern group for the SG active line.

Region 3

Region 3 also uses the standard, single line, vertical shift timing,

the same timing used in Region 1. In summary, four regions are

required in each of the three fields.

The example shown in Figure 52 requires four regions, labeled

Region 0, Region 1, Region 2, and Region 3, for each of the

three fields. Because the AD9923A allows many individual

fields to be programmed, Field 0, Field 1, and Field 2 can be

created to meet the requirements of this timing example. In this

example, the four regions for each field are very similar, but the

individual registers for each field allow flexibility to accommodate

more complex timing requirements.

The timing for Region 1 and Region 3 is essentially the same,

reducing the complexity of the register programming. Other

registers, such as the MODE register, shutter control registers

(that is, TRIGGER, and the registers to control the SUBCK,

VSUB, MSHUT, and STROBE outputs), and the AFE gain

registers, VGAGAIN and CDSGAIN, must be used during the

readout operation. These registers are explained in the MODE

Register and Variable Gain Amplifier sections.

Region 0

Region 0 is a high speed vertical shift region. Sweep mode can

be used to generate this timing operation, with the desired

Rev. 0 | Page 39 of 88

AD9923A

1

0 5 5 - 4 1 0 6

N

3

N –

2 1

1 8

1 5

1 2

9

6

3

1

4

N –

2 0

1 7

1 4

1 1

8

5

2

5

N –

1 6

1 3

1 0

7

4

1

Figure 52. CCD Timing Example—Dividing Each Field into Regions

Rev. 0 | Page 40 of 88

AD9923A

VERTICAL DRIVER SIGNAL CONFIGURATION

VDR_EN = low, V1 to V13 are forced to VM and SUBCK is

forced to VLL. The VDR_EN pin takes priority over the XV and

VSG signals coming from the timing generator.

As shown in Figure 53, XV1 to XV13, VSG1 to VSG8, and

XSUBCK are outputs from the internal AD9923A timing

generator, and V1 to V13 and SUBCK are the resulting outputs

from the AD9923A vertical driver. When VDR_EN = high, the

vertical driver mixes the XV and VSG pulses and amplifies

them to the high voltages required for driving the CCD. Table 21

through Table 36 describe the output polarities for these signals

vs. their input levels. Refer to these tables when determining the

register settings for the desired output levels. Note that when

The VDR_EN pin can be driven either with an external 3 V

logic signal or by one of the AD9923A shutter outputs

(MSHUT, VSUB, STROBE). To make the AD9923A compatible

with existing AD9923 designs, drive the VDR_EN pin with a

diode to either an external 3 V logic signal or to one of the

shutter outputs.

AD9923A

V-DRIVER

VH VL

3V

XV1

VSG1

XV11

VSG2

XV3

V1

V11

V3

VSG3

XV12

VSG4

3-LEVEL OUTPUTS

V12

VSG5

XV5

V5A

V5B

V7A

V7B

VSG6

INTERNAL

TIMING

GENERATOR

VSG7

XV7

VSG8

XV2

XV4

V2

V4

XV6

V6

XV8

V8

2-LEVEL OUTPUTS

XV9

V9

XV10

XV13

V10

V13

XSUBCK

SUBCK

XSUBCNT

VDR_EN

Figure 53. Internal Vertical Driver Input Signals

Rev. 0 | Page 41 of 88

AD9923A

Table 21. V1 Output Polarity

Table 27. V11 Output Polarity

Vertical Driver Input

V1 Output

V11 Output

XV1

L

H

VSG1

XV11

VSG2

L

H

L

VH

VM

VL

L

H

L

H

L

VH

VM

VL

H

VL

H

VL

Table 22. V3 Output Polarity

Table 28. V12 Output Polarity

Vertical Driver Input

V3 Output

V12 Output

XV3

L

H

VSG3

XV12

VSG4

L

H

L

VH

VM

VL

L

H

L

H

L

VH

VM

VL

H

VL

H

VL

Table 23. V5A Output Polarity

Table 29. V2 Output Polarity

Vertical Driver Input

Vertical Driver Input XV2

V2 Output

V5A Output

L

H

VM

VL

XV5

L

H

VSG5

L

H

L

VH

VM

VL

Table 30. V4 Output Polarity

Vertical Driver Input XV4

H

VL

V4 Output

L

H

VM

VL

Table 24. V5B Output Polarity

Vertical Driver Input

V5B Output

XV5

L

H

VSG6

Table 31. V6 Output Polarity

Vertical Driver Input XV6

L

H

L

H

L

VH

VM

VL

V6 Output

VM

VL

H

VL

Table 32. V8 Output Polarity

Vertical Driver Input XV8

Table 25. V7A Output Polarity

V8 Output

Vertical Driver Input

L

H

VM

VL

V7A Output

XV7

L

VSG7

L

VH

VM

VL

L

H

L

Table 33. V9 Output Polarity

H

VL

Vertical Driver Input XV9

V9 Output

L

H

VM

VL

Table 26. V7B Output Polarity

Vertical Driver Input

V7B Output

XV7

L

VSG8

L

H

L

VH

VM

VL

H

VL

Rev. 0 | Page 42 of 88

AD9923A

Table 34. V10 Output Polarity

Table 36. SUBCK Output Polarity

Vertical Driver Input XV10

V10 Output

Vertical Driver Input

SUBCK Output

L

H

VM

VL

XSUBCK

XSUBCNT

L

VH

L

H

L

H

VH

VMM

VLL

Table 35. V13 Output Polarity

Vertical Driver Input XV13

V13 Output

L

H

VM

VL

XV1

VSG1

VH

V1

VM

VL

Figure 54. XV1, VSG1, and V1 Output Polarities

XV11

VSG2

VH

VM

VL

V11

Figure 55. XV11, VSG2, and V11 Output Polarities

XV3

VSG3

VH

VM

VL

V3

Figure 56. XV3, VSG3, and V3 Output Polarities

Rev. 0 | Page 43 of 88

AD9923A

XV12

VSG4

VH

V12

VM

VL

Figure 57. XV12, VSG4, and V12 Output Polarities

XV5

VSG5

VH

VM

VL

V5A

Figure 58. XV5, VSG5, and V5A Output Polarities

XV5

VSG6

VH

VM

VL

V5B

Figure 59. XV5, VSG6, and V5B Output Polarities

XV7

VSG7

VH

VM

VL

V7A

Figure 60. XV7, VSG7, and V7A Output Polarities

Rev. 0 | Page 44 of 88

AD9923A

XV7

VSG8

VH

VM

VL

V7B

Figure 61. XV7, VSG8, and V7B Output Polarities

XV2, XV4, XV6, XV8

XV9, XV10, XV13

VM

V2, V4, V6, V8

V9, V10, V13

VL

Figure 62. XV2, XV4, XV6, XV8, XV9, XV10, XV13 and V2, V4, V6, V8, V9, V10, V13 Output Polarities

XSUBCNT

XSUBCK

VH

SUBCK

VMM

VLL

Figure 63. XSUBCNT, XSUBCK, and SUBCK Output Polarities

SHUTTER TIMING CONTROL

shutter and VSUB pulses with a logic XOR operation (symbolized

by ^) to generate more complex timing (up to four toggle posi-

tions per line) for MSHUT, STROBE and VSUB: SHUT0 ^ VSUB0,

SHUT0 ^ VSUB1, SHUT0 ^ SHUT1, and SHUT0 ^ SHUT2.

The CCD image exposure time is controlled by the substrate clock

signal (SUBCK) that pulses the CCD substrate to clear out

accumulated charge. The AD9923A supports three types of

electronic shuttering: normal, high precision, and low speed.

Together with the SUBCK pulse placement, the AD9923A can

accommodate different readout configurations to further

suppress the SUBCK pulses during multiple field readouts. The

AD9923A also provides programmable outputs to control an

external mechanical shutter (MSHUT), strobe/flash (STROBE),

and CCD bias select signal (VSUB). Up to four general shutter

pulses (SHUT0 to SHUT3) and two VSUB pulses (VSUB0 and

VSUB1) can be programmed and assigned to any of the three

shutter output pins. The user can also combine the following

SUBCK: Three-Level Output

The AD9923A supports a three-level output from the SUBCK

buffer: VH, VMM, and VLL. The VH power supply is shared

with the V-driver outputs, but VMM and VLL are dedicated

mid and low supplies for the SUBCK buffer. There are two in-

puts to the SUBCK buffer, XSUBCK and XSUBCNT. XSUBCNT

is created by an internal multiplexer that selects from XV1 to

XV13, VSG1 to VSG8, MSHUT, STROBE, VSUB, SHUT0 to

SHUT3, FG_TRIG, high and low.

Rev. 0 | Page 45 of 88

AD9923A

SUBCK: Normal Operation

Table 37. XSUBCNT Multiplexer

By default, the AD9923A operates in a normal SUBCK configu-

ration with the SUBCK signal pulsing in every VD field (see

Figure 64). The SUBCK pulse occurs once per line, and the total

number of repetitions within the field determines the exposure

time. The SUBCK pulse polarity and toggle positions within a

line are programmable, using the SUBCKPOL and SUBCK1TOG

registers (see Table 38). The number of SUBCK pulses per field

is programmed in the SUBCKNUM register (Address 0x64).

Length

(Bits)

Register

Range

Description

XSUBCNT_MUX

5

0 to 31

Selects internal signal to

be used for XSUBCNT

0: XV6

1: XV8

2: XV9

3: XV10

4: VSG5

As shown in Figure 64, the SUBCK pulses always begin in the

line following the SG active line (specified in the SGACTLINE

registers for each field). The SUBCKPOL, SUBCK1TOG,

SUBCK2TOG, SUBCKNUM, and SUBCKSUPPRESS registers

are updated at the start of the line after the sensor gate line, as

described in the Updating New Register Values section.

5: VSG6

6: VSG7

7: VSG8

8: VSG2

9: VSG3

10: VSG4

11: VSG1

12: XV13

13: VSUB

14: MSHUT

15: STROBE

16: XV1

17: XV2

18: XV3

19: XV4

20: XV5

SUBCK: High Precision Operation

High precision shuttering is used in the same manner as normal

shuttering, but an additional register is used to control the last

SUBCK pulse. In this mode, the SUBCK pulses once per line,

but the last SUBCK in the field has an additional SUBCK pulse,

whose location is determined by the SUBCK2TOG register, as

shown in Figure 65. Finer resolution of the exposure time is

possible using this mode. Leaving the SUBCK2TOG register set

to its maximum value (0xFFFFFF) disables the last SUBCK

pulse (default setting).

21: XV7

22: XV11

23: XV12

24: SHUT0

25: SHUT1

26: SHUT2

27: SHUT3

28: FG_TRIG

29: invalid setting

30: high

31: low

SUBCK: Low Speed Operation

Normal and high precision shutter operations are used when

the exposure time is less than one field long. For exposure times

longer than one field interval, low speed shutter operation is

used. The AD9923A uses a separate exposure counter to

achieve long exposure times. The number of fields for the low

speed shutter operation is specified in the EXPOSURENUM

register (Address 0x63). As shown in Figure 66, this shutter

mode suppresses the SUBCK and VSG outputs from 0 fields up

to 4095 fields (VD periods). The VD and HD outputs can be

suppressed during the exposure period by programming the

VDHDOFF register to 1.

To generate a low speed shutter operation, trigger a long ex-

posure by writing to the TRIGGER register, Bit D3. When this

bit is set high, the AD9923A begins an exposure operation at

the next VD edge. If a value greater than 0 is specified in the

EXPOSURENUM register, the AD9923A suppresses the

SUBCK output on subsequent fields.

If the exposure is generated using the TRIGGER register and

the EXPOSURENUM register is set to 0, the behavior of the

SUBCK is the same as during normal shutter or high precision

shutter operations, in which the TRIGGER register is not used.

Rev. 0 | Page 46 of 88

AD9923A

VD

HD

VSG

t_EXP

SUBCK

SUBCK PROGRAMMABLE SETTINGS:

1. PULSE POLARITY USING THE SUBCKPOL REGISTER.

2. NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER (SUBNUM = 3 IN THE ABOVE EXAMPLE).

3. PIXEL LOCATION OF PULSE WITHIN THE LINE AND PULSE WIDTH PROGRAMMED USING THE SUBCK1TOG REGISTER.

Figure 64. Normal Shutter Mode

VD

HD

VSG

t_EXP

SUBCK

NOTES

1. SECOND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE.

2. LOCATION OF SECOND PULSE IS FULLY PROGRAMMABLE USING THE SUBCK2TOG REGISTER.

Figure 65. High Precision Shutter Mode

TRIGGER

EXPOSURE

VD

VSG

t_EXP

SUBCK

NOTES

1. SUBCK CAN BE SUPPRESSED FOR MULTIPLE FIELDS BY PROGRAMMING THE EXPOSURE REGISTER TO BE GREATER THAN 0.

2. ABOVE EXAMPLE USES EXPOSURE = 1.

3. TRIGGER REGISTER MUST ALSO BE USED TO START THE LOW SPEED EXPOSURE.

4. VD/HD OUTPUTS CAN ALSO BE SUPPRESSED USING THE VDHDOFF REGISTER = 1.

Figure 66. Low Speed Shutter Mode Using EXPOSURE Register

Rev. 0 | Page 47 of 88

AD9923A

users to select the internal SHUT3 signal and create a custom

SUBCK masking pattern that spans several fields.

SUBCK: Suppression

Normally, the SUBCK begins pulsing on the line following the

sensor gate line (VSG). Some CCDs require suppressing the

SUBCK pulse for one or more lines following the VSG line. The

SUBCKSUPPRESS register enables such suppression.

When generating an exposure by using the TRIGGER register,

as previously described in the Readout After Exposure section,

the AD9923A outputs the SUBCK and VSG signals on every

field by default. This works well for continuous, single field

exposure and readout operations, such as those in the CCD live

preview mode. However, if the CCD requires a longer exposure

time, or if multiple readout fields are needed, the TRIGGER

register is needed to initiate specific exposure and readout

sequences.

Readout After Exposure

After the exposure, the readout of the CCD data occurs, beginning

with the sensor gate (VSG) operation. By default, the AD9923A

generates VSG pulses in every field. When only a single exposure

and readout frame are needed, as is the case in the CCD preview

mode, the VSG and SUBCK pulses can operate in every field.

Typically, the exposure and readout bits in the TRIGGER register

are used together. This initiates a complete exposure-plus-readout

operation. After the exposure, the readout occurs automatically.

The values in the EXPOSURE and READOUTNUM registers

determine the length of each operation.

However, often during readout, the SUBCK output must be

suppressed until the readout is complete. The READOUTNUM

register specifies the number of additional fields after the exposure

to continue the suppression of SUBCK. READOUTNUM can be

programmed for 0 to 7 fields, and should be preprogrammed at

startup, not at the same time as the exposure write. A typical

interlaced CCD frame readout mode generally requires two fields

of SUBCK suppression (READOUTNUM = 2) during readout.

A three-field, six-phase CCD requires three fields of SUBCK

suppression after the readout begins (READOUTNUM = 3).

It is possible to independently trigger the readout operation

without triggering the exposure operation. This causes the readout

to occur at the next VD, and the SUBCK output is suppressed

according to the value set in the READOUTNUM register.

The TRIGGER register also controls the SHUT and VSUB signals.

Each signal is individually controlled, but dependent on the

triggering of the exposure and readout operations. See Figure 71

for a complete example of triggering the exposure and readout

operations.

If SUBCK output is required to initiate backup during the last field

of readout, program the READOUTNUM register to one less

than the total number of CCD readout fields. Similar to the

exposure operation, the readout operation must be triggered

using the TRIGGER register.

Alternatively, it is possible to manually control the exposure and

readout operations by carefully updating the SUBCKSUPPRESS

and VSG masking registers upon every VD field. As described in

the following sections, it is possible to have partial or full manual

control of the shutter signals. This allows greater flexibility in

generating custom exposure/readout/shutter signal timing.

SUBCK: Additional Masking

The SUBCKMASK register (Address 0x65) allows more complex

SUBCK masking. If SUBCKMASK = 1, it starts masking the

SUBCK at the next VD edge. If SUBCKMASK = 2, it enables

Rev. 0 | Page 48 of 88

AD9923A

Table 38. SUBCK and TRIGGER Register Parameters

Length

(Bits)

Register

Range

Description

TRIGGER

8

On/off for eight signals

0: triggers SHUT0 signal.

1: triggers SHUT1 signal.

2: triggers SHUT2 signal.

3: triggers SHUT3 signal.

4: triggers VSUB0 signal.

5: triggers VSUB1 signal.

6: triggers EXPOSURE operation.

7: triggers READOUT operation.

Number of fields to suppress SUBCK after exposure.

READOUTNUM

EXPOSURENUM

3

0 to 7 fields

12

0 to 4095 fields

Number of fields to suppress to SUBCK and VSG during exposure time (low

speed shutter).

VDHDOFF

1

On/off

Disable VD/HD output during exposure.

1 = disable VD.

0 = enable VD.

SUBCKPOL¹

1

High/low

SUBCK start polarity for SUBCK1 and SUBCK2.

SUBCK1TOG1¹

SUBCK1TOG2¹

SUBCK2TOG1¹

SUBCK2TOG2¹

SUBCKNUM¹

SUBCKSUPPRESS¹12

SUBCKMASK¹

12

0 to 4095 pixel locations First toggle positions for first SUBCK pulse (normal shutter).

0 to 4095 pixel locations Second toggle positions for first SUBCK pulse (normal shutter).

0 to 4095 pixel locations First toggle positions for second SUBCK pulse in last line (high precision).

0 to 4095 pixel locations Second toggle positions for second SUBCK pulse in last line (high precision).

1 to 4095 pulses

Total number of SUBCKs per field, at one pulse per line.

Number of pulses, after the VSG line, to suppress SUBCK.

Additional masking of SUBCK output.

0 = no additional mask.

0 to 4095 pulses

0 to 3 masking mode

2

1 = start mask at VD edge.

2 = use internal SHUT3 signal to mask.

¹Register is not VD updated, but updated at the start of the line after the sensor gate line.

Shutter Outputs

VSUB Signal Operation

The AD9923A contains three shutter output pins: VSUB,

MSHUT, and STROBE. Internally, there are six possible shutter

signals available: VSUB0, VSUB1, SHUT0, SHUT1, SHUT2,

and SHUT3. Any of these signals, and the following combinations:

SHUT0 ^ VSUB0, SHUT0 ^ VSUB1, SHUT0 ^ SHUT1,

SHUT0 ^ SHUT2, can be mapped to any of the output pins

using the VSUB_CTRL, MSHUT_CTRL, and STROBE_CTRL

registers.

The CCD readout bias (VSUB) can be programmed to accom-

modate different CCDs. Figure 67 shows two available modes.

In Mode 0, VSUB goes active when the exposure begins during

the field of the last SUBCK. The on position (rising edge in

Figure 67) is programmable to any line within the field. VSUB

remains active until the end of the image readout. In Mode 1,

the VSUB is not activated until the start of the readout.

A function called VSUB_KEEPON is also available. When the

appropriate VSUB_KEEPON bit is set high, the VSUB output

remains active, even after the readout has finished. To disable

the VSUB at a later time, return this bit to low.

The VSUB signals behave differently than the SHUT signals,

and are generally used for the VSUB output pin. If a more generic

approach is desired for the shutter signals, the SHUT signals can

be used for the VSUB output pin.

The AD9923A contains two programmable VSUB signals,

VSUB0 and VSUB1. Either of these signals can be mapped to

the VSUB output pin, the MSHUT pin, or the STROBE pin.

It is also possible to configure the SYNC pin as an output and

send one of the internal shutter signals, or the combinations listed

above, to the SYNC pin using the TESTO_CTRL register

function. This provides the flexibility of outputting up to four

shutter outputs if the external SYNC input function is not needed.

Rev. 0 | Page 49 of 88

AD9923A

SHUT Signal Operation

readout operation. Also, single trigger operation is useful when

the exposure or readout operation is manually generated without

using the TRIGGER register, and the SUBCK and VSG masking

are manually controlled.

SHUT signal operation is shown in Figure 68 through Figure 71.

Table 39 shows the register parameters for controlling the

SHUT signals. There are three different ways to use the SHUT

signals: automatic trigger, single trigger, and manual control.

Note that single trigger operation cannot occur if an exposure

operation has been triggered. SHUT signals behave in automatic

trigger mode if they, and an exposure operation, have been

triggered.

Automatic Trigger

Generally, SHUT signals are triggered together with an expo-

sure or readout operation, using the TRIGGER register. The

SHUT_ON and SHUT_OFF positions are fully programmable

to anywhere within the exposure period, using the field

Manual Control

Any SHUT signal can be controlled in manual control mode,

instead of using the TRIGGER register to activate it. In this

mode, the individual on and off lines and pixel positions are

used separately, depending on the status of the manual signal

control register. Note that only a single toggle position, either

off or on, can be used in a VD interval.

(SHUT_ON_FD/SHUT_OFF_FD), line

(SHUT_ON_LN/SHUT_OFF_LN), and pixel

(SHUT_ON_PX/SHUT_OFF_PX) registers.

The field registers define the field in which the line and pixel

values are used, with respect to the value of the exposure counter.

The on and off positions can occur as soon as the field contains

the last SUBCK (Exposure Field 0), or as late as the final exposure

field before the readout begins. Separate field registers allow the

on and off positions to occur in different exposure fields.

As with single trigger operation, when manual control is

enabled, the SHUT_ON_FD/SHUT_OFF_FD register values

are ignored.

Because there is a separate bit to enable manual control on

SHUT signals, this operation can be used regardless of the

status of a triggered exposure operation.

Single Trigger

SHUT signals can be triggered without triggering an exposure

or readout operation. In this case, SHUT signals are triggered

using the TRIGGER register, but the exposure bit is not triggered.

Both the SHUT on and off positions occur in the next field, and

the SHUT_ON_FD/SHUT_OFF_FD register values are ignored.

Single trigger operation is useful if a pulse is required immedi-

ately in the next field without the occurrence of an exposure or

Note that manual control can be used in conjunction with

automatic or single trigger operations. If a SHUT signal is turned

on using manual control, and then manual control is disabled,

the SHUT signal remains on. If a subsequent trigger operation

occurs, the on position toggle is ignored, because the signal is

already on. In this case, only the off position can be triggered.

TRIGGER

VSUB

VD

VSG1

t_EXP

READOUT

SUBCK

4

2

MODE 0

VSUB

1

3

MODE 1

VSUB OPERATION:

1

2

3

4

ACTIVE POLARITY IS DEFINED BY VSUBPOL (ABOVE EXAMPLE IS VSUB ACTIVE HIGH).

ON POSITION IS PROGRAMMABLE, MODE 0 TURNS ON AT THE START OF EXPOSURE, MODE 1 TURNS ON AT THE START OF READOUT.

OFF POSITION OCCURS AT END OF READOUT.

OPTIONAL VSUB KEEP-ON MODE LEAVES THE VSUB ACTIVE AT THE END OF THE READOUT.

Figure 67. VSUB0, VSUB1 Signal Programmability

Rev. 0 | Page 50 of 88

AD9923A

SINGLE TRIGGER

WRITE

VD

VSG

ON STATE

SHUT0 TO SHUT3

1

OFF STATE

2

3

SHUT PROGRAMMABLE SETTINGS:

1

ACTIVE POLARITY. DEFINES THE LOGIC LEVEL DURING ON TIME. ABOVE EXAMPLE USES ACTIVE POLARITY = 1.

ON POSITION IS PROGRAMMABLE TO ANY LINE/PIXEL IN FIELD IMMEDIATELY FOLLOWING SINGLE TRIGGER WRITE.

OFF POSITION IS PROGRAMMABLE TO ANY LINE/PIXEL IN FIELD IMMEDIATELY FOLLOWING SINGLE TRIGGER WRITE.

2

3

Figure 68. SHUT0 to SHUT3 Signal Programmability

SHUT_ON = 1

TRIGGER

EXPOSURE

SHUT_ON = 0

(OFF)

(ON)

VD

EXPOSURE FIELD 0

EXPOSURE FIELD 1

EXPOSURE FIELD 2

VSG

t_EXP

SUBCK

ON STATE

SHUT0 TO SHUT3

1

OFF STATE

2

3

SHUT PROGRAMMABLE SETTINGS:

1

ACTIVE POLARITY. DEFINES THE LOGIC LEVEL DURING ON TIME. ABOVE EXAMPLE USES ACTIVE POLARITY = 1.

ON POSITION IS PROGRAMMABLE DURING ANY EXPOSURE FIELD. ABOVE EXAMPLE USES SHUTON_FD = 1.

OFF POSITION IS PROGRAMMABLE DURING ANY EXPOSURE FIELD. ABOVE EXAMPLE USES SHUTOFF_FD = 2.

2

3

Figure 69. Manual Control of SHUT0 to SHUT3 Signals

TRIGGER

EXPOSURE

AND SHUT

VD

EXPOSURE FIELD 0

EXPOSURE FIELD 1

EXPOSURE FIELD 2

VSG

t_EXP

SUBCK

ON STATE

SHUT0 TO SHUT3

1

OFF STATE

2

3

SHUT PROGRAMMABLE SETTINGS:

1

ACTIVE POLARITY. DEFINES THE LOGIC LEVEL DURING ON TIME. ABOVE EXAMPLE USES ACTIVE POLARITY = 1.

ON POSITION IS PROGRAMMABLE DURING ANY EXPOSURE FIELD. ABOVE EXAMPLE USES SHUTON_FD = 1.

OFF POSITION IS PROGRAMMABLE DURING ANY EXPOSURE FIELD. ABOVE EXAMPLE USES SHUTOFF_FD = 2.

2

3

Figure 70. Single Trigger Control of SHUT0 to SHUT3 Signals

Rev. 0 | Page 51 of 88

AD9923A

Table 39. VSUB0 to VSUB1 and SHUT0 to SHUT3 Register Parameters

Length

(Bits)

Register

Range

Description

VSUB_CTRL

3

0 to 7

Selects which internal shutter signal is mapped to the VSUB pin.

0: SHUT0.

1: SHUT1.

2: SHUT2.

3: SHUT3.

4: use VSUB0_MUX output.

5: use VSUB1_MUX output.

6: invalid setting.

7: use SHUT1_SHUT2_MUX output.

MSHUT_CTRL

STROBE_CTRL

TESTO_CTRL

3

0 to 7

Selects which internal shutter signal is mapped to the MSHUT pin.

0: SHUT0.

1: SHUT1.

2: SHUT2.

3: SHUT3.

4: use VSUB0_MUX output.

5: use VSUB1_MUX output.

6: invalid setting.

7: use SHUT1_SHUT2_MUX output.

Selects which internal shutter signal is mapped to the STROBE pin.

0: SHUT0.

1: SHUT1.

2: SHUT2.

3: SHUT3.

4: use VSUB0_MUX output.

5: use VSUB1_MUX output.

6: invalid setting.

7: use SHUT1_SHUT2_MUX output.

Selects which internal shutter signal is mapped to the TEST0 signal.

0: SHUT0.

1: SHUT1.

2: SHUT2.

3: SHUT3.

4: use VSUB0_MUX output.

5: use VSUB1_MUX output.

6: invalid setting.

7: use SHUT1_SHUT2_MUX output.

0 = use VSUB0.

1= use SHUT0 ^ VSUB0.

0 = use VSUB1.

1= use SHUT0 ^ VSUB 1.

0 = use SHUT0 ^ SHUT1.

1 = use SHUT0 ^ SHUT2.

VSUB mode. See Figure 67.

0 = Mode 0.

VSUB0_MUX

1

High/low

VSUB1_MUX

1

SHUT1_SHUT2_MUX

VSUB_MODE

1

1b

1 = Mode 1.

VSUB_KEEPON

VSUB_ON

1

High/low

VSUB keep-on mode. VSUB stays active after readout when set high.

VSUB on position. Can turn on at any line in the field.

VSUB start polarity. When VSUB is triggered on.

SHUT manual control.

12

1

0 to 4095 line location

High/low

VSUBPOL

SHUT_ON

1

On/off

0 = SHUT off.

1 = SHUT on.

Rev. 0 | Page 52 of 88

AD9923A

Length

(Bits)

Register

Range

Description

SHUTPOL

SHUT_MAN

1

High/low

SHUT active polarity.

Enable/disable

Enables SHUT manual control mode.

0 = disable.

1 = enable.

SHUT_ON_FD

SHUT_ON_LN

SHUT_ON_PX

SHUT_OFF_FD

SHUT_OFF_LN

SHUT_OFF_PX

12

13

12

13

0 to 4095 field location

0 to 4095 line location

0 to 8191 pixel location

0 to 4095 field location

0 to 4095 line location

0 to 8191 pixel location

Field location to switch on MSHUT. Inactive, or closed.

Line position to switch on MSHUT. Inactive, or closed.

Pixel position to switch on MSHUT. Inactive, or closed.

Field location to switch off MSHUT. Inactive, or closed.

Line position to switch off MSHUT. Inactive, or closed.

Pixel position to switch off MSHUT. Inactive, or closed.

Explanation of Figure 71

4. STROBE output turns on and off at the location specified

in the SHUT0_ON/SHUT0_OFF registers (Address 0x6D/

Address 0x71).

The numbers in this section, Explanation of Figure 71,

correspond precisely to the numbers embedded in Figure 71.

5. MSHUT output turns off at the location specified in the

SHUT1_OFF_FD, SHUT1_OFF_LN, and SHUT1_OFF_PX

registers (Address 0x75 and Address 0x76). The SHUT1 on

position is ignored, because the SHUT1 signal is already on

from a previous manual operation (see Step 10).

1. Write to the READOUTNUM register (Address 0x62) to

specify the number of fields to suppress SUBCK during

readout of CCD data. In this example, READOUTNUM = 3.

Write to the EXPOSURENUM register (Address 0x63) to

specify the number of fields to suppress SUBCK and VSG out-

puts during exposure. In this example, EXPOSURENUM = 1.

6. The next VD falling edge automatically starts the first

readout field.

Write to the TRIGGER register (Address 0x61) to trigger

the SHUT0 (STROBE), SHUT1 (MSHUT), and VSUB0

(VSUB) signals, and to start the exposure-plus-readout

operation. To trigger these events (see Figure 71), set the

register TRIGGER = 0xD3. Readout automatically occurs

after the exposure period finishes.

7. The next VD falling edge automatically starts the second

readout field.

8. The next VD falling edge automatically starts the third

readout field.

9. Write to the MODE register to reconfigure the single draft

mode field timing.

Write to the MODE register to configure the next five

fields. The first two fields during exposure are the same as

the current draft mode fields, and the next three fields are

the still frame readout fields. The register settings for the

draft mode field and the three readout fields are previously

programmed.

Write a 1 to the SHUT1_MAN and SHUT1_ON registers

(Address 0x72) to turn the MSHUT output back manually.

10. VD/HD falling edge updates the serial writes from 9. VSG

outputs return to draft mode timing. SUBCK output

resumes operation.

2. VD/HD falling edge updates the serial writes from 1.

3. If VSUB0 MODE = 0 (Address 0x69), VSUB output

turns on at the line specified in the VSUB0_ON

register (Address 0x6A).

MSHUT output returns to the on position (active or open).

Be sure to disable manual control of SHUT1 before another

automatic trigger of the SHUT1 signal is needed.

VSUB output returns to the off position (inactive).

Rev. 0 | Page 53 of 88

AD9923A

EXAMPLE OF EXPOSURE AND READOUT OF INTERLACED FRAME

6 0 9 5 - 4 1 0 6

Figure 71. Example of Exposure and Still Image Readout Using Shutter Signals and MODE Register

Rev. 0 | Page 54 of 88

AD9923A

and pixel resolution. The field registers for SHUT1 are ignored

because the field placement of the FG_TRIG pulse is matched

to the field count specified by the MODE register operation.

The FG_TRIGEN register contains a three-bit value that specifies

which field count contains the FG_TRIG pulse. Figure 72 shows

how the FG_TRIG pulse is generated using these registers.

FG_TRIG OPERATION

The AD9923A contains one additional signal that can be used

in conjunction with shutter operation or general system

operation. The FG_TRIG signal is an internally generated pulse

that can be output on the SYNC pins for shutter or other system

functions. A unique feature of the FG_TRIG signal is that it is

output with respect to the MODE register field status.

After the FG_TRIG signal is specified, it can be enabled using

Bit 3 of the FG_TRIGEN register. The FG_TRIG signal is

mapped to the SYNC output if the SYNC pin is configured as

an output (SYNCENABLE = 0).

The FG_TRIG signal is generated using the SHUT1 start

polarity and toggle position registers, programmable with line

Table 40. FG_TRIG Operation Registers

Register

Address Bit Location Description

SYNCENABLE

0x12

[0]

0 = configures SYNC pin as an output. By default, the FG_TRIG signal is output on the SYNC pin.

1 = SYNC pin is an external synchronization input.

[2:0] selects the field count for the pulse based on the mode field counter.

[3] = 1 to enable FG_TRIG signal output.

FG_TRIGEN

0xF1

[3:0]

SHUT1POL

SHUT1_ON_LN

SHUT1_ON_PX

0x72

0x74

[1]

[1] FG_TRIG start polarity.

FG_TRIG first toggle, line location.

[11:0]

[25:13]

[11:0]

[25:13]

FG_TRIG first toggle, pixel location.

SHUT1_OFF_LN 0x76

SHUT1_OFF_PX 0x76

FG_TRIG second toggle, line location.

FG_TRIG second toggle, pixel location.

VD

MODE REGISTER

FIELD COUNT

FIELD 0

FIELD 1

FIELD 2

FIELD 0

FIELD 1

4

FG_TRIG

1

2

3

FG_TRIG PROGRAMMABLE SETTINGS:

1

ACTIVE POLARITY.

2

FIRST TOGGLE POSITION, LINE AND PIXEL LOCATION.

3

4

SECOND TOGGLE POSITION, LINE AND PIXEL LOCATION.

FIELD PLACEMENT BASED ON MODE REGISTER FIELD COUNT.

Figure 72. FG_TRIG Signal Generation

Rev. 0 | Page 55 of 88

AD9923A

0.1µF 0.1µF

REFB REFT

1.0V 2.0V

FIXED

DELAY

1

0

DC RESTORE

1.5V

CLI

DCLK

DOUT

INTERNAL

DOUT PHASE

V

REF

DOUT

DLY

SHP

DCLK

MODE

SHD

2V FULL SCALE

6dB ~ 42dB

VGA

0.1µF

CCDIN

12

12-BIT

ADC

OUTPUT

DATA

LATCH

CDS

OPTICAL BLACK

CLAMP

DAC

VGA GAIN

REGISTER

CLPOB PBLK

DIGITAL

FILTER

DOUT

PHASE

SHP SHD

CLPOB PBLK

8

CLAMP LEVEL

REGISTER

PRECISION

V-H

TIMING

CLI

GENERATION

AD9923A

Figure 73. Analog Front End Functional Block Diagram

signal with an ADC full-scale range of 2 V. When compared to 1 V

full-scale systems, the equivalent range of gain is 0 dB to 36 dB.

ANALOG FRONT END DESCRIPTION/OPERATION

The AD9923A signal processing chain is shown in Figure 73.

Each step is essential to achieve a high quality image from the

raw CCD pixel data.

The VGA gain curve follows a linear-in-dB characteristic. The

exact VGA gain can be calculated for any gain register value

using the following equation

DC Restore

Gain (dB) = (0.0358 × Code) + 5.5 dB

To reduce the large dc offset of the CCD output signal, a dc restore

circuit is used with an external 0.1 μF series coupling capacitor.

This restores the dc level of the CCD signal to approximately 1.5 V

so that it is compatible with the 3 V supply voltage of the AD9923A.

where the code range is 0 to 1023.

42

Correlated Double Sampler

36

30

24

18

12

6

The CDS circuit samples each CCD pixel twice to extract video

information and reject low frequency noise. The timing shown in

Figure 20 illustrates how the two internally generated CDS

clocks, SHP and SHD, are used to sample the reference and data

levels of the CCD signal, respectively. The placement of the SHP

and SHD sampling edges is determined by the setting of the

SHPLOC and SHDLOC registers located at Address 0x37.

Placement of these clock signals is critical to achieve the best

CCD performance.

0

127

255

383

511

639

767

895

1023

The CDS gain can be set to −3 dB, 0 dB (default), +3 dB, or +6 dB

in the CDSGAIN register, Address 0x04. The +3 dB and +6 dB

settings improve noise performance, but reduce the input range

(see Figure 8).

VGA GAIN REGISTER CODE

Figure 74. VGA Gain Curve

ADC

The AD9923A uses a high performance ADC architecture

optimized for high speed and low power. Differential nonlin-

earity (DNL) performance is typically better than 1 LSB. The

ADC uses a 2 V input range. See Figure 6 and Figure 8 for

typical linearity and noise performance plots.

Variable Gain Amplifier

The VGA stage provides gain in the range of 6 dB to 42 dB,

programmable with 10-bit resolution through the serial digital

interface. A minimum gain of 6 dB is needed to match a 1 V input

Rev. 0 | Page 56 of 88

AD9923A

Optical Black Clamp

immediately valid. Programming the DOUTLATCH register,

Bit D1 to 1 sets the output latches transparent. The data outputs

can also be disabled (three-stated) by setting the DOUTDISABLE

Register 0x01, Bit D0 to 1.

The optical black clamp loop removes residual offsets in the

signal chain and tracks low frequency variations in the CCD

black level. During the optical black (shielded) pixel interval on

each line, the ADC output is compared with a fixed black level

reference, selected by the user in the CLAMPLEVEL register.

The value can be programmed between 0 LSB and 255 LSB in

1023 steps. The resulting error signal is filtered to reduce noise

and the correction value is applied to the ADC input through a

DAC. Normally, the optical black clamp loop is turned on once

per horizontal line, but this loop can be updated more slowly to

suit a particular application. If external digital clamping is used

during postprocessing, the AD9923A optical black clamping

can be disabled using the CLPENABLE register (Address 0x00,

Bit D2). Even though the loop is disabled, the CLAMPLEVEL

register can still be used to provide programmable offset

adjustment.

The DCLK output can be used for external latching of the data

outputs. By default, the DCLK output tracks the value of the

DOUTPHASE register. By changing the DCLKMODE register,

the DCLK output can be held at a fixed phase, and the

DOUTPHASE register value is ignored.

To optimize the delay between the DCLK rising edge and the

data output transition, the DOUTDELAY register is used. By

default, there is approximately 8 ns of delay from the rising edge

of DCLK to the transition of the data outputs. See the High

Speed Timing Generation section for more information.

Switching the data outputs can couple noise into the analog

signal path. To minimize switching noise, set the DOUTPHASE

register to the same edge as the SHP sampling location, or up to

11 edges after the SHP sampling location. Other settings can

produce good results, but require experimentation. It is

recommended that the DOUTPHASE location not occur

between the SHD sampling location and 11 edges after the SHD

location. For example, if SHDLOC = 0, set DOUTPHASE to an

edge location of 12 or greater. If adjustable phase is not required

for the data outputs, the output latch can be left transparent

using Register 0x01, Bit D1.

The CLPOB pulse should be placed during the CCD optical

black pixels. It is recommended that the CLPOB pulse duration

is at least 20 pixels wide to minimize clamping noise. Shorter

pulse widths can be used, but clamping noise might increase,

reducing the ability to track low frequency variations in the

black level. See the Horizontal Clamping and Blanking section

for timing examples.

Digital Data Outputs

The digital output data is latched using the DOUTPHASE

register value, as shown in Figure 73. Output data timing is shown

in Figure 21 and Figure 22. It is also possible to leave the output

latches transparent, so that the data outputs from the ADC are

Data output coding is normally straight binary, but can be

changed to gray coding by setting the GRAYEN Register 0x01,

Bit D2 to 1.

Rev. 0 | Page 57 of 88

AD9923A

CLI input, set the CLIDIVIDE register (Address 0x30) to

1 before resetting the timing core. It is important to wait

at least 500 ꢀs after starting the master clock (CLI) before

resetting the timing core, especially if using a crystal or

crystal oscillator.

Recommended Power-Up Sequence for Master Mode

When the AD9923A is powered up, the following sequence is

recommended (see Figure 75):

1.

2.

3.

4.

Turn on the +3 V power supplies for the AD9923A, and

start the master clock (CLI).

7.

8.

Configure the AD9923A for master mode timing by

writing 1 to the MASTER register (Address 0x20).

Turn on the V-driver supplies (VH and VL). There are no

restrictions on the order in which VH and VL are turned on.

Bring the VDR_EN signal high to +3 V to enable the

V-driver outputs. If VDR_EN = 0 V, all V-driver outputs =

VM, and SUBCK = VLL.

Reset the internal AD9923A registers by writing 1 to the

SW_RST register (Address 0x10).

9.

Write 1 to the OUTCONTROL register (Address 0x11).

This allows the outputs to become active after the next

SYNC rising edge.

Load the required registers to configure the required

VPAT group, V-sequence, field timing information, high

speed timing, horizontal timing, and shutter timing

information.

10. Generate a SYNC event. If SYNC is high at power-up,

bring SYNC input low for a minimum of 100 ns. Then,

bring SYNC high. This causes the internal counters to

reset and starts a VD/HD operation. The first VD/HD

edge allows VD register updates to occur, including

OUTCONTROL to enable all outputs. If an external

SYNC pulse is not available, generate an internal SYNC

pulse by writing to the SYNCPOL register as described in

the Generating Software Sync Without External Sync

Signal section.

5.

6.

To place the part into normal power operation, write 0x04

to the AFE STANDBY register (Bits[1:0], Address 0x00)

and 0x60 to TEST3 Register 0xEA. If the CLO output is

being used to drive a crystal, also power up the CLO

oscillator by writing 1 to Register 0x16.

By default, the internal timing core is held in a reset state

with TGCORE_RSTB register = 0. Write 1 to the

TGCORE_RSTB register (Address 0x15) to start the

internal timing core operation. If a 2× clock is used for the

VH SUPPLY

1

2

+3V SUPPLIES

VL SUPPLY

0V

POWER

SUPPLIES

5

CLI

(INPUT)

3

4

5

6

7

9

SERIAL

WRITES

10

SYNC

(INPUT)

t_SYNC

1V

(HI-Z BY DEFAULT)

VD

FIRST FIELD

(OUTPUT)

1H

HD

(OUTPUT)

DIGITAL

OUTPUTS

H1/H3, RG, DCLK, STROBE, MSHUT, VSUB

(AND INTERNAL XV1 TO XV13, VSG1 TO VSG8, XSBUCK, XSUBCNT)

CLOCKS ACTIVE WHEN OUTCONTROL

REGISTER IS UPDATED AT VD/HD EDGE.

+3V

8

VDR_EN

0V

VH

VM

V1 TO V13

VM

VL

Figure 75. Recommended Power-Up Sequence and Synchronization, Master Mode

Rev. 0 | Page 58 of 88

AD9923A

Table 41. Power-Up Register Write Sequence

Register

Address

Data

Description

SW_RST

0x10

0x20 to 0xFFF

0x00

0xEA

0x16

0x01

User defined

0x04

0x60

0x01

Resets all registers to default values

Horizontal, vertical, shutter timing

Powers up the AFE

Set TEST3 register to required value

Resets crystal oscillator circuit

Resets internal timing core

Configures master mode

STANDBY

TEST3

OSC_RST

TGCORE_RSTB

MASTER

0x15

0x20

0x01

OUTCONTROL

SYNCPOL

0x11

0x13

0x01

Enables all outputs after SYNC

SYNC active polarity (for software SYNC only)

SYNC

VD

SUSPEND

HD

HL, H1 TO H4, RG,

XV1 TO XV13,

VSG1 TO VSG8, SUBCK

NOTES

1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0.

2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13).

3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x14).

4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUTCONTROL = LOW.

5. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE.

Figure 76. SYNC Timing to Synchronize AD9923A with External Timing

Generating Software Sync Without External Sync Signal

Power-Up and Synchronization in Slave Mode

If an external sync pulse is not available, it is possible to generate

an internal sync pulse by writing to the SYNCPOL register

(Address 0x13). If the software SYNC option is used, the SYNC

input (Pin 35) should be low (VSS) during the power-up proce-

dure. After the power-up procedure is complete, the SYNC pin

can be used as an output by setting the SYNCENABLE register

low (Address 0x12).

The power-up procedure for slave mode operation is the same

as the procedure described for master mode operation, with

two exceptions:

•

Eliminate Step 8. Do not configure the part for master

mode timing.

•

No sync pulse is required in slave mode. Substitute Step 10

with starting the external VD and HD signals. This

synchronizes the part, allows the register updates, and

starts the timing operation.

After power-up, follow Step 1 to Step 9 of the procedure in the

Recommended Power-Up Sequence for Master Mode section.

For Step 10, instead of using the external sync pulse, write 1 to

the SYNCPOL register to generate an internal sync pulse and

begin the timing operation.

Note that DCLK does not begin to transition until Step 7 is

complete.

SYNC During Master Mode Operation

When the AD9923A is in slave mode, the VD/HD inputs

synchronize the internal counters. After a falling edge of VD,

there is a latency of 34 master clock edges (CLI) after the falling

edge of HD until the internal H-counter is reset. The reset

operation is shown in Figure 77.

The SYNC input can be used anytime during master mode

operation to synchronize the AD9923A counters with external

timing, as shown in Figure 76.

To suspend operation of the digital outputs during the SYNC

operation, set the SYNCSUSPEND register (Address 0x14) to 1. If

SYNCSUSPEND = 1, the polarities of the outputs are held at the

same state as when OUTCONTROL = low, as shown in Table 42

and Table 43.

Note that if SHDLOC is set so that the 3 ns minimum delay

between the rising edge of SLI and the falling edge of the

internal SHD signal is not met, the internal H-counter can reset

after only 33 master clock edges (CLI).

Rev. 0 | Page 59 of 88

AD9923A

VD

HD

3ns MIN

CLI

3ns MIN

t_CLIDLY

SHD

INTERNAL

HD

INTERNAL

H-COUNTER

RESET

32.5 CYCLES

H-COUNTER

(PIXEL COUNTER)

X

0

1

2

NOTES

1. INTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE.

2. INTERNAL H-COUNTER IS ALWAYS RESET 32.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE.

3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 33 OR 34 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.

4. SHDLOC = 0 IS SHOWN IN ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 34 CLI RISING EDGES AFTER HD FALLING EDGE.

Figure 77. External VD/HD and Internal H-Counter Synchronization, Slave Mode

VD

H-COUNTER

RESET

HD

NO TOGGLE POSITIONS ALLOWED IN THIS AREA

H-COUNTER

N-28 N-27 N-26 N-25 N-24 N-23 N-22 N-21 N-20 N-19 N-18 N-17 N-16 N-15 N-14 N-13 N-12 N-11 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1

N

0

1

2

3

4

(PIXEL COUNTER)

NOTES

1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 28 PIXELS OF PIXEL 0 LOCATION.

Figure 78. Toggle Position Inhibited Area—Master Mode

VD

HD

H-COUNTER

RESET

NO TOGGLE POSITIONS ALLOWED IN THIS AREA

H-COUNTER

(PIXEL COUNTER)

N-33 N-32 N-31 N-30 N-29 N-28 N-27 N-26 N-25 N-24 N-23 N-22 N-21 N-20 N-19 N-18 N-17 N-16 N-15 N-14 N-13 N-12 N-11 N-10 N-9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1

N

0

1

2

NOTES

1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 28 PIXELS OF PIXEL 0 LOCATION.

Figure 79. Toggle Position Inhibited Area—Slave Mode

Vertical Toggle Position Placement Near Counter Reset

Figure 79 shows the same example for slave mode. The same

restriction applies—the last 28 pixels before the counters are

reset cannot be used. However, the counter reset is delayed with

respect to VD/HD placement; therefore, the inhibited area is

different than it is in master mode.

One additional consideration during the reset of the internal

counters is the vertical toggle position placement. Prior to the

internal counters being reset, there is a region of 28 pixels

during which no toggle positions can be programmed.

It is also recommended that Pixel Location 0 is not used for

toggle positions for the VSG and SUBCK pulses.

As shown in Figure 78, in master mode, the last 28 pixels before

the HD falling edge should not be used for toggle position place-

ment of the XV, VSG, SUBCK, HBLK, PBLK, or CLPOB pulses.

Rev. 0 | Page 60 of 88

AD9923A

to hold a specific value during the Standby 3 mode using

STANDBY MODE OPERATION

Register 0xE2, as detailed in Table 43. The vertical outputs can be

programmed to hold a specific value when OUTCONTROL =

low, or when in Standby 1 or Standby 2 mode, by using

Register 0xF3. The following list provides guidelines for the

mapping of the bits in these registers to the various vertical and

shutter outputs when the device is in one of the three standby

modes, or when OUTCONTROL = low.

The AD9923A contains three standby modes to optimize the

overall power dissipation in various applications. Bits[1:0] of

Register 0x00 control the power-down state of the device:

STANDBY[1:0] = 00 = normal operation (full power)

STANDBY[1:0] = 01 = Standby 1 mode

STANDBY[1:0] = 2 = Standby 2 mode

•

Standby 3 mode takes priority over OUTCONTROL for

determining the output polarities.

These polarities assume OUTCONTROL = high, because

OUTCONTROL = low takes priority over Standby 1 and

Standby 2.

Standby 1 and Standby 2 set H and RG drive strength to

their minimum values (4.3 mA).

VD and HD default to High-Z status when in slave mode

regardless of standby mode or OUTCONTROL status.

STANDBY[1:0] = 3 = Standby 3 mode (lowest power)

Table 42 and Table 43 summarize the operation of each power-

down mode. Note that when OUTCONTROL = LO, it takes

priority over the Standby 1 and Standby 2 modes in determining

the digital output states, but Standby 3 mode takes priority over

OUTCONTROL. Standby 3 has the lowest power consumption,

and can shut down the crystal oscillator circuit between CLI

and CLO. If CLI and CLO are being used with a crystal to

generate the master clock, this circuit is powered down and

there is no clock signal. When returning the device from

Standby 3 mode to normal operation, reset the timing core at

least 500 μs after writing to the STANDBY register (Bits[1:0],

Address 0x00). This allows sufficient time for the crystal circuit

to settle. The vertical and shutter outputs can be programmed

•

This feature is useful during power-up if different polarities are

required by the V-driver and CCD to prevent damage.

It is important to note that when VDR_EN = 0 V, V1 to V13 are

at VM, and SUBCK is at VLL regardless of the state of the value

of the STANDBY and OUTCONTROL registers.

Table 42. Standby Mode Operation

I/O Block

Standby 3 (Default)^{1, 2}

OUTCONTROL = LOW²

No change

Running

Low

High

Low

High

Standby 2^{3, 4}

Off

On

Standby 1^{3, 4}

Only REFT, REFB on

On

Running

Low (4.3 mA)

High (4.3 mA)

Low (4.3 mA)

High (4.3 mA)

Low (4.3 mA)

Running

AFE

Off

Timing Core

Off

CLO Oscillator

Off

CLO

HL

H1

H2

H3

H4

RG

VD⁵

High

High-Z

Low

Running

Low (4.3 mA)

High (4.3 mA)

Low (4.3 mA)

High (4.3 mA)

Low (4.3 mA)

VDHDPOL value

Low

VDHDPOL value

Running

Low

HD

Low

Running

DCLK

D0 to D11

Low

Running

Low

¹To exit Standby 3, write 00 to STANDBY (Bits[1:0], Address 0x00), then reset the timing core after 500 μs to guarantee proper settling of the oscillator.

²Standby 3 mode takes priority over OUTCONTROL for determining the output polarities.

³These polarities assume OUTCONTROL = high, because OUTCONTROL = low takes priority over Standby 1 and Standby 2.

⁴Standby 1 and Standby 2 set H and RG drive strength to their minimum values (4.3 mA).

5

VD and HD default to High-Z status when in slave mode regardless of Standby mode or OUTCONTROL status.

Rev. 0 | Page 61 of 88

AD9923A

Table 43. Standby Mode Operation—Vertical and Shutter Outputs

Output

Standby 3 (Default)^{1, 2}

OUTCONTROL = Low

Standby 2^{3, 4}

Low

Standby 1^{3, 4}

Low

XV1

Low

High

Low

XV2

XV3

XV4

XV5

XV6

XV7

XV8

XV9

XV10

XV11

XV12

XV13

VSG1

VSG2

VSG3

VSG4

VSG5

VSG6

VSG7

VSG8

XSUBCK

VSUB⁵

MSHUT⁵

STROBE⁵

Low

High

Low

High

Low

¹Polarities for vertical and shutter outputs when the AD9923 is in Standby 3 mode are programmable using the STANDBY3POL register, Address 0xE2 (default register

value = 0x000000).

²Bit assignments for the STANDBY3POL[23:0] register (Address 0xE2): (MSB) STROBE, MSHUT, VSUB, XSUBCK, VSG8, VSG7, VSG6, VSG3, VSG5, VSG4, VSG2, VSG1, XV13,

XV12, XV11, XV10, XV9, XV8, XV7, XV6, XV5, XV4, XV3, XV2, and XV1 (LSB).

³Polarities for vertical outputs when the AD9923 is in Standby 1, Standby 2, or if OUTCONTROL = low, are programmable using the STANDBY12POL register,

Address 0xF3 (default register value = 0x3FE000)

⁴Bit assignments for the STANDBY12POL[20:0] register (Address 0xF3): (MSB) XSUBCK, VSG8, VSG7, VSG6, VSG3, VSG5, VSG4, VSG2, VSG1, XV13, XV12, XV11, XV10, XV9,

XV8, XV7, XV6, XV5, XV4, XV3, XV2, and XV1 (LSB).

⁵VSUB, MSHUT, and STROBE polarities for Standby 1, Standby 2, or if OUTCONTROL = low are controlled by STANDBY3POL.

Rev. 0 | Page 62 of 88

AD9923A

mutual inductance, route the complementary signals, H1 and

H2, as symmetrically and close together as possible. The same

should be done for the H3 and H4 signals. Heavier PCB traces

are recommended because of the large transient current

demand placed by the CCD on HL and H1 to H4. If possible,

physically locating the AD9923A closer to the CCD reduces the

inductance on these lines. The routing path should be as direct

as possible from the AD9923A to the CCD.

CIRCUIT LAYOUT INFORMATION

The AD9923A typical circuit connections are shown in Figure 82.

The PCB layout is critical for achieving good image quality from

the AD9923A. All supply pins, particularly the pins for the AVDD,

TCVDD, RGVDD, and HVDD supplies, must be decoupled to

ground with quality, high frequency chip capacitors.

The decoupling capacitors should be as close as possible to the

supply pins and have a very low impedance path to a continuous

ground plane. There should be a bypass capacitor of at least

4.7 μF for each main supply—AVDD, HVDD, and DRVDD—

but this is not necessary for each individual pin. In most

applications, it is easier to share the supply for RGVDD and

HVDD; this requires bypassing each supply pin separately. A

separate 3 V supply can also be used for DRVDD, but it should

be decoupled to the same ground plane as the rest of the chip. A

separate ground for DRVSS is not recommended.

The AD9923A also contains an on-chip oscillator for driving an

external crystal. The maximum crystal frequency that the

AD9923A can support is 36 MHz. Figure 80 shows an example

application using a typical 24 MHz crystal. For the exact values

of the external resistors and capacitors, see the crystal

manufacturer’s data sheet.

~2MΩ

AD9923A

The analog bypass pins (REFT and REFB) should be carefully

decoupled to ground, as close as possible to their respective

pins. The analog input (CCDIN) capacitor should also be

located close to the pin.

~375Ω

CLI (H12)

CLO (J12)

10pF~20pF

24MHz

XTAL

To avoid excessive distortion of the signals, design the HL, H1

to H4, and RG traces to have low inductance. To minimize

Figure 80. Crystal Driver Application

VH

V5V

VDR_EN

VDD

0V

VL

Figure 81. AD9923A Recommended Power up Sequence

Rev. 0 | Page 63 of 88

AD9923A

3

SERIAL INTERFACE (FROM ASIC/DSP)

SYNC (FROM ASIC/DSP)

VERTICAL SYNC (TO/FROM ASIC/DSP)

HORIZONTAL SYNC (TO/FROM ASIC/DSP)

RESETB (FROM ASIC/DSP)

MASTER CLOCK INPUT

OPTIONAL CLOCK OSCILLATOR OUTPUT

(FOR CRYSTAL APPLICATION)

DCLK OUTPUT

12

VSUB OUTPUT (TO CCD BIAS CIRCUIT)

DATA OUTPUTS

STROBE CONTROL OUTPUT

MECHANICAL SHUTTER CONTROL OUTPUT

0.1µF

REFB

REFT

A2

A3

DRVDD

DVDD1

+3V SUPPLY

0.1µF

L4

E1

0.1µF

CCDGND

CCDIN

A5

A6

0.1µF

CCD SIGNAL INPUT

DVDD2

K8

+3V SUPPLY

RG

HL

H4

H3

H2

H1

C10

B11

C11

D11

E11

L8

L7

TEST3

VDR_EN

NC

+3V SUPPLY

J8

V-DRIVER ENABLE

(FROM ASIC/DSP)

K11

K4

F11

6

H, RG OUTPUTS

(TO CCD)

AVSS

A1

B2

B3

B4

B5

A4

TEST1

J7

J5

TEST0

DRVSS

DVSS1

DVSS2

AD9923ABBCZ

(Not to Scale)

L5

AVSS

F2

K9

A11

E6

G2

G3

H9

NC

B6

B7

B9

NC

AVSS

TCVSS

NC

RGVSS

HVSS

A10

D10

+3V ANALOG

SUPPLY

NC

J6

AVDD

J9

A7

B8

J10

J11

K7

L1

L6

L9

4.7µF

6.3V

0.1µF

TCVDD

0.1µF

+3V H,

RG SUPPLY

RGVDD

HVDD

B10

0.1µF

+3V H,

RG SUPPLY

L11

D9

NC = NOT INTERNALLY

CONNECTED

4.7µF

6.3V

VH SUPPLY

VL SUPPLY

+3V SUPPLY

0.1µF

2.2µF

25V

4.7µF

10V

0.1µF

10V

0.1µF

15

VERTICAL OUTPUTS (TO CCD)

SUBCK OUTPUT (TO CCD)

Figure 82. AD9923ABBCZ Typical Circuit Configuration using External Hardware Sync

Rev. 0 | Page 64 of 88

AD9923A

3

SERIAL INTERFACE (FROM ASIC/DSP)

VERTICAL SYNC (TO/FROM ASIC/DSP)

HORIZONTAL SYNC (TO/FROM ASIC/DSP)

RESETB (FROM ASIC/DSP)

MASTER CLOCK INPUT

OPTIONAL CLOCK OSCILLATOR OUTPUT

(FOR CRYSTAL APPLICATION)

DCLK OUTPUT

12

VSUB OUTPUT (TO CCD BIAS CIRCUIT)

DATA OUTPUTS

STROBE CONTROL OUTPUT

MECHANICAL SHUTTER CONTROL OUTPUT

0.1µF

REFB

REFT

A2

A3

DRVDD

DVDD1

+3V SUPPLY

0.1µF

L4

E1

0.1µF

CCDGND

CCDIN

A5

A6

0.1µF

CCD SIGNAL INPUT

DVDD2

K8

+3V SUPPLY

RG

HL

H4

H3

H2

H1

C10

B11

C11

D11

E11

L8

L7

TEST3

VDR_EN

NC

+3V SUPPLY

J8

V-DRIVER ENABLE

(FROM ASIC/DSP)

K11

K4

F11

6

H, RG OUTPUTS

(TO CCD)

AVSS

A1

B2

B3

B4

B5

A4

TEST1

J7

J5

TEST0

DRVSS

DVSS1

DVSS2

AD9923ABBCZ

(Not to Scale)

L5

AVSS

F2

K9

A11

E6

G2

G3

H9

NC

B6

B7

B9

NC

AVSS

TCVSS

NC

RGVSS

HVSS

A10

D10

+3V ANALOG

SUPPLY

NC

J6

AVDD

J9

A7

B8

J10

J11

K7

L1

L6

L9

4.7µF

6.3V

0.1µF

TCVDD

0.1µF

+3V H,

RG SUPPLY

RGVDD

HVDD

B10

0.1µF

+3V H,

RG SUPPLY

L11

D9

NC = NOT INTERNALLY

CONNECTED

4.7µF

6.3V

VH SUPPLY

VL SUPPLY

+3V SUPPLY

0.1µF

2.2µF

25V

4.7µF

10V

0.1µF

10V

0.1µF

15

VERTICAL OUTPUTS (TO CCD)

SUBCK OUTPUT (TO CCD)

Figure 83. Typical Circuit Configuration When Using Software Sync Function

Rev. 0 | Page 65 of 88

AD9923A

with 0s during the serial write operation. If fewer than 28 data

bits are written, the register is not updated with new data.

SERIAL INTERFACE TIMING

All of the AD9923A internal registers are accessed through a

3-wire serial interface. Each register consists of a 12-bit address

and a 28-bit data-word. Both the address and data-word are

written by starting with the LSB. To write to each register, a 40-bit

operation is required, as shown in Figure 84. Although many

data-words are fewer than 28 bits wide, all 28 bits must be

written for each register. For example, if the data-word is only

20 bits wide, the upper 8 bits are don’t cares and must be filled

Figure 85 shows a more efficient way to write to the registers,

using the AD9923A address auto-increment capability. Using

this method, the lowest desired address is written first, followed

by multiple 28-bit data-words. Each data-word is automatically

written to the address of the next highest register. By eliminating

the need to write each address, faster register loading is achieved.

Continuous write operations can start with any register location.

12-BIT ADDRESS

28-BIT DATA

SDI

A0

A1

A2

A3

A4

A5

A6

A8

A9 A10 A11 D0

D1

D2

D3

D25 D26 D27

A7

t_DS

t_DH

SCK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

38

39

40

t_LS

t_LH

SL

NOTES

1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK MAY IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.

2. ALL 40 BITS MUST BE WRITTEN: 12 BITS FOR ADDRESS AND 28 BITS FOR DATA-WORD.

3. IF THE DATA-WORD IS <28 BITS, 0s MUST BE USED TO COMPLETE THE 28-BIT DATA-WORD LENGTH.

4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON THE

PARTICULAR REGISTER WRITTEN TO. SEE THE UPDATING OF NEW REGISTER VALUES SECTION FOR MORE INFORMATION.

Figure 84. Serial Write Operation

DATA FOR STARTING

REGISTER ADDRESS

DATA FOR NEXT

REGISTER ADDRESS

SDI

A0

A1

A2

A10 A11 D0

D1

D26 D27 D0

D1

D26 D27 D0

A3

D1

D2

SCK

SL

70

71

1

2

3

4

11

12

13

14

39

40

41

42

67

68

69

NOTES

1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.

2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 28-BIT DATA-WORDS.

3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 28-BIT DATA-WORD (ALL 28 BITS MUST BE WRITTEN).

4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER IS LOADED.

Figure 85. Continuous Serial Write Operation

Rev. 0 | Page 66 of 88

AD9923A

number of V-sequences. Each V-sequence occupies 20 register

addresses, and each field occupies 12 register addresses.

LAYOUT OF INTERNAL REGISTERS

The AD9923A address space is divided into two register areas,

as illustrated in Figure 86. In the first area, Address 0x00 to

Address 0x91 contain the registers for the AFE, miscellaneous

functions, VD/HD parameters, timing core, CLPOB masking,

SG patterns, shutter functions, and memory configuration. The

second area of the address space, beginning at Address 0x400,

consists of the registers for the V-pattern groups, V-sequences,

and fields. This is a configurable set of registers; the user can

decide how many V-pattern groups, V-sequences, and fields are

used in a particular design. Therefore, the addresses for these

registers vary, depending on the number of V-patterns and

V-sequences chosen.

The starting address for a V-sequence is equal to 0x400 plus the

number of V-pattern groups times 40. The starting address for a

field is equal to the starting address of a V-sequence plus the

number of V-sequences times 20. The VPAT, VSEQ, and field

registers must occupy a continuous block of addresses.

Figure 87 shows an example with three V-pattern groups, four

V-sequences, and two fields. The starting address for the V-pattern

groups is 0x400. Because VPAT_NUM = 3, the V-pattern groups

occupy 120 address locations. The start of the V-sequence register

is 0x400 + 120 = 0x478. With VSEQ_NUM = 3, the V-sequences

occupy 60 address locations. Therefore, the field registers begin at

0x448 + 60 = 0x4B4.

Register 0x90 (VPAT_NUM) and Register 0x91 (VSEQ_NUM)

specify the total number of V-pattern groups and V-sequences

used. The starting address for the V-pattern groups is 0x400.

The starting address for a V-sequence is based on the number

of V-pattern groups used, with each V-pattern group occupying

40 register addresses. The starting address for a field register

depends on both the number of V-pattern groups and the

The AD9923A address space contains many unused addresses.

Undefined addresses between Address 0x00 and Address 0x399

should not be written to, or the AD9923A might operate

incorrectly. Continuous register writes should be performed

carefully to avoid writing to undefined registers.

CONFIGURABLE REGISTER DATA

FIXED REGISTER AREA

ADDR 0x00

ADDR 0x400

AFE REGISTERS

ADDR 0x10

MISCELLANEOUS REGISTERS

V-PATTERN GROUPS

(EACH GROUP USES 40 REGISTERS)

ADDR 0x20

VD/HD REGISTERS

ADDR 0x30

TIMING CORE REGISTERS

ADDR 0x40

VSEQ START

FIELD START

MAX 0x7FF

CLPOB MASK REGISTERS

ADDR 0x50

V-SEQUENCES

(EACH VSEQ USES 20 REGISTERS)

SG PATTERN REGISTERS

ADDR 0x60

SHUTTER CONTROL REGISTERS

ADDR 0x90

FIELDS

CONFIGURE MEMORY USING

VPAT_NUM AND VSEQ_NUM

ADDR 0x92

(EACH FIELD USES 12 REGISTERS)

INVALID DO NOT ACCESS

ADDR 0xFF

Figure 86. Layout of AD9923A Registers

ADDR 0x400

3 V-PATTERN GROUPS

(40 × 3 = 120 REGISTERS)

ADDR 0x478

ADDR 0x4B4

4 V-SEQUENCES

(20 × 3 = 60 REGISTERS)

2 FIELDS

(12 × 2 = 24 REGISTERS)

ADDR 0x4CC

MAX 0x7FF

UNUSED MEMORY

Figure 87. Example of Register Configuration

Rev. 0 | Page 67 of 88

AD9923A

•

SCP Updated—All V-pattern and V-sequence registers are

updated at the next SCP where they will be used. For

example, in Figure 88, this field has selected Region 1 to

use V-Sequence 3 for the vertical outputs; therefore, a write

to a V-Sequence 3 or V-pattern group register, which is

referenced by V-Sequence 3, is updated at SCP 1. If there

are multiple writes to the same register, only the last one

before SCP1 is updated. Likewise, a register write to a

V-Sequence 5 register is updated at SCP 2, and a register

write to a V-Sequence 8 register is updated at SCP 3.

UPDATING NEW REGISTER VALUES

The AD9923A internal registers are updated at different times,

depending on the particular register. Table 44 summarizes the

four types of register updates. The register listing (Table 45

through Table 57) also contain a column with update type to

identify when each register is updated:

•

SCK Updated—Some registers are updated when the 28^th

data bit (D27) is written. These registers are used for

functions, such as power-up and reset, that do not require

gating with the next VD boundary.

Table 44. Register Update Locations

•

VD Updated—Many of the registers are updated at the

next VD falling edge. By updating these values at the next

VD edge, the current field is not corrupted, and the new

register values are applied to the next field. The VD update

can be further delayed, past the VD falling edge, by using

the UPDATE register (Address 0x18). This delays the

VD-updated register updates to any desired HD line in the

field. Note that the field registers are not affected by the

UPDATE register.

Update

Type

Description

SCK

Register is immediately updated when the 28^thdata

bit (D27) is written.

VD

Register is updated at the VD falling edge. VD

updated registers can be delayed further by using the

UPDATE register at Address 0x18. Field registers are

not affected by the UPDATE register.

Register is updated at the HD falling edge at the end

of the SG active line.

SG

SCP

Register is updated at the next SCP when the register

is used.

•

SG Updated—A few shutter registers are updated at the

HD falling edge at the end of an SG active line. These

registers control the SUBCK signal; therefore, the SUBCK

output is not updated until the SG line is complete.

SCK

VD

SG

UPDATED

SCP

UPDATED

UPDATED UPDATED

SERIAL

WRITE

VD

HD

SGLINE

VSG

USE VSEQ2

USE VSEQ3

REGION 1

USE VSEQ5

REGION 2

USE VSEQ8

REGION 3

V1A TO V10

REGION 0

SCP 0

SCP 1

SCP 2

SCP 3

Figure 88. Register Update Locations (See Table 44 for Definitions)

Rev. 0 | Page 68 of 88

AD9923A

COMPLETE REGISTER LISTING

When an address contains less than 28 data bits, all remaining bits must be written as 0s.

Table 45. AFE Registers

Address Data

Default

Value

Update

Type

(Hex)

Bits

Name

Description

00

[1:0]

3

SCK

STANDBY

Standby modes.

0: normal operation.

1: Standby 1 mode.

2: Standby 2 mode.

3: Standby 3 mode.

[2]

1

0

CLPENABLE

CLPSPEED

FASTUPDATE

PBLK_LVL

DCBYP

0: disable OB clamp.

1: enable OB clamp.

[3]

0: select normal OB clamp settling.

1: select fast OB clamp settling.

0: ignore VGA update.

1: very fast clamping when VGA is updated.

0: blank data outputs to 0 during PBLK.

1: blank data outputs to programmed clamp level during PBLK.

0: enable input dc-restore circuit during PBLK.

1: disable input dc-restore circuit during PBLK.

[4]

[5]

[6]

[15:11]

XSUBCNT_MUX Selects which internal signal is used for the XSUBCNT signal.

0: assign XV6 to XSUBCNT.

1: assign XV8 to XSUBCNT.

2: assign XV9 to XSUBCNT.

3: assign XV10 to XSUBCNT.

4: assign VSG5 to XSUBCNT.

5: assign VSG6 to XSUBCNT.

6: assign VSG7 to XSUBCNT.

7: assign VSG8 to XSUBCNT.

8: assign VSG2 to XSUBCNT.

9: assign VSG3 to XSUBCNT.

10: assign VSG4 to XSUBCNT.

11: assign VSG1 to XSUBCNT.

12: assign XV13 to XSUBCNT.

13: assign VSUB to XSUBCNT.

14: assign MSHUT to XSUBCNT.

15: assign STROBE to XSUBCNT.

16: assign XV1 to XSUBCNT.

17: assign XV2 to XSUBCNT.

18: assign XV3 to XSUBCNT.

19: assign XV4 to XSUBCNT.

20: assign XV5 to XSUBCNT.

21: assign XV7 to XSUBCNT.

22: assign XV11 to XSUBCNT.

23: assign XV12 to XSUBCNT.

24: assign SHUT0 to XSUBCNT.

25: assign SHUT1 to XSUBCNT.

26: assign SHUT2 to XSUBCNT.

27: assign SHUT3 to XSUBCNT.

28: assign FG_TRIG to XSUBCNT.

29: invalid setting.

30: tie XSUBCNT high.

31: tie XSUBCNT low.

Rev. 0 | Page 69 of 88

AD9923A

Address Data

Default

Value

Update

Type

(Hex)

Bits

Name

Description

01

[0]

0

SCK

DOUTDISABLE

0: data outputs are driven.

1: data outputs are three-stated.

0: latch data outputs using DOUT PHASE register setting.

1: output latch is transparent.

[1]

[2]

DOUTLATCH

GRAYEN

0: straight binary encoding of ADC digital output data.

1: enable gray encoding of ADC digital output data.

[3]

1

TEST

Set to 1.

04

[1:0]

VD

CDSGAIN

CDS gain setting.

0: −3 dB.

1: 0 dB.

2: +3 dB.

3: +6 dB.

05

06

[9:0]

F

VD

VGAGAIN

VGA gain. 6 dB to 42 dB (0.035 dB per step).

Optical black clamp level. 0 LSB to 256 LSB (0.25 LSB per step).

1EC

CLAMPLEVEL

Rev. 0 | Page 70 of 88

AD9923A

Table 46. Miscellaneous Registers

Address Data

Default

Value

Update

Type

(Hex)

Bits

Name

Description

10

[0]

0

1

SCK

SW_RST

Software reset. Bit resets to 0.

1: reset Register 0x00 to Register 0x91 to default values.

0: make all outputs dc inactive.

11

12

[0]

VD

OUTCONTROL

SYNCENABLE

1: enable outputs at next VD edge.

SCK

0: configure Ball G7 as an output signal, determined by

Register 0x12, Bits[9:8].

1: external synchronization enable (configure Ball G7 as SYNC input).

Test mode only. Must be set to 0.

When SYNCENABLE = 0, selects which signal is output on the SYNC pin.

0: CLPOB.

[7:1]

[9:8]

0

TEST

OUTPUTPBLK

1: PBLK.

2: GPO (from Register 0x1A).

3: TESTOUT (from shutter registers).

SYNC active polarity.

0: active low.

1: active high.

13

14

15

16

17

[0]

0

SCK

SYNCPOL

SYNCSUSPEND

TGCORE_RSTB

OSC_RST

Suspends clocks during SYNC active pulse.

0: don’t suspend.

1: suspend.

Timing core reset bar.

0: reset TG core.

1: resume operation.

CLO oscillator reset.

0: oscillator in power-down state.

1: resume oscillator operation.

Test mode only. Must be set to 0.

[7:0]

[8]

0

TEST1

TEST2

18

19

[11:0]

VD

UPDATE

Serial update line. Sets the HD line within the field to update the VD

updated registers.

[0]

0

SCK

PREVENTUP

GPO

Prevents the updating of the VD updated registers.

0: normal update.

1: prevent update of VD updated registers.

1A

0

VD

General-purpose output (GPO) value when SYNCENABLE = 0 and

OUTPUTPBLK = 2.

0: GPO is low at next VD edge.

1: GPO is high at next VD edge.

Table 47. VD/HD Registers

Address

(Hex)

Data

Bits

Default

Value

Update

Type

Name

Description

20

21

22

[0]

0

SCK

VD

MASTER

VD/HD master or slave mode.

0: slave mode.

1: master mode.

[0]

0

VDHDPOL

VD/HD active polarity.

0: low.

1: high.

[12:0]

[24:13]

0

HDRISE

VDRISE

Rising edge location for HD.

Rising edge location for VD.

Rev. 0 | Page 71 of 88

AD9923A

Table 48. Timing Core Registers

Address

(Hex)

Data

Bits

Default

Value

Update

Type

Name

Description

30

[0]

0

SCK

CLIDIVIDE

Divide CLI input frequency by 2.

0: no divide.

1: divide by 2.

31

[5:0]

[13:8]

[16]

0

20

1

SCK

H1POSLOC

H1NEGLOC

H1H2POL

H1 rising edge location.

H1 falling edge location.

H1/H2 polarity control.

0: inverse of convention in Figure 18.

1: no inversion.

32

33

34

35

[5:0]

[13:8]

[16]

0

20

1

SCK

VD

H3POSLOC

H3NEGLOC

H3H4POL

H3 rising edge location.

H3 falling edge location.

H3/H4 polarity control.

0: inverse of convention in Figure 18.

1: no inversion.

[5:0]

[13:8]

[16]

0

20

1

HLPOSLOC

HLNEGLOC

HLPOL

HL rising edge location.

HL falling edge location.

HL polarity control.

0: inverse of convention in Figure 18.

1: no inversion.

[5:0]

[13:8]

[16]

0

10

1

RGPOSLOC

RGNEGLOC

RGPOL

RG rising edge location.

RG falling edge location.

RG polarity control.

0: inverse of convention in Figure 18.

1: no inversion.

[0]

0

H1H2RETIME Retime HBLK for H1/H2 to the internal H1 clock. The preferred setting is 1,

which adds one cycle of delay to the HBLK toggle positions.

0: no retime.

1: retime.

[1]

[2]

[3]

0

H3H4RETIME Retime HBLK for H3/H4 to the internal H3 clock.

HLRETIME

HLHBLKEN

Retime HBLK for HL to the internal HL clock.

Enable HBLK for HL output.

0: disable.

1: enable.

[6:4]

0

HBLKWIDTH

Controls H1 to H4 width during HBLK as a fraction of pixel rate.

0: same frequency as pixel rate.

1: 1/2 pixel frequency, that is, it doubles the H1 to H4 pulse width.

2: 1/4 pixel frequency.

3: 1/6 pixel frequency.

4: 1/8 pixel frequency.

5: 1/10 pixel frequency.

6: 1/12 pixel frequency.

7: 1/14 pixel frequency.

H1 drive strength.

0: off.

36

[3:0]

1

SCK

H1DRV

1: 4.3 mA.

2: 8.6 mA.

3: 12.9 mA.

4: 17.2 mA.

5: 21.5 mA.

6: 25.8 mA.

7: 30.1 mA.

Rev. 0 | Page 72 of 88

AD9923A

Address

(Hex)

Data

Bits

Default

Value

Update

Type

Name

Description

[7:4]

1

H2DRV

H3DRV

H4DRV

HLDRV

RGDRV

SHPLOC

SHDLOC

H2 drive strength.

H3 drive strength.

H4 drive strength.

HL drive strength.

RG drive strength.

SHP sample location.

SHD sample location.

[11:8]

[15:12]

[19:16]

[23:20]

[5:0]

37

38

24

0

SCK

[13:8]

[5:0]

0

DOUTPHASE DOUT (internal signal) phase control.

[7:6]

0

Unused

Must be set to 0.

[8]

0

DCLKMODE

DCLK mode.,

0: DCLK tracks DOUT phase.

1: DCLK phase is fixed.

[10:9]

[11]

2

0

DOUTDELAY Data output delay (t_OD) with respect to DCLK rising edge.

0: no delay.

1: ~4 ns.

2: ~8 ns.

3: ~12 ns.

DCLKINV

Invert DCLK output.

0: no inversion.

1: inversion of DCLK.

Table 49. CLPOB and PBLK Masking Registers

Address

(Hex)

Data

Bits

Update

Type

Default Value

Name

Description

40

41

42

43

44

45

[11:0]

[12]

[24:13]

[11:0]

[12]

[24:13]

[11:0]

[12]

[24:13]

[11:0]

[12]

[24:13]

[11:0]

[12]

[24:13]

[11:0]

[12]

FFF

0

FFF

0

FFF

0

FFF

0

FFF

0

FFF

0

VD

CLPOBMASKSTART1

Unused

CLPOBMASKEND1

CLPOBMASKSTART2

Unused

CLPOBMASKEND2

CLPOBMASKSTART3

Unused

CLPOBMASKEND3

PBLKMASKSTART1

Unused

PBLKMASKEND1

PBLKMASKSTART12

Unused

PBLKMASKEND2

PBLKMASKSTART3

Unused

CLPOB Masking Start Line 1.

Must be set to 0.

CLPOB Masking End Line 1.

CLPOB Masking Start Line 2.

Must be set to 0.

CLPOB Masking End Line 2.

CLPOB Masking Start Line 3.

Must be set to 0.

CLPOB Masking End Line 3.

PBLK Masking Start Line 1.

Must be set to 0.

PBLK Masking End Line 1.

PBLK Masking Start Line 2.

Must be set to 0.

PBLK Masking End Line 2.

PBLK Masking Start Line 3.

Must be set to 0.

[24:13]

FFF

PBLKMASKEND3

PBLK Masking End Line 3.

Rev. 0 | Page 73 of 88

AD9923A

Table 50. SG Pattern Registers

Address Data

Default Update

(Hex)

Bits

Value

Type

Name

Description

50

[0]

1

VD

SGPOL_0

Start polarity for SGPattern 0.

0: low.

1: high.

[1]

[2]

[3]

[4]

[5]

[6]

[7]

1

SGPOL_1

SGPOL_2

SGPOL_3

SGPOL_4

SGPOL_5

SGPOL_6

SGPOL_7

Start polarity for SGPattern 1.

Start polarity for SGPattern 2.

Start polarity for SGPattern 3.

Start polarity for SGPattern 4.

Start polarity for SGPattern 5.

Start polarity for SGPattern 6.

Start polarity for SGPattern 7.

Pattern 0. Toggle Position 1.

Pattern 0. Toggle Position 2.

Pattern 1. Toggle Position 1.

Pattern 1. Toggle Position 2.

Pattern 2. Toggle Position 1.

Pattern 2. Toggle Position 2.

Pattern 3. Toggle Position 1.

Pattern 3. Toggle Position 2.

Pattern 4. Toggle Position 1.

Pattern 4. Toggle Position 2.

Pattern 5. Toggle Position 1.

Pattern 5. Toggle Position 2.

Pattern 6. Toggle Position 1.

Pattern 6. Toggle Position 2.

Pattern 7. Toggle Position 1.

Pattern 7. Toggle Position 2.

51

52

53

54

55

56

57

58

59

[12:0]

1FFF

VD

SGTOG1_0

SGTOG2_0

SGTOG1_1

SGTOG2_1

SGTOG1_2

SGTOG2_2

SGTOG1_3

SGTOG2_3

SGTOG1_4

SGTOG2_4

SGTOG1_5

SGTOG2_5

SGTOG1_6

SGTOG2_6

SGTOG1_7

SGTOG2_7

SGMASK_BYP

[25:13] 1FFF

[12:0] 1FFF

[25:13] 1FFF

[12:0] 1FFF

[25:13] 1FFF

[12:0] 1FFF

[25:13] 1FFF

[12:0] 1FFF

[25:13] 1FFF

[12:0] 1FFF

[25:13] 1FFF

[12:0] 1FFF

[25:13] 1FFF

[12:0] 1FFF

[25:13] 1FFF

[7:0]

0

SCK

SGMASK override. These values override the VSG mask value located in the

field registers.

[8]

0

SGMASK_BYP_EN SGMASK override enable. Must be set to 1 to enable override.

Rev. 0 | Page 74 of 88

AD9923A

Table 51. Shutter Control Registers

Address Data

Default

Value

Update

Type

(Hex)

Bits

Name

Description

60

[2:0]

0

1

2

3

0

VD

VSUB_CTRL

Selects which internal signal is used for the VSUB output pin.

0: use SHUT0 parameters (Register 0x06D to Register 0x071).

1: use SHUT1 parameters (Register 0x072 to Register 0x076).

2: use SHUT2 parameters (Register 0x077 to Register 0x07B).

3: use SHUT3 parameters (Register 0x07C to Register 0x080).

4: use VSUB0_MUX output.

5: use VSUB1_MUX output.

6: invalid setting.

7: use SHUT1_SHUT2_MUX output.

See Register 0xEB, Bits[15,13:12] for VSUB0_MUX, VSUB1_MUX,

and SHUT1_SHUT2_MUX.

[5:3]

[8:6]

[11:9]

[7:0]

MSHUT_CTRL

STROBE_CTRL

TESTO_CTRL

TRIGGER

Selects which internal signal is used for the MSHUT output pin.

0: use SHUT0 parameters.

1: use SHUT1 parameters.

2: use SHUT2 parameters.

3: use SHUT3 parameters.

4: use VSUB0_MUX output.

5: use VSUB1_MUX output.

6: invalid setting.

7: use SHUT1_SHUT2_MUX output.

See Register 0xEB, Bits[15,13:12] for VSUB0_MUX, VSUB1_MUX, and

SHUT1_SHUT2_MUX.

Selects which internal signal is used for the STROBE output pin.

0: use SHUT0 parameters.

1: use SHUT1 parameters.

2: use SHUT2 parameters.

3: use SHUT3 parameters.

4: use VSUB0_MUX output.

5: use VSUB1_MUX output.

6: invalid setting.

7: use SHUT1_SHUT2_MUX output.

See Register 0xEB, Bits[15,13:12] for VSUB0_MUX, VSUB1_MUX, and

SHUT1_SHUT2_MUX.

Selects which internal signal is used for the TESTO signal.

0: use SHUT0 parameters.

1: use SHUT1 parameters.

2: use SHUT2 parameters.

3: use SHUT3 parameters.

4: use VSUB0_MUX output.

5: use VSUB1_MUX output.

6: invalid setting.

7: use SHUT1_SHUT2_MUX output.

See Register 0xEB, Bits[15,13:12] for VSUB0_MUX, VSUB1_MUX, and

SHUT1_SHUT2_MUX.

61

VD

Trigger for exposure/readout operation. Set bits high to trigger.

[0]: SHUT0.

[1]: SHUT1.

[2]: SHUT2.

[3]: SHUT3.

[4]: VSUB0.

[5]: VSUB1.

Rev. 0 | Page 75 of 88

AD9923A

Address Data

Default

Value

Update

Type

(Hex)

Bits

Name

Description

[6]: EXPOSURE.

[7]: READOUT.

Note that if EXPOSURE and READOUT are triggered together,

READOUT occurs immediately after the exposure is complete.

62

63

[2:0]

2

0

VD

READOUTNUM

EXPOSURENUM

Number of fields to suppress the SUBCK pulses during READOUT.

[11:0]

Number of fields to suppress the SUBCK and VSG pulses during

exposure.

[12]

0

VDHDOFF

Disable VD and HD during exposure.

0: enable.

1: disable.

64

65

[11:0]

[23:12]

[1:0]

0

SG

SUBSUPPRESS

SUBCKNUM

SUBCKMASK

Number of SUBCK pulses to suppress after VSG line.

Number of SUBCK pulses per field.

Additional masking of SUBCK output.

0: no mask.

1: begin mask on VD edge.

2: mask using internal SHUT3 signal.

3: same as 1 and 2 (1 has priority).

SUBCK pulse start polarity.

First SUBCK Pulse Toggle Position 1.

First SUBCK Pulse Toggle Position 2.

Second SUBCK Pulse Toggle Position 1.

Second SUBCK Pulse Toggle Position 2.

VSUB0 readout mode.

66

67

[0]

1

SG

SUBCKPOL

[12:0]

[25:13]

[12:0]

[25:13]

[0]

1FFF

0

SUBCK1TOG1

SUBCK1TOG2

SUBCK2TOG1

SUBCK2TOG2

VSUB0_MODE

68

69

SG

VD

0: Mode 0.

1: Mode 1.

[1]

0

VSUB0_KEEPON VSUB0 keep-on mode.

0: turn VUB0 off after READOUT or at next VD.

1: keep VSUB0 active beyond READOUT, until reset to 0.

6A

6B

[11:0]

[12]

[13]

[0]

0

1

0

VD

VSUB0_ON

Unused

VSUB0POL

VSUB1_MODE

VSUB0 on position.

Must be set to 0.

VSUB0 start polarity.

VSUB1 readout mode.

0: Mode 0.

1: Mode 1.

[1]

0

VSUB1_KEEPON VSUB1 keep on mode.

1: keep VSUB1 active beyond readout.

VSUB1 on position.

6C

6D

[11:0]

[12]

[13]

[0]

0

1

0

VD

VSUB1_ON

Unused

Must be set to 0.

VSUB1POL

SHUT0_ON

VSUB1 start polarity.

SHUT0 manual control of signal.

0: off.

1: on.

[1]

[2]

1

0

SHUT0POL

SHUT0_MAN

SHUT0 active polarity. 1: on state produces high output.

SHUT0 manual control enable.

0: disable.

1: enable manual control.

6E

6F

[11:0]

[12]

[25:13]

[11:0]

0

VD

SHUT0_ON_FD

SHUT0_ON_LN

Unused

SHUT0_ON_PX

SHUT0_OFF_FD

SHUT0 field on position. Ignored during manual or nonshutter mode.

SHUT0 line on position.

Must be set to 0.

VD

SHUT0 pixel on position.

70

SHUT0 field off position. Ignored during manual or nonshutter mode.

Rev. 0 | Page 76 of 88

AD9923A

Address Data

Default

Value

Update

Type

(Hex)

Bits

Name

Description

71

[11:0]

[12]

[25:13]

[0]

0

VD

SHUT0_OFF_LN

Unused

SHUT0_OFF_PX

SHUT1_ON

SHUT0 line off position.

Must be set to 0.

SHUT0 pixel off position.

SHUT1 manual control of signal.

0: off.

VD

72

1: on.

[1]

[2]

1

0

SHUT1POL

SHUT1_MAN

SHUT1 active polarity. 1 = on state produces high output.

SHUT1 manual control enable.

0: disable.

1: enable manual control.

73

74

[11:0]

[12]

[25:13]

[11:0]

[12]

0

VD

SHUT1_ON_FD

SHUT1_ON_LN

Unused

SHUT1_ON_PX

SHUT1_OFF_FD

SHUT1_OFF_LN

Unused

SHUT1 field on position. Ignored during manual or nonshutter mode.

SHUT1 line on position.

Must be set to 0.

SHUT1 pixel on position.

VD

75

76

SHUT1 field off position. Ignored during manual or nonshutter mode.

SHUT1 line off position.

Must be set to 0.

SHUT1 pixel off position.

[25:13]

[0]

VD

SHUT1_OFF_PX

SHUT2_ON

77

SHUT2 manual control of signal.

0: off.

1: on.

[1]

[2]

1

0

SHUT2POL

SHUT2_MAN

SHUT2 active polarity. 1: on state produces high output.

SHUT2 manual control enable.

0: disable.

1: enable manual control.

78

79

[11:0]

[12]

[25:3]

[11:0]

[12]

0

VD

SHUT2_ON_FD

SHUT2_ON_LN

Unused

SHUT2_ON_PX

SHUT2_OFF_FD

SHUT2_OFF_LN

Unused

SHUT2 field on position. Ignored during manual or nonshutter mode.

SHUT2 line on position.

Must be set to 0.

SHUT2 pixel on position.

VD

7A

7B

SHUT2 field off position. Ignored during manual or nonshutter mode.

SHUT2 line off position.

Must be set to 0.

SHUT2 pixel off position.

[25:13]

[0]

VD

SHUT2_OFF_PX

SHUT3_ON

7C

SHUT3 manual control of signal.

0: off.

1: on.

[1]

[2]

1

0

SHUT3POL

SHUT3_MAN

SHUT3 active polarity. 1: on state produces high output.

SHUT3 manual control enable.

0: disable.

1: enable manual control.

7D

7E

[11:0]

[12]

[25:13]

[11:0]

[12]

0

VD

SHUT3_ON_FD

SHUT3_ON_LN

Unused

SHUT3_ON_PX

SHUT3_OFF_FD

SHUT3_OFF_LN

Unused

SHUT3 field on position. Ignored during manual or nonshutter mode.

SHUT3 line on position.

Must be set to 0.

VD

SHUT3 pixel on position.

7F

80

SHUT3 field off position. Ignored during manual or nonshutter mode.

SHUT3 line off position.

Must be set to 0.

[25:13]

VD

SHUT3_OFF_PX

SHUT3 pixel off position.

Rev. 0 | Page 77 of 88

AD9923A

Table 52. Memory Configuration Registers

Address Data

Default

Value

(Hex)

Bits

[4:0]

Update Name

Description

90

0

VD

VPAT_NUM

VSEQ_NUM

Total number of V-pattern groups.

Total number of V-sequences.

91

Table 53. Standby Polarity, Shutter Mux, and FG_TRIG Registers

Address Data

Default

Value

(Hex)

Bits

Update Name

SCK STANDBY3POL

Description

E2

[24:0]

0

Programmable polarities for vertical and shutter outputs during Standby 3.

[0] = XV1 polarity.

[1] = XV2 polarity.

[2] = XV3 polarity.

[3] = XV4 polarity.

[4] = XV5 polarity.

[5] = XV6 polarity.

[6] = XV7 polarity.

[7] = XV8 polarity.

[8] = XV9 polarity.

[9] = XV10 polarity.

[10] = XV11 polarity.

[11] = XV12 polarity.

[12] = XV13 polarity.

[13] = VSG1 polarity.

[14] = VSG2 polarity.

[15] = VSG3 polarity.

[16] = VSG4 polarity.

[17] = VSG5 polarity.

[18] = VSG6 polarity.

[19] = VSG7 polarity.

[20] = VSG8 polarity.

[21] = XSUBCK polarity.

[22] = VSUB polarity.

Note: controls polarity for Standby 1, Standby 2, Standby 3, or if

OUTCONTROL = low.

[23] = MSHUT polarity.

Note: controls polarity for Standby 1, Standby 2, Standby 3, or if

OUTCONTROL = low.

[24] = STROBE polarity.

Note: controls polarity for Standby 1, Standby 2, Standby 3, or if

OUTCONTROL = low.

E6

[0]

0

SCK

VCNT_RUN

0: counters behave the same as AD9923 in sweep region.

1: enables additional toggles after last repeat of sweep region.

Required start-up register; must be set to 0x60

Test register.

0: use VSUB0, 1: Use SHUT0 ^ VSUB0.

0: use VSUB1, 1: Use SHUT0 ^ VSUB1.

Test register. Set to 0.

EA

EB

[9:0]

[11:0]

[12]

[13]

[14]

[15]

0

SCK

TEST3

300

0

TEST4

VSUB0_MUX

VSUB1_MUX

TEST5

SHUT1_SHUT2_MUX 0: use SHUT0 ^ SHUT1.

1: Use SHUT0 ^ SHUT2.

F1

[3:0]

0

SCK

FG_TRIGEN

FG_TRIG operation enable and field count selection.

[2:0] Selects field count for pulse (based on mode field counter).

[3] = 1 to enable FG_TRIG signal output.

Rev. 0 | Page 78 of 88

AD9923A

Address Data

Default

Value

(Hex)

Bits

Update Name

Description

F3

[21:0]

3FE000 SCK

STANDBY12POL

Programmable polarities for V-outputs and XSUBCK during Standby 1,

Standby 2, or if OUTCONTROL = low.

[0] = XV1 polarity.

[1] = XV2 polarity.

[2] = XV3 polarity.

[3] = XV4 polarity.

[4] = XV5 polarity.

[5] = XV6 polarity.

[6] = XV7 polarity.

[7] = XV8 polarity.

[8] = XV9 polarity.

[9] = XV10 polarity.

[10] = XV11 polarity.

[11] = XV12 polarity.

[12] = XV13 polarity.

[13] = VSG1 polarity.

[14] = VSG2 polarity.

[15] = VSG3 polarity.

[16] = VSG4 polarity.

[17] = VSG5 polarity.

[18] = VSG6 polarity.

[19] = VSG7 polarity.

[20] = VSG8 polarity.

[21] = XSUBCK polarity.

Table 54. Mode Register: VD Updated

Address (Binary)

12b10_xx_xxxx_xxxx

(Set A11, A10 = 10)

Data Bits

[37:0]

Default Value

Description

0

A11, A10 set to 10, remaining A9 to A0 bits used for D37:D28.

Number of fields (maximum of seven).

Selected field for Field 7.

Selected field for Field 6.

Selected field for Field 5.

Selected field for Field 4.

Selected field for Field 3.

Selected field for Field 2.

[37:35]

[34:30]

[29:25]

[24:20]

[19:15]

[14:10]

[9:5]

[4:0]

Selected field for Field 1.

Rev. 0 | Page 79 of 88

AD9923A

Unused XV-channels must have toggle positions programmed to maximum values. For example, if XV1 to XV8 are used, XV9 to XV12

must have all toggle positions set to maximum values. This prevents unpredictable behavior because the default values are unknown.

Table 55. V-Pattern Group 0 (VPAT0) Registers

Address

(Hex)

Default

Value

Update

Type

Data Bits

[12:0]

Name

Description

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

Undefined

SCP

XV1TOG1

XV1TOG2

XV1TOG3

XV1TOG4

XV2TOG1

XV2TOG2

XV2TOG3

XV2TOG4

XV3TOG1

XV3TOG2

XV3TOG3

XV3TOG4

XV4TOG1

XV4TOG2

XV4TOG3

XV4TOG4

XV5TOG1

XV5TOG2

XV5TOG3

XV5TOG4

XV6TOG1

XV6TOG2

XV6TOG3

XV6TOG4

XV7TOG1

XV7TOG2

XV7TOG3

XV7TOG4

XV8TOG1

XV8TOG2

XV8TOG3

XV8TOG4

XV9TOG1

XV9TOG2

XV9TOG3

XV9TOG4

XV10TOG1

XV10TOG2

XV10TOG3

XV10TOG4

XV11TOG1

XV11TOG2

XV11TOG3

XV11TOG4

XV12TOG1

XV12TOG2

XV1 Toggle Position 1.

XV1 Toggle Position 2.

XV1 Toggle Position 3.

XV1 Toggle Position 4.

XV2 Toggle Position 1.

XV2 Toggle Position 2.

XV2 Toggle Position 3.

XV2 Toggle Position 4.

XV3 Toggle Position 1.

XV3 Toggle Position 2.

XV3 Toggle Position 3.

XV3 Toggle Position 4.

XV4 Toggle Position 1.

XV4 Toggle Position 2.

XV4 Toggle Position 3.

XV4 Toggle Position 4.

XV5 Toggle Position 1.

XV5 Toggle Position 2.

XV5 Toggle Position 3.

XV5 Toggle Position 4.

XV6 Toggle Position 1.

XV6 Toggle Position 2.

XV6 Toggle Position 3.

XV6 Toggle Position 4.

XV7 Toggle Position 1.

XV7 Toggle Position 2.

XV7 Toggle Position 3.

XV7 Toggle Position 4.

XV8 Toggle Position 1.

XV8 Toggle Position 2.

XV8 Toggle Position 3.

XV8 Toggle Position 4.

XV9 Toggle Position 1.

XV9 Toggle Position 2.

XV9 Toggle Position 3.

XV9 Toggle Position 4.

XV10 Toggle Position 1.

XV10 Toggle Position 2.

XV10 Toggle Position 3.

XV10 Toggle Position 4.

XV11 Toggle Position 1.

XV11 Toggle Position 2.

XV11 Toggle Position 3.

XV11 Toggle Position 4.

XV12 Toggle Position 1.

XV12 Toggle Position 2.

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

Rev. 0 | Page 80 of 88

AD9923A

Address

(Hex)

Default

Value

Update

Type

Data Bits

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

Name

Description

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

Undefined

SCP

XV12TOG3

XV12TOG4

XV1TOG5

XV1TOG6

XV2TOG5

XV2TOG6

XV3TOG5

XV3TOG6

XV4TOG5

XV4TOG6

XV5TOG5

XV5TOG6

XV6TOG5

XV6TOG6

XV7TOG5

XV7TOG6

XV8TOG5

XV8TOG6

XV9TOG5

XV9TOG6

XV10TOG5

XV10TOG6

XV11TOG5

XV11TOG6

XV12TOG5

XV12TOG6

XV13TOG1

XV13TOG2

XV13TOG3

XV13TOG4

XV13TOG5

XV13TOG6

Unused

XV12 Toggle Position 3.

XV12 Toggle Position 4.

XV1 Toggle Position 5.

XV1 Toggle Position 6.

XV2 Toggle Position 5.

XV2 Toggle Position 6.

XV3 Toggle Position 5.

XV3 Toggle Position 6.

XV4 Toggle Position 5.

XV4 Toggle Position 6.

XV5 Toggle Position 5.

XV5 Toggle Position 6.

XV6 Toggle Position 5.

XV6 Toggle Position 6.

XV7 Toggle Position 5.

XV7 Toggle Position 6.

XV8 Toggle Position 5.

XV8 Toggle Position 6.

XV9 Toggle Position 5.

XV9 Toggle Position 6.

XV10 Toggle Position 5.

XV10 Toggle Position 6.

XV11 Toggle Position 5.

XV11 Toggle Position 6.

XV12 Toggle Position 5.

XV12 Toggle Position 6.

XV13 Toggle Position 1.

XV13 Toggle Position 2.

XV13 Toggle Position 3.

XV13 Toggle Position 4.

XV13 Toggle Position 5.

XV13 Toggle Position 6.

Must be set to 0.

SCP

[25:13]

[25:0]

Table 56. V-Sequence Registers

Address

(Hex)

Default

Value

Update

Type

Data Bits

[0]

[1]

[2]

[4:3]

Name

Description

00

Undefined

SCP

CLPOBPOL

PBLKPOL

HOLD

CLPOB start polarity.

PBLK start polarity.

HOLD function.

Enable masking of V-outputs.

0: no mask.

VMASK

1: enable Freeze1/Resume1.

2: enable Freeze2/Resume2.

3: enable both Freeze1/Resume1 and Freeze2/Resume2.

Enable HBLK alternation.

Must be set to 0.

[7:5]

[12:8]

[25:13]

Undefined

HBLKALT

Unused

HDLEN

HD line length (number of pixels in the line).

Rev. 0 | Page 81 of 88

AD9923A

Address

(Hex)

Default

Value

Update

Type

Data Bits

Name

Description

01

[0]

[1]

[2]

[3]

[4]

[5]

[6]

[7]

Undefined

SCP

XV1POL

XV2POL

XV3POL

XV4POL

XV5POL

XV6POL

XV7POL

XV8POL

XV1 start polarity.

XV2 start polarity.

XV3 start polarity.

XV4 start polarity.

XV5 start polarity.

XV6 start polarity.

XV7 start polarity.

XV8 start polarity.

[8]

[9]

XV9POL

XV9 start polarity.

XV10POL

XV11POL

XV12POL

XV13POL

XV1POL2

XV2POL2

XV3POL2

XV4POL2

XV5POL2

XV6POL2

XV7POL2

XV8POL2

XV9POL2

XV10POL2

XV11POL2

XV12POL2

XV13POL13

GROUPSEL

TWO_GROUP

XV10 start polarity.

XV11 start polarity.

XV12 start polarity.

XV13 start polarity.

XV1 second polarity.

XV2 second polarity.

XV3 second polarity.

XV4 second polarity.

XV5 second polarity.

XV6 second polarity.

XV7 second polarity.

XV8 second polarity.

XV9 second polarity.

XV10 second polarity.

XV11 second polarity.

XV12 second polarity.

XV13 second polarity.

Select between Group A and Group B. 0: Group A, 1: Group B.

[10]

[11]

[12]

[13]

[14]

[15]

[16]

[17]

[18]

[19]

[20]

[21]

[22]

[23]

[24]

[25]

[12:0]

[13]

02

SCP

1: use all Group A and Group B toggle positions for single V-

pattern.

[18:14]

Undefined

VPATSELB

Selected V-pattern Group B or Special V-pattern Second

position.

[23:19]

[25:24]

Undefined

VPATSELA

VPATA_MODE

Selected V-pattern Group A.

Number of alternation repeats.

0: disable alternation, use VREPA_1 for all lines.

1: 2-line alternation.

2: 3-line alternation.

3: 4-line alternation.

03

[12:0]

Undefined

SCP

VSTARTB

Start position of selected V-pattern Group B, or start

position of special V-pattern.

[25:13]

[12:0]

[25:13]

[11:0]

[12]

[24:13]

[11:0]

[12]

Undefined

VLENB

Length of selected V-pattern Group B.

Start position of selected V-pattern Group A.

Length of selected V-pattern Group A.

Number of repetitions for V-pattern Group B for odd lines.

Must be set to 0.

Number of repetitions for V-pattern Group B for even lines.

Number of repetitions for V-pattern Group A for first lines.

Must be set to 0.

04

05

SCP

VSTARTA

VLENA

VREPB_ODD

Unused

VREPB_EVEN

VREPA_1

Unused

06

SCP

[24:13]

VREPA_2

Number of repetitions for V-pattern Group A for second

lines.

Rev. 0 | Page 82 of 88

AD9923A

Address

(Hex)

Default

Value

Update

Type

Data Bits

Name

Description

07

08

09

[12:0]

Undefined

SCP

VREPA_3

Number of repetitions for V-pattern Group A for third lines,

or first HBLK toggle position for odd lines.

Number of repetitions for V-pattern Group A for fourth

lines, or second HBLK toggle position for odd lines.

[25:13]

[12:0]

VEPA_4

FREEZE1

RESUME1

FREEZE2

RESUME2

Holds the XV1 to XV13 outputs at their current levels, or

third HBLK toggle position for odd lines.

Resumes the operation of XV1 to XV13 outputs to finish the

pattern, or fourth HBLK toggle position for odd lines.

[25:13]

[12:0]

Holds the XV1 to XV13 outputs at their current levels, or

fifth HBLK toggle position for odd lines.

Resumes the operation of XV1 to XV13 outputs to finish the

pattern, or sixth HBLK toggle position for odd lines.

[25:13]

0A

0B

0C

[12:0]

[25:13]

[12:0]

[25:13]

[12:0]

Undefined

SCP

HBLKTOGE1

HBLKTOGE2

HBLKTOGE3

HBLKTOGE4

HBLKSTART

First HBLK toggle position for even lines.

Second HBLK toggle position for even lines.

Third HBLK toggle position for even lines.

Fourth HBLK toggle position for even lines.

Start location for HBLK in Alternation Mode 4 to Alternation

Mode 7, or fifth HBLK toggle position for even lines.

[25:13]

[12:0]

Undefined

HBLKEND

HBLKLEN

HBLKREP

End location for HBLK in Alternation Mode 4 to Alternation

Mode 7, or sixth HBLK toggle position for even lines.

0D

SCP

HBLK length in HBLK Alternation Mode 4 to Alternation

Mode 7.

Number of HBLK repetitions in HBLK Alternation Mode 4 to

Alternation Mode 7.

[20:13]

[21]

[22]

[23]

Undefined

HBLKMASK_H1

HBLKMASK_H3

HBLKMASK_HL

CLPOBTOG1

CLPOBTOG2

PBLKTOG1

PBLKTOG2

UNUSED

Masking polarity for H1 during HBLK.

Masking polarity for H3 during HBLK.

Masking polarity for HL during HBLK.

CLPOB Toggle Position 1.

CLPOB Toggle Position 2.

PBLK Toggle Position 1.

0E

0F

[12:0]

[25:13]

[12:0]

[25:13]

[25:0]

[11:0]

[12]

SCP

PBLK Toggle Position 2.

10

11

SCP

Must be set to 0.

SPXV_ACT

UNUSED

SPXV_EN

Special XV-pattern active line.

Must be set to 0.

Special XV-pattern enable (active high).

Must be set to 0.

[13]

12

13

[25:0]

SCP

UNUSED

Must be set to 0.

Rev. 0 | Page 83 of 88

AD9923A

Table 57. Field Registers

Address

(Hex)

Default

Value

Update

Type

Data Bits

[4:0]

[9:5]

[14:10]

[19:15]

[24:20]

[4:0]

Name

SEQ0

SEQ1

SEQ2

SEQ3

Description

00

Undefined

VD

Selected V-sequence for first region in the field.

Selected V-sequence for second region in the field.

Selected V-sequence for third region in the field .

Selected V-sequence for fourth region in the field.

Selected V-sequence for fifth region in the field.

Selected V-sequence for sixth region in the field.

Selected V-sequence for seventh region in the field.

Selected V-sequence for eighth region in the field.

Selected V-sequence for ninth region in the field.

Enables multiplier mode and/or sweep mode for Region 0.

0: multiplier off/sweep off.

SEQ4

01

02

VD

SEQ5

SEQ6

SEQ7

SEQ8

[9:5]

[14:10]

[19:15]

[1:0]

MULT_SWEEP0

1: multiplier off/sweep on.

2: multiplier on/sweep off.

3: multiplier on/sweep on.

[3:2]

[5:4]

[7:6]

[9:8]

Undefined

MULT_SWEEP1

MULT_SWEEP2

MULT_SWEEP3

MULT_SWEEP4

MULT_SWEEP5

MULT_SWEEP6

MULT_SWEEP7

MULT_SWEEP8

SCP0

Enables multiplier mode and/or sweep mode for Region 1.

Enables multiplier mode and/or sweep mode for Region 2.

Enables multiplier mode and/or sweep mode for Region 3.

Enables multiplier mode and/or sweep mode for Region 4.

Enables multiplier mode and/or sweep mode for Region 5.

Enables multiplier mode and/or sweep mode for Region 6.

Enables multiplier mode and/or sweep mode for Region 7.

Enables multiplier mode and/or sweep mode for Region 8.

V-Sequence Change Position 0.

[11:10]

[13:12]

[15:14]

[17:16]

[11:0]

[12]

[24:13]

[11:0]

[12]

[24:13]

[11:0]

[12]

[24:13]

[11:0]

[12]

[24:13]

[11:0]

[12]

[24:13]

[12:0]

[25:13]

[4:0]

[20:5]

[23:0]

[11:0]

[12]

03

04

05

06

07

VD

Unused

SCP1

Must be set to 0.

V-Sequence Change Position 1.

SCP2

Unused

SCP3

V-Sequence Change Position 2.

Must be set to 0.

V-Sequence Change Position 3.

SCP4

Unused

SCP5

V-Sequence Change Position 4.

Must be set to 0.

V-Sequence Change Position 5.

SCP6

Unused

SCP7

V-Sequence Change Position 6.

Must be set to 0.

V-Sequence Change Position 7.

SCP8

Unused

VDLEN

V-Sequence Change Position 8.

Must be set to 0.

VD field length (number of lines in the field).

HD last line length. Line length of last line in the field.

Start position for second V-pattern on SG active line.

Selected second V-pattern group for SG active line.

Masking of VSG outputs during SG active line.

Selection of VSG patterns for each VSG output.

SG Active Line 1.

08

09

VD

HDLAST

VSTARTSECOND

VPATSECOND

SGMASK

0A

0B

VD

SGPATSEL

SGACTLINE1

Unused

Must be set to 0.

SG Active Line 2.

[24:13]

SGACTLINE2

Rev. 0 | Page 84 of 88

AD9923A

OUTLINE DIMENSIONS

A1 CORNER

INDEX AREA

8.00

BSC SQ

11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

A1 BALL

CORNER

6.50

BSC SQ

TOP VIEW

G

H

J

K

L

BOTTOM

VIEW

0.65 BSC

DETAIL A

*1.40

1.31

1.16

DETAIL A

0.91 MIN

0.25 MIN

0.10 MAX

COPLANARITY

0.45

0.40

0.35

SEATING

PLANE

BALL DIAMETER

*

COMPLIANT TO JEDEC STANDARDS MO-225

WITH THE EXCEPTION TO PACKAGE HEIGHT.

Figure 89. 105-Lead Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-105)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD9923ABBCZ¹

AD9923ABBCZRL¹

−25°C to +85°C

105-Lead Chip Scale Package Ball Grid Array [CSP_BGA]

BC-105

¹Z = Pb-free part.

Rev. 0 | Page 85 of 88

AD9923A

NOTES

Rev. 0 | Page 86 of 88

AD9923A

NOTES

Rev. 0 | Page 87 of 88

AD9923A

NOTES

registered trademarks are the property of their respective owners.

D06415-0-10/06(0)

Rev. 0 | Page 88 of 88


型号：	AD9923ABBCZRL
厂家：	ADI
描述：	CCD Signal Processor with V-Driver and Precision Timing⑩ Generator CCD信号处理器， V型驱动器和Precision Timing⑩发生器驱动器 CD
文件：	总88页 (文件大小：1531K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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