ADA4410-6ACPZ-RL_技术文档

Integrated Video Filter with Selectable Cutoff

Frequencies for RGB, HD/SD Y, C, and CV

ADA4410-6

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Sixth-order filters with selectable cutoff frequencies

36 MHz, 18 MHz, 9 MHz

Many video standards supported

RGB/YPbPr/YUV/SD/YC/CV

Y1/G1 IN

Y2/G2 IN

×2

×4

36MHz,

18MHz,

9MHz

Y/G OUT

Pb/B OUT

Pr/R OUT

Ideal for resolutions up to 1080i

−1 dB bandwidth of 30 MHz for HD

2:1 multiplexers on all inputs

Selectable gain: ×2 or ×4

DC output offset adjust: 0.5 V, input referred

Excellent video specifications

NTSC differential gain: 0.11%

NTSC differential phase: 0.25°

Low input bias current: 6.6 μA

Wide supply range: +4.5 V to 5 V

Rail-to-rail output

Pb1/B1 IN

Pb2/B2 IN

×2

×4

36MHz,

18MHz,

9MHz

Pr1/R1 IN

Pr2/R2 IN

×2

×4

36MHz,

18MHz,

9MHz

HD INPUT SELECT

LEVEL1

DC

OFFSET

ADA4410-6

LEVEL2

2

CUTOFF SELECT

GAIN SELECT

Typical output swing of 4.5 V p-p on single 5 V supply

Disable feature

Y1 IN

Y2 IN

×2

×4

Y OUT

9MHz

APPLICATIONS

Set-top boxes

DVD players and recorders

HDTVs

×2

CV OUT

C OUT

C1 IN

C2 IN

×2

×4

9MHz

GENERAL DESCRIPTION

SD INPUT SELECT

DISABLE

The ADA4410-6 is a comprehensive integrated filtering solution

that is carefully designed to give designers the flexibility to

easily filter and drive many types of video signals, including

high definition video. In the RGB/component channels, the

cutoff frequencies of the sixth-order filters can be selected by

two logic pins to obtain four filter combinations that are tuned

for RGB, high definition, and standard definition video. Cutoff

frequencies range from 9 MHz to 36 MHz.

Figure 1.

The ADA4410-6 offers 2:1 multiplexers on its inputs that can be

used in applications where multiple sources of video exist.

The ADA4410-6 can operate on a single +5 V supply as well as

5 V supplies. Single-supply operation is ideal for applications

where power consumption is critical. The disable feature allows

for further power conservation by reducing the supply current

to typically 15 μA when a particular device is not in use.

The ADA4410-6 also provides filtering for the legacy standard

S-video and composite video signals. With a differential gain of

0.11% and a differential phase of 0.25°, the ADA4410-6 is an

excellent choice for any composite video (CV) application.

Dual-supply operation is best for applications where the

negative-going excursions of the signal must swing at or below

ground while maintaining excellent video performance. The

output buffers have the ability to drive two 75 Ω doubly

terminated cables that are either dc- or ac-coupled.

The ADA4410-6 offers gain and output offset voltage

adjustments. With a single logic pin, the gain of the part can be

selected to be ×2 or ×4. Output offset voltage is continuously

adjustable over an input-referred range of 500 mV by applying

a differential voltage to an independent offset control input.

The ADA4410-6 is available in a 32-lead LFCSP and operates in

the extended industrial temperature range of −40°C to +85°C.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

ADA4410-6

TABLE OF CONTENTS

Features .............................................................................................. 1

Overview ..................................................................................... 13

Multiplexer Select Inputs........................................................... 13

Throughput Gain........................................................................ 13

Disable ......................................................................................... 13

Cutoff Frequency Selection....................................................... 13

Output DC Offset Control........................................................ 13

Input and Output Coupling ...................................................... 14

Printed Circuit Board Layout ................................................... 15

Video Encoder Reconstruction Filter...................................... 15

Outline Dimensions....................................................................... 16

Ordering Guide .......................................................................... 16

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

Applications..................................................................................... 13

REVISION HISTORY

3/06—Rev. A to Rev. B

8/05—Rev. 0 to Rev. A

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 5

Changes to Figure 4 through Figure 9 ........................................... 9

Changes to Figure 10...................................................................... 10

Changes to Ordering Guide .......................................................... 16

Updated Outline Dimensions....................................................... 16

Changes to Features, General Description, and Figure 1.............1

Changes to Table 1.............................................................................3

Changes to Table 2.............................................................................5

Changes to Figure 4...........................................................................9

Changes to Theory of Operation Section.................................... 12

Changes to Overview, Throughput Gain, and Output DC

Offset Control Sections.................................................................. 13

Renamed Gain Select Section Throughput Gain Section ........ 13

Added Composite Video Path Gain Section............................... 13

Changes to Table 6 and Table 7 .................................................... 13

Changes to Figure 24 Caption ...................................................... 14

Changes to Input and Output Coupling Section........................ 14

Added Figure 25 and Figure 26; Renumbered Sequentially ..... 14

Changes to Figure 27...................................................................... 15

1/05—Revision 0: Initial Version

Rev. B | Page 2 of 16

ADA4410-6

SPECIFICATIONS

V_S= 5 V, @ T_A= 25°C, V_O= 1.4 V p-p, G = ×2, R_L= 150 Ω, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

OVERALL PERFORMANCE

Offset Error

Input referred, all channels except CV

Input referred, CV

10

12

±±00

32

40

mV

V

Max Voltage Across LEVEL1 and LEVEL2 Inputs

Input Voltage Range, All Inputs

V_S−− 0.1

V_S+− 2.0

Output Voltage Swing, All Outputs

Positive swing

Negative swing

V_S+− 0.3± V_S+− 0.2±

V

V_S−+ 0.10 V_S−+ 0.3

Linear Output Current per Channel

Integrated Voltage Noise, Referred to Input

Filter Input Bias Current

Total Harmonic Distortion at 1 MHz

RGB/YPbPr CHANNEL DYNAMIC PERFORMANCE

−1 dB Bandwidth

30

±00

6.6

0.01/0.07

mA

μV_rms

μA

%

All channels except CV

All channels

F_C= 36 MHz, F_C= 18 MHz/F_C= 9 MHz

1±

Cutoff frequency select = 36 MHz

Cutoff frequency select = 18 MHz

Cutoff frequency select = 9 MHz

Cutoff frequency select = 36 MHz

Cutoff frequency select = 18 MHz

Cutoff frequency select = 9 MHz

f = 7± MHz

f = ± MHz, F_C= 36 MHz

f = 1 MHz, R_SOURCE= 300 Ω

f = 16 MHz, F_C= 36 MHz

31

1±

8

36

18

9

−42

−68

86

20.±

9.±

16.±

29.±

MHz

dB

ns

−3 dB Bandwidth

34

16

8

Out-of-Band Rejection

Crosstalk

Input Mux Isolation

Propagation Delay

Group Delay Variation

−33

Cutoff frequency select = 36 MHz

Cutoff frequency select = 18 MHz

Cutoff frequency select = 9 MHz

ns

Y/C SD CHANNEL DYNAMIC PERFORMANCE

−1 dB Bandwidth

−3 dB Bandwidth

Out-of-Band Rejection

Propagation Delay

7.±

9

−±6

72

MHz

dB

8

f = 27 MHz

f = 1 MHz

ns

Group Delay Variation

Crosstalk

Input Mux Isolation

30

−72

77

ns

dB

f = 1 MHz

f = 1 MHz, R_SOURCE= 7± Ω

Y/C, CV OUTPUT VIDEO PERFORMANCE

Differential Gain

Differential Phase

NTSC

0.09

0.37

%

Degrees

CONTROL INPUT PERFORMANCE

Input Logic 0 Voltage

Input Logic 1 Voltage

All inputs except DISABLE

0.8

1±

V

μA

2.0

Input Bias Current

7

DISABLE PERFORMANCE

DISABLE Assert Voltage

DISABLE Assert Time

DISABLE Deassert Time

DISABLE Input Bias Current

Input-to-Output Isolation—Disabled

V_S+− 0.±

100

130

12

100

V

ns

μA

dB

20

Rev. B | Page 3 of 16

ADA4410-6

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

POWER SUPPLY

Operating Range

Quiescent Current

Quiescent Current—Disabled

PSRR, Positive Supply

4.±

12

88

1±0

V

82

1±

72

66

62

±6

mA

μA

dB

All channels except CV

CV channel

All channels except CV

CV channel

62

±9

±±

±2

PSRR, Negative Supply

Rev. B | Page 4 of 16

ADA4410-6

V_S= 5 V, @ T_A= 25°C, V_O= 1.4 V p-p, G = ×2, R_L= 150 Ω, unless otherwise noted.

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

OVERALL PERFORMANCE

Offset Error

Input referred, all channels except CV

Input referred, CV

14

1±

±±00

33.±

42.±

mV

V

mA

μV_rms

μA

%

Max Voltage Across LEVEL1 and LEVEL2 Inputs

Input Voltage Range, All Inputs

Output Voltage Swing, All Outputs

V_S−− 0.1

V_S+− 2.0

V_S−+ 0.±

Positive swing

Negative swing

V_S+− 0.3± V_S+− 0.2±

V_S−+ 0.3

30

±00

6.3

0.01/0.07

Linear Output Current per Channel

Integrated Voltage Noise, Referred to Input

Filter Input Bias Current

Total Harmonic Distortion at 1 MHz

RGB/YPbPr CHANNEL DYNAMIC PERFORMANCE

−1 dB Bandwidth

All channels except CV

All channels

F_C= 36 MHz, F_C= 18 MHz/F_C= 9 MHz

1±

Cutoff frequency select = 36 MHz

Cutoff frequency select = 18 MHz

Cutoff frequency select = 9 MHz

Cutoff frequency select = 36 MHz

Cutoff frequency select = 18 MHz

Cutoff frequency select = 9 MHz

f = 7± MHz

f = ± MHz, F_C= 36 MHz

f = 1 MHz, R_SOURCE= 300 Ω

f = ± MHz, F_C= 36 MHz

29

1±

8

3±.±

18

9.±

−41.±

−68

86

MHz

dB

ns

−3 dB Bandwidth

33.0

16.±

8

Out-of-Band Rejection

Crosstalk

Input Mux Isolation

Propagation Delay

Group Delay Variation

−33

21

7.±

14

Cutoff frequency select = 36 MHz

Cutoff frequency select = 18 MHz

Cutoff frequency select = 9 MHz

ns

26

Y/C SD CHANNEL DYNAMIC PERFORMANCE

−1 dB Bandwidth

−3 dB Bandwidth

Out-of-Band Rejection

Propagation Delay

7.±

9

−±7

64

MHz

dB

8

f = 27 MHz

f = 1 MHz

ns

Group Delay Variation

Crosstalk

Input Mux Isolation

26

−72

77

ns

dB

f = 1 MHz

f = 1 MHz, R_SOURCE= 7± Ω

Y/C, CV OUTPUT VIDEO PERFORMANCE

Differential Gain

Differential Phase

NTSC

0.11

0.2±

%

Degrees

CONTROL INPUT PERFORMANCE

Input Logic 0 Voltage

Input Logic 1 Voltage

All inputs except DISABLE

0.8

1±

V

μA

2.0

Input Bias Current

7

DISABLE PERFORMANCE

DISABLE Assert Voltage

DISABLE Assert Time

DISABLE Deassert Time

DISABLE Input Bias Current

Input-to-Output Isolation—Disabled

V_S+− 0.±

7±

12±

3±

100

V

ns

μA

dB

4±

Rev. B | Page ± of 16

ADA4410-6

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

POWER SUPPLY

Operating Range

Quiescent Current

Quiescent Current—Disabled

PSRR, Positive Supply

4.±

12

93

1±0

V

86

1±

72

66

62

±6

mA

μA

dB

All channels except CV

CV channel

All channels except CV

CV channel

62

±9

±±

±2

PSRR, Negative Supply

Rev. B | Page 6 of 16

ADA4410-6

ABSOLUTE MAXIMUM RATINGS

Table 3.

The power dissipated in the package (P_D) is the sum of the

quiescent power dissipation and the power dissipated in the

package due to the load drive for all outputs. The quiescent

power is the voltage between the supply pins (V_S) times the

quiescent current (I_S). The power dissipated due to load drive

depends upon the particular application. For each output, the

power due to load drive is calculated by multiplying the load

current by the associated voltage drop across the device. The

power dissipated due to all of the loads is equal to the sum of

the power dissipations due to each individual load. RMS

voltages and currents must be used in these calculations.

Parameter

Rating

Supply Voltage

Power Dissipation

Storage Temperature Range

Operating Temperature Range

Lead Temperature (Soldering 10 sec)

Junction Temperature

12 V

See Figure 2

–6±°C to +12±°C

–40°C to +8±°C

300°C

1±0°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Airflow increases heat dissipation, effectively reducing θ_JA. In

addition, more metal directly in contact with the package leads

from metal traces, through-holes, ground, and power planes,

reduces the θ_JA. The exposed paddle on the underside of the

package must be soldered to a pad on the PCB surface that is

thermally connected to a copper plane to achieve the specified θ_JA.

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, θ_JAis

specified for a device soldered in the circuit board with its

exposed paddle soldered to a pad on the PCB surface that is

thermally connected to a copper plane.

Figure 2 shows the maximum safe power dissipation in the

package vs. the ambient temperature for the 32-lead LFCSP

(43°C/W) on a JEDEC standard 4-layer board with the underside

paddle soldered to a pad that is thermally connected to a PCB

plane. θ_JAvalues are approximations.

Table 4. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

4.5

4.0

3.5

± mm × ± mm, 32-Lead LFCSP

43

±.1

°C/W

Maximum Power Dissipation

The maximum safe power dissipation in the ADA4410-6

package is limited by the associated rise in junction temperature

(T_J) on the die. At approximately 150°C, which is the glass

transition temperature, the plastic changes its properties. Even

temporarily exceeding this temperature limit can change the

stresses that the package exerts on the die, permanently shifting

the parametric performance of the ADA4410-6. Exceeding a

junction temperature of 150°C for an extended time can result

in changes in the silicon devices, potentially causing failure.

LFCSP

3.0

2.5

2.0

1.5

1.0

–40

–20

0

20

40

60

80

AMBIENT TEMPERATURE (°C)

Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate

on the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. B | Page 7 of 16

ADA4410-6

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

32

1

25

24

PIN 1

INDICATOR

ADA4410-6

(Not to Scale)

8

17

16

9

Figure 3. 32-Lead LFCSP Pin Configuration, Top View

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Pb1/B1_HD

GND

Description

1

2

Channel 1 Pb/B High Definition Input

Signal Ground Reference

3

4

±

6

Pr1/R1_HD

F_SEL_A

F_SEL_B

Y2/G2_HD

GND

Channel 1 Pr/R High Definition Input

Filter Cutoff Select Input A

Filter Cutoff Select Input B

Channel 2 Y/G High Definition Input

Signal Ground Reference

7

8

9

Pb2/B2_HD

GND

Channel 2 Pb/B High Definition Input

Signal Ground Reference

10

11

12

13

14

1±

16

17

18

19

20

21

22

23

24

2±

26

27

28

29

30

31

32

Pr2/R2_HD

MUX_SD

Y1_SD

Y2_SD

C1_SD

C2_SD

VCC

VEE

CV_OUT

C_SD_OUT

Y_SD_OUT

G_SEL

Pr/R_HD_OUT

Pb/B_HD_OUT

Y/G_HD_OUT

VEE

Channel 2 Pr/R High Definition Input

Standard Definition Input Mux Select Line

Channel 1 Y Standard Definition Input

Channel 2 Y Standard Definition Input

Channel 1 C Standard Definition Input

Channel 2 C Standard Definition Input

Positive Power Supply

Negative Power Supply

Composite Video Output

C Standard Definition Output

Y Standard Definition Output

Gain Select

Pr/R High Definition Output

Pb/B High Definition Output

Y/G High Definition Output

Negative Power Supply

Positive Power Supply

Disable/Power Down/Logic Reference

DC Level Adjust Pin 2

VCC

DISABLE

LEVEL2

LEVEL1

DC Level Adjust Pin 1

MUX_HD

Y1/G1_HD

GND

High Definition Input Mux Select Line

Channel 1 Y/G High Definition Input

Signal Ground Reference

Rev. B | Page 8 of 16

ADA4410-6

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise noted, G = ×2, R_L= 150 ꢀ, V_O= 1.4 V p-p, V_S= 5 V, T_A= 25°C.

9

6

3

0

–3

–6

15

12

9

6

3

0

–3

–6

–9

–12

–15

–18

–21

–24

–27

–30

–33

–36

–39

–42

–45

F

= 18MHz

F

= 18MHz

C

F

= 9MHz

–9

C

F

= 36MHz

–12

–15

–18

–21

–24

–27

–30

–33

–36

–39

–42

–45

–48

F = 9MHz

C

F

= 36MHz

C

BLACK LINES: V = +5V

S

GRAY LINES: V = ±5V

S

BLACK LINES: V = +5V

S

GRAY LINES: V = ±5V

S

1

10

100

1

10

FREQUENCY (MHz)

100

FREQUENCY (MHz)

Figure 4. Frequency Response vs. Power Supply and Cutoff Frequency (G = ×2)

Figure 7. Frequency Response vs. Power Supply and Cutoff Frequency (G = ×4)

6.5

6.0

5.5

12.5

12.0

F

= 36MHz

11.5

11.0

10.5

10.0

9.5

C

F

C

= 9MHz

F

= 9MHz

C

5.0

4.5

4.0

3.5

3.0

F

= 36MHz

C

F

= 18MHz

C

F

= 18MHz

BLACK LINES: V = +5V

S

GRAY LINES: V = ±5V

BLACK LINES: V = +5V

S

GRAY LINES: V = ±5V

S

9.0

1

10

FREQUENCY (MHz)

100

1

10

FREQUENCY (MHz)

100

Figure 5. Frequency Response Flatness vs. Cutoff Frequency (G = ×2)

Figure 8. Frequency Response Flatness vs. Cutoff Frequency (G = ×4)

9

6

3

0

9

6

3

0

–3

–6

–9

F

= 18MHz

–3

–6

–9

–12

C

–12

–15

–18

–21

–24

–27

–30

–33

–36

–39

–42

–45

–48

F

= 9MHz

F

= 36MHz

–15

–18

–21

–24

–27

–30

–33

–36

–39

–42

–45

–48

F

= 9MHz

F

= 36MHz

C

F

= 18MHz

C

RED LINES: +85°C

GREEN LINES: +25°C

BLUE LINES: –40°C

BLACK LINES: V = 2V p-p

GRAY LINES: V = 0.1V p-p

O

1

10

100

1

10

FREQUENCY (MHz)

100

FREQUENCY (MHz)

Figure 6. Frequency Response vs. Cutoff Frequency and Output Amplitude

Figure 9. Frequency Response vs. Temperature and Cutoff Frequency

Rev. B | Page 9 of 16

ADA4410-6

100

–60

–65

BLACK LINES: V = +5V

BANDWIDTH 100kHz TO 4.2MHz

NTC-7 WEIGHT

S

GRAY LINES: V = ±5V

S

90

–70

80

F

= 9MHz

C

–75

70

60

50

40

30

20

10

–80

–85

–90

F

= 18MHz

C

–95

–100

–105

–110

F

= 36MHz

C

1

10

FREQUENCY (MHz)

100

0

1

2

3

4

5

FREQUENCY (MHz)

Figure 10. Group Delay vs. Frequency, Power Supply, and Cutoff Frequency

Figure 13. CV Noise Spectrum

–40

–50

R

= 300Ω

Y1, C1 SOURCE CHANNELS

F

= 36MHz

SOURCE

C

MUX INPUT 2 SELECTED Y2 RECEPTOR CHANNEL

F

= 18MHz

C

–50

–60

F

= 9MHz

C

–60

–70

–80

–90

C2 SOURCE CHANNEL

Y2 RECEPTOR CHANNEL

R

= 300Ω

–100

–110

–100

–110

SOURCE

Y1, Pb1 SOURCE CHANNELS

Pr1 RECEPTOR CHANNEL

0.1

1

10

FREQUENCY (MHz)

100

0.1

1

10

100

FREQUENCY (MHz)

Figure 11. HD Channel Crosstalk vs. Frequency and Cutoff Frequency

Figure 14. SD Channel Crosstalk vs. Frequency

–40

R

= 300Ω

UNSELECTED MUX IS DRIVEN

SOURCE

UNSELECTED MUX IS DRIVEN

–50

–60

–50

–60

F

= 36MHz

C

R

= 300Ω

SOURCE

–70

–80

F

= 18MHz

= 9MHz

C

R

= 75Ω

SOURCE

–90

F

C

–100

–110

–100

–110

0.1

1

10

100

0.1

1

10

FREQUENCY (MHz)

100

FREQUENCY (MHz)

Figure 12. HD Mux Isolation vs. Frequency and Cutoff Frequency

Figure 15. SD Mux Isolation vs. Frequency and Source Resistance

Rev. B | Page 10 of 16

ADA4410-6

–5

–15

–25

–35

–45

–55

–65

–75

–5

–15

–25

–35

–45

–55

–65

–75

F

= 9MHz

C

F

= 9MHz

C

F

= 18MHz

C

F

= 18MHz

C

F

= 36MHz

C

F

= 36MHz

C

0.1

1

10

FREQUENCY (MHz)

100

0.1

1

10

FREQUENCY (MHz)

100

Figure 16. Positive Supply PSRR vs. Frequency and Cutoff Frequency

Figure 19. Negative Supply PSRR vs. Frequency and Cutoff Frequency

3.5

3.3

3.1

3.5

G = 4

3.3

3.1

2.9

2.7

2.5

2.3

2.1

1.9

1.7

1.5

V

= 1.4V p-p

O

F

= 18MHz

= 9MHz

F

= 18MHz

= 9MHz

F

= 36MHz

F = 36MHz

C

2.9

2.7

2.5

2.3

2.1

1.9

1.7

1.5

F

C

200ns/DIV

Figure 17. Transient Response vs. Cutoff Frequency (G = ×2)

Figure 20. Transient Response vs. Cutoff Frequency (G = ×4)

3.5

3.3

6

2 × INPUT VOLTAGE

5

3.1

F

= 18MHz

C

1% (57ns)

4

3

2.9

2 × INPUT

F

= 36MHz

C

2.7

ERROR = 2 × INPUT – OUTPUT (0.5%/DIV)

2.5

F

= 9MHz

C

2

2.3

2.1

1

0.5% (65ns)

1.9

1.7

0

OUTPUT

50ns/DIV

200ns/DIV

–1

1.5

t = 0

Figure 21. Overdrive Recovery vs. Cutoff Frequency

Figure 18. Settling Time

NETWORK

ANALYZER Tx

NETWORK

ANALYZER Rx

R

= 150Ω

L

50Ω

118Ω

DUT

50Ω

86.6Ω

MINIMUM-LOSS MATCHING NETWORK LOSS CALIBRATED OUT

Figure 22. Basic Test Circuit for Swept Frequency Measurements

Rev. B | Page 11 of 16

ADA4410-6

THEORY OF OPERATION

The ADA4410-6 is an integrated video filtering and driving

solution that offers variable bandwidth to meet the needs of

several different video formats. There are a total of five filter

sections, three for component video and two for Y/C and

composite video. The component video filters have switchable

bandwidths for standard definition interlaced, progressive, and

high definition systems. The Y/C channels have fixed 9 MHz,

3 dB cutoff frequencies and include a summing circuit that

feeds an additional buffer for a composite video output. Each

filter section has a sixth-order Butterworth response that

includes group delay optimization. The group delay variation

from 100 kHz to 36 MHz in the 36 MHz section is 8 ns, which

produces a fast settling pulse response.

For single-supply applications (V_S−= GND), the input voltage

range extends from 100 mV below ground to within 2.0 V of

the most positive supply. Each filter section has a 2:1 input

multiplexer that includes level-shifting circuitry. The level-

shifting circuitry adds a dc component to ground-referenced

input signals so that they can be reproduced accurately without

the output buffers hitting the negative rail. Because the filters

have negative rail input and rail-to-rail output, dc level shifting

is generally not necessary, unless accuracy greater than that of

the saturated output of the driver is required at the most negative

edge. This varies with load but is typically 100 mV in a dc-

coupled, single-supply application. If ac coupling is used, the

saturated output level is higher because the drivers have to

sink more current on the low side. If dual supplies are used

(V_S−< GND), no level shifting is required. In dual-supply

applications, the level shifting circuitry can be used to take a

ground-referenced signal and put the blanking level at ground

while the sync level is below ground.

The ADA4410-6 is designed to operate in many different video

environments. The supply range is 5 V to 12 V, single supply or

dual supply, and requires a relatively low quiescent current of

15 mA per channel. In single-supply applications, the PSRR is

greater than 70 dB, providing excellent rejection in systems with

supplies that are noisy or under-regulated. In applications

where power consumption is critical, the part can be powered

down to draw 15 μA by pulling the DISABLE pin to the most

positive rail. The ADA4410-6 is also well suited for high

encoding frequency applications because it maintains a stop-

band attenuation of 50 dB beyond 200 MHz.

The output drivers on the ADA4410-6 have rail-to-rail output

capabilities. They provide either 6 dB or 12 dB of gain with

respect to the ground pins. Gain is controlled by the external

gain select pin. Each output is capable of driving two ac- or dc-

coupled 75 Ω source-terminated loads. If a large dc output level

is required while driving two loads, ac coupling should be used

to limit the power dissipation.

The ADA4410-6 is intended to take dc-coupled inputs from an

encoder or other ground-referenced video signals. The ADA4410-6

input is high impedance. No minimum or maximum input

termination is required, though input terminations above 1 kΩ

can degrade crosstalk performance at high frequencies. No

clamping is provided internally. For applications where dc

restoration is required, dual supplies work best. Using a

termination resistance of less than a few hundred ohms to

ground on the inputs and suitably adjusting the level shift

circuitry provides precise placement of the output voltage.

Input mux isolation is primarily a function of the source

resistance driving into the ADA4410-6. Higher resistances

result in lower isolation over frequency, while a low source

resistance, such as 75 Ω, has the best isolation performance. In

the SD channels, the isolation variation is most pronounced due

to the stray capacitance that exists between the adjacent input

pins. The HD input pins are not adjacent; therefore, this effect is

less pronounced on the HD channels. See Figure 15 for a

performance comparison of the different source resistances

feeding the SD inputs.

Rev. B | Page 12 of 16

ADA4410-6

APPLICATIONS

OVERVIEW

DISABLE

With its high impedance multiplexed inputs and high output

drive, the ADA4410-6 is ideally suited to video reconstruction

and antialias filtering applications. The high impedance inputs

give designers flexibility with regard to how the input signals

are terminated. Devices with DAC current source outputs that

feed the ADA4410-6 can be loaded in whatever resistance

provides the best performance, and devices with voltage outputs

can be optimally terminated as well. The ADA4410-6 outputs

can each drive up to two source-terminated 75 Ω loads and can

therefore directly drive the outputs from set-top boxes, DVD

players, and the like without the need for a separate output buffer.

The ADA4410-6 includes a disable feature that can be used to

save power when a particular device is not in use. As indicated

in the Overview section, the disable feature is asserted by pulling

the DISABLE pin to the positive supply. Table 6 summarizes the

disable feature operation. The DISABLE pin also functions as a

reference level for the logic inputs and, therefore, must be

connected to ground when the device is not disabled.

Table 6. Logic Pin Function Description

DISABLE

MUX_HD

1 = HD Channel 1 1 = SD Channel 1 1 = ×4

Selected Selected Gain

0 = HD Channel 2 0 = SD Channel 2 0 = ×2

Selected Selected Gain

MUX_SD

G_SEL

V_S+

=

Disabled

GND =

Enabled

Binary control inputs are provided to select cutoff frequency,

throughput gain, and input signal. These inputs are compatible

with 3 V and 5 V TTL and CMOS logic levels, referenced to

GND. The disable feature is asserted by pulling the DISABLE

pin to the positive supply.

CUTOFF FREQUENCY SELECTION

Four combinations of cutoff frequencies are provided for the

HD video signals. The cutoff frequencies were selected to

correspond with the most commonly deployed HD scanning

systems. Selection between the cutoff frequency combinations is

controlled by the logic signals applied to the F_SEL_A and

F_SEL_B inputs. Table 7 summarizes cutoff frequency selection.

The LEVEL1 and LEVEL2 inputs comprise a differential input

that controls the dc level at the output pins.

MULTIPLEXER SELECT INPUTS

Selection between the two multiplexer inputs is controlled by

the logic signals applied to the MUX_SD and MUX_HD inputs.

The MUX_SD input controls the standard definition (SD)

inputs, and the MUX_HD input controls the high definition

(HD) inputs. Table 6 summarizes the multiplexer operation.

Table 7. Filter Cutoff Frequency Selection

F_SEL_A F_SEL_B Y/G Cutoff Pb/B Cutoff Pr/R Cutoff

0

1

0

1

0

1

36 MHz

18 MHz

9 MHz

36 MHz

18 MHz

9 MHz

36 MHz

18 MHz

9 MHz

THROUGHPUT GAIN

The throughput gain of the ADA4410-6 signal paths can be ×2

or ×4. Gain selection is controlled by the logic signal applied to

the G_SEL pin. Table 6 summarizes how the gain is selected.

OUTPUT DC OFFSET CONTROL

The LEVEL1 and LEVEL2 inputs work as a differential input-

referred output offset control. In other words, the output offset

voltage of a given channel (with the exception of the CV

channel) is equal to the difference in voltage between the

LEVEL1 and LEVEL2 inputs multiplied by the overall filter

gain. This relationship is expressed in Equation 1.

Composite Video Path Gain

The composite video signal is produced by passively summing

the C and V outputs (see Figure 1), which have been amplified

by their respective gain stages. Each signal experiences a 6 dB

loss as it passes through the passive summer and is subsequently

amplified by 6 dB in the fixed ×2 stage following the summer.

The net signal gain through the composite video path is therefore

0 dB, and the resulting composite signal present at the ADA4410-6

output is the sum of Y and C with unity gain. The offset voltage

at the composite video output is twice that of the offset on the Y

or C outputs because the offsets on the Y and C outputs are the

same and appear as a common-mode input to the summer. The

voltage between the summing resistors due to the offset voltages

is therefore equal to the output offset voltage on the Y and C

outputs and appears at the composite video output with a gain

of 2 after passing through the fixed ×2 gain stage.

V

_OS(OUT) = (LEVEL1 − LEVEL2)(G)

(1)

where:

LEVEL1 and LEVEL2 are the voltages applied to the respective

inputs.

G is throughput gain.

For example, with the G_SEL input set for ×2 gain, setting

LEVEL1 to 300 mV and LEVEL2 to 0 V shifts the offset voltages

at the ADA4410-6 outputs to 600 mV. This particular setting

can be used in most single-supply applications to keep the

output swings safely above the negative supply rail.

Rev. B | Page 13 of 16

ADA4410-6

+5V

10kΩ

+5V

DNP

As previously discussed, the composite video output is

developed by passively summing the Y and C outputs that have

passed through their respective output gain stages, then multiplying

this sum by a factor of two to obtain the output (see Figure 1).

The offset of this output is equal to 2× that of the other outputs.

Because of this, in many cases, it is necessary to ac-couple the

CV output or ensure that it is connected to an input that is ac-

coupled. This is generally not an issue because it is common

practice to employ ac coupling on composite video inputs.

LEVEL1

0.1μF

LEVEL2

DNP

634Ω

0Ω

Figure 24. Flexible Circuits to Set the LEVEL1 and LEVEL2 Inputs to Obtain

a 600 mV Output Offset on a Single Supply (G = ×2)

INPUT AND OUTPUT COUPLING

The maximum differential voltage that can be applied across the

LEVEL1 and LEVEL2 inputs is 500 mV. From a single-ended

standpoint, the LEVEL1 and LEVEL2 inputs have the same

range as the filter inputs. See the Specifications tables for the

limits. The LEVEL1 and LEVEL2 inputs must each be bypassed

to GND with a 0.1 μF ceramic capacitor.

Inputs to the ADA4410-6 are normally dc-coupled. Ac coupling

the inputs is not recommended; however, if ac coupling is

necessary, suitable circuitry must be provided following the ac

coupling element to provide proper dc level and bias currents at

the ADA4410-6 input stages.

The ADA4410-6 outputs can be either ac- or dc-coupled. As

discussed in the Output DC Offset Control section, the CV

output offset is different from the other outputs, and the CV

output is generally ac-coupled.

In single-supply applications, a positive output offset must be

applied to keep the negative-most excursions of the output

signals above the specified minimum output swing limit.

Figure 23 and Figure 24 illustrate several ways to use the

LEVEL1 and LEVEL2 inputs. Figure 23 shows an example of

how to generate fully adjustable LEVEL1 and LEVEL2 voltages

from 5 V and single +5 V supplies. These circuits show a

general case, but a more practical approach is to fix one voltage

and vary the other. Figure 24 illustrates an effective way to

produce a 600 mV output offset voltage in a single-supply

application. Although the LEVEL2 input could simply be

connected to GND, Figure 24 includes bypassed resistive

voltage dividers for each input so that the input levels can be

changed, if necessary. Additionally, many in-circuit testers

require that I/O signals not be tied directly to the supplies or

GND. DNP indicates do not populate.

When driving single ac-coupled loads in standard 75 Ω video

distribution systems, 220 μF coupling capacitors are recommended

for use on all but the chrominance signal output. Because the

chrominance signal is a narrow-band modulated carrier, it has

no low frequency content and can therefore be coupled with a

0.1 μF capacitor.

There are two ac coupling options when driving two loads from

one output. One is to simply use the same value capacitor on

the second load, while the other is to use a common coupling

capacitor that is at least twice the value used for the single load

(see Figure 25 and Figure 26).

75Ω

CABLE

220µF

75Ω

DUAL SUPPLY

+5V

9.53kΩ

+5V

75Ω

9.53kΩ

75Ω

CABLE

220µF

LEVEL1

0.1µF

LEVEL2

0.1µF

75Ω

1kΩ

9.53kΩ

–5V

Figure 25. Driving Two AC-Coupled Loads with Two Coupling Capacitors

SINGLE SUPPLY

+5V

75Ω

CABLE

75Ω

9.09kΩ

1kΩ

9.09kΩ

1kΩ

LEVEL1

0.1µF

LEVEL2

0.1µF

470µF

75Ω

CABLE

75Ω

Figure 23. Generating Fully Adjustable Output Offsets

75Ω

Figure 26. Driving Two AC-Coupled Loads with One Common Coupling Capacitor

Rev. B | Page 14 of 16

ADA4410-6

When the ADA4410-6 receives its inputs from a device with

current outputs, the required load resistor value for the output

current is often different from the characteristic impedance of

the signal traces. In this case, if the interconnections are sufficiently

short (<< 0.1 wavelength), the trace does not have to be terminated

in its characteristic impedance. Figure 27 shows an example in

which the ADA4410-6 input originates from DACs that require

300 Ω load resistors. Traces of 75 ꢀ can be used in this instance,

provided their lengths are an inch or two at the most. This is

easily achieved because the ADA4410-6 and the device feeding

it are usually adjacent to each other, and connections can be

made that are less than one inch in length.

PRINTED CIRCUIT BOARD LAYOUT

As with all high speed applications, attention to printed circuit

board layout is of paramount importance. Standard high speed

layout practices should be adhered to when designing with the

ADA4410-6. A solid ground plane is recommended, and

surface-mount ceramic power supply decoupling capacitors

should be placed as close as possible to the supply pins. All of

the ADA4410-6 GND pins should be connected to the ground

plane with traces that are as short as possible. Controlled

impedance traces of the shortest length possible should be used

to connect to the signal I/O pins and should not pass over any

voids in the ground plane. A 75 Ω impedance level is typically

used in video applications. All signal outputs of the ADA4410-6

should include series termination resistors when driving

transmission lines.

VIDEO ENCODER RECONSTRUCTION FILTER

The ADA4410-6 is easily applied as a reconstruction filter at the

DAC outputs of a video encoder. Figure 27 illustrates how to use

the ADA4410-6 in this type of application with an ADV7314 video

encoder in a single-supply application with ac-coupled outputs.

NOTE: EACH POWER SUPPLY PIN MUST HAVE ITS OWN DECOUPLING NETWORK

5V

(ANALOG)

2.5V

(ANALOG)

2.5V/3.3V

(DIGITAL I/O)

2.5V

(DIGITAL)

DEVICE

ADDRESS

SELECT

0.1µF

5kΩ

1.1kΩ

4.7kΩ

0.01µF 0.1µF

0.01µF

10, 56

0.1µF

45

0.1µF

41

36

10kΩ

634Ω

DNP*

16

26

V

COMP1

COMP2

V

DD

V

AA

REF

46

1

VCC

DD_IO

0Ω

AD1580

0.1µF

29

0.1µF

LEVEL1

0.1µF

5kΩ

0.01µF

28

LEVEL2

33

+

19

22

21

20

44

2

RESET

5kΩ 5kΩ

I C

DNP*

ADA4410-6

DISABLE

100Ω

4.7µF

SCLK

SDA

RESET

820pF

27

21

11

30

4

2

I C

BUS

75Ω

18

CV_OUT

G_SEL

220µF

0.1µF

220µF

34

EXT_LF

MUX_SD

MUX_HD

F_SEL_A

F_SEL_B

BINARY

CONTROL

INPUTS

ALSB

DAC A

3.5pF

4.7kΩ

20

19

24

23

22

ADV7314

Y_SD_OUT

NC

5

2-9, 12, 13

Y9–Y0

C9–C0

S9–S0

C_SD_OUT

43

42

39

38

37

12

13

DAC B

DAC C

DAC D

DAC E

DAC F

Y1_SD

Y2_SD

DIGITAL

VIDEO

BUSES

14-18, 26-30

51-55, 58-62

300Ω

Y/G_HD_OUT

Pb/B_HD_OUT

Pr/R_HD_OUT

14

15

C1_SD

C2_SD

32

63

31

6

CLKIN_A

CLKIN_B

Y1/G1_HD

Y2/G2_HD

PIXEL

CLOCKS

23

24

25

1

8

P_HSYNC

P_VSYNC

P_BLANK

Pb1/B1_HD

Pb2/B2_HD

SYNC AND

BLANKING

SIGNALS

3

Pr1/R1_HD

Pr2/R2_HD

10

50

49

48

31

S_HSYNC

S_VSYNC

S_BLANK

3.04kΩ

47

35

GND

VEE

R

SET1

2, 7, 9, 32

17, 25

MULTIFUNCTIONAL

INPUT

3.04kΩ

RTC_SCR_TR

R

SET2

CHANNEL 2

VIDEO INPUTS

GND_IO

64

DGND

11, 57

AGND

40

*DO NOT POPULATE

Figure 27. The ADA4410-6 Applied as a Reconstruction Filter Following the ADV7314

Rev. B | Page 1± of 16

ADA4410-6

OUTLINE DIMENSIONS

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

3.25

3.10 SQ

2.95

EXPOSED

PAD

(BOTTOM VIEW)

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

3.50 REF

0.80 MAX

0.65 TYP

12° MAX

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 28. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Ordering

Quantity

Model

Temperature Range

–40°C to +8±°C

Package Description

Package Option

ADA4410-6ACPZ-R2¹

ADA4410-6ACPZ-R7¹

ADA4410-6ACPZ-RL¹

32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

CP-32-2

2±0

1,±00

±,000

–40°C to +8±°C

¹Z = Pb-free part.

©

registered trademarks are the property of their respective owners.

D05265–0–3/06(B)

Rev. B | Page 16 of 16


型号：	ADA4410-6ACPZ-RL
厂家：	ADI
描述：	Integrated Video Filter with Selectable Cutoff Frequencies for RGB, HD/SD Y, C, and CV 集成视频滤波器，具有可选截止频率为RGB ， HD / SD Y， C和CV
文件：	总16页 (文件大小：457K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADA4410-6ACPZ-RL [ADI]

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