ADA4938-1ACPZ-RL [ADI]
Ultra-Low Distortion Differential ADC Driver; 超低失真差分ADC驱动器
| 型号： | ADA4938-1ACPZ-RL |
| 厂家： | 
ADI |
| 描述： | Ultra-Low Distortion Differential ADC Driver |
| 文件： | 总14页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra-Low Distortion
Differential ADC Driver
Preliminary Technical Data
ADA4938-1
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Extremely low harmonic distortion
−112 dBc HD2 @ 10 MHz
−79 dBc HD2 @ 50 MHz
−102 dBc HD3 @ 10 MHz
−81 dBc HD3 @ 50 MHz
Low input voltage noise: 2.2 nV/√Hz
High speed
−3 dB bandwidth of 1.5 GHz, G = 1
Slew rate: 4700 V/μs
0.1 dB gain flatness to 125 MHz
Fast overdrive recovery of 4 ns
1 mV typical offset voltage
Externally adjustable gain
+
–
Differential to differential or single-ended to differential
operation
Adjustable output common-mode voltage
Wide Supply Voltage Range: +5 V & 5 V
Pb-free 3 mm x 3 mm LFCSP package
Figure 1.
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
GENERAL DESCRIPTION
The ADA4938-1 is a low noise, ultra-low distortion, high speed
differential amplifier. It is an ideal choice for driving high
performance ADCs with resolutions up to 16 bits from dc to 70
MHz. The output common mode voltage is adjustable over a
wide range, allowing the ADA4938-1 to match the input of the
ADC. The internal common mode feedback loop also provides
exceptional output balance as well as suppression of even-order
harmonic distortion products.
The ADA4938-1 is fabricated using ADI’s proprietary third
generation high-voltage XFCB process, enabling it to achieve
very low levels of distortion with input voltage noise of only 2.2
nV/√Hz. The low dc offset and excellent dynamic performance
of the ADA4938-1 make it well suited for a wide variety of data
acquisition and signal processing and applications.
The ADA4938-1 is available in a Pb-free, 3 mm x 3mm lead
frame chip scale package (LFCSP). Pinout has been optimized
to facilitate layout and minimize distortion. The part is
specified to operate over the extended industrial temperature
range of −40°C to +85°C.
Full differential and single-ended to differential gain
configurations are easily realized with the ADA4938-1. A
simple external feedback network of four resistors determines
the amplifier’s closed-loop gain.
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
ADA4938-1
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Definition of Terms.......................................................................9
Theory of Operation ...................................................................... 10
Analyzing an Application Circuit ............................................ 10
Setting the Closed-Loop Gain .................................................. 10
Estimating the Output Noise Voltage...................................... 10
The Impact of Mismatches in the Feedback Networks......... 11
Calculating the Input Impedance of an Application Circuit 11
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply Operation................................................................ 3
Single Supply Operation.............................................................. 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Operational Description.................................................................. 9
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 11
Setting the Output Common-Mode Voltage.......................... 11
Layout, Grounding, and Bypassing.............................................. 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
05/07—Rev. PrC to Rev. PrD
Changes to Features.......................................................................... 1
Changes to Figure 1.......................................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Figure 3.......................................................................... 8
Changes to Table 5 ........................................................................... 8
Added to Operational Description Section .................................. 9
Added to Theory of Operation Section....................................... 10
Added to Layout, Grounding, and Bypassing Section............... 13
04/07—Rev. PrB to Rev. PrC
Changes to Features.......................................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Table 3............................................................................ 7
Changes to Table 4............................................................................ 7
Added Figure 2 ................................................................................. 7
Changes to Figure 4.......................................................................... 9
Changes to Ordering Guide ............................................................ 9
01/07—Rev. PrA to Rev. PrB
Changes to Features.......................................................................... 1
Changes to General Description .................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
12/06—Revision PrA: Initial Version
Rev. PrD | Page 2 of 14
Preliminary Technical Data
ADA4938-1
SPECIFICATIONS
DUAL SUPPLY OPERATION
TA = 25°C, +VS = 5 V, −VS = -5 V, VOCM = 0 V, RT = 61.9 Ω, RG = RF = 200 Ω, G = 1, RL, dm = 1 kꢀ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max Unit
DIN TO OꢀT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
VOꢀT = 0.1 V p-p, Differential Input
VOꢀT = 2 V p-p, Differential Input
VOꢀT = 2 V p-p, Differential Input
VOꢀT = 4 V p-p, Differential Input
VOꢀT = 2 V p-p
1500
125
1300
800
4700
4
MHz
MHz
MHz
MHz
V/μs
ns
Slew Rate
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
VIN = 5 V to 0 V step, G = +2
VOꢀT = 2 V p-p, 10 MHz
VOꢀT = 2 V p-p, 50 MHz
VOꢀT = 2 V p-p, 10 MHz
VOꢀT = 2 V p-p, 50 MHz
50 MHz
−112
−79
−102
−81
dBc
dBc
dBc
dBc
Third Harmonic
IMD
dBc
IP3
50 MHz
dBm
nV/√Hz
dB
Voltage Noise (RTI)
Noise Figure
Input Current Noise
INPꢀT CHARACTERISTICS
Offset Voltage
2.2
21
2
G = +2
pA/√Hz
VOS, dm = VOꢀT, dm/2; VDIN+ = VDIN− = 0 V
TMIN to TMAX variation
1
4
3.5
−0.01
6
3
1
mV
μV/°C
μA
μA/°C
MΩ
MΩ
pF
Input Bias Current
Input Resistance
TMIN to TMAX variation
Differential
Common mode
Input Capacitance
Input Common-Mode Voltage
CMRR
−4.7 to 3.4
−77
V
dB
∆VOꢀT, dm/∆VIN, cm; ∆VIN, cm = 1 V
OꢀTPꢀT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Output Balance Error
VOCM to OꢀT PERFORMANCE
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Maximum ∆VOꢀT; single-ended output
∆VOꢀT, cm/∆VOꢀT, dm; ∆VOꢀT, dm = 1 V; 10 MHz
-3.9
3.9
V
mA
dB
95
−66
400
1700
7.5
MHz
V/μs
nV/√Hz
Slew Rate
Input Voltage Noise (RTI)
VOCM INPꢀT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
−3.8
3.8
3.5
V
200
1
0.5
−75
1
kΩ
mV
μA
dB
V/V
VOS, cm = VOꢀT, cm; VDIN+ = VDIN– = 0 V
∆VOꢀT, dm/∆VOCM; ∆VOCM = 1 V
∆VOꢀT, cm/∆VOCM; ∆VOCM = 1 V
Gain
POWER SꢀPPLY
Operating Range
4.5
11
V
Rev. PrD | Page 3 of 14
ADA4938-1
Preliminary Technical Data
Parameter
Conditions
Min
Typ
40
Max Unit
Quiescent Current
mA
TMIN to TMAX variation
Powered down
∆VOꢀT, dm/∆VS; ∆VS = 1 V
40
< 1
−90
μA/°C
mA
dB
Power Supply Rejection Ratio
PD
POWER DOWN (
)
PD
Powered down
Enabled
≤ 1
≥ 2
1
V
Input Voltage
V
μs
ns
Turn-Off Time
Turn-On Time
200
PD
Bias Current
Enabled
Disabled
PD
PD
40
μA
μA
= 5 V
= 0 V
200
OPERATING TEMPERATꢀRE RANGE
−40
+85
°C
Rev. PrD | Page 4 of 14
Preliminary Technical Data
ADA4938-1
SINGLE SUPPLY OPERATION
TA = 25°C, +VS = 5 V, −VS = 0 V, VOCM = +VS/2, RT = 61.9 Ω, RG = RF = 200 Ω, G = 1, RL, dm = 1 kꢀ, unless otherwise noted.
All specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max Unit
DIN TO OꢀT PERFORMANCE
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
VOꢀT = 0.1 V p-p, Differential Input
VOꢀT = 2 V p-p, Differential Input
VOꢀT = 2 V p-p, Differential Input
VOꢀT = 2 V p-p
1500
125
1100
3900
4
MHz
MHz
MHz
V/μs
ns
VIN = 2.5 V to 0 V step, G = +2
VOꢀT = 2 V p-p, 10 MHz
VOꢀT = 2 V p-p, 50 MHz
VOꢀT = 2 V p-p, 10 MHz
VOꢀT = 2 V p-p, 50 MHz
50 MHz
−110
−79
−100
−79
dBc
dBc
dBc
dBc
dBc
dBm
Third Harmonic
IMD
IP3
50 MHz
Voltage Noise (RTI)
Noise Figure
Input Current Noise
INPꢀT CHARACTERISTICS
Offset Voltage
2.2
21
2
nV/√Hz
dB
pA/√Hz
G = +2
VOS, dm = VOꢀT, dm/2; VDIN+ = VDIN− = VOCM = 2.5 V
TMIN to TMAX variation
1
4
3.5
−0.01
6
3
1
mV
μV/°C
μA
μA/°C
MΩ
MΩ
pF
Input Bias Current
Input Resistance
TMIN to TMAX variation
Differential
Common mode
Input Capacitance
Input Common-Mode Voltage
CMRR
0.3 to 3.4
−77
V
dB
∆VOꢀT, dm/∆VIN, cm; ∆VIN, cm = 1 V
OꢀTPꢀT CHARACTERISTICS
Output Voltage Swing
Output Current
Output Balance Error
VOCM TO OꢀT PERFORMANCE
VOCM DYNAMIC PERFORMANCE
−3 dB Bandwidth
Maximum ∆VOꢀT; single-ended output
∆VOꢀT, cm/∆VOꢀT, dm; ∆VOꢀT, dm = 1 V
1.1
3.9
V
mA
dB
95
−66
400
1700
7.5
MHz
V/μs
nV/√Hz
Slew Rate
V = 0.5 V
Input Voltage Noise (RTI)
VOCM INPꢀT CHARACTERISTICS
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
1.2
4.5
3.8
V
200
1
0.5
−75
1
kΩ
mV
μA
dB
V/V
VOS, cm = VOꢀT, cm; VDIN+ = VDIN– = VOCM = 2.5 V
∆VOꢀT, dm/∆VOCM; ∆VOCM = 1 V
∆VOꢀT, cm/∆VOCM; ∆VOCM = 1 V
Gain
POWER SꢀPPLY
Operating Range
11
V
Quiescent Current
36
40
< 1
mA
μA/°C
mA
TMIN to TMAX variation
Powered down
Rev. PrD | Page 5 of 14
ADA4938-1
Preliminary Technical Data
Parameter
Conditions
Min
Typ
Max Unit
Power Supply Rejection Ratio
∆VOꢀT, dm/∆VS; ∆VS = 1 V
−90
dB
PD
POWER DOWN (
)
PD
Powered down
Enabled
≤ 1
≥ 2
1
V
Input Voltage
V
μs
ns
Turn-Off Time
Turn-On Time
PD Bias Current
Enabled
200
PD
PD
20
μA
μA
= 5 V
Disabled
−120
= 0 V
OPERATING TEMPERATꢀRE RANGE
−40
+85
°C
Rev. PrD | Page 6 of 14
Preliminary Technical Data
ADA4938-1
ABSOLUTE MAXIMUM RATINGS
The power dissipated in the package (PD) is the sum of the
Table 3.
Parameter
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the
voltage between the supply pins (VS) times the quiescent
current (IS). The power dissipated due to the load drive depends
upon the particular application. The power due to load drive is
calculated by multiplying the load current by the associated
voltage drop across the device. RMS voltages and currents must
be used in these calculations.
Rating
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
12 V
See Figure 2
−65°C to +125°C
−40°C to +85°C
300°C
150°C
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package
leads/exposed pad from metal traces, through-holes, ground,
and power planes reduces the θJA.
Stresses above those listed under Absolute Maximum
Rating may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational section of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 16-lead LFCSP
(95 °C/W) on a JEDEC standard 4-layer board.
THERMAL RESISTANCE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
θJA is specified for the device (including exposed pad)
soldered to a high thermal conductivity 2s2p circuit board,
as described in EIA/JESD 51-7.
Table 4. Thermal Resistance
Package Type
θJA
Unit
16-Lead LFCSP (Exposed Pad)
95
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4938-1
package is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which
is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature
limit can change the stresses that the package exerts on the
die, permanently shifting the parametric performance of
the ADA4938-1. Exceeding a junction temperature of 150°C
for an extended period can result in changes in the silicon
devices, potentially causing failure.
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. PrD | Page 7 of 14
ADA4938-1
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
−FB
+IN
Negative Output for Feedback Component Connection
Positive Input Summing Node
3
4
−IN
+FB
+VS
VOCM
+OꢀT
−OꢀT
PD
Negative Input Summing Node
Positive Output for Feedback Component Connection
Positive Supply Voltage
Output Common-Mode Voltage
Positive Output for Load Connection
Negative Output for Load Connection
Power-Down Pin
5 to 8
9
10
11
12
13 to 16
−VS
Negative Supply Voltage
Rev. PrD | Page 8 of 14
Preliminary Technical Data
ADA4938-1
OPERATIONAL DESCRIPTION
Common-Mode Voltage
DEFINITION OF TERMS
This refers to the average of two node voltages. The output
common-mode voltage is defined as
V
OUT, cm = (V+OUT + V−OUT)/2
Balance
Balance is a measure of how well differential signals are
matched in amplitude and are exactly 180° apart in phase.
Balance is most easily determined by placing a well-matched
resistor divider between the differential voltage nodes and
comparing the magnitude of the signal at the divider’s midpoint
with the magnitude of the differential signal. By this definition,
output balance is the magnitude of the output common-mode
voltage divided by the magnitude of the output differential
mode voltage.
Figure 4. Circuit Definitions
Differential Voltage
This refers to the difference between two node voltages. For
example, the output differential voltage (or equivalently, output
differential-mode voltage) is defined as
VOUT, cm
Output Balance Error =
VOUT, dm
V
OUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Rev. PrD | Page 9 of 14
ADA4938-1
Preliminary Technical Data
THEORY OF OPERATION
The ADA4938-1 differs from conventional op amps in that it
has two outputs whose voltages move in opposite directions.
Like an op amp, it relies on open-loop gain and negative
feedback to force these outputs to the desired voltages. The
ADA4938-1 behaves much like a standard voltage feedback op
amp and makes it easier to perform single-ended-to-differential
conversions, common-mode level shifting, and amplifications
of differential signals. Also like an op amp, the ADA4938-1 has
high input impedance and low output impedance.
SETTING THE CLOSED-LOOP GAIN
The differential-mode gain of the circuit in Figure 4 can be
determined by
VOUT, dm
RF
RG
=
VIN, dm
This assumes the input resistors (RG) and feedback resistors (RF)
on each side are equal.
Two feedback loops are employed to control the differential and
common-mode output voltages. The differential feedback, set
with external resistors, controls only the differential output
voltage. The common-mode feedback controls only the common-
mode output voltage. This architecture makes it easy to set the
output common-mode level to any arbitrary value. It is forced,
by internal common-mode feedback, to be equal to the voltage
applied to the VOCM input, without affecting the differential
output voltage.
ESTIMATING THE OUTPUT NOISE VOLTAGE
The differential output noise of the ADA4938-1 can be
estimated using the noise model in Figure 5. The input-referred
noise voltage density, vnIN, is modeled as a differential input, and
the noise currents, inIN− and inIN+, appear between each input and
ground. The noise currents are assumed to be equal and
produce a voltage across the parallel combination of the gain
and feedback resistances. vnCM is the noise voltage density at the
VOCM pin. Each of the four resistors contributes (4kTRx)1/2. Table
6 summarizes the input noise sources, the multiplication factors,
and the output-referred noise density terms.
The ADA4938-1 architecture results in outputs that are highly
balanced over a wide frequency range without requiring tightly
matched external components. The common-mode feedback
loop forces the signal component of the output common-
mode voltage to zero. This results in nearly perfectly balanced
differential outputs that are identical in amplitude and are
exactly 180° apart in phase.
VnRG1
VnRF1
RG1
RF1
inIN+
+
VnIN
VnOD
inIN–
ADA4938-1
ANALYZING AN APPLICATION CIRCUIT
The ADA4938-1 uses open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and −IN (see
Figure 4). For most purposes, this voltage can be assumed to be
zero. Similarly, the difference between the actual output
common-mode voltage and the voltage applied to VOCM can also
be assumed to be zero. Starting from these two assumptions,
any application circuit can be analyzed.
VOCM
VnCM
RG2
RF2
VnRG2
VnRF2
Figure 5. ADA4938-1 Noise Model
Table 6. Output Noise Voltage Density Calculations
Input Noise
Voltage Density
Output
Multiplication Factor
Output Noise
Voltage Density Term
vnO1 = GN(vnIN
vnO2 = GN[inIN− × (RG2||RF2)]
vnO3 = GN[inIN+ × (RG1||RF1)]
Input Noise Contribution
Differential Input
Inverting Input
Noninverting Input
VOCM Input
Gain Resistor RG1
Gain Resistor RG2
Feedback Resistor RF1
Feedback Resistor RF2
Input Noise Term
vnIN
inIN−
inIN+
vnCM
vnRG1
vnRG2
vnRF1
vnRF2
vnIN
GN
GN
GN
)
inIN− × (RG2||RF2)
inIN+ × (RG1||RF1)
vnCM
(4kTRG1)1/2
(4kTRG2)1/2
(4kTRF1)1/2
(4kTRF2)1/2
GN(β1 − β2)
GN(1 − β2)
GN(1 − β1)
1
1
vnO4 = GN(β1 − β2)(vnCM)
vnO5 = GN(1 − β2)(4kTRG1)1/2
vnO6 = GN(1 − β1)(4kTRG2)1/2
vnO7 = (4kTRF1)1/2
vnO8 = (4kTRF2)1/2
Rev. PrD | Page 10 of 14
Preliminary Technical Data
ADA4938-1
Similar to the case of a conventional op amp, the output noise
voltage densities can be estimated by multiplying the input-
referred terms at +IN and −IN by the appropriate output factor,
where:
2
GN
=
is the circuit noise gain.
(
β1 + β2
RG1
F1 + RG1
)
RG2
β1 =
and β2 =
are the feedback factors.
R
RF2 + RG2
Figure 6. ADA4938-1 Configured for Balanced (Differential) Inputs
When RF1/RG1 = RF2/RG2, then β1 = β2 = β, and the noise gain
becomes
For an unbalanced, single-ended input signal (see Figure 7), the
input impedance is
1
β
RF
RG
GN = =1+
⎛
⎜
⎞
⎟
RG
RF
RG + RF
⎜
⎜
⎟
⎟
Note that the output noise from VOCM goes to zero in this case.
The total differential output noise density, vnOD, is the root-sum-
square of the individual output noise terms.
RIN, cm =
1−
⎜
⎟
2×
(
)
⎝
⎠
8
vnOD
=
v2
nOi
∑
i=1
THE IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback networks
(RF/RG) are mismatched, the internal common-mode feedback
loop still forces the outputs to remain balanced. The amplitudes
of the signals at each output remain equal and 180° out of phase.
The input-to-output, differential mode gain varies proportionately
to the feedback mismatch, but the output balance is unaffected.
Figure 7. ADA4938-1 Configured for Unbalanced (Single-Ended) Input
The input impedance of the circuit is effectively higher than it
would be for a conventional op amp connected as an inverter
because a fraction of the differential output voltage appears at
the inputs as a common-mode signal, partially bootstrapping
the voltage across the input resistor RG.
As well as causing a noise contribution from VOCM, ratio
matching errors in the external resistors result in a degradation
of the ability of the circuit to reject input common-mode signals,
much the same as for a four-resistor difference amplifier made
from a conventional op amp.
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
In addition, if the dc levels of the input and output common-
mode voltages are different, matching errors result in a small
differential-mode output offset voltage. When G = 1, with a
ground referenced input signal and the output common-mode
level set to 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worst-
case input CMRR of about 40 dB, a worst-case differential-
mode output offset of 25 mV due to 2.5 V level-shift, and no
significant degradation in output balance error.
The ADA4938-1 is optimized for level-shifting, ground-referenced
input signals. As such, the center of the input common-mode
range is shifted approximately 1 V down from midsupply. For
5 V single-supply operation, the input common-mode range at
the summing nodes of the amplifier is 0.3 V to 3.0 V. To avoid
clipping at the outputs, the voltage swing at the +IN and –IN
terminals must be confined to these ranges.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The VOCM pin of the ADA4938-1 is internally biased at a voltage
approximately equal to the midsupply point (average value of
the voltages on V+ and V−). Relying on this internal bias results
in an output common-mode voltage that is within about 100 mV of
the expected value.
CALCULATING THE INPUT IMPEDANCE OF AN
APPLICATION CIRCUIT
The effective input impedance of a circuit depends on whether
the amplifier is being driven by a single-ended or differential
signal source. For balanced differential input signals, as shown
in Figure 6, the input impedance (RIN, dm) between the inputs
(+DIN and −DIN) is simply RIN, dm = 2 × RG.
In cases where more accurate control of the output common-
mode level is required, it is recommended that an external
source, or resistor divider (10 kꢀ or greater resistors), be used.
It is also possible to connect the VOCM input to a common-mode
level (CML) output of an ADC. However, care must be taken to
Rev. PrD | Page 11 of 14
ADA4938-1
Preliminary Technical Data
assure that the output has sufficient drive capability. The input
impedance of the VOCM pin is approximately 10 kꢀ. If multiple
ADA4938-1 devices share one reference output, it is
recommended that a buffer be used.
Table 7 and Table 8 list several common gain settings,
associated resistor values, input impedance, output noise
density, and approximate large signal bandwidth for both balanced
and unbalanced input configurations. Also shown are the input
common-mode voltage swings under the given conditions for
different VOCM settings with both dual and single 5 V supplies.
Table 7. Differential Ground-Referenced Input, DC-Coupled; See Figure 6
Common-Mode Swing at +IN, −IN (V)
Differential
Output
Noise Density Bandwidth (MHz)
Approximate
Large-Signal
+VS = 5 V, -VS = -5 V
VOUT, dm = 2.0 V p-p
VOCM = 0 V
+VS =5 V
VOUT, dm = 2.0 V p-p
Nominal
Gain (dB) RF (Ω) RG (Ω) RIN, dm(Ω) (nV/√Hz)
VOCM = 3.5 V VOCM = 2.5 V
VOCM = 3.2 V
0
200
348
280
348
200
348
316
348
402
348
499
348
200
348
200
249
100
174
100
110
100
86.6
100
69.8
400
696
400
498
200
348
200
220
200
173
200
140
5.8
6.7
7.2
7.6
8.0
9.0
11
12
14
13
17
-0.50 to 0.50 1.25 to 2.25
-0.35 to 0.35 1.10 to 1.82
-0.25 to 0.25 0.92 to 1.42
-0.16 to 0.16 0.68 to 1.00
-0.13 to 0.13 0.57 to 0.82
-0.10 to 0.10 0.48 to 0.68
0.75 to 1.75
0.69 to 1.40
0.58 to 1.08
0.44 to 0.76
0.37 to 0.62
0.32 to 0.52
1.10 to 2.10
0.98 to 1.69
0.82 to 1.32
0.61 to 0.92
0.51 to 0.76
0.43 to 0.63
3
6
10
12
14
16
Table 8. Single-Ended Ground-Referenced Input, DC-Coupled, RS = 50 Ω; See Figure 7
Differential
Output
Noise
Density
(nV/√Hz)
Common-Mode Swing at +IN, -IN (V)
Approximate
Large-Signal
Bandwidth
(MHz)
+VS = 5 V, -VS = -5 V
VOUT,dm = 2.0 V p-p
VOCM = 0 V
+VS =5 V
VOUT, dm = 2.0 V p-p
Nominal
Gain (dB) (Ω) (Ω)
RF
RG1
RT
(Ω)
RIN,cm RG2
(Ω)
(Ω)1
VOCM = 3.5 V VOCM = 2.5 V VOCM = 3.2 V
0
200 200 61.9 267
348 348 56.2 464
280 200 60.4 282
348 249 59.0 351
200 100 75.0 150
348 174 61.9 261
316 100 73.2 161
348 110 69.8 177
402 100 71.5 167
348 86.6 76.8 144
499 100 71.5 171
348 69.8 86.6 120
226 5.5
374 6.5
226 6.8
274 7.3
130 7.0
200 8.4
130 9.7
140 10
130 12
118 11
130 14
100 12
-0.56 to 0.56 1.29 to 2.42
-0.40 to 0.40 1.16 to 1.97
-0.33 to 0.33 1.05 to 1.70
-0.21 to 0.21 0.82 to 1.23
-0.16 to 0.16 0.70 to 1.02
-0.13 to 0.13 0.59 to 0.85
0.75 to 1.75
0.71 to 1.52
0.66 to 1.31
0.52 to 0.93
0.45 to 0.77
0.39 to 0.65
1.13 to 2.26
1.03 to 1.83
0.94 to 1.59
0.73 to 1.14
0.62 to 0.94
0.53 to 0.79
3
6
10
12
14
1 RG2 = RG1 + (RS||RT)
Rev. PrD | Page 12 of 14
Preliminary Technical Data
ADA4938-1
LAYOUT, GROUNDING, AND BYPASSING
As a high speed device, the ADA4938-1 is sensitive to the
PCB environment in which it operates. Realizing its superior
performance requires attention to the details of high speed
PCB design.
The power supply pins should be bypassed as close to the device
as possible and directly to a nearby ground plane. High frequency
ceramic chip capacitors should be used. It is recommended that
two parallel bypass capacitors (1000 pF and 0.1 μF) be used for
each supply. The 1000 pF capacitor should be placed closer to
the device. Further away, low frequency bypassing should be
provided, using 10 μF tantalum capacitors from each supply
to ground.
The first requirement is a solid ground plane that covers as
much of the board area around the ADA4938-1 as possible.
However, the area near the feedback resistors (RF), gain resistors
(RG), and the input summing nodes (Pin 2 and Pin 3) should be
cleared of all ground and power planes (see Figure 8). This
minimizes any stray capacitance at these nodes and prevents
peaking of the response of the amplifier at high frequencies.
Signal routing should be short and direct to avoid parasitic
effects. Wherever complementary signals exist, a symmetrical
layout should be provided to maximize balanced performance.
When routing differential signals over a long distance, PCB
traces should be close together, and any differential wiring
should be twisted such that loop area is minimized. This
reduces radiated energy and makes the circuit less susceptible
to interference.
Figure 8. Ground and Power Plane Voiding in Vicinity of RF and RG
Rev. PrD | Page 13 of 14
Preliminary Technical Data
OUTLINE DIMENSIONS
ADA4938-1
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
13
12
16
1
0.45
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
9 (BOTTOM VIEW)
4
0.50
BSC
8
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
1.00
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 9. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body
(CP-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Ordering Quantity Temperature Range
Package Description
Package Option
Branding
TBD
TBD
ADA4938-1ACPZ-R2 5,000
ADA4938-1ACPZ-RL 1,500
ADA4938-1ACPZ-R7 250
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
16-Lead 3 mm × 3 mm LFCSP CP-16-2
16-Lead 3 mm × 3 mm LFCSP CP-16-2
16-Lead 3 mm × 3 mm LFCSP CP-16-2
TBD
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06592-0-6/07(PrD)
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