ADAS3022SCPZ-EP [ADI]
16-Bit, 1 MSPS, 8 Channel Data Acquisition System;
| 型号： | ADAS3022SCPZ-EP |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 1 MSPS, 8 Channel Data Acquisition System |
| 文件： | 总40页 (文件大小：802K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, 1 MSPS, 8-Channel
Data Acquisition System
ADAS3022
Data Sheet
and buffer; and a 16-bit charge redistribution analog-to-digital
converter (ADC) with successive approximation register (SAR)
architecture. The ADAS3022 can resolve eight single-ended
inputs or four fully differential inputs up to ±24.576 V when
using 15 V supplies. In addition, the device can accept the
commonly used bipolar differential, bipolar single-ended,
pseudo bipolar, or pseudo unipolar input signals, as shown in
Table 1, thus enabling the use of almost any direct sensor
interface.
FEATURES
Ease of use—16-bit, 1 MSPS complete data acquisition system
High impedance, 8-channel input: >500 MΩ
Differential input voltage range: 24.576 V maximum
High input common-mode rejection: >100 dB
User-programmable input ranges
Channel sequencer with individual channel gains
On-chip 4.096 V reference and buffer
Auxiliary input—direct interface to PulSAR ADC inputs
No latency or pipeline delay (SAR architecture)
Serial 4-wire, 1.8 V to 5 V SPI-/SPORT-compatible interface
LFCSP package (6 mm × 6 mm)
The ADAS3022 simplifies design challenges by eliminating
signal buffering, level shifting, amplification/attenuation,
common-mode rejection, settling time, and any other analog
signal conditioning challenge while allowing a smaller form
factor, faster time to market, and lower cost.
−40°C to +85°C industrial temperature range
APPLICATIONS
Multichannel data acquisition and system monitoring
Process control
Power line monitoring
Table 1. Typical Input Range Selection
Signal
Input Range, VIN (V)
Differential
1 V
Automated test equipment
Instrumentation
1.28 V
2.5 V
5 V
10 V
2.56 V
10.24 V
20.48 V
GENERAL DESCRIPTION
The ADAS3022 is a complete 16-bit, 1 MSPS, successive approxi-
mation–based analog-to-digital data acquisition system, which is
manufactured on Analog Devices, Inc., proprietary iCMOS® high
voltage industrial process technology. The device integrates an
8-channel, low leakage multiplexer; a high impedance program-
mable gain instrumentation amplifier (PGIA) stage with high
common-mode rejection; a precision, low drift 4.096 V reference
Single Ended1
0 V to 1 V
0 V to 2.5 V
0 V to 5 V
0 V to 10 V
0.64 V
1.28 V
2.56 V
5.12 V
1 See Figure 59 and Figure 60 in the Analog Inputs section for more information.
FUNCTIONAL BLOCK DIAGRAM
AVDD
DVDD
VIO
RESET
PD
VDDH
DIFF TO
COM
DIFF
PAIR
ADAS3022
CNV
LOGIC/
INTERFACE
IN0/IN1
BUSY
IN0
IN1
CS
IN2
IN2/IN3
IN4/IN5
IN6/IN7
IN3
SCK
DIN
SDO
PulSAR
ADC
PGIA
MUX
IN4
IN5
IN6
IN7
TEMP
SENSOR
COM
AUX+
BUF
REFIN
REF
AUX–
VSSH
AGND
DGND
REFx
Figure 1.
Rev. A
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ADAS3022
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Application Connection Diagram.............................. 24
Analog Inputs.............................................................................. 25
Voltage Reference Output/Input .............................................. 28
Power Supply............................................................................... 29
Conversion Modes ..................................................................... 30
Digital Interface .............................................................................. 31
Conversion Control ................................................................... 31
Reset and Power-Down (PD) Inputs ....................................... 32
Serial Data Interface................................................................... 32
General Considerations............................................................. 33
General Timing........................................................................... 34
Configuration Register .............................................................. 36
Channel Sequencer Details ....................................................... 37
Outline Dimensions....................................................................... 39
Ordering Guide .......................................................................... 39
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 22
Overview...................................................................................... 22
ADAS3022 Operation................................................................ 22
Transfer Function ....................................................................... 23
REVISION HISTORY
1/13—Rev. 0 to Rev. A
Removed Endnote 3 and Added TA = 25°C to Gain Error Test
Conditions/Comments, Table 2...................................................... 3
Changes to REF1 and REF2 Description..................................... 11
Added Figure 25 to Figure 28; Renumbered Sequentially ........ 15
Changes to Figure 29...................................................................... 15
Added Figure 30.............................................................................. 16
Changes to Figure 33, Figure 34, and Figure 35 ......................... 16
Changes to Figure 36 and Figure 37............................................. 17
Changes to Figure 50...................................................................... 19
Changes to Figure 54...................................................................... 24
Changes to Figure 56...................................................................... 25
Changes to Figure 57, Figure 58, Figure 59, and Figure 60....... 26
Changes to Voltage Reference Output/Input Section, Figure 62,
and Figure 63................................................................................... 28
Changes to Core Supplies Section................................................ 29
11/12—Revision 0: Initial Version
Rev. A | Page 2 of 40
Data Sheet
ADAS3022
SPECIFICATIONS
VDDH = 15 V 5%, VSSH = −15 V 5%, AVDD = DVDD = 5 V 5%, VIO = 1.8 V to AVDD, internal reference, VREF = 4.096 V,
fS = 1 MSPS. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit1
RESOLUTION
16
Bits
ANALOG INPUTS—IN[7:0], COM
Operating Input Voltage Range
Differential Input Voltage Range, VIN
VIN
VIN+ − VIN−
−VSSH + 2.5
VDDH − 2.5
V
PGIA gain = 0.16, VIN = 49.15 V p-p
PGIA gain = 0.2, VIN = 40.96 V p-p
PGIA gain = 0.4, VIN = 20.48 V p-p
PGIA gain = 0.8, VIN = 10.24 V p-p
PGIA gain = 1.6, VIN = 5.12 V p-p
PGIA gain = 3.2, VIN = 2.56 V p-p
PGIA gain = 6.4, VIN = 1.28 V p-p
−6VREF
−5VREF
−2.5VREF
−1.25VREF
−0.625VREF
−0.3125VREF
−0.1563VREF
+6VREF
+5VREF
+2.5VREF
+1.25VREF
+0.625VREF
+0.3125VREF
+0.1563VREF
V
V
V
V
V
V
V
Channel Off Leakage
Channel On Leakage
Common-Mode Voltage Range2
0.6
0.02
nA
nA
VIN+, VIN−; full-scale differential inputs
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
−5.12
−7.68
−8.96
−9.60
−9.92
+5.12
+7.68
+8.96
+9.60
+9.92
V
V
V
V
V
PGIA gain = 6.4
ANALOG INPUTS—AUX+, AUX−
Differential Input Voltage Range
THROUGHPUT
−VREF
+VREF
V
Conversion Rate
One channel/one pair
Two channels/two pairs
Four channels/four pairs
Eight channels
0
0
0
0
1000
500
250
125
520
kSPS
kSPS
kSPS
kSPS
ns
Transient Response
DC ACCURACY
Full-scale step
No Missing Codes
Integral Linearity Error
16
−2
−3
−5
−0.9
−0.9
−0.9
Bits
LSB
LSB
LSB
LSB
LSB
LSB
PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6
PGIA gain = 3.2
PGIA gain = 6.4
PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6
PGIA gain = 3.2
PGIA gain = 6.4
0.6
1.0
1.5
0.6
0.75
0.75
+2
+3
+5
+1.0
+1.25
+1.25
Differential Linearity Error
Transition Noise
External reference
PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6
PGIA gain = 3.2
5
7
LSB
LSB
PGIA gain = 6.4
11
LSB
Gain Error
Gain Error Temperature Drift
Offset Error
External reference, all PGIA gains, TA = 25°C
External reference, all PGIA gains
External reference, TA = 25°C
PGIA gain = 0.16, 0.2, 0.4, 0.8
PGIA gain = 1.6
−9
+9
0.1
LSB
ppm/°C
−3.0
−4.0
−7.5
−12.5
+0.2
+0.2
+0.2
+0.2
+3.0
+4.0
+7.5
+12.5
LSB
LSB
LSB
LSB
PGIA gain = 3.2
PGIA gain = 6.4
Rev. A | Page 3 of 40
ADAS3022
Data Sheet
Parameter
Test Conditions/Comments
External reference
Min
Typ
Max
Unit1
Offset Error Temperature Drift
PGIA gain = 0.16, 0.2, 0.4, 0.8
PGIA gain = 1.6
PGIA gain = 3.2
0.1
0.2
0.4
0.8
0.5
1.0
2.0
4.0
ppm/°C
ppm/°C
ppm/°C
ppm/°C
PGIA gain = 6.4
Total Unadjusted Error
External reference, TA = 25°C
PGIA gain = 0.16, 0.2, 0.4, 0.8, 1.6, 3.2
PGIA gain = 6.4
−9
−15
+9
+15
LSB
LSB
AC ACCURACY3
Signal-to-Noise Ratio (SNR)
fIN = 10 kHz
PGIA gain = 0.16
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
fIN = 10 kHz
90.0
90.0
89.5
89.0
88.0
86.0
83.0
91.5
91.5
91.5
91.0
89.7
86.8
84.5
dB
dB
dB
dB
dB
dB
dB
Signal-to-Noise-and-Distortion
(SINAD)
PGIA gain = 0.16
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
88.0
88.0
88.5
88.5
87.5
85.5
82.5
90.0
90.0
91.0
90.5
89.5
86.5
84.0
dB
dB
dB
dB
dB
dB
dB
PGIA gain = 3.2
PGIA gain = 6.4
Dynamic Range
fIN = 10 kHz, −60 dB input
PGIA gain = 0.16
PGIA gain = 0.2
91.0
91.0
90.5
90.0
89.0
86.0
83.5
92.0
92.0
91.5
91.0
90.0
87.0
85.0
−100
101
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Common-Mode Rejection Ratio
(CMRR)
fIN = 10 kHz, all PGIA gains
fIN = 10 kHz, all PGIA gains
fIN = 10 kHz, all channels inactive
fIN = 2 kHz
−120
PGIA gain = 0.16, 0.2, 0.4, 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
−40 dBFS
90.0
90.0
90.0
90.0
110.0
105.0
98.0
98.0
8
dB
dB
dB
dB
−3 dB Input Bandwidth
AUXILIARY ADC INPUT CHANNEL
DC Accuracy
MHz
External reference
Integral Nonlinearity Error
Differential Nonlinearity Error
Gain Error
−1.5
−0.8
−2.5
−5
0.5
0.6
0.2
0.2
+1.5
+1.0
+2.5
+5
LSB
LSB
LSB
LSB
Offset Error
Rev. A | Page 4 of 40
Data Sheet
ADAS3022
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit1
AC Performance
Internal reference
Signal-to-Noise Ratio (SNR)
Signal-to-Noise-and-Distortion
(SINAD)
90.0
89.5
93.0
92.5
dB
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
(SFDR)
−105
110
dB
dB
INTERNAL REFERENCE
REFx Output Voltage
REFx Output Current
REFx Temperature Drift
TA = 25°C
TA = 25°C
REFEN = 1
REFEN = 0
AVDD = 5 V 5%
4.088
4.096
250
5
4.104
2.505
V
µA
ppm/°C
ppm/°C
1
REFx Line Regulation
Internal Reference
Buffer Only
REFIN Output Voltage4
Turn-On Settling Time
EXTERNAL REFERENCE
Voltage Range
20
4
2.500
100
µV/V
µV/V
V
TA = 25°C
CREFIN, CREF1, CREF2 = 10 µF and 0.1 µF
2.495
4.000
ms
REFx input
REFIN input (buffered)
VREF = 4.096 V
4.096
2.5
100
4.104
2.505
V
V
µA
Current Drain
TEMPERATURE SENSOR
Output Voltage
Temperature Sensitivity
TA = 25 °C
275
800
mV
µV/°C
DIGITAL INPUTS
Logic Levels
VIL
VIH
VIL
VIH
IIL
IIH
VIO > 3 V
VIO > 3 V
VIO ≤ 3 V
VIO ≤ 3 V
−0.3
0.7 × VIO
−0.3
0.9 × VIO
−1
−1
+0.3 × VIO
VIO + 0.3
+0.1 × VIO
VIO + 0.3
+1
V
V
V
V
µA
µA
+1
DIGITAL OUTPUTS5
Data Format
VOL
VOH
Twos complement
0.4
ISINK = +500 µA
ISOURCE = −500 µA
PD = 0
V
V
VIO − 0.3
POWER SUPPLIES
VIO
1.8
AVDD + 0.3
5.25
5.25
15.75
−14.25
3.5
3.5
4.0
5.5
9.5
V
V
V
V
AVDD
4.75
4.75
14.25
−15.75
5
5
15
DVDD
VDDH6
VSSH6
IVDDH
VDDH > input voltage + 2.5 V
VSSH < input voltage − 2.5 V
PGIA gain = 0.16
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
−15
3.0
3.0
3.5
5.0
8.5
15.5
15.5
100
V
mA
mA
mA
mA
mA
mA
mA
µA
17.5
17.5
All PGIA gains, PD = 1
Rev. A | Page 5 of 40
ADAS3022
Data Sheet
Parameter
Test Conditions/Comments
PGIA gain = 0.16
PGIA gain = 0.2
PGIA gain = 0.4
PGIA gain = 0.8
PGIA gain = 1.6
PGIA gain = 3.2
PGIA gain = 6.4
All PGIA gains, PD = 1
PGIA gain = 6.4, reference buffer enabled
Min
Typ
−2.5
−2.5
−3.0
−4.5
−8.0
−15
−15
10
Max
Unit1
mA
mA
mA
mA
mA
mA
mA
µA
IVSSH
−3.0
−3.0
−3.5
−5.5
−9.5
−17.5
−17.5
IAVDD
18
16
21.0
19.0
mA
mA
All other PGIA gains, reference buffer
enabled
PGIA gain = 6.4, reference buffer disabled
All other PGIA gains, reference buffer
disabled
14
12
17.5
16.0
mA
mA
All PGIA gains, PD = 1
All PGIA gains, PD = 0
All PGIA gains, PD = 1
VIO = 3.3 V, PD = 0
PD = 1
100
2.5
10
0.30
10
µA
mA
µA
mA
µA
IDVDD
IVIO
3.5
1.2
Power Supply Sensitivity
At TA = 25°C
External reference
PGIA gain = 0.16, 0.2, 0.4, 0.8; VDDH/VSSH 5%
PGIA gain = 3.2, VDDH/VSSH 5%
PGIA gain = 6.4, VDDH/VSSH 5%
PGIA gain = 0.16, AVDD/DVDD 5%
PGIA gain = 0.2, AVDD/DVDD 5%
PGIA gain = 0.4, AVDD/DVDD 5%
PGIA gain = 0.8, AVDD/DVDD 5%
PGIA gain = 1.6, AVDD/DVDD 5%
PGIA gain = 3.2, AVDD/DVDD 5%
PGIA gain = 6.4, AVDD/DVDD 5%
0.5
1.0
2.0
0.6
0.8
1.0
1.5
2.0
3.5
7.0
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
−40
+85
°C
1 LSB means least significant bit and changes depending on the voltage range. See the Programmable Gain section for the LSB size.
2 The common-mode voltage (VCM) range for a PGIA gain of 0.16 or 0.2 is 0 V.
3 All ac accuracy specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4 This is the output from the internal band gap reference.
5 There is no pipeline delay. Conversion results are available immediately after a conversion is complete.
6 The differential input common-mode voltage (VCM) range changes according to the maximum input range selected and the high voltage power supplies (VDDH and
VSSH). Note that the specified operating input voltage of any input pin requires 2.5 V of headroom from the VDDH and VSSH supplies; therefore, (VSSH + 2.5 V) ≤
INx/COM ≤ (VDDH − 2.5 V).
Rev. A | Page 6 of 40
Data Sheet
ADAS3022
TIMING SPECIFICATIONS
VDDH = 15 V 5ꢀ% VSSH = −15 V 5ꢀ% ꢁVDD = DVDD = 5 V 5ꢀ% VꢂO = 1.8 V to ꢁVDD% internal reference% VREF = 4.096 V%
fS = 1 MSPS. ꢁll specifications TMꢂN to TMꢁX% unless otherwise noted.
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Time Between Conversions
Warp Mode,1 CMS = 0
tCYC
1
1000
μs
μs
Normal Mode (Default), CMS = 1
Conversion Time: CNV Rising Edge to Data Available
Warp Mode, CMS = 0
1.1
tCONV
825
925
ns
ns
ns
ns
ns
ns
ns
Normal Mode (Default), CMS = 1
Auxiliary ADC Input Channel Acquisition Time
CNV Pulse Width
1000
tACQ
tCH
600
10
CNV High to Hold Time (Aperture Delay)
CNV High to Busy Delay
Safe Data Access Time During Conversion
Quiet Conversion Time (BUSY High)
Warp Mode, CMS = 0
tAD
2
tCBD
tDDC
tQUIET
520
500
400
500
ns
ns
Normal Mode (Default), CMS = 1
Data Access During Quiet Conversion Time
Warp Mode, CMS = 0
tDDCA
200
300
ns
ns
ns
ns
ns
ns
Normal Mode (Default), CMS = 1
SCK Period
tSCK
15
5
SCK Low Time
tSCKL
tSCKH
tSDOH
tSDOD
SCK High Time
5
SCK Falling Edge to Data Valid
SCK Falling Edge to Data Valid Delay
VIO > 4.5 V
4
12
18
24
25
37
ns
ns
ns
ns
ns
VIO > 3.0 V
VIO > 2.7 V
VIO > 2.3 V
VIO > 1.8 V
CS
tEN
/RESET/PD Low to SDO
VIO > 4.5 V
15
16
18
23
28
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIO > 3.0 V
VIO > 2.7 V
VIO > 2.3 V
VIO > 1.8 V
CS
tDIS
/RESET/PD High to SDO High Impedance
DIN Valid Setup Time from SCK Rising Edge
DIN Valid Hold Time from SCK Rising Edge
tDINS
tDINH
tCCS
tRH
4
4
5
5
CS
CNV Rising to
RESET/PD High Pulse
1 Exceeding the maximum time has an effect on the accuracy of the conversion (see the Conversion Modes section).
I
500µA
OL
70% VIO
30% VIO
tDELAY
tDELAY
1.4V
TO SDO
1
1
2V OR VIO – 0.5V
2V OR VIO – 0.5V
C
L
50pF
2
2
0.8V OR 0.5V
0.8V OR 0.5V
1
500µA
I
2V IF VIO > 2.5V; VIO – 0.5V IF VIO < 2.5V.
0.8V IF VIO > 2.5V; 0.5V IF VIO < 2.5V.
OH
2
Figure 3. Voltage Levels for Timing
Figure 2. Load Circuit for Digital Interface Timing
Rev. A | Page 7 of 40
ADAS3022
Data Sheet
tACQ
EOC
tCYC
SOC
SOC
EOC
tQUIET
NOTE 2
tDDC
NOTE 1
tDAC
NOTE 1
POWER
UP
CONVERSION (n – 1)
UNDEFINED
ACQUISITION (n)
UNDEFINED
CONVERSION (n)
UNDEFINED
ACQUISITION (n + 1)
UNDEFINED
CONVERSION (n + 1)
UNDEFINED
PHASE
CNV
BUSY
tDDCA
NOTE 2
NOTE 5
tAD
NOTE 4
CS
X
1
16/32
NOTE 3
1
16
SCK
CFG
INVALID
CFG (n + 2)
CFG (n + 2)
CFG (n + 3)
CFG (n + 3)
DIN
DATA
INVALID
DATA (n – 1)
INVALID
DATA (n – 1)
INVALID
DATA (n)
INVALID
DATA (n)
INVALID
SDO
EOC
EOC
EOC
ACQUISITION
(n + 4)
CONVERSION
(n + 2)
ACQUISITION
(n + 3)
CONVERSION
(n + 3)
CONVERSION
(n + 4)
ACQUISITION
(n + 2)
PHASE
CNV
BUSY
CS
1
1
16
16
1
SCK
CFG (n + 4)
CFG (n + 4)
CFG (n + 5)
CFG (n + 5)
CFG (n + 6)
CFG (n + 6)
DIN
DATA (n + 1)
INVALID
DATA (n + 1)
INVALID
SDO
DATA (n + 2)
DATA (n + 2)
DATA (n + 3)
DATA (n + 3)
NOTES
1. DATA ACCESS CAN OCCUR DURING A CONVERSION (tDDC), AFTER A CONVERSION (tDAC), OR BOTH DURING AND AFTER A CONVERSION.
THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC).
2. DATA ACCESS CAN ALSO OCCUR UP TO tDDCA WHILE BUSY IS ACTIVE (SEE THE DIGITAL INTERFACE SECTION FOR DETAILS). ALL OF THE BUSY
TIME CAN BE USED TO ACQUIRE DATA.
3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO
READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION.
4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE.
5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME
OF THE APERTURE DELAY (tAD) SHOULD ELAPSE PRIOR TO DATA ACCESS.
Figure 4. General Timing Diagram
Rev. A | Page 8 of 40
Data Sheet
ADAS3022
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
Analog Inputs/Outputs
INx, COM to AGND
AUX+, AUX− to AGND
REFx to AGND
REFIN to AGND
REFN to AGND
VSSH − 0.3 V to VDDH + 0.3 V
−0.3 V to AVDD + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
AGND −0.3 V to +2.7 V
0.3 V
Ground Voltage Differences
AGND, RGND, DGND
Supply Voltages
ESD CAUTION
0.3 V
VDDH to AGND
VSSH to AGND
−0.3 V to +16.5 V
+0.3 V to −16.5 V
−0.3 V to +7 V
AVDD, DVDD, VIO to AGND
ACAP, DCAP, RCAP to GND
Digital Inputs/Outputs
CNV, DIN, SCK, RESET, PD, CS
to DGND
−0.3 V to +2.7 V
−0.3 V to VIO + 0.3 V
SDO, BUSY to DGND
Internal Power Dissipation
Junction Temperature
Storage Temperature Range
θJA Thermal Impedance
θJC Thermal Impedance
−0.3 V to VIO + 0.3 V
2 W
125°C
−65°C to +125°C
44.1°C/W
0.28°C/W
Rev. A | Page 9 of 40
ADAS3022
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
IN0
IN1
IN2
IN3
AUX+
IN4
IN5
IN6
IN7
COM 10
1
2
3
4
5
6
7
8
9
30 NC
29 NC
INDICATOR
28 AVDD
27 DVDD
26 ACAP
25 DCAP
24 AGND
23 AGND
22 DGND
21 DGND
ADAS3022
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT. THIS PIN IS NOT INTERNALLY CONNECTED.
2. THE EXPOSED PADDLE SHOULD BE CONNECTED TO VSSH.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1 to 4
5
6 to 9
10
Mnemonic Type1 Description
IN0 to IN3
AUX+
AI
AI
AI
AI
Input Channel 0 to Input Channel 3.
Auxiliary Input Channel Positive Input.
Input Channel 4 to Input Channel 7.
IN4 to IN7
COM
IN[7:0] Common Channel Input. The IN[7:0] input channels can be referenced to a common point. The
maximum voltage on this pin is 10.24 V for all PGIA gains except for a PGIA gain of 0.16, in which case
the maximum voltage on this pin is 12.228 V. AUX+ and AUX− are not referenced to COM.
11
12
13
CS
DI
DI
DI
Chip Select. Active low signal. Enables the digital interface for writing and reading data. Use this pin
when sharing the serial bus. For a dedicated ADAS3022 serial interface, CS can be tied to DGND or CNV
to simplify the interface.
Data Input. Serial data input used for writing the 16-bit configuration word (CFG) that is latched on SCK
rising edges. CFG is an internal register that is updated on the rising edge of the end of a conversion, which is
the falling edge of BUSY. The configuration register can be written to during and after a conversion.
DIN
RESET
Asynchronous Reset. A low-to-high transition resets the ADAS3022. The current conversion, if active, is
aborted and CFG is reset to the default state.
14, 29, 30
15
NC
PD
NC
DI
No Connect. This pin is not connected internally.
Power-Down. A low-to-high transition powers down the ADAS3022, minimizing the bias current. Note
that this pin must be held high until the user is ready to power on the device; after powering on the
device, the user must wait 100 ms until the reference is enabled and then wait for the completion of
two dummy conversions before the device is ready to convert. See the Power-Down Mode section for
more information.
16
17
SCK
VIO
DI
P
Serial Clock Input. The DIN and SDO data sent to and from the ADAS3022 are synchronized with SCK.
Digital Interface Supply. Nominally, this supply should be at the same voltage as the supply of the host
interface: 1.8 V, 2.5 V, 3.3 V, or 5 V.
18
19
SDO
DO
DO
Serial Data Output. The conversion result is output on this pin and is synchronized to SCK falling edges.
The conversion result is output in twos complement format.
Busy Output. An active high signal on this pin indicates that a conversion is in process. Reading or
writing data during the quiet conversion phase (tQUIET) may cause incorrect bit decisions.
BUSY
20
CNV
DI
P
P
Convert Input. A conversion is initiated on the rising edge of this pin.
Digital Ground. Connect these pins to the system digital ground plane.
Analog Ground. Connect these pins to the system analog ground plane.
Internal 2.5 V Digital Regulator Output. Decouple this internally regulated output using a 10 μF
capacitor and a 0.1 μF local capacitor.
21, 22
23, 24
25
DGND
AGND
DCAP
P
26
ACAP
P
Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal ADC core and all
of the supporting analog circuits with the exception of the internal reference. Decouple this internally
regulated output using a 10 μF capacitor and a 0.1 μF local capacitor.
Rev. A | Page 10 of 40
Data Sheet
ADAS3022
Pin No.
27
28
Mnemonic Type1 Description
DVDD
AVDD
RCAP
P
P
P
Digital 5 V Supply. Decouple this supply using a 10 μF capacitor and a 0.1 μF local capacitor.
Analog 5 V Supply. Decouple this supply using a 10 μF capacitor and a 0.1 μF local capacitor.
Internal 2.5 V Analog Regulator Output. This regulator supplies power to the internal reference.
Decouple this pin using a 1 μF capacitor connected to RCAP and a 0.1 μF local capacitor.
31
32
REFIN
AI/O
Internal 2.5 V Band Gap Reference Output, Reference Buffer Input, or Reference Power-Down Input. See
the Voltage Reference Input/Output section for more information.
33, 34
REF1, REF2 AI/O
Reference Input/Output. Regardless of the reference method, these pins need individual decoupling
using external 10 μF ceramic capacitors connected as close to REF1, REF2, and REFN as possible. See
the Voltage Reference Output/Input section for more information. REF1 and REF2 must be tied
together externally.
35
36, 37
RGND
REFN
P
P
Reference Supply Ground. Connect this pin to the system analog ground plane.
Reference Input/Output Ground. Connect the 10 μF capacitors on REF1 and REF2 to these pins, and
connect these pins to the system analog ground plane.
38
39
40
VSSH
P
High Voltage Analog Negative Supply. Nominally, the supply of this pin should be −15 V. Decouple this
pin using a 10 μF capacitor and a 0.1 μF local capacitor.
High Voltage Analog Positive Supply. Nominally, the supply of this pin should be +15 V. Decouple this
pin using a 10 μF capacitor and a 0.1 μF local capacitor.
Auxiliary Input Channel Negative Input.
Exposed Paddle. The exposed paddle should be connected to VSSH.
VDDH
P
AUX−
EPAD
AI
1AI = analog input, AI/O = analog input/output, DI = digital input, DO = digital output, and P = power.
Rev. A | Page 11 of 40
ADAS3022
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VDDH = 15 V, VSSH = −15 V, AVDD = DVDD = 5 V, VIO = 1.8 V to AVDD, unless otherwise noted.
2.0
1.00
0.75
0.50
0.25
0
GAIN = 0.16, 0.2, 0.4, 0.8, 1.6
INL MAX = 0.649
INL MIN = –0.592
FOR ALL GAINS
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.25
–0.50
–0.75
–1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE
Figure 6. Integral Nonlinearity vs. Code,
PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
Figure 9. Differential Nonlinearity vs. Code for All PGIA Gains
400,000
2.0
1.5
GAIN = 3.2
INL MAX = 1.026
INL MIN = –0.948
GAIN = 0.16, 0.2, 0.4, 0.8, 1.6
350,000
300,000
250,000
200,000
150,000
100,000
50,000
0
300,200
1.0
0.5
0
152,600
–0.5
–1.0
–1.5
–2.0
52,300
6,400
600
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE
CODE IN HEX
Figure 7. Integral Nonlinearity vs. Code, PGIA Gain = 3.2
Figure 10. Histogram of a DC Input at Code Center,
PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
2.0
1.5
400,000
350,000
300,000
250,000
200,000
150,000
100,000
50,000
0
GAIN = 6.4
INL MAX = 0.558
INL MIN = –1.319
GAIN = 3.2
1.0
0.5
213,200
0
–0.5
–1.0
–1.5
–2.0
129,000
118,400
25,500
1,600
22,700
1,400
0
8192 16384 24576 32768 40960 49152 57344 65536
CODE
CODE IN HEX
Figure 8. Integral Nonlinearity vs. Code, PGIA Gain = 6.4
Figure 11. Histogram of a DC Input at Code Center, PGIA Gain = 3.2
Rev. A | Page 12 of 40
Data Sheet
ADAS3022
400,000
100
90
80
70
60
50
40
30
20
10
0
EXTERNAL REFERENCE
GAIN = 6.4
S = 1000kSPS
GAIN = 6.4
350,000
300,000
250,000
200,000
150,000
100,000
50,000
0
f
157,300
151,900
82,000
75,100
21,700
18,400
2,400
300
200
100
0
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
OFFSET DRIFT (ppm/°C)
CODE IN HEX
Figure 15. Offset Drift, PGIA Gain = 6.4
Figure 12. Histogram of a DC Input at Code Center, PGIA Gain = 6.4
100
120
100
80
60
40
20
0
112
EXTERNAL REFERENCE
fS = 1000kSPS
EXTERNAL 2.5V REFERENCE
INTERNAL BUFFER
GAIN = 0.16, 0.2, 0.4, 0.8, 1.6
S = 1000kSPS
90
80
70
60
50
40
30
20
10
0
f
72
23
2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OFFSET DRIFT (ppm/°C)
0
1
2
3
4
5
6
7
8
9
10
REFERENCE BUFFER DRIFT (ppm/°C)
Figure 13. Offset Drift, PGIA Gain = 0.16, 0.2, 0.4, 0.8, and 1.6
Figure 16. Reference Buffer Drift, External Reference
100
120
100
80
60
40
20
0
EXTERNAL REFERENCE
GAIN = 3.2
fS = 1000kSPS
INTERNAL 2.5V REFERENCE
INTERNAL BUFFER
90
80
70
60
50
40
30
20
10
0
fS = 1000kSPS
46
38
35
30
15 15
11
10
6
2
1
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
OFFSET DRIFT (ppm/°C)
REFERENCE BUFFER DRIFT (ppm/°C)
Figure 14. Offset Drift, PGIA Gain = 3.2
Figure 17. Reference Buffer Drift, Internal Reference
Rev. A | Page 13 of 40
ADAS3022
Data Sheet
0
0
–20
GAIN = 0.16
fS = 1000kSPS
GAIN = 0.8
fS = 1000kSPS
–20
fIN = 10.1kHz
fIN = 10.1kHz
–40
–40
SNR = 91.7dB
SINAD = 89.2dB
THD = –92.5dB
SFDR = 92.5dB
SNR = 90.7dB
SINAD = 90.6dB
THD = –107dB
SFDR = 106dB
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
–180
–180
0
100
200
300
400
500
0
100
200
300
400
500
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 18. 10 kHz FFT, PGIA Gain = 0.16
Figure 21. 10 kHz FFT, PGIA Gain = 0.8
0
–20
0
–20
GAIN = 0.2
fS = 1000kSPS
GAIN = 1.6
fS = 1000kSPS
fIN = 10.1kHz
fIN = 10.1kHz
–40
–40
SNR = 91.4dB
SINAD = 89.9dB
THD = –94.7dB
SFDR = 94.8dB
SNR = 89.8dB
SINAD = 89.7dB
THD = –106dB
SFDR = 107dB
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
–180
–180
0
100
200
300
400
500
0
100
200
300
400
500
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 19. 10 kHz FFT, PGIA Gain = 0.2
Figure 22. 10 kHz FFT, PGIA Gain = 1.6
0
–20
0
–20
GAIN = 0.4
fS = 1000kSPS
GAIN = 3.2
fS = 1000kSPS
fIN = 10.1kHz
fIN = 10.1kHz
–40
–40
SNR = 91.2dB
SINAD = 91.0dB
THD = –103dB
SFDR = 104dB
SNR = 87.6dB
SINAD = 87.5dB
THD = –105dB
SFDR = 106dB
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
–180
–180
0
100
200
300
400
500
0
100
200
300
400
500
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 20. 10 kHz FFT, PGIA Gain = 0.4
Figure 23. 10 kHz FFT, PGIA Gain = 3.2
Rev. A | Page 14 of 40
Data Sheet
ADAS3022
0
–55
–60
GAIN = 0.4, –0.5dBFS
GAIN = 0.8, –0.5dBFS
GAIN = 1.6, –0.5dBFS
GAIN = 3.2, –0.5dBFS
GAIN = 0.4, –10dBFS
GAIN = 0.8, –10dBFS
GAIN = 1.6, –10dBFS
GAIN = 3.2, –10dBFS
GAIN = 6.4
fS = 1000kSPS
fIN = 10.1kHz
SNR = 85.7dB
SINAD = 85.6dB
THD = –101dB
SFDR = 103dB
–20
–65
–70
–40
–75
–60
–80
–85
–80
–90
–100
–120
–140
–160
–95
–100
–105
–110
–115
–120
–125
–180
0
1
10
100
1000
100
200
300
400
500
1000
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 24. 10 kHz FFT, PGIA Gain = 6.4
Figure 27. THD vs. Frequency
100
95
90
85
80
75
70
–60
–70
INTERNAL REFERENCE
CHANNEL 4 TO COM, SEQUENCER DISABLED
VIN = –0.5dBFS ON CHANNELS 0 TO 3, 5 TO 7
fS = 1000kSPS
–80
–90
–100
–110
–120
–130
–140
GAIN = 0.4, –0.5dBFS
GAIN = 0.8, –0.5dBFS
GAIN = 1.6, –0.5dBFS
GAIN = 3.2, –0.5dBFS
GAIN = 0.4, –10dBFS
GAIN = 0.8, –10dBFS
GAIN = 1.6, –10dBFS
GAIN = 3.2, –10dBFS
1
10
100
0
20
40
60
80
100 120 140 160 180 200
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 25. SNR vs. Frequency
Figure 28. Crosstalk vs. Frequency
100
95
90
85
80
75
70
65
60
55
50
130
120
110
100
90
GAIN = 0.16
GAIN = 0.20
GAIN = 0.40
GAIN = 0.80
GAIN = 1.60
GAIN = 3.20
GAIN = 6.40
GAIN = 0.4, –0.5dBFS
GAIN = 0.8, –0.5dBFS
GAIN = 1.6, –0.5dBFS
GAIN = 3.2, –0.5dBFS
GAIN = 0.4, –10dBFS
GAIN = 0.8, –10dBFS
GAIN = 1.6, –10dBFS
GAIN = 3.2, –10dBFS
80
COMMON-MODE AMPLITUDE = 20.48V p-p
INTERNAL REFERENCE
fS = 1000kSPS
70
60
1
10
100
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 26. SINAD vs. Frequency
Figure 29. CMRR vs. Frequency
Rev. A | Page 15 of 40
ADAS3022
Data Sheet
20
18
16
14
12
10
–50
PSRR VDDH
PSRR VSSH
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
AVDD, GAIN = 0.2
AVDD, GAIN = 3.2
AVDD, GAIN = 1.6
AVDD, GAIN = 6.4
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
0.01
0.1
1
10
100
10
100
THROUGHPUT (kSPS)
1000
FREQUENCY (kHz)
Figure 30. PSRR vs. Frequency
Figure 33. AVDD Current vs. Throughput, Internal Reference
15
14
13
12
11
10
9
19
18
17
16
15
14
13
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
10
100
THROUGHPUT (kSPS)
1000
4.7
4.8
4.9
5.0
AVDD SUPPLY (V)
5.1
5.2
5.3
Figure 34. AVDD Current vs. Throughput, External Reference
Figure 31. AVDD Current vs. Supply, Internal Reference
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
15
14
13
12
11
10
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
10
100
THROUGHPUT (kSPS)
1000
4.7
4.8
4.9
5.0
AVDD SUPPLY (V)
5.1
5.2
5.3
Figure 35. DVDD Current vs. Throughput
Figure 32. AVDD Current vs. Supply, External Reference
Rev. A | Page 16 of 40
Data Sheet
ADAS3022
0
–2
18
fS = 1000kSPS
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
15
12
9
–4
–6
–8
–10
–12
–14
–16
–18
–20
6
3
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
0
10
100
THROUGHPUT (kSPS)
1000
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
Figure 36. VDDH Current vs. Throughput
Figure 39. VSSH Current vs. Temperature
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
0
–3
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
fS = 1000kSPS
–6
–9
–12
–15
–18
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
10
100
THROUGHPUT (kSPS)
1000
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
Figure 37. VSSH Current vs. Throughput
Figure 40. AVDD Current vs. Temperature
20
18
16
14
12
10
8
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
VIO = 3.3V
fS = 1000kSPS
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
fS = 1000kSPS
6
4
2
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 38. VDDH Current vs. Temperature
Figure 41. DVDD Current vs. Temperature
Rev. A | Page 17 of 40
ADAS3022
Data Sheet
5
4
4.00
GAIN = 0.2
GAIN = 1.6
GAIN = 0.4
GAIN = 3.2
GAIN = 0.8
GAIN = 6.4
GAIN = 0.16
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
fS = 1000kSPS
fS = 1000kSPS
EXTERNAL REFERENCE
3.75
3.50
3.25
3.00
2.75
2.50
2.25
2.00
3
2
1
0
–1
–2
–3
–4
–5
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 45. Gain Error vs. Temperature
Figure 42. VIO Current vs. Temperature
12
8
100
98
96
94
92
90
88
86
84
82
80
fS = 1000kSPS
GAIN = 0.16
GAIN = 0.16
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
fS = 1000kSPS
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
EXTERNAL REFERENCE
4
0
–4
–8
–12
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 46. Offset Error vs. Temperature
Figure 43. SNR vs. Temperature
5
4
–80
–85
GAIN = 0.16
fS = 1000kSPS
EXTERNAL REFERENCE
GAIN = 0.2
GAIN = 0.4
GAIN = 0.8
GAIN = 1.6
GAIN = 3.2
GAIN = 6.4
3
–90
2
GAIN ERROR
–95
1
0
–100
–105
–110
–115
–120
OFFSET ERROR
–1
–2
–3
–4
–5
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 47. Offset and Gain Errors of the AUX ADC Channel Pair vs. Temperature
Figure 44. THD vs. Temperature
Rev. A | Page 18 of 40
Data Sheet
ADAS3022
5600
5400
5200
5000
4800
4600
4400
4200
4000
3800
3600
3400
32
28
24
20
16
12
8
25
20
15
10
5
T
= 25°C
A
INTERNAL REFERENCE
4
0
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
0
100 200 300 400 500 600 700 800 900 1000
THROUGHPUT (kSPS)
TEMPERATURE (°C)
Figure 48. Temperature Sensor Output Code vs. Temperature
Figure 50. Temperature Sensor Output Error vs. Throughput
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–0.5dBFS
–3.5
GAIN = 0.2
GAIN = 0.8
GAIN = 3.2
GAIN = 0.4
GAIN = 1.6
GAIN = 6.4
–4.0
–4.5
10
100
1k
10k
FREQUENCY (Hz)
Figure 49. Large Signal Frequency Response vs. Gain
Rev. A | Page 19 of 40
ADAS3022
Data Sheet
TERMINOLOGY
Operating Input Voltage Range
Differential Nonlinearity (DNL) Error
Operating input voltage range is the maximum input voltage
range, including the common-mode voltage, allowed on the
input channels IN[7:0] and COM.
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Differential Input Voltage Range
Offset Error
Differential input voltage range is the maximum differential
full-scale input range. The value changes according to the
programmable gain setting.
Offset error is the deviation of the actual MSB transition from
the ideal MSB transition point. The ideal MSB transition occurs
at an input level ½ LSB above analog ground.
Channel Off Leakage
Channel off leakage is the leakage current with the channel off.
Gain Error
The last transition (from 111 … 10 to 111 … 11) for an analog
voltage should occur 1½ LSB below the nominal full scale. The
gain error is the deviation expressed in LSB (or as a percentage
of the full-scale range) of the actual level of the last transition
from the ideal level after the offset error is removed. Closely
related to this parameter is the full-scale error (also expressed in
LSB or as a percentage of the full-scale range), which includes
the effects of the offset error.
Channel On Leakage
Channel on leakage is the leakage current with the channel on.
Charge Injection
Charge injection is a measure of the glitch impulse that is
transferred through the analog input pin into the source when
the sample is taken and/or the multiplexer is switched.
Total Unadjusted Error (TUE)
Common-Mode Rejection Ratio (CMRR)
TUE is the deviation of each code from an ideal transfer function
and is a combination of all error contributors, including non-
linearity, offset error, and gain error. TUE for the ADAS3022 is
expressed as the maximum deviation in LSB or as a percentage
of the full-scale range.
CMRR is the ratio of the amplitude of a signal referred to input in
the converted result to the amplitude of the modulation common
to a pair of inputs and is expressed in decibels. CMRR is a measure
of the ability of the ADAS3022 to reject signals, such as power
line noise, that are common to the inputs. This specification is
for a 2 kHz sine wave of 20.48 V p-p applied to both channels of
an input pair.
Aperture Delay
Aperture delay is a measure of the acquisition performance. It is
the time between the rising edge of the CNV input and the point
at which the input signal is held for a conversion.
Transient Response
Transient response is a measure of the time required for the
ADAS3022 to properly acquire the input after a full-scale step
function is applied to the system.
Dynamic Range
Dynamic range is the ratio of the rms value of the full-scale signal
to the total rms noise measured with the inputs shorted together.
The value for the dynamic range is expressed in decibels.
Least Significant Bit (LSB)
LSB is the smallest increment that can be represented by a
converter. For a fully differential input ADC with N bits of
resolution, the LSB expressed in volts is
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
2VREF
LSB (V) =
2N
Integral Nonlinearity (INL) Error
Signal-to-Noise-and-Distortion Ratio (SINAD)
INL refers to the deviation of each individual code from a line
drawn from negative full scale to positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line (see Figure 53).
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Rev. A | Page 20 of 40
Data Sheet
ADAS3022
Reference Voltage Temperature Coefficient
Total Harmonic Distortion (THD)
Reference voltage temperature coefficient is derived from the
typical shift of output voltage at 25°C on a sample of parts at the
maximum and minimum reference output voltage (VREF) measured
at TMIN, T (25°C), and TMAX. The value is expressed in ppm/°C as
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, expressed in decibels, between the rms
amplitude of the input signal and the peak spurious signal.
V
REF (Max)–VREF (Min)
TCVREF (ppm/°C) =
×106
V
REF (25°C) × (TMAX –TMIN )
where:
REF (Max) is the maximum reference output voltage at TMIN
T (25°C), or TMAX
Channel-to-Channel Crosstalk
V
,
Channel-to-channel crosstalk is a measure of the level of crosstalk
between any channel and all other channels. The crosstalk is
measured by applying a dc input to the channel under test and
applying a full-scale, 10 kHz sine wave signal to all other channels.
The crosstalk is the amount of signal that leaks into the test channel
and is expressed in decibels.
.
V
REF (Min) is the minimum reference output voltage at TMIN,
T (25°C), or TMAX
.
V
REF (25°C) is the reference output voltage at 25°C.
T
MAX = +85°C.
T
MIN = −40°C.
Rev. A | Page 21 of 40
ADAS3022
Data Sheet
THEORY OF OPERATION
the ADAS3022 solution include reduced footprint and less
complex design requirements, which also results in faster time
to market and lower cost.
OVERVIEW
The ADAS3022 is the first system on a single chip that integrates
the typical components used in a data acquisition system in one
easy to use, programmable device. This single-chip solution is
capable of converting up to 1,000,000 samples per second
(1 MSPS) of aggregate throughput. The ADAS3022 features
ADAS3022 OPERATION
As shown in Figure 51, the ADAS3022 internal analog circuitry
consists of a high impedance, low leakage multiplexer and a
programmable gain instrumentation amplifier that can accept
full-scale differential voltages of 0.64 V, 1.28 V, 2.56 V, 5.12 V,
10.24 V, 20.48 V, and 24.576 V. The ADAS3022 can be con-
figured to use up to eight single-ended input channels or four
pairs of channels, that is, 125 kSPS per channel for eight channels
or effectively 250 kSPS for four channel pairs. The device can also
provide a relative temperature measurement using the internal
temperature sensor. In addition, the differential auxiliary channel
pair (AUX+ and AUX−) is provided with the specified input
•
•
•
•
High impedance inputs
High common-mode rejection
8-channel, low crosstalk multiplexer (mux)
Programmable gain instrumentation amplifier (PGIA) with
seven selectable differential input ranges from 0.64 V to
24.576 V
•
•
•
•
16-bit PulSAR® ADC with no missing codes
Internal, precision, low drift 4.096 V reference and buffer
Temperature sensor
range of
V
REF . This option bypasses the mux and PGIA stages,
Channel sequencer
allowing direct access to the SAR ADC core.
Reducing the number of channels or pairs increases the throughput
rate by an amount proportional to the reciprocal of the number
of sampled channels multiplied by the aggregate throughput:
The ADAS3022 uses an Analog Devices patented high voltage
iCMOS® process, allowing up to a 24.576 V differential input
voltage range when using 15 V supplies, which makes the
device suitable for industrial applications.
1/(Number of Channels or Pairs) × 1000 kSPS
The device is housed in a small, 6 mm × 6 mm, 40-lead LFCSP
and can operate over the industrial temperature range (−40°C
to +85°C). A typical discrete multichannel data acquisition
system containing similar circuitry would require at least three
times more space on the circuit board. Therefore, advantages of
For a single channel or channel pair, the maximum throughput
rate is 1 MSPS. For all eight channels, the AUX channel pair, and
the temperature sensor, the throughput rate of a given channel
decreases to 100 kSPS.
AVDD
DVDD
VIO
RESET
PD
VDDH
DIFF TO
COM
DIFF
PAIR
ADAS3022
CNV
LOGIC/
INTERFACE
IN0/IN1
BUSY
IN0
IN1
CS
IN2
IN2/IN3
IN4/IN5
IN6/IN7
IN3
SCK
DIN
SDO
PulSAR
ADC
PGIA
MUX
IN4
IN5
IN6
IN7
TEMP
SENSOR
COM
AUX+
REFIN
BUF
REF
AUX–
VSSH
AGND
DGND
REFx
Figure 51. ADAS3022 Simplified Block Diagram
Rev. A | Page 22 of 40
Data Sheet
ADAS3022
The ADAS3022 offers true high impedance inputs in a differential
structure and rejects common-mode signals present on the inputs.
The ADAS3022 architecture does not require any of the additional
input buffers (op amps) that are usually required to condition
the input signal and drive the ADC inputs when using switched
capacitor-based successive approximation register (SAR) analog-
to-digital converters (ADCs).
A rising edge on CNV initiates a conversion and changes the
state of the ADAS3022 from track to hold. In this state, the
ADAS3022 performs analog signal conditioning. When the
signal conditioning is complete, the ADAS3022 returns to the
track state while at the same time quantizing the sample. This
two-part process satisfies the necessary settling time requirement
while achieving a fast throughput rate of up to 1 MSPS with 16-bit
accuracy.
The inputs are multiplexed to the PGIA using a high voltage
multiplexer with low charge injection and very low leakage. The
inputs can be configured for a single-ended to common point
(COM) measurement or can be paired for up to four fully
differential inputs with independent gain settings. This requires
using the advanced sequencer or programming sequential
configuration words with the desired gain for each pair. The
digitally controlled, programmable gain is used to select one of
seven voltage input ranges (see Table 7).
tCYC
tACQ
CNV
PHASE
HOLD
CONVERT/TRACK
Figure 52. ADAS3022 System Timing
Regardless of the type of signal (differential or single-ended,
antiphase or nonantiphase, symmetric or asymmetric), the
ADAS3022 converts all signals present on the enabled inputs in
a differential fashion, like an industry-standard difference or
instrumentation amplifier.
When the sequencer option is used, an on-chip sequencer scans
channels in order and offers independent input voltage ranges
for each channel (see the Channel Sequencer Details section).
In this mode, a single configuration word initiates the sequencer
to scan repeatedly without the need to rewrite the register. After
the last channel is scanned, the ADAS3022 automatically begins
at IN0 again and repeats the sequence until a word is written to
stop the sequencer or the asynchronous RESET is asserted.
Additionally, if changes are made to certain configuration bits,
the sequencer is reset to IN0.
The conversion result is available after the conversion is complete
and can be read back at any time before the end of the next
conversion. Reading back data should be avoided during the
quiet period, as indicated by BUSY being active high. Because
the ADAS3022 has an on-board conversion clock, the serial
clock (SCK) is not required for the conversion process. It is only
required to present results to the user.
The PulSAR-based ADC core is capable of converting 1 MSPS
from a single rising edge on the convert start input (CNV). The
conversion results are available in twos complement format and
are presented on the serial data output (SDO). The digital interface
TRANSFER FUNCTION
The ideal transfer characteristics of the ADAS3022 are shown in
Figure 53. With the inputs configured for differential input
ranges, the data output is twos complement, as described in
Table 6.
CS
uses a dedicated chip select pin ( ) to transfer data to and from
the ADAS3022 and also provides a BUSY indicator, asynchronous
RESET, and power-down (PD) inputs.
The ADAS3022 on-chip reference uses an internal temperature
compensated 2.5 V output band gap reference and a precision
buffer amplifier to provide the 4.096 V high precision system
reference.
TWOS
COMPLEMENT
011 ... 111
011 ... 110
011 ... 101
All of the bits in Table 11 are configured through a serial (SPI-
compatible), 16-bit configuration register (CFG). Configuration
and conversion results can be read after or during a conversion,
or the readback option can be disabled.
100 ... 010
100 ... 001
100 ... 000
The ADAS3022 requires a minimum of three power supplies: +5 V,
+15 V, and −15 V. On-chip low dropout regulators provide the
necessary 2.5 V system voltages and must be decoupled externally
via dedicated pins (ACAP, DCAP, and RCAP). The ADAS3022
can be interfaced to any 1.8 V to 5 V digital logic family using
the dedicated VIO logic level voltage supply (see Table 9).
–FSR
–FSR + 1LSB
+FSR – 1LSB
–FSR + 0.5LSB
+FSR – 1.5LSB
ANALOG INPUT
Figure 53. ADC Ideal Transfer Function
Rev. A | Page 23 of 40
ADAS3022
Data Sheet
TYPICAL APPLICATION CONNECTION DIAGRAM
Table 6. Output Codes and Ideal Input Voltages
As shown in Figure 54, the ADP1613 is used in an inexpensive
SEPIC-Ćuk topology, which is an ideal candidate for providing
the ADAS3022 with the necessary high voltage 15 V robust
supplies (at 20 mA) and low output ripple (3 mV maximum)
from an external 5 V supply. The ADP1613 satisfies the
specification requirements of the ADAS3022 with minimal
external components while achieving greater than 86% of
efficiency. Refer to the CN-0201 circuit note for complete
information about this test setup.
Differential Analog
Inputs, VREF = 4.096 V
Digital Output Code
(Twos Complement, Hex)
Description
FSR − 1 LSB
(32,767 × VREF)/
(32,768 × PGIA gain)
0x7FFF
Midscale + 1 LSB
VREF/(32,768 × PGIA
0x0001
gain)
Midscale
Midscale − 1 LSB
0
0x0000
0xFFFF
−(VREF/(32,768 × PGIA
gain))
−(32,767 × VREF)/
−FSR + 1 LSB
−FSR
0x8001
0x8000
(32,768 × PGIA gain)
−VREF × PGIA gain
D2
C
4.7µF
3
OUT
+
L2
47µH
C2
+
1µF
1.78Ω
FILT
L1
47µH
R
+5V
D1
V
= +5V
IN
L3
1µF
+15V
+
C
1µF
IN
C1
1µF
+
+
R
0
C
1
C
2
B
OUT
OUT
1Ω
1µF
2.2µF
VDDH
AVDD DVDD
VIO
RESET PD
R
EN
ENABLE
DIFF DIFF
PAIR COM
ADAS3022
CNV
50kΩ
R 1
S
0Ω
BUSY
LOGIC/
IN0
IN0/IN1
IN1
INTERFACE
ADP1613
CS
IN2
IN2/IN3
IN3
COMP
SS
SCK
DIN
SDO
+
1
12nF
+
C
C
C
10pF
2
C
PulSAR
ADC
PGIA
IN4
IN4/IN5
IN5
MUX
FB
FREQ
VIN
R
1
C
IN6
IN6/IN7
IN7
EN
100kΩ
REFIN
BUF
REF
TEMP
SENSOR
COM
GND
SW
AUX+
+
+
C 5
V
R 2
S
C
SS
AUX–
1µF
DNI
1µF
Z1
+5V
ADR434
VSSH
–15V
AGND DGND
REFx
DNI
+5V
+
–
4.096V
RF2
4.22kΩ
RF1B
47.5kΩ
AD8031
Figure 54. Complete 5 V, Single-Supply, 8-Channel Multiplexed Data Acquisition System with PGIA
Rev. A | Page 24 of 40
Data Sheet
ADAS3022
Note that because the ADAS3022 can use any input type, such
as bipolar differential (antiphase or nonantiphase), bipolar single
ended, or pseudo bipolar, setting the PGIA is important to
make full use of the allowable input span.
ANALOG INPUTS
Input Structure
The ADAS3022 uses a differential input structure between
IN[7:0] and COM or between IN[7:0]+ and IN[7:0]− of a
channel pair. The COM input is sampled identically such that
the same voltages can be present on inputs IN[7:0]. Therefore,
the selection of paired channels or all channels referenced to
one common point is available. Because all inputs are sampled
differentially, the ADAS3022 offers true high common-mode
rejection, whereas a discrete system would require the use of
additional instrumentation or a difference amplifier.
Table 7 describes each differential input range and the
corresponding LSB size, PGIA bits settings, and PGIA gain.
Table 7. Differential Input Ranges, LSB Size, and PGIA
Settings
Differential Input Ranges,
INx+ − INx− (V)
PGIA Gain
LSB (μV) PGIA Bits (V/V)
24.5ꢀ7
20.4ꢁ
80.24
5.82
2.57
8.2ꢁ
ꢀꢁ8.25
725
000
888
008
080
088
800
808
0.87
0.2
0.4
0.ꢁ
8.7
ꢂ.2
7.4
Figure 55 shows an equivalent circuit of the analog inputs. The
internal diodes provide ESD protection for the analog inputs
(IN[7:0] and COM) from the high voltage supplies (VDDH and
VSSH). Care must be taken to ensure that the analog input
signal does not exceed the supply rails by more than 0.3 V
because this can cause the diodes to become forward-biased and
to start conducting current. Note that if the auxiliary input pair
(AUX±) is used, the diodes provide ESD protection from only the
lower voltage AVDD (5 V) supply and the system analog ground
because these inputs are connected directly to the internal SAR
ADC circuitry.
ꢂ82.5
857.ꢂ
ꢀꢁ.8ꢂ
ꢂ3.07
83.5ꢂ
0.74
Common-Mode Operating Range
The differential input common-mode voltage (VCM) range
changes according to the maximum input range selected and
the high voltage power supplies (VDDH and VSSH). Note that
the specified operating input voltage of any input pin (see the
Specifications section) requires 2.5 V of headroom from the
VDDH and VSSH supplies; therefore,
VDDH
IN[7:0]
OR COM
MUX
PGIA
C
PIN
(VSSH + 2.5 V) ≤ INx/COM ≤ (VDDH − 2.5 V)
VSSH
This section provides some examples of setting the PGIA for
various input signals. Note that the ADAS3022 always calculates
the difference between the IN+ and IN− signals.
AVDD
AUX+
OR AUX–
C
PIN
Fully Differential, Antiphase Signals with a
Zero Common Mode
AGND
For a pair of 20.4ꢁ V p-p differential antiphase signals with a
zero common mode, the maximum differential voltage across
the inputs is 20.4ꢁ V, and the PGIA gain configuration should
be set to ±±±.
Figure 55. Equivalent Analog Input Circuit
Voltages beyond the absolute maximum ratings may cause
permanent damage to the ADAS3022 (see Table 4).
INx+
INx+
+10.24V
Programmable Gain
20.48V p-p
The ADAS3022 incorporates a programmable gain instru-
mentation amplifier with seven selectable ranges (±0.ꢀ4 V,
±±.2ꢁ V, ±2.5ꢀ V, ±5.±2 V, ±±0.24 V, ±20.4ꢁ V, and ±24.57ꢀ V),
enabling the use of almost any direct sensor interface. The PGIA
settings are specified in terms of the maximum absolute differential
input voltage across a pair of inputs (for example, INx+ to INx−
or INx+ to COM). The power-on and default conditions are
preset to the ±20.4ꢁ V (PGIA = ±±±) input range.
ADAS3022
–10.24V
20.48V p-p
INx–
INx–
Figure 56. Differential, Antiphase Inputs with a Zero Common Mode
Rev. A | Page 25 of 40
ADAS3022
Data Sheet
for single-ended signals, if possible, is to remove as much dc
offset as possible between INx+ and INx− to produce a bipolar
input voltage that is symmetric around the ground sense. In this
example, the differential voltage across the inputs is never greater
than 0.64 V, and the PGIA gain configuration is set to 101 for
the 1.28 V p-p range. This scenario uses all of the codes
available for the transfer function, making full use of the
allowable differential input range.
Fully Differential, Antiphase Signals with a
Nonzero Common Mode
For a pair of 5.12 V p-p differential antiphase signals with a
nonzero common mode (dc common-mode voltage of 7 V in
this example), the maximum differential voltage across the
inputs is ±5.12 V (dc common-mode voltage is rejected), and
the PGIA gain configuration should be set to 010.
INx+
INx+
INx+
5.12V p-p
+0.64V
INx–
INx+
ADAS3022
V
= 7V
0V
CM
1.28V p-p
ADAS3022
V
INx–
CM
5.12V p-p
–0.64V
INx–
INx–
Figure 57. Differential, Antiphase Inputs with a Nonzero Common Mode
Figure 60. Better Single-Ended Configuration—Uses All Codes
Differential, Nonantiphase Signals with a
Zero Common Mode
Notice that the voltages in this example are not integer values
due to the 4.096 V reference and the PGIA scaling ratios.
For a pair of 10.24 V p-p differential nonantiphase signals with
a zero common mode, the maximum differential voltage across
the inputs is ±10.24 V, and the PGIA gain configuration should
be set to 001.
Multiplexer
The ADAS3022 uses a high voltage, high performance, low
charge injection multiplexer and a total of nine inputs (IN[7:0]
and COM). Using the INx and COM bits of the configuration
register, the ADAS3022 is configurable for differential inputs
between any of the eight input channels (IN[7:0]) and COM or
for up to four input pairs. Figure 61 shows various methods for
configuring the analog inputs for the type of channel (single or
paired). Refer to the Configuration Register section for more
information.
INx+
INx+
10.24V p-p
10.24V p-p
+5.12V
0V
ADAS3022
–5.12V
INx–
INx–
Figure 58. Differential, Nonantiphase Inputs with a Zero Common Mode
Single-Ended Signals with a Nonzero DC Offset
(Asymmetrical)
The analog inputs can be configured as follows:
When a 12 V p-p signal with a 6 V dc level-shift is connected to
one input (INx+) and the dc ground sense of the signal is
connected to INx− or COM, the PGIA gain configuration is set
to 000 for the 24.576 V range because the maximum differential
voltage across the inputs is 12 V p-p and only half the codes
available for the transfer function are used.
•
•
•
Figure 61A: IN[7:0] referenced to a system ground.
Figure 61B: IN[7:0] with a common reference point.
Figure 61C: IN[7:0] differential pairs. For pairs, COM = 0.
The positive channel is configured with INx. If INx is even,
then IN0, IN2, IN4, and IN6 are used. If INx is odd, then
IN1, IN3, IN5, and IN7 are used, as indicated by the channels
with parentheses in Figure 61C. For example, for the IN0/IN1
pair with the positive channel on IN0, INx = 0002. For the
IN4/IN5 pair with the positive channel on IN5, INx = 1012.
Note that when the channel sequencer is used, as detailed in
the Channel Sequencer Details section, the positive channels
are always IN0, IN2, IN4, and IN6.
INx+
INx+
+12V
12V p-p
V
OFF
0V
ADAS3022
V
OFF
INx–
INx–
Figure 59. Typical Single-Ended Unipolar Input—Uses Only Half the Codes
•
Figure 61D: inputs configured in a combination of any of
the preceding configurations (showing that the ADAS3022
can be configured dynamically).
Single-Ended Signals with a 0 V DC Offset (Symmetrical)
Compared with the example in the Single-Ended Signals with a
Nonzero DC Offset (Asymmetrical) section, a better solution
Rev. A | Page 26 of 40
Data Sheet
ADAS3022
Driver Amplifier Choice
IN0+
IN1+
IN2+
IN3+
IN4+
IN5+
IN6+
IN7+
IN0+
IN1+
IN2+
IN3+
IN4+
IN5+
IN6+
IN7+
COM–
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
For systems that cannot drive AUX directly, a suitable op amp
buffer should be used to preserve the ADAS3022 performance.
The driver amplifier must meet the following requirements:
•
The noise generated by the driver amplifier must be kept as
low as possible to preserve the SNR and the transition noise
performance of the ADAS3022. The noise from the
amplifier is filtered by the ADAS3022 analog input circuit
or by an external filter, if one is used. Because the typical
noise of the ADAS3022’s SAR ADC core is 35 µV rms (VREF
4.096 V), the SNR degradation due to the amplifier is
=
A—8 CHANNELS,
SINGLE-ENDED
B—8 CHANNELS,
COMMON REFERENCE
IN0+ (–)
IN0– (+)
IN1+ (–)
IN1– (+)
IN2+ (–)
IN2– (+)
IN3+ (–)
IN3– (+)
IN0+ (–)
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
COM
IN0– (+)
IN1+ (–)
IN1– (+)
35
SNRLOSS = 20log
π
2
352 + f−3dB (NeN )2
IN2+
IN3+
where:
−3dB is the input bandwidth (8 MHz) of the ADAS3022’s SAR
ADC core expressed in megahertz or the cutoff frequency of
f
IN4+
IN5+
an input filter, if one is used.
COM–
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp
expressed in nV/√Hz.
C—4 CHANNELS,
DIFFERENTIAL
D—COMBINATION
Figure 61. Multiplexed Analog Input Configurations
•
•
For ac applications, the driver should have a THD performance
commensurate with the ADAS3022.
Channel Sequencer
The ADAS3022 includes a channel sequencer that is useful for
scanning channels in a repeated fashion. Refer to the Channel
Sequencer Details section for more information.
The analog input circuit must settle a full-scale step onto
the capacitor array at a 16-bit level (0.0015%). In amplifier
data sheets, settling at 0.1% to 0.01% is more commonly
specified. This may differ significantly from the settling
time at a 16-bit level and should be verified prior to driver
selection.
Auxiliary Input Channel
The ADAS3022 includes an auxiliary input channel pair (AUX+
and AUX−) that bypasses the mux and PGIA stages, allowing direct
access to the SAR ADC core for applications where the additional
dedicated channel pair is required. As detailed previously, the
inputs are protected only from AVDD and AGND because the high
voltage supplies are used for the mux and PGIA stages but not the
lower voltage ADC core.
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841-1, ADA4841-2 Very low noise, small, and low power
ADA4897-1, ADA4897-2 Very low noise, low and high frequencies
AD8655
AD8021, AD8022
OP184
5 V single supply, low noise
When the source impedance of the driving circuit is low, the
AUX inputs can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performance parameters are less sensitive to the input impedance.
The maximum source impedance depends on the amount of
THD that can be tolerated. The THD degrades as a function of
the source impedance and the maximum input frequency.
Very low noise and high frequency
Low power, low noise, and low frequency
5 V single supply, low power
AD8605, AD8615
Rev. A | Page 27 of 40
ADAS3022
Data Sheet
the main system reference. With REFIN = 2.5 V, REF1 and REF2
output 4.096 V, which serves as the main system reference.
VOLTAGE REFERENCE OUTPUT/INPUT
The ADAS3022 allows the choice of an internal reference or an
external reference using the on-chip buffer/amplifier, or an
external reference.
For this configuration, connect the external source as shown
in Figure 63. Any type of 2.5 V reference, including those with
low power, low drift, and a small package, can be used in this
configuration because the internal buffer handles the dynamics
of the ADAS3022 reference.
The internal reference of the ADAS3022 provides excellent
performance and can be used in almost all applications. To set
the reference selection mode, use the internal reference enable bit
(REFEN) and the REFIN pin as described in this section. REF1
and REF2 must be tied together externally.
0.1µ
F
0.1µF
0.1µF
REFERENCE
SOURCE = 2.5V
10µF
10µ
F
10µF
Internal Reference
REFN
REF2 REFN
REF1 REFN REFIN
The precision internal reference is factory trimmed and is
suitable for most applications.
RCAP
1µF
BAND
GAP
ADAS3022
Setting the REFEN bit in the CFG register to 1 (default) enables
the internal reference and produces 4.096 V on the REF1 and
REF2 pins; this 4.096 V output serves as the main system
reference. The unbuffered 2.5 V (typical) band gap voltage is
output on the REFIN pin, which requires an external parallel
decoupling using 10 µF and 0.1 µF capacitors to reduce the
noise on the output. Because the current output of REFIN is
limited, it can be used as a source if followed by a suitable buffer,
such as the AD8031. Note that excessive loading of the REFIN
output will also lower the 4.096 V system reference because the
internal amplifier uses a fixed gain.
RGND
Figure 63. External Reference Using Internal Buffer
External Reference
For applications that require a precise, low drift 4.096 V reference,
an external reference can also be used.
This option requires disabling the internal buffer by setting
REFEN to 0 and driving or connecting REFIN to AGND; therefore,
both hardware and software control are necessary. Attempting
to drive the REF1 and REF2 pins prior to disabling the internal
buffer can cause source/sink contention in the driving amplifiers.
The internal reference output is trimmed to the targeted value
of 4.096 V with an initial accuracy of 8 mV. The reference is
also temperature compensated to provide a typical drift of
5 ppm/°C.
Connect the precision 4.096 V reference, which serves as the
main system reference, through a low impedance buffer (such as
the AD8031 or the AD8605) to REF1 and REF2 as shown in
Figure 64. Recommended references include the ADR434,
ADR444, and ADR4540.
When the internal reference is used, the ADAS3022 should be
decoupled as shown in Figure 62. Note that both REF1 and
REF2 connections are required, along with suitable decoupling
on the REFIN output and the RCAP internally regulated supply.
REFERENCE
SOURCE = 4.096V
0.1µF
0.1µF
0.1µ
F
0.1µ
F
0.1µF
10µF
10µF
10µF
10µ
F
10µF
REFN
REF2 REFN REF1
REFIN
REFN
REF2 REFN
REF1 REFN REFIN
RCAP
1µF
BAND
GAP
RCA
1µF
P
ADAS3022
BAND
GAP
ADAS3022
RGND
RGND
Figure 64. External Reference
Figure 62. 4.096 V Internal Reference Connection
If an op amp is used as the external reference source, take note
of any concerns regarding driving capacitive loads. Capacitive
loading for op amps usually refers to the ability of the amplifier
to remain marginally stable in ac applications but can also play
a role in dc applications, such as a reference source. Keep in
mind that the reference source sees the dynamics of the bit
decision process on the reference pins and further analysis
beyond the scope of this data sheet may be required.
External Reference and Internal Buffer
The external reference and internal buffer are useful when a com-
mon system reference is used or if improved drift performance
is required.
Setting REFEN to 0 disables the internal band gap reference,
allowing the user to provide an external voltage reference (2.5 V
typical) to the REFIN pin. The internal buffer remains enabled,
thus reducing the need for an external buffer amplifier to generate
Rev. A | Page 28 of 40
Data Sheet
ADAS3022
POWER SUPPLY
Reference Decoupling
The ADAS3022 uses five supplies: AVDD, DVDD, VIO, VDDH,
and VSSH (see Table 9). Note that ACAP, DCAP, and RCAP are
included in Table 9 for informational purposes only because these
supplies are outputs of the on-chip supply regulators. Refer to
UG-484 for more information about how these supplies are
generated on the EVAL-ADAS3022EDZ.
With any of the reference topologies described in the Voltage
Reference Input/Output section, the REF1 and REF2 reference
pins of the ADAS3022 have dynamic impedances and require
sufficient decoupling, regardless of whether the pins are used as
inputs or outputs. This decoupling usually consists of a low ESR
capacitor connected to each REF1 and REF2 and to the accom-
panying REFN return paths. Using X5R, 1206 size ceramic chip
capacitors is recommended for decoupling in all the reference
topologies described in the Voltage Reference Input/Output section.
Table 9. Power Supplies
Name
AVDD
DVDD
Function
Required
Analog 5 V core
Digital 5 V core
Yes
The placement of the reference decoupling capacitors plays an
important role in the system performance. Mount the decoupling
capacitors on the same side as the ADAS3022, close to the REF1
and REF2 pins, with thick PCB traces. Route the return paths to the
REFN inputs, which are in turn connected to the analog ground
plane of the system. The resistance of the return path to ground
should be minimized by using as many through vias as possible
when it is necessary to connect to an internal PCB layer.
Yes, or can connect to
AVDD
VIO
Digital input/output
Yes, and can connect
to DVDD (for 5 V
level)
VDDH
VSSH
ACAP
DCAP
RCAP
Positive high voltage
Negative high voltage
Analog 2.5 V core
Digital 2.5 V core
Yes, +15 V typ
Yes, −15 V typ
No, on chip
No, on chip
No, on chip
Analog 2.5 V core
The REFN and RGND inputs should be connected with the
shortest distance to the analog ground plane of the system,
preferably adjacent to the solder pads, using several vias. One
common mistake is to route these traces to an individual trace
that connects to the ground of the system. This can introduce
noise, which may adversely affect LSB sensitivity. To prevent
such noise, it is highly recommended to use PCBs with multiple
layers, including ground planes, rather than using single- or
double-sided boards. Refer to UG-484 for more information
about the PCB layout of the EVAL-ADAS3022EDZ.
Core Supplies
AVDD and DVDD supply the ADAS3022 analog and digital
cores, respectively. Sufficient decoupling of these supplies is
required, consisting of at least a 10 μF capacitor and a 100 nF
capacitor on each supply. The 100 nF capacitors should be
placed as close as possible to the ADAS3022. To reduce the
number of supplies needed, DVDD can be supplied from the
analog supply by connecting a simple RC filter between AVDD
and DVDD, as shown in Figure 65.
For applications that use multiple ADAS3022 devices or other
PulSAR ADCs, it is more effective to use the internal reference
buffer to buffer the external reference voltage, thus reducing
SAR conversion crosstalk.
VIO is the variable digital input/output supply and can be
directly interfaced to any logic between 1.8 V and 5 V (DVDD
supply maximum). To reduce the supplies needed, VIO can
alternatively be connected to DVDD when DVDD is supplied
from the analog supply through an RC filter. The recommended
low dropout regulators are ADP3334, ADP1715, and ADP7102/
ADP7104 for the AVDD, DVDD, and VIO supplies.
The voltage reference temperature coefficient (TC) directly
affects the full-scale accuracy of the system; therefore, in
applications where full-scale accuracy is crucial, care must be
taken with the TC. For example, a 15 ppm/°C TC of the
reference changes the full-scale accuracy by 1 LSB/°C.
20
Ω
ANALOG
SUPPLY
+5V
+5V DIGITAL
SUPPLY
10µF
100nF
100nF
10µF
1.8V TO 5V
DIGITAL I/O
SUPPLY
AVDD AGND DVDD DGND
+15V
10µF
VDDH
VIO
10µF
100nF
100nF
ADAS3022
10µF
–15V
100nF
DGND
VSSH
Figure 65. ADAS3022 Supply Connections
Rev. A | Page 29 of 40
ADAS3022
Data Sheet
High Voltage Supplies
be allowed the specified settling time. Returning PD low also
resets the ADAS3022 digital core, including the CFG register, to
its default state. Therefore, the desired CFG must be rewritten
to the device and two dummy conversions must be completed
before the device operation is restored to the configuration
programmed prior to PD assertion.
The high voltage bipolar supplies (VDDH and VSSH) are
required and must be at least 2.5 V larger than the maximum
input. For example, the supplies should be 15 V for headroom
in the 24.576 V differential input range. Sufficient decoupling
of these supplies is also required, consisting of at least a 10 μF
capacitor and a 100 nF capacitor on each supply.
CONVERSION MODES
Power Dissipation Modes
The ADAS3022 offers two conversion modes to accommodate
varying applications. The mode is set with the conversion mode
select bit (CMS, Bit 1 of the CFG register).
The ADAS3022 offers two power dissipation modes: fully
operational mode and power-down mode.
Warp Mode (CMS = 0)
Fully Operational Mode
Setting CMS to 0 is useful when an aggregate throughput rate of
1 MSPS is required. However, in this mode, the maximum time
between conversions is restricted. If this maximum period is
exceeded, the conversion result may be corrupted. Therefore,
this mode is more suitable for continually sampled applications.
In fully operational mode, the ADAS3022 can perform
conversions as soon as all internal bias currents are established.
Power-Down Mode
To minimize the operating currents of the device when it is idle,
place the device in full power-down mode by bringing the PD
input high. This places the ADAS3022 into a deep sleep mode, in
which CNV activity is ignored and the digital interface is inactive.
Refer to the Reset and Power-Down (PD) Inputs section for
timing details. In deep sleep mode, the internal regulators
(ACAP, RCAP, and DCAP) and the voltage reference are also
powered down. To reestablish operation, return PD low. Note
that before the device can operate at the specified performance, the
reference voltage must charge up the external reservoir
capacitor(s) and
Normal Mode (CMS = 1, Default)
Setting CMS to 1 is useful for all applications with a maximum
aggregate throughput of 900 kSPS. In this mode, there is no
restriction in terms of the maximum time between conversions.
This mode is the default condition from the assertion of an
asynchronous RESET. The main difference between normal
mode and warp mode is the BUSY time; tQUIET is slightly longer
in normal mode than it is in warp mode.
Rev. A | Page 30 of 40
Data Sheet
ADAS3022
DIGITAL INTERFACE
BUSY Falling Edge—End of a Conversion (EOC)
The ADAS3022 digital interface consists of asynchronous
inputs, a busy indicator, and a 4-wire serial interface for
conversion result readback and configuration register
programming.
The EOC event is indicated by BUSY returning low and can be
used as a host interrupt. In addition, the EOC gates data access
to and from the ADAS3022. If the current conversion result is
not read prior to the following EOC event, the data is lost.
Furthermore, if the CFG update is not completed prior to EOC, it
is discarded and the current configuration is applied to future con-
versions. This pipeline ensures that the ADAS3022 has
sufficient time to acquire the next sample to the specified 16-bit
accuracy.
This interface uses the three asynchronous signals (CNV,
RESET, and PD) and a 4-wire serial interface composed of
CS
,
CS
SDO, SCK, and DIN.
applications.
can also be tied to CNV for some
Conversion results are available on the serial data output pin
(SDO), and the 16-bit configuration word (CFG) is program-
med on the serial data input pin (DIN). This register controls
Conversion Timing
A detailed timing diagram of the conversion process is shown
in Figure 66.
settings such as the channel to be converted, the programmable
gain setting, and the reference choice (see the Configuration
Register section for more information).
tCYC
SOC
(n)
EOC
(n)
SOC
(n + 1)
CONVERSION CONTROL
tCONV
tCBD
tDDC
Conversions are initiated by the CNV input. The ADAS3022 is
fully asynchronous and can perform conversions at any frequency
from dc up to 1 MHz, depending on the conversion mode.
tQUIET
tDDCA
tDAC
tAD
tCH
CNV
BUSY
SAFE
QUIET
CNV Rising Edge—Start of a Conversion (SOC)
CONVER-
SION
(n + 1)
(n)
A rising edge on CNV changes the state of the ADAS3022 from
track mode to hold mode and is all that is necessary to initiate a
conversion. All conversion timing clocks are internally generated.
After a conversion is initiated, the ADAS3022 ignores other
activity on the CNV line (governed by the throughput rate) until
the end of the conversion; the conversion can only be aborted
by the power-down (PD) or RESET inputs.
ACQUI-
SITION
(n)
XXX
tCCS
(n + 1)
XXX
tACQ
tCCS
CS
SDO
DIN
DATA
(n – 1)
DATA
(n)
CFG
CFG
x
x
x
(n + 2)
(n + 3)
When the ADAS3022 is performing a conversion and the BUSY
output is driven high, the ADAS3022 uses a unique 2-phase
conversion process to allow for safe data access and quiet times.
Figure 66. Basic Conversion Timing
Register Pipeline
CS
The CNV signal is decoupled from the
pin, allowing
To ensure that all CFG updates are applied during a known safe
instant to the various circuit elements, the asynchronous data
transfer is synchronized to the ADAS3022 timing engine using
the EOC event. This synchronization introduces an inherent delay
between updating the CFG register setting and the application
of the configuration to a conversion. This pipeline from the end
of the current conversion (n) consists of a two-deep delay (shown
as (n + 2) in Figure 66) before the CFG setting takes effect. This
means that two SOC and EOC events must elapse before the
setting (that is, new channel, gain, and so on) takes effect. Note
that the nomenclature (n), (n + 1), and so on is used in the
remainder of the following digital sections for simplicity.
multiple ADAS3022 devices to be controlled by the same
processor. For applications where SNR is critical, the CNV
source should have very low jitter. This can be achieved by
using a dedicated oscillator or by clocking CNV with a high
frequency, low jitter clock. For applications where jitter is more
CS
tolerable or a single device is in use, CNV can be tied to . For
more information about sample clock jitter and aperture delay,
refer to the MT-007 Tutorial, Aperture Time, Aperture Jitter,
Aperture Delay Time—Removing the Confusion.
Although CNV is a digital signal, it should be designed to
ensure fast, clean edges with minimal overshoot, undershoot,
and ringing. The CNV trace should be shielded by connecting a
trace to ground, and a low value (such as 50 Ω) serial resistor
termination should be added close to the output of the component
that drives this line. In addition, care should be taken to avoid
digital activity close to the sampling instant because such activity
may result in degraded SNR performance.
There is no pipeline after the end of a conversion, however,
before data can be read back.
Rev. A | Page 31 of 40
ADAS3022
Data Sheet
RESET AND POWER-DOWN (PD) INPUTS
Note that in Figure 67 and Figure 68, SCK is shown idling high.
SCK can idle high or low, requiring that the system developer
design an interface that suits setup and hold times for both SDO
and DIN.
The asynchronous RESET and PD inputs can be used to reset
and power down the ADAS3022, respectively. Timing details
are shown in Figure 67.
tSCK
A rising edge on RESET or PD aborts the conversion process and
tSCKH
tDIS
tSCKL
CS
places SDO into high impedance, regardless of the
level. Note
CS
that RESET has a minimum pulse width (active high) time for
setting the ADAS3022 into the reset state. See the Configuration
Register section for the default CFG setting when the ADAS3022
returns from the reset state. If the default setting is used after
RESET is deasserted (Logic 0), a period equal to the acquisition
time (tACQ) must elapse before CNV can be asserted for the
conversion result to be valid. If a conversion is initiated, the
result will be corrupted. In addition, the output data from the
previous conversion is cleared upon a reset. Attempting to
access the data result prior to initiating a new conversion results
in an invalid result.
SCK
tSDOH
tEN
SDO
tSDOD
(MISO)
DIN
(MOSI)
tDINS
tDINH
Figure 68. Serial Timing
CPHA
The clock phase select bit (CPHA, Bit 0) sets the first bit of the
conversion result on SDO after the end of a conversion (see
Figure 69).
When the device returns from power-down mode or from a reset
and the default CFG is not used, there is no tACQ requirement;
the first two conversions from power-up are undefined/invalid
because the two-deep delay pipeline requirement must be satisfied
to reconfigure the device to the desired setting.
CS
Setting CPHA to 0 outputs the MSB when
is asserted. Sub-
sequent SCK falling edges clock out bits in an MSB − 1, MSB − 2,
and so on fashion. This mode is useful for hosts limited to 16 clock
edges where the first falling (or rising) edge can be used to latch
the data.
tACQ
SEE NOTE
tRH
CNV
n – 1
n
RESET/
PD
CS
Setting CPHA to 1 outputs the MSB not only when is asserted
n – 1
BUSY
but also after the first SCK falling edge. Subsequent SCK falling
edges clock out bits in an MSB − 1, MSB − 2, and so on fashion.
This mode can be useful for sign extension applications.
tEN
tDIS
CS
n – 2
n + 1
n – 1
x
SDO
CFG
CS
x
x
n + 2
x
2
15
16
1
SEE NOTE
SCK
NOTES
1. WHEN THE PART IS RELEASED FROM RESET, tACQ MUST BE MET FOR
CONVERSION n IF USING THE DEFAULT CFG SETTING FOR CHANNEL IN0.
WHEN THE PART IS RELEASED FROM POWER-DOWN, tACQ IS NOT REQUIRED,
AND THE FIRST TWO CONVERSIONS, n AND n + 1, ARE UNDEFINED.
MSB MSB – 1 MSB – 2
LSB + 1
LSB + 2
LSB
MSB
LSB
SDO
CPHA = 0
SDO
CPHA = 1
MSB
MSB
MSB – 1
LSB + 1
Figure 67. RESET and PD Timing
Figure 69. CPHA Details
SERIAL DATA INTERFACE
Sampling on the SCK Falling Edge
The ADAS3022 uses a simple 4-wire interface and is compatible
with FPGAs, DSPs, and common serial interfaces, such as SPI,
QSPI, and MICROWIRE™. The interface uses the , SCK,
SDO, and DIN signals. Timing details for the serial interface are
shown in Figure 68. SDO is activated when
conversion result is output on SDO and is updated on SCK
falling edges. Simultaneously, the 16-bit CFG word is updated, if
desired, on the serial data input (DIN). The state of the clock
phase select bit (CPHA, Bit 0) determines whether the MSB is
output again on the first clock or whether the MSB − 1 bit is
output when SDO is activated after the EOC.
To achieve the fastest data transfer rate, the host should sample
data on the SCK falling edge, as long as there is a sufficient hold
time of ≤tSDOH (see Figure 68). When using this method, data
transfers should occur during the safe conversion time (tDDC).
Because this time is fixed, extending data reading or writing into
the quiet conversion phase (tQUIET) may cause data corruption.
However, for systems that need slightly more time, tDDCA (data
during conversion additional) can be used.
CS
CS
is asserted. The
Rev. A | Page 32 of 40
Data Sheet
ADAS3022
SOC
EOC
tDDCA
Sampling on the SCK Rising Edge (Alternate Edge)
tAD
tDDC
SPI or other alternate edge transfers typically require more time
to access data because the total data transfer time of these slower
hosts can be >tDDC. If this is the case, the time from tQUIET to the next
CNV rising edge, which is known as the data access time after
conversion (tDAC) and is determined by the user, must be
adjusted by lowering the throughput rate (CNV frequency),
thus providing the necessary time. If this does not allow enough
time, the data access can be broken up so that some data access
occurs during this time followed by the remainder of data
access occurring during the next tDDC and tDDCA times.
tQUIET
CNV
BUSY
CS
n
n + 1
n + 2
n + 1
n
n – 1
n + 2
n
SDO
DIN
n + 3
SCK
Figure 70. Data Access During Conversion
CFG Readback
Data Access After/Spanning Conversion—Host Determined
Throughput
The CFG result associated with the current conversion can be read
back with an additional 16 SCK burst following the conversion
result (see Figure 69). After the LSB of the conversion result is
clocked out, the MSB of the CFG associated with that conversion
follows. Subsequent SCK falling edges repeat the conversion
result and CFG word. For example, when CPHA is 0, the MSB
of the conversion result is output on the 32nd falling edge.
For hosts that do not have the 34 MHz or 25 MHz SCK rates
available, the maximum throughput rate cannot be achieved
because the data access time after conversion, tDAC, must be
increased to allow more time to access data. In this case, there
are three methods to access data:
•
The first method is to adjust tDAC for 17 SCK edges (worst
CS
GENERAL CONSIDERATIONS
case) and the additional
to CNV setup and hold times.
Because the time to access data is somewhat restricted, the
following guidelines are useful in determining the ADAS3022
throughput, or CNV frequency, and the serial interface details.
Note that in Figure 70 to Figure 72, tAD is for reference purposes
only and denotes a time without digital activity because such
activity should not occur prior to or just after sampling.
In this case, all data access occurs during tDAC. This is the
only method that can be used when using a slow host that
cannot break up data into bytes or other partial data bursts.
A second method is to break up the data into bursts that
can transfer part of the data during tDAC of the current
conversion and the rest of the data during tDDC of the next
•
Data Access During Conversion—Maximum Throughput
CS
conversion. Note that
can stay low throughout the CNV
rising phase; however, serial clock activity should pause
while the input is being sampled.
A third method is to use the second method along with the
additional tDDCA, again noting that digital activity must cease
after this time to prevent the current conversion from
becoming corrupted.
The maximum throughput rate per channel is determined
mainly by the maximum SCK period of the host. When using
the maximum throughput rate of 1 MSPS, the ADAS3022 has
an almost symmetric period for both safe data and quiet times
(~500 ns each; see Figure 70). Consequently, tDDC is basically
fixed and only provides the host ~500 ns to access data. Note
that in Figure 70, tAD is for reference purposes only and denotes
a time without digital activity because such activity should not
occur during the sampling edge. For 17 SCK edges (worst case), the
minimum SCK frequency required to achieve a 1 MSPS (1 µs
between CNV rising) aggregate throughput rate is
•
In any of these methods, if the time between conversions (tCYC
)
is exceeded for the fastest possible throughput mode (CMS = 0),
the conversion results will be inaccurate. If this is the case, the
fully asynchronous mode (CMS = 1) must be selected (see the
Conversion Modes section for details).
17
f
≥
≥ 34 MHz
SCK
Figure 71 shows a basic timing diagram for all three methods.
For conversion (n), the data is read back after the end of a
conversion (n), with the remainder of data read into the next
(n + 1) conversion.
tAD + tDDC
Although additional time to access data can be attained by trans-
ferring data during tDDCA, this is not recommended because the
ADAS3022 performs sensitive bit decisions during this time. If
tDDCA is used, however, the minimum SCK frequency is
17
f
≥
≥ 25 MHz
SCK
tAD + tDDC + tDDCA
Rev. A | Page 33 of 40
ADAS3022
Data Sheet
tDDCA
SOC
EOC
SOC
GENERAL TIMING
tAD
tDAC
tDDC
Figure 72 is a general timing diagram showing the complete
register to conversion and readback pipeline delay. The figure
details the timing upon power-up or upon returning from a full
power-down by use of the PD input. Figure 73 and Figure 74 show
the general timing diagrams when only the auxiliary ADC input
channel pair is enabled for the data read during conversion (RDC)
mode and the read after conversion (RAC) mode, respectively.
CNV
n
n + 1
tCCS
BUSY
n
n + 1
CS
SDO
n – 1
n + 2
n
n + 3
n
DIN
x
x
x
n + 3
SCK
Figure 71. Data Access Spanning Conversion
tACQ
EOC
tCYC
SOC
SOC
EOC
tQUIET
NOTE 2
tDDC
NOTE 1
tDAC
NOTE 1
POWER
UP
CONVERSION (n – 1)
UNDEFINED
ACQUISITION (n)
UNDEFINED
CONVERSION (n)
UNDEFINED
ACQUISITION (n + 1)
UNDEFINED
CONVERSION (n + 1)
UNDEFINED
PHASE
CNV
BUSY
tDDCA
NOTE 2
NOTE 5
tAD
NOTE 4
CS
X
1
16/32
NOTE 3
1
16
SCK
CFG
INVALID
CFG (n + 2)
CFG (n + 2)
CFG (n + 3)
CFG (n + 3)
DIN
DATA
INVALID
DATA (n – 1)
INVALID
DATA (n – 1)
INVALID
DATA (n)
INVALID
DATA (n)
INVALID
SDO
EOC
EOC
EOC
ACQUISITION
(n + 4)
CONVERSION
(n + 2)
ACQUISITION
(n + 3)
CONVERSION
(n + 3)
CONVERSION
(n + 4)
ACQUISITION
(n + 2)
PHASE
CNV
BUSY
CS
1
1
16
16
1
SCK
CFG (n + 4)
CFG (n + 4)
CFG (n + 5)
CFG (n + 5)
CFG (n + 6)
CFG (n + 6)
DIN
DATA (n + 1)
INVALID
DATA (n + 1)
INVALID
SDO
DATA (n + 2)
DATA (n + 2)
DATA (n + 3)
DATA (n + 3)
NOTES
1. DATA ACCESS CAN OCCUR DURING A CONVERSION (tDDC), AFTER A CONVERSION (tDAC), OR BOTH DURING AND AFTER A CONVERSION.
THE CONVERSION RESULT AND THE CFG REGISTER ARE UPDATED AT THE END OF A CONVERSION (EOC).
2. DATA ACCESS CAN ALSO OCCUR UP TO tDDCA WHILE BUSY IS ACTIVE (SEE THE DIGITAL INTERFACE SECTION FOR DETAILS). ALL OF THE BUSY
TIME CAN BE USED TO ACQUIRE DATA.
3. A TOTAL OF 16 SCK FALLING EDGES IS REQUIRED FOR A CONVERSION RESULT. AN ADDITIONAL 16 EDGES ARE REQUIRED TO
READ BACK THE CFG RESULT ASSOCIATED WITH THE CURRENT CONVERSION.
4. CS CAN BE HELD LOW OR CONNECTED TO CNV. CS WITH FULL INDEPENDENT CONTROL IS SHOWN IN THIS FIGURE.
5. FOR OPTIMAL PERFORMANCE, DATA ACCESS SHOULD NOT OCCUR DURING THE SAMPLING EDGE. A MINIMUM TIME
OF THE APERTURE DELAY (tAD) SHOULD ELAPSE PRIOR TO DATA ACCESS.
Figure 72. General Timing Diagram
Rev. A | Page 34 of 40
Data Sheet
ADAS3022
SOC
EOC
tAD
tQUIET
CNV
n + 2
n
n + 1
BUSY
CS
n
n + 1
n + 2
n – 1
n + 2
SDO
DIN
n
n + 1
n + 4
n + 3
16
16
1
1
1
16
SCK
Figure 73. General Timing Diagram of AUX Input Channel Pair (RDC)
SOC
EOC
tEN
tAD
tQUIET
CNV
n + 2
n + 3
n + 3
n
n + 1
BUSY
CS
n
n + 1
n + 2
n
SDO
DIN
n + 1
n + 4
n + 2
n + 5
n + 3
16
1
1
16
1
16
SCK
Figure 74. General Timing Diagram of AUX Input Channel Pair (RAC)
Rev. A | Page 35 of 40
ADAS3022
Data Sheet
conversions are required for the user-specified CFG setting to
take effect. Therefore, the default value is CFG[15:0] = 0x8FCF.
This sets the ADAS3022 as follows:
CONFIGURATION REGISTER
The configuration register, CFG, is a 16-bit, programmable
register for selecting all of the ADAS3022 user-programmable
options (see Table 11). The register is loaded when data is read
back for the first 16 SCK rising edges and is updated at the next
EOC. Note that there is always a two-deep delay (n + 2) when
writing CFG and when reading back CFG for the setting
associated with the current conversion.
•
•
•
•
•
•
•
•
•
Overwrites contents of CFG register
Selects the IN0 input channel referenced to COM
Configures the PGIA gain to 0.20 ( 20.48 V)
Selects the multiplexer input
Disables the internal channel sequencer
Disables the temperature sensor
Enables the internal reference
Selects normal conversion mode
Selects SPI interface mode
The default CFG setting is applied when the ADAS3022 returns
from the reset state (RESET = high) to the operational state
(RESET = low). However, when the ADAS3022 returns from the
full power-down state (PD = high) to an enabled state (PD = low),
the default CFG setting is not applied, and at least two dummy
Table 10. Configuration Register, CFG; Default Value = 0x8FCF (1000 1111 1100 1111)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CFG
INx
INx
INx
COM
RSV
PGIA PGIA PGIA MUX SEQ
SEQ
TEMPB REFEN CMS
CPHA
Table 11. Configuration Register Bit Description
Bits
Bit Name
Description
15
CFG
Configuration update.
0 = keep current configuration settings.
1 = overwrite contents of register (default).
[14:12] INx
Input channel selection in binary fashion. See the Multiplexer section.
Bit 14
Bit 13
Bit 12
Channel
0
0
0
IN0 (default)
…
1
…
1
…
1
IN7
11
COM
IN[7:0] common channel input. AUX+ and AUX− are not referenced to COM.
0 = channels are referenced in differential pairs: IN0/IN1, IN2/IN3, IN4/IN5, and IN6/IN7 (see the Channel Sequencer
Details section).
1 = each channel is referenced to a common sense, COM (default).
Reserved. Setting or clearing this bit has no effect.
10
RSV
[9:7]
PGIA
Programmable gain selection (see the Input Structure section). In basic sequencer modes, this register configures
the range for all channels. In advanced sequencer mode, this register sets the range for IN0 (COM = 1) or the IN0/IN1
pair (COM = 0). See the Advanced Mode section for the PGIA configurations of individual channels or channel pairs.
Bit 9
Bit 8
Bit 7
Absolute Input Voltage Range
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24.576 V
10.24 V
5.12 V
2.56 V
1.28 V
0.64 V
Not used
20.48 V (default)
6
MUX
Multiplexer/auxiliary channel input (see the Auxiliary Input Channel section).
0 = selects auxiliary channel on AUX inputs as active channel.
1 = uses the selected analog front end (AFE) channel/channel pair (default).
Rev. A | Page 36 of 40
Data Sheet
ADAS3022
Bits
Bit Name
Description
[5:4]
SEQ
Channel sequencer. Allows for scanning channels sequentially from IN0 to INx. INx is the last channel converted prior
to resetting the sequence back to IN0 and is specified by the channel selected in the INx[2:0] configuration bits (see
the Channel Sequencer Details section).
Bit 5
Bit 4
Function
0
0
1
1
0
1
0
1
Disable sequencer (default)
Update configuration during basic sequence
Initialize advanced sequencer
Initialize basic sequencer
Temperature sensor enable control (see the Channel Sequencer Details section).
0 = internal temperature sensor enabled.
1 = internal temperature sensor disabled (default).
3
2
TEMPB
REFEN
Internal reference selection (see the Pin Configuration and Function Descriptions and Voltage Reference
Input/Output sections for more information).
0 = disables the internal reference. The internal reference buffer is disabled by pulling REFIN to ground.
1 = enables the internal reference (default).
1
0
CMS
Conversion mode select (see the Conversion Modes section).
0 = uses the warp mode for conversions with a time between conversion restriction.
1 = uses the normal mode for conversions (default).
CPHA
MSB select (see the CPHA section).
0 = asserting CS after the end of a conversion places the MSB on SDO, and the first SCK falling edge places (MSB − 1) on SDO.
1 = asserting CS after the end of a conversion places the MSB on SDO, and the first SCK falling edge repeats MSB on SDO
(default).
CHANNEL SEQUENCER DETAILS
Table 12. Typical Channel Sequencer Example
The ADAS3022 includes a channel sequencer, which is useful for
scanning channels in a sequential order. Channels are scanned
individually with reference to COM or as pairs and can also
include the auxiliary channel pair and/or the internal temperature
sensor measurement. After the last programmed measurement
is sampled, the ADAS3022 sequencer is reset to the first channel
(IN0) or channel pair (IN0/IN1) and repeats the sequence until
the sequencer is disabled or an asynchronous RESET or PD occurs.
INx[14:12]
COM
MUX
TEMPB
End of Sequence
IN3 (to COM)
IN7 (to COM)
IN6 to IN7
TEMPB
011
111
11x
111
111
111
1
1
0
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
AUX
AUX
INx and COM Inputs (MUX = 1, TEMPB = 1)
When the channel sequencer is enabled, for all differential
pairs, the positive terminals are the even channels (IN0, IN2,
IN4, and IN6), and the negative terminals are, conversely, the
odd channels (IN1, IN3, IN5, and IN7). When the channel
sequencer is disabled, the user can assign either positive or
negative terminals to even or odd channels for all differential
pairs, depending on the INx[14:12] settings. For example, if
INx[14:12] = 001 when using the IN0/IN1 pair, IN1 is the
positive input and IN0 is the negative input.
To use individual INx channels with reference to COM or pairs
of INx channels in a sequence without converting the AUX or
temperature sensor channels, the MUX and TEMPB bits must
be set to 1. The last channel to be converted in the sequence is
specified by the channel set in the INx bits. After the last channel is
scanned, the next conversion starts over at IN0 or IN0/IN1. For
paired channels, the channels are paired depending on the last
channel set in INx. Note that the channels are always paired
with the positive input on the even channels (IN0, IN2, IN4,
IN6) and the negative input on the odd channels (IN1, IN3, IN5,
IN7). Therefore, setting INx to 110 or 111 scans all pairs with
the positive inputs dedicated to IN0, IN2, IN4, and IN6. For
example, to scan four single channels, set INx to 011, COM to 1,
and MUX to 1, which results in a sequence order of IN0, IN1,
IN2, IN3, IN0, IN1, IN2, and IN3.
Each sequence loop always starts with IN0 or IN0/IN1 and
terminates with either the last channel/channel pair set in the
INx bits, the temperature sensor, or the auxiliary input channel,
depending on the configuration word. Table 12 provides a quick
reference for how the device responds to the programmed configu-
ration. For the first case, the channel sequencer scans Channel IN0
through Channel IN3 in a repeated fashion. Note that the last
conversion is corrupted when exiting the sequencer.
Rev. A | Page 37 of 40
ADAS3022
Data Sheet
Update During Sequence (SEQ = 01)
INx and COM Inputs with AUX Inputs (MUX = 0, TEMPB = 1)
Some of the CFG settings, such as PGIA and CMS, can be updated
during a sequence. Writing a new CFG word with the appropriate
bits to be changed for the (n + 2) conversion updates the sequencer
from that point; all channels then use, for example, the new PGIA
value. Note that changing bits in INx for the last channel or chang-
ing COM reinitializes the sequencer at the (n + 2) conversion. A
more practical method is to use the advanced sequencer mode as
described in the Advanced Sequencer Mode (SEQ = 10) section.
To use individual INx channels with reference to COM or pairs
of INx channels with the AUX inputs in a sequence, the MUX
bit must be set to 0 to append the AUX channel to the end of the
sequence (after the channel set in INx is scanned). Note that the
AUX input is a pair, whereas the INx channel can be referenced to
COM or pairs of INx channels. For example, to scan four single
channels and the AUX inputs, set INx to 011, COM to 1, and
MUX to 0, which results in a sequence order of IN0, IN1, IN2,
IN3, AUX, IN0, IN1, IN2, IN3, AUX, and so on.
Advanced Sequencer Mode (SEQ = 10)
INx and COM Inputs with Temperature Sensor
(MUX = 1, TEMPB = 0)
The advanced mode is useful for systems that require different
gains for different individual INx inputs or different pairs of
INx inputs. In this mode, two additional registers are used to
program the various gain settings. After the initial CFG word
enabling the advanced sequencer mode is written, the ADAS3022
expects to receive at least one additional data transfer for the
first advanced sequencer register, ASR0, or both advanced
sequencer registers, depending on how many channels are in the
sequence. Each ASR requires a conversion and a corresponding
EOC to load the data into the device. The user cannot simply
write 48 bits all at once because, as with all CFG word transfers,
only the first 16 bits are latched and updated at EOC.
To append the temperature sensor conversion to the end of the
input channel sequence, the TEMPB bit must be set low in the
configuration word. Note that the temperature sensor requires
at least 5 µs between conversions. The data is output in straight
binary format.
INx and COM Inputs with AUX Inputs and Temperature
Sensor (MUX = 0, TEMPB = 0)
Both temperature sensor conversions and auxiliary channel
conversions can be appended to the end of the input sequence
by setting the MUX and TEMPB bits in the CFG register. For
example, to scan all input channels with respect to COM, the
temperature sensor, and the auxiliary channel at once, the user
must set INx to 111, COM to 1, MUX to 0, and TEMPB to 0.
The resulting sequence would be IN0, IN1, IN2, IN3, IN4, IN5,
IN6, IN7, temperature sensor, and AUX.
Note that the PGIA setting for IN0 or IN0/IN1 is written in the
initial CFG register, and if using pairs of INx channels, only
ASR0 is required. After the CFG and the associated advanced
sequencer registers are updated, DIN must be held low for at
least the MSB of subsequent data transfers; otherwise, the
advanced sequencer mode will be aborted.
Sequencer Modes
The ADAS3022 has two sequencer modes, which are
Table 13. Advanced Sequencer Register 0
configured with the SEQ bits: basic mode and advanced mode.
Basic mode can be used when all channels are configured with
the same PGIA range. Advanced mode allows individual
channel ranges to be programmed using two additional
advanced sequence registers, ASR0 and ASR1. The SEQ bits are
used to enable the sequencer. Setting SEQ to 01, 10, or 11 specifies
which sequencer mode is used. Depending on the mode, basic
or advanced sequencing determines the next data into DIN.
Bits
Function
15
ASR0 write enable
0 = update ASR0 following CFG for advanced sequencer
1 = enters normal CFG update
Reserved
[14:11]
[10:8]
7
PGIA for IN1 or IN2/IN3
Reserved
[6:4]
3
PGIA for IN2 or IN4/IN5
Reserved
Note that for any sequencer update there exists a two-deep
delay when writing the register for the setting to take effect.
[2:0]
PGIA for IN3 or IN6/IN7
Table 14. Advanced Sequencer Register 1
Basic Sequencer Mode (SEQ = 11)
Bits
Function
The basic mode is useful for systems that use the same PGIA
range on all channels. In basic sequencer mode, all that is
required is a single CFG word to place the ADAS3022 in an
automatically scanned mode. On the second conversion
following the EOC for sequencer CFG, the sequencer starts.
15
ASR1 write enable
0 = update ASR1 following ASR0
1 = enters normal CFG update
PGIA for IN4
[14:12]
11
Reserved
[10:8]
7
PGIA for IN5
After the CFG for basic sequence updates, DIN must be held
low for at least the MSB during the data readback or a new CFG
word will update, disabling the sequencer.
Reserved
[6:4]
3
PGIA for IN6
Reserved
[2:0]
PGIA for IN7
Rev. A | Page 38 of 40
Data Sheet
ADAS3022
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
31
30
40
1
0.50
BSC
*
4.70
EXPOSED
PAD
4.60 SQ
4.50
21
10
11
20
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.00
0.95
0.85
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 75. 40-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
6 mm × 6 mm Body, Very Thin Quad
(CP-40-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADAS3022BCPZ
ADAS3022BCPZ-RL7
EVAL-ADAS3022EDZ
−40°C to +85°C
−40°C to +85°C
40-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-40-15
40-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-40-15
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. A | Page 39 of 40
ADAS3022
NOTES
Data Sheet
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10516-0-1/13(A)
Rev. A | Page 40 of 40
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