ADATE302-02BSVZ_技术文档

500 MHz Dual Integrated DCL with Differential

Drive/Receive, Level Setting DACs, and Per Pin PMU

ADATE302-02

FEATURES

GENERAL DESCRIPTION

Driver

The ADATE302-02 is a complete, single-chip solution that

3-level driver with high-Z mode and built-in clamps

Precision trimmed output resistance

Low leakage mode (typically <10 nA)

Voltage range: −2.0 V to +6.0 V

1.0 ns minimum pulse width, 1 V terminated

Comparator

Window and differential comparator

>1 GHz input equivalent bandwidth

Load

performs the pin electronic functions of the driver, the compa-

rator, and the active load (DCL), per pin PMU, and dc levels for

ATE applications. The device also contains an HVOUT driver

with a VHH buffer capable of generating up to 13.5 V.

The driver features three active states: data high mode, data low

mode, and term mode, as well as an inhibit state. The inhibit

state, in conjunction with the integrated dynamic clamp, facilitates

the implementation of a high speed active termination. The output

voltage range is −2.0 V to +6.0 V to accommodate a wide

variety of test devices.

12 mA maximum current capability

Per pin PMU

Force voltage range: −2.0 V to +6.0 V

5 current ranges: 25 mA, 2 mA, 200 μA, 20 μA, and 2 μA

Levels

14-bit DAC for DCL levels

Typically < 5 mV INL (calibrated)

16-bit DAC for PMU levels

Typically < 1.5 mV INL (calibrated) linearity in FV mode

HVOUT output buffer

0 V to 13.5 V output range

The ADATE302-02 can be used as either a dual single-ended

drive/receive channel or a single differential drive/receive

channel. Each channel of the ADATE302-02 features a high

speed window comparator for functional testing as well as a per

pin PMU with FV or FI and MV or MI functions. All necessary

dc levels for DCL functions are generated by on-chip 14-bit

DACs. The per pin PMU features an on-chip 16-bit DAC for

high accuracy and contains integrated range resistors to

minimize external component counts.

Packages

84-ball, 9 mm × 9 mm, flip-chip BGA

100-lead TQFP_EP

1.7 W per channel with no load

The ADATE302-02 uses a serial bus to program all functional

blocks and has an on-board temperature sensor for monitoring

the device temperature.

APPLICATIONS

Automatic test equipment

Semiconductor test systems

Board test systems

Instrumentation and characterization equipment

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks are theproperty of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

ADATE302-02* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

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DOCUMENTATION

Data Sheet

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• ADATE302-02: 500 MHz Dual Integrated DCL with

Differential Drive/Receive, Level Setting DACs, and Per Pin

PMU Data Sheet

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DESIGN RESOURCES

• ADATE302-02 Material Declaration

• PCN-PDN Information

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ADATE302-02

TABLE OF CONTENTS

Features .............................................................................................. 1

Absolute Maximum Ratings ......................................................... 20

Thermal Resistance.................................................................... 20

Explanation of Test Levels......................................................... 20

ESD Caution................................................................................ 20

Pin Configuration and Function Descriptions........................... 21

Typical Performance Characteristics........................................... 27

Serial Peripheral Interface Details................................................ 39

Definition of SPI Word.............................................................. 40

Write Operation.......................................................................... 41

Read Operation .......................................................................... 42

Reset Operation.......................................................................... 43

Register Map ................................................................................... 44

Details of Registers......................................................................... 45

User Information............................................................................ 47

Details of DACs vs. Levels......................................................... 48

Recommended PMU Mode Switching Sequences ................ 50

Block Diagrams............................................................................... 53

Outline Dimensions....................................................................... 57

Ordering Guide .......................................................................... 58

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Total Function............................................................................... 4

Driver ............................................................................................. 5

Reflection Clamp.......................................................................... 7

Normal Window Comparator .................................................... 7

Differential Comparator.............................................................. 9

Active Load.................................................................................. 11

PMU............................................................................................. 12

External Sense (PMUS_CHx)................................................... 16

DUTGND Input ......................................................................... 17

Serial Peripheral Interface......................................................... 17

HVOUT Driver........................................................................... 17

Overvoltage Detector (OVD) ................................................... 18

16-Bit DAC Monitor Mux ......................................................... 19

REVISION HISTORY

4/09—Rev. 0 to Rev. A

Added 100-Lead TQFP_EP Package........................... Throughout

Added Figure 3, Renumbered Figures Sequentially................... 22

Added Table 17, Renumbered Tables Sequentially .................... 22

Updated Outline Dimensions....................................................... 52

Changes to Ordering Guide .......................................................... 53

6/08—Revision 0: Initial Version

Rev. A | Page 2 of 58

ADATE302-02

FUNCTIONAL BLOCK DIAGRAM

CH1

PMU_FLAG

PMU

16-BIT DAC

*

MUX

DAC16_MON

*

OVD

OVD_CH0

MUX

MEASOUT01

PMUS_CH0

CH1

VCH

VCL

VH

VT

VL

R

OUT

DATA0P

(TRIMMED)

100Ω

DRV

DUT0

DATA0N

RCV0P

*

WINDOW

DIFF.

C

RCV0N

OTHER CHANNEL

DUT1

*

COMP_VTT0

VHH

HVOUT

50Ω

COMP_QH0P

COMP_QH0N

C

VOH

VOL

COMP_QL0P

COMP_QL0N

*

G

IOL

IOH

ADATE302-02

SDIN

*

RST

SCLK

CS

VCOM

*

14-BIT DAC

SPI

TEMPERATURE

SENSOR

TEMPSENSE

SDOUT

*

ONE PER DEVICE.

Figure 1. Functional Block Diagram with One of Two Channels Shown

Rev. A | Page 3 of 58

ADATE302-02

SPECIFICATIONS

V_DD= 10.0 V, V_CC= 3.3 V, V_SS= −5.75 V, V_PLUS= 16.75 V, V_{COMP_VTTx}= 1.5 V, V_REF= 5.0 V, V_{REF_GND}= 0.0 V. All default test conditions are as

defined in Table 38. All specified values are at T_J= 80°C, where T_Jcorresponds to the internal temperature sensor, unless otherwise noted.

Temperature coefficients are measured at T_J= 80°C 20°C, unless otherwise noted. Typical values are based on design, simulation

analyses, and/or limited bench evaluations. Typical values are not tested or guaranteed. Test levels are specified in the Explanation of Test

Levels section.

TOTAL FUNCTION

Table 1.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

TOTAL FUNCTION

Output Leakage Current

PE Disable, Range E

−20.0 +6.0

7.5

+20.0 nA

nA

P

−2.0 V < V_DUTx< +6.0 V; PMU and PE disabled via SPI;

VCH = 7.0 V, VCL = −2.5 V

−2.0 V < V_DUTx< +6.0 V; PMU and PE disabled via SPI;

VCH = 7.0 V, VCL = −2.5 V

−2.0 V < V_DUTx< +6.0 V; PMU disabled and PE enabled via

SPI; RCVx pins active, VCH = 7.0 V, VCL = −2.5V

PE Disable, Range A, B, C, D

High-Z Mode

C_T

P

−400 +15

+400 nA

pF

Output Capacitance

DUT Pin Range

4

S

D

VTERM mode operation

−2.0

+6.0

V

POWER SUPPLIES

Total Supply Range, V_PLUSto V_SS

VPLUS Supply, V_PLUS

Positive Supply, V_DD

Negative Supply, V_SS

Logic Supply, V_CC

Comparator Termination, V_{COMP_VTTx}

V_PLUSSupply Current, I_PLUS

Logic Supply Current, I_CC

Comparator Termination Current,

I_{COMP_VTTx}

22.5

23.25

V

mA

D

P

Defines PSRR conditions

16.25 16.75 17.25

9.5

−6.0

3.1

10.0

−5.75 −5.5

3.3

1.5

+1.3

12.7

2.7

10.5

3.5

3.3

+4.0

17.0

10.0

70.0

1

−1.0

4.0

1.0

HVOUT disabled

HVOUT enabled, RCVx pins active, no load, VHH = 12 V

Quiescent (SPI is static)

40.0

46

Positive Supply Current, I_DD

Negative Supply Current, I_SS

Total Power Dissipation

140.0 190

170.0 231

200.0 272

230.0 311

256.0 mA

311.0 mA

406.0 mA

461.0 mA

P

Load power down (IOH = IOL = 0 mA)

Load active off (IOH = IOL = 12 mA)

Load power down (IOH = IOL = 0 mA)

Load active off (IOH = IOL = 12 mA)

Load power down (IOH = IOL = 0 mA)

Load active off (IOH = IOL = 12 mA)

2.5

3.0

3.55

4.2

4.0

5.5

W

TEMPERATURE MONITORS

Temperature Sensor Gain

Temperature Sensor Accuracy Without

Calibration over 25°C to 100°C

10

6

mV/K C_T

°C

C_T

Temperature voltage available on Pin A1 at all times and

on Pin K1 when selected (see Table 25 and Table 37)

VREF INPUT

Reference Input Voltage Range for

DACs (VREF Pin)

Input Bias Current

4.95

5

5.05

100

V

D

P

Referenced to V_{REF_GND}; not referenced to V_DUTGND

Tested with 5 V applied

0.08

μA

Rev. A | Page 4 of 58

ADATE302-02

DRIVER

VH − VL ≥ 200 mV (to meet dc/ac specifications).

Table 2.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DC SPECIFICATIONS

High-Speed Differential Logic Input

Characteristics (DATAx, RCVx)

Input Termination Resistance

92

100

108

Ω

P

Push 6 mA into xP pins, force 1.3 V on xN pins; measure

voltage from xP to xN, calculate resistance (V/I)

Input Voltage Differential

Common-Mode Voltage

Input Bias Current

0.2

0.85

−20.0 +4.0

1.0

3.5

+20.0 μA

V

P_F

P

Each pin tested at 2.85 V and 0.35 V, while other high speed

pin left open

Pin Output Characteristics

Output High Range, VH

Output Low Range, VL

Output Term Range, VT

Functional Amplitude (VH − VL)

−1.9

−2.0

+6.0

+5.9

+6.0

V

D

0.0

8.0

Amplitude can be programmed to VH = VL, accuracy

specifications apply when VH − VL ≥ 200 mV

DC Output Current Limit Source

75

100

120

mA

P

Driver high, VH = 6.0 V, short DUTx pin to −2.0 V, measure

current

DC Output Current Limit Sink

Output Resistance, 50 mA

−120

45.0

−100

48.5

−75

51.0

mA

Ω

P

Driver low, VL = −2.0 V, short DUTx pin to 6.0 V, measure current

Source: driver high, VH = 3.0 V, I_DUTx= 1 mA and 50 mA;

sink: driver low, VL = 0.0 V, I_DUTx= −1 mA and −50 mA; ΔV_DUTx/ΔI_DUTx

ABSOLUTE ACCURACY

VH tests done with VL = −2.5 V and VT = −2.5 V;

VL tests done with VH = 7.5 V and VT = 7.5 V;

VT tests done with VL = −2.5 V and VH = 7.5 V;

unless otherwise specified

VH, VL, VT Uncalibrated Accuracy

VH, VL, VT Offset Tempco

VH, VL, VT DNL

−300

−10

75

450

1

+300

mV

μV/°C C_T

mV

P

Error measured at calibration points of 0 V and 5 V

Measured at calibration points

After two-point gain/offset calibration

After two-point gain/offset calibration; measured over driver

output ranges

After two-point gain/offset calibration; range/number of DAC

bits as measured at calibration points of 0 V and 5 V

Over 0.1 V range; measured at end points of VH, VL, and VT

functional range

VL = −2.0 V: VH = −1.9 V → 6.0 V, VT = −2.0 V → 6.0 V;

VH = 6.0 V: VL = −2.0 V → 5.9 V, VT = −2.0 V → 6.0 V;

VT = 1.5 V: VL = −2.0 V → 5.9 V, VH = −1.9 V → 6.0 V;

dc crosstalk on VL, VH, VT output level when other driver

DACs are varied

C_T

P

VH, VL, VT INL

2.5

+10

1

VH, VL, VT Resolution

DUTGND Voltage Accuracy

VH, VL, VT Crosstalk

0.6

1.3

2

mV

P_F

P

−7

+7

C_T

Overall Voltage Accuracy

10

15

mV

C_T

Sum of INL, crosstalk, DUTGND, and tempco over 5°C,

after gain/offset calibration

Measured at calibration points

VH, VL, VT DC PSRR

AC SPECIFICATIONS

mV/V C_T

Rise/Fall Times

Toggle DATAx pins

0.2 V Programmed Swing

1.0 V Programmed Swing

1.8 V Programmed Swing

2.0 V Programmed Swing

3.0 V Programmed Swing

5.0 V Programmed Swing

Rise to Fall Matching

683

521

524

531

589

811

1105

6

ps

C_B

P/C_B

C_B

VH = 0.2 V, VL = 0.0 V, terminated; 20% to 80%

VH = 1.0 V, VL = 0.0 V, terminated; 20% to 80%

VH = 1.8 V, VL = 0.0 V, terminated; 20% to 80%

VH = 2.0 V, VL = 0.0 V, terminated; 20% to 80%

VH = 3.0 V, VL = 0.0 V, terminated; 20% to 80%

VH = 3.0 V, VL = 0.0 V, unterminated; 10% to 90%

VH = 5.0 V, VL = 0.0 V, unterminated; 10% to 90%

VH = 1.0 V, VL = 0.0 V, terminated; rise to fall within one channel

430

630

Rev. A | Page 5 of 58

ADATE302-02

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

Minimum Pulse Width

2.0 V Programmed Swing

Toggle DATAx pins

VH = 2.0 V, VL = 0.0 V, terminated; timing error 27 ps

VH = 2.0 V, VL = 0.0 V, terminated; less than 10% amplitude

degradation

1.2

ns

C_B

1.0

ns

C_B

VH = 2.0 V, VL = 0.0 V, terminated; less than 20% amplitude

degradation

VH = 2.0 V, VH = 0.0 V, terminated, 18% amplitude degradation

Toggle DATAx pins

Maximum Toggle Rate

Dynamic Performance, Drive

(VH to VL and VL to VH)

500

MHz

Propagation Delay Time

Propagation Delay Tempco

Delay Matching

Edge to Edge

Channel to Channel

Delay Change vs. Duty Cycle

Overshoot and Undershoot

Settling Time (VH to VL)

To Within 3% of Final Value

To Within 1% of Final Value

Dynamic Performance, VTERM

(VH or VL to VT and VT to

VH or VL)

2.1

4.5

ns

C_B

VH = 2.0 V, VL = 0.0 V, terminated

VH = 1.8 V, VL = 0.0 V, terminated

VH = 2.0 V, VL = 0.0 V, terminated

Rising vs. falling

Rising vs. rising, falling vs. falling

VH = 3.0 V, VL = 0.0 V, terminated; 5% to 95% duty cycle; 1 MHz

VH = 3.0 V, VL = 0.0 V, terminated

Toggle DATAx pins

ps/°C C_T

41

15

30

48

ps

mV

C_B

1.2

14

ns

C_B

VH = 3.0 V, VL = 0.0 V, terminated

Toggle RCVx pins

Propagation Delay Time

Delay Matching, Edge to Edge

Propagation Delay Tempco

2.7

59

5.5

ns

ps

C_B

VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated

VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; rising vs. falling

VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated

ps/°C C_T

Transition Time, Active to VT,

VT to Active

0.614

ns

C_B

VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; 20% to 80%

Dynamic Performance,

Toggle RCVx pins

Inhibit (VH or VL to/from Inhibit)

Propagation Delay Time

Active to Inhibit

Inhibit to Active

Transition Time

Active to Inhibit

Inhibit to Active

I/O Spike

VH = +1.0 V, VL = −1.0 V, terminated

2.7

3.7

ns

C_B

VH = +1.0 V, VL = −1.0 V, terminated; 20% to 80%

VH = 0.0 V, VL = 0.0 V, terminated

1.3

0.4

157

ns

mV

C_B

Rev. A | Page 6 of 58

ADATE302-02

REFLECTION CLAMP

Clamp accuracy specifications apply when VCH > VCL.

Table 3.

Test

Parameter

VCH

Min

Typ

Max

Unit

Level Conditions/Comments

Range

−1.0

+6.0

V

D

Uncalibrated Accuracy

−200

45

+200

mV

P

Driver high-Z, sinking 1 mA; VCH error measured at

calibration points of 0 V and 5 V

Resolution

0.6

0.75

mV

P_F

Driver high-Z, sinking 1 mA; after two-point gain/offset

calibration; range/number of DAC bits as measured at

calibration points of 0 V and 5 V

DNL

INL

1

2

mV

C_T

P

Driver high-Z, sinking 1 mA; after two-point gain/offset

calibration

Driver high-Z, sinking 1 mA; after two-point gain/offset

calibration; measured over VCH range of −1 V to +6 V

−40

+40

mV

Tempco

−0.5

mV/°C

C_T

Measured at calibration points

VCL

Range

Uncalibrated Accuracy

−2

−200

+5.0

+200

V

mV

D

P

70

Driver high-Z, sourcing 1 mA; VCL error measured at

calibration points of 0 V and 5 V

Resolution

0.6

0.75

mV

P_F

Driver high-Z, sourcing 1 mA; after two-point gain/offset

calibration; range/number of DAC bits as measured at

calibration points of 0 V and 5 V

DNL

INL

1

2

mV

C_T

P

Driver high-Z, sourcing 1 mA; after two-point gain/offset

calibration

Driver high-Z, sourcing 1 mA; after two-point gain/offset

calibration; measured over VCL range of −2 V to +5 V

−40

+40

mV

Tempco

0.6

mV/°C

C_T

Measured at calibration points

DC CLAMP CURRENT LIMIT

VCH

VCL

−120

60

−83

86

1

−60

120

+7

mA

mV

P

Driver high-Z, VCH = 0 V, VCL = −2.0 V, V_DUTx= 5 V

Driver high-Z, VCH = 6.0 V, VCL= 5.0 V, V_DUTx= 0.0 V

DUTGND VOLTAGE ACCURACY

−7

Over 0.1 V range; measured at the end points of VCH

and VCL functional range

NORMAL WINDOW COMPARATOR

VOH tests done with VOL = −2.0 V, VOL tests done with VOH = 6.0 V, unless otherwise specified.

Table 4.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DC SPECIFICATIONS

Input Voltage Range

Differential Voltage Range

−2.0

0.1

+6.0

8.0

V

D

Comparator Input Offset Voltage

Accuracy, Uncalibrated

−150

30

+150

mV

P

Offset measured at calibration points of 0 V and 5 V

Comparator Threshold Resolution

0.61

1

mV

P_F

After two-point gain/offset calibration; range/

number of DAC bits as measured at calibration

points of 0 V and 5 V

Comparator Threshold DNL

Comparator Threshold INL

1

1.2

mV

C_T

P

After two-point gain/offset calibration

After two-point gain/offset calibration; measured

over VOH, VOL range of −2.0 V to +6.0 V

−7

+7

Comparator Input Offset Voltage

Tempco

200

ꢀV/°C C_T

Measured at calibration points

Rev. A | Page 7 of 58

ADATE302-02

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DUTGND Voltage Accuracy

−7

0.5

+7

mV

P

Over 0.1 V range; measured at end points of VOH

and VOL functional range

Comparator Uncertainty Range

5.3

mV

C_B

V_DUTx= 0 V, sweep comparator threshold to

determine uncertainty region

DC Hysteresis

DC PSRR

0.5

5

mV

mV/V C_T

C_B

V_DUTx= 0 V

Measured at calibration points

Digital Output Characteristics

Internal Pull-Up Resistance to

Comparator, COMP_VTTx Pin

46

1

50

54

Ω

P

Pull 1 mA and 10 mA from Logic 1 leg and measure

ΔV to calculate resistance; measured ΔV/9 mA; done

for both comparator logic states

V_{COMP_VTTx}Range

Common-Mode Voltage

1.5

V_{COMP_VTTx}

− 0.3

3.3

V

D

C_T

Measured with 100 Ω differential termination

Measured with no external termination

V_{COMP_VTTx}

− 0.5

V_{COMP_VTTx}

V

P

Differential Voltage

250

500

222

mV

ps

C_T

P

C_B

Measured with 100 Ω differential termination

Measured with no external termination

Measured with each comparator leg terminated

50 Ω to GND

450

550

Rise/Fall Time, 20% to 80%

AC SPECIFICATIONS

Input transition time = 600 ps, 10% to 90%;

measured with each comparator leg terminated

50 Ω to GND; unless otherwise specified

Propagation Delay, Input to Output

1.4

4

ns

C_B

V_DUTx= 0 V to 1.0 V swing, driver VTERM mode,

VT = 0.0 V; high-side measurement: VOH = 0.5 V,

VOL = −2.0 V; low-side measurement: VOH = 6.0 V,

VOL = 0.5 V

V_DUTx= 0 V to 0.9 V swing, driver VTERM mode,

VT = 0.0 V; VOL = VOH = 0.45 V

V_DUTx= 0 V to 1.0 V swing, driver VTERM mode,

VT = 0.0 V; high-side measurement: VOH = 0.5 V,

VOL = −2.0 V; low-side measurement: VOH = 6.0 V,

VOL = 0.5 V

Propagation Delay Tempco

Propagation Delay Matching

ps/°C C_T

High Transition to Low Transition

High to Low Comparator

39

30

ps

C_B

Propagation Delay Change with

Respect to

Slew Rate, 600 ps and 1 ns

(10% to 90%)

19

65

ps

C_B

V_DUTx= 0 V to 0.5 V swing, driver VTERM mode,

VT = 0.0 V; high-side measurement: VOH = 0.25 V,

VOL = −2.0 V; low-side measurement: VOH = 6.0 V,

VOL = 0.25 V

Overdrive, 250 mV and 1.0 V

For 250 mV: V_DUTx= 0 V to 0.5 V swing; for 1.0 V: V_DUTx=

0 V to 1.25 V swing; driver VTERM mode, VT = 0.0 V;

high-side measurement: VOH = 0.25 V, VOL = −2.0 V;

low-side measurement: VOH = 6.0 V, VOL = 0.25 V;

input transition time = 400 ps (10%/90%)

Pulse Width, 1 ns, 5 ns, 10 ns, and

15 ns

27

ps

C_B

V_DUTx= 0 V to 1.0 V swing @ 32.0 MHz, driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.5 V,

VOL = −2.0 V; low-side measurement: VOH = 6.0 V,

VOL = 0.5 V; input transition time = 400 ps (10%/90%)

V_DUTx= 0 V to 1.0 V swing @ 1.0 MHz, driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.5 V,

VOL = −2.0 V; low-side measurement: VOH = 6.0 V,

VOL = 0.5 V; input transition time = 400 ps (10%/90%)

Duty Cycle, 5% to 95%

11.8

Rev. A | Page 8 of 58

ADATE302-02

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

Minimum Pulse Width

1

ns

C_B

V_DUTx= 0 V to 1.0 V swing, driver VTERM mode,

VT = 0.0 V; less than 10% amplitude degradation

measured by shmoo; input transition time = 400 ps

(10%/90%)

Input Equivalent Bandwidth,

Terminated

1000

0.9

MHz

ns

C_B

V_DUTx= 0 V to 1.0 V swing, driver VTERM mode,

VT = 0.0 V; as measured by shmoo; input transition

time = 400 ps (10%/90%)

V_DUTx= 0 V to 3.0 V swing, driver high-Z; as measured

by shmoo

ERT High-Z Mode, 3 V, 20% to 80%

DIFFERENTIAL COMPARATOR

VOH tests done with VOL = −1.1 V, VOL tests done with VOH = 1.1 V, unless otherwise specified.

Table 5.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DC SPECIFICATIONS

Input Voltage Range

Operational Differential Voltage

Range

−1.5

0.05

+4.5

1.1

V

D

Maximum Differential Voltage Range

8

V

D

Comparator Input Offset Voltage

Accuracy, Uncalibrated

−150

25

+150

mV

P

Offset measured at differential calibration points of

+1 V and −1 V, with common mode = 0 V

VOH, VOL Resolution

0.61

1

mV

P_F

After two-point gain/offset calibration; range/number of

DAC bits as measured at differential calibration points of

+1 V and −1 V, with common mode = 0 V

VOH, VOL DNL

VOH, VOL INL

1

mV

C_T

P

After two-point gain/offset calibration; common mode =

0 V

After two-point gain/offset calibration; measured over

VOH, VOL range of −1.1 V to +1.1 V, common mode = 0 V

−7

1.0

+7

VOH, VOL Offset Voltage Tempco

Comparator Uncertainty Range

200

18

ꢀV/°C C_T

Measured at calibration points

V_DUTx= 0 V, sweep comparator threshold to determine

uncertainty region

mV

C_B

DC Hysteresis

CMRR

0.5

mV

mV/V

C_B

P

V_DUTx= 0 V

1

Offset measured at common-mode voltage points of

−1.5 V and +4.5 V, with differential voltage = 0 V

DC PSRR

15

mV/V C_T

Measured at calibration points

AC SPECIFICATIONS

Input transition time = 600 ps, 10% to 90%, measured

with each comparator leg terminated 50 Ω to GND

Propagation Delay, Input to Output

1.4

ns

C_B

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V,

VOL = 0.0 V; repeat for other DUT channel

Propagation Delay Tempco

Propagation Delay Matching

4

ps/°C C_T

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, driver VTERM

mode, VT = 0.0 V; VOL = VOH = 0.0 V; repeat for other DUT

channel

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V,

VOL = 0.0 V; repeat for other DUT channel

High Transition to Low Transition

High to Low Comparator

27

32

ps

C_B

Propagation Delay Change with

Respect to

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V,

Rev. A | Page 9 of 58

ADATE302-02

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

VOL = 0.0 V; repeat for other DUT channel

Slew Rate, 400 ps and 1 ns

(10% to 90%)

25

ps

C_B

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V,

VOL = 0.0 V; repeat for other DUT channel

V_DUT0= 0 V, for 250 mV: V_DUT1= 0 V to 0.5 V swing;

for 750 mV: V_DUT1= 0 V to 1.0 V swing, driver VTERM mode,

VT = 0.0 V; VOH = −0.25 V; repeat for other DUT channel

with comparator threshold = 0.25 V

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing @ 32 MHz,

driver VTERM mode, VT = 0.0 V; high-side measurement:

VOH = 0.0 V, VOL = −1.1 V; low-side measurement:

VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing @ 32 MHz, driver

VTERM mode, VT = 0.0 V; high-side measurement:

VOH = 0.0 V, VOL = −1.1 V; low-side measurement:

VOH = 1.1 V, VOL = 0.0 V; repeat for other DUT channel

Overdrive, 250 mV and 750 mV

79

56

16

1

ps

ns

Pulse Width, 1 ns, 5 ns, 10 ns, and

15 ns

Duty Cycle, 5% to 95%

Minimum Pulse Width

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V,

VOL = 0.0 V; less than 22% amplitude degradation

measured by shmoo; repeat for other DUT channel

Input Equivalent Bandwidth,

Terminated

500

MHz

C_B

V_DUT0= 0 V, V_DUT1= −0.5 V to +0.5 V swing, driver VTERM

mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,

VOL = −1.1 V; low-side measurement: VOH = 1.1 V,

VOL = 0.0 V

Rev. A | Page 10 of 58

ADATE302-02

ACTIVE LOAD

See Table 30 for load control information.

Table 6.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DC SPECIFICATIONS

Input Characteristics

VCOM Voltage Range

V_DUTxRange

Load active on, RCVx pins active, unless otherwise noted

−1.75

−2.0

−200

+5.75

+6.0

+200

V

mV

D

P

VCOM Accuracy, Uncalibrated

25

IOH = IOL = 6 mA, VCOM error measured at calibration

points of 0 V and 5 V

VCOM Resolution

0.61

1

mV

P_F

IOH = IOL = 6 mA, after two-point gain/offset

calibration; range/number of DAC bits as measured at

calibration points of 0 V and 5 V

VCOM DNL

VCOM INL

1

2

mV

C_T

P

IOH = IOL = 6 mA, after two-point gain/offset calibration

−7

+7

IOH = IOL = 6 mA, after two-point gain/offset

calibration; measured over VCOM range of −1.75 V to

+5.75 V

Over 0.1 V range; measured at end points of VCOM

functional range

DUTGND Voltage Accuracy

1

mV

P

Output Characteristics

IOL

Maximum Source Current

Uncalibrated Offset

12

−600.0

mA

ꢀA

D

P

100

+600.0

+12

2

IOH = 0 mA, VCOM = 1.5 V, V_DUTx= 0.0 V, IOL offset

calculated from calibration points of 1 mA and 11 mA

IOH = 0 mA, VCOM = 1.5 V, V_DUTx= 0.0 V, IOL gain

Uncalibrated Gain

Resolution

−12

1

%

P

calculated from calibration points of 1 mA and 11 mA

1.5

ꢀA

P_F

IOH = 0 mA, VCOM = 1.5 V, V_DUTx= 0.0 V, after two-point

gain/offset calibration; range/number of DAC bits as

measured at calibration points of 1 mA and 11 mA

DNL

INL

3.0

ꢀA

C_T

P

IOH = 0 mA, VCOM = 1.5 V, V_DUTx= 0.0 V, after two-

point gain/offset calibration

IOH = 0 mA, VCOM = 1.5 V, V_DUTx= 0.0 V, after two-

point gain/offset calibration; measured over IOL range

of 0 mA to 12 mA

−70

20

+70

0.25

90% Commutation Voltage

V

P

IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOL

reference at V_DUTx= −1.0 V, measure IOL current at

V_DUTx= 1.75 V, ensure >90% of reference current

IOH

Maximum Sink Current

Uncalibrated Offset

12

−600.0

mA

ꢀA

D

P

100

1

+600.0

+12

2

IOL = 0 mA, VCOM = 1.5 V, V_DUTx= 3.0 V, IOH offset

calculated from calibration points of 1 mA and 11 mA

IOL = 0 mA, VCOM = 1.5 V, V_DUTx= 3.0 V, IOH gain

Uncalibrated Gain

Resolution

−12

%

P

calculated from calibration points of 1 mA and 11 mA

1.5

ꢀA

P_F

IOL = 0 mA, VCOM = 1.5 V, V_DUTx= 3.0 V, after two-point

gain/offset calibration; range/number of DAC bits as

measured at calibration points of 1 mA and 11 mA

DNL

INL

3.0

20

ꢀA

C_T

P

IOL = 0 mA, VCOM = 1.5V, V_DUTx= 3.0 V, after two-point

gain/offset calibration

IOL = 0 mA, VCOM = 1.5V, V_DUTx= 3.0 V, after two-point

gain/offset calibration; measured over IOH range of

0 mA to 12 mA

−70

+70

0.25

90% Commutation Voltage

Output Current Tempco

V

P

IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOH

reference at V_DUTx= 5.0 V, measure IOH current at

V_DUTx= 2.25 V, ensure >90% of reference current

1.5

ꢀA/°C

C_T

Measured at calibration points

Rev. A | Page 11 of 58

ADATE302-02

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

AC SPECIFICATIONS

Dynamic Performance

Load active on, unless otherwise noted

Propagation Delay, Load Active On

to Load Active Off; 50%, 90%

4.1

ns

C_B

Toggle RCVx pins, DUTx terminated 50 Ω to GND,

IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for

IOL and VCOM = −1.25 V for IOH; measured from 50%

point of RCVxP − RCVxN to 90% point of final output,

repeat for drive low and high

Toggle RCVx pins, DUTx terminated 50 Ω to GND,

IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for

IOL and VCOM = −1.25 V for IOH; measured from 50%

point of RCVxP − RCVxN to 90% point of final output,

repeat for drive low and high

Propagation Delay, Load Active Off

to Load Active On; 50%, 90%

11

ns

Propagation Delay Matching

Load Spike

6.9

156

1.6

ns

C_B

Toggle RCVx pins, DUTx terminated 50 Ω to GND,

IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for

IOL and VCOM = −1.25 V for IOH; active on vs. active

off, repeat for drive low and high

Toggle RCVx pins, DUTx terminated 50 Ω to GND,

IOH = IOL = 0 mA, VH = VL = 0 V, VCOM = +1.25 V for

IOL and VCOM = −1.25 V for IOH; repeat for drive low

and high

Toggle RCVx pins, DUTx terminated 50 Ω to GND,

IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for

IOL and VCOM= −1.25 V for IOH; measured at 90% of

final value

mV

ns

Settling Time to 90%

PMU

FV = force voltage, MV = measure voltage, FI = force current, MI = measure current, FN = force nothing.

Table 7.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

FORCE VOLTAGE (FV)

Current Range A

Current Range B

Current Range C

Current Range D

Current Range E

25

2

200

20

2

−2.0

mA

ꢀA

V

D

Force Input Voltage Range at

Output For All Ranges

+6.0

Force Voltage Uncalibrated

Accuracy for Range C

Force Voltage Uncalibrated

Accuracy for All Ranges

Force Voltage Offset Tempco

for All Ranges

Force Voltage Gain Tempco

for All Ranges

−100

25

75

2

+100 mV

mV

P

PMU enabled, FV, PE disabled, error measured at calibration

points of 0 V and 5 V

PMU enabled, FV, PE disabled, error measured at calibration

points of 0 V and 5 V; repeat for each PMU current range

Measured at calibration points for each PMU current range

C_T

ꢀV/°C

ppm/°C C_T

Measured at calibration points for each PMU current range

Forced Voltage INL

−7

+7

mV

P

PMU enabled, FV, Range C, PE disabled, after two-point gain/

offset calibration; measured over output range of −2.0 V to

+6.0 V

Force Voltage Compliance vs.

Current Load

PMU enabled, FV, PE disabled, force −2.0 V, measure voltage

while PMU sinking zero- and full-scale current; measure ꢁV;

force 6.0 V, measure voltage while PMU sourcing zero- and full-

scale current; measure ꢁV; repeat for each PMU current range

Range A

Range B to Range E

4

1

mV

C_T

Rev. A | Page 12 of 58

ADATE302-02

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

Current Limit, Source and Sink

Range A

108

135

180

% FS

P

PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx

to 6.0 V; source: force 2.5 V, short DUTx to −1.0 V;

Range A FS = 25 mA, 108% FS = 27 mA, 180% FS = 45 mA

PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx to

6.0 V; source: force 2.5 V, short DUTx to −1.0 V; repeat for each

PMU current range; example: Range B FS = 2 mA,

120% FS = 2.4 mA, 180% FS = 3.6 mA

Over 0.1 V range; measured at end points of FV functional

range

Range B to Range E

120

−7

140

1

180

+7

% FS

mV

DUTGND Voltage Accuracy

MEASURE CURRENT (MI)

P

V_DUTxexternally forced to 0.0 V, unless otherwise specified;

ideal MEASOUT transfer functions:

V_MEASOUT01[V] = (I_MEASOUT01× 5/FSR) + 2.5 + V_DUTGND

I(V_MEASOUT01) [A] = (V_MEASOUT01− V_DUTGND− 2.5) × FSR/5

Measure Current, Pin DUTx

Voltage Range for All Ranges

−2.0

+6.0

V

D

Measure Current Uncalibrated

Accuracy

Range A

Range B

Range C

Range D

Range E

650

ꢀA

C_T

P

PMU enabled, FIMI, PE disabled, error at calibration points of

−20 mA and 20 mA, error = (I(V_MEASOUT01) − I_DUTx

PMU enabled, FIMI, PE disabled, error at calibration points of

−1.6 mA and 1.6 mA, error = (I(V_MEASOUT01) − I_DUTx

PMU enabled, FIMI, PE disabled, error at calibration points of

80% FS, error = (I(V_MEASOUT01) − I_DUTx

PMU enabled, FIMI, PE disabled, error at calibration points of

80% FS, error = (I(V_MEASOUT01) − I_DUTx

PMU enabled, FIMI, PE disabled, error at calibration points of

)

−400

20

+400 ꢀA

)

2.00

0.20

0.02

ꢀA

C_T

)

80% FS, error = (I(V_MEASOUT01) − I_DUTx

)

Measure Current Offset Tempco

Range A

Range B

Range C

Range D and Range E

2.5

125

20

4

ꢀA/°C

C_T

Measured at calibration points

nA/°C

Measure Current Gain Error,

Nominal Gain = 1

Range A

−3.5

%

C_T

P

PMU enabled, FIMI, PE disabled, gain error from calibration

points of 80% FS

PMU enabled, FIMI, PE disabled, gain error from calibration

points of 1.6 mA

PMU enabled, FIMI, PE disabled, gain error from calibration

points of 80% FS

Range B

−20

2

+20

Range C to Range E

C_T

Measure Current Gain Tempco

Range A

Range B to Range E

Measure Current INL

Range A

Measured at calibration points

300

50

ppm/°C C_T

0.05

% FSR

% FSR/V

mV

C_T

P

PMU enabled, FIMI, PE disabled, after two-point gain/offset

calibration, measured over FSR output of −25 mA to +25 mA

PMU enabled, FIMI, PE disabled, after two-point gain/

offset calibration measured over FSR output of −2 mA to +2 mA

PMU enabled, FIMI, PE disabled, after two-point gain/offset

calibration; measured over FSR output

PMU enabled, FVMI, PE disabled, force −1 V and +5 V into load

of 1 mA; measure ꢁI reported at MEASOUT01

Over 0.1 V range; measured at end points of MI functional

range

Range B

−0.02

−0.01

0.005 0.02

0.005

Range B to Range E

C_T

P

FVMI DUT Pin Voltage Rejection

DUTGND Voltage Accuracy

0.01

2.5

C_T

Rev. A | Page 13 of 58

ADATE302-02

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

FORCE CURRENT (FI)

V_DUTxexternally forced to 0.0 V, unless otherwise specified

Ideal force current transfer function:

_FORCE= (PMUDAC − 2.5) × (FSR/5)

I

Force Current, DUTx Pin Voltage −2.0

Range for All Ranges

Force Current Uncalibrated

Accuracy

+6.0

+5.0

V

D

Range A

Range B

Range C

Range D

Range E

−5.0

−400

−40

−4

0.5

40

4

mA

P

PMU enabled, FIMI, PE disabled, error at calibration points of

−20 mA and +20 mA

PMU enabled, FIMI, PE disabled, error at calibration points of

−1.6 mA and +1.6 mA

PMU enabled, FIMI, PE disabled, error at calibration points of

80% FS

PMU enabled, FIMI, PE disabled, error at calibration points of

80% FS

+400 ꢀA

+40

+4

ꢀA

0.4

75

−400

+400 nA

PMU enabled, FIMI, PE disabled, error at calibration points of

80% FS

Force Current Offset Tempco

Range A

Range B

Range C to Range E

Forced Current Gain Error,

Nominal Gain = 1

1

80

4

ꢀA/°C

C_T

P

Measured at calibration points

PMU enabled, FIMI, PE disabled, gain error from calibration

points of 80% FS

nA/°C

%

−20

4

+20

Forced Current Gain Tempco

Range A

Range B to Range E

Force Current INL

Range A

Measured at calibration points

−500

75

ppm/°C C_T

−0.3

-0.2

0.05

+0.3

% FSR

P

PMU enabled, FIMI, PE disabled, after two-point gain/offset

calibration; measured over FSR output of

−25 mA to +25 mA

PMU enabled, FIMI, PE disabled, after two-point gain/offset

calibration; measured over FSR output

Range B to Range E

0.015 0.2

Force Current Compliance vs.

Voltage Load

PMU enabled, FIMV, PE disabled; force positive full-scale

current driving −2.0 V and +6.0 V, measure ꢁI @ DUTx pin;

force negative full-scale current driving −2.0 V and +6.0 V,

measure ꢁI @ DUTx pin

Range A to Range D

Range E

−0.6

−1.0

0.06

+ 0.1

+0.6

+1.0

% FSR

P

MEASURE VOLTAGE

Measure Voltage Range

Measure Voltage Uncalibrated

Accuracy

−2.0

−25

+6.0

+25

V

mV

D

P

2.0

PMU enabled, FVMV, Range B, PE disabled, error at calibration

points of 0 V and 5 V, error = (V_MEASOUT01− V_DUTx

)

Measure Voltage Offset Tempco

Measure Voltage Gain Error

10

0.01

ꢀV/°C

%

C_T

P

Measured at calibration points

PMU enabled, FVMV, Range B, PE disabled, gain error from

calibration points of 0 V and 5 V

−2

+2

Measure Voltage Gain Tempco

Measure Voltage INL

25

1

ppm/°C C_T

Measured at calibration points

−7

+7

mV

P

PMU enabled, FVMV, Range B, PE disabled, after two-point

gain/offset calibration; measured over output range of −2.0 V

to +6.0 V

Rejection of Measure V vs. I_DUTx

−1.5

0.1

+1.5

mV

P

PMU enabled, FVMV, Range D, PE disabled, force 0 V into load

of −10 ꢀA and +10 ꢀA; measure ꢁV reported at MEASOUT01

Rev. A | Page 14 of 58

ADATE302-02

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

MEASOUT01 DC CHARACTERISTICS

MEASOUT01 Voltage Range

DC Output Current

MEASOUT01 Pin Output

Impedance

−2.0

+6.0

4

200

V

mA

Ω

D

P

25

PMU enabled, FVMV, PE disabled; source resistance: PMU force

6.0 V and load with 0 mA and 4 mA; sink resistance: PMU force

−2.0 V and load with 0 mA and −4 mA; resistance = ꢁV/ꢁI at

MEASOUT01 pin

Output Leakage Current When

Tristated

Output Short-Circuit Current

−1

+1

ꢀA

P

Tested at −2.0 V and +6.0 V

−25

+25

mA

PMU enabled, FVMV, PE disabled; source: PMU force 6.0 V,

short MEASOUT01 to −2.0 V; sink: PMU force −2.0 V, short

MEASOUT01 to 6.0 V

VOLTAGE CLAMPS

Low Clamp Range (VCL)

High Clamp Range (VCH)

Positive Clamp Voltage Droop

−2.0

0.0

−300 +50

+4.0

6.0

V

D

P

+300 mV

+250 mV

PMU enabled, FIMI, Range A, PE disabled, PMU clamps

enabled, VCH = 5 V, VCL = −1 V, PMU force 1 mA and 25 mA

into open; ꢁV seen at DUTx pin

PMU enabled, FIMI, Range A, PE disabled, PMU clamps

enabled, VCH = 5 V, VCL = −1 V, PMU force −1 mA and −25 mA

into open; ꢁV seen at DUTx pin

PMU enabled, FIMI, Range B, PE disabled, PMU damps enabled,

PMU force 1 mA into open; VCH errors at calibration points of

0 V and 5 V; VCL errors at the calibration points of 0 V and 4 V

PMU enabled, FIMI, Range B, PE disabled, PMU damps enabled,

PMU force 1 mA into open; after two-point gain/offset

calibration; measured over PMU clamp range

Negative Clamp Voltage Droop

Uncalibrated Accuracy

INL

−300 −50

P

−250

−70

100

P

5

1

+70

mV

P

DUTGND Voltage Accuracy

SETTLING/SWITCHING TIMES

C_T

Over 0.1 V range; measured at end points of PMU clamp

functional range

SCAP = 330 pF, FFCAP = 220 pF

Voltage Force Settling Time to

0.1% of Final Value

PMU enabled, FV, PE disabled, program PMUDAC steps of

500 mV and 5.0 V; simulation of worst case, 2000 pF load,

PMUDAC step of 5.0 V

Range A, 200 pF and

2000 pF Load

Range B, 200 pF and

2000 pF Load

Range C, 200 pF and

2000 pF Load

Range D, 200 pF and

2000 pF Load

15

ꢀs

S

20

124

1015

3455

Range E, 200 pF and

2000 pF Load

Voltage Force Settling Time to

1.0% of Final Value

PMU enabled, FV, PE disabled, start with PMUDAC

programmed to 0.0 V, program PMUDAC to 500 mV

Range A, 200 pF and

2000 pF Load

Range B, 200 pF and

2000 pF Load

Range C, 200 pF and

2000 pF Load

8.0

ꢀs

C_B

Range D, 200 pF Load

Range D, 2000 pF Load

Range E, 200 pF Load

Range E, 2000 pF Load

8.1

585

8.1

ꢀs

C_B

590

Rev. A | Page 15 of 58

ADATE302-02

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

Voltage Force Settling Time to

1.0% of Final Value

PMU enabled, FV, PE disabled, start with PMUDAC

programmed to 0.0 V, program PMUDAC to 5.0 V

Range A, 200 pF and

2000 pF Load

4.2

ꢀs

C_B

Range B, 200 pF Load

Range B, 2000 pF Load

Range C, 200 pF Load

Range C, 2000 pF Load

Range D, 200 pF Load

Range D, 2000 pF Load

Range E, 200 pF Load

Range E, 2000 pF Load

4.4

7.6

6.3

8.1

130

280

390

605

ꢀs

C_B

Current Force Settling Time to

0.1% of Final Value

PMU enabled, FI, PE disabled, start with PMUDAC

programmed to 0 current, program PMUDAC to FS current

Range A, 200 pF in Parallel

with 120 Ω

Range B, 200 pF in Parallel

with 1.5 kΩ

Range C, 200 pF in Parallel

with 15.0 kΩ

Range D, 200 pF in Parallel

with 150 kΩ

8.2

ꢀs

S

9.4

30

281

2668

Range E, 200 pF in Parallel

with 1.5 MΩ

Current Force Settling Time to

1.0% of Final Value

PMU enabled, FI, PE disabled, start with PMUDAC

programmed to 0 current, program PMUDAC to FS current

Range A, 200 pF in Parallel

with 120 Ω

Range B, 200 pF in Parallel

with 1.5 kΩ

Range C, 200 pF in Parallel

with 15.0 kΩ

Range D, 200 pF in Parallel

with 150 kΩ

3.3

4.4

8

ꢀs

C_B

205

505

Range E, 200 pF in Parallel

with 1.5 MΩ

INTERACTION AND CROSSTALK

Measure Voltage Channel-to-

Channel Crosstalk

0.125

% FSR

C_T

PMU enabled, FIMV, PE disabled, Range B, forcing 0 mA into

0 V load; other channel: Range A, forcing a step of 0 mA to 25 mA

into 0 V load; report ꢁV of MEASOUT01 pin under test;

0.125% × 8.0 V = 10 mV

PMU enabled, FVMI, PE disabled, Range E, forcing 0 V into

0 mA current load; other channel: Range E, forcing a step of 0 V

to 5 V into 0 mA current load; report ꢁV of MEASOUT01 pin

under test; 0.01% × 5.0 V = 0.5 mV

Measure Current Channel-to-

Channel Crosstalk

0.01

EXTERNAL SENSE (PMUS_CHx)

Table 8.

Test

Parameter

Min

Typ

Max

+6.0

+20

Unit

Level Conditions/Comments

Voltage Range

Input Leakage Current

−2.0

−20

V

nA

D

P

Tested at −2.0 V and +6.0 V

Rev. A | Page 16 of 58

ADATE302-02

DUTGND INPUT

Table 9.

Test

Parameter

Min

Typ

Max

+0.1

100

Unit

V

μA

Level Conditions/Comments

Input Voltage Range, Referenced to GND

Input Bias Current

−0.1

D

P

1

Tested at −100 mV and +100 mV

SERIAL PERIPHERAL INTERFACE

Table 10.

Test

Parameter

Min

Typ

Max

Unit

V

μA

MHz

ns

mV

V

Level Conditions/Comments

P_F

Serial Input Logic High

Serial Input Logic Low

Input Bias Current

SCLK Clock Rate

1.8

0

−10

V_CC

0.7

+10

+1

50

9

P

Tested at 0.0 V and 3.3 V

P_F

C_T

C_B

P_F

D

SCLK Pulse Width

SCLK Crosstalk on DUTx Pin

Serial Output Logic High

Serial Output Logic Low

Update Time

8

PE disabled, PMU FV enabled and forcing 0 V

Sourcing 2 mA

Sinking 2 mA

Maximum delay time required for the part to enter

a stable state after a serial bus command is loaded

V_CC− 0.4

0

V_CC

0.8

V

μs

10

HVOUT DRIVER

Table 11.

Test

Parameter

Min

Typ

Max

V_PLUS− 3.25

Unit

Level Conditions/Comments

VHH BUFFER

Voltage Range

VHH = (VT + 1 V) × 2 + DUTGND

5.9

V

D

P

V_PLUS= 16.75 V nominal; in this condition,

_HVOUTmaximum = 13.5 V

V

Output High

13.5

V

VHH mode enabled, RCVx pins active, VHH level = full

scale, sourcing 15 mA

VHH mode enabled, RCVx pins active, VHH level = zero

scale, sinking 15 mA

VHH mode enabled, RCVx pins active, V_HVOUTerror

measured at calibration points of 7 V and 12 V

Measured at calibration points

VHH mode enabled, RCVx pins active, after two-point

gain/offset calibration; range/number of DAC bits as

measured at calibration points of 7 V and 12 V

VHH mode enabled, RCVx pins active, after two-point gain/

offset calibration; measured over VHH range of 5.9 V to 13.5 V

Over 0.1 V range; measured at end points of VHH

functional range

VHH mode enabled, RCVx pins active, source: VHH = 10.0 V,

Output Low

5.9

100 +500

V

Accuracy Uncalibrated

−500

−30

mV

Offset Tempco

Resolution

1

1.21

mV/°C

mV

C_T

P_F

1.5

INL

15

1

+30

mV

Ω

P

DUTGND Voltage Accuracy

Output Resistance

C_T

P

1

10

I

_HVOUT= 0 mA and 15 mA; sink: VHH = 6.5 V, I_HVOUT= 0 mA

and −15 mA; ꢁV/ꢁI

DC Output Current Limit Source

DC Output Current Limit Sink

60

100

−60

mA

ns

P

VHH mode enabled, RCVx pins active, VHH = 10.0 V, short

HVOUT pin to 5.9 V, measure current

VHH mode enabled, RCVx pins active, VHH = 6.5 V, short

HVOUT pin to 14.1 V, measure current

VHH mode enabled, toggle RCVx pins, VHH = 13.5 V, VL =

VH = 3.0 V; 20% to 80%, for DATAx high and DATAx low

−100

P

Rise Time (From VL or VH to

VHH)

175

C_B

Rev. A | Page 17 of 58

ADATE302-02

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

Fall Time (From VHH to VL or VH)

23

ns

C_B

VHH mode enabled, toggle RCVx pins, VHH = 13.5 V, VL =

VH = 3.0 V; 20% to 80%, for DATAx high and DATAx low

Preshoot, Overshoot, and

Undershoot

100

mV

C_B

VHH mode enabled, toggle RCVx pins, VHH = 13.5 V, VL =

VH = 3.0 V; for DATAx high and DATAx low

VL/VH BUFFER

Voltage Range

Accuracy Uncalibrated

−0.1

−500

+6.0

100 +500

V

mV

D

P

VHH mode enabled, RCVx pins inactive, error measured at

calibration points of 0 V and 5 V

Offset Tempco

Resolution

1

0.61

mV/°C

mV

C_T

P_F

Measured at calibration points

0.75

+20

VHH mode enabled, RCVx pins inactive, after two-point

gain/offset calibration; range/number of DAC bits as

measured at calibration points of 0 V and 5 V

VHH mode enabled, RCVx pins inactive, after two-point

gain/offset calibration; measured over range of −0.1 V to

+6.0 V

Over 0.1 V range; measured at end points of VH and VL,

functional range

VHH mode enabled, RCVx pins inactive, source: VH = 3.0 V,

INL

−20

46

4

mV

P

DUTGND Voltage Accuracy

Output Resistance

2

mV

Ω

C_T

P

48

50

I

_HVOUT= 1 mA and 50 mA; sink: VL = 2.0 V, I_HVOUT= −1 mA

and −50 mA; ꢁV/ꢁI

DC Output Current Limit Source

DC Output Current Limit Sink

Rise Time (VL to VH)

60

100

−60

mA

ns

P

VHH mode enabled, RCVx pins inactive, VH = 6.0 V, short

HVOUT pin to −0.1 V, DATAx high, measure current

VHH mode enabled, RCVx pins inactive, VL = −0.1 V, short

HVOUT pin to 6.0 V, DATAx low, measure current

VHH mode enabled, RCVx pins inactive, VL = 0.0 V,

VH = 3.0 V, toggle DATAx pins; 20% to 80%

VHH mode enabled, RCVx pins inactive, VL = 0.0 V,

VH = 3.0 V, toggle DATAx pins; 20% to 80%

−100

P

10.0

11.3

54

C_B

Fall Time (VH to VL)

ns

Preshoot, Overshoot, and

Undershoot

mV

VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,

toggle DATAx pins

OVERVOLTAGE DETECTOR (OVD)

Table 12.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DC CHARACTERISTICS

Programmable Voltage Range

Accuracy Uncalibrated

−3.0

−200

+7.0

+200

V

mV

D

P

OVD offset errors measured at programmed levels of

7.0 V and −3.0 V

Hysteresis

112

mV

C_B

LOGIC OUTPUT CHARACTERISTICS

Off State Leakage

10

1000

0.7

nA

V

P

Disable OVD alarm, apply 3.3 V to OVD_CHx pin,

measure leakage current

Activate alarm, force 100 μA into OVD_CHx, measure

active alarm voltage

For OVD high: DUTx = 0 V to 6 V swing, OVD_CHx high =

3.0 V, OVD_CHx low = −3.0 V; for OVD_CHx low:

DUTx = 0 V to 6 V swing, OVD_CHx high = 7.0 V,

OVD_CHx low = 3.0 V

Maximum On Voltage @100 μA

Propagation Delay

0.2

1.8

P

μs

C_B

Rev. A | Page 18 of 58

ADATE302-02

16-BIT DAC MONITOR MUX

Table 13.

Test

Parameter

Min

Typ

Max

Unit

Level Conditions/Comments

DC CHARACTERISTICS

Programmable Voltage Range

Output Resistance

−2.5

+7.5

V

kΩ

D

C_T

16

PMUDAC = 0.0 V, FV, I = 0 μA, 200 μA; ꢁV/ꢁI

Rev. A | Page 19 of 58

ADATE302-02

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 14.

Parameter

Rating

Supply Voltages

Positive Supply Voltage (V_DDto GND)

Positive V_CCSupply Voltage (V_CCto GND)

Negative Supply Voltage (V_SSto GND)

Supply Voltage Difference (V_DDto V_SS)

Reference Ground (DUTGND to GND)

AGND to DGND

−0.5 V to +11.0 V

−0.5 V to +4.0 V

−6.25 V to +0.5 V

−1.0 V to +16.5 V

−0.5 V to +0.5 V

−0.5 V to +17.5 V

THERMAL RESISTANCE

Table 15. Thermal Resistance

VPLUS Supply Voltage (V_PLUSto GND)

Input Voltages

Package Type

θ_JA

θ_JC

Unit

Input Common-Mode Voltage

Short-Circuit Voltage¹

High Speed Input Voltage²

High Speed Differential Input Voltage³

VREF

V_SSto V_DD

−3.0 V to +8.0 V

0 to V_CC

−0.5 V to +5.5 V

84-Ball CSP_BGA

31.1

0.51

°C/W

EXPLANATION OF TEST LEVELS

D

Definition

DUTx I/O Pin Current

DCL Maximum Short-Circuit Current⁴

Temperature

Operating Temperature, Junction

Storage Temperature Range

S

Design verification simulation

100% production tested

140 mA

P

125°C

−65°C to +150°C

P_F

C_T

C_B

Functionally checked during production test

Characterized on tester

¹R_L= 0 Ω, V_DUTxcontinuous short-circuit condition (VH, VL, VT, high-Z, VCOM,

clamp modes).

²DATAxP, DATAxN, RCVxP, RCVxN, under source R = 0 Ω.

³DATAxP to DATAxN, RCVxP, RCVxN.

Characterized on bench

⁴R_L= 0 Ω, V_DUTx= −3 V to +8 V; DCL current limit. Continuous short-circuit

condition. ADATE302-02 must current limit and survive continuous short

circuit.

ESD CAUTION

Rev. A | Page 20 of 58

ADATE302-02

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

10

9

8

7

6

5

4

3

2

1

VSSO_0

(DRIVE)

VDDO_0

(DRIVE)

VDDO_1

(DRIVE)

VSSO_1

(DRIVE)

HVOUT

PMUS_CH0

DUT0

DUT1

PMUS_CH1 TEMPSENSE

A

B

C

D

E

F

VDD/VDD_

TMPSNS

VPLUS

FFCAP_0B

OVD_CH0

FFCAP_0A

AGND

SCAP0

AGND

VDD

VSS

AGND

VSS

VDD

AGND

VSS

SCAP1

DATA0N

DATA0P

RCV0N

RCV0P

DATA1N

DATA1P

RCV1N

RCV1P

AGND

VDD

FFCAP_1B

OVD_CH1

FFCAP_1A

AGND

VSS

AGND

COMP_VTT1 COMP_QL1N COMP_QL1P

COMP_QL0P COMP_QL0N COMP_VTT0

G

H

J

VSS

RST

VCC

VDD

SDIN

SCLK

VDD

DGND

SDOUT

VSS

DAC16_MON

CS

AGND

COMP_QH1N COMP_QH1P

COMP_QH0P COMP_QH0N

AGND

VREF

MEASOUT01/

TEMPSENSE

K

VREF_GND

AGND

DUTGND

Figure 2. 84-Ball BGA Pin Configuration, Bottom Side (BGA Balls Are Visible)

Table 16. Pin Function Descriptions

BGA Designator

Mnemonic

TEMPSENSE

PMUS_CH1

VSSO_1 (Drive)

DUT1

VDDO_1 (Drive)

VDDO_0 (Drive)

DUT0

VSSO_0 (Drive)

PMUS_CH0

HVOUT

Description

Temperature Sense Output

PMU External Sense Path Channel 1

Driver Output Supply −5.75 V Channel 1

Device Under Test Channel 1

Driver Output Supply +10.0 V Channel 1

Driver Output Supply +10.0 V Channel 0

Device Under Test Channel 0

Driver Output Supply −5.75 V Channel 0

PMU External Sense Path Channel 0

High Voltage Driver Output

Temperature Sense Supply +10.0 V

PMU Stability Capacitor Connection Channel 1 (330 pF)

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

B1

B2

VDD/VDD_TMPSNS

SCAP1

Rev. A | Page 21 of 58

ADATE302-02

BGA Designator

Mnemonic

VSS

Description

Supply −5.75 V

B3

B4

B5

B6

B7

B8

B9

B10

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

D1

D2

D3

D8

D9

D10

E1

AGND

VDD

AGND

VSS

SCAP0

VPLUS

FFCAP_1B

AGND

DATA1N

VSS

VDD

VSS

DATA0N

AGND

FFCAP_0B

OVD_CH1

VDD

DATA1P

DATA0P

VDD

OVD_CH0

FFCAP_1A

VSS

Analog Ground

Supply +10.0 V

Analog Ground

Supply −5.75 V

PMU Stability Capacitor Connection Channel 0 (330 pF)

Supply +16.75 V

PMU Feedforward Capacitor Connection B Channel 1 (220 pF)

Analog Ground

Driver Data Input (Negative) Channel 1

Supply −5.75 V

Supply +10.0 V

Supply −5.75 V

Driver Data Input (Negative) Channel 0

Analog Ground

PMU Feedforward Capacitor Connection B Channel 0 (220 pF)

Overvoltage Detection Flag Output Channel 1

Supply +10.0 V

Driver Data Input (Positive) Channel 1

Driver Data Input (Positive) Channel 0

Supply +10.0 V

Overvoltage Detection Flag Output Channel 0

PMU Feedforward Capacitor Connection A Channel 1 (220 pF)

Supply −5.75 V

E2

E3

E8

E9

RCV1N

RCV0N

VSS

Receive Data Input (Negative) Channel 1

Receive Data Input (Negative) Channel 0

Supply −5.75 V

E10

F1

FFCAP_0A

AGND

PMU Feedforward Capacitor Connection A Channel 0 (220 pF)

Analog Ground

F2

AGND

Analog Ground

F3

F8

F9

RCV1P

RCV0P

AGND

Receive Data Input (Positive) Channel 1

Receive Data Input (Positive) Channel 0

Analog Ground

F10

G1

G2

G3

G8

G9

G10

H1

H2

H3

H4

H5

H6

H7

H8

AGND

Analog Ground

COMP_QL1P

COMP_QL1N

COMP_VTT1

COMP_VTT0

COMP_QL0N

COMP_QL0P

COMP_QH1P

COMP_QH1N

AGND

VSS

VDD

VSS

Low-Side Comparator Output (Positive) Channel 1

Low-Side Comparator Output (Negative) Channel 1

Comparator Supply Termination Channel 1

Comparator Supply Termination Channel 0

Low-Side Comparator Output (Negative) Channel 0

Low-Side Comparator Output (Positive) Channel 0

High-Side Comparator Output (Positive) Channel 1

High-Side Comparator Output (Negative) Channel 1

Analog Ground

Supply −5.75 V

Supply +10.0 V

Supply −5.75 V

AGND

Analog Ground

Rev. A | Page 22 of 58

ADATE302-02

BGA Designator

Mnemonic

COMP_QH0N

COMP_QH0P

AGND

Description

H9

H10

J1

High-Side Comparator Output (Negative) Channel 0

High-Side Comparator Output (Positive) Channel 0

Analog Ground

J2

AGND

Analog Ground

J3

AGND

Analog Ground

J4

J5

DAC16_MON

DGND

16-Bit DAC Monitor Mux Output

Digital Ground

J6

J7

SDIN

RST

Serial Peripheral Interface (SPI) Data In

Serial Peripheral Interface (SPI) Reset

Analog Ground

J8

AGND

J9

AGND

Analog Ground

J10

K1

AGND

Analog Ground

MEASOUT01/TEMPSENSE

Muxed Output Shared by PMU MEASOUT Channel 0, PMU MEASOUT Channel 1,

Temperature Sense and Temperature Sense GND Reference

K2

K3

K4

K5

K6

K7

K8

K9

K10

DUTGND

AGND

CS

DUT Ground Reference

Analog Ground

Serial Peripheral Interface (SPI) Chip Select

Serial Peripheral Interface (SPI) Data Out

Serial Peripheral Interface (SPI) Clock

Supply +3.3 V

Analog Ground

+5 V DAC Reference Voltage

DAC Ground Reference

SDOUT

SCLK

VCC

AGND

VREF

VREF_GND

Rev. A | Page 23 of 58

ADATE302-02

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

75

74

NC

1

NC

PIN 1

2

73 HVOUT

TEMPSENSE

3

72

VPLUS

4

VDD/VDD_TMPSNS

SCAP1

71

SCAP0

5

70

FFCAP_0B

6

FFCAP_1B

VDD

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VDD

7

OVD_CH0

DATA0N

8

OVD_CH1

DATA1N

9

DATA0P

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

DATA1P

FFCAP_1A

VSS

FFCAP_0A

VSS

ADATE302-02

TOP VIEW

(Not to Scale)

RCV0N

RCV1N

RCV0P

RCV1P

AGND

COMP_QL0P

COMP_QL0N

COMP_VTT0

COMP_QH0P

COMP_QH0N

COMP_QL1P

COMP_QL1N

COMP_VTT1

COMP_QH1P

COMP_QH1N

AGND

NC

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

NOTES

1. NC = NO CONNECT.

2. EXPOSED PAD IS CONNEC TED TO V

.

SS

Figure 3. 100-Lead TQFP_EP Pin Configuration

Table 17. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

2

3

4

5

6

7

NC

No Connect. No physical connection to die.

Temperature Sense Output.

TEMPSENSE

VDD/VDD_TMPSNS

SCAP1

FFCAP_1B

VDD

Temperature Sense Supply +10.0 V.

PMU Stability Capacitor Connection Channel 1 (330 pF).

PMU Feed Forward Capacitor Connection B Channel 1 (220 pF).

Supply +10.0 V.

8

9

10

11

12

OVD_CH1

DATA1N

DATA1P

FFCAP_1A

VSS

Overvoltage Detection Flag Output Channel 1.

Driver Data Input (Negative) Channel 1.

Driver Data Input (Positive) Channel 1.

PMU Feedforward Capacitor Connection A Channel 1 (220 pF).

Supply −5.75 V.

Rev. A | Page 24 of 58

ADATE302-02

Pin No.

13

14

Mnemonic

RCV1N

RCV1P

Description

Receive Data Input (Negative) Channel 1.

Receive Data Input (Positive) Channel 1.

Analog Ground.

15

AGND

16

17

18

19

20

21

COMP_QL1P

COMP_QL1N

COMP_VTT1

COMP_QH1P

COMP_QH1N

AGND

Low-Side Comparator Output (Positive) Channel 1.

Low-Side Comparator Output (Negative) Channel 1.

Comparator Supply Channel 1.

High-Side Comparator Output (Positive) Channel 1.

High-Side Comparator Output (Negative) Channel 1.

Analog Ground.

22

AGND

Analog Ground.

23

AGND

Analog Ground.

24

25

26

27

NC

No Connect. No physical connection to die.

28

MEASOUT01/TEMP SENSE

Shared Muxed Output. Muxed output shared by PMU MEASOUT Channel 0, PMU

MEASOUT Channel 1, and the temperature sense and temperature sense GND

reference.

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

DUTGND

AGND

CS

Device Under Test Ground Reference.

Analog Ground.

Serial Peripheral Interface (SPI®) Chip Select.

16-Bit DAC Monitor Mux Output.

Supply −5.75 V.

Supply +10.0 V.

Digital Ground.

Serial Programmable Interface (SPI) Data Output.

Serial Programmable Interface (SPI) Clock.

Serial Programmable Interface (SPI) Data Input.

Supply +10.0 V.

Supply +3.3 V.

Supply −5.75 V.

Serial Peripheral Interface (SPI) Reset.

Analog Ground.

+5 V DAC Reference Voltage.

DAC Ground Reference.

No Connect. No physical connection to die.

Analog Ground.

DAC16_MON

VSS

VDD

DGND

SDOUT

SCLK

SDIN

VDD

VCC

VSS

RST

AGND

VREF

VREF_GND

NC

AGND

Comp_QH0N

Comp_QH0P

Comp_VTT0

Comp_QL0N

Comp_QL0P

Analog Ground.

High-Side Comparator Output (Negative) Channel 0.

High-Side Comparator Output (Positive) Channel 0.

Comparator Supply Channel 0.

Low-Side Comparator Output (Negative) Channel 0.

Low-Side Comparator Output (Positive) Channel 0.

Rev. A | Page 25 of 58

ADATE302-02

Pin No.

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

EP

Mnemonic

AGND

RCV0P

RCV0N

VSS

FFCAP_0A

DATA0P

DATA0N

OVD_CH0

VDD

FFCAP_0B

SCAP0

VPLUS

HVOUT

NC

PMUS_CH0

VSS

VDD

VSSO_0 (DRIVE)

DUT0

VDDO_0 (DRIVE)

AGND

VSS

VDD

AGND

VDD

VSS

AGND

VDDO_1 (DRIVE)

DUT1

VSSO_1 (DRIVE)

VDD

VSS

PMUS_CH1

NC

Description

Analog Ground.

Receive Data Input (Positive) Channel 0.

Receive Data Input (Negative) Channel 0.

Supply −5.75 V.

PMU Feedforward Capacitor Connection A Channel 0 (220 pF).

Driver Data Input (Positive) Channel 0.

Driver Data Input (Negative) Channel 0.

Overvoltage Detection Flag Output Channel 0.

Supply +10.0 V.

PMU Feedforward Capacitor Connection B Channel 0 (220 pF).

PMU Stability Capacitor Connection Channel 0 (330 pF).

Supply +16.75 V.

High Voltage Driver Output.

No Connect. No physical connection to die.

PMU External Sense Path Channel 0.

Supply −5.75 V.

Supply +10.0 V.

Driver Output Supply −5.75 V Channel 0.

Device Under Test Channel 0.

Driver Output Supply +10.0 V Channel 0.

Analog Ground.

Supply −5.75 V.

Supply +10.0 V.

Analog Ground.

Supply +10.0 V.

Supply −5.75 V.

Analog Ground.

Driver Output Supply +10.0 V Channel 1.

Device Under Test Channel 1.

Driver Output Supply −5.75 V Channel 1.

Supply +10.0 V.

Supply −5.75 V.

PMU External Sense Path Channel 1.

No Connect. No physical connection to die.

Exposed Pad. The exposed pad is connected to V_SS.

Rev. A | Page 26 of 58

ADATE302-02

TYPICAL PERFORMANCE CHARACTERISTICS

0.30

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

0.5V

0.25

0.20

0.15

0.2V

0.10

0.05

0

–0.2

0

2

4

6

8

10

12

14

16

18

0

2

4

6

8

10

12

14

16

18

TIME (ns)

Figure 4. Driver Small Signal Response;

VH = 0.2 V, 0.5 V; VL = 0.0 V; 50 Ω Termination

Figure 7. 100 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V;

50 Ω Termination

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–0.2

0

1

2

3

4

5

6

7

8

9

10

0

2

4

6

8

10

12

14

16

18

TIME (ns)

Figure 5. Driver Large Signal Response;

VH = 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V; 50 Ω Termination

Figure 8. 300 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V;

50 Ω Termination

6

5

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

4

3

2

1

0

–1

0

2

4

6

8

10

12

14

16

18

0

1

2

3

4

5

6

7

8

9

TIME (ns)

Figure 6. Driver Large Signal Response; VH = 1.0 V, 3.0 V, 5.0 V; VL = 0.0 V;

500 Ω Termination

Figure 9. 400 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V;

50 Ω Termination

Rev. A | Page 27 of 58

ADATE302-02

1.2

1.0

0.8

0.6

0.4

0.2

0

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–0.2

0

2

4

6

8

10

12

14

16

18

20

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

TIME (ns)

Figure 13. Driver Active (VH/VL) to/from VTERM Transition;

VH = 2.0 V; VT = 1.0 V; VL = 0.0 V

Figure 10. 500 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V;

50 Ω Termination

1.6

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–0.2

0

2

4

6

8

10

12

14

16

18

20

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

TIME (ns)

Figure 11. 600 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V; VL = 0.0 V;

50 Ω Termination

Figure 14. Driver Active (VH/VL) to/from VTERM Transition;

VH = 3.0 V; VT = 1.5 V; VL = 0.0 V

0.6

0.5

0.4

0.3

0.2

0.1

0

10

0

NEGATIVE PULSE

–10

–20

–30

–40

–50

POSITIVE PULSE

0

2

4

6

8

10

12

14

16

18

1

10

TIME (ns)

PULSE WIDTH (ns)

Figure 15. Driver Minimum Pulse Width;

VH = 0.2 V; VL = 0.0 V

Figure 12. Driver Active (VH/VL) to/from VTERM Transition;

VH = 1.0 V; VT = 0.5 V; VL = 0.0 V

Rev. A | Page 28 of 58

ADATE302-02

10

0

10

0

NEGATIVE PULSE

–10

–20

–30

–40

–50

–10

–20

–30

–40

–50

POSITIVE PULSE

1

10

1

10

PULSE WIDTH (ns)

Figure 16. Driver Minimum Pulse Width;

VH = 0.5 V; VL = 0.0 V

Figure 19. Driver Minimum Pulse Width;

VH = 3.0 V; VL = 0.0 V

10

0

1.5

1.0

0.5

0

NEGATIVE PULSE

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–10

–20

–30

POSITIVE PULSE

10

–2

–1

0

1

2

3

4

5

6

PULSE WIDTH (ns)

DRIVER OUTPUT VOLTAGE (V)

Figure 17. Driver Minimum Pulse Width;

VH = 1.0 V; VL = 0.0 V

Figure 20. Driver VH Linearity Error

10

0

2.0

1.5

1.0

0.5

NEGATIVE PULSE

0

–0.5

–1.0

–1.5

–2.0

–2.5

–10

–20

–30

POSITIVE PULSE

10

–2

–1

0

1

2

3

4

5

6

PULSE WIDTH (ns)

DRIVER OUTPUT VOLTAGE (V)

Figure 18. Driver Minimum Pulse Width;

VH = 2.0 V; VL = 0.0 V

Figure 21. Driver VL Linearity Error

Rev. A | Page 29 of 58

ADATE302-02

2.0

1.5

0.2

0

1.0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–2

–1

0

1

2

3

4

5

6

–2

–1

0

1

2

3

4

5

6

60

6

DRIVER OUTPUT VOLTAGE (V)

PROGRAMMED VH DAC LEVEL (V)

Figure 22. Driver VT Linearity Error

Figure 25. Driver Interaction Error;

VL = −2.0 V; VH Swept from −1.9 V to +6.0 V

1.4

53

52

51

50

49

48

47

1.2

1.0

0.8

0.6

0.4

0.2

0

–0.2

–2

–1

0

1

2

3

4

–60

–40

–20

0

20

40

PROGRAMMED VL DAC LEVEL (V)

DRIVER OUTPUT CURRENT (mA)

Figure 23. Driver Interaction Error;

Figure 26. Driver Output Resistance vs. Output Current

VH = 6.0 V; VL Swept from −2.0 V to +5.9 V

0.6

0.5

0.4

0.3

0.2

0.1

0

120

100

80

60

40

20

0

–0.1

–2

–1

0

1

2

3

4

–2

–1

0

1

2

3

4

5

PROGRAMMED VH DAC LEVEL (V)

V

(V)

DUTx

Figure 24. Driver Interaction Error;

VT = 1.5 V; VH Swept from −1.9 V to +6.0 V

Figure 27. Driver Output Current Limit;

Driver Programmed to −2.0 V; V_DUTxSwept from −2.0 V to +6.0 V

Rev. A | Page 30 of 58

ADATE302-02

6

4

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

2

0

–2

–4

–6

–8

–10

–12

6

–1

5

7

8

9

10

11

12

13

14

–2

–1

0

1

2

3

4

5

6

VHH PROGRAMMED VOLTAGE (V)

V

(V)

DUTx

Figure 31. HVOUT VHH Linearity Error

Figure 28. Driver Output Current Limit;

Driver Programmed to 6.0 V; V_DUTxSwept from −2.0 V to +6.0 V

90

80

70

60

50

40

30

20

10

0

16

14

12

10

8

6

4

2

0

1

2

3

4

5

6

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

V

(V)

HVOUT

TIME (µs)

Figure 32. HVOUT VH Current Limit;

VH = −0.1 V; V_HVOUTSwept from −0.1 V to +6.0 V

Figure 29. HVOUT VHH Response;

VHH = 13.5 V

100

80

3

2

60

1

40

0

20

0

–1

–2

–3

–4

–20

–40

–60

–80

6

7

8

9

10

11

(V)

12

13

14

15

0

1

2

3

4

5

6

V

VL PROGRAMMED VOLTAGE (V)

HVOUT

Figure 33. HVOUT VHH Current Limit;

VHH = 10.0 V; V_HVOUTSwept from 5.9 V to 14.1 V

Figure 30. HVOUT VL Linearity Error

Rev. A | Page 31 of 58

ADATE302-02

1.1

1.0

0.9

0.8

0.7

0.6

30

25

20

15

10

5

INPUT VOLTAGE SWING = 1V

COMPARATOR THRESHOLD = 0.5V

INPUT RISING EDGE

INPUT EDGE

SHMOO

0.5

0.4

0.3

0.2

0.1

0

INPUT FALLING EDGE

–0.1

0

1.2

2.4

TIME (ns)

3.6

4.8

6.0

0.4

0.6

0.8

1.0

INPUT SLEW RATE [10%/90%] (ns)

Figure 34. Comparator Shmoo;

1.0 V Swing; 200 ps (10%/90%)

Figure 37.Comparator Slew Rate Dispersion

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

COMP_QH0P

INPUT EDGE

SHMOO

COMP_QH0N

–0.1

0

1.2

2.4

TIME (ns)

3.6

4.8

6.0

TIME (ns)

Figure 35. Comparator Shmoo;

1.0 V Swing; 200 ps (10%/90%)

Figure 38. Comparator Output Waveform; COMP_QH0P, COMP_QH0N

0.4

0.2

10

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

POSITIVE PULSE

–10

–20

–30

NEGATIVE PULSE

–2

–1

0

1

2

3

4

5

6

1

10

PULSE WIDTH (ns)

PROGRAM THRESHOLD VOLTAGE (V)

Figure 39. Comparator Threshold Linearity

Figure 36. Comparator Minimum Pulse Width Input;

1.0 V Swing; 200 ps (10%/90%)

Rev. A | Page 32 of 58

ADATE302-02

0.2

0

8

6

4

–0.2

–0.4

–0.6

–0.8

–1.0

2

0

–2

–4

–6

–2

–1

0

1

2

3

4

5

0

2

4

6

8

10

12

INPUT COMMON-MODE VOLTAGE (V)

ACTIVE LOAD CURRENT (mA)

Figure 40. Differential Comparator CMRR

Figure 43. Active Load Current Linearity

3

0

0.8

0.6

DRIVER ACTIVE LOW (VL)

TO/FROM FULL LOAD CURRENT

0.4

0.2

–3

0

–6

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–9

–12

–15

FULL LOAD CURRENTTO/FROM

DRIVER ACTIVE LOW (VL)

0

10

20

30

40

50

–2

–1

0

1

2

3

4

5

6

TIME (ns)

VCOM VOLTAGE (V)

Figure 41. Active Load Response

Figure 44. Active Load VCOM Linearity

15

10

5

5.5

5.0

4.5

4.0

3.5

3.0

2.5

0

–5

–10

–15

–2

–1

0

1

2

3

4

5

6

–2

–1

0

1

2

3

4

5

6

V

(V)

V

(V)

DUTx

Figure 42. Active Load Commutation Response;

VCOM = 2.0 V; IOH = IOL = 12 mA

Figure 45. DUTx Pin Leakage Current in Low Leakage Mode

Rev. A | Page 33 of 58

ADATE302-02

6

30

20

4

10

0

2

–10

–20

–30

–40

–50

–60

–70

0

–2

–4

–6

–2

–1

0

1

2

3

4

5

6

–30

–20

–10

0

10

20

30

V

(V)

PMU OUTPUT CURRENT (mA)

DUTx

Figure 49. PMU Force Current Range A Linearity

Figure 46. DUTx Pin Leakage Current in High-Z Mode

0.5

0.4

0.5

0.4

0.3

0.2

0.1

0

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

0

–0.1

–0.2

–0.3

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

–0.20 –0.15 –0.10 –0.05

0

0.05

0.10

0.15

0.20

PMU OUTPUT CURRENT (mA)

DUTGND VOLTAGE (mV)

Figure 47. DUTGND Voltage Effects

Figure 50. PMU Force Current Range B Linearity

0.04

0.03

0.02

0.01

0

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–0.01

–0.02

–0.03

–0.04

–0.05

–0.20 –0.15 –0.10 –0.05

0

0.05

0.10

0.15

0.20

–3

–2

–1

0

1

2

3

4

5

6

7

PMU OUTPUT CURRENT (mA)

PMU OUTPUT VOLTAGE (V)

Figure 51. PMU Force Current Range C Linearity

Figure 48. PMU Force Voltage Linearity

Rev. A | Page 34 of 58

ADATE302-02

0.004

0.003

0.002

0.001

0

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.001

–0.002

–0.003

–0.004

–0.005

–0.020 –0.015 –0.010 –0.005

0

0.005 0.010 0.015 0.020

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

PMU OUTPUT CURRENT (mA)

I

(mA)

DUTx

Figure 52. PMU Force Current Range D Linearity

Figure 55. PMU Force Voltage Range B Output Voltage Error at −2.0 V vs.

Output Current

0.0004

0.0002

0

4

3

2

1

–0.0002

–0.0004

–0.0006

–0.0008

0

–1

–2

–3

–4

–0.0020 –0.0015 –0.0010 –0.0005

0

0.0005 0.0010 0.0015 0.0020

–25 –20 –15 –10

–5

0

5

10

15

20

25

PMU OUTPUT CURRENT (mA)

I

(mA)

DUTx

Figure 53. PMU Force Current Range E Linearity

Figure 56. PMU Force Voltage Range A Output Voltage Error at 6.0 V vs.

Output Current

0.6

0.4

4

3

2

0.2

1

0

–1

–2

–3

–4

–0.2

–0.4

–0.6

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

–25 –20 –15 –10

–5

0

5

10

15

20

25

I

(mA)

I

(mA)

DUTx

Figure 54. PMU Force Voltage Range B Output Voltage Error at 6.0 V vs.

Output Current

Figure 57. PMU Force Voltage Range A Output Voltage Error at −2.0 V vs.

Output Current

Rev. A | Page 35 of 58

ADATE302-02

2

1.0

0.8

0.6

0.4

0.2

0

–2

–4

–6

–8

–10

–0.2

–0.4

–2

–1

0

1

2

3

4

5

6

–2

–1

0

1

2

3

4

5

6

V

(V)

V

(V)

DUTx

Figure 58. PMU Force Current Range A Output Current Error at −25 mA vs.

Output Voltage

Figure 61. PMU Force Current Range B Output Current Error at 2 mA vs.

Output Voltage; Output Voltage Is Pulled Externally

10

0

0.004

0.003

0.002

0.001

0

–10

–20

–30

–40

–50

–60

–0.001

–0.002

–2

–1

0

1

2

3

4

5

6

–2

–1

0

1

2

3

4

5

6

V

(V)

V

(V)

DUTx

Figure 59. PMU Force Current Range A Output Current Error at 25 mA vs.

Output Voltage; Output Voltage Is Pulled Externally

Figure 62. PMU Force Current Range E Output Current Error at −2 μA vs.

Output Voltage; Output Voltage Is Pulled Externally

0.0035

0.0030

0.0025

0.0020

0.0015

0.0010

0.0005

0

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.0005

–0.0010

–2

–1

0

1

2

3

4

5

6

–2

–1

0

1

2

3

4

5

6

V

(V)

V

(V)

DUTx

Figure 63. PMU Force Current Range E Output Current Error at 2 μA vs.

Output Voltage; Output Voltage Is Pulled Externally

Figure 60. PMU Force Current Range B Output Current Error at −2 mA vs.

Output Voltage; Output Voltage Is Pulled Externally

Rev. A | Page 36 of 58

ADATE302-02

40

30

0.20

0.15

0.10

0.05

0

20

10

0

–10

–20

–30

–40

–0.05

–0.10

–2

–1

0

1

2

3

4

5

6

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

V

(V)

I

(mA)

DUTx

Figure 64. PMU Range A Internal Current Limit, Programmed to Force 2.5 V;

_DUTxSwept from −2.0 V to +6.0 V

Figure 67. PMU Range B Measure Current Linearity

V

0.003

0.002

0.001

0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

–0.001

–0.002

–0.003

–2

–1

0

1

2

3

4

5

6

–2

–1

0

1

2

3

4

5

V

(V)

V

(V)

DUTx

Figure 65. PMU Range E Internal Current Limit, Programmed to Force 2.5 V;

_DUTxSwept from −2.0 V to +6.0 V

Figure 68. PMU Measure Current CMRR, Externally Pulling 1 mA, FVMI;

Error of MI vs. External 1 mA

V

0.05

0.04

0.03

0.02

0.01

0

–0.01

–0.02

–0.03

–0.04

1ns/DIV

–2

–1

0

1

2

3

4

5

6

V

(V)

DUTx

Figure 66. PMU Range B Measure Voltage Linearity

Figure 69. Eye Diagram, 200 Mbps, PRBS31;

VH = 1.0 V; VL = 0.0 V

Rev. A | Page 37 of 58

ADATE302-02

500ps/DIV

200ps/DIV

Figure 70. Eye Diagram, 400 Mbps, PRBS31;

VH = 1.0 V; VL = 0.0 V

Figure 73. Eye Diagram, 800 Mbps, PRBS31;

VH = 2.0 V; VL= 0.0 V

200ps/DIV

500ps/DIV

Figure 71. Eye Diagram, 400 Mbps, PRBS31;

VH = 2.0 V; VL = 0.0 V

Figure 74. Eye Diagram, 1000 Mbps, PRBS31;

VH = 1.0 V; VL = 0.0 V

200ps/DIV

Figure 72. Eye Diagram, 800 Mbps, PRBS31;

VH = 1.0 V; VL = 0.0 V

Figure 75. Eye Diagram, 1000 Mbps, PRBS31;

VH = 2.0 V; VL = 0.0 V

Rev. A | Page 38 of 58

ADATE302-02

SERIAL PERIPHERAL INTERFACE DETAILS

t_CH

SCLK

t_CL

t_CSSA

t_CSSD

t_CSHA

t_CSHD

CS

t_CSW

t_DH

t_DS

DATA[15]

DATA[14]

ADDR[1]

ADDR[0]

CH[1]

R/W

LAST

SDIN

DO_15

DO_14

DO_13

DO_12

DO_2

DO_1

DO_0

LAST

SDOUT

LAST

t

DO

Figure 76. SPI Timing Diagram

Table 18. Serial Peripheral Interface Timing Requirements

Symbol

t_CH

t_CL

t_CSHA

t_CSSA

t_CSHD

t_CSSD

t_DH

Parameter

SCLK minimum high

SCLK minimum low

Min

9.0

3.0

Max

Unit

ns

assert hold

CS

assert setup

deassert hold

deassert setup

ns

SDIN hold

SDIN setup

ns

t_DS

t_DO

t_CSW

SDOUT Data Out

15.0

ns

minimum between assertions¹

2

SCLK cycles

CS

minimum directly after a read request

3

t_CSTP

Minimum delay after is deasserted before SCLK can be

CS

16

stopped (not shown in Figure 76); this allows any internal

operations to complete

¹Extra cycle is needed after read request to prime read data into SPI shift register.

Rev. A | Page 39 of 58

ADATE302-02

DEFINITION OF SPI WORD

The SPI can take variable length words, depending on the operation. At most, the word is 24 bits longs: 16 bits of data, two channel

selects, one R/W selector, and a 5-bit address.

Depending on the operation, the data can be smaller (or nonexistent in the case of a read operation).

Example 1

Write 16 bits of data to a register or DAC; unused MSBs are ignored. For example, Bit 15 and Bit 14 are ignored, and Bit 13 through Bit 0

are applied to the 14-bit DAC.

DATA[15:0]

DATA[13:0]

DATA[1:0]

CH[1:0]

R/W

ADDR[4:0]

Figure 77.

Example 2

Write 14 bits of data to the DAC.

CH[1:0]

R/W

ADDR[4:0]

Figure 78.

Example 3a

Write two bits of data to the 2-bit register.

CH[1:0]

R/W

ADDR[4:0]

Figure 79.

Example 3b

Write two bits of data to the 2-bit register. Bit 15 through Bit 2 are ignored, while Bit 1 through Bit 0 are applied to the register.

DATA[15:0]

CH[1:0]

R/W

ADDR[4:0]

Figure 80.

Example 4

Read request and follow with a 2^ndinstruction (could be NOP) to clock out the data.

CH[1:0]

R/W = 0

ADDR[4:0]

DATA[15:0]

CH[1:0]

R/W

Figure 81.

Table 19. Channel Selection

Channel 1 Channel 0 Channel Selected

Table 20. R/W Definition

R/W

Description

0

NOP (no channel selected, no register

changes)

0

Current register specified by address is shifted out

of SDOUT on next shift operation

0

1

0

1

Channel 0 selected

Channel 1 selected

Channel 0 and Channel 1 selected

1

Current data is written to register specified by

address and channel select

Rev. A | Page 40 of 58

ADATE302-02

WRITE OPERATION

CS

INPUT

SCLK

INPUT

DATA[15] DATA[14] DATA[13]

DATA[2] DATA[1] DATA[0] CH[1]

CH[0]

17

R/W

18

ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]

X

SDIN

INPUT

0

1

2

13

14

15

16

19

20

21

22

23

24

25

SDOUT

OUTPUT

X

R/W = 1

Figure 82. 16-Bit SPI Write

CS

INPUT

SCLK

INPUT

DATA[1] DATA[0] CH[1]

CH[0]

3

R/W

4

ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]

X

SDIN

INPUT

0

1

2

5

6

7

8

9

10

11

SDOUT

OUTPUT

X

R/W = 1

Figure 83. 2-Bit SPI Write

Rev. A | Page 41 of 58

ADATE302-02

previous specified data. The NOP address can be used for this

read if there is no need to write/read another register. It is

strongly recommended that the NOP address be used for all

reads for clarity of operations.

READ OPERATION

The read operation is a two-stage operation. First, a word is

shifted in, specifying which register to read.

three clock cycles, and then a second word is shifted in to get

the readback data. This second word can be either another

operation or an NOP address. If another operation is shifted in,

it needs to shift in at least eight bits of data to read back the

CS

is deasserted for

Any register read that is less than 16 bits has zeros filled in the

top bits to make it a 16-bit word.

CS

INPUT

SCLK

INPUT

SDIN

INPUT

READ INSTRUCTION

X

NOP

X

SDOUT

OUTPUT

X

READ DATA

X

Figure 84. SPI Read Overview

CS

INPUT

SCLK

INPUT

SDIN

INPUT

ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]

DATA[15:0], VALUE IS A DON’T CARE

13 14

CH[1]

16

CH[0]

17

R/W

18

X

0

1

2

15

19

20

21

22

23

24

25

SDOUT

OUTPUT

X

Figure 85. SPI Read—Details of Read Request

CS

INPUT

SCLK

INPUT

SDIN

DATA[15:0], VALUE IS A DON’T CARE

13 14

CH[1]

16

CH[0]

17

R/W = 1

18

ADDR[4:0] = 0x00 (NOP)

X

INPUT

0

1

2

15

19

20

21

X

22

23

24

25

SDOUT

OUTPUT

RDATA[15] RDATA[14]

RDATA[2] RDATA[1] RDATA[0]

RDATA IS THE REGISTER VALUE BEING READ.

Figure 86. SPI Read—Details of Read Out

Rev. A | Page 42 of 58

ADATE302-02

RST

by utilizing the

pin. To initiate the reset operation, deassert

RESET OPERATION

The ADATE302-02 contains an asynchronous reset feature. The

ADATE302-02 can be reset to the default values shown in Table 21

RST

CS

the

pin for a minimum of 100 ns and deassert the

for a minimum of two SCLK cycles.

100ns

MINIMUM

RST

CS

SCLK

MINIMUM OF TWO SCLK EDGES AFTER ASSERTING RST BEFORE RESUMING NORMAL OPERATION.

Figure 87. Reset Operation

Rev. A | Page 43 of 58

ADATE302-02

REGISTER MAP

The ADDR[4:0] bits determine the destination register of the data being written to the ADATE302-02.

Table 21. Register Selection

Data[15:0]

N/A

CH[1:0]

N/A

R/W

N/A

R/W

R

ADDR[4:0]

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

Register Selected

NOP

VH DAC level

VL DAC level

VT/VCOM DAC level

VOL DAC level

VOH DAC level

VCH DAC level

VCL DAC level

V(IOH ) DAC level

V(IOL ) DAC level

OVD high level

OVD low level

Reset State

N/A

Data[13:0]

Data[15:0]

Data[2:0]

Data[9:0]

Data[2:0]

Data[0]

CH[1:0]

CH[1]

4096d

16384d

000b

0d

000b

0b

00b

01b

N/A

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

CH[0]

CH[1:0]

N/A

PMUDAC level

PE/PMU enable

Channel state

PMU state

PMU measure enable

Differential comparator enable

16-bit DAC monitor

OVD_CHx alarm mask

OVD_CHx alarm state

Reserved

Data[1:0]

Data[2:0]

N/A

0x13

0x14 to 0x1F

N/A

Rev. A | Page 44 of 58

ADATE302-02

DETAILS OF REGISTERS

Table 22. PE/PMU Enable (ADDR[4:0] = 0x0C)

Bit

Name

Description

Data[2]

PMU enable

0 = disable PMU force output and clamps, place PMU in MV mode

1 = enable PMU force output

When set to 0, the PMU State bits are ignored, except for PMU Sense Path (Data[7]).

Data[1]

Data[0]

Force VT

0 = normal driver operation

1 = force driver to V_T

See Table 30 for complete functionality of this bit.

0 = enable driver functions

PE disable

1 = disable driver (low leakage)

See Table 30 for complete functionality of this bit.

Table 23. Channel State (ADDR[4:0] = 0x0D)

Bit

Name

Description

Data[2]

HVOUT mode select

0 = HVOUT driver in low impedance

1 = enable HVOUT driver

This bit affects Channel 0 only. Ensure that Channel 0 bit in SPI write is active.

Channel 1 bit in SPI write is don’t care.

Data[1]

Data[0]

Load enable

0 = disable load

1 = enable load

See Table 30 for complete functionality of this bit.

0 = enable driver high-Z function

Driver high-Z/VT

1 = enable driver VTERM function

See Table 30 for complete functionality of this bit.

Table 24. PMU State (ADDR[4:0] = 0x0E)^{1, 2}

Bit

Name

Description

Data[9:8]

PMU input selection 00 = V_DUTGND(calibrated for 0.0 V voltage reference)

01 = 2.5 V + V_DUTGND(calibrated for 0.0 A current reference)

1X = PMUDAC

Data[7]

PMU sense path

0 = internal sense

1 = external sense

Data[6]

Data[5]

Reserved

PMU clamp enable

0 = disable clamps

1 = enable clamps

Data[4]

Data[3]

Data[2:0]

PMU measure V/I

PMU force V/I

PMU range

0 = measure voltage mode

1 = measure current mode

0 = force voltage mode

1 = force current mode

0XX = Range E (2 μA)

100 = Range D (20 μA)

101 = Range C (200 μA)

110 = Range B (2 mA)

111 = Range A (25 mA)

¹Note that when the ADDR[4:0] = 0x0C PMU enable bit (Data[2]) = 0, the PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage

mode. Data[9:8] and Data[6:0] of the PMU state register are ignored, and only Data[7], the PMU sense path bit, is valid.

²X = don’t care.

Rev. A | Page 45 of 58

ADATE302-02

Table 25. PMU Measure Enable (ADDR[4:0] = 0x0F)¹

Bit

Name

Description

Data[2:1]

MEASOUT01 select

00 = PMU MEASOUT Channel 0

01 = PMU MEASOUT Channel 1

10 = Temp sensor ground reference

11 = Temp sensor

Data[0]

MEASOUT01 output enable

0 = MEASOUT01 is tristated

1 = MEASOUT01 is enabled

¹This register is written to or read from if either of the CH[1:0] bits is 1.

Table 26. Differential Comparator Enable (ADDR[4:0] = 0x10)¹

Bit

Name

Description

Data[0]

Differential comparator enable

0 = differential comparator is disabled, Channel 0 normal window comparator (NWC)

outputs are on Channel 0

1 = differential comparator is enabled, the differential comparator outputs are on Channel 0

¹This register is written to or read from if either of the CH[1:0] bits is 1.

Table 27. DAC16_MON (16-Bit DAC Monitor) (ADDR[4:0] = 0x11)¹

Bit

Name

Description

Data[1]

16-bit DAC mux enable

0 = 16-bit DAC mux is tristated

1 = 16-bit DAC mux is enabled

Data[0]

16-bit DAC mux select

0 = 16-bit DAC Channel 0

1 = 16-bit DAC Channel 1

¹This register is written to or read from if either of the CH[1:0] bits is 1.

Table 28. OVD_CHx Alarm Mask (ADDR[4:0] = 0x12)

Bit

Name

Description

Data[1]

PMU mask

0 = disable PMU alarm flag

1 = enable PMU alarm flag

Data[0]

OVD mask

0 = disable OVD alarm flag

1 = enable OVD alarm flag

Table 29. OVD_CHx Alarm State (ADDR[4:0] = 0x13)¹

Bit

Name

Description

Data[2]

PMU clamp flag

0 = PMU not clamped

1 = PMU clamped

Data[1]

Data[0]

OVD high flag

OVD low flag

0 = DUT voltage < OVD high voltage

1 = DUT voltage > OVD high voltage

0 = DUT voltage > OVD low voltage

1 = DUT voltage < OVD low voltage

¹This register is a read-only register.

Rev. A | Page 46 of 58

ADATE302-02

USER INFORMATION

Table 30. Driver and Load Truth Table¹

Registers

Load Enable

Data[1]

Signals

PE Disable

Data[0]

Force VT

Data[1]

Driver High-Z/VT

Data[0]

ADDR[4:0] = 0x0C ADDR[4:0] = 0x0C ADDR[4:0] = 0x0D ADDR[4:0] = 0x0D DATAx RCVx Driver State

Load State

1

X

High-Z without Power-down

clamps

0

1

0

X

0

X

0

X

0

X

0

1

VT

VL

Power-down

High-Z with

clamps

0

1

0

1

VH

Power-down

High-Z with

clamps

0

1

0

1

0

1

0

1

0

1

VL

VT

VH

VT

VL

Power-down

Active off

High-Z with

clamps

Active on

0

1

0

1

0

1

VH

Active off

Active on

High-Z with

clamps

0

1

0

1

VL

Active on

High-Z with

clamps

0

1

0

1

VH

Active on

High-Z with

clamps

¹X = don’t care.

Table 31. HVOUT Truth Table¹

HVOUT Mode Select

Data[2]

ADDR[4:0] = 0x0D

Channel 0

RCV

Channel 0

Data

HVOUT Driver Output

1

0

1

0

X

0

1

X

VHH mode; VHH = (VT + 1 V) × 2 + DUTGND (Channel 0 VT DAC)

VL (Channel 0 VL DAC)

VH (Channel 0 VH DAC)

Disabled (HVOUT pin set to 0 V low impedance)

¹X = don’t care.

Table 32. Comparator Truth Table

Differential

Comparator Enable

Data[0]

ADDR[4:0] = 0x10

COMP_QH0

COMP_QL0

COMP_QH1

COMP_QL1

0

Normal window mode

Logic high: VOH0 < V_DUT0

Logic low: VOH0 > V_DUT0

Normal window mode

Logic high: VOL0 < V_DUT0

Logic low: VOL0 > V_DUT0

Normal window mode

Logic high: VOH1 < V_DUT1Logic high: VOL1 < V_DUT1

Logic low: VOH1 > V_DUT1Logic low: VOL1 > V_DUT1

Normal window mode

1

Differential comparator mode Differential comparator mode Normal window mode

Normal window mode

Logic high: VOH0 < V_DUT0− V_DUT1Logic high: VOL0 < V_DUT0− V_DUT1Logic high: VOH1 < V_DUT1Logic high: VOL1 < V_DUT1

Logic low: VOH0 > V_DUT0− V_DUT1

Logic low: VOL0 > V_DUT0− V_DUT1

Logic low: VOH1 > V_DUT1Logic low: VOL1 > V_DUT1

Rev. A | Page 47 of 58

ADATE302-02

There is one 16-bit DAC per channel. This DAC provides the

levels for the PMU. The output level is:

DETAILS OF DACs vs. LEVELS

There are ten 14-bit DACs per channel. These DACs provide

levels for the driver, comparator, load currents, VHH buffer, OVD,

and clamp levels. There are three versions of output levels:

•

−2.5 V to +7.5 V; tracks DUTGND. Controls PMU levels.

•

−2.5 V to +7.5 V; tracks DUTGND. Controls VH, VL,

VT/VCOM/VHH, VOH, VOL, VCH, and VCL levels.

−3.0 V to +7.0 V; tracks DUTGND. Controls OVD levels.

−2.5 V to +7.5 V; does not track DUTGND. Controls IOH

and IOL levels.

•

Table 33. Level Transfer Functions

Programmable Range¹

DAC Transfer Function

V_OUT= 2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁴)) − 0.5 × (V_REF− V_{REF_GND}) + V_DUTGND

(All 0s to All 1s)

−2.5 V to +7.5 V

Levels

VH, VL, VT/VCOM,

Code = [V_OUT− V_DUTGND+ 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁴)/(2.0 × (V_REF− V_{REF_GND}))]

V_OUT= 4.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁴)) − 1.0 × (V_REF− V_{REF_GND}) + 2.0 + V_DUTGND

Code = [V_OUT− V_DUTGND− 2.0 + 1.0 × (V_REF− V_{REF_GND})] × [(2¹⁴)/(4.0 × (V_REF− V_{REF_GND}))]

V_OUT= 2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁴)) − 0.6 × (V_REF− V_{REF_GND}) + V_DUTGND

Code = [V_OUT− V_DUTGND+ 0.6 × (V_REF− V_{REF_GND})] × [(2¹⁴)/(2.0 × (V_REF− V_{REF_GND}))]

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁴)) − 0.5 × (V_REF− V_{REF_GND})] × (0.012/5.0)

Code = [(I_OUT× (5.0/0.012)) + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁴)/(2.0 × (V_REF− V_{REF_GND}))]

V_OUT= 2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) − 0.5 × (V_REF− V_{REF_GND}) + V_DUTGND

Code = [V_OUT− V_DUTGND+ 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) − 0.5 × (V_REF− V_{REF_GND}) − 2.5] × (0.050/5.0)

Code = [(I_OUT× (5.0/0.050)) + 2.5 + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) − 0.5 × (V_REF− V_{REF_GND}) − 2.5] × (0.004/5.0)

Code = [(I_OUT× (5.0/0.004)) + 2.5 + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) − 0.5 × (V_REF− V_{REF_GND}) − 2.5] × (0.0004/5.0)

Code = [(I_OUT× (5.0/0.0004)) + 2.5 + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) − 0.5 × (V_REF− V_{REF_GND}) − 2.5] × (0.00004/5.0)

Code = [(I_OUT× (5.0/0.00004)) + 2.5 + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

I_OUT= [2.0 × (V_REF− V_{REF_GND}) × (Code/(2¹⁶)) − 0.5 × (V_REF− V_{REF_GND}) − 2.5] × (0.000004/5.0)

Code = [(I_OUT× (5.0/0.000004)) + 2.5 + 0.5 × (V_REF− V_{REF_GND})] × [(2¹⁶)/(2.0 × (V_REF− V_{REF_GND}))]

VOL, VOH, VCH, VCL

−3.0 V to +17.0 V

−3.0 V to +7.0 V

−6 mA to +18 mA

−2.5 V to +7.5 V

−50 mA to +50 mA

−4 mA to +4 mA

−400 μA to +400 μA

−40 μA to +40 μA

−4 μA to +4 μA

VHH

OVD

IOH, IOL

PMUDAC

(PMU FI Range A)

PMUDAC

(PMU FI Range B)

PMUDAC

(PMU FI Range C)

PMUDAC

(PMU FI Range D)

PMUDAC

(PMU FI Range E)

¹Programmable range includes margin outside of specified part performance, allowing for offset/gain calibration.

Table 34. Load Transfer Functions

Load Level

IOL

IOH

Transfer Function¹

V(IOL)/5 V × 12 mA

V(IOH)/5 V × 12 mA

¹V(IOH), V(IOL) DAC levels are not referenced to DUTGND.

Table 35. PMU Transfer Functions

PMU Mode

Transfer Function

Force Voltage

Measure Voltage

Force Current

Measure Current

V_OUT= PMUDAC

V_MEASOUT01= V_DUTx(internal sense) or V_MEASOUT01= V_{PMUS_CHx}(external sense)

I_OUT= [PMUDAC − (V_REF/2)]/(R¹× 5)

V_MEASOUT01= (V_REF/2) + V_DUTGND+ (I_DUTx× 5 × R¹)

¹R = 20 Ω for Range A; 250 Ω for Range B; 2.5 kΩ for Range C; 25 kΩ for Range D; 250 kΩ for Range E.

Rev. A | Page 48 of 58

ADATE302-02

Table 36. PMU User Required Capacitors

Capacitor

Location

220 pF

330 pF

Across Pin C10 (FFCAP_0B) and Pin E10 (FFCAP_0A)

Across Pin C1 (FFCAP _1B) and Pin E1 (FFCAP_1A)

Between GND and Pin B9 (SCAP0)

330 pF

Between GND and Pin B2 (SCAP1)

Table 37. Temperature Sensor

Temperature

Output

0 K

0 V

300 K

x K

3 V

(x K) × 10 mV/K

Table 38. Default Test Conditions

Name

Default Test Condition

VH DAC Level

2.0 V

VL DAC Level

0.0 V

VT/VCOM DAC Level

VOL DAC Level

1.0 V

−2.0 V

VOH DAC Level

6.0 V

VCH DAC Level

7.5 V

VCL DAC Level

−2.5 V

IOH DAC Level

0.0 A

IOL DAC Level

0.0 A

OVD Low DAC Level

OVD High DAC Level

PMUDAC DAC Level

PE/PMU Enable

Channel State

PMU State

PMU Measure Enable

Differential Comparator Enable

16-Bit DAC Monitor

OVD_CHx Alarm Mask

Data Input

−2.5 V

6.5 V

0.0 V

0x0000: PMU disabled, not force VT, PE enabled

0x0000: HVOUT mode disabled, load disabled, VTERM inactive

0x0000: input of DUTGND, internal sense, clamps disabled, FVMV, Range E

0x0000: MEASOUT01 pin tristated

0x0000: normal window comparator mode

0x0000: DAC16_MON tristated

0x0000: disable alarm functions

Logic low

Receive Input

Logic low

DUTx Pin

Unterminated

Comparator Output

Unterminated

Rev. A | Page 49 of 58

ADATE302-02

RECOMMENDED PMU MODE SWITCHING SEQUENCES

To minimize any possible aberrations and voltage spikes on the DUT output, specific mode switching sequences are recommended for the

following transitions:

•

PMU disable to PMU enable

PMU force voltage mode to PMU force current mode

PMU force current mode to PMU force voltage mode.

PMU Disable to PMU Enable

Step 1: See Table 39 for state of registers in PMU disabled mode.

Table 39.

Register

Bit

Setting

PE/PMU Enable Register, ADDR[4:0] = 0x0C

PMU State Register, ADDR[4:0] = 0x0E

Data[2]

Data[9:8]

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2:0]

0

XX

X

XXX

Step 2: Write to Register ADDR[4:0] = 0x0E (see Table 40).

Table 40.

Register

Bit

Setting

Comments

PMU State Register, ADDR[4:0] = 0x0E

Data[9:8]

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

1X or 00

Set desired input selection

X

0

This bit must be set to force voltage mode to

reduce aberrations

Data[2:0]

XXX

Set desired range

Step 3: Write to Register ADDR[4:0] = 0x0C (see Table 41).

Table 41.

Register

Bit

Setting

Comments

PE/PMU Enable Register, ADDR[4:0] = 0x0C

Data[2]

1

PMU is now enabled in force voltage mode

Rev. A | Page 50 of 58

ADATE302-02

PMU Force Voltage Mode to PMU Force Current Mode

Step 1: See Table 42 for state of registers in force voltage mode.

Table 42.

Register

Bit

Setting

PE/PMU Enable Register, ADDR[4:0] = 0x0C

PMU State Register, ADDR[4:0] = 0x0E

Data[2]

Data[9:8]

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2:0]

1

XX

X

0

XXX

Step 2: Write to Register ADDR[4:0] = 0x0E (see Table 43).

Table 43.

Register

Bit

Setting

Comments

PMU State Register, ADDR[4:0] = 0x0E

Data[9:8]

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2:0]

01

X

Set 2.5 V + V_DUTGNDinput selection

X

1

Set to force current mode

0XX

2 μA range has the minimum offset current

Step 3: Write to Register ADDR[4:0] = 0x0B (see Table 44).

Table 44.

Register

Bit

Setting

Comments

PMUDAC Level, ADDR[4:0] = 0x0B

Data[15:0]

X

Update the PMUDAC level register to the

desired value

Step 4: Write to Register ADDR[4:0] = 0x0E (see Table 45).

Table 45.

Register

Bit

Setting

Comments

PMU State Register, ADDR[4:0] = 0x0E

Data[9:8]

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2:0]

1X

X

PMUDAC input selection

1

XXX

Set to force current mode

Set to the desired current range

Rev. A | Page 51 of 58

ADATE302-02

Transition from PMU Force Current Mode to PMU Force Voltage Mode

Step 1: See Table 46 for state of registers in force current mode.

Table 46.

Register

Bits

Setting

PE/PMU Enable Register, ADDR[4:0] = 0x0C

PMU State Register, ADDR[4:0] = 0x0E

Data[2]

Data[9:8]

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2:0]

1

XX

X

1

XXX

Step 2: Write to Register ADDR[4:0] = 0x0E (see Table 47).

Table 47.

Register

Bits

Setting

Comments

PMU State Register, ADDR[4:0] = 0x0E

Data[9:8]

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2:0]

00

X

Set DUTGND input selection

0

XXX

Set to force voltage mode

Set to the desired current range

Step 3: Write to Register ADDR[4:0] = 0x0B (see Table 48).

Table 48.

Register

Bits

Setting

Comments

PMUDAC Level, ADDR[4:0] = 0x0B

Data[15:0]

X

Update the PMUDAC level register to the

desired value

Step 4: Write to Register ADDR[4:0] = 0x0E (see Table 49).

Table 49.

Register

Bits

Setting

Comments

PMU State Register, ADDR[4:0] = 0x0E

Data[9:8]

Data[7]

Data[6]

Data[5]

Data[4]

Data[3]

Data[2:0]

1X

X

PMUDAC input selection

0

XXX

Force voltage mode

Rev. A | Page 52 of 58

ADATE302-02

BLOCK DIAGRAMS

PE DISABLE DATA[0] (ADDR[4:0] = 0x0C)

FORCES SWITCH OPEN WHEN 1

VCL VCH

VH

VL

R

= 48ꢀ

OUT

(TRIMMED)

DUT

DRIVER

DATA

VT

DRIVER HIGH-Z/VT DATA[0]

(ADDR[4:0] = 0x0D)

VT BUFFER WHEN 1

HIGH-Z BUFFER WHEN 0

V(IOH)

RCV

VCOM

FORCE VT DATA[1] (ADDR[4:0] = 0x0C)

OVERRIDES THE RCV PIN AND FORCES

VTERM MODE ON THE DRIVER AND LOAD

POWER-DOWN MODE

V(IOL)

LOAD ENABLE DATA[1] (ADDR[4:0] = 0x0D)

FORCES SWITCHES OPEN AND POWERS

DOWN LOAD WHEN 0

Figure 88. Driver and Load Block Diagram

~1ꢀ

VHH = (VT + 1V) × 2 + DUTGND

HVOUT

VH

VL

48ꢀ

DATA

RCV (SHOWN IN

RCV = 0 STATE)

HV MODE SELECT DATA[2]

(ADDR [4:0] = 0x0D) DISABLES

HV DRIVER AND FORCES

0V ON HVOUT WHEN 0

Figure 89. HVOUT Driver Output Stage

Rev. A | Page 53 of 58

ADATE302-02

VOH0

–

VOH

NWC

+

DUT0

COMP_QH0

2:1

MUX

+

VOL

NWC

VOL0

VOH0

–

DIFFERENTIAL

COMPARATOR ENABLE

DATA[0] (ADDR[4:0] = 0x10)

–

VOH

DMC

COMP_QL0

2:1

MUX

+

DU T0 –

DUT0–

DUT1

DU T1

DUT1

DIFFERENTIAL

BUFFER

+

VOL

DMC

VOL0

–

NOTES

1. DIFFERENTIAL COMPARATOR ONLY ON CHANNEL 0.

Figure 90. Comparator Block Diagram

COMP_VTT

COMP_QP

50ꢀ

COMP_QN

10mA

Figure 91. Comparator Output Scheme

Rev. A | Page 54 of 58

ADATE302-02

PMU SENSE PATH DATA[7]

(ADDR[4:0] = 0x0E)

PMU MEASURE V/I DATA[4]

(ADDR[4:0] = 0x0E)

EXTERNAL DUT

SENSE PIN

MEASURE V

MEASURE I

MEASOUT01 SELECT DATA[2:1]

(ADDR[4:0] = 0x0F)

MUX

PMU FORCE V/I DATA[3]

(ADDR[4:0] = 0x0E)

MEASURE

OUT

CH[1] PMU V/I

IN-AMP G = 5

10kꢀ

TEMP SENSE

GND REF

TEMP SENSE

REF

2.5 + DUTGND

MUX

MEASOUT01 OUTPUT

ENABLE DATA[0]

(ADDR[4:0] = 0x0F)

ONE PER DEVICE

DUT

225kꢀ

22.5kꢀ

2.25kꢀ

250ꢀ

20ꢀ

2µA

20µA

200µA

25mA BUFFER

25mA

2mA

PMU INPUT SELECTION DATA[9:8]

(ADDR[4:0] = 0x0E)

MV

VIN

2.5V + DUTGND

DUTGND

FFCAP_A

FFCAP_B

330pF

SCAP

(EXTERNAL)

MUX

PMU CLAMP ENABLE DATA[5]

(ADDR[4:0] = 0x0E)

CRA = 220pF

VCH

MEASURE V

(AT OUTPUT OF

SENSE MUX)

VCL

NOTES

1. SWITCHES CONNECTED WITH DOTTED LINES REPRESENT PMU RANGE DATA[2:0] (ADDR[4:0] = 0x0E); WHEN PMU ENABLE DATA[2] = 0 (ADDR[4:0] = 0x0C), ALL

SWITCHES OPEN AND PMU POWERS DOWN.

2. THE EXTERNAL SENSE PATH MUST CLOSE THE LOOP TO ENABLE THE CLAMPS TO OPERATE CORRECTLY.

3. 25mA RANGE HAS ITS OWN OUTPUT BUFFER.

4. 25mA BUFFER WILL BE TRISTATED WHEN NOT IN USE.

Figure 92. PMU Block Diagram

Rev. A | Page 55 of 58

ADATE302-02

(ADDR[4:0] = 0x12) DATA[0]

OVD MASK ENABLES OVD

FLAGS TO ALARM OVD_CHx PIN

1

6.5V

OVD HIGH LEVEL

DAC (ADDR[4:0] = 0x0A, CH[1])

OVD_CHx

SHORT CIRCUIT

CURRENT = 100µA

DUT

ADATE302-02

1

–2.5V

OVD LOW LEVEL

DAC (ADDR[4:0] = 0x0A, CH[0])

PMU

V/I CLAMP

FLAG

(ADDR[4:0] = 0x12) DATA[1]

PMU MASK ENABLES PMU V/I

FLAG TO ALARM OVD_CHx PIN

2

(ADDR[4:0] = 0x13) DATA[2] DATA[1] DATA[0]

1

THE OVD HIGH/LOW LEVEL DAC IS SHARED BY EACH CHANNEL; THEREFORE, ONLY ONE OVD HIGH/LOW VOLTAGE

LEVEL CAN BE SET PER CHIP. THE OVD DACs PROVIDE A VOLTAGE RANGE OF –3V TO +7V. THE RECOMMENDED

HIGH/LOW SETTINGS ARE +6.5V/–2.5V. (THESE VALUES NEED TO BE PROGRAMMED BY THE USER UPON STARTUP/RESET.)

THIS IS A READ ONLY REGISTER THAT ALLOWS THE USER TO DETERMINE THE CAUSE OF THE ACTIVE OVD FLAG.

2

Figure 93. OVD Block Diagram

Rev. A | Page 56 of 58

ADATE302-02

OUTLINE DIMENSIONS

9.10

9.00 SQ

8.90

A1 BALL

CORNER

A1 BALL

CORNER

10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

6.731

REF SQ

7.20

BSC SQ

0.80

BSC

G

H

J

K

TOP VIEW

DETAIL A

BOTTOM VIEW

0.305 REF

0.90 REF

0.83

0.76

0.69

*

1.20

1.09

1.00

DETAIL A

0.36

REF

0.38

0.33

0.28

0.53

0.48

0.43

COPLANARITY

0.12

SEATING

PLANE

BALL DIAMETER

*

COMPLIANT TO JEDEC STANDARDS MO-219 WITH

EXCEPTION TO PACKAGE HEIGHT.

Figure 94. 84-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-84-2)

Dimensions shown in millimeters

16.00 BSC SQ

1.20

MAX

0.75

0.60

0.45

14.00 BSC SQ

76

100

1

75

PIN 1

8.00

BSC SQ

EXPOSED

PAD

0° MIN

1.05

1.00

0.95

0.20

0.09

TOP VIEW

(PINS DOWN)

51

25

26

7°

50

3.5°

0.15

0.05

0°

0.50 BSC

LEAD PITCH

VIEW A

0.27

0.22

0.17

SEATING

PLANE

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.08 MAX

COPLANARITY

SECTION OF THIS DATA SHEET.

VIEW A

ROTATED 90

°

CCW

COMPLIANT TO JEDEC STANDARDS MS-026-AED-HU

Figure 95. 100-Lead Thin Quad Flatpack, Exposed Pad [TQFP_EP]

(SV-100-7)

Dimensions shown in millimeters

Rev. A | Page 57 of 58

ADATE302-02

ORDERING GUIDE

Model

ADATE302-02BBCZ¹

ADATE302-02BSVZ¹

Temperature Range

−40°C to +85°C

Package Description

84-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

100-Lead Thin Quad Flatpack, Exposed Pad [TQFP_EP]

Package Option

BC-84-2

SV-100-7

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D07278-0-4/09(A)

Rev. A | Page 58 of 58


型号：	ADATE302-02BSVZ
厂家：	ADI
描述：	500 MHz Dual Integrated DCL
文件：	总59页 (文件大小：1139K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADATE302-02BSVZ [ADI]

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