ADATE209BBCZ [ADI]
4.0 Gbps Dual Driver; 4.0 Gbps的双驱动
| 型号： | ADATE209BBCZ |
| 厂家： | 
ADI |
| 描述： | 4.0 Gbps Dual Driver |
| 文件： | 总16页 (文件大小：784K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4.0 Gbps Dual Driver
ADATE209
FUNCTIONAL BLOCK DIAGRAM
FEATURES
VH1
VL1
VT1
>4.0 Gbps (2 V swings)
120 ps rise time/fall time (2 V swings)
<1.0 W for dual driver (<500 mW/channel)
−1 V to +3.5 V range
Fast termination mode (VTx)
Cable loss compensation
DA1
DROUT1
DB1
TERM1
CLC1EN
VH2
VL2
VT2
APPLICATIONS
Automatic test equipment
Semiconductor test systems
Board test systems
DA2
DROUT2
DB2
TERM2
Instrumentation and characterization equipment
High speed memory testing (DDR2/DDR3/DDR4)
HDMI testing
CLC2EN
Figure 1.
GENERAL DESCRIPTION
The ADATE209 is a dual pin driver designed for testing DDR2,
DDR3, and DDR4. It can also be used for high speed SoC applica-
tions, such as testing PCI Express 1.0 and HDMI™. The device is a
three-level driver capable of high fidelity swings from 200 mV
to 4 V over a −1 V to +3.5 V range. It has rise/fall times (20% to
80%) under 120 ps for a 2 V programmed swing and 150 ps for
a 3 V programmed swing, and is capable of supporting data
rates of 4.4 Gbps and 3.2 Gbps, respectively.
The device is capable of high speed transitions into and out of
termination mode. It also contains peaking/pre-emphasis circuitry.
The ADATE209 is available in an 8 mm × 8 mm, 49-ball
CSP_BGA.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADATE209
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Typical Performance Characteristics ..............................................9
Applications Information.............................................................. 14
Data Inputs.................................................................................. 14
Thermal Diode String................................................................ 14
Cable Loss Compensation/Peaking Circuitry ........................ 14
Default Test Conditions............................................................. 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
Explanation of Test Levels........................................................... 6
REVISION HISTORY
5/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADATE209
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 7.0 V, VEE = −4.5 V, GND = 0.0 V; all test conditions are as defined in Table 7, unless otherwise specified. All specified values are at
TJ = 70°C, where TJ corresponds to the internal temperature sensor, unless otherwise noted. Temperature coefficients are measured at TJ =
70°C 20°C, unless otherwise noted. Typical values are based on design, simulation analyses, and/or limited bench evaluations. Typical
values are not tested or guaranteed.
Table 1.
Test
Parameter
Min
Typ Max
Unit
Level1 Test Conditions/Comments
TOTAL FUNCTION
DROUTx Pin Range
−1.0
+3.5
V
I
POWER SUPPLIES
Positive Supply, VCC
Negative Supply, VEE
Data and Termination, VDAx, VDBx, VTERMx
Data and Termination, IDAx, IDBx, ITERMx
6.65
−4.73
−1
7.0
7.35
V
V
V
mA
I
I
I
I
Defines PSRR conditions
Defines PSRR conditions
−4.5 −4.28
+1.3 +3.3
40
Exceeding 40 mA through any input
termination resistor may cause damage to the
device or cause long-term reliability concerns
Positive Supply Current, ICC
Negative Supply Current, IEE
Total Power Dissipation
50
60
0.5
76
80
100
110
mA
mA
W
II
II
II
0.87 1.3
Quiescent; excludes current draw through data
input termination resistors
0.97
W
III
VLx = 0.0 V, VHx = 2.0 V; driver toggling into
open circuit; excludes current draw through
data input termination resistors
TEMPERATURE MONITORS
Temperature Sensor Gain
Temperature Sensor Offset
−4.7
3.1
III
III
mV/°C
V
Voltage reading at 30°C
DRIVER DC SPECIFICATIONS
High Speed Differential Logic Input
Characteristics (DAx, DBx, TERMx)
Input Termination Resistance
45
48
55
Ω
II
9 mA pushed into DAxB/DBxB/TERMxB signal,
0.6 V forced on DAx/DBx/TERMx signal; DAxT,
DBxT, TERMxT open; measure voltage from
DAx/DBx/ TERMx signal to DAxB/DBxB/TERMxB
signal, calculate resistance (ΔV/ΔI)
Input Voltage Differential
Common-Mode Voltage
Input Bias Current
0.25
−1.0
−10
0.8
+3.3
+1.2 +10
V
V
μA
IV
IV
II
Each pin tested at −1.0 V and +3.3 V, while other
high speed pins (DAxB, DBx, DBxB, TERMx,
TERMxB) are left open, termination pins (DAxT,
DBxT, TERMxT) open
Pin Output Characteristics
Output High Range, VHx
Output Low Range, VLx
Output Termination Range, VTx
Output High Range, VHx
Output Low Range, VLx
−0.9
−1.0
−1.0
−0.9
−1.0
−1.0
0.2
+3.5
+3.4
+3.5
+4.0
+3.9
+4.0
4.5
V
V
V
V
V
V
V
I
I
I
I
I
I
I
VCC = 7.5 V, this range is not production tested
VCC = 7.5 V, this range is not production tested
VCC = 7.5 V, this range is not production tested
Amplitude can be programmed to VHx = VLx,
accuracy specifications apply when VHx − VLx ≥
200 mV
Output Termination Range, VTx
Functional Amplitude (VHx − VLx)
DC Output Current-Limit Source
50
60
70
mA
II
Driver high, VHx = 3.5 V, short DROUTx pin to
−1.0 V, then measure current
Rev. 0 | Page 3 of 16
ADATE209
Test
Parameter
Min
Typ Max
Unit
Level1 Test Conditions/Comments
DC Output Current-Limit Sink
−70
−60 −50
mA
II
Driver high, VHx = −1.0 V, short DROUTx pin to
3.5 V, then measure current
Output Resistance, 30 mA
Absolute Accuracy
46.5
48.5 50.5
Ω
II
Source: driver high, VHx = 3.0 V, IDUT = 1 mA and
9 mA; sink: driver low, VLx = 0.0 V, IDUT = −1 mA
and −9 mA; ΔVDROUTx/ΔIDROUTx
VHx tests conducted with VLx = −1.0 V and
VTx = −1.0 V; VLx tests conducted with VHx =
3.5 V and VTx = 3.5 V; VTx tests conducted with
VLx = −1.0 V and VHx = 3.5 V
VHx, VLx, VTx Offset
−150
+20 +150 mV
II
Measured at 0.0 V, target: improve offset
VHx, VLx, VTx Offset Temperature
Coefficient
270
μV/°C
III
Measured at calibration points, 0.0 V and 2.0 V
VHx, VLx, VTx Gain
VHx, VLx, VTx Linearity
0.97
−15
1.02 1.03
2.4 +15
%FSR
mV
II
II
Relative to straight line from 0.0 V to 2.0 V
After two-point gain/offset calibration, relative
to straight line from 0.0 V to 2.0 V
VLx, VHx, VTx Interaction
0.3
mV
III
VLx = −1.0 V, VHx swept from −0.9 V to +3.5 V,
VTx swept from −1.0 V to 3.5 V,
VHx = 3.5 V, VLx swept from −1.0 V to +3.4 V,
VTx swept from −0.8 V to +3.5 V,
VTx = 1.5 V, VLx swept from −1.0 V to +3.5 V,
VHx swept from −1.0 V to +3.5 V
VHx, VLx, VTx DC PSRR
−36
−10
+24 +36
mV/V
μA
II
II
Change in output voltage as power supplies are
moved by 5%; measured at calibration points,
0.0 V and 2.0 V
VHx, VLx, VTx Input Bias Current
DRIVER AC SPECIFICATIONS
Rise/Fall Times
+1
+10
Toggle DAx inputs
0.2 V Programmed Swing
0.5 V Programmed Swing
1.0 V Programmed Swing
2.0 V Programmed Swing
3.0 V Programmed Swing
4.0 V Programmed Swing
Rise-to-Fall Matching
115
90
90
110 130
150
190
ps
ps
ps
ps
ps
ps
ps
V
V
V
II/V
V
VHx = 0.2 V, VLx = 0.0 V, terminated, 20% to 80%
VHx = 0.5 V, VLx = 0.0 V, terminated, 20% to 80%
VHx = 1.0 V, VLx = 0.0 V, terminated, 20% to 80%
VHx = 2.0 V, VLx = 0.0 V, terminated, 20% to 80%
VHx = 3.0 V, VLx = 0.0 V, terminated, 20% to 80%
VHx = 3.5V, VLx = −0.5V, terminated, 20% to 80%
90
V
V
10
VHx = 1.0 V, VLx = 0.0 V, terminated; rise to fall
within one channel
Minimum Pulse Width
Toggle both DAx and DBx inputs
0.2 V Programmed Swing
200
180
180
200
300
2.5
ps
V
V
V
V
V
V
V
V
VHx = 0.2 V, VLx = 0.0 V, terminated, timing error
less than 25 ps
VHx = 0.5 V, VLx = 0.0 V, terminated, timing error
less than 25 ps
VHx = 1.0 V, VLx = 0.0 V, terminated, timing error
less than 25 ps
VHx = 2.0 V, VLx = 0.0 V, terminated, timing error
less than 25 ps
VHx = 3.0 V, VLx = 0.0 V, terminated, timing error
less than 25 ps
VHx = 1.0 V, VLx = 0.0 V, terminated, 10%
amplitude degradation
VHx = 2.0 V, VLx = 0.0 V, terminated, 10%
amplitude degradation
VHx = 3.0 V, VLx = 0.0 V, terminated, 10%
amplitude degradation
0.5 V Programmed Swing
1.0 V Programmed Swing
2.0 V Programmed Swing
3.0 V Programmed Swing
Maximum Toggle Rate
ps
ps
ps
ps
GHz
GHz
GHz
2.2
1.8
Rev. 0 | Page 4 of 16
ADATE209
Test
Parameter
Min
Typ Max
Unit
Level1 Test Conditions/Comments
Dynamic Performance, Drive (VHx to VLx)
Propagation Delay Time
Propagation Delay Temperature
Coefficient
Toggle DAx inputs
VHx = 2.0 V, VLx = 0.0 V, terminated
VHx = 2.0 V, VLx = 0.0 V, terminated
300
660 1400 ps
0.7 ps/ºC
II/V
III
Delay Matching, Edge to Edge
Delay Change vs. Duty Cycle
15
10
ps
ps
V
V
VHx = 2.0 V, VLx = 0.0 V, terminated, rising vs. falling
VHx = 2.0 V, VLx = 0.0 V, terminated, 5% to 95%
duty cycle
Preshoot and Undershoot
Settling Time (VHx to VLx)
To Within 3% of Final Value
To Within 1% of Final Value
Rise/Fall Times (VTx to/from VHx/VLx)
1.0 V Programmed Swing
10
mV
V
VHx = 2.0 V, VLx = 0.0 V, terminated
Toggle DAx Inputs
VHx = 2.0 V, VLx = 0.0 V, terminated
VHx = 2.0 V, VLx = 0.0 V, terminated
Toggle DAx inputs
VHx = 1.0 V, VTx = 0.5V, VLx = 0.0 V, terminated,
20% to 80%
VHx = 2.0 V, VTx = 1.0 V, VLx = 0.0 V, terminated,
20% to 80%
0.4
2
ns
ns
V
V
110
170
ps
ps
V
V
2.0 V Programmed Swing
Dynamic Performance, VTERM
(VHx or VLx to/from VTx)
Toggle TERMx inputs
Propagation Delay Time
Cable Loss Compensation
Logic Control Inputs, CLCxEN
Logic High
Logic Low
ICLCxEN
Compensation Constants
Boost Time Constant
720
ns
V
VHx = 3.0 V, VTx = 1.5 V, VLx = 0.0 V, terminated
0
0.9
0
3.3
3.3
0.7
V
V
V
μA
I
IV
IV
II
−10
1.2 +10
275
18
VIN = 0.0 V and 3.3 V
ps
%
V
V
CLCxEN = 3.3 V, VHx = 1.0 V, VLx = 0.0 V,
terminated
CLCxEN = 3.3 V, VHx = 1.0 V, VLx = 0.0 V,
terminated
Boost Peaking Amplifier
1 See the Explanation of Test Levels section.
Rev. 0 | Page 5 of 16
ADATE209
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
θJA is specified for the following conditions: JEDEC 4L PCB,
50°C, and 100 LFM forced convection. θJC is specified for a 50°C
cold plate and 50°C ambient temperature.
Parameter
Rating
Supply Voltages
Positive Supply Voltage (VCC to GND)
Negative Supply Voltage (VEE to GND)
Supply Voltage Difference (VCC to VEE)
Reference Ground (DUTGND to GND)
Input Voltages
−0.5 V to +8.0 V
−5.0 V to +0.5 V
−1.0 V to +13 V
−0.5 V to +0.5 V
Table 3. Thermal Resistance
Package Type
θJA
θJC
Unit
49-Ball CSP_BGA
48.4
3.9
°C/W
Input Common-Mode Voltage
Short-Circuit Voltage (RL = 0 Ω, VDUT
Continuous Short-Circuit Condition)
VEE to VCC
−1.5 V to +4.0 V
EXPLANATION OF TEST LEVELS
I.
Definition.
High Speed Input Voltage
(Data and Termination Inputs, DAx, DBx,
and TERMx)
High Speed Differential Input Voltage
(DAx, DBx, TERMx to Termination Pin
DAxT, DBxT, TERMxT)
−1.5 V to +3.9 V
2 V
II.
III.
IV.
V.
100% Production Tested.
Characterized on Tester.
Functionally Checked During Production Test.
Characterized on Bench.
VHx, VLx, VTx
CLCxEN
−2 V to +4.5 V
−1 V to +3.5 V
ESD CAUTION
DROUTx I/O Pin Current
DCL Maximum Short-Circuit Current
(RL = 0 Ω, VDUT = −1.5 V to +4 V; DCL
Current Limit)
100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 16
ADATE209
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
GND
VEE
DROUT2
GND
DROUT1
VEE
GND
A
B
C
D
E
F
VEE
VCC
GND
VH2
VL2
GND
GND
VEE
VCC
GND
VH1
VL1
VCC
TERM1T
DA1T
TERM1
TERM1B
DA1
TERM2
TERM2B
DA2
VCC
TERM2T
DA2T
GND
GND
GND
DA1B
DB1
DA2B
DB2
GND
VCCTHERM
DB1T
DB2T
DB2B
CLC2EN
VT2
THERM
VT1
CLC1EN
DB1B
G
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
A1
A2
A3
A4
A5
A6
A7
B1
Mnemonic
Description
GND
VEE
DROUT2
GND
DROUT1
VEE
GND
TERM2
VCC
Ground.
Negative Power Supply, −4.5 V.
Driver Output, Channel 2.
Ground.
Driver Output, Channel 1.
Negative Power Supply, −4.5 V.
Ground.
Termination Mode Data Input. Noninverting input for Channel 2.
Positive Power Supply, 7.0 V.
B2
B3
VEE
Negative Power Supply, −4.5 V.
B4
GND
Ground.
B5
VEE
Negative Power Supply, − 4.5 V.
B6
VCC
Positive Power Supply, 7.0 V.
B7
TERM1
TERM2B
TERM2T
VCC
GND
VCC
TERM1T
TERM1B
DA2
DA2T
GND
Termination Mode Data Input. Noninverting input for Channel 1.
Termination Mode Data Input. Inverting input for Channel 2.
Termination Pin for Termination Mode Data Input, Channel 2.
Positive Power Supply, 7.0 V.
Ground.
Positive Power Supply, 7.0 V.
Termination Pin for Termination Mode Data Input, Channel 1.
Termination Mode Data Input. Inverting input for Channel 1.
Data Input A. Noninverting input for Channel 2.
Termination for Data Input A, Channel 2.
Ground.
C1
C2
C3
C4
C5
C6
C7
D1
D2
D3
Rev. 0 | Page 7 of 16
ADATE209
Pin No.
D4
D5
D6
D7
E1
Mnemonic
GND
GND
DA1T
DA1
DA2B
GND
Description
Ground.
Ground.
Termination for Data Input A, Channel 1.
Data Input A. Noninverting input for Channel 1.
Data Input A. Inverting input for Channel 2.
Ground.
E2
E3
VH2
VH Input, Channel 2.
E4
GND
Ground.
E5
VH1
VH Input, Channel 1.
E6
GND
Ground.
E7
F1
F2
F3
DA1B
DB2
DB2T
VL2
Data Input A. Inverting input for Channel 1.
Data Input B. Noninverting input for Channel 2.
Termination for Data Input B, Channel 2.
VL Input, Channel 2.
F4
F5
VCCTHERM
VL1
Positive Power Supply for Thermal Diode String, 7.0 V.
VL Input, Channel 1.
F6
F7
DB1T
DB1
DB2B
CLC2EN
VT2
THERM
VT1
CLC1EN
DB1B
Termination for Data Input B, Channel 1.
Data Input B. Noninverting input for Channel 1.
Data Input B. Inverting input for Channel 2.
Cable-Loss Compensation Control Pin, Channel 2.
VT Input, Channel 2.
Thermal Diode Connection.
VT Input, Channel 1.
Cable-Loss Compensation Control Pin, Channel 1.
Data Input B. Inverting input for Channel 1.
G1
G2
G3
G4
G5
G6
G7
Rev. 0 | Page 8 of 16
ADATE209
TYPICAL PERFORMANCE CHARACTERISTICS
0.30
1.2
1.0
0.8
0.6
0.4
0.2
0
0.5V
0.25
0.20
0.15
0.2V
0.10
0.05
0
CLC ENABLED
CLC DISABLED
–0.05
–0.2
TIME (ns)
TIME (ns)
Figure 3. Small Signal Response, VHx = 500 mV, 200 mV, VLx = 0.0 V
Figure 6. VHx = 2.0 V, VLx = 0.0 V, 1.5 GHz Waveform,
CLC Disabled and Enabled
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.2
1.0
0.8
0.6
0.4
0.2
0
CLC ENABLED
CLC DISABLED
–0.2
–0.2
TIME (ns)
TIME (ns)
Figure 7. VHx = 2.0 V, VLx = 0.0 V, 2.0 GHz Waveform,
CLC Disabled And Enabled
Figure 4. Large Signal Response, VHx = 3.0 V, 2.0 V, 1.0 V, VLx = 0.0 V
2.0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
CLC ENABLED
CLC DISABLED
CLC ENABLED
CLC DISABLED
1.5
1.0
0.5
0
–0.5
–0.2
TIME (ns)
TIME (ns)
Figure 8. VHx = 2.0 V, VLx = 0.0 V, 1.0 GHz Waveform,
CLC Disabled and Enabled
Figure 5. Large Signal Response, VHx = 3.0 V, 2.0 V, 1.0 V, VLx = 0.0 V,
CLC Disabled and Enabled
Rev. 0 | Page 9 of 16
ADATE209
1.2
1.0
0.8
0.6
0.4
0.2
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
CLC ENABLED
CLC DISABLED
–0.2
–0.1
–0.2
CLC ENABLED
CLC DISABLED
–0.4
TIME (ns)
TIME (ns)
Figure 9. VHx = 2.0 V, VLx = 0.0 V, 500 MHz Waveform,
CLC Disabled and Enabled
Figure 12. VHx = 1.0 V, VLx = 0.0 V, 1.0 GHz Waveform,
CLC Disabled and Enabled
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.1
–0.2
CLC ENABLED
CLC DISABLED
CLC ENABLED
CLC DISABLED
TIME (ns)
TIME (ns)
Figure 10. VHx = 1.0 V, VLx = 0.0 V, 500 MHz Waveform,
CLC Disabled and Enabled
Figure 13. VHx = 1.0 V, VLx = 0.0 V, 1.5 GHz Waveform,
CLC Disabled and Enabled
0.6
0.5
0.4
0.3
0.2
0.1
0
0.6
0.5
0.4
0.3
0.2
0.1
0
CLC ENABLED
CLC DISABLED
–0.1
–0.1
TIME (ns)
TIME (ns)
Figure 11. VHx = 1.0 V, VLx = 0.0 V, 2.0 GHz Waveform,
CLC Disabled and Enabled
Figure 14. VHx = 1.0 V, VTx = 0.5 V, VLx = 0.0 V,
Transitions Between VHx/VLx and VTx
Rev. 0 | Page 10 of 16
ADATE209
30
20
1.2
1.0
0.8
0.6
0.4
0.2
0
NEGATIVE PULSE
10
0
POSITIVE PULSE
–10
–20
–30
–0.2
0.1
1
PULSE WIDTH (ns)
10
TIME (ns)
Figure 18. 3 V Minimum Pulse Width (VHx = 3.0 V, VLx = 0.0 V), CLC Disabled
Figure 15. VHx = 2.0 V, VTx = 1.0 V, VLx = 0.0 V,
Transitions Between VHx/VLx and VTx
30
20
5
0
10
–5
NEGATIVE PULSE
POSITIVE PULSE
0
–10
50°C
–15
–10
–20
–30
70°C
–20
90°C
–25
0.1
1
10
–2
–1
0
1
2
3
4
PULSE WIDTH (ns)
VHx (V)
Figure 16. 1 V Minimum Pulse Width (VHx = 1.0 V, VLx = 0.0 V), CLC Disabled
Figure 19. Driver Linearity (VHx), VLx = −1.1 V, VTx = 1.0 V
4
30
20
3
90°C
70°C
50°C
NEGATIVE PULSE
2
10
1
POSITIVE PULSE
0
0
–10
–20
–30
–1
–2
–3
–2
–1
0
1
2
3
4
0.1
1
10
VLx (V)
PULSE WIDTH (ns)
Figure 17. 2 V Minimum Pulse Width (VHx = 2.0 V, VLx = 0.0 V), CLC Disabled
Figure 20. Driver Linearity (VLx), VHx = 3.6 V, VTx = 1.0 V
Rev. 0 | Page 11 of 16
ADATE209
1.5
3.10
3.05
3.00
2.95
2.90
2.85
2.80
2.75
2.70
90°C
1.0
0.5
70°C
0
–0.5
–1.0
–1.5
–2.0
50°C
–2.5
–3.0
–3.5
–2
–1
0
1
2
3
4
0
20
40
60
80
100
120
VTx (V)
TEMPERATURE (°C)
Figure 24. Temperature Sensor Output Voltage vs. Temperature
Figure 21. Driver Linearity (VTx), VHx = 2.0 V, VLx = 0.0 V
1.040
GAIN VHx CH1
GAIN VHx CH2
1.035
1.030
1.025
1.020
1.015
1.010
40
50
60
70
80
90
100
TEMPERATURE (°C)
200ps/DIV
Figure 22. Gain of VHx
Figure 25. VHx = 1.8 V, VLx = 0.0 V, PRBS31, 1.6 Gbps, CLC Disabled
10
5
CH2 OFFSET
CH1 OFFSET
0
–5
–10
–15
–20
–25
40
50
60
70
80
90
100
TEMPERATURE (°C)
200ps/DIV
Figure 26. VHx = 1.8 V, VLx = 0.0 V, PRBS31, 2.1 Gbps, CLC Disabled
Figure 23. Driver Offset vs. Temperature
Rev. 0 | Page 12 of 16
ADATE209
100ps/DIV
50ps/DIV
Figure 27. VHx = 1.5 V, VLx = 0.0 V, PRBS31, 3.2 Gbps, CLC Disabled
Figure 29. VHx = 0.5 V, VLx = 0.0 V, PRBS31, 5.0 Gbps, CLC Disabled
100ps/DIV
50ps/DIV
Figure 28. VHx = 1.5 V, VLx = 0.0 V, PRBS31, 4.0 Gbps, CLC Disabled
Figure 30. VHx = 0.5 V, VLx = 0.0 V, PRBS31, 5.0 Gbps, CLC Enabled
Rev. 0 | Page 13 of 16
ADATE209
APPLICATIONS INFORMATION
VCCTHERM
THERM
DATA INPUTS
40Ω
The ADATE209 contains three high speed differential inputs
for each channel. Two of the inputs, combined in an on-chip
exclusive-OR gate, control the VHx/VLx transitions. The
exclusive-OR gate can be used as a data mux or for data inversion.
The third input is used to control the transitions to the VTx level.
GND
ADATE209
Table 5. Logic Truth Table
Figure 32. Thermal Diode String Schematic
DAx
Low
High
Low
High
X1
DBx
Low
Low
High
High
X1
TERMx
DROUTx
CABLE LOSS COMPENSATION/PEAKING
CIRCUITRY
Low
Low
Low
Low
VL
VH
VH
VL
VT
The ADATE209 has two different CLC/peaking modes: nominal
and boost. In nominal mode, a small amount of high frequency
energy is injected in the driver output signal to compensate for
high frequency losses in the test interface. In boost mode, a
much larger percentage of high frequency energy is injected in
the driver output signal. The two modes are controlled through
the CLCxEN signal.
High
1 X = don’t care.
The high speed inputs are designed to be compatible with most
types of differential inputs. Each side of the differential inputs is
terminated through 50 Ω to a common point. For connection to
PECL inputs, connect the DAxT/DBxT/TERMxT input
termination to VCC − 2.0 V (VCC of the input signal, not of the
ADATE209) or to an appropriate resistor to ground. For connec-
tion to LVDS, do not connect DAxT/DBxT/TERMxT. For
connection to CML signals, either leave DAxT/DBxT/TERMxT
open or connect DAxT/DBxT/TERMxT to the appropriate
Table 6.
CLCxEN
CLC/Peaking Mode
Nominal
Boost
Logic low
Logic high
For applications using very short path lengths, very high fidelity
cables and connectors, and/or lower data rates, nominal mode
should be used. For applications using lower fidelity cables and
connectors (and often lower cost) and/or at higher data rates,
use boost mode.
V
CC/VDD level.
DAxT, DBxT,
TERMxT
DEFAULT TEST CONDITIONS
50Ω
50Ω
Table 7 lists the default test conditions.
DAx, DBx,
TERMx
Table 7.
Name
DB1/DB1B
DAxB, DBxB,
TERMxB
Default Test Condition
Figure 31. Input Termination Schematic Diagram
Logic high
Logic high
1.3 V
2.0 V
0.0 V
DB2/DB2B
DA1T/DA2T/DB1T/DB2T
VHx
VLx
VTx
THERMAL DIODE STRING
Figure 32 shows a simplified schematic of the thermal diode
string. To use the diode string, connect VCCTHERM to 7.0 V
and measure the voltage at THERM. The nominal gain of the
thermal diode string is −4.7 mV/°C.
1.0 V
Rev. 0 | Page 14 of 16
ADATE209
OUTLINE DIMENSIONS
8.10
8.00 SQ
7.90
A1 BALL
CORNER
3.275
REF
A1 BALL
CORNER
7
6
5
4
3
2
1
A
B
C
D
E
F
6.00
BSC SQ
3.225
REF
1.00
BSC
G
BOTTOM VIEW
0.305 REF
TOP VIEW
DETAIL A
DETAIL A
*
1.60 MAX
1.21 NOM
0.60
0.56
0.52
0.100 REF
0.55
0.50
0.45
0.68
0.63
0.58
COPLANARITY
0.10
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT TO JEDEC STANDARDS MO-192-ABB-1 WITH
EXCEPTION TO PACKAGE HEIGHT.
Figure 33. 49-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-49-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADATE209BBCZ1
Temperature Range
−40°C to +85°C
Package Description
Package Option
49-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
BC-49-4
1 Z = RoHS Compliant Part.
Rev. 0 | Page 15 of 16
ADATE209
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07277-0-5/08(0)
Rev. 0 | Page 16 of 16
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