ADATE304 [ADI]
200 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH; 200 MHz双通道集成DCL与电平设置的DAC ,每个引脚PMU和每个芯片VHH型号: | ADATE304 |
厂家: | ADI |
描述: | 200 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH |
文件: | 总52页 (文件大小:1202K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
200 MHz Dual Integrated DCL with Level
Setting DACs, Per Pin PMU, and Per Chip VHH
ADATE304
FEATURES
GENERAL DESCRIPTION
Driver
The ADATE304 is a complete, single-chip solution that performs
3-level driver with high-Z mode and built-in clamps
Precision trimmed output resistance
Low leakage mode (typically <10 nA)
Voltage range: up to −2.0 V to +6.0 V
2.4 ns minimum pulse width, 2 V terminated
Comparator
Window and differential comparator
500 MHz input equivalent bandwidth
Load
12 mA maximum current capability
Per pin PMU
Force voltage range: up to −2.0 V to +6.0 V
5 current ranges: 32 mA, 2 mA, 200 μA, 20 μA, 2 μA
Levels
the pin electronic functions of the driver, the comparator, and
the active load (DCL), per pin PMU, and dc levels for ATE appli-
cations. The device also contains an HVOUT driver with a VHH
buffer capable of generating up to 13.5 V.
The driver features three active states: data high mode, data low
mode, and term mode, as well as an inhibit state. The inhibit
state, in conjunction with the integrated dynamic clamp, facili-
tates the implementation of a high speed active termination.
The ADATE304 supports two output voltage ranges: −2.0 V
to +6.0 V and −1.25 V to +6.75 V by adjusting the positive and
negative supply voltages.
Each channel of the ADATE304 features a high speed window
comparator per pin for functional testing, as well as a per pin
PMU with FV, or FI and MV, or MI functions. All necessary dc
levels for DCL functions are generated by on-chip 14-bit DACs.
The per pin PMU features an on-chip 16-bit DAC for high
accuracy and contains integrated range resistors to minimize
external component counts.
14-bit DAC for DCL levels
Typically < 5 mV INL (calibrated)
16-bit DAC for PMU levels
Typically < 1.5 mV INL (calibrated) linearity in FV mode
HVOUT output buffer
0 V to 13.5 V output range
84-lead, 9 mm × 9 mm, CSP_BGA package
900 mW per channel with no load
The ADATE304 uses a serial bus to program all functional blocks
and has an on-board temperature sensor for monitoring the
device temperature.
APPLICATIONS
Automatic test equipment
Semiconductor test systems
Board test systems
Instrumentation and characterization equipment
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADATE304
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance.................................................................... 19
Explanation of Test Levels......................................................... 19
ESD Caution................................................................................ 19
Pin Configuration and Function Descriptions........................... 20
Typical Performance Characteristics ........................................... 23
SPI Details ....................................................................................... 33
Definition of SPI Word.............................................................. 34
Write Operation.......................................................................... 35
Read Operation........................................................................... 36
Reset Operation.......................................................................... 37
Register Map ................................................................................... 38
Details of Registers......................................................................... 39
User Information............................................................................ 41
Power Supply Considerations................................................... 41
Truth Tables................................................................................. 41
Details of DACs vs. Levels......................................................... 43
Recommended PMU Mode Switching Sequences................. 45
Block Diagrams............................................................................... 47
Outline Dimensions....................................................................... 51
Ordering Guide .......................................................................... 51
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Total Function............................................................................... 4
Driver ............................................................................................. 5
Reflection Clamp.......................................................................... 7
Normal Window Comparator .................................................... 7
Differential Comparator.............................................................. 9
Active Load.................................................................................. 10
PMU............................................................................................. 11
External Sense (PMUS_CHx)................................................... 16
DUTGND Input ......................................................................... 16
Serial Peripheral Interface......................................................... 16
HVOUT Driver........................................................................... 17
Overvoltage Detector (OVD) ................................................... 18
16-Bit DAC Monitor MUX ....................................................... 18
Absolute Maximum Ratings.......................................................... 19
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 52
ADATE304
FUNCTIONAL BLOCK DIAGRAM
CH1
PMU_FLAG
PMU
16-BIT DAC
*
MUX
MUX
DAC16_MON
*
OVD
OVD_CH0
MUX
MEASOUT01
PMUS_CH0
CH1
VCLAMPH
VCLAMPL
VH
VT
VL
R
OUT
(TRIMMED)
DATA0P
100Ω
DRV
DUT0
DATA0N
RCV0P
*
100Ω
WINDOW
DIFF.
C
RCV0N
OTHER CHANNEL
DUT1
*
COMP_VTT0
VHH
HVOUT
50Ω
COMP_QH0P
COMP_QH0N
C
C
VOH
VOL
COMP_QL0P
COMP_QL0N
*
G
IOL
ADATE304
SDIN
*
RST
SCLK
CS
VCOM
*
14-BIT DAC
SPI
TEMPERATURE
SENSOR
TEMPSENSE
IOH
SDOUT
*
ONE PER DEVICE.
Figure 1. One of Two Channels
Rev. 0 | Page 3 of 52
ADATE304
SPECIFICATIONS
Characterization and production tests performed using Power Supply Range 1 (see Table 37). VDD = +10.75 V, VCC = +3.3 V, VSS = −5.00 V,
VPLUS = +16.75 V, VCOMP_VTT = +3.3 V, VREF = +5.0 V, VREF_GND = 0.0 V. All default test conditions are as defined in Table 38. All specified
values are at TJ = 55°C, where TJ corresponds to the internal temperature sensor and the temperature coefficients are measured at TJ =
55°C ꢀ0°C, unless otherwise noted. Typical values are based on design, simulation analyses, and/or limited bench evaluations. Typical
values are not tested or guaranteed. Test levels are specified in the Explanation of Test Levels section.
TOTAL FUNCTION
Table 1.
Test
Parameter
Symbol Min
Typ
Max
Unit
Level Test Conditions/Comments
TOTAL FUNCTION
Output Leakage Current
PE Disable Range E
−20.0 +5.3
5.3
+20.0 nA
nA
P
−1.25 V < VDUTx < +6.0 V; PMU and PE disabled
via SPI; PMU Range E, VCH = 7.0 V, VCL = −2.5 V
−1.25 V < VDUTx < +6.0 V; PMU and PE disabled via
SPI; PMU Range A, PMU Range B, PMU Range C,
and PMU Range D, VCH = +7.0 V, VCL = −2.5 V
−1.25 V < VDUTx < +6.0 V; PMU disabled and PE
enabled via SPI; RCV active, VCH = +7.0 V, VCL =
−2.5 V
PE Disable Range A to Range D
High-Z Mode
CT
−400
−1.25
+5.4
4
+400
nA
P
Output Capacitance
DUT Pin Range
pF
V
S
D
VTERM mode operation
+6.0
POWER SUPPLIES
Total Supply Range, VPLUS to VSS
VPLUS Supply
Positive Supply
Negative Supply
Logic Supply
Comparator Termination
VPLUS Supply Current
22.5
23.25
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
W
mA
mA
W
D
D
D
D
D
D
P
P
P
P
P
P
P
P
P
P
Defines PSRR conditions
Defines PSRR conditions
Defines PSRR conditions
Defines PSRR conditions
Defines PSRR conditions
VPLUS
VDD
VSS
16.25 16.75 17.25
10.25 10.75 11.25
−5.25 −5.00 −4.75
VCC
3.1
3.3
3.5
5.0
VCOMP_VTT 3.3
IPLUS
−1.0
4.0
1.0
10.0
72
100
1.0
102
130
1.8
+1.3
12.7
2.7
+3.0
16.0
4.0
26.0
97
126
1.82
152
181
2.5
HVOUT disabled
HVOUT enabled, RCV active, no load, VHH = 12 V
Quiescent (SPI is static)
Logic Supply Current
Comparator Termination Current
Positive Supply Current
Negative Supply Current
Total Power Dissipation
Positive Supply Current
Negative Supply Current
Total Power Dissipation
TEMPERATURE MONITORS
Temperature Sensor Gain
ICC
ICOMP_VTT
IDD
17
90.5
116
1.6
120
146
2.2
Load power down (IOH = IOL = 0 mA)
Load power down (IOH = IOL = 0 mA)
Load power down (IOH = IOL = 0 mA)
Load active off (IOH = IOL = 12 mA)
Load active off (IOH = IOL = 12 mA)
Load active off (IOH = IOL = 12 mA)
ISS
IDD
ISS
10
6
mV/K CT
°C
Temperature Sensor Accuracy Without
Calibration over 25°C to 100°C
CT
Temperature voltage available on Pin A1 at all
times and on Pin K1 (MEASOUT01/TEMPSENSE)
when selected (see Table 24 and Table 36)
VREF INPUT
Reference Input Voltage Range for
DACs (VREF Pin)
Input Bias Current
4.95
5
5.05
100
V
D
P
Referenced to VREF_GND; not referenced to VDUTGND
Tested with 5 V applied
0.1
μA
Rev. 0 | Page 4 of 52
ADATE304
DRIVER
VH − VL ≥ 200 mV (to meet dc and ac specifications).
Table 2.
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
DC SPECIFICATIONS
High Speed Differential Logic Input
Characteristics (DATAxx, RCVxx)
Input Termination Resistance
Push 6 mA into xP pins1, force 1.3 V on xN pins1; measure
92
100
108
Ω
P
voltage from xP to xN1, calculate resistance (ΔV/ΔI)
Input Voltage Differential
Common-Mode Voltage
0.2
0.85
0.85
1.0
2.35
3.5
V
V
V
PF
PF
D
P
Input Bias Current
−20.0 +2.2
+20.0 μA
Each pin tested at 2.85 V and 0.35 V while the other high speed
pin remains open
Pin Output Characteristics
Output High Range, VH
Output Low Range, VL
Output Term Range, VT
Functional Amplitude (VH − VL)
−1.15
−1.25
−1.25
+6.75
+6.65
+6.75
V
V
V
V
D
D
D
D
0.0
8.0
Amplitude can be programmed to VH = VL, accuracy specifica-
tions apply when VH − VL ≥ 200 mV
DC Output Current Limit Source
DC Output Current Limit Sink
Output Resistance, 50 mA
ABSOLUTE ACCURACY
75
100
120
mA
mA
Ω
P
P
P
Driver high, VH = 6.75 V, short DUTx pin to −1.25 V, measure
current
Driver low, VL = −1.25 V, short DUTx pin to +6.75 V, measure
current
Source: driver high, VH = +3.0 V, IDUTx = +1 mA and +50 mA;
sink: driver low, VL = 0.0 V, IDUTx = −1 mA and −50 mA; ΔVDUT/ΔIDUT
−120 −100 −75
45.0
47.0
49.0
VH tests done with VL = −2.5 V and VT= −2.5 V;
VL tests done with VH = +7.5 V and VT = +7.5 V;
VT tests done with VL = −2.5 V and VH = +7.5 V; unless
otherwise specified
VH, VL, VT Uncalibrated Accuracy
VH, VL, VT Offset Tempco
VH, VL, VT DNL
−250
−10
75
450
1
2.5
+250 mV
P
Error measured at calibration points of 0 V and 5 V
Measured at calibration points
After two-point gain/offset calibration
After two-point gain/offset calibration; measured over driver
output ranges
After two-point gain/offset calibration; range/number of DAC
bits as measured at calibration points of 0 V and 5 V
μV/°C CT
mV
mV
CT
P
VH, VL, VT INL
+10
+1
VH, VL, VT Resolution
DUTGND Voltage Accuracy
VH, VL, VT Crosstalk
0.6
mV
mV
mV
PF
P
−7
1.3
2
+7
Over 0.1 V range; measured at endpoints of VH, VL, and VT
functional range
CT
VL = −1.25 V: VH = −1.15 V → +6.75 V, VT = −1.25 V → +6.75 V;
VH = +6.75 V: VL = −1.25 V → +6.65 V, VT = −1.25 V → +6.75 V;
VT = +1.25 V: VL = −1.25 V → +6.65 V, VH = −1.15 V → +6.75 V;
dc crosstalk on VL, VH, VT output level when other driver DACs
are varied
Overall Voltage Accuracy
10
15
mV
CT
Sum of INL, crosstalk, DUTGND, and tempco over 5°C, after
gain/offset calibration
Measured at calibration points
VH, VL, VT DC PSRR
AC SPECIFICATIONS
mV/V CT
Rise/Fall Times
Toggle DATAxx
0.2 V Programmed Swing
1.0 V Programmed Swing
2.0 V Programmed Swing
3.0 V Programmed Swing
3.0 V Programmed Swing
5.0 V Programmed Swing
Rise-to-Fall Matching
950
850
1150 1350
1500
2000
3100
ps
ps
ps
ps
ps
ps
ps
CB
CB
CB
P/CB
CB
VH = 0.2 V, VL = 0.0 V, terminated; 20% to 80%
VH = 1.0 V, VL = 0.0 V, terminated; 20% to 80%
VH = 3.0 V, VL = 0.0 V, terminated; 20% to 80%
VH = 3.0 V, VL = 0.0 V, terminated; 20% to 80%
VH = 3.0 V, VL = 0.0 V, unterminated; 10% to 90%
VH = 5.0V, VL = 0.0 V, unterminated; 10% to 90%
VH = 3.0 V, VL = 0.0 V, terminated; rise-to-fall within one channel
850
CB
CB
40
Rev. 0 | Page 5 of 52
ADATE304
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
Minimum Pulse Width
1.0 V Programmed Swing
Toggle DATAxx
VH = 1.0 V, VL = 0.0 V, terminated; timing error 75 ps
VH = 1.0 V, VL = 0.0 V, terminated; less than 10% amplitude
degradation
1.7
1.7
ns
ns
CB
CB
2.0 V Programmed Swing
3.0 V Programmed Swing
2.0
2.2
ns
ns
CB
CB
VH = 2.0 V, VL = 0.0 V, terminated; timing error 75 ps
VH = 2.0 V, VL = 0.0 V, terminated; less than 10% amplitude
degradation
VH = 3.0 V, VL = 0.0 V, terminated; timing error 75 ps
VH = 3.0 V, VL = 0.0 V, terminated; less than 10% amplitude
degradation
2.7
2.7
ns
ns
CB
CB
Maximum Toggle Rate
2.0 V Programmed Swing
Dynamic Performance, Drive
(VH to VL and VL to VH)
200
MHz
CB
VH = 2.0 V, VH = 0.0 V, terminated, 10% amplitude degradation
Toggle DATAxx
Propagation Delay Time
Propagation Delay Tempco
Delay Matching
Edge to Edge
Channel to Channel
3.0
3.0
ns
CB
VH = 2.0 V, VL = 0.0 V, terminated
VH = 2.0 V, VL = 0.0 V, terminated
VH = 2.0 V, VL = 0.0 V, terminated
Rising vs. falling
Rising vs. rising, falling vs. falling
VH = 3.0 V, VL = 0.0 V, terminated; 5% to 95% duty cycle; 1 MHz
VH = 3.0 V, VL = 0.0 V, terminated
Toggle DATAxx
ps/°C CT
80
30
30
30
ps
ps
ps
mV
CB
CB
CB
CB
Delay Change vs. Duty Cycle
Overshoot and Undershoot
Settling Time (VH to VL)
To Within 3% of Final Value
To Within 1% of Final Value
Dynamic Performance, VT
(VH or VL to VT and VT to VH or VL)
Propagation Delay Time
Delay Matching, Edge to Edge
Propagation Delay Tempco
4
25
ns
ns
CB
CB
VH = 3.0 V, VL = 0.0 V, terminated
VH = 3.0 V, VL = 0.0 V, terminated
Toggle RCVxx
3.7
150
4.0
1.0
ns
ps
CB
CB
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; rising vs. falling
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated
ps/°C CT
ns
Transition Time, Active to VT
and VT to Active
CB
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; 20% to 80%
Dynamic Performance, Inhibit
(VH or VL to/from Inhibit)
Propagation Delay Time
Toggle RCVxx
VH = +1.0 V, VL = −1.0 V, terminated
Active to Inhibit
Inhibit to Active
Transition Time
Active to Inhibit
Inhibit to Active
I/O Spike
4.5
7.9
ns
ns
CB
CB
VH =+1.0 V, VL = −1.0 V, terminated; 20% to 80%
2.9
0.65
190
ns
ns
mV
CB
CB
CB
VH = 0.0 V, VL = 0.0 V, terminated
1 The xP pins include DATA0P, DATA1P, RCV0P, and RCV1P; the xN pins include DATA0N, DATA1N, RCV0N, and RCV1N. For example, push 6 mA into the DATA0P pin,
force 1.3 V into DATA0N, and measure the voltage from DATA0P to DATA0N.
Rev. 0 | Page 6 of 52
ADATE304
REFLECTION CLAMP
Clamp accuracy specifications apply when VCH > VCL.
Table 3.
Test
Parameter
VCH
Min
Typ
Max
Unit
Level Test Conditions/Comments
Range
Uncalibrated Accuracy
−1.0
−200
+6.75
+200
V
mV
D
P
50
Driver high-Z, sinking 1 mA; VCH error measured at the
calibration points of 0.0 V and 5.0 V
Resolution
0.6
0.75
mV
PF
Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration; range/number of DAC bits as measured at
the calibration points of 0.0 V and 5.0 V
DNL
INL
1
2
mV
CT
P
Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration
Driver high-Z, sinking 1 mA; after two-point gain/offset
calibration; measured over VCH range of −1.0 V to +6.75 V
−40
+40
mV
Tempco
−0.3
mV/°C
CT
Measured at calibration points
VCL
Range
Uncalibrated Accuracy
−1.25
−200
+5.75
+200
V
mV
D
P
50
Driver high-Z, sourcing 1 mA; VCL error measured at the
calibration points of 0.0 V and 5.0 V
Resolution
0.6
0.75
mV
PF
Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration; range/number of DAC bits as measured at
the calibration points of 0.0 V and 5.0 V
DNL
INL
1
2
mV
CT
P
Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration
Driver high-Z, sourcing 1 mA; after two-point gain/offset
calibration; measured over VCL range of −1.0 V to +5.75 V
−40
+40
mV
Tempco
0.5
mV/°C
CT
Measured at calibration points
DC CLAMP CURRENT LIMIT
VCH
VCL
−120
60
−85
85
1
−60
120
+7
mA
mA
mV
P
P
P
Driver high-Z, VCH = 0 V, VCL = −1.0 V, VDUTx = +5 V
Driver high-Z, VCH = 6.75 V, VCL= 5.0 V, VDUTx = 0.0 V
DUTGND VOLTAGE ACCURACY
−7
Over 0.1 V range; measured at the endpoints of VCH
and VCL functional range
NORMAL WINDOW COMPARATOR
VOH tests done with VOL = −1.25 V; VOL tests done with VOH = 6.0 V, unless otherwise specified.
Table 4.
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Range
Differential Voltage Range
−1.25
0.1
+6.75
8.0
V
D
D
V
Comparator Input Offset Voltage
Accuracy, Uncalibrated
−150
30
+150
mV
P
Offset measured at the calibration points
of 0.0 V and 5.0 V
Comparator Threshold Resolution
0.6
1
mV
PF
After two-point gain/offset calibration;
range/number of DAC bits as measured at
the calibration points of 0 V and 5 V
Comparator Threshold DNL
Comparator Threshold INL
1
mV
mV
CT
P
After two-point gain/offset calibration
−7
−7
1.3
+7
After two-point gain/offset calibration;
measured over VOH, VOL range of −1.25 V
to +6.75 V
Comparator Input Offset Voltage
Tempco
100
0.5
ꢀV/°C CT
mV
Measured at calibration points
DUTGND Voltage Accuracy
+7
P
Over 0.1 V range; measured at endpoints
of VOH and VOL functional range
Rev. 0 | Page 7 of 52
ADATE304
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
Comparator Uncertainty Range
6.0
mV
CB
VDUTx = 0 V, sweep comparator threshold to
determine uncertainty region
DC Hysteresis
0.5
5
mV
CB
VDUTx = 0 V
DC PSRR
mV/V CT
Measured at calibration points
Digital Output Characteristics
Internal Pull-Up Resistance to
Comparator, COMP_VTT Pin
40
50
60
Ω
P
Pull 1 mA and 10 mA from Logic 1 leg and
measure ΔV to calculate resistance; measured
ΔV/9 mA; done for both comparator logic
states
VCOMP_VTT Range
3.3
5.0
V
D
CT
P
Common-Mode Voltage
VCOMP_VTT − 1.88
V
Measured with 100 Ω differential termination
Measured with no external termination
Measured with 100 Ω differential termination
Measured with no external termination
VCOMP_VTT − 2.075
400
VCOMP_VTT − 1.675
600
V
Differential Voltage
250
500
450
mV
mV
ps
CT
P
Rise/Fall Time, 20% to 80%
AC SPECIFICATIONS
CB
Measured with each comparator leg
terminated 50 Ω to GND
Input transition time = 800 ps, 10% to 90%;
measured with each comparator leg
terminated 50 Ω to GND, unless otherwise
specified
Propagation Delay, Input to
Output
1.75
5
ns
CB
CT
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement:
VOH = +0.50 V, VOL = −1.25 V; low-side
measurement: VOH = +6.75 V, VOL = +0.50 V
Propagation Delay Tempco
Propagation Delay Matching
ps/°C
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement:
VOH = +0.50 V, VOL = −1.25 V; low-side
measurement: VOH = +6.75 V, VOL = +0.50 V
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement:
VOH = +0.50 V, VOL = −1.25 V; low-side
measurement: VOH = +6.75 V, VOL = +0.50 V
High Transition to Low
Transition
200
50
ps
ps
CB
CB
High to Low Comparator
Propagation Delay Change (with
Respect To)
Slew Rate, 800 ps, 1 ns, 1.2 ns,
and 2.2 ns (10% to 90%)
50
75
ps
ps
CB
CB
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement:
VOH = +0.50 V, VOL = −1.25 V; low-side
measurement: VOH = +6.75V, VOL = +0.50 V
Overdrive, 250 mV and 1.0 V
For 250 mV: VDUTx = 0 V to 0.5 V swing; for
1.0 V: VDUTx = 0 V to 1.25 V swing; Driver
VTERM mode, VT = 0.0 V; high-side
measurement: VOH = +0.25 V, VOL = −1.25
V; low-side measurement: VOH = +6.75 V,
VOL = +0.25 V
Pulse Width, Sweep 1.6 ns to
10 ns
75
50
2.0
ps
ps
ns
CB
CB
CB
VDUTx = 0 V to 1.0 V swing @ 32.0 MHz,
Driver VTERM mode, VT = 0.0 V; high-side
measurement: VOH = +0.5 V, VOL = −1.25 V;
low-side measurement: VOH = +6.75 V,
VOL = +0.5 V
Duty Cycle, 5% to 95%
Minimum Pulse Width
VDUTx = 0 V to 1.0 V swing @ 1.0 MHz, Driver
VTERM mode, VT =0.0 V; high-side
measurement: VOH = +0.50 V, VOL = −1.25
V; low-side measurement: VOH = +6.75 V,
VOL = +0.50 V
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; less than 12% amplitude
degradation measured by shmoo
Input Equivalent Bandwidth,
Terminated
500
2.5
MHz
ns
CB
CB
VDUTx = 0 V to 1.0 V swing, Driver VTERM
mode, VT = 0.0 V; as measured by shmoo
ERT High-Z Mode, 3 V, 20%
to 80%
VDUTx = 0 V to 3.0 V swing, driver high-Z; as
measured by shmoo; input transition time of
~2000 ps, 10% to 90%
Rev. 0 | Page 8 of 52
ADATE304
DIFFERENTIAL COMPARATOR
VOH tests done with VOL = −1.1 V, VOL tests done with VOH = +1.1 V, unless otherwise specified.
Table 5.
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
DC SPECIFICATIONS
Input Voltage Range
Operational Differential Voltage
Range
−1.25
0.05
+4.5
1.1
V
V
D
D
Maximum Differential Voltage Range
8
V
D
Comparator Input Offset Voltage
Accuracy, Uncalibrated
VOH, VOL Resolution
−150
−15
35
+150
mV
P/CT
Offset measured at differential calibration points +1.0 V
and −1.0 V, with common mode = 0.0 V
After two-point gain/offset calibration; range/number of
DAC bits as measured at differential calibration points
+1.0 V and −1.0 V, with common mode = 0.0 V
After two-point gain/offset calibration; common
mode = 0.0 V
After two-point gain/offset calibration; measured over VOH,
VOL range of −1.1 V to +1.1 V, common mode = 0.0 V
0.6
1
mV
PF
VOH, VOL DNL
VOH, VOL INL
1
mV
mV
CT
P
2.0
+15
VOH, VOL Offset Voltage Tempco
Comparator Uncertainty Range
200
18
ꢀV/°C CT
Measured at calibration points
VDUTx = 0 V, sweep comparator threshold to determine
uncertainty region
mV
CB
DC Hysteresis
CMRR
0.5
0.15
mV
mV/V
CB
P
VDUTx = 0 V
1
Offset measured at common-mode voltage points of
−1.5 V and +4.5 V, with differential voltage = 0.0 V
DC PSRR
1.5
1.7
mV/V CT
Measured at calibration points
AC SPECIFICATIONS
Input transition time = 800 ps, 10% to 90%, measured
with each comparator leg terminated 50 Ω to GND
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
Propagation Delay, Input to Output
Propagation Delay Tempco
ns
CB
5
ps/°C CT
Propagation Delay Matching
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
High Transition to Low Transition
High-to-Low Comparator
100
50
ps
ps
CB
CB
Propagation Delay Change (with
Respect To)
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
Slew Rate, 800 ps, 1 ns, 1.2 ns, and
2.2 ns (10% to 90%)
60
ps
ps
ps
ps
CB
CB
CB
CB
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, for 250 mV: VDUT1 = 0 V to 0.5 V swing; for
750 mV: VDUT1 = 0 V to 1.0 V swing, Driver VTERM mode,
VT = 0.0 V; VOH = −0.25 V; repeat for other DUT channel
with comparator threshold = +0.25 V
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing @ 32 MHz, Driver
VTERM mode, VT = 0.0 V; high-side measurement: VOH =
0.0 V, VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing @ 1 MHz, Driver
VTERM mode, VT = 0.0 V; high-side measurement: VOH =
0.0 V, VOL = −1.1 V; low-side measurement: VOH = +1.1 V,
VOL = 0.0 V; repeat for other DUT channel
Overdrive, 250 mV and 750 mV
100
75
Pulse Width, Sweep from 1.6 ns to
10 ns
Duty Cycle, 5% to 95%
60
Rev. 0 | Page 9 of 52
ADATE304
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
Minimum Pulse Width
2.5
ns
CB
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V, VOL
= 0.0 V; less than 10% amplitude degradation measured
by shmoo; repeat for other DUT channel
Input Equivalent Bandwidth,
Terminated
400
MHz
CB
VDUT0 = 0 V, VDUT1 = −0.5 V to +0.5 V swing, Driver VTERM
mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V,
VOL = −1.1 V; low-side measurement: VOH = +1.1 V, VOL
= 0.0 V; less than 22% amplitude degradation measured
by shmoo; repeat for other DUT channel
ACTIVE LOAD
See the Truth Tables section and Table 29 for load control information.
Table 6.
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
DC SPECIFICATIONS
Input Characteristics
VCOM Voltage Range
VDUT Range
Load active on, RCV active, unless otherwise noted
−1.00
−1.25
−200
+6.50
+6.75
+200 mV
V
V
D
D
P
VCOM Accuracy, Uncalibrated
30
IOH = IOL = 6 mA, VCOM error measured at the calibration points
of 0.0 V and 5.0 V
VCOM Resolution
0.6
1
mV
PF
IOH = IOL = 6 mA, after two-point gain/offset calibration;
range/number of DAC bits as measured at the calibration points
of 0.0 V and 5.0 V
VCOM DNL
VCOM INL
1
2
mV
mV
CT
P
IOH = IOL = 6 mA, after two-point gain/offset calibration
IOH = IOL = 6 mA, after two-point gain/offset calibration;
measured over VCOM range of −1.00 V to +6.50 V
Over 0.1 V range; measured at end points of VCOM functional
range
−7
−7
+7
+7
DUTGND Voltage Accuracy
1
mV
P
Output Characteristics
IOL
Maximum Source Current
Uncalibrated Offset
12
−600
mA
D
P
100 +600 ꢀA
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL offset calculated from
the calibration points of 1 mA and 11 mA
Uncalibrated Gain
Resolution
−12
4
+12
2
%
P
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL gain calculated from
the calibration points of 1 mA and 11 mA
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/
offset calibration; range/number of DAC bits as measured at the
calibration points of 1 mA and 11 mA
1.5
ꢀA
PF
DNL
3.0
20
ꢀA
ꢀA
V
CT
P
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point
gain/offset calibration
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/
offset calibration; measured over IOL range of 0 mA to 12 mA
IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOL reference at
VDUTx = −1.0 V, measure IOL current at VDUTx = +1.75 V, ensure > 90%
of reference current
INL
−80
+80
0.25
90% Commutation Voltage
P
IOH
Maximum Sink Current
Uncalibrated Offset
12
−600
mA
D
P
100 +600 ꢀA
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH offset calculated from
the calibration points of 1 mA and 11 mA
Uncalibrated Gain
Resolution
−12
4
+12
2
%
P
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH gain calculated from
the calibration points of 1 mA and 11 mA
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point
gain/offset calibration; range/number of DAC bits as measured at
the calibration points of 1 mA and 11 mA
1.5
ꢀA
PF
DNL
3.0
ꢀA
CT
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point
gain/offset calibration
Rev. 0 | Page 10 of 52
ADATE304
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
INL
−80
20
+80
ꢀA
P
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point gain/
offset calibration; measured over IOH range of 0 mA to 12 mA
90% Commutation Voltage
0.25
V
P
IOH = IOL =12 mA, VCOM = 2.0 V, measure IOH reference at VDUTx
= 5.0 V, measure IOH current at VDUTx = 2.25 V, ensure > 90% of
reference current
Output Current Tempco
AC SPECIFICATIONS
Dynamic Performance
Propagation Delay, Load Active
On to Load Active Off;
50%,90%
1.5
7.3
ꢀA/°C CT
Measured at calibration points
Load active on, unless otherwise noted
ns
ns
CB
CB
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; measured from 50% point of RCVxP − RCVxN to 90% point of
final output, repeat for drive low and high
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; measured from 50% point of RCVxP − RCVxN to 90% point of
final output, repeat for drive low and high
Propagation Delay, Load Active
Off to Load Active On;
50%, 90%
10.3
Propagation Delay Matching
Load Spike
3.0
190
1.9
ns
CB
CB
CB
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for
IOH; active on vs. active off, repeat for drive low and high
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 0 mA, VH
= VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for IOH;
repeat for drive low and high
Toggle RCV, DUTx terminated 50 Ω to GND, IOH = IOL = 12 mA,
VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = −1.25 V for IOH;
measured at 90% of final value
mV
ns
Settling Time to 90%
PMU
FV is the force voltage, MV is the measure voltage, FI is the force current, MI is the measure current, FN is force nothing.
Table 7.
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
FORCE VOLTAGE (FV)
Current Range A
Current Range B
Current Range C
Current Range D
Current Range E
32
2
200
20
2
−1.25
mA
mA
ꢀA
ꢀA
ꢀA
V
D
D
D
D
D
D
Force Input Voltage Range at
Output for All Ranges
+6.75
Force Voltage Uncalibrated
Accuracy for Range C
Force Voltage Uncalibrated
Accuracy for All Ranges
Force Voltage Offset Tempco
for All Ranges
Force Voltage Gain Tempco
for All Ranges
−100
25
25
25
10
2
+100 mV
mV
P
PMU enabled, FV, Range C, PE disabled, error measured at
calibration points of 0.0 V and 5.0 V
PMU enabled, FV, PE disabled, error measured at calibration
points of 0.0 V and 5.0 V; repeat for each PMU current range
CT
CT
ꢀV/°C
Measured at calibration points for each PMU current range
ppm/°C CT
Measured at calibration points for each PMU current range
Forced Voltage INL
−7
+7
mV
P
PMU enabled, FV, Range C, PE disabled, after two-point gain/offset
calibration; measured over output range of −1.25 V to +6.75 V
Force Voltage Compliance vs.
Current Load
PMU enabled, FV, PE disabled, force −1.25 V, measure voltage
while PMU sinking zero and full-scale current; measure ∆V;
force 6.75 V, measure voltage while PMU sourcing zero and
full-scale current; measure ∆V; repeat for each PMU current
range
Range A
Range B to Range E
4
1
mV
mV
CT
CT
Rev. 0 | Page 11 of 52
ADATE304
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
Current Limit, Source, and Sink
Range A
108
140
180
%FS
P
P
PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx
to 6.0 V; source: force 2.5 V, short DUTx to −1.0 V; Range A FS =
32 mA, 108% FS = 35 mA, 180% FS = 58 mA
PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx to
6.0 V; source: force 2.5 V, short DUTx to −1.0 V; repeat for each
PMU current range; example: Range B FS = 2 mA, 120 % FS =
2.4 mA, 180% FS = 3.6 mA
Range B to Range E
120
−7
145
1
180
+7
%FS
mV
DUTGND Voltage Accuracy
MEASURE CURRENT (MI)
P
Over 0.1 V range; measured at endpoints of FV functional
range
VDUTx externally forced to 0.0V, unless otherwise specified; ideal
MEASOUT transfer functions: VMEASOUT01 [V] = (IMEASOUT01 × 5/FSR) +
2.5 + VDUTGND I(VMEASOUT01) [A] = (VMEASOUT01 − VDUTGND − 2.5) × FSR/5
Measure Current, Pin DUTx
Voltage Range for All Ranges
−1.5
+6.0
V
D
Measure Current Uncalibrated
Accuracy
Range A
Range B
Range C
Range D
Range E
500
ꢀA
CT
P
PMU enabled, FIMI, Range A, PE disabled, error at calibration
points −25 mA and +25 mA, error = (I(VMEASOUT01) − IDUTx
PMU enabled, FIMI, Range B, PE disabled, error at calibration
points −1.6 mA and +1.6 mA, error = (I(VMEASOUT01) − IDUTx
PMU enabled, FIMI, PE disabled, error at calibration points of
80% FS, error = (I(VMEASOUT01)1 − IDUTx
PMU enabled, FIMI, PE disabled, error at calibration points of
80% FS, error = (I(VMEASOUT01) − IDUTx
PMU enabled, FIMI, PE disabled, error at calibration points of
)
−400
3.0
+400 ꢀA
)
2.00
0.30
0.08
ꢀA
ꢀA
ꢀA
CT
CT
CT
)
)
80% FS, error = (I(VMEASOUT01) − IDUTx
)
Measure Current Offset Tempco
Range A
Range B
Range C
Range D and Range E
2
25
5
ꢀA/°C
CT
CT
CT
CT
Measured at calibration points
Measured at calibration points
Measured at calibration points
Measured at calibration points
nA/°C
nA/°C
nA/°C
1
Measure Current Gain Error,
Nominal Gain = 1
Range A
2.5
2
%
%
%
CT
P
PMU enabled, FIMI, PE disabled, gain error from calibration
points 80% FS
PMU enabled, FIMI, Range B, PE disabled, gain error from
calibration points 1.6 mA
PMU enabled, FIMI, PE disabled, gain error from calibration
points 80% FS
Range B
−20
+20
Range C to Range E
4
CT
Measure Current Gain Tempco
Range A
Range B to Range E
Measure Current INL
Range A
Measured at calibration points
300
50
ppm/°C CT
ppm/°C CT
0.05
%FSR
CT
PMU enabled, FIMI, Range A, PE disabled, after two-point
gain/offset calibration, measured over FSR output of −32 mA
to +32 mA
Range B
−0.02
−0.01
+0.02 %FSR
%FSR
P
PMU enabled, FIM,I Range B, PE disabled, after two-point gain/
offset calibration measured over FSR output of −2 mA to +2 mA
PMU enabled, FIMI, PE disabled, after two-point gain/offset
calibration; measured over FSR output
PMU enabled, FVMI, Range B, PE disabled, force −1 V and +5 V
into load of 1 mA; measure ∆I reported at MEASOUT01
Over 0.1 V range; measured at endpoints of MI functional range
Range B to Range E
0.01
2.5
CT
P
FVMI DUT Pin Voltage Rejection
DUTGND Voltage Accuracy
+0.01 %FSR/V
mV
CT
Rev. 0 | Page 12 of 52
ADATE304
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
FORCE CURRENT (FI)
VDUTx externally forced to 0.0V, unless otherwise specified, ideal
force current transfer function: IFORCE = (PMUDAC − 2.5) × (FSR/5)
Force Current, DUTx Pin Voltage −1.25
Range for All Ranges
+6.75
V
D
Force Current Uncalibrated
Accuracy
Range A
Range B
Range C
Range D
Range E
−5.0
−400
−40
−4
0.5
40
4
+5.0
mA
P
P
P
P
P
PMU enabled, FIMI, Range A, PE disabled, error at calibration
points of −25 mA and +25 mA
PMU enabled, FIMI, Range B, PE disabled, error at calibration
points of −1.6 mA and 1.6 mA
PMU enabled, FIMI, Range C, PE disabled, error at calibration
points of 80% FS
PMU enabled, FIMI, Range D, PE disabled, error at calibration
points of 80% FS
+400 ꢀA
+40
+4
ꢀA
ꢀA
0.4
75
−400
+400 nA
PMU enabled, FIMI, Range E, PE disabled, error at calibration
points of 80% FS
Force Current Offset Tempco
Range A
Range B
Range C to Range E
Forced Current Gain Error,
Nominal Gain = 1
1
80
4
ꢀA/°C
CT
CT
CT
P
Measured at calibration points
Measured at calibration points
Measured at calibration points
PMU enabled, FIMI, PE disabled, gain error from calibration
points of 80% FS
nA/°C
nA/°C
%
−20
4
+20
Forced Current Gain Tempco
Range A
Range B to Range E
Force Current INL
Range A
Measured at calibration points
−500
75
ppm/°C CT
ppm/°C CT
−0.3
−0.2
0.05
+0.3
%FSR
%FSR
P
P
PMU enabled, FIMI, Range A, PE disabled, after two-point
gain/offset calibration; measured over FSR output of −32 mA
to +32 mA
PMU enabled, FIMI, PE disabled, after two-point gain/offset
calibration; measured over FSR output
Range B to Range E
0.015 +0.2
Force Current Compliance vs.
Voltage Load
PMU enabled, FIMV, PE disabled; force positive full-scale
current driving −1.5 V and +6.0 V, measure ∆I @ DUTx pin;
force negative full-scale current driving −1.25 V and +6.75 V,
measure ∆I @ DUTx pin
Range A to Range D
Range E
−0.6
−1.0
0.06
0.1
+0.6
+1.0
%FSR
%FSR
P
P
MEASURE VOLTAGE
Measure Voltage Range
Measure Voltage Uncalibrated
Accuracy
−1.5
−25
+6.0
+25
V
mV
D
P
2.0
PMU enabled, FVMV, Range B, PE disabled, error at calibration
points of 0 V and 5 V, error = (VMEASOUT01 − VDUTx
)
Measure Voltage Offset Tempco
Measure Voltage Gain Error
10
0.01
ꢀV/°C
%
CT
P
Measured at calibration points
PMU enabled, FVMV, Range B, PE disabled, gain error from
calibration points of 0 V and 5 V
−0.2
+0.2
Measure Voltage Gain Tempco
Measure Voltage INL
25
1
ppm/°C CT
Measured at calibration points
−7
+7
mV
P
PMU enabled, FVMV, Range B, PE disabled, after two-point
gain/offset calibration; measured over output range of −1.25 V
to +6.75 V
Rejection of Measure V vs. IDUTx
−1.5
0.1
+1.5
mV
P
PMU enabled, FVMV, Range D, PE disabled, force 0 V into load
of −10 ꢀA and +10 ꢀA; measure ∆V reported at MEASOUT01
Rev. 0 | Page 13 of 52
ADATE304
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
MEASOUT01 DC CHARACTERISTICS
MEASOUT01 Voltage Range
DC Output Current
MEASOUT01 Pin Output
Impedance
−1.5
+6.0
4
200
V
mA
Ω
D
D
P
25
PMU enabled, FVMV, PE disabled; source resistance: PMU force
+6.75 V and load with 0 mA and +4 mA; sink resistance: PMU
force −1.25 V and load with 0 mA and −4 mA; resistance =
∆V/∆I at MEASOUT01 pin
Output Leakage Current when
Tristated
Output Short-Circuit Current
−1
+1
ꢀA
P
P
Tested at −1.25 V and +6.75 V
−25
+25
mA
PMU enabled, FVMV, PE disabled; source: PMU force +6.75 V,
short MEASOUT01 to −1.25 V; sink: PMU force −1.25 V, short
MEASOUT01 to +6.75 V
VOLTAGE CLAMPS
Low Clamp Range (VCL)
High Clamp Range (VCH)
Positive Clamp Voltage Droop
−1.25
0.75
−300 +10
+4.75
6.75
V
V
D
D
P
+300 mV
+300 mV
+250 mV
PMU enabled, FIMI, Range A, PE disabled, PMU clamps
enabled, VCH = +5.0 V, VCL = −1.0 V, PMU force 2.0 mA and
32 mA into open; ∆V seen at DUTx pin
PMU enabled, FIMI, Range A, PE disabled, PMU clamps
enabled, VCH = +5.0 V, VCL = −1.0 V, PMU force −2.0 mA and
−32 mA into open; ∆V seen at DUTx pin
PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled,
PMU force 1 mA into open; VCH errors at calibration points
1.0 V and 5.0 V; VCL errors at the calibration points 0.0 V and
4.0 V
PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled,
PMU force 1 mA into open; after two-point gain/offset
calibration; measured over PMU clamp range
Negative Clamp Voltage Droop
Uncalibrated Accuracy
−300 −10
P
P
−250
−70
100
INL
5
1
+70
mV
mV
P
DUTGND Voltage Accuracy
SETTLING/SWITCHING TIMES
CT
Over 0.1 V range; measured at endpoints of PMU clamp
functional range
SCAP = 330 pF, FFCAP = 220 pF
Voltage Force Settling Time to
0.1% of Final Value
PMU enabled, FV, PE disabled, program PMUDAC steps of
500 mV and 5.0 V; simulation of worst case, 2000 pF load,
PMUDAC step of 5.0 V
Range A, 200 pF and
2000 pF Load
Range B, 200 pF and
2000 pF Load
Range C, 200 pF and
2000 pF Load
Range D, 200 pF and
2000 pF Load
15
ꢀs
ꢀs
ꢀs
ꢀs
ꢀs
S
S
S
S
S
20
124
1015
3455
Range E, 200 pF and
2000 pF Load
Voltage Force Settling Time to
1.0% of Final Value
PMU enabled, FV, PE disabled, start with PMUDAC
programmed to 0.0 V, program PMUDAC to 500 mV
Range A, 200 pF and
2000 pF Load
Range B, 200 pF and
2000 pF Load
Range C, 200 pF and
2000 pF Load
14
14
14
ꢀs
ꢀs
ꢀs
CB
CB
CB
Range D, 200 pF Load
Range D, 2000 pF Load
Range E, 200 pF Load
Range E, 2000 pF Load
45
45
45
225
ꢀs
ꢀs
ꢀs
ꢀs
CB
CB
CB
CB
Rev. 0 | Page 14 of 52
ADATE304
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
Voltage Force Settling Time to
1.0% of Final Value
PMU enabled, FV, PE disabled, start with PMUDAC
programmed to 0.0 V, program PMUDAC to 5.0 V
Range A, 200 pF and
2000 pF Load
4.0
ꢀs
CB
Range B, 200 pF Load
Range B, 2000 pF Load
Range C, 200 pF Load
Range C, 2000 pF Load
Range D, 200 pF Load
Range D, 2000 pF Load
Range E, 200 pF Load
Range E, 2000 pF Load
4.2
4.2
5.8
19
ꢀs
ꢀs
ꢀs
ꢀs
ꢀs
ꢀs
ꢀs
ꢀs
CB
CB
CB
CB
CB
CB
CB
CB
50
210
360
610
Current Force Settling Time to
0.1% of Final Value
PMU enabled, FI, PE disabled, start with PMUDAC
programmed to 0 current, program PMUDAC to FS current
Range A, 200 pF in Parallel
with 120 Ω
Range B, 200 pF in Parallel
with 1.5 kΩ
Range C, 200 pF in Parallel
with 15.0 kΩ
Range D, 200 pF in Parallel
with 150 kΩ
8.2
ꢀs
ꢀs
ꢀs
ꢀs
ꢀs
S
S
S
S
S
9.4
30
281
2668
Range E, 200 pF in Parallel
with 1.5 MΩ
Current Force Settling Time to
1.0% of Final Value
PMU enabled, FI, PE disabled, start with PMUDAC
programmed to 0 current, program PMUDAC to FS current
Range A, 200 pF in Parallel
with 120 Ω
Range B, 200 pF in Parallel
with 1.5 kΩ
Range C, 200 pF in Parallel
with 15.0 kΩ
Range D, 200 pF in Parallel
with 150 kΩ
4.2
4.3
8.1
205
505
ꢀs
ꢀs
ꢀs
ꢀs
ꢀs
CB
CB
CB
CB
CB
Range E, 200 pF in Parallel
with 1.5 MΩ
INTERACTION AND CROSSTALK
Measure Voltage Channel-to-
Channel Crosstalk
0.125
%FSR
%FSR
CT
CT
PMU enabled, FIMV, PE disabled, Range B, forcing 0 mA into
0 V load; other channel: Range A, forcing a step of 0 mA to 25 mA
into 0 V load; report ∆V of MEASOUT01 pin under test;
0.125% × 8.0 V = 10 mV
PMU enabled, FVMI, PE disabled, Range E, forcing 0 V into
0 mA current load; other channel: Range E, forcing a step of 0 V
to 5 V into 0 mA current load; report ∆V of MEASOUT01 pin
under test; 0.01% × 5.0 V = 0.5 mV
Measure Current Channel-to-
Channel Crosstalk
0.01
Rev. 0 | Page 15 of 52
ADATE304
EXTERNAL SENSE (PMUS_CHx)
Table 8.
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
EXTERNAL SENSE (PMUS_CHX)
Voltage Range
Input Leakage Current
−1.25
−20
+6.75
+20
V
nA
D
P
Tested at −1.25 V and +6.75 V
DUTGND INPUT
Table 9.
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
DUTGND INPUT
Input Voltage Range, Referenced to GND
Input Bias Current
−0.1
+0.1
100
V
μA
D
P
1
Tested at −100 mV and +100 mV
SERIAL PERIPHERAL INTERFACE
Table 10.
Test
Parameter
Min
Typ
Max
Unit
Level Test Conditions/Comments
SERIAL PERIPHERAL INTERFACE
Serial Input Logic High
Serial Input Logic Low
Input Bias Current
SCLK Clock Rate
SCLK Pulse Width
1.8
0
−10
VCC
0.7
+10
V
V
PF
PF
P
PF
CT
CB
PF
1
50
9
μA
MHz
ns
mV
V
Tested at 0.0 V and 3.3 V
SCLK Crosstalk on DUTx Pin
Serial Output Logic High
8
PE disabled, PMU FV enabled and forcing 0 V
Sourcing 2 mA
VCC − 0.4
0
VCC
0.8
Serial Output Logic Low
Update Time
V
μs
PF
D
Sinking 2 mA
Maximum delay time required for the part to
enter a stable state after a serial bus
10
Rev. 0 | Page 16 of 52
ADATE304
HVOUT DRIVER
Table 11.
Test
Level
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
VHH BUFFER
Voltage Range
Output High
VHH = (VT + 1 V) × 2 + DUTGND
VPLUS = 16.75 V nominal; in this condition, VHVOUT max = 13.5 V
VHH mode enabled, RCV active, VHH level = full scale,
sourcing 15 mA
5.9
13.5
VPLUS − 3.25
V
V
D
P
Output Low
5.9
V
P
P
VHH mode enabled, RCV active, VHH level = zero scale,
sinking 15 mA
VHH mode enabled, RCV active, VHVOUT error measured at
the calibration points of 7 V and 12 V
Accuracy Uncalibrated
−500
−30
100
+500
mV
Offset Tempco
Resolution
1
mV/°C
mV
CT
PF
Measured at calibration points
1.21
1.5
VHH mode enabled, RCV active, after two-point gain/offset
calibration; range/number of DAC bits as measured at the
calibration points of 7 V and 12 V
VHH mode enabled, RCV active, after two-point gain/offset
calibration; measured over VHH range of 5.9 V to 13.5 V
Over 0.1 V range; measured at endpoints of VHH
functional range
VHH mode enabled, RCV active, source: VHH = 10.0 V,
IHVOUT = 0 mA and 15 mA; sink: VHH = 6.5 V, IHVOUT = 0 mA and
−15 mA; ∆V/∆I
INL
15
1
+30
mV
mV
Ω
P
DUTGND Voltage Accuracy
Output Resistance
CT
P
1
10
DC Output Current Limit
Source
DC Output Current Limit Sink
60
100
−60
mA
mA
ns
P
VHH mode enabled, RCV active, VHH = 10.0 V, short HVOUT
pin to 5.9 V, measure current
VHH mode enabled, RCV active, VHH = 6.5 V, short HVOUT
pin to 14.1 V, measure current
VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; 20% to 80%, for DATA = high and DATA = low
VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; 20% to 80%, for DATA = high and DATA = low
−100
P
Rise Time (From VL or VH to
VHH)
Fall Time (From VHH to VL or
VH)
Preshoot, Overshoot, and
Undershoot
200
26
CB
CB
CB
ns
125
mV
VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH =
3.0 V; for DATA = high and DATA = low
VL/VH BUFFER
Voltage Range
Accuracy Uncalibrated
−0.1
−500
+6.0
+500
V
mV
D
P
100
VHH mode enabled, RCV inactive, error measured at the
calibration points 0 V and 5 V
Offset Tempco
Resolution
1
0.61
mV/°C
mV
CT
PF
Measured at calibration points
0.75
+20
VHH mode enabled, RCV inactive, after two-point
gain/offset calibration; range/number of DAC bits as
measured at the calibration points 0 V and 5 V
VHH mode enabled, RCV inactive, after two-point
gain/offset calibration; measured over range of −0.1 V to
+6.0 V
Over 0.1 V range; measured at endpoints of VH and VL,
functional range
VHH mode enabled, RCV inactive, source: VH = 3.0 V, IHVOUT
= +1 mA and +50 mA; sink: VL = 2.0 V, IHVOUT = −1 mA and
−50 mA; ∆V/∆I
INL
−20
45
4
mV
P
DUTGND Voltage Accuracy
Output Resistance
2
mV
Ω
CT
P
48
50
DC Output Current Limit
Source
DC Output Current Limit Sink
60
100
−60
mA
mA
ns
P
VHH mode enabled, RCV inactive, VH = +6.0 V, short
HVOUT pin to −0.1 V, DATA high, measure current
VHH mode enabled, RCV inactive, VL = −0.1 V, short HVOUT
pin to +6.0 V, DATA low, measure current
VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA; 20% to 80%
VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA; 20% to 80%
−100
P
Rise Time (VL to VH)
11
CB
CB
CB
Fall Time (VH to VL)
11.3
54
ns
Preshoot, Overshoot, and
Undershoot
mV
VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V,
toggle DATA
Rev. 0 | Page 17 of 52
ADATE304
OVERVOLTAGE DETECTOR (OVD)
Table 12.
Test
Level
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC CHARACTERISTICS
Programmable Voltage Range
Accuracy Uncalibrated
−2.25
−200
+7.0
+200
V
mV
D
P
OVD offset errors measured at programmed levels of +7.0 V
and −2.25 V
Hysteresis
112
mV
CB
LOGIC OUTPUT CHARACTERISTICS
Off State Leakage
10
1000
0.7
nA
V
P
Disable OVD alarm, apply 3.3 V to OVD pin, measure
leakage current
Activate alarm, force 100 μA into OVD pin, measure active
alarm voltage
For OVD high: DUTx = 0 V to +6 V swing, OVD high = +3.0 V,
OVD low = −2.25 V; for OVD low: DUTx = 0 V to +6 V swing,
OVD high = +7.0 V, OVD low = +3.0 V
Maximum On Voltage @ 100 μA
Propagation Delay
0.2
1.9
P
μs
CB
16-BIT DAC MONITOR MUX
Table 13.
Test
Level
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC CHARACTERISTICS
Programmable Voltage Range
Output Resistance
−2.5
+7.5
V
kΩ
D
CT
16
PMUDAC = 0.0 V, FV, I = 0, 200 μA; ∆V/∆I
Rev. 0 | Page 18 of 52
ADATE304
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 14.
Parameter
Rating
Table 15. Thermal Resistance
Package Type
Supply Voltages
θJA
θJC
Positive Supply Voltage (VDD to GND)
Positive VCC Supply Voltage (VCC to GND)
Negative Supply Voltage (VSS to GND)
Supply Voltage Difference (VDD to VSS)
Reference Ground (DUTGND to GND)
AGND to DGND
−0.5 V to +11.5 V
−0.5 V to +4.0 V
−6.25 V to +0.5 V
−1.0 V to +16.5 V
−0.5 V to +0.5 V
−0.5 V to +0.5 V
−0.5 V to +17.5 V
84-Ball CSP_BGA
31.1
0.51
EXPLANATION OF TEST LEVELS
D
Definition
S
Design verification simulation
100% production tested
VPLUS Supply Voltage (VPLUS to GND)
Input Voltages
P
Input Common-Mode Voltage
Short-Circuit Voltage1
High Speed Input Voltage2
High Speed Differential Input Voltage3
VREF
VSS to VDD
−3.0 V to +8.0 V
0.0 V to VCC
0.0 V to VCC
−0.5 V to +5.5 V
PF
Functionally checked during production test
CT Characterized on tester
CB Characterized on bench
DUTx I/O Pin Current
DCL Maximum Short-Circuit Current4
Temperature
140 mA
ESD CAUTION
Operating Temperature, Junction
Storage Temperature Range
125°C
−65°C to +150°C
1 RL = 0 Ω, VDUT continuous short-circuit condition (VH, VL, VT, high-Z, VCOM,
clamp modes).
2 DATAxP, DATAxN, RCVxP, RCVxN, under source RL = 0 Ω.
3 DATAxP to DATAxN, RCVxP, RCVxN.
4 RL = 0 Ω, VDUTx = –3 V to +8 V; DCL current limit. Continuous short-circuit
condition. ADATE304 must current limit and survive continuous short circuit.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 19 of 52
ADATE304
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10
9
8
7
6
5
4
3
2
1
VSSO_0
(DRIVE)
VDDO_0
(DRIVE)
VDDO_1
(DRIVE)
VSSO_1
(DRIVE)
HVOUT
PMUS_CH0
DUT0
DUT1
PMUS_CH1 TEMPSENSE
A
B
C
D
E
F
VDD/VDD_
TMPSNS
VSS
AGND
VSS
VDD
VDD
VDD
VDD
AGND
VSS
VSS
SCAP1
VPLUS
FFCAP_0B
OVD_CH0
FFCAP_0A
AGND
SCAP0
AGND
VDD
DATA0N
DATA0P
RCV0N
RCV0P
DATA1N
DATA1P
RCV1N
RCV1P
AGND
VDD
FFCAP_1B
OVD_CH1
FFCAP_1A
AGND
VSS
VSS
AGND
AGND
COMP_VTT1 COMP_QL1N COMP_QL1P
COMP_QL0P COMP_QL0N COMP_VTT0
G
H
J
VSS
RST
VCC
VDD
SDIN
SCLK
VDD
DGND
SDOUT
VSS
DAC16_MON
CS
AGND
AGND
AGND
COMP_QH1N COMP_QH1P
COMP_QH0P COMP_QH0N
AGND
AGND
AGND
AGND
AGND
AGND
VREF
MEASOUT01/
TEMPSENSE
K
VREF_GND
AGND
DUTGND
Figure 2. Pin Configuration
Rev. 0 | Page 20 of 52
ADATE304
Table 16. Pin Function Descriptions
Pin No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
Mnemonic
TEMPSENSE
PMUS_CH1
VSSO_1 (Drive)
DUT1
VDDO_1 (Drive)
VDDO_0 (Drive)
DUT0
VSSO_0 (Drive)
PMUS_CH0
HVOUT
VDD/VDD_TMPSNS
SCAP1
Description
Temperature Sense Output
PMU External Sense Path Channel 1
Driver Output Supply (−5.0 V) Channel 1
Device Under Test Channel 1
Driver Output Supply (+10.75 V) Channel 1
Driver Output Supply (+10.75 V) Channel 0
Device Under Test Channel 0
Driver Output Supply (−5.0 V) Channel 0
PMU External Sense Path Channel 0
High Voltage Driver Output
Temperature Sense Supply (+10.75 V)
PMU Stability Capacitor Connection Channel 1 (330 pF)
Supply (−5.0 V)
B2
B3
VSS
B4
AGND
Analog Ground
B5
VDD
Supply (+10.75 V)
B6
VDD
Supply (+10.75 V)
B7
AGND
Analog Ground
B8
VSS
Supply (−5.0 V)
B9
SCAP0
VPLUS
PMU Stability Capacitor Connection Channel 0 (330 pF)
Supply (+16.75 V)
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D8
D9
D10
E1
FFCAP_1B
AGND
DATA1N
VSS
VDD
VDD
VSS
DATA0N
AGND
FFCAP_0B
OVD_CH1
VDD
DATA1P
DATA0P
VDD
PMU Feedforward Capacitor Connection B Channel 1 (220 pF)
Analog Ground
Driver Data Input (Negative) Channel 1
Supply (−5.0 V)
Supply (+10.75 V)
Supply (+10.75 V)
Supply (−5.0 V)
Driver Data Input (Negative) Channel 0
Analog Ground
PMU Feedforward Capacitor Connection B Channel 0 (220 pF)
Overvoltage Detection Flag Output Channel 1
Supply (+10.75 V)
Driver Data Input (Positive) Channel 1
Driver Data Input (Positive) Channel 0
Supply (+10.75 V)
OVD_CH0
FFCAP_1A
VSS
Overvoltage Detection Flag Output Channel 0
PMU Feedforward Capacitor Connection A Channel 1 (220 pF)
Supply (−5.0 V)
E2
E3
E8
E9
RCV1N
RCV0N
VSS
Receive Data Input (Negative) Channel 1
Receive Data Input (Negative) Channel 0
Supply (−5.0 V)
E10
F1
FFCAP_0A
AGND
PMU Feedforward Capacitor Connection A Channel 0 (220 pF)
Analog Ground
F2
AGND
Analog Ground
F3
F8
F9
RCV1P
RCV0P
AGND
Receive Data Input (Positive) Channel 1
Receive Data Input (Positive) Channel 0
Analog Ground
F10
G1
G2
G3
G8
AGND
Analog Ground
COMP_QL1P
COMP_QL1N
COMP_VTT1
COMP_VTT0
Low-Side Comparator Output (Positive) Channel 1
Low-Side Comparator Output (Negative) Channel 1
Comparator Supply Termination Channel 1
Comparator Supply Termination Channel 0
Rev. 0 | Page 21 of 52
ADATE304
Pin No.
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
J1
Mnemonic
COMP_QL0N
COMP_QL0P
COMP_QH1P
COMP_QH1N
AGND
VSS
VDD
VDD
VSS
Description
Low-Side Comparator Output (Negative) Channel 0
Low-Side Comparator Output (Positive) Channel 0
High-Side Comparator Output (Positive) Channel 1
High-Side Comparator Output (Negative) Channel 1
Analog Ground
Supply (−5.0 V)
Supply (+10.75 V)
Supply (+10.75 V)
Supply (−5.0 V)
AGND
Analog Ground
COMP_QH0N
COMP_QH0P
AGND
High-Side Comparator Output (Negative) Channel 0
High-Side Comparator Output (Positive) Channel 0
Analog Ground
J2
AGND
Analog Ground
J3
AGND
Analog Ground
J4
J5
DAC16_MON
DGND
16-Bit DAC Monitor Mux Output
Digital Ground
J6
J7
SDIN
RST
Serial Peripheral Interface (SPI) Data In
Serial Peripheral Interface (SPI) Reset
Analog Ground
J8
AGND
J9
AGND
Analog Ground
J10
K1
AGND
Analog Ground
MEASOUT01/TEMPSENSE
Muxed Output Shared by PMU MEASOUT Channel 0, PMU MEASOUT Channel 1/
Temperature Sense and Temperature Sense GND Reference
K2
K3
K4
K5
K6
K7
K8
K9
K10
DUTGND
AGND
CS
DUT Ground Reference
Analog Ground
Serial Peripheral Interface (SPI) Chip Select
Serial Peripheral Interface (SPI) Data Out
Serial Peripheral Interface (SPI) Clock
Supply (+3.3 V)
Analog Ground
+5 V DAC Reference Voltage
DAC Ground Reference
SDOUT
SCLK
VCC
AGND
VREF
VREF_GND
Rev. 0 | Page 22 of 52
ADATE304
TYPICAL PERFORMANCE CHARACTERISTICS
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.30
0.5V
0.25
3V
2V
0.20
0.15
0.2V
0.10
1V
0.05
0
–0.2
–0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
TIME (ns)
Figure 3. Driver Small Signal Response; VH = 0.2 V, 0.5 V;
VL = 0.0 V; 50 Ω Termination
Figure 6. 50 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V, 50 Ω Termination
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3V
2V
1V
3V
2V
1V
–0.2
–0.2
0
2
4
6
8
10
12
14
16
18
20
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
TIME (ns)
TIME (ns)
Figure 7. 100 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
Figure 4. Driver Large Signal Response; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
1.6
6
3V
2V
5V
1.4
1.2
1.0
0.8
0.6
5
4
3V
3
2
1V
1V
1
0.4
0.2
0
0
–1
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
TIME (ns)
Figure 8. Response at 200 MH; VH = 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
Figure 5. Driver Large Signal Response; VH = 1.0 V, 3.0 V, 5.0 V;
VL = 0.0 V; 500 Ω Termination
Rev. 0 | Page 23 of 52
ADATE304
0.6
0.5
0.4
0.3
0.2
0.1
0
1.6
3V
2V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1V
0.5V
–0.1
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
0
1
2
3
4
5
6
7
8
9
10
TIME (ns)
TIME (ns)
Figure 9. 300 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V;
VL = 0.0 V; 50 Ω Termination
Figure 12. Driver Active (VH and VL) to and from VTERM Transition;
VH = 1.0 V, VT = 0.5 V, VL = 0.0 V
1.0
1.2
1.0
0.8
0.6
0.4
0.2
0
2V
0.9
0.8
0.7
0.6
0.5
1V
0.4
0.3
0.5V
0.2
0.1
0
–0.2
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5 5.0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
TIME (ns)
TIME (ns)
Figure 10. 400 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V,
VL = 0.0 V; 50 Ω Termination
Figure 13. Driver Active (VH and VL) to and from VTERM Transition;
VH = 2.0 V, VT = 1.0 V, VL = 0.0 V
1.2
1.6
1.4
1.2
1.0
1.0
0.8
0.6
0.8
0.6
0.4
0.4
0.2
0
0.2
0
–0.2
200
250
300
350
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
TIME (ns)
Figure 11. Driver Toggle Rate, VH = 2.0 V, VL = 0.0 V, 50 Ω Termination
Figure 14. Driver Active (VH and VL) to and from VTERM Transition;
VH = 3.0 V, VT = 1.5 V, VL = 0.0 V
Rev. 0 | Page 24 of 52
ADATE304
20
20
0
2V POS
0.2V NEG
0.2V POS
0
2V NEG
–20
–40
–60
–80
–100
–20
–40
–60
–80
1
2
3
4
5
6
7
8 9 10
1
2
3
4
5
6
7
8 9 10
PULSEWIDTH (ns)
PULSEWIDTH (ns)
Figure 15. Driver Minimum Pulse Width; VH = 0.2 V, VL = 0.0 V
Figure 18. Driver Minimum Pulse Width; VH = 2.0 V, VL = 0.0 V
20
20
0
3V POS
0
0.5V NEG
–20
0.5V POS
3V NEG
–20
–40
–60
–80
–40
–60
–80
–100
1
2
3
4
5
6
7
8 9 10
1
2
3
4
5
6
7
8 9 10
PULSEWIDTH (ns)
PULSE WIDTH (ns)
Figure 16. Driver Minimum Pulse Width; VH = 0.5 V, VL = 0.0 V
Figure 19. Driver Minimum Pulse Width; VH = 3.0 V, VL = 0.0 V
20
1.0
1V NEG
0.5
0
0
1V POS
–20
–0.5
–1.0
–1.5
–2.0
–40
–60
–80
–100
1
2
3
4
5
6
7
8
9 10
–2
–1
0
1
2
3
4
5
6
7
PULSEWIDTH (ns)
DRIVER OUTPUT VOLTAGE (V)
Figure 20. Driver VH Linearity Error
Figure 17. Driver Minimum Pulse Width; VH = 1.0 V, VL = 0.0 V
Rev. 0 | Page 25 of 52
ADATE304
1.0
120
100
80
0.5
0
60
40
–0.5
–1.0
–1.5
20
0
–20
–2
–2
–1
0
1
2
3
4
5
6
–1
0
1
2
3
4
5
6
7
DRIVER OUTPUT VOLTAGE (V)
V
(V)
DUTx
Figure 24. Driver Output Current Limit; Driver Programmed to −1.25 V;
VDUTx Swept from −1.25 V to +6.75 V
Figure 21. Driver VL Linearity Error
20
0.8
0.6
0.4
0
–20
–40
–60
–80
–100
–120
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–2
–1
0
1
2
3
4
5
6
7
–2
–1
0
1
2
3
4
5
6
7
V
(V)
DUTx
DRIVER OUTPUT VOLTAGE (V)
Figure 22. Driver VT Linearity Error
Figure 25. Driver Output Current Limit; Driver Programmed to 6.75 V;
DUTx Swept from −1.25 V to +6.75 V
V
48.0
47.8
47.6
47.4
47.2
47.0
46.8
46.6
46.4
46.2
8
7
6
5
4
3
2
1
0
–1
–2
–3
–60
–40
–20
0
20
40
60
–1
0
1
2
3
4
5
6
DRIVER OUTPUT CURRENT (mA)
VL PROGRAMMED VOLTAGE (V)
Figure 26. HVOUT VL Linearity Error
Figure 23. Driver Output Resistance vs. Output Current
Rev. 0 | Page 26 of 52
ADATE304
1.0
0.8
0.6
3
2
RISE INPUT
1
0
RISE SHMOO
–1
–2
–3
–4
–5
–6
–7
0.4
0.2
0
FALL SHMOO
FALL INPUT
1.2
0
0.6
1.8
2.4
3.0
5
6
7
8
9
10
11
12
13
14
TIME (ns)
VL PROGRAMMED VOLTAGE (V)
Figure 27. HVOUT VHH Linearity Error
Figure 30. Comparator Shmoo, 1.0 V Input, 0.7 ns (10% to 90%) Input,
50 Ω Terminated
80
70
60
50
40
30
20
10
0
1.0
RISE INPUT
0.8
RISE SHMOO
0.6
0.4
FALL SHMOO
0.2
FALL INPUT
1.8
0
–10
–1
0
1
2
3
4
5
6
0
0.6
1.2
2.4
3.0
V
(V)
TIME (ns)
HVOUT
Figure 28. HVOUT VH Current Limit; VH = −0.1 V;
VHVOUT Swept from −0.1 V to +6.0 V
Figure 31. Comparator Shmoo, 1.5 V Input, 1.0 ns (10% to 90%) Input,
50 Ω Terminated
80
1.6
RISE INPUT
60
40
20
0
1.2
RISE SHMOO
0.8
–20
–40
–60
–80
0.4
0
FALL SHMOO
FALL INPUT
5
6
7
8
9
10
11
(V)
12
13
14
15
0
0.6
1.2
TIME (ns)
1.8
2.4
3.0
V
HVOUT
Figure 29. HVOUT VHH Current Limit; VHH = 10.0 V;
HVOUT Swept from −5.9 V to +14.1 V
Figure 32. Comparator Shmoo, 1.5 V Input, 1.0 ns (10% to 90%) Input,
50 Ω Terminated
V
Rev. 0 | Page 27 of 52
ADATE304
10
0.6
0.4
0.2
0
0
–10
–20
–30
–40
–0.2
–0.4
–0.6
1V POS
–0.8
–1.0
–50
–60
–70
1V NEG
–1.2
–1.4
–1.6
1
2
3
4
5
6
7
8
9 10
–2
–1
0
1
2
3
4
5
6
7
PULSEWIDTH (ns)
PROGRAMMED THRESHOLD VOLTAGE (V)
Figure 33. Comparator Minimum Pulse Width, 1.0 V
Figure 36. Comparator Threshold Linearity
100
75
–2.5
–2.6
–2.7
–2.8
–2.9
–3.0
–3.1
–3.2
TOTAL
50
25
0
RISING
FALLING
–25
–50
0.5
1.0
1.5
2.0
2.5
–2
–1
0
1
2
3
4
5
INPUT SLEWRATE (10%-90%) (ns)
INPUT COMMON-MODE VOLTAGE (V)
Figure 34. Comparator Slew Rate Dispersion, Input Swing = 1.5 V,
Comparator Threshold = 0.75 V
Figure 37. Differential Comparator CMRR
15
10
5
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
–5
–10
–15
–2
–1
0
1
2
3
4
5
6
0
5
10
15
20
25
30
35
40
45
50
V
(V)
DUTx
TIME (ns)
Figure 38. Active Load Commutation Response; VCOM = 2.0 V;
IOH = IOL = 12 mA
Figure 35. Comparator Output Waveform, COMP_QH0P, COMP_QH0N
Rev. 0 | Page 28 of 52
ADATE304
6
4
6
5
4
3
2
1
0
2
0
–2
–4
–6
0
2
4
6
8
10
12
–2
–1
0
1
2
3
4
5
6
7
ACTIVE LOAD CURRENT (mA)
V
(V)
DUTx
Figure 39. Active Load Current Linearity
Figure 42. DUTx Pin Leakage in High-Z Mode
40
20
0.8
0.6
0.4
0
0.2
0
–20
–40
–60
–80
–100
–120
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–40
–30
–20
–10
0
10
20
30
40
–1
0
1
2
3
4
5
6
7
PMU OUTPUT CURRENT (mA)
VCOM VOLTAGE (V)
Figure 43. PMU Force Current Range A Linearity
Figure 40. Active Load VCOM Linearity
0.8
0.6
6.0
5.5
5.0
4.5
4.0
3.5
3.0
0.4
0.2
0
–0.2
–0.4
–0.6
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–2
–1
0
1
2
3
4
5
6
7
PMU OUTPUT CURRENT (mA)
V
(V)
DUTx
Figure 44. PMU Force Current Range B Linearity
Figure 41. DUTx Pin Leakage in Low Leakage Mode
Rev. 0 | Page 29 of 52
ADATE304
4
3
0.06
0.04
0.02
0
2
1
0
–1
–2
–3
–4
–0.02
–0.04
–0.06
–40
–30
–20
–10
0
10
20
30
40
–0.20 –0.15 –0.10 –0.05
0
0.05
0.10
0.15
0.20
I
(mA)
PMU OUTPUT CURRENT (mA)
DUTx
Figure 45. PMU Force Current Range C Linearity
Figure 48. PMU Force Voltage Range A Output Voltage Error at
6.75 V vs. Output Current
0.006
0.004
0.002
0
4
3
2
1
0
–1
–2
–3
–4
–0.002
–0.004
–0.006
–0.020 –0.015 –0.010 –0.005
0
0.005 0.010 0.015 0.020
–40
–30
–20
–10
0
10
20
30
40
PMU OUTPUT CURRENT (mA)
I
(mA)
DUTx
Figure 46. PMU Force Current Range D Linearity
Figure 49. PMU FV Range A Output Voltage Error at −1.25 V
vs. Output Current
0.6
0.0006
0.0004
0.0002
0
0.4
0.2
0
–0.0002
–0.0004
–0.0006
–0.0008
–0.2
–0.4
–0.6
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–0.0020 –0.0015 –0.0010 –0.0050
0
0.0050 0.0010 0.0015 0.0020
I
(mA)
PMU OUTPUT CURRENT (mA)
DUTx
Figure 47. PMU Force Current Range E Linearity
Figure 50. PMU FV Range B Output Voltage Error at 6.75 V vs. Output Current
Rev. 0 | Page 30 of 52
ADATE304
0.6
0.4
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.2
0
–0.2
–0.4
–0.6
–0.1
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–2
–1
0
1
2
3
4
5
6
7
I
(mA)
V
(V)
DUTx
DUTx
Figure 51. PMU FV Range B Output Voltage Error at −1.25 V
vs. Output Current
Figure 54. PMU FI Range B Output Current Error at −2 mA vs. Output Voltage;
Output Voltage Is Pulled Externally
5
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
–5
–10
–15
–20
–25
–30
–0.1
–0.2
–0.3
–2
–1
0
1
2
3
4
5
6
7
–2
–1
0
1
2
3
4
5
6
7
V
(V)
V
(V)
DUTx
DUTx
Figure 52. PMU FI Range A Output Current Error at −32 mA vs. Output
Voltage; Output Voltage Is Pulled Externally
Figure 55. PMU FI Range B Output Current Error at +2 mA vs. Output Voltage;
Output Voltage Is Pulled Externally
10
0
0.0025
0.0020
0.0015
0.0010
0.0005
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–0.0005
–0.0010
–2
–1
0
1
2
3
4
5
6
7
–2
–1
0
1
2
3
4
5
6
7
V
(V)
V
(V)
DUTx
DUTx
Figure 56. PMU FI Range E Output Current Error at −2 μA vs. Output Voltage;
Output Voltage Is Pulled Externally
Figure 53. PMU FI Range A Output Current Error at +32 mA vs. Output
Voltage; Output Voltage Is Pulled Externally
Rev. 0 | Page 31 of 52
ADATE304
0.0020
0.0015
0.0010
0.0005
0
C1
–0.0005
–2
–1
0
1
2
3
4
5
6
7
(500ps/DIV)
V
(V)
DUTx
Figure 57. PMU FI Range E Output Current Error at +2 μA vs. Output Voltage;
Output Voltage Is Pulled Externally
Figure 60. Eye Diagram, 400 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
0.5
0.4
0.3
0.2
0.1
0
C1
–0.1
(200ps/DIV)
–2
–1
0
1
2
3
4
5
V
(V)
DUTx
Figure 61. Eye Diagram, 600 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
Figure 58. PMU Measure Current Range B CMRR,
Externally Pulling 1 mA, FVMI
C1
C1
(500ps/DIV)
(1ns/DIV)
Figure 59. Eye Diagram, 200 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
Figure 62. Eye Diagram, 400 Mbps, PRBS31; VH = 2.0 V, VL = 0.0 V
Rev. 0 | Page 32 of 52
ADATE304
SPI DETAILS
tCH
SCLK
tCL
tCSSA
tCSSD
tCSHA
tCSHD
CS
tCSW
tDH
tDS
DATA[15]
DATA[14]
ADDR[1]
ADDR[0]
CH[1]
R/W
LAST
SDIN
DO_15
DO_14
DO_13
DO_12
DO_2
DO_1
DO_0
LAST
SDOUT
LAST
LAST
LAST
LAST
LAST
t
DO
Figure 63. SPI Timing Diagram
Table 17. Serial Peripheral Interface Timing Requirements
Symbol
Parameter
Min
9.0
9.0
3.0
3.0
3.0
3.0
3.0
3.0
Max
Unit
tCH
tCL
SCLK minimum high
SCLK minimum low
CS assert hold
ns
ns
ns
tCSHA
tCSSA
tCSHD
tCSSD
tDH
CS assert setup
ns
CS deassert hold
ns
CS deassert setup
SDIN hold
SDIN setup
ns
ns
ns
tDS
tDO
tCSW
SDOUT data out
15.0
ns
CS minimum between assertions1
2
SCLK cycles
SCLK cycles
SCLK cycles
CS minimum directly after a read request
3
tCSTP
Minimum delay after CS is deasserted before SCLK can be
stopped (not shown in Figure 63); this allows any internal
operations to complete
16
1 An extra cycle is needed after a read request to prime the read data into the SPI shift register.
Rev. 0 | Page 33 of 52
ADATE304
DEFINITION OF SPI WORD
Table 18. Channel Selection
The SPI can accept variable length words, depending on the
operation. At most, the word length equals 24 bits: 16 bits of
data, two channel selects, one read/write (R/W) selector, and a
5-bit address.
Channel 1 Channel 0 Channel Selected
0
0
NOP (no channel selected, no register
changes)
0
1
1
1
0
1
Channel 0 selected
Channel 1 selected
Channel 0 and Channel 1 selected
Depending on the operation, the data can be smaller or, in the
case of a read operation, nonexistent.
Table 19. R/W Definition
R/W
Description
0
Current register specified by address shifts out of
SDOUT on next shift operation
1
Current data written to the register specified by
address and channel select
Example 1: 16-Bit Write
Write 16 bits of data to a register or DAC; ignore unused MSBs. For example, Bit 15 and Bit 14 are ignored, and Bit 13 through Bit 0 are
applied to the 14-bit DAC.
DATA[15:0]
DATA[13:0]
DATA[1:0]
CH[1:0]
R/W
ADDR[4:0]
Figure 64. 16-Bit Write
Example 2: 14-Bit Write
Write 14 bits of data to the DAC.
CH[1:0]
R/W
ADDR[4:0]
Figure 65. 14-Bit Write
Example 3a: 2-Bit Write
Write two bits of data to the 2-bit register.
CH[1:0]
R/W
ADDR[4:0]
Figure 66. 2-Bit Write
Example 3b: 2-Bit Write
Write two bits of data to the 2-bit register. Bit 15 through Bit 2 are ignored and Bit 1 through Bit 0 are applied to the register.
DATA[15:0]
CH[1:0]
R/W
ADDR[4:0]
Figure 67. 2-Bit Write
Example 4: Read Request
Read request and follow with a second instruction (could be NOP) to clock out the data.
CH[1:0]
CH[1:0]
R/W = 0
R/W
ADDR[4:0]
ADDR[4:0]
DATA[15:0]
Figure 68. Read Request
Rev. 0 | Page 34 of 52
ADATE304
WRITE OPERATION
CS
INPUT
SCLK
INPUT
DATA[15] DATA[14] DATA[13]
DATA[2] DATA[1] DATA[0] CH[1]
CH[0]
17
R/W
18
ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
X
SDIN
INPUT
0
1
2
13
14
15
16
19
20
21
22
23
24
25
SDOUT
OUTPUT
X
NOTES
1. R/W = 1.
2. X = DON’T CARE.
Figure 69. 16-Bit SPI Write
CS
INPUT
SCLK
INPUT
DATA[1] DATA[0] CH[1]
CH[0]
3
R/W
4
ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
X
SDIN
INPUT
0
1
2
5
6
7
8
9
10
11
SDOUT
OUTPUT
X
NOTES
1. R/W = 1.
2. X = DON’T CARE.
Figure 70. 2-Bit SPI Write
Rev. 0 | Page 35 of 52
ADATE304
the previous specified data. The NOP address can be used for
this read if there is no need to read/write another register. To
maintain the clarity of the operation, it is strongly recommended
that the NOP address be used for all reads.
READ OPERATION
The read operation is a two-stage operation. First, a word is
shifted in, specifying which register to read.
for three clock cycles, and then a second word is shifted in to
obtain the readback data. This second word can be either
another operation or an NOP address. If another operation is
shifted in, it must shift in at least eight bits of data to read back
CS
is deasserted
Any register read that is fewer than 16 bits has zeros filled in the
top bits to make it a 16-bit word.
CS
INPUT
SCLK
INPUT
SDIN
INPUT
READ INSTRUCTION
X
NOP
X
SDOUT
OUTPUT
X
READ DATA
X
NOTES
1. X = DON’T CARE.
Figure 71. SPI Read Overview
CS
INPUT
SCLK
INPUT
SDIN
INPUT
ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
19 20 21 22 23
DATA[15:0], VALUE IS A DON’T CARE
13 14
CH[1]
16
CH[0]
17
R/W
18
X
0
1
2
15
24
25
SDOUT
OUTPUT
X
NOTES
1. X = DON’T CARE.
Figure 72. SPI Read—Details of Read Request
CS
INPUT
SCLK
INPUT
SDIN
DATA[15:0], VALUE IS A DON’T CARE
13 14
CH[1]
16
CH[0]
17
R/W = 1
18
ADDR[4:0] = 0x00 (NOP)
X
INPUT
0
1
2
15
19
20
21
X
22
23
24
25
SDOUT
OUTPUT
RDATA[15] RDATA[14]
RDATA[2] RDATA[1] RDATA[0]
NOTES
1. RDATA IS THE REGISTER VALUE BEING READ.
2. X = DON’T CARE.
Figure 73. SPI Read—Details of Read Out
Rev. 0 | Page 36 of 52
ADATE304
RST
by utilizing the
pin. To initiate the reset operation, deassert
RESET OPERATION
RST
CS
pin
the
pin for a minimum of 100 ns and deassert the
The ADATE304 contains an asynchronous reset feature. The
ADATE304 can be reset to the default values shown in Table 20
for a minimum of two SCLK cycles.
100ns
MINIMUM
RST
CS
SCLK
MINIMUM OF TWO SCLK EDGES AFTER ASSERTING RST BEFORE RESUMING NORMAL OPERATION.
Figure 74. Reset Operation
Rev. 0 | Page 37 of 52
ADATE304
REGISTER MAP
The ADDR[4:0] bits determine the destination register of the data being written to the ADATE304.
Table 20. Register Selection
DATA[15:0]
N/A1
CH[1:0]
R/W
N/A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
ADDR[4:0]
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
Register Selected
NOP
VH DAC level
VL DAC level
VT/VCOM DAC level
VOL DAC level
VOH DAC level
VCH DAC level
VCL DAC level
V(IOH ) DAC level
V(IOL ) DAC level
OVD high level
OVD low level
Reset State
N/A
N/A
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[13:0]
DATA[15:0]
DATA[2:0]
DATA[2:0]
DATA[9:0]
DATA[2:0]
DATA[0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1]
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
4096d
16384d
000b
000b
0d
000b
0b
00b
01b
N/A
N/A
CH[0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
CH[1:0]
N/A
PMUDAC level
PE/PMU enable
Channel state
PMU state
PMU measure enable
Differential comparator enable
16-bit DAC monitor
OVD_CHx alarm mask
OVD_CHx alarm state
Reserved
DATA[1:0]
DATA[1:0]
DATA[2:0]
N/A
0x11
0x12
0x13
0x14 to 0x1F
N/A
1 N/A means not applicable.
Rev. 0 | Page 38 of 52
ADATE304
DETAILS OF REGISTERS
Table 21. PE/PMU Enable (ADDR[4:0] = 0x0C)
Bit
Name
Description
DATA[2]
PMU enable
0 = disable PMU force output and clamps, place PMU in MV mode
1 = enable PMU force output
When set to 0, the PMU state bits are ignored, except for the PMU sense path (DATA[7])
0 = normal driver operation
1 = force driver to VT
See Table 29 for complete functionality of this bit
0 = enable driver functions
DATA[1]
DATA[0]
Force VT
PE disable
1 = disable driver (low leakage)
See Table 29 for complete functionality of this bit
Table 22. Channel State (ADDR[4:0] = 0x0D)
Bit
Name
Description
DATA[2]
HV mode select
0 = HV driver in low impedance.
1 = enable HV driver.
This bit affects Channel 0 only. Ensure that the Channel 0 bit in SPI write is active.
Channel 1 bit in SPI write is don’t care.
DATA[1]
DATA[0]
Load enable
0 = disable load.
1 = enable load.
See Table 29 for complete functionality of this bit.
0 = enable Driver high-Z function.
1 = enable Driver VTERM function.
See Table 29 for complete functionality of this bit.
Driver high-Z or VT
Table 23. PMU State (ADDR[4:0] = 0x0E)1, 2
Bit
Name
Description
DATA[9:8]
PMU input selection
00 = VDUTGND (calibrated for 0.0 V voltage reference)
01 = 2.5 V + VDUTGND (calibrated for 0.0 A current reference)
1X = PMUDAC
DATA[7]
PMU sense path
0 = internal sense
1 = external sense
DATA[6]
DATA[5]
Reserved
PMU clamp enable
0 = disable clamps
1 = enable clamps
DATA[4]
DATA[3]
DATA[2:0]
PMU measure voltage or current
PMU force voltage or current
PMU range
0 = measure voltage mode
1 = measure current mode
0 = force voltage mode
1 = force current mode
0XX = 2 μA range
100 = 20 μA range
101 = 200 μA range
110 = 2 mA range
111 = 32 mA range
1 Note that when ADDR[4:0] = 0x0C, the PMU enable bit (DATA[2]) = 0, PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage mode.
PMU State DATA[9:8] and DATA[6:0] are ignored, and only the DATA[7] PMU sense path is valid.
2 X means don’t care.
Rev. 0 | Page 39 of 52
ADATE304
Table 24. PMU Measure Enable (ADDR[4:0] = 0x0F)1
Bit
Name
Description
DATA[2:1]
MEASOUT01 select
00 = PMU MEASOUT Channel 0
01 = PMU MEASOUT Channel 1
10 = Temperature sensor ground reference
11 = Temperature sensor
DATA[0]
MEASOUT01 output enable
0 = MEASOUT01 is tristated
1 = MEASOUT01 is enabled
1 This register is written to or read from when either of the CH[1:0] bits is 1.
Table 25. Differential Comparator Enable (ADDR[4:0] = 0x10)1
Bit
Name
Description
DATA[0]
Differential Comparator Enable
0 = differential comparator is disabled; the Channel 0 normal window
comparator (NWC) outputs are located on Channel 0
1 = differential comparator is enabled; the differential comparator outputs
are located on Channel 0
1 This register is written to or read from when either of the CH[1:0] bits is 1.
Table 26. DAC16_MON (16-Bit DAC Monitor) (ADDR[4:0] = 0x11)1
Bit
Name
Description
DATA[1]
16-Bit DAC mux enable
0 = 16-bit DAC mux is tristated
1 = 16-bit DAC mux is enabled
0 = 16-bit DAC Channel 0
1 = 16-bit DAC Channel 1
DATA[0]
16-Bit DAC mux select
1 This register is written to or read from when either of the CH[1:0] bits is 1.
Table 27. OVD_CHx Alarm Mask (ADDR[4:0] = 0x12)
Bit
Name
Description
DATA[1]
PMU mask
0 = disable PMU alarm flag
1 = enable PMU alarm flag
0 = disable OVD alarm flag
1 = enable OVD alarm flag
DATA[0]
OVD mask
Table 28. OVD_CHx Alarm State (ADDR[4:0] = 0x13)1
Bit
Name
Description
DATA[2]
PMU clamp flag
0 = PMU is not clamped
1 = PMU is clamped
DATA[1]
DATA[0]
OVD high flag
OVD low flag
0 = DUT voltage < OVD high voltage
1 = DUT voltage > OVD high voltage
0 = DUT voltage > OVD low voltage
1 = DUT voltage < OVD low voltage
1 This register is a read-only register.
Rev. 0 | Page 40 of 52
ADATE304
USER INFORMATION
Power Supply Decoupling
POWER SUPPLY CONSIDERATIONS
Power Supply Sequencing
The ADATE304 is a high performance device that requires
close attention to power supply decoupling to deliver the best
performance. The use of full power planes with low inductance
capacitors placed as close to the power pins as possible is recom-
mended. The following power connections are the most important:
It is recommended that the power supplies be brought up in the
following order:
1. Grounds (DGND, AGND, VREF_GND)
2. VSS
•
•
•
VPLUS to AGND (for the HVOUT driver)
VDD to VSS near the DUTx pin (for the driver)
VDD and VSS to AGND near the DUTx pin (for the
comparators)
3.
VCC, VCOMP_VTT, and VREF
4. VDD
5. VPLUS
If the HVOUT pin is not used, the VPLUS supply can be
•
VCC to DGND (for the digital)
connected to VDD
.
Additionally, large bulk capacitors (that is, 10 μF) should be
used on every power supply on the printed circuit board (PCB).
TRUTH TABLES
Table 29. Driver and Load Truth Table1
Registers
Load Enable
DATA[1]
Signals
PE Disable
DATA[0]
Force VT
DATA[1]
Driver High-Z/VT
DATA[0]
ADDR[4:0] = 0x0C ADDR[4:0] = 0x0C ADDR[4:0] = 0x0D ADDR[4:0] = 0x0D DATAx RCVx Driver State
Load State
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
High-Z without clamps Power-down
VT
Power-down
Power-down
Power-down
Power-down
Power-down
Power-down
Power-down
Power-down
Power-down
Active off
VL
High-Z with clamps
VH
High-Z with clamps
VL
VT
VH
VT
VL
High-Z with clamps
Active on
VH
Active off
High-Z with clamps
VL
Active on
Active on
High-Z with clamps
VH
Active on
Active on
High-Z with clamps
Active on
1 X means don’t care.
Table 30. HVOUT Truth Table1
HVOUT Mode Select
DATA[2]
ADDR[4:0] =0x0D
Channel 0
RCV
Channel 0
DATA
HVOUT Driver Output
1
1
1
0
1
0
0
X
X
0
1
X
VHH mode; VHH = (VT + 1 V) × 2 + DUTGND (Channel 0 VT DAC)
VL (Channel 0 VL DAC)
VH (Channel 0 VH DAC)
Disabled (HVOUT pin set to 0 V low impedance)
1 X means don’t care.
Rev. 0 | Page 41 of 52
ADATE304
Table 31. Comparator Truth Table
Differential
Comparator Enable
DATA[0]
ADDR[4:0] = 0x10
COMP_QH0
COMP_QL0
COMP_QH1
COMP_QL1
0
Normal window mode
Logic high: VOH0 < VDUT0
Logic low: VOH0 > VDUT0
Normal window mode
Logic high: VOL0 < VDUT0
Logic low: VOL0 > VDUT0
Normal window mode
Normal window mode
Logic high: VOH1 < VDUT1 Logic high: VOL1 < VDUT1
Logic low: VOH1 > VDUT1 Logic low: VOL1 > VDUT1
1
Differential comparator mode Differential comparator mode Normal window mode
Normal window mode
Logic high: VOH0 < VDUT0 − VDUT1 Logic high: VOL0 < VDUT0 − VDUT1 Logic high: VOH1 < VDUT1 Logic high: VOL1 < VDUT1
Logic low: VOH0 > VDUT0 − VDUT1
Logic low: VOL0 > VDUT0 − VDUT1
Logic low: VOH1 > VDUT1 Logic low: VOL1 > VDUT1
Rev. 0 | Page 42 of 52
ADATE304
•
•
−3.0 V to +7.0 V and tracks DUTGND. Controls the
OVD levels.
−2.5 V to +7.5 V and does not track DUTGND. Controls
the IOH and IOL levels.
DETAILS OF DACS vs. LEVELS
There are ten 14-bit DACs per channel. These DACs provide
levels for the driver, comparator, load currents, VHH buffer, OVD,
and clamp levels. There are three versions of output levels as
follows:
There is one 16-bit DAC per channel. This DAC provides the
levels for the PMU. The output level is as follows:
•
−2.5 V to +7.5 V and tracks DUTGND. Controls the VH,
VL, VT/VCOM/VHH, VOH, VOL, VCH, and VCL levels.
•
−2.5 V to +7.5 V and tracks DUTGND; controls the
PMU levels.
Table 32. Level Transfer Functions
Programmable Range1
DAC Transfer Function
(All 0s to All 1s)
Levels
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(214)) − 0.5 × (VREF − VREF_GND) + VDUTGND
−2.5 V to +7.5 V
VH, VL, VT/VCOM,
VOL, VOH, VCH, VCL
Code = [VOUT − VDUTGND + 0.5 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
VOUT = 4.0 × (VREF − VREF_GND) × (Code/(214)) − 1.0 × (VREF − VREF_GND) + 2.0 + VDUTGND
Code = [VOUT − VDUTGND − 2.0 + 1.0 × (VREF − VREF_GND)] × [(214)/(4.0 × (VREF − VREF_GND))]
−3.0 V to +17.0 V
−3.0 V to +7.0 V
VHH
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(214)) − 0.6 × (VREF − VREF_GND) + VDUTGND
OVD
Code = [VOUT − VDUTGND + 0.6 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(214)) − 0.5 × (VREF − VREF_GND)] × (0.012/5.0)
Code = [(IOUT × (5.0/0.012)) + 0.5 × (VREF − VREF_GND)] × [(214)/(2.0 × (VREF − VREF_GND))]
−6 mA to +18 mA
−2.5 V to +7.5 V
IOH, IOL
PMUDAC
VOUT = 2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) + VDUTGND
Code = [VOUT − VDUTGND + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) − 2.5] × (0.050/5.0)
Code = [(IOUT × (5.0/0.050)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
−50 mA to +50 mA
−4 mA to +4 mA
−400 μA to +400 μA
−40 μA to +40 μA
−4 μA to +4 μA
PMUDAC
(PMU FI Range A)
PMUDAC
(PMU FI Range B)
PMUDAC
(PMU FI Range C)
PMUDAC
(PMU FI Range D)
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) − 2.5] × (0.004/5.0)
Code = [(IOUT × (5.0/0.004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) − 2.5] × (0.0004/5.0)
Code = [(IOUT × (5.0/0.0004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) − 2.5] × (0.00004/5.0)
Code = [(IOUT × (5.0/0.00004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
IOUT = [2.0 × (VREF − VREF_GND) × (Code/(216)) − 0.5 × (VREF − VREF_GND) − 2.5] × (0.000004/5.0)
Code = [(IOUT × (5.0/0.000004)) + 2.5 + 0.5 × (VREF − VREF_GND)] × [(216)/(2.0 × (VREF − VREF_GND))]
PMUDAC
(PMU FI Range E)
1 Programmable range includes a margin outside the specified part performance, allowing for offset/gain calibration.
Table 33. Load Transfer Functions
Load Level
IOL
Transfer Function1
V(IOL)/5 V × 12 mA
V(IOH)/5 V × 12 mA
IOH
1 V(IOH)and V(IOL) DAC levels are not referenced to DUTGND.
Table 34. PMU Transfer Functions
PMU Mode
Transfer Functions
Force Voltage
VOUT = PMUDAC
Measure Voltage
Force Current
VMEASOUT01 = VDUTx (internal sense) or VMEASOUT01 = VPMUS_CHx (external sense)
IOUT = [PMUDAC − (VREF/2)]/(R1 × 5)
VMEASOUT01 = (VREF/2) + VDUTGND + (IDUTx × 5 × R1)
Measure Current
1 R = 15.5 Ω for Range A; 250 Ω for Range B; 2.5 kΩ for Range C; 25 kΩ for Range D; 250 kΩ for Range E.
Table 35. PMU User Required Capacitors
Capacitor
Location
220 pF
Across Pin C10 (FFCAP_0B) and Pin E10 (FFCAP_0A)
Across Pin C1 (FFCAP _1B) and Pin E1 (FFCAP_1A)
Between GND and Pin B9 (SCAP0)
Between GND and Pin B2 (SCAP1)
220 pF
330 pF
330 pF
Rev. 0 | Page 43 of 52
ADATE304
Table 36. Temperature Sensor
Temperature
Output
0 K
0 V
300 K
x K
3 V
(x K) × 10 mV/K
Table 37. Power Supply Ranges
Parameter
Range 1
+10.75 V
−5.00 V
Range 2
+10.0 V
−5.75 V
Nominal VDD
Nominal VSS
Driver
VH range
−1.15 V to +6.75 V
−1.25 V to +6.65 V
−1.25 V to +6.75 V
8.0 V
−1.9 V to +6.0 V
−2.0 V to +5.9 V
−2.0 V to +6.0 V
8.0 V
VL range
VT range
Functional Amplitude
Reflection Clamp
VCH Range
−1.0 V to +6.75 V
−1.25 V to +5.75 V
−1.25 V to +6.75 V
−1.00 V to +6.50 V
−1.0 V to +6.0 V
−2.0 V to +5.0 V
−2.0 V to +6.0 V
−1.75 V to +5.75 V
VCL Range
Comparator Input Voltage Range
Active Load VCOM Range
PMU
Force Voltage Range
Measure Voltage Range
Force Current Voltage Range
Measure Current Voltage Range
Low Clamp Range
High Clamp Range
OVD
−1.25 V to +6.75 V
−1.25 V to +6.75 V
−1.25 V to +6.75 V
−1.25 V to +6.75 V
−1.25 V to +4.75 V
0.75 V to 6.75 V
−2.0 V to +6.0 V
−2.0 V to +6.0 V
−2.0 V to +6.0 V
−2.0 V to +6.0 V
−2.0 V to +4.0 V
0.0 V to 6.0 V
−2.25 V to +7.0 V
−3.0 V to +7.0 V
Table 38. Default Test Conditions (Range 1)
Name
Default Test Condition
VH DAC Level
VL DAC Level
VT/VCOM DAC Level
VOL DAC Level
VOH DAC Level
VCH DAC Level
VCL DAC Level
IOH DAC Level
+2.0 V
+0.0 V
+1.0 V
−1.0 V
+6.0 V
+7.5 V
−2.5 V
0.0 A
IOL DAC Level
0.0 A
OVD Low DAC Level
OVD High DAC Level
PMUDAC DAC Level
PE/PMU Enable
Channel State
PMU State
PMU Measure Enable
Differential Comparator Enable
16-Bit DAC Monitor
OVD_CHx Alarm Mask
Data Input
−2.5 V
+6.5 V
0.0 V
0x0000: PMU disabled, VT not forced through driver, PE enabled
0x0000: HV mode disabled, load disabled, VTERM inactive
0x0000: input of DUTGND, internal sense, clamps disabled, FVMV, Range E
0x0000: MEASOUT01 pin tristated
0x0000: normal window comparator mode
0x0000: DAC16_MON tristated
0x0000: disable alarm functions
Logic low
Receive Input
Logic low
DUTx Pin
Unterminated
Comparator Output
Unterminated
Rev. 0 | Page 44 of 52
ADATE304
PMU Force Voltage Mode to PMU Force Current Mode
RECOMMENDED PMU MODE SWITCHING
SEQUENCES
Step 1. Table 42 lists the state of registers in force voltage mode.
To minimize any possible aberrations and voltage spikes on the
DUT output, specific mode switching sequences are recommended
for the following transitions:
Table 42.
Register
Bits
Setting
PE/PMU Enable
Register, ADDR[4:0]
= 0x0C
DATA[2]
1
•
•
•
PMU disable to PMU enable.
PMU force voltage mode to PMU force current mode.
PMU force current mode to PMU force voltage mode.
PMU State Register, DATA[9:8] XX
ADDR[4:0] = 0x0E
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
X
X
X
X
0
PMU Disable to PMU Enable
Note that, in Table 39 through Table 49, X indicates the don’t
care bit.
Step 1. Table 39 lists the state of the registers in PMU disabled
mode.
DATA[2:0] XXX
Table 39.
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 43).
Register
Bits
Setting
Table 43.
Register
PE/PMU Enable
Register, ADDR[4:0]
= 0x0C
DATA[2]
0
Bits
Setting Comments
PMU State Register,
ADDR[4:0] = 0x0E
DATA[9:8] 01
Set 2.5 V +
DUTGND input
selection
PMU State
DATA[9:8] XX
Register, ADDR[4:0]
= 0x0E
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
X
X
X
X
X
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
X
X
X
X
1
Set to force
current mode
DATA[2:0] XXX
DATA[2:0] 0XX
The 2 μA range
has the
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 40).
minimum offset
current
Table 40.
Register
Bits
Setting Comments
PMU State
Register,
ADDR[4:0] =
0x0E
DATA[9:8] 1X or
00
Set desired input
selection
Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 44).
Table 44.
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
X
X
X
X
0
Register
Bits
Setting Comments
VIN 16-Bit DAC,
ADDR[4:0] = 0x0B
DATA[15:0]
X
Update the VIN
16-Bit DAC
register to the
desired value
This bit must be set
to force voltage mode
to reduce aberrations
Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 45).
DATA[2:0] XXX
Set desired range
Table 45.
Register
Step 3. Write to Register ADDR[4:0] = 0x0C (see Table 41).
Bits
Setting Comments
Table 41.
Register
PMU State Register,
ADDR[4:0] = 0x0E
DATA[9:8] 1X
Set VIN input
selection
Bits
Setting Comments
1
PMU is now enabled
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
X
X
X
X
1
PE/PMU Enable
Register,
ADDR[4:0] = 0x0C
DATA[2]
in force voltage
mode
DATA[2:0] XXX
Set to the
desired current
range
Rev. 0 | Page 45 of 52
ADATE304
Transition from PMU Force Current Mode to PMU Force
Voltage Mode
Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 48).
Table 48.
Step 1. Table 46 lists the state of the registers in force current mode.
Register
Bits
Setting Comments
VIN 16-Bit DAC,
ADDR[4:0] = 0x0B
DATA[15:0]
X
Update the VIN
16-Bit DAC
register to the
desired value
Table 46.
Register
Bits
Setting
PE/PMU Enable Register, ADDR[4:0] = 0x0C
PMU State Register, ADDR[4:0] = 0x0E
DATA[2]
1
DATA[9:8] XX
Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 49).
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
X
X
X
X
1
Table 49.
Register
Bits
Setting Comments
PMU State Register,
ADDR[4:0] = 0x0E
DATA[9:8] 1X
Set VIN input
selection
DATA[2:0] XXX
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
X
X
X
X
0
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 47).
Table 47.
Register
Bits
Setting Comments
Force voltage
mode
PMU State Register, DATA[9:8] 00
ADDR[4:0] = 0x0E
Set DUTGND input
selection
DATA[2:0] XXX
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
X
X
X
X
0
Set to force
voltage mode
DATA[2:0] XXX
Set to the desired
current range
Rev. 0 | Page 46 of 52
ADATE304
BLOCK DIAGRAMS
VCL VCH
PE DISABLE DATA[0] (ADDR[4:0] = 0x0C)
FORCES SWITCH OPEN WHEN 1
VH
VL
R
= 47ꢀ
OUT
(TRIMMED)
DUT
DRIVER
DATA
VT
DRIVER HIGH-Z/VT DATA[0]
(ADDR[4:0] = 0x0D)
VT BUFFER WHEN 1
HIGH-Z BUFFER WHEN 0
V(IOH)
RCV
VCOM
FORCE VT DATA[1] (ADDR[4:0] = 0x0C)
OVERRIDES THE RCV PIN AND FORCES
VTERM MODE ON THE DRIVER AND LOAD
POWER-DOWN MODE
V(IOL)
LOAD ENABLE DATA[1] (ADDR[4:0] = 0x0D)
FORCES SWITCHES OPEN AND POWERS
DOWN LOAD WHEN 0
Figure 75. Driver and Load Block Diagram
~5ꢀ
VHH = (VT + 1V) × 2 + DUTGND
HVOUT
VH
VL
48ꢀ
DATA
RCV (SHOWN IN
RCV = 0 STATE)
HV MODE SELECT DATA[2]
(ADDR [4:0] = 0x0D) DISABLES
HV DRIVER AND FORCES
0V ON HVOUT WHEN 0
Figure 76. HVOUT Driver Output Stage
Rev. 0 | Page 47 of 52
ADATE304
VOH0
–
VOH
NWC
+
DUT0
COMP_QH0
2:1
MUX
+
VOL
NWC
VOL0
VOH0
–
DIFFERENTIAL
COMPARATOR ENABLE
DATA[0] (ADDR[4:0] = 0x10)
–
VOH
DMC
COMP_QL0
2:1
MUX
+
DUT0–
DUT1
DUT1
DIFFERENTIAL
BUFFER
+
VOL
DMC
VOL0
–
NOTES
1. DIFFERENTIAL COMPARATOR ONLY ON CHANNEL 0.
Figure 77. Comparator Block Diagram
COMPARATOR
OUTPUT (AB)
VTT = 3.3V
RECEIVER
OUT HIGH = 1.55V
OUT CM = 1.42V
OUT LOW = 1.30V
50ꢀ
50ꢀ
100ꢀ
GND
Figure 78. Comparator Output Scheme
Rev. 0 | Page 48 of 52
ADATE304
PMU SENSE PATH DATA[7]
(ADDR[4:0] = 0x0E)
PMU MEASURE V/I DATA[4]
(ADDR[4:0] = 0x0E)
EXTERNAL DUT
SENSE PIN
MEASURE V
MEASURE I
MEASOUT01 SELECT DATA[2:1]
(ADDR[4:0] = 0x0F)
MUX
MUX
PMU FORCE V/I DATA[3]
(ADDR[4:0] = 0x0E)
MEASURE
OUT
CH[1] PMU V/I
IN-AMP G = 5
10kꢀ
TEMP SENSE
GND REF
TEMP SENSE
REF
2.5 + DUTGND
MUX
MUX
MEASOUT01 OUTPUT
ENABLE DATA[0]
(ADDR[4:0] = 0x0F)
ONE PER DEVICE
DUTx
225kꢀ
22.5kꢀ
2.25kꢀ
250ꢀ
15.5ꢀ
2µA
20µA
200µA
32mA BUFFER
32mA
2mA
PMU INPUT SELECTION DATA[9:8]
(ADDR[4:0] = 0x0E)
MV
VIN
2.5V + DUTGND
DUTGND
FFCAP_xA
FFCAP_xB
330pF
SCAPx
(EXTERNAL)
MUX
PMU CLAMP ENABLE DATA[5]
(ADDR[4:0] = 0x0E)
CRA = 220pF
VCH
MEASURE V
(AT OUTPUT OF
SENSE MUX)
VCL
NOTES
1. SWITCHES CONNECTED WITH DOTTED LINES REPRESENT PMU RANGE DATA[2:0] (ADDR[4:0] = 0x0E); WHEN PMU ENABLE DATA[2] = 0 (ADDR[4:0] = 0x0C), ALL
SWITCHES OPEN AND PMU POWERS DOWN.
2. THE EXTERNAL SENSE PATH MUST CLOSE THE LOOP TO ENABLE THE CLAMPS TO OPERATE CORRECTLY.
3. 32mA RANGE HAS ITS OWN OUTPUT BUFFER.
4. 32mA BUFFER TRISTATES WHEN NOT IN USE.
Figure 79. PMU Block Diagram
Rev. 0 | Page 49 of 52
ADATE304
(ADDR[4:0] = 0x12) DATA[0]
OVD MASK ENABLES OVD
FLAGS TO ALARM OVD_CHx PIN
1
6.5V
OVD HIGH LEVEL
DAC (ADDR[4:0] = 0x0A, CH[1])
OVD_CHx
SHORT-CIRCUIT
CURRENT = 100µA
DUT
ADATE304
1
–2.5V
OVD LOW LEVEL
DAC (ADDR[4:0] = 0x0A, CH[0])
PMU
V/I CLAMP
FLAG
(ADDR[4:0] = 0x12) DATA[1]
PMU MASK ENABLES PMU V/I
FLAG TO ALARM OVD_CHx PIN
2
(ADDR[4:0] = 0x13) DATA[2] DATA[1] DATA[0]
1
THE OVD HIGH/LOW LEVEL DAC IS SHARED BY EACH CHANNEL; THEREFORE, ONLY ONE OVD HIGH/LOW VOLTAGE
LEVEL CAN BE SET PER CHIP. THE OVD DACs PROVIDE A VOLTAGE RANGE OF –3V TO +7V. THE RECOMMENDED
HIGH/LOW SETTINGS ARE +6.5V/–2.5V. (THESE VALUES NEED TO BE PROGRAMMED BY THE USER UPON STARTUP/RESET.)
THIS IS A READ ONLY REGISTER THAT ALLOWS THE USER TO DETERMINE THE CAUSE OF THE ACTIVE OVD FLAG.
2
Figure 80. OVD Block Diagram
Rev. 0 | Page 50 of 52
ADATE304
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
A1 BALL
CORNER
A1 BALL
CORNER
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
6.731
REF SQ
7.20
BSC SQ
0.80
BSC
G
H
J
K
TOP VIEW
DETAIL A
BOTTOM VIEW
0.305 REF
0.90 REF
0.83
0.76
0.69
*
1.20
1.09
1.00
DETAIL A
0.36
REF
0.38
0.33
0.28
0.53
0.48
0.43
COPLANARITY
0.12
SEATING
PLANE
BALL DIAMETER
*
COMPLIANT TO JEDEC STANDARDS MO-219 WITH
EXCEPTION TO PACKAGE HEIGHT.
Figure 81. 84-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-84-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADATE304BBCZ1
Temperature Range
−40°C to +85°C
Package Description
Package Option
84-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
BC-84-2
1 Z = RoHS Compliant Part.
Rev. 0 | Page 51 of 52
ADATE304
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07279-0-10/08(0)
Rev. 0 | Page 52 of 52
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