ADAU1961WBCPZ [ADI]
Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL; 立体声，低功耗， 96 kHz的24位音频编解码器集成PLL
| 型号： | ADAU1961WBCPZ |
| 厂家： | 
ADI |
| 描述： | Stereo, Low Power, 96 kHz, 24-Bit Audio Codec with Integrated PLL |
| 文件： | 总76页 (文件大小：985K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Stereo, Low Power, 96 kHz, 24-Bit
Audio Codec with Integrated PLL
ADAU1961
Data Sheet
FEATURES
GENERAL DESCRIPTION
24-bit stereo audio ADC and DAC: >98 dB SNR
Sampling rates from 8 kHz to 96 kHz
Low power: 17 mW record, 18 mW playback, 48 kHz
6 analog input pins, configurable for single-ended or
differential inputs
Flexible analog input/output mixers
Stereo digital microphone input
Analog outputs: 2 differential stereo, 2 single-ended stereo,
1 mono headphone output driver
The ADAU1961 is a low power, stereo audio codec that supports
stereo 48 kHz record and playback at 35 mW from a 3.3 V analog
supply. The stereo audio ADCs and DACs support sample rates
from 8 kHz to 96 kHz as well as a digital volume control.
The record path includes an integrated microphone bias circuit
and six inputs. The inputs can be mixed and muxed before the
ADC, or they can be configured to bypass the ADC. The
ADAU1961 includes a stereo digital microphone input.
The ADAU1961 includes five high power output drivers (two
differential and three single-ended), supporting stereo head-
phones, an earpiece, or other output transducer. AC-coupled
or capless configurations are supported. Individual fine level
controls are supported on all analog outputs. The output mixer
stage allows for flexible routing of audio.
The serial control bus supports the I2C and SPI protocols. The
serial audio bus is programmable for I2S, left-/right-justified,
and TDM modes. A programmable PLL supports flexible clock
generation for all standard integer rates and fractional master
clocks from 8 MHz to 27 MHz.
PLL supporting input clocks from 8 MHz to 27 MHz
Analog automatic level control (ALC)
Microphone bias reference voltage
Analog and digital I/O: 3.3 V
I2C and SPI control interfaces
Digital audio serial data I/O: stereo and time-division
multiplexing (TDM) modes
Software-controllable clickless mute
32-lead, 5 mm × 5 mm LFCSP
−40°C to +105°C operating temperature range
Qualified for automotive applications
APPLICATIONS
Automotive head units
Automotive amplifiers
Navigation systems
Rear-seat entertainment systems
FUNCTIONAL BLOCK DIAGRAM
HP JACK
DETECTION
REGULATOR
ADAU1961
JACKDET/MICIN
LAUX
LINP
LINN
LOUTP
LOUTN
LHP
DAC
DAC
ADC
INPUT
ADC
DAC
MIXERS
OUTPUT
MIXERS
MONOOUT
RHP
DIGITAL DIGITAL
FILTERS FILTERS
RINP
RINN
ALC
ADC
ROUTP
ROUTN
RAUX
2
I C/SPI
CONTROL PORT
MICROPHONE
BIAS
SERIAL DATA
INPUT/OUTPUT PORTS
MICBIAS
PLL
MCLK ADC_SDATA
DAC_SDATA ADDR0/ ADDR1/ SCL/ SDA/
CDATA CCLK COUT
CLATCH
Figure 1.
Rev. A
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Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. All rights reserved.
Technical Support
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ADAU1961
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Sampling Rates............................................................................ 24
PLL ............................................................................................... 25
Record Signal Path ......................................................................... 27
Input Signal Paths....................................................................... 27
Analog-to-Digital Converters................................................... 29
Automatic Level Control (ALC)................................................... 30
ALC Parameters.......................................................................... 30
Noise Gate Function .................................................................. 31
Playback Signal Path ...................................................................... 33
Output Signal Paths ................................................................... 33
Headphone Output .................................................................... 34
Pop-and-Click Suppression ...................................................... 35
Line Outputs ............................................................................... 35
Control Ports................................................................................... 36
Burst Mode Writing and Reading............................................ 36
I2C Port ........................................................................................ 36
SPI Port ........................................................................................ 39
Serial Data Input/Output Ports .................................................... 40
Applications Information .............................................................. 42
Power Supply Bypass Capacitors.............................................. 42
GSM Noise Filter........................................................................ 42
Grounding................................................................................... 42
Exposed Pad PCB Design ......................................................... 42
Control Registers............................................................................ 43
Control Register Details ............................................................ 44
Outline Dimensions....................................................................... 75
Ordering Guide .......................................................................... 75
Automotive Products................................................................. 75
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Analog Performance Specifications, TA = 25°C ....................... 3
Analog Performance Specifications, −40°C < TA < +105°C ... 5
Power Supply Specifications........................................................ 7
Digital Filters................................................................................. 8
Digital Input/Output Specifications........................................... 8
Digital Timing Specifications ..................................................... 9
Digital Timing Diagrams........................................................... 10
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 15
System Block Diagrams ................................................................. 18
Theory of Operation ...................................................................... 21
Startup, Initialization, and Power................................................. 22
Power-Up Sequence ................................................................... 22
Power Reduction Modes............................................................ 22
Digital Power Supply.................................................................. 22
Input/Output Power Supply...................................................... 22
Clock Generation and Management........................................ 22
Clocking and Sampling Rates ....................................................... 24
Core Clock................................................................................... 24
REVISION HISTORY
4/13—Rev. 0 to Rev. A
Added Maximum Junction Temperature of 125°C.................... 12
Updated Outline Dimensions....................................................... 75
10/10—Revision 0: Initial Version
Rev. A | Page 2 of 76
Data Sheet
ADAU1961
SPECIFICATIONS
Supply voltage (AVDD) = 3.3 V, TA = 25°C, master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement
bandwidth = 20 Hz to 20 kHz, word width = 24 bits, CLOAD (digital output) = 20 pF, ILOAD (digital output) = 2 mA, VIH = 2 V, VIL = 0.8 V,
unless otherwise noted. Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase
deviation specifications.
ANALOG PERFORMANCE SPECIFICATIONS, TA = 25°C
IOVDD = 3.3 V 10%.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC performance excludes mixers
and PGA
ADC Resolution
All ADCs
24
0.375
95
Bits
dB
dB
Digital Attenuation Step
Digital Attenuation Range
INPUT RESISTANCE
Single-Ended Line Input
−12 dB gain
0 dB gain
6 dB gain
−12 dB gain
0 dB gain
35.25 dB gain
All gains
80.4
21
10.5
84.5
53
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
PGA Inverting Inputs
1.7
105
PGA Noninverting Inputs
SINGLE-ENDED LINE INPUT
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
1.0 (2.83)
V rms (V p-p)
20 Hz to 20 kHz, −60 dB input
−1 dBFS
83.5
83
99
96
−90
dB
dB
dB
−71
With A-Weighted Filter (RMS)
No Filter (RMS)
Input Mixer Gain per Step
Mute Attenuation
99
96
3
dB
dB
dB
dB
−12 dB to +6 dB range
2.89
3.07
−77
LINPG[2:0], LINNG[2:0] = 000,
RINPG[2:0], RINNG[2:0] = 000,
MX1AUXG[2:0], MX2AUXG[2:0] = 000
−85.5
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Power Supply Rejection Ratio
PSEUDO-DIFFERENTIAL PGA INPUT
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
−0.3
−5
−17
+0.032
0
−12
68
+0.3
+5
−8
dB
mV
%
dB
dB
CM capacitor = 20 μF, 100 mV p-p @ 1 kHz
20 Hz to 20 kHz, −60 dB input
−1 dBFS
67
1.0 (2.83)
V rms (V p-p)
94
91
98
95
−89
dB
dB
dB
−83
+8
98
95
+0.4
dB
dB
dB
PGA Boost Gain Error
20 dB gain setting (RDBOOST[1:0],
LDBOOST[1:0] = 10)
−8
Rev. A | Page 3 of 76
ADAU1961
Data Sheet
Parameter
Test Conditions/Comments
PGA muted
Min
Typ
Max
Unit
Mute Attenuation
LDMUTE, RDMUTE = 0
RDBOOST[1:0], LDBOOST[1:0] = 00
−76
−87
−0.073
0
−14
83
−73
−82
+0.6
+6
dB
dB
dB
mV
%
dB
dB
dB
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Common-Mode Rejection Ratio
−0.6
−6
−24
−3
100 mV rms, 1 kHz
100 mV rms, 20 kHz
Differential PGA inputs
−58
−48
−52
−44
FULL DIFFERENTIAL PGA INPUT
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
PGA Boost Gain Error
1.0 (2.83)
V rms (V p-p)
20 Hz to 20 kHz, −60 dB input
−1 dBFS
94
91
98
95
−78
dB
dB
dB
−74
+8
98
95
−0.15
dB
dB
dB
20 dB gain setting (RDBOOST[1:0],
LDBOOST[1:0] = 10)
−8
Mute Attenuation
PGA muted
LDMUTE, RDMUTE = 0
RDBOOST[1:0], LDBOOST[1:0] = 00
−76
−87
−0.0005
0
−14
83
−73
−82
+0.3
+6
dB
dB
dB
mV
%
dB
dB
dB
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Common-Mode Rejection Ratio
−0.3
−6
−17
−9
100 mV rms, 1 kHz
100 mV rms, 20 kHz
MBIEN = 1
−58
−48
−52
−44
MICROPHONE BIAS
Bias Voltage
0.65 × AVDD
MBI = 1, MPERF = 0
MBI = 1, MPERF = 1
MBI = 0, MPERF = 0
MBI = 0, MPERF = 1
MBI = 0, MPERF = 1
1 kHz to 20 kHz
2.00
2.04
2.89
2.89
2.145
2.13
2.97
2.99
2.19
2.21
3.04
3.11
3
V
V
V
V
0.90 × AVDD
Bias Current Source
Noise in the Signal Bandwidth
mA
MBI = 0, MPERF = 0
MBI = 0, MPERF = 1
MBI = 1, MPERF = 0
MBI = 1, MPERF = 1
42
85
25
22
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
13
36
DIGITAL-TO-ANALOG CONVERTERS
DAC performance excludes mixers and
headphone amplifier
DAC Resolution
All DACs
24
0.375
95
Bits
dB
dB
Digital Attenuation Step
Digital Attenuation Range
DAC TO LINE OUTPUT
Full-Scale Output Voltage (0 dB)
Dynamic Range
0.92 (2.60)
V rms (V p-p)
20 Hz to 20 kHz, −60 dBFS input, line
output mode
With A-Weighted Filter (RMS)
No Filter (RMS)
95
93.5
101
98
dB
dB
Rev. A | Page 4 of 76
Data Sheet
ADAU1961
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
Total Harmonic Distortion + Noise
Line Output Mode
Headphone Output Mode
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
0 dBFS, 10 kΩ load
−92
−89
−77
−79
dB
dB
Line output mode
101
98
dB
dB
Mute Attenuation
Mixer 3 and Mixer 4 Muted
MX3RM, MX3LM, MX4RM, MX4LM = 0,
MX3AUXG[3:0], MX4AUXG[3:0] = 0000,
MX3G1[3:0], MX3G2[3:0] = 0000,
MX4G1[3:0], MX4G2[3:0] = 0000
MX5G3[1:0], MX5G4[1:0], MX6G3[1:0],
MX6G4[1:0], MX7[1:0] = 00
−85
−78
−80
dB
Mixer 5, Mixer 6, and Mixer 7 Muted
All Volume Controls Muted
−89
dB
LOUTM, ROUTM = 0
MONOM, LHPM, RHPM = 0
−82
−74
−0.005
0
−74
−69
+0.3
+22
+10
dB
dB
dB
mV
%
Interchannel Gain Mismatch
Offset Error
Gain Error
−0.3
−22
−10
+3
Interchannel Isolation
Power Supply Rejection Ratio
1 kHz, 0 dBFS input signal
CM capacitor = 20 μF, 100 mV p-p @ 1 kHz
100
70
dB
dB
DAC TO HEADPHONE/EARPIECE
OUTPUT
LOUTx, ROUTx, LHP, RHP in headphone
output mode; PO = output power per
channel
Full-Scale Output Voltage (0 dB)
Total Harmonic Distortion + Noise
Scales linearly with AVDD
−4 dBFS, 16 Ω load, PO = 21.1 mW
−4 dBFS, 32 Ω load, PO = 10.6 mW
−2 dBFS, 16 Ω load
−2 dBFS, 32 Ω load
0 dBFS, 10 kΩ load
1 kHz, 0 dBFS input signal, 32 Ω load
Referred to GND
Referred to CM (capless headphone
mode)
0.92 (2.60)
−82
−82
−78
−75
V rms (V p-p)
dB
dB
dB
dB
dB
Capless Headphone Mode
−71
−65
−77
Headphone Output Mode
Interchannel Isolation
−86
73
50
dB
dB
Power Supply Rejection Ratio
REFERENCE
Common-Mode Reference Output
CM capacitor = 20 μF, 100 mV p-p @ 1 kHz
67
dB
V
CM pin
1.62
1.65
1.67
ANALOG PERFORMANCE SPECIFICATIONS, −40°C < TA < +105°C
IOVDD = 3.3 V 10%.
Table 2.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
SINGLE-ENDED LINE INPUT
Dynamic Range
20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Input Mixer Gain per Step
Mute Attenuation
74
71
dB
dB
dB
dB
dB
−1 dBFS
−12 dB to +6 dB range
LINPG[2:0], LINNG[2:0] = 000,
RINPG[2:0], RINNG[2:0] = 000,
MX1AUXG[2:0], MX2AUXG[2:0] = 000
−67
3.09
−77
2.88
Interchannel Gain Mismatch
Offset Error
Gain Error
−0.5
−5
−22
+0.5
+5
−6
dB
mV
%
Rev. A | Page 5 of 76
ADAU1961
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
PSEUDO-DIFFERENTIAL PGA INPUT
Dynamic Range
20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
PGA Boost Gain Error
94
91
dB
dB
dB
dB
−1 dBFS
−75
−7
20 dB gain setting (RDBOOST[1:0],
LDBOOST[1:0] = 10)
−11
Mute Attenuation
PGA muted
LDMUTE, RDMUTE = 0
RDBOOST[1:0], LDBOOST[1:0] = 00
−73
−82
+0.6
+6
−3
−38
−43
dB
dB
dB
mV
%
Interchannel Gain Mismatch
Offset Error
Gain Error
−0.6
−6
−24
−64
−53
Common-Mode Rejection Ratio
100 mV rms, 1 kHz
100 mV rms, 20 kHz
dB
dB
FULL DIFFERENTIAL PGA INPUT
Dynamic Range
Differential PGA inputs
20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
PGA Boost Gain Error
89
86
dB
dB
dB
dB
−1 dBFS
−70
−7
20 dB gain setting (RDBOOST[1:0],
LDBOOST[1:0] = 10)
−11
Mute Attenuation
PGA muted
LDMUTE, RDMUTE = 0
RDBOOST[1:0], LDBOOST[1:0] = 00
−73
−82
+0.4
+6
−7
−38
−43
dB
dB
dB
mV
%
Interchannel Gain Mismatch
Offset Error
Gain Error
−0.4
−6
−21
−64
−53
Common-Mode Rejection Ratio
100 mV rms, 1 kHz
100 mV rms, 20 kHz
MBIEN = 1
dB
dB
MICROPHONE BIAS
Bias Voltage
0.65 × AVDD
MBI = 1, MPERF = 0
MBI = 1, MPERF = 1
MBI = 0, MPERF = 0
MBI = 0, MPERF = 1
1 kHz to 20 kHz
1.85
1.87
2.65
2.65
11
2.45
2.45
3.40
3.40
36
V
V
V
V
0.90 × AVDD
Noise in the Signal Bandwidth
DAC TO LINE OUTPUT
Dynamic Range
nV/√Hz
20 Hz to 20 kHz, −60 dB input, line
output mode
With A-Weighted Filter (RMS)
No Filter (RMS)
85
78
dB
dB
Total Harmonic Distortion + Noise
Line Output Mode
Headphone Output Mode
Mute Attenuation
0 dBFS, 10 kΩ load
−76
−78
dB
dB
Mixer 3 and Mixer 4 Muted
MX3RM, MX3LM, MX4RM, MX4LM = 0,
MX3AUXG[3:0], MX4AUXG[3:0] = 0000,
MX3G1[3:0], MX3G2[3:0] = 0000,
MX4G1[3:0], MX4G2[3:0] = 0000
−77
dB
Mixer 5, Mixer 6, and Mixer 7 Muted
All Volume Controls Muted
MX5G3[1:0], MX5G4[1:0], MX6G3[1:0],
MX6G4[1:0], MX7[1:0] = 00
LOUTM, ROUTM = 0
−77
dB
−74
−69
dB
dB
MONOM, LHPM, RHPM = 0
Rev. A | Page 6 of 76
Data Sheet
ADAU1961
Parameter
Test Conditions/Comments
Min
−0.3
−22
−10
Typ
Max
+0.3
+22
+10
Unit
dB
mV
%
Interchannel Gain Mismatch
Offset Error
Gain Error
DAC TO HEADPHONE/EARPIECE
OUTPUT
LOUTx, ROUTx, LHP, RHP in headphone
output mode; PO = output power per
channel
Total Harmonic Distortion + Noise
Capless Headphone Mode
−2 dBFS, 16 Ω load
−2 dBFS, 32 Ω load
0 dBFS, 10 kΩ load
−61
−63
−76
dB
dB
dB
Headphone Output Mode
REFERENCE
Common-Mode Reference Output
CM pin
1.47
1.83
V
POWER SUPPLY SPECIFICATIONS
Master clock = 12.288 MHz, input sample rate = 48 kHz, input tone = 1 kHz, ADC input @ −1 dBFS, DAC input @ 0 dBFS,
−40°C < TA < +105°C, IOVDD = 3.3 V 10%. For total power consumption, add the IOVDD current listed in Table 3.
Table 3.
Parameter
SUPPLIES
Voltage
Test Conditions/Comments
Min
Typ
Max
Unit
DVDDOUT
AVDD
IOVDD
1.56
3.3
3.3
V
V
V
2.97
2.97
3.65
3.65
Digital I/O Current (IOVDD)
Slave Mode
20 pF capacitive load on all digital pins
fS = 48 kHz
fS = 96 kHz
fS = 8 kHz
fS = 48 kHz
fS = 96 kHz
fS = 8 kHz
0.48
0.9
0.13
1.51
3
mA
mA
mA
mA
mA
mA
Master Mode
0.27
Analog Current (AVDD)
Record Stereo Differential to ADC
PLL bypass
Integer PLL
10 kΩ load
PLL bypass
Integer PLL
32 Ω load
5.24
6.57
mA
mA
DAC Stereo Playback to Line Output
DAC Stereo Playback to Headphone
5.55
6.90
mA
mA
PLL bypass
Integer PLL
30.9
32.25
mA
mA
DAC Stereo Playback to Capless Headphone 32 Ω load
PLL bypass
Integer PLL
56.75
58
mA
mA
Rev. A | Page 7 of 76
ADAU1961
Data Sheet
DIGITAL FILTERS
Table 4.
Parameter
Mode
Factor
Min
Typ
Max
Unit
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
All modes, typ @ 48 kHz
0.4375 fS
21
0.015
24
27
67
479
kHz
dB
kHz
kHz
dB
0.5 fS
0.5625 fS
Stop-Band Attenuation
Group Delay
22.9844/fS
µs
DAC INTERPOLATION FILTER
Pass Band
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
0.4535 fS
0.3646 fS
22
35
kHz
kHz
dB
Pass-Band Ripple
Transition Band
Stop Band
0.01
0.05
dB
0.5 fS
0.5 fS
0.5465 fS
0.6354 fS
24
48
26
61
69
68
521
115
kHz
kHz
kHz
kHz
dB
dB
µs
µs
Stop-Band Attenuation
Group Delay
25/fS
11/fS
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +105°C, IOVDD = 3.3 V 10%.
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
INPUT SPECIFICATIONS
Input Voltage High (VIH)
Input Voltage Low (VIL)
Input Leakage
0.7 × IOVDD
V
V
0.3 × IOVDD
Pull-Ups/Pull-Downs Disabled
IIH @ VIH = 3.3 V
IIL @ VIL = 0 V
IIL @ VIL = 0 V (MCLK pin)
IIH @ VIH = 3.3 V
IIL @ VIL = 0 V
−0.17
−0.17
−13.5
−0.7
−13.5
2.7
+0.17
+0.17
−0.5
+0.7
−0.5
8.3
µA
µA
µA
µA
µA
µA
µA
pF
Pull-Ups Enabled
Pull-Downs Enabled
IIH @ VIH = 3.3 V
IIL @ VIL = 0 V
−0.18
+0.18
5
Input Capacitance
OUTPUT SPECIFICATIONS
Output Voltage High (VOH)
Output Voltage Low (VOL)
IOH = 2 mA @ 3.3 V
IOL = 2 mA @ 3.3 V
0.8 × IOVDD
V
V
0.1 × IOVDD
Rev. A | Page 8 of 76
Data Sheet
ADAU1961
DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +105°C, IOVDD = 3.3 V 10%.
Table 6. Digital Timing
Limit
tMAX
Parameter
tMIN
Unit
Description
MASTER CLOCK
tMP
tMP
tMP
74
37
24.7
18.5
488
244
162.7
122
ns
ns
ns
ns
MCLK period, 256 × fS mode.
MCLK period, 512 × fS mode.
MCLK period, 768 × fS mode.
MCLK period, 1024 × fS mode.
tMP
SERIAL PORT
tBIL
tBIH
tLIS
tLIH
5
5
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
BCLK pulse width low.
BCLK pulse width high.
LRCLK setup. Time to BCLK rising.
LRCLK hold. Time from BCLK rising.
DAC_SDATA setup. Time to BCLK rising.
DAC_SDATA hold. Time from BCLK rising.
tSIS
tSIH
tSODM
SPI PORT
fCCLK
tCCPL
tCCPH
tCLS
50
10
ADC_SDATA delay. Time from BCLK falling in master mode.
MHz
ns
ns
CCLK frequency.
CCLK pulse width low.
CCLK pulse width high.
CLATCH setup. Time to CCLK rising.
CLATCH hold. Time from CCLK rising.
CLATCH pulse width high.
10
10
5
ns
tCLH
10
10
5
ns
tCLPH
tCDS
tCDH
ns
ns
ns
ns
CDATA setup. Time to CCLK rising.
CDATA hold. Time from CCLK rising.
COUT three-stated. Time from CLATCH rising.
5
tCOD
50
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tSCR
tSCF
400
kHz
µs
µs
µs
µs
ns
ns
ns
ns
ns
µs
SCL frequency.
SCL high.
SCL low.
Setup time; relevant for repeated start condition.
Hold time. After this period, the first clock is generated.
Data setup time.
SCL rise time.
SCL fall time.
0.6
1.3
0.6
0.6
100
300
300
300
300
tSDR
tSDF
tBFT
SDA rise time.
SDA fall time.
0.6
Bus-free time. Time between stop and start.
RLOAD = 1 MΩ, CLOAD = 14 pF.
Digital microphone clock fall time.
Digital microphone clock rise time.
Digital microphone delay time for valid data.
Digital microphone delay time for data three-stated.
DIGITAL MICROPHONE
tDCF
tDCR
tDDV
tDDH
10
10
30
12
ns
ns
ns
ns
22
0
Rev. A | Page 9 of 76
ADAU1961
Data Sheet
DIGITAL TIMING DIAGRAMS
tLIH
tBIH
BCLK
tBIL
tLIS
LRCLK
tSIS
DAC_SDATA
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
tSIH
tSIS
DAC_SDATA
I S MODE
2
MSB
tSIH
tSIS
tSIS
DAC_SDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
tSIH
tSIH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Input Port Timing
tBIH
BCLK
tBIL
LRCLK
tSODM
MSB
ADC_SDATA
LEFT-JUSTIFIED
MODE
MSB – 1
tSODM
MSB
ADC_SDATA
I S MODE
2
tSODM
ADC_SDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 3. Serial Output Port Timing
Rev. A | Page 10 of 76
Data Sheet
ADAU1961
tCLS
tCLH
tCLPH
tCCPL
tCCPH
CLATCH
CCLK
CDATA
tCDH
tCDS
COUT
tCOD
Figure 4. SPI Port Timing
tDS
tSCH
tSCH
SDA
SCL
tSCR
tSCLH
tSCS
tBFT
tSCLL tSCF
Figure 5. I2C Port Timing
tDCF
tDCR
CLK
tDDH
tDDH
tDDV
tDDV
DATA1/
DATA2
DATA1
DATA2
DATA1
DATA2
Figure 6. Digital Microphone Timing
Rev. A | Page 11 of 76
ADAU1961
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 7.
Parameter
Rating
θJA represents thermal resistance, junction-to-ambient; θJC repre-
sents thermal resistance, junction-to-case. All characteristics are
for a 4-layer board.
Power Supply (AVDD)
−0.3 V to +3.65 V
20 mA
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
−0.3 V to AVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
125°C
Table 8. Thermal Resistance
Package Type
θJA
θJC
Unit
32-Lead LFCSP
50.1
17
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 12 of 76
Data Sheet
ADAU1961
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IOVDD
MCLK
ADDR0/CLATCH
JACKDET/MICIN
MICBIAS
1
2
3
4
5
6
7
8
24 DVDDOUT
23 AVDD
22 AGND
21 MONOOUT
20 LHP
19 RHP
18 LOUTP
17 LOUTN
PIN 1
INDICATOR
ADAU1961
TOP VIEW
(Not to Scale)
LAUX
CM
AVDD
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE
ADAU1961 GROUNDS. FOR INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE SOLDERED TO THE
GROUND PLANE.
Figure 7. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
IOVDD
PWR
Supply for Digital Input and Output Pins. The digital output pins are supplied from IOVDD,
which also sets the highest input voltage that should be seen on the digital input pins.
IOVDD should be set to 3.3 V. The current draw of this pin is variable because it is dependent
on the loads of the digital outputs. IOVDD should be decoupled to DGND with a 100 nF
capacitor and a 10 μF capacitor.
2
3
MCLK
ADDR0/CLATCH
D_IN
D_IN
External Master Clock Input.
I2C Address Bit 0 (ADDR0).
SPI Latch Signal (CLATCH). Must go low at the beginning of an SPI transaction and high at the
end of a transaction. Each SPI transaction can take a different number of CCLKs to complete,
depending on the address and read/write bit that are sent at the beginning of the SPI
transaction.
4
JACKDET/MICIN
D_IN
Detect Insertion/Removal of Headphone Plug (JACKDET).
Digital Microphone Stereo Input (MICIN).
5
6
7
MICBIAS
LAUX
CM
A_OUT
A_IN
A_OUT
Bias Voltage for Electret Microphone.
Left Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
AVDD/2 V Common-Mode Reference. A 10 μF to 47 μF standard decoupling capacitor should
be connected between this pin and AGND to reduce crosstalk between the ADCs and DACs.
This pin can be used to bias external analog circuits, as long as they are not drawing current
from CM (for example, the noninverting input of an op amp).
8
9
AVDD
AGND
PWR
PWR
3.3 V Analog Supply for DAC and Microphone Bias. This pin should be decoupled locally to
AGND with a 100 nF capacitor.
Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
10
11
12
13
14
15
16
17
18
LINP
LINN
RINP
RINN
RAUX
ROUTP
ROUTN
LOUTN
LOUTP
A_IN
A_IN
A_IN
A_IN
Left Channel Noninverting Input or Single-Ended Input 0. Biased at AVDD/2.
Left Channel Inverting Input or Single-Ended Input 1. Biased at AVDD/2.
Right Channel Noninverting Input or Single-Ended Input 2. Biased at AVDD/2.
Right Channel Inverting Input or Single-Ended Input 3. Biased at AVDD/2.
Right Channel Single-Ended Auxiliary Input. Biased at AVDD/2.
Right Line Output, Positive. Biased at AVDD/2.
Right Line Output, Negative. Biased at AVDD/2.
Left Line Output, Negative. Biased at AVDD/2.
Left Line Output, Positive. Biased at AVDD/2.
A_IN
A_OUT
A_OUT
A_OUT
A_OUT
Rev. A | Page 13 of 76
ADAU1961
Data Sheet
Pin No.
19
20
Mnemonic
Type1
Description
RHP
LHP
MONOOUT
A_OUT
A_OUT
A_OUT
Right Headphone Output. Biased at AVDD/2.
Left Headphone Output. Biased at AVDD/2.
Mono Output or Virtual Ground for Capless Headphone. Biased at AVDD/2 when set as mono
output.
21
22
23
24
AGND
PWR
PWR
PWR
Analog Ground. The AGND and DGND pins can be tied together on a common ground plane.
AGND should be decoupled locally to AVDD with a 100 nF capacitor.
3.3 V Analog Supply for ADC, Output Driver, and Input to Digital Supply Regulator. This pin
should be decoupled locally to AGND with a 100 nF capacitor.
Digital Core Supply Decoupling Point. The digital supply is generated from an on-board
regulator and does not require an external supply. DVDDOUT should be decoupled to DGND
with a 100 nF capacitor and a 10 μF capacitor.
AVDD
DVDDOUT
25
DGND
PWR
Digital Ground. The AGND and DGND pins can be tied together on a common ground plane.
DGND should be decoupled to DVDDOUT and to IOVDD with 100 nF capacitors and 10 μF
capacitors.
26
27
28
29
30
ADC_SDATA
DAC_SDATA
BCLK
LRCLK
ADDR1/CDATA
D_OUT
D_IN
D_IO
D_IO
D_IN
ADC Serial Output Data.
DAC Serial Input Data.
Serial Data Port Bit Clock.
Serial Data Port Frame Clock.
I2C Address Bit 1 (ADDR1).
SPI Data Input (CDATA).
31
SDA/COUT
D_IO
I2C Data (SDA). This pin is a bidirectional open-collector input/output. The line connected to
this pin should have a 2 kΩ pull-up resistor.
SPI Data Output (COUT). This pin is used for reading back registers and memory locations. It is
three-state when an SPI read is not active.
32
EP
SCL/CCLK
D_IN
I2C Clock (SCL). This pin is always an open-collector input when in I2C control mode. The line
connected to this pin should have a 2 kΩ pull-up resistor.
SPI Clock (CCLK). This pin can run continuously or be gated off between SPI transactions.
Exposed Pad. The exposed pad is connected internally to the ADAU1961 grounds. For
increased reliability of the solder joints and maximum thermal capability, it is recommended
that the pad be soldered to the ground plane. See the Exposed Pad PCB Design section for
more information.
Exposed Pad
1 A_IN = analog input, A_OUT = analog output, D_IN = digital input, D_IO = digital input/output, D_OUT = digital output, PWR = power.
Rev. A | Page 14 of 76
Data Sheet
ADAU1961
TYPICAL PERFORMANCE CHARACTERISTICS
28
26
24
22
20
18
16
14
12
10
8
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
–105
6
4
2
0
–60
–50
–40
–30
–20
–10
0
–60
–50
–40
–30
–20
–10
0
DIGITAL 1kHz INPUT SIGNAL (dBFS)
DIGITAL 1kHz INPUT SIGNAL (dBFS)
Figure 8. Headphone Amplifier Power vs. Input Level, 16 Ω Load
Figure 11. Headphone Amplifier THD + N vs. Input Level, 16 Ω Load
18
16
14
12
10
8
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
6
4
2
0
–60
–50
–40
–30
–20
–10
0
–60
–50
–40
–30
–20
–10
0
DIGITAL 1kHz INPUT SIGNAL (dBFS)
DIGITAL 1kHz INPUT SIGNAL (dBFS)
Figure 9. Headphone Amplifier Power vs. Input Level, 32 Ω Load
Figure 12. Headphone Amplifier THD + N vs. Input Level, 32 Ω Load
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.04
0.02
0
−0.02
−0.04
−0.06
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
FREQUENCY (NORMALIZED TO fS)
FREQUENCY (NORMALIZED TO fS
)
Figure 10. ADC Decimation Filter, 64× Oversampling, Normalized to fS
Figure 13. ADC Decimation Filter Pass-Band Ripple, 64× Oversampling,
Normalized to fS
Rev. A | Page 15 of 76
ADAU1961
Data Sheet
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.10
0.08
0.06
0.04
0.02
0
−0.02
−0.04
−0.06
−0.08
−0.10
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (NORMALIZED TO fS
FREQUENCY (NORMALIZED TO fS
)
)
Figure 14. ADC Decimation Filter, 128× Oversampling, Normalized to fS
Figure 17. ADC Decimation Filter Pass-Band Ripple, 128× Oversampling,
Normalized to fS
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.04
0.02
0
−0.02
−0.04
−0.06
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
FREQUENCY (NORMALIZED TO fS)
FREQUENCY (NORMALIZED TO fS
)
Figure 15. ADC Decimation Filter, 128× Oversampling, Double-Rate Mode,
Normalized to fS
Figure 18. ADC Decimation Filter Pass-Band Ripple, 128× Oversampling,
Double-Rate Mode, Normalized to fS
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.20
0.15
0.10
0.05
0
−0.05
−0.10
−0.15
−0.20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
FREQUENCY (NORMALIZED TO fS
)
FREQUENCY (NORMALIZED TO fS
)
Figure 16. DAC Interpolation Filter, 64× Oversampling, Double-Rate Mode,
Normalized to fS
Figure 19. DAC Interpolation Filter Pass-Band Ripple, 64× Oversampling,
Double-Rate Mode, Normalized to fS
Rev. A | Page 16 of 76
Data Sheet
ADAU1961
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.05
0.04
0.03
0.02
0.01
0
−0.01
−0.02
−0.03
−0.04
−0.05
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
FREQUENCY (NORMALIZED TO fS
FREQUENCY (NORMALIZED TO fS
)
)
Figure 20. DAC Interpolation Filter, 128× Oversampling, Normalized to fS
Figure 23. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling,
Normalized to fS
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.20
0.15
0.10
0.05
0
−0.05
−0.10
−0.15
−0.20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
FREQUENCY (NORMALIZED TO fS)
FREQUENCY (NORMALIZED TO fS
)
Figure 21. DAC Interpolation Filter, 128× Oversampling, Double-Rate Mode,
Normalized to fS
Figure 24. DAC Interpolation Filter Pass-Band Ripple, 128× Oversampling,
Double-Rate Mode, Normalized to fS
90
80
70
60
50
40
30
20
10
0
GAIN (dB)
Figure 22. Input Impedance vs. Gain for Analog Inputs
Rev. A | Page 17 of 76
ADAU1961
Data Sheet
SYSTEM BLOCK DIAGRAMS
FROM VOLTAGE
REGULATOR
(1.8V TO 3.3V)
10µF
+
0.1µF
10µF
+
10µF
+
0.1µF
0.1µF
0.1µF
1.2nH
9.1pF
THE INPUT CAPACITOR VALUE DEPENDS ON THE
INPUT IMPEDANCE, WHICH VARIES WITH THE
VOLUME SETTING.
DVDDOUT
IOVDD
AVDD
AVDD
10µF
LOUTP
LOUTN
RHP
EARPIECE
SPEAKER
LINP
LINN
LEFT
MICROPHONE
10µF
CAPLESS
HEADPHONE
OUTPUT
MONOOUT
LHP
2kΩ
ROUTP
ROUTN
ADAU1961
MICBIAS
EARPIECE
SPEAKER
2kΩ
10µF
RINN
RINP
RIGHT
MICROPHONE
10µF
ADC_SDATA
JACK
DETECTION
SIGNAL
JACKDET/MICIN
DAC_SDATA
LRCLK
SERIAL DATA
BCLK
AUX LEFT
10µF
10µF
1kΩ
LAUX
RAUX
ADDR1/CDATA
SDA/COUT
SYSTEM
CONTROLLER
SCL/CCLK
AUX RIGHT
1kΩ
ADDR0/CLATCH
49.9Ω
MCLK
CM
+
CLOCK
SOURCE
0.1µF
10µF
Figure 25. System Block Diagram
Rev. A | Page 18 of 76
Data Sheet
ADAU1961
FROM VOLTAGE
REGULATOR
(1.8V TO 3.3V)
10µF
+
0.1µF
10µF
+
10µF
+
0.1µF
0.1µF
0.1µF
1.2nH
9.1pF
THE INPUT CAPACITOR VALUE DEPENDS ON THE
INPUT IMPEDANCE, WHICH VARIES WITH THE
VOLUME SETTING.
DVDDOUT
MICBIAS
IOVDD
AVDD
AVDD
LOUTP
LOUTN
RHP
V
DD
EARPIECE
SPEAKER
10µF
SINGLE-ENDED
ANALOG
MICROPHONE
LINN
LINP
OUTPUT
CAPLESS
HEADPHONE
OUTPUT
CM
MONOOUT
LHP
GND
ADAU1961
ROUTP
ROUTN
EARPIECE
SPEAKER
V
DD
10µF
SINGLE-ENDED
ANALOG
RINN
RINP
OUTPUT
MICROPHONE
CM
GND
ADC_SDATA
JACK
DETECTION
SIGNAL
JACKDET/MICIN
DAC_SDATA
LRCLK
SERIAL DATA
BCLK
10µF
AUX LEFT
1kΩ
LAUX
RAUX
ADDR1/CDATA
SDA/COUT
10µF
SYSTEM
CONTROLLER
SCL/CCLK
AUX RIGHT
1kΩ
ADDR0/CLATCH
49.9Ω
MCLK
CM
+
CLOCK
SOURCE
0.1µF
10µF
Figure 26. System Block Diagram with Analog Microphones
Rev. A | Page 19 of 76
ADAU1961
Data Sheet
FROM VOLTAGE
REGULATOR
(1.8V TO 3.3V)
10µF
+
0.1µF
10µF
+
10µF
+
0.1µF
0.1µF
0.1µF
1.2nH
9.1pF
CAPLESS
HEADPHONE
OUTPUT
DVDDOUT
IOVDD
AVDD
AVDD
RHP
MICBIAS
BCLK
CM
2.5V TO 5.0V
MONOOUT
LHP
CLK
DIGITAL
MICROPHONE
LINP
LINN
RINN
0.1µF
10µF
V
DATA
DD
0.1µF
VDD
VDD
22nF
R
R
EXT
L/R SELECT
GND
RINP
LOUTP
LOUTN
INL+
INL–
ADAU1961
OUTL+
OUTL–
LEFT
SPEAKER
22nF
EXT
SSM2306
CLASS-D 2W
BCLK
STEREO SPEAKER
DRIVER
CLK
DIGITAL
22nF
22nF
R
R
EXT
EXT
ROUTP
ROUTN
INR+
RIGHT
SPEAKER
OUTR+
MICROPHONE
OUTR–
INR–
V
DATA
DD
SD GND
GND
0.1µF
L/R SELECT
GND
JACKDET/MICIN
LAUX
ADC_SDATA
DAC_SDATA
LRCLK
10µF
10µF
AUX LEFT
1kΩ
SERIAL DATA
BCLK
RAUX
MCLK
ADDR1/CDATA
SDA/COUT
SYSTEM
CONTROLLER
AUX RIGHT
1kΩ
SCL/CCLK
49.9Ω
ADDR0/CLATCH
CLOCK
SOURCE
CM
+
0.1µF
10µF
Figure 27. System Block Diagram with Digital Microphones and SSM2306 Class-D Speaker Driver
Rev. A | Page 20 of 76
Data Sheet
ADAU1961
THEORY OF OPERATION
The ADAU1961 is a low power audio codec that offers high
quality audio, low power, small size, and many advanced
features. The stereo ADC and stereo DAC each have an SNR
of at least +98 dB and a THD + N of at least −90 dB. The serial
data port is compatible with I2S, left-justified, right-justified, and
TDM modes for interfacing to digital audio data. The operating
voltage is 3.3 V, with an on-board regulator generating the
internal digital supply voltage.
The ADCs and DACs are high quality, 24-bit Σ-Δ converters
that operate at selectable 64× or 128× oversampling ratios. The
base sampling rate of the converters is set by the input clock rate
and can be further scaled with the converter control register
settings. The converters can operate at sampling frequencies
from 8 kHz to 96 kHz. The ADCs and DACs also include very
fine-step digital volume controls.
The playback path allows input signals and DAC outputs to be
mixed into various output configurations. Headphone drivers
are available for a stereo headphone output, and the other output
pins are capable of differentially driving an earpiece speaker.
Capless headphone outputs are possible with the use of the
mono output as a virtual ground connection. The stereo line
outputs can be used as either single-ended or differential
outputs and as an optional mix-down mono output.
The record signal path includes very flexible input configurations
that can accept differential and single-ended analog microphone
inputs as well as a digital microphone input. A microphone bias
pin provides seamless interfacing to electret microphones. Input
configurations can accept up to six single-ended analog signals
or variations of stereo differential or stereo single-ended signals
with two additional auxiliary single-ended inputs. Each input
signal has its own programmable gain amplifier (PGA) for volume
adjustment and can be routed directly to the playback path output
mixers, bypassing the ADCs. An automatic level control (ALC)
can also be implemented to keep the recording volume constant.
The ADAU1961 can generate its internal clocks from a wide
range of input clocks by using the on-board fractional PLL.
The PLL accepts inputs from 8 MHz to 27 MHz.
The ADAU1961 is provided in a small, 32-lead, 5 mm × 5 mm
LFCSP with an exposed bottom pad.
Rev. A | Page 21 of 76
ADAU1961
Data Sheet
STARTUP, INITIALIZATION, AND POWER
This section describes the procedure for properly starting up
the ADAU1961. The following sequence provides a high level
approach to the proper initiation of the system.
POWER REDUCTION MODES
Sections of the ADAU1961 chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
the DACs, and the PLL.
1. Apply power to the ADAU1961.
2. Lock the PLL to the input clock (if using the PLL).
3. Enable the core clock.
The digital filters of the ADCs and DACs can each be set to over-
sampling ratios of 64× or 128× (default). Setting the oversampling
ratios to 64× for these filters lowers power consumption with a
minimal impact on performance. See the Digital Filters section
for specifications; see the Typical Performance Characteristics
section for graphs of these filters.
4. Load the register settings.
POWER-UP SEQUENCE
The ADAU1961 uses a power-on reset (POR) circuit to
reset the registers upon power-up. The POR monitors the
DVDDOUT pin and generates a reset signal whenever power
is applied to the chip. During the reset, the ADAU1961 is set
to the default values documented in the register map (see the
Control Registers section). Typically, with a 10 μF capacitor on
AVDD, the POR takes approximately 14 ms.
DIGITAL POWER SUPPLY
The digital power supply for the ADAU1961 is generated from
an internal regulator. This regulator generates a 1.5 V supply
internally. The only external connection to this regulator is the
DVDDOUT bypassing point. A 100 nF capacitor and a 10 μF
capacitor should be connected between this pin and DGND.
1.5V
1.35V
DVDDOUT
INPUT/OUTPUT POWER SUPPLY
0.95V
The power for the digital output pins is supplied from IOVDD,
and this pin also sets the highest input voltage that should be
seen on the digital input pins. IOVDD should be set to 3.3 V; no
digital input signal should be at a voltage level higher than the
one on IOVDD. The current draw of this pin is variable because
it depends on the loads of the digital outputs. IOVDD should be
decoupled to DGND with a 100 nF capacitor and a 10 μF
capacitor.
AVDD
PART READY
POR
POR
ACTIVE
POR
FINISHED
POR ACTIVE
CLOCK GENERATION AND MANAGEMENT
The ADAU1961 uses a flexible clocking scheme that enables the
use of many different input clock rates. The PLL can be bypassed
or used, resulting in two different approaches to clock manage-
ment. For more information about clocking schemes, PLL
configuration, and sampling rates, see the Clocking and
Sampling Rates section.
Figure 28. Power-On Reset Sequence
The PLL lock time is dependent on the MCLK rate. Typical
lock times are provided in Table 10.
Table 10. PLL Lock Times
PLL Mode
Fractional
Fractional
Integer
Fractional
Fractional
Fractional
Fractional
Fractional
Fractional
Integer
MCLK Frequency
Lock Time (Typical)
3.5 ms
8 MHz
Case 1: PLL Is Bypassed
12 MHz
3.0 ms
If the PLL is bypassed, the core clock is derived directly from
the MCLK input. The rate of this clock must be set properly in
Register R0 (clock control register, Address 0x4000) using the
INFREQ[1:0] bits. When the PLL is bypassed, supported external
clock rates are 256 × fS, 512 × fS, 768 × fS, and 1024 × fS, where fS
is the base sampling rate. The core clock of the chip is off until
the core clock enable bit (COREN) is asserted.
12.288 MHz
13 MHz
2.96 ms
2.4 ms
14.4 MHz
19.2 MHz
19.68 MHz
19.8 MHz
24 MHz
2.4 ms
2.98 ms
2.98 ms
2.98 ms
2.95 ms
2.96 ms
2.4 ms
24.576 MHz
26 MHz
Fractional
Fractional
27 MHz
2.4 ms
Rev. A | Page 22 of 76
Data Sheet
ADAU1961
Case 2: PLL Is Used
To program the PLL during initialization or reconfiguration of
the clock setting, the following procedure must be followed:
The core clock to the entire chip is off during the PLL lock
acquisition period. The user can poll the lock bit to determine
when the PLL has locked. After lock is acquired, the ADAU1961
can be started by asserting the core clock enable bit (COREN)
in Register R0 (clock control register, Address 0x4000). This bit
enables the core clock to all the internal blocks of the ADAU1961.
1. Power down the PLL.
2. Reset the PLL control register.
3. Start the PLL.
4. Poll the lock bit.
5. Assert the core clock enable bit after the PLL lock
is acquired.
PLL Lock Acquisition
The PLL control register (Register R1, Address 0x4002) is a
48-bit register where all bits must be written with a single
continuous write to the control port.
During the lock acquisition period, only Register R0 (Address
0x4000) and Register R1 (Address 0x4002) are accessible
through the control port. Because all other registers require a
valid master clock for reading and writing, do not attempt to
access any other register. Any read or write is prohibited until
the core clock enable bit (COREN) and the lock bit are both
asserted.
Rev. A | Page 23 of 76
ADAU1961
Data Sheet
CLOCKING AND SAMPLING RATES
SERIAL DATA
INPUT/OUTPUT
PORT
ADCs
DACs
R0: CLOCK
R17: CONVERTER
CONTROL 0 REGISTER
R1: PLL CONTROL REGISTER
CONTROL REGISTER
÷ X
MCLK
CORE
CLOCK
× (R + N/M)
INFREQ[1:0]
CONVSR[2:0]
fS/0.5, 1, 1.5, 2, 3, 4, 6
256 × fS, 512 × fS
768 × fS, 1024 × fS
,
CLKSRC
Figure 29. Clock Tree Diagram
CORE CLOCK
SAMPLING RATES
Clocks for the converters and the serial ports are derived from
the core clock. The core clock can be derived directly from
MCLK or it can be generated by the PLL. The CLKSRC bit (Bit
3 in Register R0, Address 0x4000) determines the clock source.
The ADCs, DACs, and serial port share a common sampling
rate that is set in Register R17 (Converter Control 0 register,
Address 0x4017). The CONVSR[2:0] bits set the sampling rate
as a ratio of the base sampling frequency.
The INFREQ[1:0] bits should be set according to the expected
input clock rate selected by CLKSRC; this value also determines
the core clock rate and the base sampling frequency, fS.
Table 12 and Table 13 list the sampling rate divisions for
common base sampling rates.
Table 12. 48 kHz Base Sampling Rate Divisions
For example, if the input to CLKSRC = 49.152 MHz (from
PLL), then
Base Sampling
Frequency
Sampling Rate Scaling Sampling Rate
fS = 48 kHz
fS/1
fS/6
fS/4
fS/3
fS/2
fS/1.5
fS/0.5
48 kHz
8 kHz
INFREQ[1:0] = 1024 × fS
fS = 49.152 MHz/1024 = 48 kHz
12 kHz
16 kHz
24 kHz
32 kHz
96 kHz
The PLL output clock rate is always 1024 × fS, and the clock
control register automatically sets the INFREQ[1:0] bits to
1024 × fS when using the PLL. When using a direct clock, the
INFREQ[1:0] frequency should be set according to the MCLK
pin clock rate and the desired base sampling frequency.
Table 13. 44.1 kHz Base Sampling Rate Divisions
Table 11. Clock Control Register (Register R0, Address 0x4000)
Base Sampling
Bits
Bit Name
Settings
Frequency
Sampling Rate Scaling Sampling Rate
3
CLKSRC
0: Direct from MCLK pin (default)
1: PLL clock
fS = 44.1 kHz
fS/1
fS/6
fS/4
fS/3
fS/2
fS/1.5
fS/0.5
44.1 kHz
7.35 kHz
11.025 kHz
14.7 kHz
22.05 kHz
29.4 kHz
88.2 kHz
[2:1]
0
INFREQ[1:0]
COREN
00: 256 × fS (default)
01: 512 × fS
10: 768 × fS
11: 1024 × fS
0: Core clock disabled (default)
1: Core clock enabled
Rev. A | Page 24 of 76
Data Sheet
ADAU1961
Fractional Mode
PLL
Fractional mode is used when the MCLK is a fractional
(R + (N/M)) multiple of the PLL output.
The PLL uses the MCLK as a reference to generate the core
clock. PLL settings are set in Register R1 (PLL control register,
Address 0x4002). Depending on the MCLK frequency, the PLL
must be set for either integer or fractional mode. The PLL can
accept input frequencies in the range of 8 MHz to 27 MHz.
For example, if MCLK = 12 MHz and fS = 48 kHz, then
PLL required output = 1024 × 48 kHz = 49.152 MHz
R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)
All six bytes in the PLL control register must be written with a
single continuous write to the control port.
Common fractional PLL parameter settings for 44.1 kHz and
48 kHz sampling rates can be found in Table 15 and Table 16.
TO PLL
CLOCK DIVIDER
÷ X
MCLK
× (R + N/M)
The PLL outputs a clock in the range of 41 MHz to 54 MHz,
which should be taken into account when calculating PLL
values and MCLK frequencies.
Figure 30. PLL Block Diagram
Integer Mode
Integer mode is used when the MCLK is an integer (R) multiple
of the PLL output (1024 × fS).
For example, if MCLK = 12.288 MHz and fS = 48 kHz, then
PLL required output = 1024 × 48 kHz = 49.152 MHz
R = 49.152 MHz/12.288 MHz = 4
In integer mode, the values set for N and M are ignored.
Table 14. PLL Control Register (Register R1, Address 0x4002)
Bits
Bit Name
Description
[47:32]
M[15:0]
Denominator of the fractional PLL: 16-bit binary number
0x00FD: M = 253 (default)
[31:16]
[14:11]
N[15:0]
R[3:0]
Numerator of the fractional PLL: 16-bit binary number
0x000C: N = 12 (default)
Integer part of PLL: four bits, only values 2 to 8 are valid
0010: R = 2 (default)
0011: R = 3
0100: R = 4
0101: R = 5
0110: R = 6
0111: R = 7
1000: R = 8
[10:9]
X[1:0]
PLL input clock divider
00: X = 1 (default)
01: X = 2
10: X = 3
11: X = 4
8
1
0
Type
Lock
PLL operation mode
0: Integer (default)
1: Fractional
PLL lock (read-only bit)
0: PLL unlocked (default)
1: PLL locked
PLLEN
PLL enable
0: PLL disabled (default)
1: PLL enabled
Rev. A | Page 25 of 76
ADAU1961
Data Sheet
Table 15. Fractional PLL Parameter Settings for fS = 44.1 kHz (PLL Output = 45.1584 MHz = 1024 × fS)
MCLK Input (MHz)
Input Divider (X)
Integer (R)
Denominator (M)
Numerator (N)
R2: PLL Control Setting (Hex)
0x0271 0193 2901
0x0271 01DD 1901
0x1FBD 0F09 1901
0x007D 0022 3301
0x007D 0058 2301
0x0401 025C 2301
0x055F 0304 2301
0x0271 01DD 1B01
0x1FBD 0F09 1B01
0x0753 0287 1B01
8
12
13
14.4
19.2
19.68
19.8
24
1
1
1
2
2
2
2
2
2
2
5
3
3
6
4
4
4
3
3
3
625
625
8125
125
125
1025
1375
625
8125
1875
403
477
3849
34
88
604
772
477
3849
647
26
27
Table 16. Fractional PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS)
MCLK Input (MHz)
Input Divider (X)
Integer (R)
Denominator (M)
Numerator (N)
R2: PLL Control Setting (Hex)
0x007D 0012 3101
0x007D 000C 2101
0x0659 04F5 1901
0x004B 003E 3301
0x0019 0003 2B01
0x00CD 00CC 2301
0x0339 031C 2301
0x007D 000C 2301
0x0659 04F5 1B01
0x0465 02D1 1B01
8
12
13
14.4
19.2
19.68
19.8
24
1
1
1
2
2
2
2
2
2
2
6
4
3
6
5
4
4
4
3
3
125
125
1625
75
18
12
1269
62
3
204
796
12
1269
721
25
205
825
125
1625
1125
26
27
Table 17. Integer PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS)
MCLK Input (MHz)
Input Divider (X)
Integer (R)
Denominator (M)
Numerator (N)
R2: PLL Control Setting (Hex)1
0xXXXX XXXX 2001
12.288
24.576
1
1
4
2
Don’t care
Don’t care
Don’t care
Don’t care
0xXXXX XXXX 1001
1 X = don’t care.
Rev. A | Page 26 of 76
Data Sheet
ADAU1961
RECORD SIGNAL PATH
MICIN LEFT
DIGITAL
MICROPHONE
INTERFACE
JACKDET/MICIN
MICIN RIGHT
LINNG[2:0]
MIXER 1
(LEFT RECORD
MIXER)
–12dB TO +6dB
LDBOOST[1:0]
PGA
LINN
LEFT
ADC
MUTE/0dB/20dB
LINPG[2:0]
–12dB TO
+35.25dB
LINP
–12dB TO +6dB
MIXER 1
INSEL
OUTPUT
(TO PLAYBACK
MIXER)
ALCSEL[2:0]
LDVOL[5:0]
ALC
CONTROL
DECIMATOR/
ALC/
DIGITAL
VOLUME
MX1AUXG[2:0]
LAUX
RAUX
–12dB TO +6dB
AUXILIARY
BYPASS
MX2AUXG[2:0]
–12dB TO +6dB
RINPG[2:0]
MIXER 2
OUTPUT
(TO PLAYBACK
MIXER)
–12dB TO +6dB
RDBOOST[1:0]
PGA
RINP
RINN
RIGHT
ADC
MUTE/0dB/20dB
RINNG[2:0]
MIXER 2
–12dB TO
+35.25dB
(RIGHT RECORD
MIXER)
INSEL
–12dB TO +6dB
ALCSEL[2:0]
RDVOL[5:0]
ALC
CONTROL
Figure 31. Record Signal Path
Signals are inverted through the PGAs and the mixers. The
result of this inversion is that differential signals input through
the PGA are output from the ADCs at the same polarity as they
are input. Single-ended inputs that pass through the mixer but
not through the PGA are inverted. The ADCs are noninverting.
INPUT SIGNAL PATHS
The ADAU1961 can accept both line level and microphone
inputs. The analog inputs can be configured in a single-ended
or differential configuration. There is also an input for a digital
microphone. The analog inputs are biased at AVDD/2. Unused
input pins should be connected to CM.
The input impedance of the analog inputs varies with the gain
of the PGA. This impedance ranges from 1.7 kΩ at the 35.25 dB
gain setting to 80.4 kΩ at the −12 dB setting. This range is shown
in Figure 22.
Each of the six analog inputs has individual gain controls (boost
or cut). The input signals are mixed and routed to an ADC. The
mixed input signals can also bypass the ADCs and be routed
directly to the playback mixers. Left channel inputs are mixed
before the left ADC; however, it is possible to route the mixed
analog signal around the ADC and output it into a left or right
output channel. The same capabilities apply to the right channel
and the right ADC.
Rev. A | Page 27 of 76
ADAU1961
Data Sheet
Analog Microphone Inputs
Analog Line Inputs
For microphone inputs, configure the part in either stereo
pseudo-differential mode or stereo full differential mode.
Line input signals can be accepted by any analog input. It is
possible to route signals on the RINN, RINP, LINN, and LINP
pins around the differential amplifier to their own amplifier and
to use these pins as single-ended line inputs by disabling the
LDEN and RDEN bits (Bit 0 in Register R8, Address 0x400E,
and Bit 0 in Register R9, Address 0x400F). Figure 34 depicts a
stereo single-ended line input using the RINN and LINN pins.
The LINN and LINP pins are the inverting and noninverting
inputs for the left channel, respectively. The RINN and RINP
pins are the inverting and noninverting inputs for the right
channel, respectively.
For a differential microphone input, connect the positive signal
to the noninverting input of the PGA and the negative signal to
the inverting input of the PGA, as shown in Figure 32. The PGA
settings are controlled with Register R8 (left differential input
volume control register, Address 0x400E) and Register R9 (right
differential input volume control register, Address 0x400F). The
PGA must first be enabled by setting the RDEN and LDEN bits.
The LAUX and RAUX pins are single-ended line inputs. They
can be used together as a stereo single-ended auxiliary input, as
shown in Figure 34. These inputs can bypass the input gain
control, mixers, and ADCs to directly connect to the output
playback mixers (see auxiliary bypass in Figure 31).
ADAU1961
LINNG[2:0]
ADAU1961
LINN
LEFT LINE
LEFT
INPUT
PGA
LDBOOST[1:0]
LINP
–12dB TO +6dB
LEFT
LINN
LAUX
MICROPHONE
LEFT AUX
INPUT
MUTE/
0dB/20dB
AUXILIARY
BYPASS
–12dB TO
+35.25dB
2kΩ
RAUX
RIGHT AUX
MICBIAS
INPUT
RINNG[2:0]
RINN
RIGHT LINE
RIGHT
PGA
2kΩ
INPUT
RDBOOST[1:0]
RINN
RINP
–12dB TO +6dB
RIGHT
MICROPHONE
Figure 34. Stereo Single-Ended Line Input with Stereo Auxiliary Bypass
MUTE/
0dB/20dB
–12dB TO
+35.25dB
Figure 32. Stereo Differential Microphone Configuration
The PGA can also be used for single-ended microphone inputs.
Connect LINP and/or RINP to the CM pin. In this configura-
tion, the signal connects to the inverting input of the PGA,
LINN and/or RINN, as shown in Figure 33.
ADAU1961
LEFT
PGA
LDBOOST[1:0]
LINN
LEFT
MICROPHONE
LINP
MUTE/
0dB/20dB
CM
–12dB TO
+35.25dB
2kΩ
MICBIAS
RIGHT
PGA
2kΩ
RDBOOST[1:0]
RINP
RINN
RIGHT
MICROPHONE
MUTE/
0dB/20dB
–12dB TO
+35.25dB
Figure 33. Stereo Single-Ended Microphone Configuration
Rev. A | Page 28 of 76
Data Sheet
ADAU1961
Digital Microphone Input
ANALOG-TO-DIGITAL CONVERTERS
When using a digital microphone connected to the JACKDET/
MICIN pin, the JDFUNC[1:0] bits in Register R2 (Address 0x4008)
must be set to 10 to enable the microphone input and disable
the jack detection function. The ADAU1961 must operate in
master mode and source BCLK to the input clock of the digital
microphone.
The ADAU1961 uses two 24-bit Σ-Δ analog-to-digital con-
verters (ADCs) with selectable oversampling ratios of 64× or
128× (selected by Bit 3 in Register R17, Address 0x4017).
ADC Full-Scale Level
The full-scale input to the ADCs (0 dBFS) is 1.0 V rms with
AVDD = 3.3 V. This full-scale analog input will output a digital
signal at −1.38 dBFS. This gain offset is built into the ADAU1961
to prevent clipping. The full-scale input level scales linearly with
the level of AVDD.
The digital microphone signal bypasses record path mixers and
ADCs and is routed directly into the decimation filters. The
digital microphone and ADCs share decimation filters and,
therefore, both cannot be used simultaneously. The digital
microphone input select bit, INSEL, can be set in Register R19
(ADC control register, Address 0x4019). Figure 35 depicts the
digital microphone interface and signal routing.
For single-ended and pseudo-differential signals, the full-scale
value corresponds to the signal level at the pins, 0 dBFS.
The full differential full-scale input level is measured after the
differential amplifier, which corresponds to −6 dBFS at each pin.
JACKDET/MICIN
R2: DIGITAL MICROPHONE/
JACK DETECTION
CONTROL
Signal levels above the full-scale value cause the ADCs to clip.
Digital ADC Volume Control
JDFUNC[1:0]
TO JACK
DETECTION
CIRCUIT
The digital ADC volume can be attenuated using Register R20 (left
input digital volume register, Address 0x401A) and Register R21
(right input digital volume register, Address 0x401B).
DIGITAL MICROPHONE
INTERFACE
High-Pass Filter
RIGHT
ADC
LEFT
RIGHT
CHANNEL CHANNEL
By default, a high-pass filter is used in the ADC path to remove
dc offsets; this filter can be enabled or disabled in Register R19
(ADC control register, Address 0x4019). At fS = 48 kHz, the
corner frequency of this high-pass filter is 2 Hz.
LEFT
ADC
R19: ADC CONTROL
INSEL
DECIMATORS
Figure 35. Digital Microphone Interface Block Diagram
Microphone Bias
The MICBIAS pin provides a voltage reference for electret analog
microphones. The MICBIAS voltage is set in Register R10
(record microphone bias control register, Address 0x4010). In
this register, the MICBIAS output can be enabled or disabled.
Additional options include high performance operation and a
gain boost. The gain boost provides two different voltage biases:
0.65 × AVDD or 0.90 × AVDD. When enabled, the high perfor-
mance bit increases supply current to the microphone bias
circuit to decrease rms input noise.
The MICBIAS pin can also be used to cleanly supply voltage
to digital microphones or analog microphones with separate
power supply pins.
Rev. A | Page 29 of 76
ADAU1961
Data Sheet
AUTOMATIC LEVEL CONTROL (ALC)
The ADAU1961 contains a hardware automatic level control
(ALC). The ALC is designed to continuously adjust the PGA
gain to keep the recording volume constant as the input level
varies.
•
ALCATCK[3:0]: The ALC attack time sets how fast the
ALC starts attenuating after a sudden increase in input
level above the ALC target. Although it may seem that
the attack time should be set as fast as possible to avoid
clipping on transients, using a moderate value results in
better overall sound quality. If the value is too fast, the
ALC overreacts to very short transients, causing audible
gain-pumping effects, which sounds worse than using a
moderate value that allows brief periods of clipping on
transients. A typical setting for music recording is 384 ms.
A typical setting for voice recording is 24 ms.
ALCHOLD[3:0]: These bits set the ALC hold time. When
the output signal falls below the target output level, the
gain is not increased unless the output remains below the
target level for the period of time set by the hold time bits.
The hold time is used to prevent the gain from modulating
on a steady low frequency sine wave signal, which would
cause distortion.
ALCDEC[3:0]: The ALC decay time sets how fast the ALC
increases the PGA gain after a sudden decrease in input level
below the ALC target. A very slow setting can be used if the
main function of the ALC is to set a music recording level.
A faster setting can be used if the function of the ALC is to
compress the dynamic range of a voice recording. Using a
very fast decay time can cause audible artifacts such as noise
pumping or distortion. A typical setting for music recording
is 24.58 sec. A typical setting for voice recording is 1.54 sec.
ALCMAX[2:0]: The maximum ALC gain bits are used to
limit the maximum gain that can be programmed into the
ALC. This can be used to prevent excessive noise in the
recording for small input signals. Note that setting this
register to a low value may prevent the ALC from reaching
its target output level, but this behavior is often desirable to
achieve the best overall sound.
For optimal noise performance, the ALC uses the analog PGA
to adjust the gain instead of using a digital method. This ensures
that the ADC noise is not amplified at low signal levels.
Extremely small gain step sizes are used to ensure high audio
quality during gain changes.
To use the ALC function, the inputs must be applied either
differentially or pseudo-differentially to input pins LINN and
LINP, for the left channel, and RINN and RINP, for the right
channel. The ALC function is not available for the auxiliary line
input pins, LAUX and RAUX.
•
•
A block diagram of the ALC block is shown in Figure 36. The
ALC logic receives the ADC output signals and analyzes these
digital signals to set the PGA gain. The ALC control registers
are used to control the time constants and output levels, as
described in this section.
ANALOG
LEFT
INPUT
ADC
LEFT
PGA
SERIAL
PORTS
–12dB TO +35.25dB
0.75dB STEP SIZE
MUTE
ANALOG
INPUT
RIGHT
RIGHT
ADC
2
I C
ALC
DIGITAL
CONTROL
•
Figure 36. ALC Architecture
ALC PARAMETERS
The ALC function is controlled with the ALC control registers
(Address 0x4011 through Address 0x4014) using the following
parameters:
•
ALCSEL[2:0]: The ALC select bits are used to enable the
ALC and set the mode to left only, right only, or stereo. In
stereo mode, the greater of the left or right inputs is used
to calculate the gain, and the same gain is then applied to
both the left and right channels.
ALCTARG[3:0]: The ALC target is the desired input
recording level that the ALC attempts to achieve.
Figure 37 shows the dynamic behavior of the PGA gain for a
tone-burst input. The target output is achieved for three differ-
ent input levels, with the effect of attack, hold, and decay shown
in the figure. Note that for very small signals, the maximum PGA
gain may prevent the ALC from achieving its target level; in the
same way, for very large inputs, the minimum PGA gain may
prevent the ALC from achieving its target level (assuming that
the target output level is set to a very low value). The effects of
the PGA gain limit are shown in the input/output graph of
Figure 38.
•
Rev. A | Page 30 of 76
Data Sheet
ADAU1961
the threshold for 250 ms before the noise gate operates.
Hysteresis is used so that the threshold for coming out of the
mute state is 6 dB higher than the threshold for going into the
mute state. There are four operating modes for the noise gate.
INPUT
Noise Gate Mode 0 (see Figure 39) is selected by setting the
NGTYP[1:0] bits to 00. In this mode, the current state of the
PGA gain is held at its current state when the noise gate logic is
activated. This prevents a large increase in background noise
during periods of silence. When using this mode, it is advisable
to use a relatively slow decay time. This is because the noise gate
takes at least 250 ms to activate, and if the PGA gain has already
increased to a large value during this time, the value at which
the gain is held will be large.
GAIN
OUTPUT
THRESHOLD
INPUT
HOLD DECAY
TIME TIME
ATTACK
TIME
Figure 37. Basic ALC Operation
ANALOG
GAIN
MAX GAIN = 30dB
MAX GAIN = 24dB
MAX GAIN = 18dB
250ms
GAIN HELD
INTERNAL
NOISE GATE
ENABLE SIGNAL
MIN PGA
GAIN POINT
DIGITAL
MUTE
TARGET
OUTPUT
INPUT LEVEL (dB)
Figure 38. Effect of Varying the Maximum Gain Parameter
Figure 39. Noise Gate Mode 0 (PGA Gain Hold)
NOISE GATE FUNCTION
Noise Gate Mode 1 (see Figure 40) is selected by setting the
NGTYP[1:0] bits to 01. In this mode, the ADAU1961 does a
simple digital mute of the ADC output. Although this mode
completely eliminates any background noise, the effect of an
abrupt mute may not be pleasant to the ear.
When using the ALC, one potential problem is that for small
input signals, the PGA gain can become very large. A side effect
of this is that the noise is amplified along with the signal of
interest. To avoid this situation, the ADAU1961 noise gate can
be used. The noise gate cuts off the ADC output when its signal
level is below a set threshold. The noise gate is controlled using
the following parameters in the ALC Control 3 register
(Address 0x4014):
THRESHOLD
INPUT
NGTYP[1:0]: The noise gate type is set to one of four
modes by writing to the NGTYP[1:0] bits.
NGEN: The noise gate function is enabled by writing to the
NGEN bit.
NGTHR[4:0]: The threshold for muting the output is set by
writing to the NGTHR[4:0] bits.
ANALOG
GAIN
250ms
INTERNAL
NOISE GATE
ENABLE SIGNAL
DIGITAL
MUTE
One common problem with noise gate functions is chatter,
where a small signal that is close to the noise gate threshold
varies in amplitude, causing the noise gate function to open and
close rapidly. This causes an unpleasant sound.
OUTPUT
To reduce this effect, the noise gate in the ADAU1961 uses a
combination of a timeout period and hysteresis. The timeout
period is set to 250 ms, so the signal must consistently be below
Figure 40. Noise Gate Mode 1 (Digital Mute)
Rev. A | Page 31 of 76
ADAU1961
Data Sheet
Noise Gate Mode 2 (see Figure 41) is selected by setting the
NGTYP[1:0] bits to 10. In this mode, the ADAU1961 improves
the sound of the noise gate operation by first fading the PGA
gain over a period of about 100 ms to the minimum PGA gain
value. The ADAU1961 does not do a hard mute after the fade is
complete, so some small background noise will still exist.
Noise Gate Mode 3 (see Figure 42) is selected by setting the
NGTYP[1:0] bits to 11. This mode is the same as Mode 2 except
that at the end of the PGA fade gain interval, a digital mute is
performed. In general, this mode is the best-sounding mode,
because the audible effect of the digital hard mute is reduced by
the fact that the gain has already faded to a low level before the
mute occurs.
THRESHOLD
THRESHOLD
INPUT
INPUT
ANALOG
ANALOG
GAIN
250ms
GAIN
250ms
MIN GAIN
100ms
MIN GAIN
100ms
INTERNAL
NOISE GATE
ENABLE SIGNAL
INTERNAL
NOISE GATE
ENABLE SIGNAL
DIGITAL
MUTE
DIGITAL
MUTE
OUTPUT
OUTPUT
Figure 42. Noise Gate Mode 3 (Analog Fade/Digital Mute)
Figure 41. Noise Gate Mode 2 (Analog Fade)
Rev. A | Page 32 of 76
Data Sheet
ADAU1961
PLAYBACK SIGNAL PATH
MX3G1[3:0]
LEFT INPUT MIXER
–15dB TO +6dB
MX3G2[3:0]
RIGHT INPUT MIXER
–15dB TO +6dB
MIXER 3
(LEFT
PLAYBACK
MIXER)
MX3AUXG[3:0]
LHPVOL[5:0]
LAUX
LHP
–15dB TO +6dB
–57dB TO +6dB
LOUTVOL[5:0]
MIXER 5
(LEFT L/R
PLAYBACK
MIXER)
LEFT DAC
LOUTP
MX3LM
MX3RM
–57dB TO +6dB
MX5G3[1:0]
RIGHT DAC
–1
LOUTN
MX6G3[1:0]
MONOVOL[5:0]
MX7[1:0]
MIXER 7
(MONO MIXER)
MONOOUT
ROUTN
–57dB TO +6dB
–1
MX4G1[3:0]
MIXER 6
(RIGHT L/R
PLAYBACK
MIXER)
LEFT INPUT MIXER
–15dB TO +6dB
ROUTVOL[5:0]
MX5G4[1:0]
MX4G2[3:0]
ROUTP
RHP
–57dB TO +6dB
RIGHT INPUT MIXER
–15dB TO +6dB
MX6G4[1:0]
MX4AUXG[3:0]
RHPVOL[5:0]
RAUX
–15dB TO +6dB
–57dB TO +6dB
MIXER 4
(RIGHT
PLAYBACK
MIXER)
LEFT DAC
MX4LM
MX4RM
RIGHT DAC
Figure 43. Playback Signal Path
Routing Flexibility
OUTPUT SIGNAL PATHS
The playback path contains five mixers (Mixer 3 to Mixer 7)
that perform the following functions:
The outputs of the ADAU1961 can be configured as a variety of
differential or single-ended outputs. All analog output pins are
capable of driving headphone or earpiece speakers. There are
selectable output paths for stereo signals or a downmixed mono
output. The line outputs can drive a load of at least 10 kΩ or can
be put into HP mode to drive headphones or earpiece speakers.
The analog output pins are biased at AVDD/2.
•
•
•
Mix signals from the record path and the DACs.
Mix or swap the left and right channels.
Mix a mono signal or generate a common-mode output.
Mixer 3 and Mixer 4 are dedicated to mixing signals from the
record path and the DACs. Each of these two mixers can accept
signals from the left and right DACs, the left and right input
mixers, and the dedicated channel auxiliary input. Signals
coming from the record path can be boosted or cut before the
playback mixer.
With a 0 dBFS digital input and AVDD = 3.3 V, the full-scale
output level is 920 mV rms.
Signals are inverted through the mixers and volume controls.
The result of this inversion is that the polarity of the differential
outputs and the headphone outputs is preserved. The single-
ended mono output is inverted. The DACs are noninverting.
For example, the MX4G2[3:0] bits set the gain from the output
of Mixer 2 (right record channel) to the input of Mixer 4, hence
the naming convention.
Signals coming from the DACs have digital volume attenu-
ation controls set in Register R20 (left input digital volume
register, Address 0x401A) and Register R21 (right input digital
volume register, Address 0x401B).
Rev. A | Page 33 of 76
ADAU1961
Data Sheet
Headphone Output Power-Up/Power-Down Sequencing
HEADPHONE OUTPUT
To prevent pops when turning on the headphone outputs, the
user must wait at least 4 ms to unmute these outputs after
enabling the headphone output with the HPMODE bit. This is
because of an internal capacitor that must charge before these
outputs can be used. Figure 45 and Figure 46 illustrate the
headphone power-up/power-down sequencing.
The LHP and RHP pins can be driven by either a line output
driver or a headphone driver by setting the HPMODE bit in
Register R30 (playback headphone right volume control register,
Address 0x4024). The headphone outputs can drive a load of at
least 16 Ω.
Separate volume controls for the left and right channels range
from −57 dB to +6 dB. Slew can be applied to all the playback
volume controls using the ASLEW[1:0] bits in Register R34
(playback pop/click suppression register, Address 0x4028).
For capless headphones, configure the MONOOUT pin before
unmuting the headphone outputs.
USER
DEFINED
4ms
Capless Headphone Configuration
HPMODE
The headphone outputs can be configured in a capless output
configuration with the MONOOUT pin used as a dc virtual
ground reference. Figure 44 depicts a typical playback path in
a capless headphone configuration. Table 18 lists the register
settings for this configuration. As shown in this table, the
MONOOUT pin outputs common mode (AVDD/2), which
is used as the virtual headphone reference.
1 = HEADPHONE
RHPM AND LHPM
1 = UNMUTE
INTERNAL
PRECHARGE
LHPVOL[5:0]
Figure 45. Headphone Output Power-Up Timing
MIXER 3
MX3LM
LEFT
DAC
LHP
MX3EN
USER DEFINED
RHPM AND LHPM
0 = MUTE
MONOM
MIXER 7
MX7[1:0]
MONOOUT
MX7EN
MOMODE
HPMODE
0 = LINE OUTPUT
RHPVOL[5:0]
MIXER 4
MX4EN
MX4RM
Figure 46. Headphone Output Power-Down Timing
RIGHT
DAC
RHP
Ground-Centered Headphone Configuration
Figure 44. Capless Headphone Configuration Diagram
The headphone outputs can also be configured as ground-
centered outputs by placing coupling capacitors on the LHP
and RHP pins. Ground-centered headphones should use the
AGND pin as the ground reference.
Table 18. Capless Headphone Register Settings
Register
Bit Name
DACEN[1:0]
MX3EN
Setting
R36
R22
11 = both DACs on
1 = enable Mixer 3
When the headphone outputs are configured in this manner,
the capacitors create a high-pass filter on the outputs. The
corner frequency of this filter, at which point its attenuation
is 3 dB, is calculated by the following formula:
MX3LM
MX4EN
1 = unmute left DAC input
1 = enable Mixer 4
R24
R28
R33
R29
R30
MX4RM
MX7EN
MX7[1:0]
MONOM
MOMODE
1 = unmute right DAC input
1 = enable Mixer 7
00 = common-mode output
1 = unmute mono output
1 = headphone output
f
3dB = 1/(2π × R × C)
where:
C is the capacitor value.
R is the impedance of the headphones.
LHPVOL[5:0] Desired volume for LHP output
LHPM
HPMODE
1 = unmute left headphone output
1 = headphone output
For a typical headphone impedance of 16 Ω and a 47 μF
capacitor, the corner frequency is 211 Hz.
RHPVOL[5:0] Desired volume for RHP output
RHPM 1 = unmute right headphone output
Rev. A | Page 34 of 76
Data Sheet
ADAU1961
Jack Detection
LINE OUTPUTS
When the JACKDET/MICIN pin is set to the jack detect func-
tion, a flag on this pin can be used to mute the line outputs
when headphones are plugged into the jack. This pin can be
configured in Register R2 (digital microphone/jack detection
control register, Address 0x4008). The JDFUNC[1:0] bits set the
functionality of the JACKDET/MICIN pin.
The line output pins (LOUTP, LOUTN, ROUTP, and ROUTN)
can be used to drive both differential and single-ended loads. In
their default settings, these pins can drive typical line loads of
10 kΩ or greater, but they can also be put into headphone mode
by setting the LOMODE bit in Register R31 (playback line output
left volume control register, Address 0x4025) and the ROMODE
bit in Register R32 (playback line output right volume control
register, Address 0x4026). In headphone mode, the line output
pins are capable of driving headphone and earpiece speakers of
16 Ω or greater. The output impedance of the line outputs is
approximately 1 kΩ.
Additional settings for jack detection include debounce time
(JDDB[1:0] bits) and detection polarity (JDPOL bit). Because
the jack detection and digital microphone share a pin, both
functions cannot be used simultaneously.
POP-AND-CLICK SUPPRESSION
When the line output pins are used in single-ended mode,
LOUTP and ROUTP should be used to output the signals, and
LOUTN and ROUTN should be left unconnected.
Upon power-up, precharge circuitry is enabled to suppress pops
and clicks. After power-up, the precharge circuitry can be put
into a low power mode using the POPMODE bit in Register R34
(playback pop/click suppression register, Address 0x4028).
The volume controls for these outputs range from −57 dB to
+6 dB. Slew can be applied to all the playback volume controls
using the ASLEW[1:0] bits in Register R34 (playback pop/click
suppression register, Address 0x4028).
The precharge time depends on the capacitor value on the CM
pin and the RC time constant of the load. For a typical line output
load, the precharge time is between 2 ms and 3 ms. After this
precharge time, the POPMODE bit can be set to low power mode.
The MX5G4[1:0], MX5G3[1:0], MX6G3[1:0], and MX6G4[1:0]
bits can all provide a 6 dB gain boost to the line outputs. This
gain boost allows single-ended output signals to achieve 0 dBV
(1.0 V rms) and differential output signals to achieve up to
6 dBV (2.0 V rms). For more information, see Register R26
(playback L/R mixer left (Mixer 5) line output control register,
Address 0x4020) and Register R27 (playback L/R mixer right
(Mixer 6) line output control register, Address 0x4021).
Changing any register settings that affect the signal path can
cause pops and clicks on the analog outputs. To avoid these pops
and clicks, mute the appropriate outputs using Register R29 to
Register R32 (Address 0x4023 to Address 0x4026). Unmute the
analog outputs after the changes are made.
MX5G3[1:0]
LOUTVOL[5:0]
MIXER 3
MIXER 5
LEFT DAC
LOUTP
–1
–1
LOUTN
ROUTN
MX6G4[1:0]
ROUTVOL[5:0]
MIXER 4
MIXER 6
RIGHT DAC
ROUTP
Figure 47. Differential Line Output Configuration
Rev. A | Page 35 of 76
ADAU1961
Data Sheet
CONTROL PORTS
The ADAU1961 can operate in one of two control modes:
The subaddresses are autoincremented by 1 following each
read or write of a data-word, regardless of whether there is a
valid register word at that address. Address holes in the register
map can be written to or read from without consequence. In
the ADAU1961, these address holes exist at Address 0x4001,
Address 0x4003 to Address 0x4007, Address 0x402E, and
Address 0x4032 to Address 0x4035. A single-byte write to these
registers is ignored by the ADAU1961, and a read returns a
single byte 0x00.
•
•
I2C control
SPI control
The ADAU1961 has both a 4-wire SPI control port and a
2-wire I2C bus control port. Both ports can be used to set the
registers. The part defaults to I2C mode, but it can be put into
CLATCH
SPI control mode by pulling the
pin low three times.
The control port is capable of full read/write operation for all
addressable registers. The ADAU1961 must have a valid master
clock in order to write to all registers except for Register R0
(Address 0x4000) and Register R1 (Address 0x4002).
I2C PORT
The ADAU1961 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU1961 and the system I2C master controller.
In I2C mode, the ADAU1961 is always a slave on the bus,
meaning that it cannot initiate a data transfer. Each slave device
All addresses can be accessed in both a single-address mode
or a burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/ bit. The next two
bytes (Byte 1 and Byte 2) together form the subaddress of the
register location within the ADAU1961. This subaddress must
be two bytes long because the memory locations within the
ADAU1961 are directly addressable and their sizes exceed the
range of single-byte addressing. All subsequent bytes (starting
with Byte 3) contain the data. The number of bytes per word
depends on the type of data that is being written.
W
W
is recognized by a unique address. The address and R/ byte
format is shown in Table 20. The address resides in the first
seven bits of the I2C write. Bits[5:6] of the I2C address for the
ADAU1961 are set by the levels on the ADDR1 and ADDR0
W
pins. The LSB of the address—the R/ bit—specifies either a
read or write operation. Logic Level 1 corresponds to a read
operation, and Logic Level 0 corresponds to a write operation.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 19 describes these
multiple functions.
2
Write
Table 20. ADAU1961 I C Address and Read/
Byte Format
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5
Bit 6 Bit 7
0
1
1
1
0
ADDR1 ADDR0 R/W
Table 19. Control Port Pin Functions
Pin Name
SCL/CCLK
SDA/COUT
I2C Mode
SPI Mode
The SDA and SCL pins should each have a 2 kΩ pull-up resistor
on the line connected to it. The voltage on these signal lines
should not be higher than IOVDD (3.3 V).
SCL: input clock
CCLK: input clock
COUT: output
SDA: open-collector
input/output
I2C Address Bit 1: input
Addressing
ADDR1/CDATA
ADDR0/CLATCH I2C Address Bit 0: input
CDATA: input
CLATCH: input
Initially, each device on the I2C bus is in an idle state and
monitors the SDA and SCL lines for a start condition and
the proper address. The I2C master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream follows. All devices on the bus respond to the start
condition and shift the next eight bits (the 7-bit address plus the
BURST MODE WRITING AND READING
Burst mode addressing, where the subaddresses are automatically
incremented at word boundaries, can be used for writing large
amounts of data to contiguous registers. This increment happens
automatically after a single-word write or read unless a stop condi-
2
CLATCH
tion is encountered (I C) or
is brought high (SPI). A
W
R/ bit) MSB first. The device that recognizes the transmitted
burst write starts like a single-word write, but following the first
data-word, the data-word for the next immediate address can be
written immediately without sending its two-byte address.
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is known as an acknowledge bit. All
other devices withdraw from the bus at this point and return to
the idle condition.
The registers in the ADAU1961 are one byte wide with the
exception of the PLL control register, which is six bytes wide.
The autoincrement feature knows the word length at each
subaddress, so the subaddress does not need to be specified
manually for each address in a burst write.
Rev. A | Page 36 of 76
Data Sheet
ADAU1961
W
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADAU1961 does
not issue an acknowledge and returns to the idle condition.
The R/ bit determines the direction of the data. A Logic 0 on
the LSB of the first byte means that the master will write infor-
mation to the peripheral, whereas a Logic 1 means that the
master will read information from the peripheral after writing
the subaddress and repeating the start address. A data transfer
takes place until a stop condition is encountered. A stop
condition occurs when SDA transitions from low to high while
SCL is held high. Figure 48 shows the timing of an I2C write,
and Figure 49 shows an I2C read.
If the user exceeds the highest subaddress while in autoincrement
mode, one of two actions is taken. In read mode, the ADAU1961
outputs the highest subaddress register contents until the master
device issues a no acknowledge, indicating the end of a read. A
no acknowledge condition is where the SDA line is not pulled
low on the ninth clock pulse on SCL. If the highest subaddress
location is reached while in write mode, the data for the invalid
byte is not loaded into any subaddress register, a no acknowledge
is issued by the ADAU1961, and the part returns to the idle
condition.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, the ADAU1961 immediately
jumps to the idle condition. During a given SCL high period,
SCL
0
1
1
1
SDA
R/W
0
ADDR1 ADDR0
ACK BY
ADAU1961
ACK BY
ADAU1961
START BY
MASTER
FRAME 2
SUBADDRESS BYTE 1
FRAME 1
CHIP ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
ACK BY
ADAU1961
ACK BY STOP BY
ADAU1961 MASTER
FRAME 4
DATA BYTE 1
FRAME 3
SUBADDRESS BYTE 2
Figure 48. I2C Write to ADAU1961 Clocking
SCL
SDA
0
1
1
1
0
R/W
ACK BY
ADAU1961
ADDR1 ADDR0
ACK BY
ADAU1961
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
SUBADDRESS BYTE 1
SCL
(CONTINUED)
SDA
(CONTINUED)
0
1
1
1
0
R/W
ACK BY
ADAU1961
ADDR1 ADDR0
ACK BY
ADAU1961
REPEATED
START BY MASTER
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
CHIP ADDRESS BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
ACK BY
STOP BY
MASTER MASTER
FRAME 5
READ DATA BYTE 1
Figure 49. I2C Read from ADAU1961 Clocking
Rev. A | Page 37 of 76
ADAU1961
Data Sheet
I2C Read and Write Operations
This causes the ADAU1961 SDA to reverse and begin driving
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1961.
Figure 50 shows the format of a single-word write operation.
Every ninth clock pulse, the ADAU1961 issues an acknowledge
by pulling SDA low.
Figure 53 shows the format of a burst mode read sequence. This
figure shows an example of a read from sequential single-byte
registers. The ADAU1961 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length. The
ADAU1961 always decodes the subaddress and sets the auto-
increment circuit so that the address increments after the
appropriate number of bytes.
Figure 51 shows the format of a burst mode write sequence. This
figure shows an example of a write to sequential single-byte
registers. The ADAU1961 increments its subaddress register
after every byte because the requested subaddress corresponds
to a register or memory area with a 1-byte word length.
Figure 52 shows the format of a single-word read operation. Note
W
that the first R/ bit is 0, indicating a write operation. This is
Figure 50 to Figure 53 use the following abbreviations:
S = start bit
P = stop bit
AM = acknowledge by master
AS = acknowledge by slave
because the subaddress still needs to be written to set up the
internal address. After the ADAU1961 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
W
followed by the chip address byte with the R/ bit set to 1 (read).
S
S
S
S
Chip address,
R/W = 0
AS
Subaddress high byte
AS
Subaddress low byte
AS
Data Byte 1
P
Figure 50. Single-Word I2C Write Format
Chip address, AS Subaddress AS Subaddress AS Data
R/W = 0
AS Data
Byte 2
AS Data
Byte 3
AS Data
Byte 4
AS
…
P
high byte
low byte
Byte 1
Figure 51. Burst Mode I2C Write Format
Chip address,
R/W = 0
AS
Subaddress high
byte
AS
Subaddress low
byte
AS
S
Chip address,
R/W = 1
AS
Data
P
Byte 1
Figure 52. Single-Word I2C Read Format
Chip address,
R/W = 0
AS Subaddress AS Subaddress AS
high byte low byte
S
Chip address,
R/W = 1
AS Data
Byte 1
AM Data
Byte 2
AM
…
P
Figure 53. Burst Mode I2C Read Format
Rev. A | Page 38 of 76
Data Sheet
ADAU1961
W
Chip Address R/
SPI PORT
By default, the ADAU1961 is in I2C mode, but it can be put into
W
The LSB of the first byte of an SPI transaction is a R/ bit. This bit
determines whether the communication is a read (Logic Level 1)
or a write (Logic Level 0). This format is shown in Table 21.
CLATCH
SPI control mode by pulling
low three times. This is
done by performing three dummy writes to the SPI port (the
ADAU1961 does not acknowledge these three writes). Beginning
with the fourth SPI write, data can be written to or read from
the IC. The ADAU1961 can be taken out of SPI mode only by
a full reset initiated by power-cycling the IC.
Write
Table 21. ADAU1961 SPI Address and Read/
Byte Format
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
0
0
0
0
0
0
R/W
CLATCH
The SPI port uses a 4-wire interface, consisting of the
CCLK, CDATA, and COUT signals, and it is always a slave port.
CLATCH
,
Subaddress
The 16-bit subaddress word is decoded into a location in one of
the registers. This subaddress is the location of the appropriate
register. The MSBs of the subaddress are zero-padded to bring
the word to a full 2-byte length.
The
signal should go low at the beginning of a trans-
action and high at the end of a transaction. The CCLK signal
latches CDATA on a low-to-high transition. COUT data is shifted
out of the ADAU1961 on the falling edge of CCLK and should
be clocked into a receiving device, such as a microcontroller, on
the CCLK rising edge. The CDATA signal carries the serial input
data, and the COUT signal carries the serial output data. The
COUT signal remains three-state until a read operation is requested.
This allows other SPI-compatible peripherals to share the same
readback line. All SPI transactions have the same basic format
shown in Table 22. A timing diagram is shown in Figure 4. All
data should be written MSB first.
Data Bytes
The number of data bytes varies according to the register being
accessed. During a burst mode write, an initial subaddress is
written followed by a continuous sequence of data for consecu-
tive register locations.
A sample timing diagram for a single-word SPI write operation
to a register is shown in Figure 54. A sample timing diagram of
a single-word SPI read operation is shown in Figure 55. The
COUT pin goes from being three-state to being driven at the
beginning of Byte 3. In this example, Byte 0 to Byte 2 contain
W
the addresses and R/ bit, and subsequent bytes carry the data.
Table 22. Generic Control Word Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 41
chip_adr[6:0], R/W
subaddr[15:8]
subaddr[7:0]
data
data
1 Continues to end of data.
CLATCH
CCLK
CDATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
Figure 54. SPI Write to ADAU1961 Clocking (Single-Word Write Mode)
CLATCH
CCLK
CDATA
BYTE 1
BYTE 0
BYTE 2
HIGH-Z
HIGH-Z
COUT
DATA
Figure 55. SPI Read from ADAU1961 Clocking (Single-Word Read Mode)
Rev. A | Page 39 of 76
ADAU1961
Data Sheet
SERIAL DATA INPUT/OUTPUT PORTS
The flexible serial data input and output ports of the ADAU1961
can be set to accept or transmit data in 2-channel format or in a
4-channel TDM stream to interface to external ADCs or DACs.
Data is processed in twos complement, MSB first format. The
left channel data field always precedes the right channel data
field in 2-channel streams. In TDM mode, Slot 0 and Slot 1 are
in the first half of the audio frame, and Slot 2 and Slot 3 are in
the second half of the frame. The serial modes and the position
of the data in the frame are set in Register R15 to Register R18
(serial port and converter control registers, Address 0x4015 to
Address 0x4018).
The serial port can operate with an arbitrary number of BCLK
transitions in each LRCLK frame. The LRCLK in TDM mode
can be input to the ADAU1961 either as a 50% duty cycle clock
or as a bit-wide pulse.
When the LRCLK is set as a pulse, a 47 pF capacitor should be
connected between the LRCLK pin and ground (see Figure 56).
This capacitor is necessary in both master and slave modes to
properly align the LRCLK signal to the serial data stream.
ADAU1961
LRCLK
47pF
If the PLL of the ADAU1961 is not used, the serial data clocks
must be synchronous with the ADAU1961 master clock input.
The LRCLK and BCLK pins are used to clock both the serial
input and output ports. The ADAU1961 can be set as the master
or the slave in a system. Because there is only one set of serial
data clocks, the input and output ports must always be both
master or both slave.
BCLK
Figure 56. LRCLK Capacitor Alignment, TDM Pulse Mode
In TDM mode, the ADAU1961 can be a master for fS up to
48 kHz. Table 23 lists the modes in which the serial output
port can function.
Register R15 and Register R16 (serial port control registers,
Address 0x4015 and Address 0x4016) allow control of clock
polarity and data input modes. The valid data formats are I2S,
left-justified, right-justified (24-/20-/18-/16-bit), and TDM. In
all modes except for the right-justified modes, the serial port
inputs an arbitrary number of bits up to a limit of 24. Extra bits
do not cause an error, but they are truncated internally.
Table 23. Serial Output Port Master/Slave Mode Capabilities
2-Channel Modes (I2S, Left-
fS
Justified, Right-Justified)
4-Channel TDM
Master and slave
Slave
48 kHz
96 kHz
Master and slave
Master and slave
Table 24 describes the proper configurations for standard audio
data formats.
Table 24. Data Format Configurations
LRCLK Mode
(LRMOD)
BCLK Polarity
(BPOL)
BCLK Cycles/Audio Data Delay from LRCLK
Format
LRCLK Polarity (LRPOL)
Frame (BPF[2:0])
Edge (LRDEL[1:0])
I2S
Frame begins on falling edge 50% duty cycle Data changes
on falling edge
32 to 64
Delayed from LRCLK edge
by 1 BCLK
(see Figure 57)
Left-Justified (see Frame begins on rising edge
Figure 58)
50% duty cycle Data changes
on falling edge
50% duty cycle Data changes
on falling edge
32 to 64
32 to 64
64 to 128
64 to 128
Aligned with LRCLK edge
Right-Justified
(see Figure 59)
Frame begins on rising edge
Delayed from LRCLK edge
by 8 or 16 BCLKs
Delayed from start of word
clock by 1 BCLK
Delayed from start of word
clock by 1 BCLK
TDM with Clock
(see Figure 60)
Frame begins on falling edge 50% duty cycle Data changes
on falling edge
TDM with Pulse
(see Figure 61)
Frame begins on rising edge
Pulse
Data changes
on falling edge
Rev. A | Page 40 of 76
Data Sheet
ADAU1961
LEFT CHANNEL
LRCLK
BCLK
RIGHT CHANNEL
MSB
LSB
LSB
SDATA
MSB
1/fS
Figure 57. I2S Mode—16 Bits to 24 Bits per Channel
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
1/fS
Figure 58. Left-Justified Mode—16 Bits to 24 Bits per Channel
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
1/fS
Figure 59. Right-Justified Mode—16 Bits to 24 Bits per Channel
LRCLK
128 BCLKs
BCLK
32 BCLKs
SLOT 0
SDATA
SLOT 1
SLOT 2
SLOT 3
LRCLK
BCLK
SDATA
MSB
MSB – 1 MSB – 2
Figure 60. TDM 4 Mode
LRCLK
BCLK
MSB TDM
CH
0
SDATA
SLOT 0
32 BCLKs
SLOT 1
SLOT 2
SLOT 3
Figure 61. TDM 4 Mode with Pulse Word Clock
Rev. A | Page 41 of 76
ADAU1961
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY BYPASS CAPACITORS
GROUNDING
Each analog and digital power supply pin should be bypassed to
its nearest appropriate ground pin with a single 100 nF capaci-
tor. The connections to each side of the capacitor should be as
short as possible, and the trace should stay on a single layer with
no vias. For maximum effectiveness, locate the capacitor equi-
distant from the power and ground pins or, when equidistant
placement is not possible, slightly closer to the power pin.
Thermal connections to the ground planes should be made
on the far side of the capacitor.
A single ground plane should be used in the application layout.
Components in an analog signal path should be placed away
from digital signals.
EXPOSED PAD PCB DESIGN
The ADAU1961 has an exposed pad on the underside of the
LFCSP. This pad is used to couple the package to the PCB for
heat dissipation when using the outputs to drive earpiece or
headphone loads. When designing a board for the ADAU1961,
special consideration should be given to the following:
Each supply signal on the board should also be bypassed with a
single bulk capacitor (10 μF to 47 μF).
VDD GND
•
A copper layer equal in size to the exposed pad should be
on all layers of the board, from top to bottom, and should
connect somewhere to a dedicated copper board layer (see
Figure 64).
•
Vias should be placed to connect all layers of copper,
allowing for efficient heat and energy conductivity. For an
example, see Figure 65, which has nine vias arranged in a
3 inch × 3 inch grid in the pad area.
CAPACITOR
TO VDD
TOP
GROUND
POWER
BOTTOM
TO GND
Figure 62. Recommended Power Supply Bypass Capacitor Layout
VIAS
COPPER SQUARES
Figure 64. Exposed Pad Layout Example, Side View
GSM NOISE FILTER
In mobile phone applications, excessive 217 Hz GSM noise on
the analog supply pins can degrade the audio quality. To avoid
this problem, it is recommended that an L-C filter be used in
series with the bypass capacitors for the AVDD pins. This filter
should consist of a 1.2 nH inductor and a 9.1 pF capacitor in
series between AVDD and ground, as shown in Figure 63.
10µF
+
0.1µF
0.1µF
1.2nH 9.1pF
Figure 65. Exposed Pad Layout Example, Top View
AVDD
AVDD
Figure 63. GSM Filter on the Analog Supply Pins
Rev. A | Page 42 of 76
Data Sheet
ADAU1961
CONTROL REGISTERS
Table 25. Register Map
Reg Address Name
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
R0
R1
0x4000
0x4002
Clock control
PLL control
CLKSRC
INFREQ[1:0]
COREN
00000000
00000000
11111101
00000000
00001100
00010000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00010000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000010
00000010
00000010
00000010
M[15:8]
M[7:0]
N[15:8]
N[7:0]
Reserved
R[3:0]
X[1:0]
Lock
Type
Reserved
PLLEN
JDPOL
R2
0x4008
0x4009
0x400A
0x400B
0x400C
0x400D
0x400E
0x400F
0x4010
0x4011
0x4012
0x4013
0x4014
0x4015
0x4016
0x4017
0x4018
0x4019
0x401A
0x401B
0x401C
0x401D
0x401E
0x401F
0x4020
0x4021
0x4022
0x4023
0x4024
0x4025
0x4026
0x4027
0x4028
0x4029
0x402A
0x402B
0x402C
0x402D
0x402F
0x4030
0x4031
0x4036
Dig mic/jack detect
Reserved
JDDB[1:0]
JDFUNC[1:0]
Reserved
LINNG[2:0]
RINNG[2:0]
R3
Reserved
R4
Rec Mixer Left 0
Rec Mixer Left 1
Rec Mixer Right 0
Rec Mixer Right 1
Left diff input vol
Right diff input vol
Record mic bias
ALC 0
Reserved
Reserved
LINPG[2:0]
RINPG[2:0]
MX1EN
MX2EN
R5
Reserved
Reserved
LDBOOST[1:0]
RDBOOST[1:0]
MX1AUXG[2:0]
R6
R7
MX2AUXG[2:0]
LDMUTE
R8
LDVOL[5:0]
RDVOL[5:0]
LDEN
RDEN
MBIEN
R9
RDMUTE
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
R37
R38
R39
R40
R41
R42
R67
Reserved
MPERF
MBI
Reserved
PGASLEW[1:0]
ALCMAX[2:0]
ALCSEL[2:0]
ALC 1
ALCHOLD[3:0]
ALCATCK[3:0]
NGTYP[1:0] NGEN
ALCTARG[3:0]
ALCDEC[3:0]
NGTHR[4:0]
ALC 2
ALC 3
Serial Port 0
DITHEN
Reserved LRMOD
BPF[2:0]
BPOL
LRPOL
CHPF[1:0]
MS
Serial Port 1
ADTDM
DAOSR
DATDM
ADOSR
MSBP
INSEL
LRDEL[1:0]
CONVSR[2:0]
Converter 0
Reserved
Reserved
DAPAIR[1:0]
Converter 1
Reserved
DMPOL
ADPAIR[1:0]
ADCEN[1:0]
ADC control
ADCPOL
HPF
DMSW
Left digital vol
Right digital vol
Play Mixer Left 0
Play Mixer Left 1
Play Mixer Right 0
Play Mixer Right 1
Play L/R mixer left
Play L/R mixer right
Play L/R mixer mono
Play HP left vol
Play HP right vol
Line output left vol
Line output right vol
Play mono output
Pop/click suppress
Play power mgmt
DAC Control 0
DAC Control 1
DAC Control 2
Serial port pad
Control Port Pad 0
Control Port Pad 1
Jack detect pin
Dejitter control
LADVOL[7:0]
RADVOL[7:0]
Reserved
Reserved
MX3RM
MX3LM
MX4LM
MX3AUXG[3:0]
MX3EN
MX3G2[3:0]
MX3G1[3:0]
MX4RM
MX4AUXG[3:0]
MX4EN
MX4G2[3:0]
MX4G1[3:0]
MX5G3[1:0]
MX6G3[1:0]
MX7[1:0]
LHPM
Reserved
Reserved
MX5G4[1:0]
MX6G4[1:0]
MX5EN
MX6EN
MX7EN
HPEN
Reserved
LHPVOL[5:0]
RHPVOL[5:0]
LOUTVOL[5:0]
ROUTVOL[5:0]
MONOVOL[5:0]
RHPM
HPMODE
LOMODE
ROMODE
LOUTM
ROUTM
MONOM
ASLEW[1:0]
PREN
MOMODE 00000010
Reserved
POPMODE POPLESS
Reserved
DACPOL
Reserved
PLEN
00000000
00000000
00000000
00000000
00000000
10101010
10101010
00000000
00001000
00000011
DACMONO[1:0]
Reserved
DEMPH
DACEN[1:0]
LDAVOL[7:0]
RDAVOL[7:0]
ADCSDP[1:0]
CDATP[1:0]
DACSDP[1:0]
CLCHP[1:0]
Reserved
Reserved
DEJIT[7:0]
LRCLKP[1:0]
BCLKP[1:0]
SDAP[1:0]
SCLP[1:0]
SDASTR
Reserved
Reserved
JDSTR
JDP[1:0]
Rev. A | Page 43 of 76
ADAU1961
Data Sheet
CONTROL REGISTER DETAILS
All registers except for the PLL control register are 1-byte write and read registers.
R0: Clock Control, 16,384 (0x4000)
Bit 7
Bit 6
Bit 5
Reserved
Table 26. Clock Control Register
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLKSRC
INFREQ[1:0]
COREN
Bits
Bit Name
Description
3
CLKSRC
Clock source select.
0 = direct from MCLK pin (default).
1 = PLL clock.
[2:1]
INFREQ[1:0]
Input clock frequency. Sets the core clock rate that generates the core clock. If the PLL is used, this value is
automatically set to 1024 × fS.
Setting
00
01
Input Clock Frequency
256 × fS (default)
512 × fS
10
768 × fS
11
1024 × fS
0
COREN
Core clock enable. Only the R0 and R1 registers can be accessed when this bit is set to 0 (core clock disabled).
0 = core clock disabled (default).
1 = core clock enabled.
R1: PLL Control, 16,386 (0x4002)
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
M[15:8]
Bit 2
Bit 1
Bit 0
0
1
2
3
4
5
M[7:0]
N[15:8]
N[7:0]
Reserved
R[3:0]
Reserved
X[1:0]
Lock
Type
PLLEN
Table 27. PLL Control Register
Byte
Bits
[7:0]
[7:0]
Bit Name
M[15:8]
M[7:0]
Description
0
1
PLL denominator MSB. This value is concatenated with M[7:0] to make up a 16-bit number.
PLL denominator LSB. This value is concatenated with M[15:8] to make up a 16-bit number.
M[15:8] (MSB)
00000000
…
M[7:0] (LSB)
00000000
…
Value of M
0
…
00000000
…
11111101
…
253 (default)
…
11111111
11111111
65,535
2
3
[7:0]
[7:0]
N[15:8]
N[7:0]
PLL numerator MSB. This value is concatenated with N[7:0] to make up a 16-bit number.
PLL numerator LSB. This value is concatenated with N[15:8] to make up a 16-bit number.
N[15:8] (MSB)
00000000
…
N[7:0] (LSB)
00000000
…
Value of N
0
…
00000000
…
00001100
…
12 (default)
…
11111111
11111111
65,535
Rev. A | Page 44 of 76
Data Sheet
ADAU1961
Byte
Bits
Bit Name
Description
4
[6:3]
R[3:0]
PLL integer setting.
Setting
Value of R
0010
2 (default)
0011
0100
0101
0110
0111
1000
3
4
5
6
7
8
4
[2:1]
X[1:0]
PLL input clock divider.
Setting
00
Value of X
1 (default)
01
10
11
2
3
4
4
5
5
0
1
0
Type
Lock
Type of PLL. When set to integer mode, the values of M and N are ignored.
0 = integer (default).
1 = fractional.
PLL lock. This read-only bit is flagged when the PLL has finished locking.
0 = PLL unlocked (default).
1 = PLL locked.
PLLEN
PLL enable.
0 = PLL disabled (default).
1 = PLL enabled.
Rev. A | Page 45 of 76
ADAU1961
Data Sheet
R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008)
Bit 7
Bit 6
JDDB[1:0]
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
Bit 1
Bit 0
JDFUNC[1:0]
JDPOL
Table 28. Digital Microphone/Jack Detection Control Register
Bits
Bit Name
Description
[7:6]
JDDB[1:0]
Jack detect debounce time.
Setting
00
01
Debounce Time
5 ms (default)
10 ms
10
20 ms
11
40 ms
[5:4]
JDFUNC[1:0]
JACKDET/MICIN pin function. Enables or disables the jack detect function or configures the pin for a digital
microphone input.
Setting
00
01
Pin Function
Jack detect off (default)
Jack detect on
10
11
Digital microphone input
Reserved
0
JDPOL
Jack detect polarity. Detects high or low signal.
0 = detect high signal (default).
1 = detect low signal.
R4: Record Mixer Left (Mixer 1) Control 0, 16,394 (0x400A)
This register controls the gain of single-ended inputs for the left channel record path. The left channel record mixer is referred to as Mixer 1.
Bit 7
Bit 6
Bit 5
LINPG[2:0]
Bit 4
Bit 3
Bit 2
LINNG[2:0]
Bit 1
Bit 0
Reserved
MX1EN
Table 29. Record Mixer Left (Mixer 1) Control 0 Register
Bits
Bit Name
Description
[6:4]
LINPG[2:0]
Gain for a left channel single-ended input from the LINP pin, input to Mixer 1.
Setting
000
001
010
011
Gain
Mute (default)
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
100
101
110
3 dB
111
6 dB
[3:1]
LINNG[2:0]
Gain for a left channel single-ended input from the LINN pin, input to Mixer 1.
Setting
000
001
010
011
Gain
Mute (default)
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
100
101
110
3 dB
111
6 dB
0
MX1EN
Left channel mixer enable in the record path. Referred to as Mixer 1.
0 = mixer disabled (default).
1 = mixer enabled.
Rev. A | Page 46 of 76
Data Sheet
ADAU1961
R5: Record Mixer Left (Mixer 1) Control 1, 16,395 (0x400B)
This register controls the gain boost of the left channel differential PGA input and the gain for the left channel auxiliary input in the
record path. The left channel record mixer is referred to as Mixer 1.
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LDBOOST[1:0]
MX1AUXG[2:0]
Table 30. Record Mixer Left (Mixer 1) Control 1 Register
Bits
Bit Name
Description
[4:3]
LDBOOST[1:0]
Left channel differential PGA input gain boost, input to Mixer 1. The left differential input uses the LINP (positive
signal) and LINN (negative signal) pins.
Setting
00
01
Gain Boost
Mute (default)
0 dB
10
20 dB
11
Reserved
[2:0]
MX1AUXG[2:0]
Left single-ended auxiliary input gain from the LAUX pin in the record path, input to Mixer 1.
Setting
000
001
Auxiliary Input Gain
Mute (default)
−12 dB
−9 dB
010
011
−6 dB
100
−3 dB
101
0 dB
110
3 dB
111
6 dB
Rev. A | Page 47 of 76
ADAU1961
Data Sheet
R6: Record Mixer Right (Mixer 2) Control 0, 16,396 (0x400C)
This register controls the gain of single-ended inputs for the right channel record path. The right channel record mixer is referred to as
Mixer 2.
Bit 7
Bit 6
Bit 5
RINPG[2:0]
Bit 4
Bit 3
Bit 2
RINNG[2:0]
Bit 1
Bit 0
Reserved
MX2EN
Table 31. Record Mixer Right (Mixer 2) Control 0 Register
Bits
Bit Name
Description
[6:4]
RINPG[2:0]
Gain for a right channel single-ended input from the RINP pin, input to Mixer 2.
Setting
000
001
010
011
Gain
Mute (default)
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
100
101
110
3 dB
111
6 dB
[3:1]
RINNG[2:0]
Gain for a right channel single-ended input from the RINN pin, input to Mixer 2.
Setting
000
001
010
011
Gain
Mute (default)
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
100
101
110
3 dB
111
6 dB
0
MX2EN
Right channel mixer enable in the record path. Referred to as Mixer 2.
0 = mixer disabled (default).
1 = mixer enabled.
Rev. A | Page 48 of 76
Data Sheet
ADAU1961
R7: Record Mixer Right (Mixer 2) Control 1, 16,397 (0x400D)
This register controls the gain boost of the right channel differential PGA input and the gain for the right channel auxiliary input in the
record path. The right channel record mixer is referred to as Mixer 2.
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDBOOST[1:0]
MX2AUXG[2:0]
Table 32. Record Mixer Right (Mixer 2) Control 1 Register
Bits
Bit Name
Description
[4:3]
RDBOOST[1:0]
Right channel differential PGA input gain boost, input to Mixer 2. The right differential input uses the RINP
(positive signal) and RINN (negative signal) pins.
Setting
00
01
Gain Boost
Mute (default)
0 dB
10
20 dB
11
Reserved
[2:0]
MX2AUXG[2:0]
Right single-ended auxiliary input gain from the RAUX pin in the record path, input to Mixer 2.
Setting
000
001
Auxiliary Input Gain
Mute (default)
−12 dB
−9 dB
010
011
−6 dB
100
−3 dB
101
0 dB
110
3 dB
111
6 dB
R8: Left Differential Input Volume Control, 16,398 (0x400E)
This register enables the differential path and sets the volume control for the left differential PGA input.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LDMUTE
LDEN
LDVOL[5:0]
Table 33. Left Differential Input Volume Control Register
Bits
Bit Name
Description
[7:2]
LDVOL[5:0]
Left channel differential PGA input volume control. The left differential input uses the LINP (positive signal) and
LINN (negative signal) pins. Each step corresponds to a 0.75 dB increase in gain. See Table 69 for a complete list
of the volume settings.
Setting
000000
000001
…
Volume
−12 dB (default)
−11.25 dB
…
010000
…
0 dB
…
111110
111111
34.5 dB
35.25 dB
1
0
LDMUTE
LDEN
Left differential input mute control.
0 = mute (default).
1 = unmute.
Left differential PGA enable. When enabled, the LINP and LINN pins are used as a full differential pair. When
disabled, these two pins are configured as two single-ended inputs with the signals routed around the PGA.
0 = disabled (default).
1 = enabled.
Rev. A | Page 49 of 76
ADAU1961
Data Sheet
R9: Right Differential Input Volume Control, 16,399 (0x400F)
This register enables the differential path and sets the volume control for the right differential PGA input.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDMUTE
RDEN
RDVOL[5:0]
Table 34. Right Differential Input Volume Control Register
Bits
Bit Name
Description
[7:2]
RDVOL[5:0]
Right channel differential PGA input volume control. The right differential input uses the RINP (positive signal)
and RINN (negative signal) pins. Each step corresponds to a 0.75 dB increase in gain. See Table 69 for a complete
list of the volume settings.
Setting
000000
000001
…
Volume
−12 dB (default)
−11.25 dB
…
010000
…
0 dB
…
111110
111111
34.5 dB
35.25 dB
1
0
RDMUTE
RDEN
Right differential input mute control.
0 = mute (default).
1 = unmute.
Right differential PGA enable. When enabled, the RINP and RINN pins are used as a full differential pair. When
disabled, these two pins are configured as two single-ended inputs with the signals routed around the PGA.
0 = disabled (default).
1 = enabled.
R10: Record Microphone Bias Control, 16,400 (0x4010)
This register controls the MICBIAS pin settings for biasing electret type analog microphones.
Bit 7
Bit 6
Bit 5
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MPERF
MBI
Reserved
MBIEN
Table 35. Record Microphone Bias Control Register
Bits
Bit Name
Description
3
MPERF
Microphone bias is enabled for high performance or normal operation. High performance operation sources
more current to the microphone.
0 = normal operation (default).
1 = high performance.
2
0
MBI
Microphone voltage bias as a fraction of AVDD.
0 = 0.90 × AVDD (default).
1 = 0.65 × AVDD.
MBIEN
Enables the MICBIAS output.
0 = disabled (default).
1 = enabled.
Rev. A | Page 50 of 76
Data Sheet
ADAU1961
R11: ALC Control 0, 16,401 (0x4011)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
ALCSEL[2:0]
Bit 0
PGASLEW[1:0]
ALCMAX[2:0]
Table 36. ALC Control 0 Register
Bits
Bit Name
Description
[7:6]
PGASLEW[1:0]
PGA volume slew time when the ALC is off. The slew time is the period of time that a volume increase or decrease
takes to ramp up or ramp down to the target volume set in Register R8 (left differential input volume control)
and Register R9 (right differential input volume control).
Setting
00
01
Slew Time
24 ms (default)
48 ms
10
96 ms
11
Off
[5:3]
ALCMAX[2:0]
The maximum ALC gain sets a limit to the amount of gain that the ALC can provide to the input signal. This
protects small signals from excessive amplification.
Setting
000
001
Maximum ALC Gain
−12 dB (default)
−6 dB
010
0 dB
011
6 dB
100
12 dB
101
18 dB
110
24 dB
111
30 dB
[2:0]
ALCSEL[2:0]
ALC select. These bits set the channels that are controlled by the ALC. When set to right only, the ALC responds
only to the right channel input and controls the gain of the right PGA amplifier only. When set to left only, the
ALC responds only to the left channel input and controls the gain of the left PGA amplifier only. When set to
stereo, the ALC responds to the greater of the left or right channel and controls the gain of both the left and
right PGA amplifiers. These bits must be off if manual control of the volume is desired.
Setting
000
001
010
011
Channels
Off (default)
Right only
Left only
Stereo
100
101
110
111
Reserved
Reserved
Reserved
Reserved
Rev. A | Page 51 of 76
ADAU1961
Data Sheet
R12: ALC Control 1, 16,402 (0x4012)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ALCHOLD[3:0]
ALCTARG[3:0]
Table 37. ALC Control 1 Register
Bits
Bit Name
Description
[7:4]
ALCHOLD[3:0]
ALC hold time. The ALC hold time is the amount of time that the ALC waits after a decrease in input level before
increasing the gain to achieve the target level. The recommended minimum setting is 21 ms (0011) to prevent
distortion of low frequency signals. The hold time doubles with every 1-bit increase.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hold Time
2.67 ms (default)
5.34 ms
10.68 ms
21.36 ms
42.72 ms
85.44 ms
170.88 ms
341.76 ms
683.52 ms
1.367 sec
2.7341 sec
5.4682 sec
10.936 sec
21.873 sec
43.745 sec
87.491 sec
[3:0]
ALCTARG[3:0]
ALC target. The ALC target sets the desired ADC input level. The PGA gain is adjusted by the ALC to reach this
target level. The recommended target level is between −16 dB and −10 dB to accommodate transients without
clipping the ADC.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ALC Target
−28.5 dB (default)
−27 dB
−25.5 dB
−24 dB
−22.5 dB
−21 dB
−19.5 dB
−18 dB
−16.5 dB
−15 dB
−13.5 dB
−12 dB
−10.5 dB
−9 dB
−7.5 dB
−6 dB
Rev. A | Page 52 of 76
Data Sheet
ADAU1961
R13: ALC Control 2, 16,403 (0x4013)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ALCATCK[3:0]
ALCDEC[3:0]
Table 38. ALC Control 2 Register
Bits
Bit Name
Description
[7:4]
ALCATCK[3:0]
ALC attack time. The attack time sets how fast the ALC starts attenuating after an increase in input level above
the target. A typical setting for music recording is 384 ms, and a typical setting for voice recording is 24 ms.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Attack Time
6 ms (default)
12 ms
24 ms
48 ms
96 ms
192 ms
384 ms
768 ms
1.54 sec
3.07 sec
6.14 sec
12.29 sec
24.58 sec
49.15 sec
98.30 sec
196.61 sec
[3:0]
ALCDEC[3:0]
ALC decay time. The decay time sets how fast the ALC increases the PGA gain after a decrease in input level
below the target. A typical setting for music recording is 24.58 seconds, and a typical setting for voice recording
is 1.54 seconds.
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Decay Time
24 ms
48 ms
96 ms
192 ms
384 ms
768 ms
1.54 sec
3.07 sec
6.14 sec
12.29 sec
24.58 sec
49.15 sec
98.30 sec
196.61 sec
393.22 sec
786.43 sec
Rev. A | Page 53 of 76
ADAU1961
Data Sheet
R14: ALC Control 3, 16,404 (0x4014)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
NGTHR[4:0]
Bit 1
Bit 0
NGEN
NGTYP[1:0]
Table 39. ALC Control 3 Register
Bits
Bit Name
Description
[7:6]
NGTYP[1:0]
Noise gate type. When the input signal falls below the threshold for 250 ms, the noise gate can hold a constant
PGA gain, mute the ADC output, fade the PGA gain to the minimum gain value, or fade then mute.
Setting
00
Noise Gate
Hold PGA constant (default)
01
10
11
Mute ADC output (digital mute)
Fade to PGA minimum value (analog fade)
Fade then mute (analog fade/digital mute)
5
NGEN
Noise gate enable.
0 = disabled (default).
1 = enabled.
[4:0]
NGTHR[4:0]
Noise gate threshold. When the input signal falls below the threshold for 250 ms, the noise gate is activated.
A 1 LSB increase corresponds to a −1.5 dB change. See Table 70 for a complete list of the threshold settings.
Setting
00000
00001
…
Threshold
−76.5 dB (default)
−75 dB
…
11110
11111
−31.5 dB
−30 dB
R15: Serial Port Control 0, 16,405 (0x4015)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CHPF[1:0]
Bit 0
DITHEN
Reserved
LRMOD
BPOL
LRPOL
MS
Table 40. Serial Port Control 0 Register
Bits
Bit Name
Description
7
DITHEN
Dither enable is applicable only for 16-bit data width modes.
0 = disabled (default).
1 = enabled.
5
4
LRMOD
BPOL
LRCLK mode sets the LRCLK for either a 50% duty cycle or a pulse. The pulse mode should be at least 1 BCLK wide.
0 = 50% duty cycle (default).
1 = pulse mode.
BCLK polarity sets the BCLK edge that triggers a change in audio data. This can be set for the falling or rising
edge of the BCLK.
0 = falling edge (default).
1 = rising edge.
3
LRPOL
LRCLK polarity sets the LRCLK edge that triggers the beginning of the left channel audio frame. This can be set
for the falling or rising edge of the LRCLK.
0 = falling edge (default).
1 = rising edge.
[2:1]
CHPF[1:0]
Channels per frame sets the number of channels per LRCLK frame.
Setting
00
01
Channels per LRCLK Frame
Stereo (default)
TDM 4
10
Reserved
11
Reserved
0
MS
Serial data port bus mode. Both LRCLK and BCLK are master of the serial port when set in master mode and are
serial port slave in slave mode.
0 = slave mode (default).
1 = master mode.
Rev. A | Page 54 of 76
Data Sheet
ADAU1961
R16: Serial Port Control 1, 16,406 (0x4016)
Bit 7
Bit 6
BPF[2:0]
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADTDM
DATDM
MSBP
LRDEL[1:0]
Table 41. Serial Port Control 1 Register
Bits
Bit Name
Description
[7:5]
BPF[2:0]
Number of bit clock cycles per LRCLK audio frame.
Setting
000
001
Bit Clock Cycles
64 (default)
32
010
48
011
128
100
256
101
110
111
Reserved
Reserved
Reserved
4
ADTDM
DATDM
MSBP
ADC serial audio data channel position in TDM mode.
0 = left first (default).
1 = right first.
3
DAC serial audio data channel position in TDM mode.
0 = left first (default).
1 = right first.
2
MSB position in the LRCLK frame.
0 = MSB first (default).
1 = LSB first.
[1:0]
LRDEL[1:0]
Data delay from LRCLK edge (in BCLK units).
Setting
00
Delay (Bit Clock Cycles)
1 (default)
01
0
10
8
11
16
Rev. A | Page 55 of 76
ADAU1961
Data Sheet
R17: Converter Control 0, 16,407 (0x4017)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
DAOSR
ADOSR
DAPAIR[1:0]
CONVSR[2:0]
Table 42. Converter Control 0 Register
Bits
Bit Name
Description
[6:5]
DAPAIR[1:0]
On-chip DAC serial data selection in TDM mode.
Setting
00
01
Pair
First pair (default)
Second pair
Third pair
10
11
Fourth pair
4
DAOSR
DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
3
ADOSR
ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.
0 = 128× (default).
1 = 64×.
[2:0]
CONVSR[2:0]
Converter sampling rate. The ADCs and DACs operate at the sampling rate set in this register. The converter rate
selected is a ratio of the base sampling rate, fS. The base sampling rate is determined by the operating frequency
of the core clock. The serial port mirrors the converter sampling rates set in this register.
Setting
000
001
Sampling Rate
Base Sampling Rate (fS = 48 kHz)
fS
fS/6
48 kHz, base (default)
8 kHz
010
fS/4
12 kHz
011
fS/3
16 kHz
100
fS/2
24 kHz
101
110
111
fS/1.5
fS/0.5
Reserved
32 kHz
96 kHz
R18: Converter Control 1, 16,408 (0x4018)
Bit 7 Bit 6 Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
ADPAIR[1:0]
Table 43. Converter Control 1 Register
Bits
Bit Name
Description
[1:0]
ADPAIR[1:0]
On-chip ADC serial data selection in TDM mode.
Setting
00
01
Pair
First pair (default)
Second pair
Third pair
10
11
Fourth pair
Rev. A | Page 56 of 76
Data Sheet
ADAU1961
R19: ADC Control, 16,409 (0x4019)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
ADCPOL
HPF
DMPOL
DMSW
INSEL
ADCEN[1:0]
Table 44. ADC Control Register
Bits
Bit Name
Description
6
ADCPOL
Invert input polarity.
0 = normal (default).
1 = inverted.
5
4
3
HPF
ADC high-pass filter select. At 48 kHz, f3dB = 2 Hz.
0 = off (default).
1 = on.
DMPOL
DMSW
Digital microphone data polarity swap.
0 = invert polarity.
1 = normal (default).
Digital microphone channel swap. Normal operation sends the left channel on the rising edge of the clock and
the right channel on the falling edge of the clock.
0 = normal (default).
1 = swap left and right channels.
2
INSEL
Digital microphone input select. When asserted, the on-chip ADCs are off, BCLK is master at 128 × fS, and
ADC_SDATA is expected to have left and right channels interleaved.
0 = digital microphone inputs off, ADCs enabled (default).
1 = digital microphone inputs enabled, ADCs off.
[1:0]
ADCEN[1:0]
ADC enable.
Setting
00
01
ADCs Enabled
Both off (default)
Left on
10
Right on
11
Both on
R20: Left Input Digital Volume, 16,410 (0x401A)
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LADVOL[7:0]
Table 45. Left Input Digital Volume Register
Bits
Bit Name
Description
[7:0]
LADVOL[7:0]
Controls the digital volume attenuation for left channel inputs from either the left ADC or the left digital micro-
phone input. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 71 for a complete
list of the volume settings.
Setting
00000000
00000001
00000010
…
Volume Attenuation
0 dB (default)
−0.375 dB
−0.75 dB
…
11111110
11111111
−95.25 dB
−95.625 dB
Rev. A | Page 57 of 76
ADAU1961
Data Sheet
R21: Right Input Digital Volume, 16,411 (0x401B)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RADVOL[7:0]
Table 46. Right Input Digital Volume Register
Bits
Bit Name
Description
[7:0]
RADVOL[7:0]
Controls the digital volume attenuation for right channel inputs from either the right ADC or the right digital
microphone input. Each bit corresponds to a 0.375 dB step with slewing between settings. See Table 71 for a
complete list of the volume settings.
Setting
00000000
00000001
00000010
…
Volume Attenuation
0 dB (default)
−0.375 dB
−0.75 dB
…
11111110
11111111
−95.25 dB
−95.625 dB
R22: Playback Mixer Left (Mixer 3) Control 0, 16,412 (0x401C)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
MX3RM
MX3LM
MX3EN
MX3AUXG[3:0]
Table 47. Playback Mixer Left (Mixer 3) Control 0 Register
Bits
Bit Name
Description
6
MX3RM
Mixer input mute. Mutes the right DAC input to the left channel playback mixer (Mixer 3).
0 = muted (default).
1 = unmuted.
5
MX3LM
Mixer input mute. Mutes the left DAC input to the left channel playback mixer (Mixer 3).
0 = muted (default).
1 = unmuted.
[4:1]
MX3AUXG[3:0]
Mixer input gain. Controls the left channel auxiliary input gain to the left channel playback mixer (Mixer 3).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
0
MX3EN
Mixer 3 enable.
0 = disabled (default).
1 = enabled.
Rev. A | Page 58 of 76
Data Sheet
ADAU1961
R23: Playback Mixer Left (Mixer 3) Control 1, 16,413 (0x401D)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MX3G2[3:0]
MX3G1[3:0]
Table 48. Playback Mixer Left (Mixer 3) Control 1 Register
Bits
Bit Name
Description
[7:4]
MX3G2[3:0]
Bypass gain control. The signal from the right channel record mixer (Mixer 2) bypasses the converters and gain
can be applied before the left playback mixer (Mixer 3).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
[3:0]
MX3G1[3:0]
Bypass gain control. The signal from the left channel record mixer (Mixer 1) bypasses the converters and gain
can be applied before the left playback mixer (Mixer 3).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
Rev. A | Page 59 of 76
ADAU1961
Data Sheet
R24: Playback Mixer Right (Mixer 4) Control 0, 16,414 (0x401E)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
MX4RM
MX4LM
MX4EN
MX4AUXG[3:0]
Table 49. Playback Mixer Right (Mixer 4) Control 0 Register
Bits
Bit Name
Description
6
MX4RM
Mixer input mute. Mutes the right DAC input to the right channel playback mixer (Mixer 4).
0 = muted (default).
1 = unmuted.
5
MX4LM
Mixer input mute. Mutes the left DAC input to the right channel playback mixer (Mixer 4).
0 = muted (default).
1 = unmuted.
[4:1]
MX4AUXG[3:0]
Mixer input gain. Controls the right channel auxiliary input gain to the right channel playback mixer (Mixer 4).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
0
MX4EN
Mixer 4 enable.
0 = disabled (default).
1 = enabled.
Rev. A | Page 60 of 76
Data Sheet
ADAU1961
R25: Playback Mixer Right (Mixer 4) Control 1, 16,415 (0x401F)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MX4G2[3:0]
MX4G1[3:0]
Table 50. Playback Mixer Right (Mixer 4) Control 1 Register
Bits
Bit Name
Description
[7:4]
MX4G2[3:0]
Bypass gain control. The signal from the right channel record mixer (Mixer 2) bypasses the converters and gain
can be applied before the right playback mixer (Mixer 4).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
[3:0]
MX4G1[3:0]
Bypass gain control. The signal from the left channel record mixer (Mixer 1) bypasses the converters and gain
can be applied before the right playback mixer (Mixer 4).
Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
Gain
Mute (default)
−15 dB
−12 dB
−9 dB
−6 dB
−3 dB
0 dB
3 dB
6 dB
R26: Playback L/R Mixer Left (Mixer 5) Line Output Control, 16,416 (0x4020)
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MX5EN
MX5G4[1:0]
MX5G3[1:0]
Table 51. Playback L/R Mixer Left (Mixer 5) Line Output Control Register
Bits
Bit Name
Description
[4:3]
MX5G4[1:0]
Mixer input gain boost. The signal from the right channel playback mixer (Mixer 4) can be enabled and boosted
in the playback L/R mixer left (Mixer 5).
Setting
00
Gain Boost
Mute (default)
01
10
11
0 dB output (−6 dB gain on each of the two inputs)
6 dB output (0 dB gain on each of the two inputs)
Reserved
[2:1]
MX5G3[1:0]
Mixer input gain boost. The signal from the left channel playback mixer (Mixer 3) can be enabled and boosted in
the playback L/R mixer left (Mixer 5).
Setting
00
Gain Boost
Mute (default)
01
10
11
0 dB output (−6 dB gain on each of the two inputs)
6 dB output (0 dB gain on each of the two inputs)
Reserved
0
MX5EN
Mixer 5 enable.
0 = disabled (default).
1 = enabled.
Rev. A | Page 61 of 76
ADAU1961
Data Sheet
R27: Playback L/R Mixer Right (Mixer 6) Line Output Control, 16,417 (0x4021)
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MX6EN
MX6G4[1:0]
MX6G3[1:0]
Table 52. Playback L/R Mixer Right (Mixer 6) Line Output Control Register
Bits
Bit Name
Description
[4:3]
MX6G4[1:0]
Mixer input gain boost. The signal from the right channel playback mixer (Mixer 4) can be enabled and boosted
in the playback L/R mixer right (Mixer 6).
Setting
00
Gain Boost
Mute (default)
01
10
11
0 dB output (−6 dB gain on each of the two inputs)
6 dB output (0 dB gain on each of the two inputs)
Reserved
[2:1]
MX6G3[1:0]
Mixer input gain boost. The signal from the left channel playback mixer (Mixer 3) can be enabled and boosted in
the playback L/R mixer right (Mixer 6).
Setting
00
Gain Boost
Mute (default)
01
10
11
0 dB output (−6 dB gain on each of the two inputs)
6 dB output (0 dB gain on each of the two inputs)
Reserved
0
MX6EN
Mixer 6 enable.
0 = disabled (default).
1 = enabled.
R28: Playback L/R Mixer Mono Output (Mixer 7) Control, 16,418 (0x4022)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Reserved
Bit 2
Bit 1
MX7[1:0]
Bit 0
MX7EN
Table 53. Playback L/R Mixer Mono Output (Mixer 7) Control Register
Bits
Bit Name
Description
[2:1]
MX7[1:0]
L/R mono playback mixer (Mixer 7). Mixes the left and right playback mixers (Mixer 3 and Mixer 4) with either a
0 dB or 6 dB gain boost. Additionally, this mixer can operate as a common-mode output, which is used as the
virtual ground in a capless headphone configuration.
Setting
00
01
10
11
Gain Boost
Common-mode output (default)
0 dB output (−6 dB gain on each of the two inputs)
6 dB output (0 dB gain on each of the two inputs)
Reserved
0
MX7EN
Mixer 7 enable.
0 = disabled (default).
1 = enabled.
Rev. A | Page 62 of 76
Data Sheet
ADAU1961
R29: Playback Headphone Left Volume Control, 16,419 (0x4023)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LHPVOL[5:0]
LHPM
HPEN
Table 54. Playback Headphone Left Volume Control Register
Bits
Bit Name
Description
[7:2]
LHPVOL[5:0]
Headphone volume control for left channel, LHP output. Each 1-bit step corresponds to a 1 dB increase in volume.
See Table 72 for a complete list of the volume settings.
Setting
000000
…
Volume
−57 dB (default)
…
111001
…
0 dB
…
111111
6 dB
1
0
LHPM
HPEN
Headphone mute for left channel, LHP output (active low).
0 = mute.
1 = unmute (default).
Headphone volume control enable. Logical OR with the HPMODE bit in Register R30. If either the HPEN bit or
the HPMODE bit is set to 1, the headphone output is enabled.
0 = disabled (default).
1 = enabled.
R30: Playback Headphone Right Volume Control, 16,420 (0x4024)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HPMODE
RHPVOL[5:0]
RHPM
Table 55. Playback Headphone Right Volume Control Register
Bits
Bit Name
Description
[7:2]
RHPVOL[5:0]
Headphone volume control for right channel, RHP output. Each 1-bit step corresponds to a 1 dB increase in
volume. See Table 72 for a complete list of the volume settings.
Setting
000000
…
Volume
−57 dB (default)
…
111001
…
0 dB
…
111111
6 dB
1
0
RHPM
Headphone mute for right channel, RHP output (active low).
0 = mute.
1 = unmute (default).
HPMODE
RHP and LHP output mode. These pins can be configured for either line outputs or headphone outputs. Logical
OR with the HPEN bit in Register R29. If either the HPMODE bit or the HPEN bit is set to 1, the headphone output
is enabled.
0 = enable line output (default).
1 = enable headphone output.
Rev. A | Page 63 of 76
ADAU1961
Data Sheet
R31: Playback Line Output Left Volume Control, 16,421 (0x4025)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LOUTM
LOMODE
LOUTVOL[5:0]
Table 56. Playback Line Output Left Volume Control Register
Bits
Bit Name
Description
[7:2]
LOUTVOL[5:0]
Line output volume control for left channel, LOUTN and LOUTP outputs. Each 1-bit step corresponds to a 1 dB
increase in volume. See Table 72 for a complete list of the volume settings.
Setting
000000
…
Volume
−57 dB (default)
…
111001
…
0 dB
…
111111
6 dB
1
0
LOUTM
Line output mute for left channel, LOUTN and LOUTP outputs (active low).
0 = mute.
1 = unmute (default).
LOMODE
Line output mode for left channel, LOUTN and LOUTP outputs. These pins can be configured for either line
outputs or headphone outputs. To drive earpiece speakers, set this bit to 1 (headphone output).
0 = line output (default).
1 = headphone output.
R32: Playback Line Output Right Volume Control, 16,422 (0x4026)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ROUTM
ROMODE
ROUTVOL[5:0]
Table 57. Playback Line Output Right Volume Control Register
Bits
Bit Name
Description
[7:2]
ROUTVOL[5:0]
Line output volume control for right channel, ROUTN and ROUTP outputs. Each 1-bit step corresponds to a 1 dB
increase in volume. See Table 72 for a complete list of the volume settings.
Setting
000000
…
Volume
−57 dB (default)
…
111001
…
0 dB
…
111111
6 dB
1
0
ROUTM
Line output mute for right channel, ROUTN and ROUTP outputs (active low).
0 = mute.
1 = unmute (default).
ROMODE
Line output mode for right channel, ROUTN and ROUTP outputs. These pins can be configured for either line
outputs or headphone outputs. To drive earpiece speakers, set this bit to 1 (headphone output).
0 = line output (default).
1 = headphone output.
Rev. A | Page 64 of 76
Data Sheet
ADAU1961
R33: Playback Mono Output Control, 16,423 (0x4027)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MONOM
MOMODE
MONOVOL[5:0]
Table 58. Playback Mono Output Control Register
Bits
Bit Name
Description
[7:2]
MONOVOL[5:0] Mono output volume control. Each 1-bit step corresponds to a 1 dB increase in volume. If MX7[1:0] in Register R28
is set for common-mode output, volume control is disabled. See Table 72 for a complete list of the volume settings.
Setting
000000
…
Volume
−57 dB (default)
…
111001
…
0 dB
…
111111
6 dB
1
0
MONOM
Mono output mute (active low).
0 = mute.
1 = unmute (default).
MOMODE
Headphone mode enable. If MX7[1:0] in Register R28 is set for common-mode output for a capless headphone
configuration, this bit should be set to 1 ( headphone output).
0 = line output (default).
1 = headphone output.
R34: Playback Pop/Click Suppression, 16,424 (0x4028)
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POPMODE
POPLESS
Reserved
ASLEW[1:0]
Table 59. Playback Pop/Click Suppression Register
Bits
Bit Name
Description
4
POPMODE
Pop suppression circuit power saving mode. The pop suppression circuits charge faster in normal operation;
however, after they are charged, they can be put into low power operation.
0 = normal (default).
1 = low power.
3
POPLESS
Pop suppression disable. The pop suppression circuits are enabled by default. They can be disabled to save
power; however, disabling the circuits increases the risk of pops and clicks.
0 = enabled (default).
1 = disabled.
[2:1]
ASLEW[1:0]
Analog volume slew rate for playback volume controls.
Setting
00
01
Slew Rate
21.25 ms (default)
42.5 ms
10
85 ms
11
Off
R35: Playback Power Management, 16,425 (0x4029)
Bit 7 Bit 6 Bit 5 Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
PREN
PLEN
Table 60. Playback Power Management Register
Bits
Bit Name
Description
1
PREN
Playback right channel enable.
0 = disabled (default).
1 = enabled.
0
PLEN
Playback left channel enable.
0 = disabled (default).
1 = enabled.
Rev. A | Page 65 of 76
ADAU1961
Data Sheet
R36: DAC Control 0, 16,426 (0x402A)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Reserved
Bit 2
Bit 1
Bit 0
DACPOL
DEMPH
DACMONO[1:0]
DACEN[1:0]
Table 61. DAC Control 0 Register
Bits
Bit Name
Description
[7:6]
DACMONO[1:0]
DAC mono mode. The DAC channels can be set to mono mode within the DAC and output on the left
channel, the right channel, or both channels.
Setting
00
Mono Mode
Stereo (default)
01
10
11
Left channel in mono mode
Right channel in mono mode
Both channels in mono mode
5
DACPOL
DEMPH
Invert input polarity of the DACs.
0 = normal (default).
1 = inverted.
2
DAC de-emphasis filter enable. The de-emphasis filter is designed for use with a sampling rate of 44.1 kHz only.
0 = disabled (default).
1 = enabled.
[1:0]
DACEN[1:0]
DAC enable.
Setting
00
01
DACs Enabled
Both off (default)
Left on
10
Right on
11
Both on
R37: DAC Control 1, 16,427 (0x402B)
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LDAVOL[7:0]
Table 62. DAC Control 1 Register
Bits
Bit Name
Description
[7:0]
LDAVOL[7:0]
Controls the digital volume attenuation for left channel inputs from the left DAC. Each bit corresponds to a
0.375 dB step with slewing between settings. See Table 71 for a complete list of the volume settings.
Setting
00000000
00000001
00000010
…
Volume Attenuation
0 dB (default)
−0.375 dB
−0.75 dB
…
11111110
11111111
−95.25 dB
−95.625 dB
Rev. A | Page 66 of 76
Data Sheet
ADAU1961
R38: DAC Control 2, 16,428 (0x402C)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDAVOL[7:0]
Table 63. DAC Control 2 Register
Bits
Bit Name
Description
[7:0]
RDAVOL[7:0]
Controls the digital volume attenuation for right channel inputs from the right DAC. Each bit corresponds to a
0.375 dB step with slewing between settings. See Table 71 for a complete list of the volume settings.
Setting
00000000
00000001
00000010
…
Volume Attenuation
0 dB (default)
−0.375 dB
−0.75 dB
…
11111110
11111111
−95.25 dB
−95.625 dB
R39: Serial Port Pad Control, 16,429 (0x402D)
The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the serial port
signals to a defined state when the signal source becomes three-state.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCSDP[1:0]
DACSDP[1:0]
LRCLKP[1:0]
BCLKP[1:0]
Table 64. Serial Port Pad Control Register
Bits
Bit Name
Description
[7:6]
ADCSDP[1:0]
ADC_SDATA pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
[5:4]
[3:2]
[1:0]
DACSDP[1:0]
LRCLKP[1:0]
BCLKP[1:0]
DAC_SDATA pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
LRCLK pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
BCLK pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
Rev. A | Page 67 of 76
ADAU1961
Data Sheet
R40: Control Port Pad Control 0, 16,431 (0x402F)
The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the control port
signals to a defined state when the signal source becomes three-state.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SCLP[1:0]
Bit 1
Bit 0
SDAP[1:0]
CDATP[1:0]
CLCHP[1:0]
Table 65. Control Port Pad Control 0 Register
Bits
Bit Name
Description
[7:6]
CDATP[1:0]
CDATA pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
[5:4]
[3:2]
[1:0]
CLCHP[1:0]
SCLP[1:0]
SDAP[1:0]
CLATCH pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
SCL/CCLK pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
SDA/COUT pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
R41: Control Port Pad Control 1, 16,432 (0x4030)
With IOVDD set to 3.3 V, the low and high drive strengths of the SDA/COUT pin are approximately 2.0 mA and 4.0 mA, respectively.
The high drive strength mode may be useful for generating a stronger ACK pulse in I2C mode, if needed.
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
SDASTR
Table 66. Control Port Pad Control 1 Register
Bits
Bit Name
Description
0
SDASTR
SDA/COUT pin drive strength.
0 = low (default).
1 = high.
Rev. A | Page 68 of 76
Data Sheet
ADAU1961
R42: Jack Detect Pin Control, 16,433 (0x4031)
With IOVDD set to 3.3 V, the low and high drive strengths of the JACKDET/MICIN pin are approximately 2.0 mA and 4.0 mA, respectively.
The optional pull-up/pull-down resistors are nominally 250 kΩ. When enabled, these pull-up/pull-down resistors set the input signals to
a defined state when the signal source becomes three-state.
Bit 7
Bit 6
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
JDP[1:0]
Bit 1
Bit 0
Reserved
JDSTR
Reserved
Table 67. Jack Detect Pin Control Register
Bits
Bit Name
Description
5
JDSTR
JACKDET/MICIN pin drive strength.
0 = low (default).
1 = high.
[3:2]
JDP[1:0]
JACKDET/MICIN pad pull-up/pull-down configuration.
Setting
00
Configuration
Pull-up
01
Reserved
10
11
None (default)
Pull-down
R67: Dejitter Control, 16,438 (0x4036)
The dejitter control register allows the size of the dejitter window to be set, and also allows all dejitter circuits in the device to be activated or
bypassed. Dejitter circuits protect against duplicate samples or skipped samples due to jitter from the serial ports in slave mode. Disabling
and reenabling certain subsystems in the device—that is, the ADCs, serial ports, and DACs—during operation can cause the associated
dejitter circuits to fail. As a result, audio data fails to be output to the next subsystem in the device.
When the serial ports are in master mode, the dejitter circuit can be bypassed by setting the dejitter window to 0. When the serial ports
are in slave mode, the dejitter circuit can be reinitialized prior to outputting audio from the device, guaranteeing that audio is output
to the next subsystem in the device. Any time that audio must pass through the ADCs, serial port, or DACs, the dejitter circuit can be
bypassed and reset by setting the dejitter window size to 0. In this way, the dejitter circuit can be immediately reactivated, without a wait
period, by setting the dejitter window size to the default value of 3.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
DEJIT[7:0]
Bit 2
Bit 1
Bit 0
Table 68. Dejitter Control Register
Bits
Bit Name
Description
Dejitter window size.
Window Size
00000000
…
[7:0]
DEJIT[7:0]
Core Clock Cycles
0
…
00000011
…
00000101
3 (default)
…
5
Rev. A | Page 69 of 76
ADAU1961
Data Sheet
Table 69. R8 and R9 Volume Settings
Binary Value
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
Volume Setting (dB)
Binary Value
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Volume Setting (dB)
−12
−11.25
−10.5
−9.75
−9
−8.25
−7.5
−6.75
−6
−5.25
−4.5
−3.75
−3
−2.25
−1.5
−0.75
0
0.75
1.5
2.25
3
3.75
4.5
5.25
6
6.75
7.5
8.25
9
9.75
10.5
11.25
12
12.75
13.5
14.25
15
15.75
16.5
17.25
18
18.75
19.5
20.25
21
21.75
22.5
23.25
24
24.75
25.5
26.25
27
27.75
28.5
29.25
30
30.75
31.5
32.25
33
33.75
34.5
35.25
Table 70. R14 Noise Gate Threshold
Noise Gate Threshold (dB)
Binary Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
−76.5
−75
−73.5
−72
−70.5
−69
−67.5
−66
−64.5
−63
−61.5
−60
−58.5
−57
−55.5
−54
−52.5
−51
−49.5
−48
−46.5
−45
−43.5
−42
−40.5
−39
−37.5
−36
−34.5
−33
−31.5
−30
Rev. A | Page 70 of 76
Data Sheet
ADAU1961
Table 71. R20, R21, R37, and R38 Volume Settings
Binary Value
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
00010000
00010001
00010010
00010011
00010100
00010101
00010110
00010111
00011000
00011001
00011010
00011011
00011100
00011101
00011110
00011111
00100000
00100001
00100010
00100011
00100100
00100101
00100110
00100111
00101000
00101001
00101010
00101011
00101100
00101101
00101110
00101111
Volume Attenuation (dB)
Binary Value
00110000
00110001
00110010
00110011
00110100
00110101
00110110
00110111
00111000
00111001
00111010
00111011
00111100
00111101
00111110
00111111
01000000
01000001
01000010
01000011
01000100
01000101
01000110
01000111
01001000
01001001
01001010
01001011
01001100
01001101
01001110
01001111
01010000
01010001
01010010
01010011
01010100
01010101
01010110
01010111
01011000
01011001
01011010
01011011
01011100
01011101
01011110
01011111
Volume Attenuation (dB)
0
−18
−0.375
−0.75
−18.375
−18.75
−19.125
−19.5
−1.125
−1.5
−1.875
−2.25
−19.875
−20.25
−20.625
−21
−2.625
−3
−3.375
−3.75
−21.375
−21.75
−22.125
−22.5
−4.125
−4.5
−4.875
−5.25
−22.875
−23.25
−23.625
−24
−5.625
−6
−6.375
−6.75
−24.375
−24.75
−25.125
−25.5
−7.125
−7.5
−7.875
−8.25
−25.875
−26.25
−26.625
−27
−8.625
−9
−9.375
−9.75
−27.375
−27.75
−28.125
−28.5
−10.125
−10.5
−10.875
−11.25
−11.625
−12
−28.875
−29.25
−29.625
−30
−12.375
−12.75
−13.125
−13.5
−30.375
−30.75
−31.125
−31.5
−13.875
−14.25
−14.625
−15
−31.875
−32.25
−32.625
−33
−15.375
−15.75
−16.125
−16.5
−33.375
−33.75
−34.125
−34.5
−16.875
−17.25
−17.625
−34.875
−35.25
−35.625
Rev. A | Page 71 of 76
ADAU1961
Data Sheet
Binary Value
01100000
01100001
01100010
01100011
01100100
01100101
01100110
01100111
01101000
01101001
01101010
01101011
01101100
01101101
01101110
01101111
01110000
01110001
01110010
01110011
01110100
01110101
01110110
01110111
01111000
01111001
01111010
01111011
01111100
01111101
01111110
01111111
10000000
10000001
10000010
10000011
10000100
10000101
10000110
10000111
10001000
10001001
10001010
10001011
10001100
10001101
10001110
10001111
10010000
Volume Attenuation (dB)
−36
Binary Value
10010001
10010010
10010011
10010100
10010101
10010110
10010111
10011000
10011001
10011010
10011011
10011100
10011101
10011110
10011111
10100000
10100001
10100010
10100011
10100100
10100101
10100110
10100111
10101000
10101001
10101010
10101011
10101100
10101101
10101110
10101111
10110000
10110001
10110010
10110011
10110100
10110101
10110110
10110111
10111000
10111001
10111010
10111011
10111100
10111101
10111110
10111111
11000000
11000001
Volume Attenuation (dB)
−54.375
−54.75
−55.125
−55.5
−36.375
−36.75
−37.125
−37.5
−55.875
−56.25
−56.625
−57
−37.875
−38.25
−38.625
−39
−57.375
−57.75
−58.125
−58.5
−39.375
−39.75
−40.125
−40.5
−58.875
−59.25
−59.625
−60
−40.875
−41.25
−41.625
−42
−60.375
−60.75
−61.125
−61.5
−42.375
−42.75
−43.125
−43.5
−61.875
−62.25
−62.625
−63
−43.875
−44.25
−44.625
−45
−63.375
−63.75
−64.125
−64.5
−45.375
−45.75
−46.125
−46.5
−64.875
−65.25
−65.625
−66
−46.875
−47.25
−47.625
−48
−66.375
−66.75
−67.125
−67.5
−48.375
−48.75
−49.125
−49.5
−67.875
−68.25
−68.625
−69
−49.875
−50.25
−50.625
−51
−69.375
−69.75
−70.125
−70.5
−51.375
−51.75
−52.125
−52.5
−70.875
−71.25
−71.625
−72
−52.875
−53.25
−53.625
−54
−72.375
Rev. A | Page 72 of 76
Data Sheet
ADAU1961
Binary Value
11000010
11000011
11000100
11000101
11000110
11000111
11001000
11001001
11001010
11001011
11001100
11001101
11001110
11001111
11010000
11010001
11010010
11010011
11010100
11010101
11010110
11010111
11011000
11011001
11011010
11011011
11011100
11011101
11011110
11011111
11100000
11100001
11100010
11100011
11100100
11100101
11100110
11100111
11101000
11101001
11101010
11101011
11101100
11101101
11101110
11101111
11110000
11110001
11110010
Volume Attenuation (dB)
−72.75
−73.125
−73.5
Binary Value
11110011
11110100
11110101
11110110
11110111
11111000
11111001
11111010
11111011
11111100
11111101
11111110
11111111
Volume Attenuation (dB)
−91.125
−91.5
−91.875
−92.25
−92.625
−93
−73.875
−74.25
−74.625
−75
−93.375
−93.75
−94.125
−94.5
−75.375
−75.75
−76.125
−76.5
−94.875
−95.25
−95.625
−76.875
−77.25
−77.625
−78
Table 72. R29 through R33 Volume Settings
−78.375
−78.75
−79.125
−79.5
Binary Value
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
Volume Setting (dB)
−57
−56
−55
−54
−53
−52
−51
−50
−49
−48
−47
−46
−45
−44
−43
−42
−41
−40
−39
−38
−37
−36
−35
−34
−33
−32
−31
−30
−29
−28
−27
−26
−25
−79.875
−80.25
−80.625
−81
−81.375
−81.75
−82.125
−82.5
−82.875
−83.25
−83.625
−84
−84.375
−84.75
−85.125
−85.5
−85.875
−86.25
−86.625
−87
−87.375
−87.75
−88.125
−88.5
−88.875
−89.25
−89.625
−90
−90.375
−90.75
Rev. A | Page 73 of 76
ADAU1961
Data Sheet
Binary Value
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Volume Setting (dB)
−24
−23
−22
−21
−20
−19
−18
−17
−16
−15
−14
−13
−12
−11
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
1
2
3
4
5
6
Rev. A | Page 74 of 76
Data Sheet
ADAU1961
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
32
1
25
24
0.50
BSC
PIN 1
INDICATOR
4.75
BSC SQ
3.65
3.50 SQ
3.35
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
COPLANARITY
0.08
0.30
0.25
0.18
SEATING
PLANE
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 66. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
ADAU1961WBCPZ
ADAU1961WBCPZ-R7 −40°C to +105°C
ADAU1961WBCPZ-RL −40°C to +105°C
Temperature Range Package Description
−40°C to +105°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7”Tape and Reel
Package Option
CP-32-4
CP-32-4
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 13”Tape and Reel CP-32-4
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADAU1961W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Rev. A | Page 75 of 76
ADAU1961
NOTES
Data Sheet
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D08915-0-4/13(A)
Rev. A | Page 76 of 76
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