ADAU1962_技术文档

12-Channel, High Performance,

Differential Output, 192 kHz, 24-Bit DAC

Data Sheet

ADAU1962

FEATURES

GENERAL DESCRIPTION

118 dB DAC dynamic range

−98 dB THD + N

Differential voltage DAC output

The ADAU1962 is a high performance, single chip, digital-

to-analog converter (DAC) that provides 12 DACs with

differential outputs using the Analog Devices, Inc., patented

multibit sigma-delta (Σ-Δ) architecture. A SPI/I²C port is included,

allowing a microcontroller to adjust volume and many other

parameters. The ADAU1962 operates from 2.5 V digital, 5 V

analog and 3.3 V or 5 V input/output supplies. A linear regulator is

included to generate the digital supply voltage from the analog

supply voltage.

2.5 V digital, 5 V analog, and 3.3 V or 5 V input/output

supplies

421 mW total quiescent power dissipation

PLL generated or direct master clock

Low EMI design

Linear regulator driver to generate digital supply

Supports 24-bit and 32 kHz to 192 kHz sample rates

Low propagation 192 kHz sample rate mode

Log volume control with autoramp function

Temperature sensor with digital readout: 3°C accuracy

SPI and I²C controllable for flexibility

Software-controllable clickless mute

Software power-down

The ADAU1962 is designed for low electromagnetic interference

(EMI), evident in both the system and circuit design architectures.

By using the on-board phase-locked loop (PLL) to derive the

internal master clock from an external left right frame clock

(LRCLK)/frame clock, the ADAU1962 eliminates the need for

a separate high frequency master clock and can be used with or

without a bit clock. The DACs are designed using the latest

Analog Devices continuous time architectures to further

minimize EMI. By using 2.5 V digital supplies, power consumption

is minimized and the digital waveforms are of a smaller amplitude,

further reducing emissions.

Right justified, left justified, I²S, and TDM modes

Master and slave modes with up to 12-channel input/output

80-lead LQFP package

Qualified for automotive applications

APPLICATIONS

The ADAU1962 is available in an 80-lead LQFP package. Note

that throughout this data sheet, multifunction pins, such as

SCLK/SCL/SA, are referred to by the entire pin name or by a

single function of the pin, for example, SCLK, when only that

function is relevant.

Automotive audio systems

Home theater systems

Digital audio effects processors

FUNCTIONAL BLOCK DIAGRAM

DIGITAL AUDIO

INPUT

ADAU1962

DAC

SERIAL DATA PORT

DAC

SDATA

IN

SDATA

IN

DAC

DIGITAL

FILTER

AND

VOLUME

CONTROL

DAC

FILTER

AND

CLOCKS

DIFFERENTIAL

ANALOG AUDIO

OUTPUTS

DIFFERENTIAL

ANALOG AUDIO

OUTPUTS

VOLUME

CONTROL

TIMING MANAGEMENT

AND CONTROL

(CLOCK AND PLL)

2

SPI/I C

CONTROL PORT

PRECISION

VOLTAGE

REFERENCE

INTERNAL

TEMP

SENSOR

CONTROL DATA

INPUT/OUTPUT

Figure 1.

Rev. A

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Technical Support

www.analog.com

ADAU1962

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

PLL and Clock Control 1 Register ........................................... 26

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Analog Performance Specifications........................................... 3

Crystal Oscillator Specifications................................................. 4

Digital Input/Output Specifications........................................... 5

Power Supply Specifications........................................................ 5

Digital Filters................................................................................. 6

Timing Specifications .................................................................. 6

Absolute Maximum Ratings ....................................................... 8

Thermal Resistance ...................................................................... 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 12

Test Circuits..................................................................................... 13

Theory of Operation ...................................................................... 14

Digital-to-Analog Converters (DACs) .................................... 14

Clock Signals............................................................................... 15

Power-Up and Reset................................................................... 16

Standalone Mode........................................................................ 16

I²C Control Port.......................................................................... 16

Serial Control Port: SPI Mode .................................................. 19

Power Supply and Voltage Reference....................................... 20

Serial Data Ports—Data Format............................................... 20

Time Division Multiplexed (TDM) Modes............................. 20

Temperature Sensor ................................................................... 22

Additional Modes....................................................................... 23

Register Summary .......................................................................... 24

Register Details ............................................................................... 25

PLL and Clock Control 0 Register ........................................... 25

Block Power-Down and Thermal Sensor Control 1 Register

....................................................................................................... 27

Power-Down Control 2 Register.............................................. 28

Power-Down Control 3 Register.............................................. 29

Thermal Sensor Temperature Readout Register.................... 29

DAC Control 0 Register ............................................................ 30

DAC Control 1 Register ............................................................ 31

DAC Control 2 Register ............................................................ 32

DAC Individual Channel Mutes 1 Register ............................ 33

DAC Individual Channel Mutes 2 Register ............................ 34

Master Volume Control Register.............................................. 35

DAC1 Volume Control Register............................................... 35

DAC2 Volume Control Register............................................... 36

DAC3 Volume Control Register............................................... 36

DAC4 Volume Control Register............................................... 37

DAC5 Volume Control Register............................................... 37

DAC6 Volume Control Register............................................... 38

DAC7 Volume Control Register............................................... 38

DAC8 Volume Control Register............................................... 39

DAC9 Volume Control Register............................................... 39

DAC10 Volume Control Register............................................. 40

DAC11 Volume Control Register............................................. 40

DAC12 Volume Control Register............................................. 41

Common Mode and Pad Strength Register............................ 41

DAC Power Adjust 1 Register................................................... 42

DAC Power Adjust 2 Register................................................... 43

DAC Power Adjust 3 Register................................................... 44

Packaging and Ordering Information ......................................... 48

Outline Dimensions................................................................... 48

Ordering Guide .......................................................................... 48

Automotive Products................................................................. 48

REVISION HISTORY

3/16—Rev. 0 to Rev. A

12/13—Revision 0: Initial Version

Changes to Table 4............................................................................ 5

Rev. A | Page 2 of 48

Data Sheet

ADAU1962

SPECIFICATIONS

Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.

Master clock = 12.288 MHz (48 kHz f_S, 256 × f_Smode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word

width = 24 bits, load capacitance (digital output) = 20 pF, load current (digital output) = 1 mA or 1.5 kΩ to ½ DVDD supply, input

voltage high = 2.0 V, input voltage low = 0.8 V, analog audio output resistive load = 3100 Ω per pin, unless otherwise noted.

ANALOG PERFORMANCE SPECIFICATIONS

Specifications guaranteed at AVDDx = 5 V, DVDD = 2.5 V, and an ambient temperature¹(T_A) at 25°C, unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range

20 Hz to 20 kHz, −60 dB input

No Filter (RMS)

With A-Weighted Filter (RMS)

Total Harmonic Distortion + Noise (THD + N)

105

108

115.5

118

−98

dB

Two channels running, −1 dBFS

All channels running, −1 dBFS

−85

−98

Full-Scale Differential Output Voltage

Gain Error

Offset Error

3.00 (8.48)

V rms (V p-p)

%

mV

ppm/°C

dB

Degrees

−10

−25

−30

+10

+25

+30

−6

Gain Drift

Interchannel Isolation

Interchannel Phase Deviation

Volume Control

100

0

Step

Range

0.375

95.25

dB

Ω

De-Emphasis Gain Error

Output Resistance at Each Pin

REFERENCE VOLTAGES

Temperature Sensor Reference Voltage

Common-Mode Reference Output

External Reference Voltage Source

TEMPERATURE SENSOR

Temperature Accuracy

Temperature Readout

Range

0.6

33

TS_REF pin

CM pin

1.50

2.25

V

2.14

2.29

−3

+3

°C

−60

0.25

+140

6

°C

Hz

Step Size

Temperature Sample Rate

REGULATOR

1

Input Supply Voltage

Regulated Output Voltage

VSUPPLY pin

VSENSE pin

3.0

2.26

5

2.50

5.5

2.59

V

¹Functionally guaranteed at −40°C to +125°C case temperature.

Rev. A | Page 3 of 48

ADAU1962

Data Sheet

Specifications guaranteed at AVDDx = 5 V, DVDD = 2.5 V, and an ambient temperature¹(T_A) at 105°C, unless otherwise noted.

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DIGITAL-TO-ANALOG CONVERTERS

Dynamic Range

20 Hz to 20 kHz, −60 dB input

No Filter (RMS)

109

113.5

dB

With A-Weighted Filter (RMS)

Total Harmonic Distortion + Noise (THD + N)

110.5

116

dB

Two channels running, −1 dBFS

All channels running, −1 dBFS

−92.5

3.00 (8.48)

−85

Full-Scale Differential Output Voltage

Gain Error

Offset Error

V rms (V p-p)

%

mV

ppm/°C

dB

Degrees

−10

−25

−30

+10

+25

+30

−6

Gain Drift

Interchannel Isolation

Interchannel Phase Deviation

Volume Control

100

0

Step

Range

0.375

95.25

dB

Ω

De-Emphasis Gain Error

Output Resistance at Each Pin

REFERENCE

0.6

33

Temperature Sensor Reference Voltage

Common-Mode Reference Output

External Reference Voltage Source

REGULATOR

TS_REF pin

CM pin

1.50

2.25

V

2.14

2.29

Input Supply Voltage

Regulated Output Voltage

VSUPPLY pin

VSENSE pin

3.0

2.25

5

2.50

5.5

2.55

V

¹Functionally guaranteed at −40°C to +125°C case temperature.

CRYSTAL OSCILLATOR SPECIFICATIONS

Table 3.

Parameter

Min

Typ

Max

Unit

TRANSCONDUCTANCE

T_A= 25°C

T_A= 105°C

6.4

5.2

7 to 10

7.5 to 8.5

14

12

mmhos

Rev. A | Page 4 of 48

Data Sheet

ADAU1962

DIGITAL INPUT/OUTPUT SPECIFICATIONS

−40°C < T_A< +105°C, IOVDD = 5.0 V, and 3.3 V 10ꢀ, unless otherwise noted.

Table 4.

Parameter

INPUT VOLTAGE

Voltage Level

High

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

V_IH

V_IL

0.7 × IOVDD

V

Low

0.3 × IOVDD

Input Leakage

I_IHat V_IH= 3.3 V

I_ILat V_IL= 0 V

10

5

μA

pF

INPUT CAPACITANCE

OUTPUT VOLTAGE

Voltage Level

High

V_OH

V_OL

I_OH= 1 mA

I_OL= 1 mA

0.8 × IOVDD

V

Low

0.1 × IOVDD

POWER SUPPLY SPECIFICATIONS

Table 5.

Parameter

SUPPLIES

Voltage

Test Conditions/Comments

Min Typ Max Unit

AVDDx

DVDD

PLLVDD

IOVDD

VSUPPLY

4.5

5.0

5.5

3.6

5.5

V

2.25 2.5

3.0

5.0

Analog Current

Normal Operation

Power-Down

AVDDx = 5.0 V

64

1

mA

μA

Digital Current

DVDD = 2.5 V

Normal Operation

Power-Down

PLL Current

f_S= 48 kHz to 192 kHz

No master clock or I²S

PLLVDD = 2.5 V

30

4

mA

μA

Normal Operation

Power-Down

f_S= 48 kHz to 192 kHz

5

1

mA

μA

Input/Output Current

Normal Operation

Power-Down

IOVDD = 3.3 V

4

1

mA

μA

QUIESCENT POWER DISSIPATION—DITHER INPUT

Operation

Master clock = 256 × f_S, 48 kHz

All Supplies

Analog Supply

Digital Supply

PLL Supply

AVDDx = 5.0 V, DVDD/PLLVDD = 2.5 V, IOVDD = 3.3 V

AVDDx = 5.0 V, 26.7 mW per channel

DVDD = 2.5 V

PLLVDD = 2.5 V

IOVDD = 3.3 V

421

320

75

13

0

mW

I/O Supply

Power-Down, All Supplies

POWER SUPPLY REJECTION RATIO

Signal at Analog Supply Pins

1 kHz, 200 mV p-p

20 kHz, 200 mV p-p

85

dB

Rev. A | Page 5 of 48

ADAU1962

Data Sheet

DIGITAL FILTERS

Table 6.

Parameter

Mode

Factor

Min Typ Max

Unit

DAC INTERPOLATION FILTER

Pass Band

48 kHz mode, typical at 48 kHz

96 kHz mode, typical at 96 kHz

192 kHz mode, typical at 192 kHz

48 kHz mode, typical at 48 kHz

96 kHz mode, typical at 96 kHz

192 kHz mode, typical at 192 kHz

48 kHz mode, typical at 48 kHz

96 kHz mode, typical at 96 kHz

192 kHz mode, typical at 192 kHz

48 kHz mode, typical at 48 kHz

96 kHz mode, typical at 96 kHz

192 kHz mode, typical at 192 kHz

48 kHz mode, typical at 48 kHz

96 kHz mode, typical at 96 kHz

192 kHz mode, typical at 192 kHz

48 kHz mode, typical at 48 kHz

96 kHz mode, typical at 96 kHz

192 kHz mode, typical at 192 kHz

192 kHz low propagation delay mode, typical at 192 kHz

0.4535 × f_S

0.3646 × f_S

22

70

kHz

35

Pass-Band Ripple

Transition Band

Stop Band

0.01 dB

0.05 dB

0.1

dB

0.5 × f_S

0.5465 × f_S

0.6354 × f_S

24

48

96

26

61

122

kHz

dB

μs

Stop-Band Attenuation

Propagation Delay

68

25/f_S

11/f_S

8/f_S

521

115

42

μs

2/f_S

10

TIMING SPECIFICATIONS

−40°C < T_A< +105°C, DVDD = 2.5 V 10ꢀ, unless otherwise noted.

Table 7.

Parameter¹

Description

Min Typ Max Unit

INPUT MASTER CLOCK (MCLKI)

t_MH

Master clock duty cycle, DAC clock source = PLL clock

at 256 × f_S, 384 × f_S, 512 × f_S, and 768 × f_S

DAC clock source = direct MCLKI at 512 × f_S(bypass

on-chip PLL)

MCLKI frequency of the MCLKI/XTALI pin, PLL mode

Direct MCLKI 512 × f_Smode

DBCLK pin, PLL mode

40

6.9

60

%

f_MCLK

40.5 MHz

27.1 MHz

27.0 MHz

f_BCLK

POWER UP and RESET (PU/RST)

t_PDR

t_PDRR

Active low for reset time

Recovery, reset to active output

15

300

ns

ms

PLL

Lock Time

MCLKI input of the MCLKI/XTALI pin

DLRCLK pin input

256 × f_SVCO clock

10

50

60

ms

%

Output Duty Cycle, MCLKO Pin

40

Rev. A | Page 6 of 48

Data Sheet

ADAU1962

Parameter¹

SPI PORT

f_SCLK

t_SCH

t_SCL

t_MOS

t_MOH

t_SSS

Description

Min Typ Max Unit

See Figure 17

SCLK frequency, not shown in Figure 17

SCLK high

10

MHz

ns

35

10

SCLK low

MOSI setup, time to SCLK rising

MOSI hold, time from SCLK rising

SS setup, time to SCLK rising

SS hold, time from SCLK falling

SS high

t_SSH

t_SSHIGH

t_MIE

MISO enable from SS falling

MISO delay from SCLK falling

MISO hold from SCLK falling, not shown in Figure 17

MISO tristate from SS rising

30

t_MID

t_MIH

t_MITS

30

I²C

f_SCL

t_SCLL

t_SCLH

t_SCS

See Figure 2 and Figure 13

SCL clock frequency

SCL low

400

kHz

μs

1.3

0.6

SCL high

μs

Setup time (start condition), relevant for repeated start 0.6

condition

t_SCH

Hold time (start condition), first clock generated after

this period

0.6

μs

t_SSH

t_DS

t_SR

t_SF

Setup time (stop condition)

Data setup time

SDA and SCL rise time

SDA and SCL fall time

Bus-free time between stop and start

See Figure 19

0.6

100

μs

ns

μs

300

t_BFT

1.3

DAC SERIAL PORT

t_DBH

t_DBL

t_DLS

t_DLH

t_DLSK

DBCLK high, slave mode

DBCLK low, slave mode

DLRCLK setup, time to DBCLK rising, slave mode

DLRCLK hold from DBCLK rising, slave mode

DLRCLK skew from DBCLK falling, master mode; not

shown in Figure 19

10

5

ns

−8

+8

t_DDS

t_DDH

DSDATAx setup to DBCLK rising

DSDATAx hold from DBCLK rising

10

5

ns

¹The timing specifications may refer to single functions of multifunction pins, such as the SCLK function of the SCLK/SCL/SA pin.

Timing Diagram

t_DS

t_SCH

SDA

SCL

t_SR

t_SCLH

t_BFT

t_SCS

t_SSH

t_SCLL

t_SF

Figure 2. I²C Timing Diagram

Rev. A | Page 7 of 48

ADAU1962

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 8.

θ_JArepresents junction-to-ambient thermal resistance, and θ_JC

represents the junction-to-case thermal resistance. All charac-

teristics are for a 4-layer board with a solid ground plane.

Parameter

Rating

Analog (AVDDx)

Input/Output (IOVDD)

Digital (DVDD)

PLL (PLLVDD)

VSUPPLY

Input Current (Except Supply Pins)

Analog Input Voltage (Signal Pins)

Digital Input Voltage (Signal Pins)

Operating Temperature Range (Case)

Storage Temperature Range

−0.3 V to +5.5 V

−0.3 V to +3.6 V

−0.3 V to +6.0 V

20 mA

–0.3 V to AVDDx + 0.3 V

−0.3 V to DVDD + 0.3 V

−40°C to +125°C

−65°C to +150°C

Table 9. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

80-Lead LQFP

42.3

10.0

°C/W

ESD CAUTION

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. A | Page 8 of 48

Data Sheet

ADAU1962

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1

2

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

DAC_BIAS3

DAC_BIAS4

AVDD3

NC

DAC_BIAS2

DAC_BIAS1

AVDD2

PIN 1

INDICATOR

3

4

DAC4N

5

NC

DAC4P

6

NC

DAC3N

7

NC

DAC3P

8

NC

DAC2N

9

NC

DAC2P

ADAU1962

10

11

12

13

14

15

16

17

18

19

20

NC

DAC1N

TOP VIEW

NC

DAC1P

(Not to Scale)

AVDD4

AGND4

PLLGND

LF

AVDD1

AGND1

PU/RST

SA_MODE

SS/ADDR0/SA

SCLK/SCL/SA

MISO/SDA/SA

MOSI/ADDR1/SA

DVDD

PLLVDD

MCLKI/XTALI

XTALO

MCLKO

DVDD

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

NOTES

1. NC = NO CONNECT. LEAVE THIS PIN FLOATING; DO NOT TIE TO GROUND OR POWER.

2. SEE THE STANDALONE MODE SECTION (TABLE 13 AND TABLE 14) FOR THE SA_MODE SETTINGS

FOR PIN 31, PIN 32, AND PIN 42 THROUGH PIN 45.

Figure 3. Pin Configuration

Table 10. Pin Function Descriptions

Pin No.

Mnemonic^{1, 2}

DAC_BIAS3

DAC_BIAS4

AVDD3

Type³

Description

1

2

3

I

DAC Bias 3. AC couple Pin 1 with a 470 nF capacitor to AGND3.

DAC Bias 4. AC couple Pin 2 with a 470 nF capacitor to AVDD3.

Analog Power.

PWR

4 to 11

12

13

14

15

16

17

18

NC

AVDD4

No Connect. Leave these pins floating; do not tie to ground or power.

Analog Power.

Analog Ground.

PWR

GND

O

PWR

I

O

PWR

GND

PWR

I

AGND4

PLLGND

LF

PLLVDD

MCLKI/XTALI

XTALO

MCLKO

DVDD

DGND

PLL Ground.

PLL Loop Filter. Reference the LF pin to PLLVDD.

PLL Power. Apply 2.5 V to power the PLL.

Master Clock Input/Input to Crystal Inverter. This is a multifunction pin.

Output from Crystal (XTAL) Inverter.

Master Clock Output.

19

20, 29, 41

21, 26, 30, 40

22, 39

Digital Power, 2.5 V.

Digital Ground.

IOVDD

VSENSE

Power for Digital Input and Output Pins, 3.3 V or 5 V.

2.5 V Regulator Output, Pass Transistor Collector. Bypass VSENSE with a 10 μF capacitor in

parallel with a 100 nF capacitor.

23

24

VDRIVE

O

Pass Transistor Base Driver.

Rev. A | Page 9 of 48

ADAU1962

Data Sheet

Pin No.

Mnemonic^{1, 2}

Type³

Description

25

VSUPPLY

I

5 V Voltage Regulator Input, Pass Transistor Emitter. Bypass VSUPPLY with a 10 μF capacitor

in parallel with a 100 nF capacitor.

27

28

31, 32

DBCLK

DLRCLK

SA

I/O

I

Bit Clock for DACs.

Left Right Frame Clock for DACs.

Standalone Mode, Time Domain Multiplexed (SA_MODE TDM) State. See the Standalone

Mode section, Table 13, and Table 14 for more information.

33

34

35

36

37

38

42

DSDATA6

DSDATA5

DSDATA4

DSDATA3

DSDATA2

DSDATA1

MOSI/ADDR1/SA

I

DAC11 and DAC12 Serial Data Input.

DAC9 and DAC10 Serial Data Input.

DAC7 and DAC8 Serial Data Input.

DAC5 and DAC6 Serial Data Input.

DAC3 and DAC4 Serial Data Input.

DAC1 and DAC2 Serial Data Input.

Master Output Slave Input (SPI)/Address 1 (I²C)/Standalone Mode (SA_MODE) State. This is

a multifunction pin. See the Standalone Mode section and Table 13 for more information.

43

MISO/SDA/SA

I/O

Master Output Slave Input (SPI)/Control Data Input (I²C)/Standalone Mode (SA_MODE) State.

This is a multifunction pin. See the Standalone Mode section and Table 13 for more

information.

44

45

46

SCLK/SCL/SA

SS/ADDR0/SA

SA_MODE

I

Serial Clock Input (SPI)/Control Clock Input (I²C)/Standalone Mode (SA_MODE) State. This is a

multifunction pin. See the Standalone Mode section and Table 13 for more information.

Slave Select (SPI) Active Low/Address 0 (I²C)/Standalone Mode (SA_MODE) State. This is a

multifunction pin. See the Standalone Mode section and Table 13 for more information.

Standalone Mode, Active High. This pin allows mode control of the ADAU1962 using Pin 42

to Pin 45, Pin 31, and Pin 32 (see Table 13 and Table 14 for more information).

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

PU/RST

AGND1

AVDD1

DAC1P

DAC1N

DAC2P

DAC2N

DAC3P

DAC3N

DAC4P

DAC4N

AVDD2

DAC_BIAS1

DAC_BIAS2

AGND2

CM

I

Power-Up/Reset (Active Low). See Power-Up and Reset section for more information.

GND

PWR

O

Analog Ground.

Analog Power.

DAC1 Positive Output.

DAC1 Negative Output.

DAC2 Positive Output.

DAC2 Negative Output.

DAC3 Positive Output.

DAC3 Negative Output.

DAC4 Positive Output.

DAC4 Negative Output.

Analog Power.

Filter for DAC Bias 1. AC couple Pin 59 with a 470 nF capacitor to AVDD2.

Filter for DAC Bias 2. AC couple Pin 60 with a 470 nF capacitor to AGND2.

Analog Ground.

Common-Mode Reference Filter Capacitor Connection. Bypass the CM pin with a 10 μF

capacitor in parallel with a 100 nF capacitor to AGND2. The internal reference can be shut

off in the PLL_CLK_CTRL1 register and the pin can be driven with an outside voltage source.

O

PWR

I

GND

O

63

TS_REF

O

Voltage Reference Filter Capacitor Connection. Bypass Pin 63 with a 10 μF capacitor in

parallel with a 100 nF capacitor to AGND2.

64

65

66

67

68

69

70

71

72

73

DAC5P

DAC5N

DAC6P

DAC6N

DAC7P

DAC7N

DAC8P

DAC8N

DAC9P

DAC9N

O

DAC5 Positive Output.

DAC5 Negative Output.

DAC6 Positive Output.

DAC6 Negative Output.

DAC7 Positive Output.

DAC7 Negative Output.

DAC8 Positive Output.

DAC8 Negative Output.

DAC9 Positive Output.

DAC9 Negative Output.

Rev. A | Page 10 of 48

Data Sheet

ADAU1962

Pin No.

74

75

76

77

78

79

80

Mnemonic^{1, 2}

Type³

O

GND

Description

DAC10P

DAC10N

DAC11P

DAC11N

DAC12P

DAC12N

AGND3

DAC10 Positive Output.

DAC10 Negative Output.

DAC11 Positive Output.

DAC11 Negative Output.

DAC12 Positive Output.

DAC12 Negative Output.

Analog Ground.

¹AVDD1, AVDD2, AVDD3, and AVDD4 are referred to elsewhere in this data sheet as AVDDx when AVDDx means any or all of the ADVD pins.

²DAC Channel 1 to DAC Channel 12 pins are referred to elsewhere in this data sheet as DACx, DACxP, or DACxN when it means any or all of the DAC channel pins.

³I = input, O = output, I/O = input/output, PWR = power, and GND = ground.

Rev. A | Page 11 of 48

ADAU1962

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0.05

0.04

0.03

0.02

0.01

0

0.20

0.15

0.10

0.05

0

–0.01

–0.02

–0.03

–0.04

–0.05

–0.10

–0.15

–0.20

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

FREQUENCY (FACTORED TO f_S

0

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

)

FREQUENCY (FACTORED TO f_S

)

Figure 4. DAC Pass-Band Filter Response, 48 kHz

Figure 6. DAC Pass-Band Filter Response, 96 kHz

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

FREQUENCY (FACTORED TO f_S

)

FREQUENCY (FACTORED TO f_S

)

Figure 5. DAC Stop-Band Filter Response, 48 kHz

Figure 7. DAC Stop-Band Filter Response, 96 kHz

Rev. A | Page 12 of 48

Data Sheet

ADAU1962

TEST CIRCUITS

10µF

+

237Ω

Typical application circuits are shown in Figure 8 to Figure 11.

Recommended loop filters for the DLRCLK and MCLKI/XTALI

modes of the PLL reference are shown in Figure 8. Output

filters for the DAC outputs are shown in Figure 9 and Figure 11,

and a recommended external regulator circuit is shown in

Figure 10.

DACxP

DACxN

OUTPUTxP

OUTPUTxN

2.7nF

237Ω

10µF

+

49.9kΩ

DLRCLK

MCLKI/XTALI

LF

39nF

5.6nF

Figure 9. Typical DAC Output Passive Filter Circuit (Differential)

2.2nF

390pF

3.32kΩ

562Ω

100nF

10µF

E

+

PLLVDD

VSUPPLY

5V

Figure 8. Recommended Loop Filters for DLRCLK and MCLKI/XTALI PLL

Reference Modes

1kΩ

B

VDRIVE

VSENSE

FZT953

C

2.5V

+

100nF

10µF

Figure 10. Recommended External Regulator Circuit

1.1nF

AD8672ARZ

1.50kΩ

1.54kΩ

5

4.7µF

+

DACxP

+12V DC

100Ω

7

OUTPUTxP

6

422Ω

2.49kΩ

100kΩ

+

0.1µF

4.7µF

1nF

4.7µF

8

V+

V–

4

+

4.7µF

2.49kΩ

422Ω

2

3

–12V DC

4.7µF

+

100Ω

1

OUTPUTxN

1.50kΩ

1.54kΩ

DACxN

AD8672ARZ

1.1nF

Figure 11. Typical DAC Output Active Filter Circuit (Differential)

Rev. A | Page 13 of 48

ADAU1962

Data Sheet

THEORY OF OPERATION

If more signal level is required or if a more robust filter is needed, a

single op amp gain stage, designed as a second-order, low-pass

Bessel filter, can be used to remove the high frequency out-of-

band noise present on each pin of the differential outputs. The

choice of components and design of this circuit are critical to

obtaining the full DNR yield of the DACs (see the recommended

passive and active circuits in Figure 9 and Figure 11). This filter

can be built into an active differential amplifier to provide a single-

ended output with gain, if necessary. Note that the use of op amps

with low slew rate or low bandwidth can cause high frequency

noise and tones to fold down into the audio band; exercise care

when selecting these components.

DIGITAL-TO-ANALOG CONVERTERS (DACs)

For improved noise and distortion performance, the ADAU1962

includes 12 differential DAC channels configured as voltage

outputs for a simplified connection. The DACs include on-chip

digital interpolation filters with 68 dB stop-band attenuation and

linear phase response, operating at an oversampling ratio of

256× (48 kHz range), 128× (96 kHz range), or 64× (192 kHz

range). Each channel has its own independently programmable

attenuator, adjustable in 255 steps in increments of 0.375 dB.

Digital inputs are supplied through six serial data input pins

(two channels on each pin), a common frame clock (DLRCLK),

and a bit clock (DBCLK). Alternatively, any one of the time domain

multiplexed (TDM) modes can be used to access up to 12 channels

on a single TDM data line.

The ADAU1962 offers control over the analog performance of

the DACs; it is possible to program the registers to reduce the

power consumption with the trade-off of lower signal-to-noise

ratio (SNR) and THD + N. The reduced power consumption is the

result of changing the internal bias current to the analog output

amplifiers.

The ADAU1962 has a low propagation delay mode; this mode

is an option for an f_Sof 192 kHz and is enabled in Register DAC_

CTRL0[2:1]. By setting these bits to 0b11, the propagation delay

is reduced by the amount listed in Table 6. The shorter delay is

achieved by reducing the amount of digital filtering; the negative

impact of selecting this mode is reduced audio frequency response

and increased out-of-band energy.

The DAC_POWER1 to DAC_POWER3 registers present four

basic settings for the DAC power vs. performance in each of the

12 channels: best performance, good performance, low power,

and lowest power.

When AVDDx is supplied with +5 V, each analog output pin

has a nominal common-mode (CM) dc level of +2.25 V and

swings 2.12 V above and below the +2.25 V for a 1.5 V rms

signal on each pin. Differentially, the signal is 3 V rms

(8.48 V p-p) from a 0 dBFS digital input signal.

Alternatively, in Register PLL_CLK_CTRL1[7:6], the

LOPWR_MODE bits offer global control over the power and

performance for all 12 channels. The default setting is 0b00.

This setting allows the channels to be controlled individually

using the DAC_POWERx registers. Setting 0b10 and 0b11

selects the low power and lowest power settings, respectively.

The data presented in Table 11 shows the result of setting all

12 channels to each of the four settings. The SNR and THD + N

specifications are shown in relation to the measured performance

of a device at the best performance setting.

The differential analog outputs require a mere single-order,

passive differential resistor-capacitor (RC) filter to provide the

specified DNR performance (see Figure 9 for an example filter).

The outputs can easily drive differential inputs on a separate

printed circuit board (PCB) through cabling, as well as

differential inputs on the same PCB.

The voltage at CM, the common-mode reference pin, can be

used to bias the external op amps that buffer the output signals

(see the Power Supply and Voltage Reference section).

Table 11. DAC Power vs. Performance

Register Setting

Total AVDDx Current

SNR

Best Performance

Good Performance

57 mA

−0.2 dB

Low Power

50 mA

−1.5 dB

−3.0 dB

Lowest Power

43 mA

−14.2 dB

−5.8 dB

64 mA

Reference

THD + N (−1 dbFS Signal)

−1.8 dB

Rev. A | Page 14 of 48

Data Sheet

ADAU1962

12.288 MHz. Switching the ADAU1962 to 96 kHz operation (by

writing to DAC_CTRL0[2:1]), the frequency of the master clock

remains at 12.288 MHz, which is an MCS ratio of 128 × f_Sin this

example. Therefore, in 192 kHz mode, MCS becomes 64 × f_S.

CLOCK SIGNALS

RST

Powering the ADAU1962 and asserting the PU/

pin high

starts the device in either standalone mode (SA_MODE) or

program mode, depending on the state of SA_MODE (Pin 46). The

clock functionality of SA_MODE is described in the Standalone

Mode section.

The internal clock for the digital core varies by mode: 512 × f_S

(48 kHz mode), 256 × f_S(96 kHz mode), or 128 × f_S(192 kHz

mode). By default, the on-board PLL generates this internal

master clock from an external clock.

The ADAU1962 default in program mode is for the MCLKO pin

to feed a buffered output of the MCLKI signal on the MCLKI/

XTALI pin. The default for the DLRCLK and DBCLK ports is

slave mode; to function, drive the DAC with a coherent set of

master clock, frame clock, and bit clock signals.

The PLL must be powered and stable before using the ADAU1962

as a source for quality audio. A reset enables the PLL and does

not require writing to the I²C or SPI port for normal operation.

With the PLL enabled, the performance of the ADAU1962 is

unaffected by jitter as high as a 300 ps rms time interval error

(TIE). When the internal PLL is disabled, use an independent

crystal oscillator to generate the master clock.

Use Register PLL_CLK_CTRL1[5:4] to program the MCLKO

pin to provide different clock signals. The default, 0b10,

provides a buffered copy of the clock signal that is driving the

MCLKI pin function. Two modes, 0b00 and 0b01, provide low

jitter clock signals.

When using the ADAU1962 in direct master clock mode, power

down the PLL in the PDN_THRMSENS_CTRL_1 register. For

direct master clock mode, feed a frequency of 512 × f_S(referenced

to 48 kHz mode) into the MCLKI pin, and set the CLK_SEL bit

in the PLL_CLK_CTRL1 register to 1.

The 0b00 setting yields a clock rate between 4 MHz and 6 MHz,

and the 0b01 setting yields a clock rate between 8 MHz and

12 MHz. Both of these clock frequencies scale automatically as

ratios of the master clock inside the ADAU1962.

The ADAU1962 PLL can also be programmed to run from an

external LRCLK without an external master clock. Setting the

PLLIN bits in the PLL_CLK_CTRL0 register to 0b01 and connect-

ing the appropriate loop filter to the LF pin (see Figure 8), the

ADAU1962 PLL generates all of the necessary internal clocks for

operation with no external master clock. This mode reduces the

number of high frequency signals in the design, reducing EMI

emissions.

As an example, an input to MCLKI of 8.192 MHz and a setting

of 0b00 yield an MCLKO of (8.192/2) = 4.096 MHz. Alternatively,

an input to MCLKI of 36.864 MHz and a setting of 0b01 yield an

MCLKO frequency of (36.864/3) = 12.288 MHz. The setting, 0b11,

shuts off the MCLKO pin.

Program the PLL_CLK_CTRLx registers (Register 0x00 and

RST

Register 0x01) only after asserting the PU/

pin high. Select

the on-chip PLL to use the clock appearing at the MCLKI/XTALI

pin at a frequency of 256, 384, 512, or 768 times the sample rate (f_S),

referenced to the 48 kHz mode from the master clock select (MCS)

setting, as listed in Table 12.

It is possible to reduce the EMI emissions of the circuit further

by using the internal bit clock generation setting of the BCLK_GEN

bit in the DAC_CTRL1 register. Setting the BCLK_GEN bit to 1

(internal) and the SAI_MS bit to 0 (slave), the ADAU1962

generates its own bit clock; this configuration works with the PLL

input register, PLL_CLK_CTRL0[7:6] set to either MCLKI/XTALI

or DLRCLK. The clock on the DLRCLK pin is the only required

clock in DLRCLK PLL mode.

In 96 kHz mode, the master clock frequency stays at the same

absolute frequency; therefore, the actual multiplication rate is

divided by 2; likewise, in 192 kHz mode, the actual multiplication

rate is divided by 4.

For example, programming the ADAU1962 in 256 × f_Smode

derives a master clock input frequency of 256 × 48 kHz =

Table 12. MCS and f_SModes

Master Clock Select (MCS), PLL_CLK_CTRL0[2:1]

Sample Rate Select,

DAC_CTRL0[2:1]

Setting 0, 0b00

Master

Setting 1, 0b01

Setting 2, 0b10

Setting 3, 0b11

Master

f_S(kHz)

Bit Setting

0b00

Ratio

Clock (MHz)

Ratio

Clock (MHz)

Ratio

Clock (MHz)

Ratio

Clock (MHz)

32

44.1

48

256 × f_S

128 × f_S

64 × f_S

8.192

384 × f_S

192 × f_S

96 × f_S

12.288

16.9344

18.432

12.288

16.9344

18.432

12.288

16.9344

18.432

512 × f_S

256 × f_S

128 × f_S

16.384

22.5792

24.576

16.384

22.5792

24.576

16.384

22.5792

24.576

768 × f_S

384 × f_S

192 × f_S

24.576

33.8688

36.864

24.576

33.8688

36.864

24.576

33.8688

36.864

11.2896

12.288

8.192

11.2896

12.288

8.192

0b00

64

88.2

96

0b01

128

176.4

192

0b10 or 0b11

64 × f_S

11.2896

12.288

96 × f_S

Rev. A | Page 15 of 48

ADAU1962

Data Sheet

Setting both the SA_MODE pin and Pin 45 to high selects TDM

mode. Table 14 shows the available TDM modes; set these modes

by connecting Pin 31 (SA) and Pin 32 (SA) to GND or IOVDD.

POWER-UP AND RESET

The power sequencing of the ADAU1962 begins with AVDDx

and IOVDD, followed by DVDD. It is very important that

AVDDx be settled at a regulated voltage and that IOVDD be

within 10ꢀ of the regulated voltage before applying DVDD.

When using the ADAU1962 internal regulator, this timing

occurs by default.

Table 14. TDM Modes

Pin No.

Setting

Function

31, 32

00

01

10

11

TDM4: DLRCLK pulse

TDM8: DLRCLK pulse

TDM16: DLRCLK pulse

TDM8: DLRCLK 50% duty cycle

RST

To guarantee proper startup, pull the PU/

an external resistor and then, after the power supplies have

RST RST

can also be pulled

pin low by using

stabilized, drive PU/

high using a simple RC network.

RST

high. The PU/

By powering up the ADAU1962 in SA_MODE and asserting the

RST

PU/

high, the MCLKO pin provides a buffered version of

the MCLKI/XTALI pin, whether the source is a crystal or an

active oscillator.

I²C CONTROL PORT

Driving the PU/

power state (<3 μA), disabling all functionality of the ADAU1962

RST

pin low puts the device into a very low

until the PU/

pin is asserted high. After asserting this pin

high, the ADAU1962 requires 300 ms to stabilize. Toggle the

MMUTE bit in the DAC_CTRL0 register for operation.

The ADAU1962 has an I²C-compatible control port that permits

programming and readback of the internal control registers for

the DACs and clock system. The I²C interface of the ADAU1962 is

a 2-wire interface consisting of a clock line (SCL) and a data line

(SDA). SDA is bidirectional, and the ADAU1962 drives SDA

either to acknowledge the master (ACK) or to send data during

a read operation. The SDA line (on the MISO/SDA/SA pin) for

the I²C port is an open-drain collector and requires a 2 kΩ pull-up

resistor. A write or read access occurs when the SDA line is

pulled low while the SCL line (on the SCLK/SCL/SA pin) is high,

indicated by a start in Figure 12 and Figure 13.

Use the PUP bit (master power-up control) in the PLL_CLK_

CTRL0 register to power down the ADAU1962. Setting the

master power-up bit to 0 puts the ADAU1962 in an idle state

while maintaining the settings of all registers. Additionally, to

power down individual sections of the ADAU1962, use the

power-down bits in the PDN_THRMSENS_CTRL1 register

(TS_PDN, PLL_PDN and VREG_PDN).

The SOFT_RST bit in the PLL_CLK_CTRL0 register sets all of

the control registers to their default settings while maintaining

the internal clocks in default mode. The SOFT_RST bit does not

power down the analog outputs, and toggling this bit does not

cause audible popping sounds at the differential analog outputs.

SDA is only allowed to change when SCL is low, except when a

start or stop condition occurs, as shown in Figure 12 and Figure 13.

The first eight bits of the data-word consist of the device address

W

and the R/ bit. The device address consists of an internal built-in

For proper startup of the ADAU1962, follow these steps:

address (0x04) and two address pins, the ADDR1 function of

the MOSI/ADDR1/SA pin and the ADDR0 function of the

/ADDR0/SA pin (see Table 15).

1. Apply power to the ADAU1962 as described previously in

the Power-Up and Reset section.

SS

RST

2. Assert the PU/

stable.

pin high after the power supplies are

Table 15. I²C Addresses

3. Set the PUP bit to 1.

4. Program all necessary registers for the desired settings.

5. Set the MMUTE bit to 0 to unmute all channels.

ADDR1 (AD1)

ADDR0 (AD0)

Slave Address

0x04

0x24

0x44

0x64

0

1

0

1

0

1

STANDALONE MODE

The ADAU1962 can operate without a typical I²C or SPI

connection to a microcontroller. This standalone mode is

available by setting the SA_MODE (Pin 46) to IOVDD. All

registers are set to default except for the options shown in Table 13.

Table 13. SA_MODE Settings

Pin No. Setting Function

42

43

0

1

0

1

0

1

Master mode serial audio interface (SAI)

Slave mode SAI

MCLKI = 256 × f_S, PLL on

MCLKI = 384 × f_S, PLL on

Must be set to 0

I²S SAI format

TDM modes, determined by Pin 31 and Pin 32

44

45

Rev. A | Page 16 of 48

Data Sheet

ADAU1962

I²C Write

3. Send a second frame directing the ADAU1962 to which

register is required to be written.

a. A second acknowledge is issued by the ADAU1962.

4. Send a third frame with the eight data bits required to be

written to the register. A third acknowledge is issued by the

ADAU1962.

The two address bits allow four ADAU1962 devices to be used in

a system. Initiating a write operation to the ADAU1962 involves

the following steps (see Figure 12):

1. Send a start condition

2. Send the device address with the R/ bit set low. The

W

5. Send a stop condition to complete the data transfer.

ADAU1962 responds by issuing an acknowledge to

indicate that it has been addressed.

Table 16. I²C Abbreviations

Abbreviation

Description

S

P

Start bit

Stop bit

AM

AS

Acknowledge by master

Acknowledge by slave

Table 17. Single Word I²C Write

S

Chip Address, R/W = 0

AS

Register Address

AS

Data-Word

AS

P

Table 18. Burst Mode I²C Write

S

Chip Address, R/W = 0

AS

Register Address

AS

Data-Word 1

AS

Data-Word 2

AS

Data-Word N

AS

P

SCL

SDA

AD1

AD0

0

1

0

R/W

0

1

0

START BY

MASTER (S)

ACK. BY

ADAU1962 (AS)

ACK. BY

ADAU1962 (AS)

FRAME 1

CHIP ADDRESS BYTE

FRAME 2

REGISTER ADDRESS BYTE

SCL

(CONTINUED)

SDA

(CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

ACK. BY STOP BY

ADAU1962 MASTER (P)

FRAME 3

DATA BYTE TO ADAU1962

Figure 12. I²C Write Format

Rev. A | Page 17 of 48

ADAU1962

Data Sheet

I²C Read

2. Issue a repeated start condition. The next frame is the

W

device address with the R/ bit set high. On the next frame,

A read operation requires that the user first write to the

ADAU1962 to point to the correct register and then read the

data. The following steps achieve this (see Figure 13):

the ADAU1962 outputs the register data on the SDA line.

3. Issue a stop condition to complete the read operation.

1. Send a start condition followed by the device address frame

W

with the R/ bit low and then the register address frame.

The ADAU1962 responds with an acknowledge.

Table 19. Single Word I²C Read

S

Chip Address, R/W = 0

AS

Register Address

AS

S

Chip Address, R/W = 1

AS

Data-Word

AM

P

Table 20. Burst Mode I²C Read

Chip Address, AS Register AS

S

Chip Address, AS Data-Word 1 AM Data-Word 2 AM Data-Word N AM

R/W = 1

P

R/W = 0

Address

SCL

SDA

AD1

AD0

0

1

0

R/W

0

1

0

START BY

MASTER (S)

ACK. BY

ADAU1962 (AS)

ACK. BY

ADAU1962 (AS)

FRAME 1

CHIP ADDRESS BYTE

FRAME 2

REGISTER ADDRESS BYTE

SCL

(CONTINUED)

SDA

(CONTINUED)

D7

D6

D5

D4

D3

D2

D1

D0

AD1

AD0

0

1

0

R/W

REPEATED START

BY MASTER (S)

ACK. BY

ADAU1962 (AS)

ACK. BY STOP BY

MASTER (AM) MASTER (P)

FRAME 3

CHIP ADDRESS BYTE

FRAME 4

REGISTER DATA

Figure 13. I²C Read Format

Rev. A | Page 18 of 48

Data Sheet

ADAU1962

The first byte is the global address with a read/write bit. For the

ADAU1962, the address is 0x06, shifted left one bit due to the

SERIAL CONTROL PORT: SPI MODE

The ADAU1962 has a 4-wire SPI control port that permits the

programming and reading back of the internal control registers for

the DACs and clock system. A standalone mode is also available

for operation without serial control; it is configured at reset using

the SA_MODE pin. See the Standalone Mode section for details

about the SA_MODE pin.

W

R/ bit. The second byte is the ADAU1962 register address, and

the third byte is the data, as shown in Figure 15 and Figure 16.

W

Table 21. SPI Address and R/ Byte Format

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

0

1

0

R/W

By default, the ADAU1962 is in I²C mode; however, to enter SPI

When reading data from the ADAU1962, the MISO pin is

SS

control mode pull low three times. To enter SPI control mode,

tristated until the third byte, at which point it drives the data

out (see Figure 16). The MISO pin is tristated at all other times,

allowing the pin to be bussed with other devices; see Figure 17

for the timing requirements.

perform three dummy writes to the SPI port (the ADAU1962 does

not acknowledge these three writes). Beginning with the fourth

SPI write, data can be written to or read from the integrated

circuits. The ADAU1962 can exit SPI control mode only by a

full reset initiated by power cycling the device.

W

Chip Address R/

W

The SPI control port of the ADAU1962 is a 4-wire serial control

port. The format is a 24-bit wide data-word. The serial bit clock

and latch can be completely asynchronous to the sample rate of

the DACs. Table 21 shows the format of the SPI address byte.

The LSB of the first byte of a SPI transaction is an R/ bit. This bit

determines whether the communication is a read (Logic Level 1)

or a write (Logic Level 0); see Table 21 for this format.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

SS

SCLK

MOSI

Figure 14. SPI Mode Initial Sequence

0

1

2

3

4

5

6

7

8

9

10

11

12

13

15

16

17

18

19

20

21 22

23

24

25

14

SS

SCLK

MOSI

DEVICE ADDRESS (7 BITS)

R/W

8

REGISTER ADDRESS BYTE

DATA BYTE

Figure 15. SPI Write to ADAU1962 Clocking

0

1

2

3

4

5

6

7

9

10

11

12

13

15

16

17

18

19

20

21 22

23

24

25

14

SCLK

SS

DEVICE ADDRESS (7 BITS)

REGISTER ADDRESS BYTE

DATA BYTE

MOSI

MISO

R/W

DATA BYTE FROM ADAU1962

Figure 16. SPI Read from ADAU1962 Clocking

t_SSHIGH

t_SSS

t_MIE

t_SSH

t_SCL

t_SCH

SS

SCLK

MOSI

t_MOH

t_MOS

t_MITS

MISO

t_MID

Figure 17. Format of the SPI Signal

Rev. A | Page 19 of 48

ADAU1962

Data Sheet

SPI Burst Read/Write

The internal band gap reference that drives the common-mode

reference voltage for the DACs and appears on the CM pin can

be disabled in the PLL_CLK_CTRL1 register by setting VREF_EN

to 0. Then, the CM pin can be driven from an external source.

Use this configuration to scale all of the DACx outputs to the

clipping level of a power amplifier based on its power supply

voltage.

The SPI port is capable of performing burst reads or writes.

This is accomplished by sending the chip address byte with the

W

R/ bit followed by the first register address that needs to be

SS

read or written to. Then, as long as (on the /ADDR0/SA

pin) is held low, registers can be sequentially read or written by

continuing to send out clock pulses into SCLK (on the

SCLK/SCL/SA pin). To initialize the ADAU1962

The CM pin is the internal common-mode reference. Bypass

CM as close to the chip as possible with a parallel combination

of 10 μF and 100 nF capacitors. Use this voltage to bias external

op amps to the common-mode voltage of the analog input and

output signal pins. To provide a quiet, low impedance source for

the external circuitry, isolate the CM pin from the external

circuitry using a high quality buffer. Use of a quiet op amp is

critical because any noise added to the reference voltage is

injected into the signal path.

W

1. Send the address byte with the R/ bit low (write).

2. Send the address of the first register.

3. Send all the register byte values.

SS

4. Toggle the pin to end the transfer.

5. Perform a burst read to verify the register writes were

successful.

When referencing back to Analog Devices legacy devices, different

pin names (mnemonics) were used for these SPI port functions.

See Table 22 for details of the changes.

SERIAL DATA PORTS—DATA FORMAT

The 12 DAC channels use a common serial bit clock (DBCLK)

and a common left right framing clock (DLRCLK) in the serial

data port. The clock signals are all synchronous with the sample

rate. The normal stereo serial modes are shown in Figure 18.

The DACx serial data mode defaults to I²S (1-bit clock delay)

upon power-up and reset. The ports can also be programmed

for left justified and right justified (24-bit and 16-bit) operation

using DAC_CTRL0[7:6]. Select stereo and TDM modes using

DAC_CTRL0[5:3]. The polarity of the DLRCLK pin is

programmable according to the DAC_CTRL1[5] bit, allowing

for easy channel swapping.

Table 22. SPI Port Pin Naming Conventions

Pin No.

Legacy Pin Mnemonic

New Pin Mnemonic

42

43

CDATA

COUT

MOSI

MISO

SCLK

SS

44

CCLK

45

CLATCH

POWER SUPPLY AND VOLTAGE REFERENCE

The ADAU1962 is designed for 5 V analog and 2.5 V digital

supplies. To minimize noise pickup, bypass the power supply

pins with 100 nF ceramic chip capacitors placed as close to the

pins as possible. Provide a bulk aluminum electrolytic capacitor

of at least 22 μF for each rail on the same PCB as the codec. It is

important that the analog supply be as clean as possible.

The DBCLK pin can latch on the rising or the falling edge of the

clock signal. The DAC_CTRL1[1] bit selects the active edge.

The serial ports are programmable, becoming either clock masters

or slaves depending on the setting of the DAC_CTRL1[0] bit.

By default, the serial ports are in slave mode.

The ADAU1962 includes a 2.5 V regulator driver that requires

only an external pass transistor and bypass capacitors to make a

2.5 V regulator from a 5 V supply. Decouple the VSUPPLY and

VSENSE pins with no more than 10 μF of capacitance in

parallel with 100 nF high frequency bypassing. If the regulator

driver is not used, connect VSUPPLY and VDRIVE to DGND,

and leave VSENSE unconnected.

TIME DIVISION MULTIPLEXED (TDM) MODES

The ADAU1962 serial ports also have several different TDM

serial data modes. The ADAU1962 can support a single data

line (TDM16), a dual data line (TDM8), a quad data line (TDM4),

or eight data lines (TDM2). The DLRCLK/frame clock can

operate in both single cycle pulse mode and a 50ꢀ duty cycle

mode. Both 16-bit clocks or 32-bit clocks per channel are

selectable for each mode.

All digital inputs are compatible with TTL and CMOS levels.

All outputs are driven from the 3.3 V or 5 V IOVDD supply

and are compatible with TTL and 3.3 V CMOS levels.

The input/output pins of the serial ports are defined according

to the serial mode that is selected. For a detailed description of

the function of each pin in TDM and stereo modes, see Table 23.

The temperature sensor internal voltage reference (V_{TS_REF}) is

made available on the TS_REF pin to filter the reference with

external capacitors; bypass this pin as close to the chip as

possible with a parallel combination of 10 μF and 100 nF

capacitors.

Rev. A | Page 20 of 48

Data Sheet

ADAU1962

LEFT CHANNEL

RIGHT CHANNEL

DLRCLK

BCLK

DSDATAx

MSB

LSB

MSB

LSB

LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 0, SDATA_FMT = 1

LEFT CHANNEL

RIGHT CHANNEL

DLRCLK

DBCLK

MSB

I S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 0, SDATA_FMT = 0

LSB

DSDATAx

MSB

LSB

2

LEFT CHANNEL

RIGHT CHANNEL

DLRCLK

DBCLK

DSDATAx

MSB

LSB

MSB

LSB

RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL: SAI = 0, SDATA_FMT = 2 OR 3

DLRCLK

DBCLK

DSDATAx

MSB

LSB

MSB

LSB

TDM MODE—16 BITS TO 24 BITS PER CHANNEL: SAI = 1, 2, 3, OR 4

1/f_S

Figure 18. Stereo and TDM Serial Audio Modes

Table 23. Pin Function Changes in Different Serial Audio Interface (SAI) Modes

Stereo Modes

(SAI = 0 or SAI = 1)

Signal

TDM4 Mode (SAI = 2)

TDM8 Mode (SAI = 3)

TDM16 Mode (SAI = 4)

DSDATA1

Channel 1/Channel 2

data input

Channel 1 to Channel 4

data input

Channel 1 to Channel 8

data input

Channel 1 to Channel 12

data input

DSDATA2

Channel 3/Channel 4

data input

Channel 5/Channel 6

data input

Channel 7/Channel 8

data input

Channel 9/Channel 10

data input

Channel 5 to Channel 8

data input

Channel 9 to Channel 12

data input

Not used

Channel 9 to Channel 12

data input

Not used

DSDATA3

Not used

DSDATA4

DSDATA5

DSDATA6

Channel 11/Channel 12

data input

DLRCLK

DLRCLK input/DLRCLK

output

TDM frame sync input/

TDM frame sync output

TDM frame sync input/

TDM frame sync output

TDM frame sync input/

TDM frame sync output

DBCLK

DBCLK input/DBCLK

output

TDM DBCLK input/

TDM DBCLK output

TDM DBCLK input/

TDM DBCLK output

TDM DBCLK input/

TDM DBCLK output

Maximum Sample Rate

192 kHz

96 kHz

48 kHz

Rev. A | Page 21 of 48

ADAU1962

Data Sheet

t_DBH

DBCLK

t_DBL

t_DLS

t_DLH

DLRCLK

t_DDS

DSDATAx

LEFT JUSTIFIED

MODE

MSB

MSB – 1

t_DDH

t_DDS

DSDATAx

2

I S JUSTIFIED

MSB

MODE

t_DDH

t_DDS

DSDATAx

RIGHT JUSTIFIED

MODE

MSB

LSB

t_DDH

Figure 19. DAC Serial Timing

In continuous operation mode, the data conversion takes place

at a rate set by Bits[7:6], THRM_RATE, with a range of 0.5 sec to

4 sec between samples. Faster rates are possible using one shot

mode.

TEMPERATURE SENSOR

The ADAU1962 has an on-board temperature sensor that allows

the user to read the temperature of the silicon inside of the

device. The temperature sensor readout has a range of −60°C to

+140°C in 1°C steps. The PDN_THRMSENS_CTRL_1 register

controls the settings of the sensor.

When a temperature conversion is placed in the

THRM_TEMP_STAT register, the data can be translated into

degrees Celsius (°C) using the following steps:

The temperature sensor powers on by default and can be shut off

by setting the TS_PDN bit to 1 in the PDN_ THRMSENS_

CTRL_1 register. The temperature sensor can run in either

continuous operation or one shot mode. The temperature sensor

conversion mode is modified using Bit 5, THRM_MODE; the

default is THRM_MODE = 1, one shot mode. In one shot mode,

writing a 0 followed by writing a 1 to Bit 4, THRM_GO, results

in a single reset and temperature conversion, placing the resulting

temperature data in the THRM_TEMP_STAT register.

1. Convert the binary or hexadecimal data read from

THRM_TEMP_STAT into decimal form.

2. Subtract 60 from the converted THRM_TEMP_STAT

data (TEMP); this is the temperature of the silicon in °C.

Rev. A | Page 22 of 48

Data Sheet

ADAU1962

To relax the requirement for the setup time of the ADAU1962

in cases of high speed TDM data transmission, the ADAU1962

can latch in the data using the falling edge of the DBCLK pin;

see the BCLK_EDGE bit in the DAC_CTRL1 register. This

effectively dedicates the entire bit clock period to the setup

time. This mode is useful in cases where the source has a large

delay time in the serial data driver. Figure 21 shows this

inverted bit clock mode of data transmission.

ADDITIONAL MODES

The ADAU1962 offers several additional modes for board level

design enhancements. To reduce the EMI in the board level

design, serial data can be transmitted without an explicit bit

clock input on the DBCLK pin. See Figure 20 for an example of a

DAC data transmission in TDM mode that does not require a

high speed bit clock or an external master clock. This configuration

is applicable when the ADAU1962 master clock is generated by

the PLL with the DLRCLK pin as the PLL reference frequency.

DLRCLK

32 BITS

INTERNAL

DBCLK

DSDATAx

DLRCLK

INTERNAL

DBCLK

TDM DSDATAx

Figure 20. Serial DAC Data Transmission in TDM Format Without a Bit Clock Input on the DBCLK Pin

(Applicable Only If PLL Locks to the Left Right Clock on the DLRCLK Pin)

DLRCLK

DBCLK

DATA MUST BE VALID

AT THIS BCLK EDGE

MSB

DSDATAx

Figure 21. Inverted Bit Clock Mode in DAC Serial Data Transmission

(Applicable in Stereo and TDM, Useful for High Frequency TDM Transmission)

Rev. A | Page 23 of 48

ADAU1962

Data Sheet

REGISTER SUMMARY

Table 24. ADAU1962Register Summary

Reg Name

Bits Bit 7

Bit 6

Bit 5

Bit 4

XTAL_SET

Bit 3

Bit 2

Bit 1

MCS

Bit 0

Reset RW

0x00 RW

0x2A RW

0xA0 RW

0x00 PLL_CLK_CTRL0

0x01 PLL_CLK_CTRL1

[7:0]

PLLIN

SOFT_RST

PLL_MUTE

RESERVED

PUP

[7:0]

LOPWR_MODE

THRM_RATE

MCLKO_SEL

PLL_LOCK

TS_PDN

VREF_EN

PLL_PDN

CLK_SEL

VREG_PDN

0x02 PDN_THRMSENS_ [7:0]

CTRL_1

THRM_MODE THRM_GO

0x03 PDN_CTRL2

0x04 PDN_CTRL3

[7:0] DAC08_PDN DAC07_PDN DAC06_PDN DAC05_PDN DAC04_PDN DAC03_PDN

[7:0] RESERVED DAC12_PDN DAC11_PDN

TEMP

DAC02_PDN DAC01_PDN 0x00 RW

DAC10_PDN DAC09_PDN 0x00 RW

0x05 THRM_TEMP_STAT [7:0]

0x00 R

0x06 DAC_CTRL0

0x07 DAC_CTRL1

0x08 DAC_CTRL2

0x09 DAC_MUTE1

0x0A DAC_MUTE2

0x0B DACMSTR_VOL

0x0C DAC01_VOL

0x0D DAC02_VOL

0x0E DAC03_VOL

0x0F DAC04_VOL

0x10 DAC05_VOL

0x11 DAC06_VOL

0x12 DAC07_VOL

0x13 DAC08_VOL

0x14 DAC09_VOL

0x15 DAC10_VOL

0x16 DAC11_VOL

0x17 DAC12_VOL

[7:0]

SDATA_FMT

SAI

LRCLK_MODE LRCLK_POL SAI_MSB

VREG_CTRL BCLK_TDMC DAC_POL

FS

MMUTE

0x01 RW

[7:0] BCLK_GEN

[7:0] RESERVED

RESERVED

BCLK_RATE

BCLK_EDGE SAI_MS

0x00 RW

AUTO_MUTE_EN DAC_OSR

DE_EMP_EN 0x06 RW

[7:0] DAC08_MUTE DAC07_MUTE DAC06_MUTE DAC05_MUTE DAC04_MUTE DAC03_MUTE

DAC02_MUTE DAC01_MUTE 0x00 RW

[7:0]

RESERVED

DAC12_MUTE DAC11_MUTE

DACMSTR_VOL

DAC10_MUTE DAC09_MUTE 0x00 RW

0x00 RW

[7:0]

DAC01_VOL

DAC02_VOL

DAC03_VOL

DAC04_VOL

DAC05_VOL

DAC06_VOL

DAC07_VOL

DAC08_VOL

DAC09_VOL

DAC10_VOL

DAC11_VOL

DAC12_VOL

0x00 RW

[7:0]

0x00 RW

[7:0]

0x00 RW

[7:0]

0x00 RW

[7:0]

0x00 RW

[7:0]

0x00 RW

[7:0]

0x00 RW

[7:0]

0x00 RW

[7:0]

0x00 RW

[7:0]

0x00 RW

[7:0]

0x00 RW

[7:0]

0x00 RW

0x1C CM_SEL_PAD_

STRGTH

[7:0] RESERVED

RESERVED PAD_DRV

RESERVED

0x02 RW

0x1D DAC_POWER1

0x1E DAC_POWER2

0x1F DAC_POWER3

[7:0]

DAC04_POWER

DAC03_POWER

DAC02_POWER

DAC01_POWER

0xAA RW

DAC08_POWER

DAC12_POWER

DAC07_POWER

DAC11_POWER

DAC06_POWER

DAC10_POWER

DAC05_POWER

DAC09_POWER

Rev. A | Page 24 of 48

Data Sheet

ADAU1962

REGISTER DETAILS

PLL AND CLOCK CONTROL 0 REGISTER

Address: 0x00, Reset: 0x00, Name: PLL_CLK_CTRL0

Table 25. Bit Descriptions for PLL_CLK_CTRL0

Bit No. Bit Name

Settings

Description

Reset

Access

[7:6]

PLLIN

PLL Input Select. Selects MCLKI/XTALI or DLRCLK pins as the input to the

PLL.

0x0

RW

00 MCLKI or XTALI.

01 DLRCLK.

10 Reserved.

11 Reserved.

[5:4]

XTAL_SET

SOFT_RST

XTAL Oscillator Setting. XTALO pin status.

00 XTAL Oscillator Enabled.

01 Reserved.

10 Reserved.

11 XTALO Off.

0x0

RW

3

Software Reset Control. This bit resets all circuitry inside the integrated

circuit, except I²C/SPI communications. All control registers are reset to

default values, except Register 0x00 and Register 0x01. The

PLL_CLK_CTRLx registers do not change state.

0

1

Normal Operation.

Device in Reset.

[2:1]

MCS

PUP

Master Clock Select. MCLKI/XTALI pin functionality (PLL active), master

clock rate setting. The following values are for the f_Srate range from

32 kHz to 48 kHz. See Table 12 for details when using other f_Sselections.

0x0

RW

00 256 × f_SMCLK (44.1 kHz or 48 kHz).

01 384 × f_SMCLK (44.1 kHz or 48 kHz).

10 512 × f_SMCLK (44.1 kHz or 48 kHz).

11 768 × f_SMCLK (44.1 kHz or 48 kHz).

0

Master Power-Up Control. This bit must be set to 1 as the first register

write to power up the IC.

0

1

Master Power-Down.

Master Power-Up.

Rev. A | Page 25 of 48

ADAU1962

Data Sheet

PLL AND CLOCK CONTROL 1 REGISTER

Address: 0x01, Reset: 0x2A, Name: PLL_CLK_CTRL1

Table 26. Bit Descriptions for PLL_CLK_CTRL1

Bit No. Bit Name

Settings

Description

Reset

Access

[7:6]

LOPWR_MODE

Global Power/Performance Adjust. These bits adjust the power consumption

and performance level for all 12 DAC channels simultaneously. See the

Digital-to-Analog Converters (DACS) section for more details.

0x0

RW

00 I²C register settings.

01 Reserved.

10 Low Power.

11 Lowest Power.

[5:4]

MCLKO_SEL

MCLKO Output Frequency. Frequency selection for MCLKO pin. See the

Clock Signals section for more details.

0x2

RW

00 MCLKO = 4 MHz to 6 MHz scaled by f_S.

01 MCLKO = 8 MHz to 12 MHz scaled by f_S.

10 MCLKO = Buffered MCLKI.

11 MCLKO Pin Disabled.

3

2

1

PLL_MUTE

PLL_LOCK

VREF_EN

PLL Automute Enable/Lock. This bit enables the PLL lock automute function.

0x1

0x0

0x1

RW

R

0

1

No DAC Automute.

DAC Automute on PLL Unlock.

PLL Lock Indicator.

PLL Not Locked.

0

1

PLL Locked.

Internal Voltage Reference Enable. The internal voltage reference powers

the common mode for the ADAU1962. Disabling this bit allows the user to

drive the CM pin with an outside voltage source.

RW

0

1

Disabled.

Enabled.

0

CLK_SEL

DAC Clock Select. Selects PLL or direct master clock mode.

MCLK from PLL.

MCLK from MCLKI or XTALI.

0x0

RW

0

1

Rev. A | Page 26 of 48

Data Sheet

ADAU1962

BLOCK POWER-DOWN AND THERMAL SENSOR CONTROL 1 REGISTER

Address: 0x02, Reset: 0xA0, Name: PDN_THRMSENS_CTRL_1

Table 27. Bit Descriptions for PDN_THRMSENS_CTRL_1

Bit No. Bit Name

Settings Description

Reset

Access

[7:6]

THRM_RATE

Conversion Time Interval. When THRM_MODE = 0, the THRM_RATE bits control the 0x2

RW

time interval between temperature conversions.

00 4 sec/Conversion.

01 0.5 sec/Conversion.

10 1 sec/Conversion.

11 2 sec/Conversion.

5

4

THRM_MODE

THRM_GO

Continuous vs. One Shot. This bit determines whether the temperature

conversions occur continuously or only when commanded. To perform one shot

temperature conversions, set this bit to 1.

Continuous Operation.

One Shot Mode.

0x1

0x0

RW

0

1

One Shot Conversion Mode. When in one shot conversion mode, THRM_MODE = 1,

the THRM_GO bit must be set to 0 followed by a write of 1. This sequence results

in a single temperature conversion. The temperature data is available 120 ms

after writing a 1 to this bit.

0

1

Reset.

Convert Temperature.

2

1

0

TS_PDN

Temperature Sensor Power-Down.

Temperature Sensor On.

Temperature Sensor Power-Down.

PLL Power-Down.

PLL Normal Operation.

PLL Power-Down.

0x0

RW

0

1

PLL_PDN

VREG_PDN

0

1

Voltage Regulator Power-Down.

Voltage Regulator Normal Operation.

Voltage Regulator Power-Down.

0

1

Rev. A | Page 27 of 48

ADAU1962

Data Sheet

POWER-DOWN CONTROL 2 REGISTER

Address: 0x03, Reset: 0x00, Name: PDN_CTRL2

Table 28. Bit Descriptions for PDN_CTRL2

Bit No. Bit Name

Settings

Description

Reset

Access

7

6

5

4

3

2

1

0

DAC08_PDN

DAC07_PDN

DAC06_PDN

DAC05_PDN

DAC04_PDN

DAC03_PDN

DAC02_PDN

DAC01_PDN

Channel 8 Power-Down

Normal Operation

Power-Down Channel 8

Channel 7 Power-Down

Normal Operation

Power-Down Channel 7

Channel 6 Power-Down

Normal Operation

Power-Down Channel 6

Channel 5 Power-Down

Normal Operation

Power-Down Channel 5

Channel 4 Power-Down

Normal Operation

Power-Down Channel 4

Channel 3 Power-Down

Normal Operation

Power-Down Channel 3

Channel 2 Power-Down

Normal Operation

Power-Down Channel 2

Channel 1 Power-Down

Normal Operation

0x0

RW

0

1

0x0

RW

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Power-Down Channel 1

Rev. A | Page 28 of 48

Data Sheet

ADAU1962

POWER-DOWN CONTROL 3 REGISTER

Address: 0x04, Reset: 0x00, Name: PDN_CTRL3

Table 29. Bit Descriptions for PDN_CTRL3

Bit No. Bit Name

Settings

Description

Reset

Access

3

2

1

0

DAC12_PDN

DAC11_PDN

DAC10_PDN

DAC09_PDN

Channel 12 Power-Down

Normal Operation

Power-Down Channel 12

Channel 11 Power-Down

Normal Operation

Power-Down Channel 11

Channel 10 Power-Down

Normal Operation

Power-Down Channel 10

Channel 9 Power-Down

Normal Operation

0x0

RW

0

1

0x0

RW

0

1

0

1

0

1

Power-Down Channel 9

THERMAL SENSOR TEMPERATURE READOUT REGISTER

Address: 0x05, Reset: 0x00, Name: THRM_TEMP_STAT

The thermal sensor temperature readout range is −60°C to +140°C with a 1°C step size. Read this register and convert the hexadecimal or

binary TEMP bit value into decimal form; then subtract 60 from this decimal conversion. The result is the temperature in degrees Celsius.

Table 30. Bit Descriptions for THRM_TEMP_STAT

Bit No. Bit Name Settings Description

Reset

Access

[7:0]

TEMP

Thermal Sensor Temperature Readout. −60°C to +140°C range, 1°C step size.

To convert the TEMP code to temperature, use the equation (TEMP − 60).

0x00

R

Rev. A | Page 29 of 48

ADAU1962

Data Sheet

DAC CONTROL 0 REGISTER

Address: 0x06, Reset: 0x01, Name: DAC_CTRL0

Table 31. Bit Descriptions for DAC_CTRL0

Bit No. Bit Name

Settings Description

Reset

Access

[7:6]

SDATA_FMT

SDATA Format. Only used when SAI = 000.

00 I²S = 1 BCLK Cycle Delay.

0x0

RW

01 Left Justified = 0 BCLK Cycle Delay.

10 Right Justified 24-Bit Data = 8 BCLK Cycle Delay.

11 Right Justified 16-Bit Data = 16 BCLK Cycle Delay.

[5:3]

SAI

Serial Audio Interface. When SAI = 000, the SDATA_FMT bits control the stereo

SDATA format.

0x0

RW

000 Stereo (I²S, left justified, right justified).

001 TDM2 = Octal Line.

010 TDM4 = Quad Line.

011 TDM8 = Dual Line.

100 TDM16 = Single Line (48 kHz).

101 Reserved.

110 Reserved.

111 Reserved.

[2:1]

FS

Sample Rate Select.

0x0

0x1

RW

00 32 kHz/44.1 kHz/48 kHz.

01 64 kHz/88.2 kHz/96 kHz.

10 128 kHz/176.4 kHz/192 kHz.

11 128 kHz/176.4 kHz/192 kHz Low Propagation Delay.

DAC Master Mute.

0

MMUTE

0

1

Normal Operation.

All Channels Muted.

Rev. A | Page 30 of 48

Data Sheet

ADAU1962

DAC CONTROL 1 REGISTER

Address: 0x07, Reset: 0x00, Name: DAC_CTRL1

Table 32. Bit Descriptions for DAC_CTRL1

Bit No. Bit Name

Settings Description

Reset

Access

7

BCLK_GEN

DBCLK Generation. When the PLL is locked to the DLRCLK pin, it is possible to

0x0

RW

run the ADAU1962 without an external bit clock.

Normal Operation—DBCLK.

Internal DBCLK Generation.

0

1

6

5

4

2

LRCLK_MODE

LRCLK_POL

SAI_MSB

DLRCLK Mode Select. Only valid for TDM modes.

50% Duty Cycle DLRCLK.

Pulse Mode.

0x0

RW

0

1

DLRCLK Polarity. Allows the swapping of data between channels.

Left/Odd Channels Are DLRCLK Low (Normal).

Left/Odd Channels Are DLRCLK High (Inverted).

MSB Position.

MSB First DSDATAx.

LSB First DSDATAx.

0

1

0

1

BCLK_RATE

DBCLK Rate. Number of bit clock cycles per channel slot. Used only for

generating bit clock in master mode operation (SAI_MS = 1).

0

1

32 Cycles per Frame.

16 Cycles per Frame.

1

0

BCLK_EDGE

SAI_MS

DBCLK Active Edge. Adjusts the polarity of the bit clock leading edge.

Latch in Rising Edge.

Latch in Falling Edge.

0x0

RW

0

1

Serial Interface Master. Both the DLRCLK and DBCLK pins become the master

when enabled.

0

1

DLRCLK/DBCLK Slave.

DLRCLK/DBCLK Master.

Rev. A | Page 31 of 48

ADAU1962

Data Sheet

DAC CONTROL 2 REGISTER

Address: 0x08, Reset: 0x06, Name: DAC_CTRL2

Table 33. Bit Descriptions for DAC_CTRL2

Bit No. Bit Name

Settings Description

Reset

Access

[6:5]

VREG_CTRL

Voltage Regulator Control. Selects the regulator output voltage.

0x0

RW

00 Regulator Output = 2.5 V.

01 Regulator Output = 2.75 V.

10 Regulator Output = 3.0 V.

11 Regulator Output = 3.3 V.

4

BCLK_TDMC

DBCLK Rate in TDM Mode. Number of bit clock cycles per channel slot when

in TDM mode.

0x0

RW

0

1

32 BCLK Cycles/Channel Slot.

16 BCLK Cycles/Channel Slot.

3

2

DAC_POL

DAC Output Polarity. This is a global switch of DAC polarity.

Noninverted DAC Output.

Inverted DAC Output.

0x0

0x1

RW

0

1

AUTO_MUTE_EN

Automute Enable. Automatically mutes the DACs when 1024 consecutive

zero input samples are received. This is independent per channel.

0

1

Auto-Zero Input Mute Disabled.

Auto-Zero Input Mute Enabled.

DAC Oversampling Rate (OSR). OSR selection.

256 × f_SDAC Oversampling.

128 × f_SDAC Oversampling.

De-Emphasis Enable.

1

0

DAC_OSR

0x1

0x0

RW

0

1

DE_EMP_EN

0

1

No De-Emphasis/Flat.

De-Emphasis Enabled.

Rev. A | Page 32 of 48

Data Sheet

ADAU1962

DAC INDIVIDUAL CHANNEL MUTES 1 REGISTER

Address: 0x09, Reset: 0x00, Name: DAC_MUTE1

Table 34. Bit Descriptions for DAC_MUTE1

Bit No. Bit Name

Settings

Description

Reset

Access

7

6

5

4

3

2

1

0

DAC08_MUTE

DAC8 Soft Mute

DAC8 Normal Operation

DAC8 Mute

0x0

RW

0

1

DAC07_MUTE

DAC06_MUTE

DAC05_MUTE

DAC04_MUTE

DAC03_MUTE

DAC02_MUTE

DAC01_MUTE

DAC7 Soft Mute

DAC7 Normal Operation

DAC7 Mute

0x0

RW

0

1

DAC6 Soft Mute

DAC6 Normal Operation

DAC6 Mute

0

1

DAC5 Soft Mute

DAC5 Normal Operation

DAC5 Mute

0

1

DAC4 Soft Mute

DAC4 Normal Operation

DAC4 Mute

0

1

DAC3 Soft Mute

DAC3 Normal Operation

DAC3 Mute

0

1

DAC2 Soft Mute

DAC2 Normal Operation

DAC2 Mute

0

1

DAC1 Soft Mute

DAC1 Normal Operation

DAC1 Mute

0

1

Rev. A | Page 33 of 48

ADAU1962

Data Sheet

DAC INDIVIDUAL CHANNEL MUTES 2 REGISTER

Address: 0x0A, Reset: 0x00, Name: DAC_MUTE2

Table 35. Bit Descriptions for DAC_MUTE2

Bit No. Bit Name

Settings

Description

Reset

Access

3

2

1

0

DAC12_MUTE

DAC12 Soft Mute

DAC12 Normal Operation

DAC12 Mute

0x0

RW

0

1

DAC11_MUTE

DAC10_MUTE

DAC09_MUTE

DAC11 Soft Mute

DAC11 Normal Operation

DAC11 Mute

0x0

RW

0

1

DAC10 Soft Mute

DAC10 Normal Operation

DAC10 Mute

0

1

DAC9 Soft Mute

0

1

DAC9 Normal Operation

DAC9 Mute

Rev. A | Page 34 of 48

Data Sheet

ADAU1962

MASTER VOLUME CONTROL REGISTER

Address: 0x0B, Reset: 0x00, Name: DACMSTR_VOL

Table 36. Bit Descriptions for DACMSTR_VOL

Bit No. Bit Name

Settings

Description

Reset Access

[7:0] DACMSTR_VOL

Master Volume Control. Each 1-bit step corresponds to a 0.375 dB change in

volume. See Table 53 for a complete list of the volume settings.

0x00

RW

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

DAC1 VOLUME CONTROL REGISTER

Address: 0x0C, Reset: 0x00, Name: DAC01_VOL

Table 37. Bit Descriptions for DAC01_VOL

Bit No. Bit Name

Settings

Description

Reset Access

0x00 RW

[7:0] DAC01_VOL

DAC Volume Control Channel 1. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

Rev. A | Page 35 of 48

ADAU1962

Data Sheet

DAC2 VOLUME CONTROL REGISTER

Address: 0x0D, Reset: 0x00, Name: DAC02_VOL

Table 38. Bit Descriptions for DAC02_VOL

Bit No. Bit Name

Settings

Description

Reset Access

[7:0] DAC02_VOL

DAC Volume Control Channel 2. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

0x00

RW

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

DAC3 VOLUME CONTROL REGISTER

Address: 0x0E, Reset: 0x00, Name: DAC03_VOL

Table 39. Bit Descriptions for DAC03_VOL

Bit No. Bit Name

Settings

Description

Reset Access

0x00 RW

[7:0] DAC03_VOL

DAC Volume Control Channel 3. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

Rev. A | Page 36 of 48

Data Sheet

ADAU1962

DAC4 VOLUME CONTROL REGISTER

Address: 0x0F, Reset: 0x00, Name: DAC04_VOL

Table 40. Bit Descriptions for DAC04_VOL

Bit No. Bit Name

Settings

Description

Reset Access

[7:0] DAC04_VOL

DAC Volume Control Channel 4. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

0x00

RW

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

DAC5 VOLUME CONTROL REGISTER

Address: 0x10, Reset: 0x00, Name: DAC05_VOL

Table 41. Bit Descriptions for DAC05_VOL

Bit No. Bit Name

Settings

Description

Reset Access

0x00 RW

[7:0] DAC05_VOL

DAC Volume Control Channel 5. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

Rev. A | Page 37 of 48

ADAU1962

Data Sheet

DAC6 VOLUME CONTROL REGISTER

Address: 0x11, Reset: 0x00, Name: DAC06_VOL

Table 42. Bit Descriptions for DAC06_VOL

Bit No. Bit Name

Settings

Description

Reset Access

[7:0] DAC06_VOL

DAC Volume Control Channel 6. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

0x00

RW

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

DAC7 VOLUME CONTROL REGISTER

Address: 0x12, Reset: 0x00, Name: DAC07_VOL

Table 43. Bit Descriptions for DAC07_VOL

Bit No. Bit Name

Settings

Description

Reset Access

0x00 RW

[7:0] DAC07_VOL

DAC Volume Control Channel 7. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

Rev. A | Page 38 of 48

Data Sheet

ADAU1962

DAC8 VOLUME CONTROL REGISTER

Address: 0x13, Reset: 0x00, Name: DAC08_VOL

Table 44. Bit Descriptions for DAC08_VOL

Bit No. Bit Name

Settings

Description

Reset Access

[7:0] DAC08_VOL

DAC Volume Control Channel 8. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

0x00

RW

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

DAC9 VOLUME CONTROL REGISTER

Address: 0x14, Reset: 0x00, Name: DAC09_VOL

Table 45. Bit Descriptions for DAC09_VOL

Bit No. Bit Name

Settings

Description

Reset Access

0x00 RW

[7:0] DAC09_VOL

DAC Volume Control Channel 9. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

Rev. A | Page 39 of 48

ADAU1962

Data Sheet

DAC10 VOLUME CONTROL REGISTER

Address: 0x15, Reset: 0x00, Name: DAC10_VOL

Table 46. Bit Descriptions for DAC10_VOL

Bit No. Bit Name

Settings

Description

Reset Access

[7:0] DAC10_VOL

DAC Volume Control Channel 10. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

0x00

RW

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

DAC11 VOLUME CONTROL REGISTER

Address: 0x16, Reset: 0x00, Name: DAC11_VOL

Table 47. Bit Descriptions for DAC11_VOL

Bit No. Bit Name

Settings

Description

Reset Access

0x00 RW

[7:0] DAC11_VOL

DAC Volume Control Channel 11. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

Rev. A | Page 40 of 48

Data Sheet

ADAU1962

DAC12 VOLUME CONTROL REGISTER

Address: 0x17, Reset: 0x00, Name: DAC12_VOL

Table 48. Bit Descriptions for DAC12_VOL

Bit No. Bit Name

Settings

Description

Reset Access

[7:0] DAC12_VOL

DAC Volume Control Channel 12. Each 1-bit step corresponds to a 0.375 dB change

in volume. See Table 53 for a complete list of the volume settings.

0x00

RW

00000000 0 dB (default).

00000001 −0.375 dB.

00000010 −0.750 dB.

11111110 −95.250 dB.

11111111 −95.625 dB.

COMMON MODE AND PAD STRENGTH REGISTER

Address: 0x1C, Reset: 0x02, Name: CM_SEL_PAD_STRGTH

Table 49. Bit Descriptions for CM_SEL_PAD_STRGTH

Bit No.

Bit Name

Settings

Description

Reset

Access

5

PAD_DRV

Output Pad Drive Strength Control. Pad strength is stated for IOVDD = 5 V.

4 mA Drive for All Pads.

8 mA Drive for All Pads.

0x0

RW

0

1

Rev. A | Page 41 of 48

ADAU1962

Data Sheet

DAC POWER ADJUST 1 REGISTER

Address: 0x1D, Reset: 0xAA, Name: DAC_POWER1

Table 50. Bit Descriptions for DAC_POWER1

Bit No. Bit Name

Settings

Description

Reset

Access

[7:6]

[5:4]

[3:2]

[1:0]

DAC04_POWER

DAC Power Control Channel 4

00 Low Power

01 Lowest Power

10 Best Performance

11 Good Performance

DAC Power Control Channel 3

00 Low Power

0x2

RW

DAC03_POWER

DAC02_POWER

DAC01_POWER

0x2

RW

01 Lowest Power

10 Best Performance

11 Good Performance

DAC Power Control Channel 2

00 Low Power

01 Lowest Power

10 Best Performance

11 Good Performance

DAC Power Control Channel 1

00 Low Power

01 Lowest Power

10 Best Performance

11 Good Performance

Rev. A | Page 42 of 48

Data Sheet

ADAU1962

DAC POWER ADJUST 2 REGISTER

Address: 0x1E, Reset: 0xAA, Name: DAC_POWER2

Table 51. Bit Descriptions for DAC_POWER2

Bit No. Bit Name

Settings

Description

Reset

Access

[7:6]

[5:4]

[3:2]

[1:0]

DAC08_POWER

DAC Power Control Channel 8

00 Low Power

01 Lowest Power

10 Best Performance

11 Good Performance

DAC Power Control Channel 7

00 Low Power

0x2

RW

DAC07_POWER

DAC06_POWER

DAC05_POWER

0x2

RW

01 Lowest Power

10 Best Performance

11 Good Performance

DAC Power Control Channel 6

00 Low Power

01 Lowest Power

10 Best Performance

11 Good Performance

DAC Power Control Channel 5

00 Low Power

01 Lowest Power

10 Best Performance

11 Good Performance

Rev. A | Page 43 of 48

ADAU1962

Data Sheet

DAC POWER ADJUST 3 REGISTER

Address: 0x1F, Reset: 0xAA, Name: DAC_POWER3

Table 52. Bit Descriptions for DAC_POWER3

Bit No. Bit Name

Settings

Description

Reset

Access

[7:6]

[5:4]

[3:2]

[1:0]

DAC12_POWER

DAC Power Control Channel 12

00 Low Power

01 Lowest Power

10 Best Performance

11 Good Performance

DAC Power Control Channel 11

00 Low Power

0x2

RW

DAC11_POWER

DAC10_POWER

DAC09_POWER

0x2

RW

01 Lowest Power

10 Best Performance

11 Good Performance

DAC Power Control Channel 10

00 Low Power

01 Lowest Power

10 Best Performance

11 Good Performance

DAC Power Control Channel 9

00 Low Power

01 Lowest Power

10 Best Performance

11 Good Performance

Rev. A | Page 44 of 48

Data Sheet

ADAU1962

Table 53. Volume Settings

Binary Value Hex Value Volume Attenuation (dB)

00000000

00000001

00000010

00000011

00000100

00000101

00000110

00000111

00001000

00001001

00001010

00001011

00001100

00001101

00001110

00001111

00010000

00010001

00010010

00010011

00010100

00010101

00010110

00010111

00011000

00011001

00011010

00011011

00011100

00011101

00011110

00011111

00100000

00100001

00100010

00100011

00100100

00100101

00100110

00100111

00101000

00101001

00101010

00101011

00101100

00101101

00101110

00101111

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

0

00110000

00110001

00110010

00110011

00110100

00110101

00110110

00110111

00111000

00111001

00111010

00111011

00111100

00111101

00111110

00111111

01000000

01000001

01000010

01000011

01000100

01000101

01000110

01000111

01001000

01001001

01001010

01001011

01001100

01001101

01001110

01001111

01010000

01010001

01010010

01010011

01010100

01010101

01010110

01010111

01011000

01011001

01011010

01011011

01011100

01011101

01011110

01011111

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

4E

4F

50

51

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

5F

−18

−0.375

−0.75

−18.375

−18.75

−19.125

−19.5

−1.125

−1.5

−1.875

−2.25

−19.875

−20.25

−20.625

−21

−2.625

−3

−3.375

−3.75

−21.375

−21.75

−22.125

−22.5

−4.125

−4.5

−4.875

−5.25

−22.875

−23.25

−23.625

−24

−5.625

−6

−6.375

−6.75

−24.375

−24.75

−25.125

−25.5

−7.125

−7.5

−7.875

−8.25

−25.875

−26.25

−26.625

−27

−8.625

−9

−9.375

−9.75

−27.375

−27.75

−28.125

−28.5

−10.125

−10.5

−10.875

−11.25

−11.625

−12

−28.875

−29.25

−29.625

−30

−12.375

−12.75

−13.125

−13.5

−30.375

−30.75

−31.125

−31.5

−13.875

−14.25

−14.625

−15

−31.875

−32.25

−32.625

−33

−15.375

−15.75

−16.125

−16.5

−33.375

−33.75

−34.125

−34.5

−16.875

−17.25

−17.625

−34.875

−35.25

−35.625

Rev. A | Page 45 of 48

ADAU1962

Data Sheet

Binary Value Hex Value Volume Attenuation (dB)

01100000

01100001

01100010

01100011

01100100

01100101

01100110

01100111

01101000

01101001

01101010

01101011

01101100

01101101

01101110

01101111

01110000

01110001

01110010

01110011

01110100

01110101

01110110

01110111

01111000

01111001

01111010

01111011

01111100

01111101

01111110

01111111

10000000

10000001

10000010

10000011

10000100

10000101

10000110

10000111

10001000

10001001

10001010

10001011

10001100

10001101

10001110

10001111

60

61

62

63

64

65

66

67

68

69

6A

6B

6C

6D

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

80

81

82

83

84

85

86

87

88

89

8A

8B

8C

8D

8E

8F

−36

10010000

10010001

10010010

10010011

10010100

10010101

10010110

10010111

10011000

10011001

10011010

10011011

10011100

10011101

10011110

10011111

10100000

10100001

10100010

10100011

10100100

10100101

10100110

10100111

10101000

10101001

10101010

10101011

10101100

10101101

10101110

10101111

10110000

10110001

10110010

10110011

10110100

10110101

10110110

10110111

10111000

10111001

10111010

10111011

10111100

10111101

10111110

10111111

90

91

92

93

94

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

AA

AB

AC

AD

AE

AF

B0

B1

B2

B3

B4

B5

B6

B7

B8

B9

BA

BB

BC

BD

BE

BF

−54

−36.375

−36.75

−37.125

−37.5

−54.375

−54.75

−55.125

−55.5

−37.875

−38.25

−38.625

−39

−55.875

−56.25

−56.625

−57

−39.375

−39.75

−40.125

−40.5

−57.375

−57.75

−58.125

−58.5

−40.875

−41.25

−41.625

−42

−58.875

−59.25

−59.625

−60

−42.375

−42.75

−43.125

−43.5

−60.375

−60.75

−61.125

−61.5

−43.875

−44.25

−44.625

−45

−61.875

−62.25

−62.625

−63

−45.375

−45.75

−46.125

−46.5

−63.375

−63.75

−64.125

−64.5

−46.875

−47.25

−47.625

−48

−64.875

−65.25

−65.625

−66

−48.375

−48.75

−49.125

−49.5

−66.375

−66.75

−67.125

−67.5

−49.875

−50.25

−50.625

−51

−67.875

−68.25

−68.625

−69

−51.375

−51.75

−52.125

−52.5

−69.375

−69.75

−70.125

−70.5

−52.875

−53.25

−53.625

−70.875

−71.25

−71.625

Rev. A | Page 46 of 48

Data Sheet

ADAU1962

Binary Value Hex Value Volume Attenuation (dB)

11000000

11000001

11000010

11000011

11000100

11000101

11000110

11000111

11001000

11001001

11001010

11001011

11001100

11001101

11001110

11001111

11010000

11010001

11010010

11010011

11010100

11010101

11010110

11010111

11011000

11011001

11011010

11011011

11011100

11011101

11011110

11011111

C0

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

−72

11100000

11100001

11100010

11100011

11100100

11100101

11100110

11100111

11101000

11101001

11101010

11101011

11101100

11101101

11101110

11101111

11110000

11110001

11110010

11110011

11110100

11110101

11110110

11110111

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

E0

E1

E2

E3

E4

E5

E6

E7

E8

E9

EA

EB

EC

ED

EE

EF

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

FA

FB

FC

FD

FE

FF

−84

−72.375

−72.75

−73.125

−73.5

−84.375

−84.75

−85.125

−85.5

−73.875

−74.25

−74.625

−75

−85.875

−86.25

−86.625

−87

−75.375

−75.75

−76.125

−76.5

−87.375

−87.75

−88.125

−88.5

−76.875

−77.25

−77.625

−78

−88.875

−89.25

−89.625

−90

−78.375

−78.75

−79.125

−79.5

−90.375

−90.75

−91.125

−91.5

−79.875

−80.25

−80.625

−81

−91.875

−92.25

−92.625

−93

−81.375

−81.75

−82.125

−82.5

−93.375

−93.75

−94.125

−94.5

−82.875

−83.25

−83.625

−94.875

−95.25

−95.625

Rev. A | Page 47 of 48

ADAU1962

Data Sheet

PACKAGING AND ORDERING INFORMATION

OUTLINE DIMENSIONS

16.20

16.00 SQ

15.80

0.75

1.60

0.60

MAX

0.45

61

80

1

60

PIN 1

14.20

14.00 SQ

13.80

TOP VIEW

(PINS DOWN)

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

0.10

COPLANARITY

20

41

0.15

0.05

40

21

SEATING

PLANE

VIEW A

0.65

0.38

0.32

0.22

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BEC

Figure 22. 80-Lead Low Profile Quad Flat Package [LQFP]

(ST-80-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2}

ADAU1962WBSTZ

ADAU1962WBSTZRL

EVAL-ADAU1962Z

Temperature Range

−40°C to +105°C

Package Description

Package Option

80-Lead LQFP

80-Lead LQFP, 13”Tape and Reel

Evaluation Board

ST-80-2

¹Z = RoHS Compliant Part.

²W = Qualified for Automotive Applications.

AUTOMOTIVE PRODUCTS

The ADAU1962W models are available with controlled manufacturing to support the quality and reliability requirements of automotive

applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers

should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in

automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to

obtain the specific Automotive Reliability reports for these models.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

www.analog.com/ADAU1962

D11862-0-3/16(A)

Rev. A | Page 48 of 48


型号：	ADAU1962
厂家：	ADI
描述：	12-Channel, High Performance Differential Output DAC
文件：	总48页 (文件大小：690K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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