ADDI7100BCPZRL [ADI]
Complete, 12-Bit, 45 MHz CCD Signal Processor; 完成后， 12位， 45 MHz的CCD信号处理器
| 型号： | ADDI7100BCPZRL |
| 厂家： | 
ADI |
| 描述： | Complete, 12-Bit, 45 MHz CCD Signal Processor |
| 文件： | 总20页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete, 12-Bit, 45 MHz
CCD Signal Processor
ADDI7100
FEATURES
GENERAL DESCRIPTION
Pin-compatible upgrade for the AD9945
45 MHz correlated double sampler (CDS) with variable gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
Low noise optical black clamp circuit
Preblanking function
12-bit, 45 MHz ADC
No missing codes guaranteed
3-wire serial digital interface
3 V single-supply operation
The ADDI7100 is a complete analog signal processor for charge-
coupled device (CCD) applications. It features a 45 MHz,
single-channel architecture designed to sample and condition
the outputs of interlaced and progressive scan area CCD arrays.
The signal chain for the ADDI7100 consists of a correlated double
sampler (CDS), a digitally controlled variable gain amplifier
(VGA), a black level clamp, and a 12-bit ADC.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input clock polarity, and power-down
modes. The ADDI7100 operates from a single 3 V power supply,
typically dissipates 125 mW, and is packaged in a space-saving,
32-lead LFCSP.
Space-saving, 32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
Digital still cameras
Digital video camcorders
PC cameras
Portable CCD imaging devices
CCTV cameras
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
PBLK
ADDI7100
DRVDD
DRVSS
BAND GAP
REFERENCE
−3dB, 0dB,
+3dB, +6dB
6dB TO 42dB
VGA
12
12-BIT
ADC
DOUT
D0 TO D11
CCDIN
CDS
CLP
10
AVDD
AVSS
CLPOB
CONTROL
REGISTERS
DVDD
DVSS
DIGITAL
INTERFACE
INTERNAL
TIMING
VD
SL
SCK
SDATA
SHP
SHD DATACLK
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.
ADDI7100
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology.................................................................................... 11
Circuit Description and Operation.............................................. 12
DC Restore .................................................................................. 12
Correlated Double Sampler (CDS) .......................................... 12
Optical Black Clamp.................................................................. 12
Analog-to-Digital Converter (ADC)....................................... 13
Variable Gain Amplifier (VGA) ............................................... 13
Digital Data Outputs.................................................................. 13
Applications Information.............................................................. 14
Initial Power-On Sequence ....................................................... 15
Grounding and Decoupling Recommendations.................... 15
Serial Interface Timing .................................................................. 16
Complete Register Listing ............................................................. 17
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
General Specifications ................................................................. 3
Digital Specifications ................................................................... 3
System Specifications................................................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Equivalent Input Circuits .............................................................. 10
REVISION HISTORY
6/10—Rev. B to Rev. C
Changes to 0x0D Description and 0xFF Description in
Table 8 .............................................................................................. 18
9/09—Rev. A. to Rev. B
Changes to Features Section............................................................ 1
Changed Power-Down Mode to Full Standby Mode, Table 1 .... 3
Moved Timing Diagrams Section .................................................. 5
Changes to Table 4, Figure 3, and Figure 4 ................................... 5
Changes to Figure 9 Caption......................................................... 10
Changes to Optical Black Clamp Section.................................... 12
Changes to Initial Power-On Sequence Section......................... 15
Changes to Figure 16...................................................................... 16
Changes to Table 8.......................................................................... 17
2/09—Rev. 0 to Rev. A
Changes to Serial Interface Timing Section................................ 16
Changes to Figure 16 and Figure 17............................................. 16
10/08—Revision 0: Initial Version
Rev. C | Page 2 of 20
ADDI7100
SPECIFICATIONS
GENERAL SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 45 MHz, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
TEMPERATURE RANGE
Operating
Storage
−25
−65
+85
+150
°C
°C
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver
POWER CONSUMPTION
Normal Operation
Full Standby Mode
MAXIMUM CLOCK RATE
2.7
3.6
V
125
1
mW
mW
MHz
45
DIGITAL SPECIFICATIONS
DRVDD = DVDD = 2.7 V, CL = 20 pF, unless otherwise noted.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.1
V
V
μA
μA
pF
0.6
10
10
10
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA
Low Level Output Voltage, IOL = 2 mA
VOH
VOL
2.2
V
V
0.5
Rev. C | Page 3 of 20
ADDI7100
SYSTEM SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 45 MHz, unless otherwise noted.
Table 3.
Parameter
Test Conditions/Comments
Input characteristics definition1
Min
Typ
Max
Unit
CDS
Allowable CCD Reset Transient
CDS Gain Accuracy
−3 dB CDS Gain
0 dB CDS Gain
+3 dB CDS Gain
0.5
1.2
V
VGA gain = 6 dB (Code 15, default value)
Default setting
−2.45
5.40
8.65
−2.95
5.90
9.15
−3.45
6.40
9.65
dB
dB
dB
dB
+6 dB CDS Gain
11.10
11.60
12.10
Maximum Input Range Before Saturation
0 dB CDS Gain
−3 dB CDS Gain
Default setting
1.0
1.4
0.5
V p-p
V p-p
V p-p
+6 dB CDS Gain
Maximum CCD Black Pixel Amplitude
0 dB CDS Gain
+6 dB CDS Gain
Positive offset definition1
Default setting
−100
−50
+200
+100
mV
mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
1024
Guaranteed
Steps
Minimum Gain (VGA Code 15)
Maximum Gain (VGA Code 1023)
See Figure 13 for VGA curve
See Variable Gain Amplifier (VGA)
section for VGA gain equation
6.0
42.0
dB
dB
BLACK LEVEL CLAMP MEASURED AT ADC OUTPUT
Clamp Level Resolution
Clamp Level
2048
Steps
Measured at ADC output
Minimum Clamp Level (Code 0)
Maximum Clamp Level (Code 1023)
ADC
0
511
LSB
LSB
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
VOLTAGE REFERENCE
12
−1.0
Bits
LSB
0.5
Guaranteed
2.0
V
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code 15)
Maximum Gain (VGA Code 1023)
Peak Nonlinearity, 1 V Input Signal
Total Output Noise
2.0
1.0
V
V
Specifications include entire signal chain
6 dB total gain (default CDS, VGA)
5.4
41.4
5.9
41.9
0.1
0.8
45
6.4
42.4
dB
dB
%
LSB rms
dB
6 dB total gain (default CDS, VGA)
AC grounded input, 6 dB total gain
Measured with step change on supply
Power Supply Rejection (PSR)
1 Input signal characteristics are defined as shown in Figure 2.
500mV TYP
RESET TRANSIENT
100mV TYP
1V TYP
INPUT SIGNAL RANGE
OPTICAL BLACK PIXEL
Figure 2.
Rev. C | Page 4 of 20
ADDI7100
TIMING SPECIFICATIONS
CL = 20 pF, fSAMP = 45 MHz, unless otherwise noted. See Figure 3, Figure 4, and Figure 16.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK High/Low Pulse Width
SHP Pulse Width
SHD Pulse Width
CLPOB Pulse Width1
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
SHD Rising Edge to SHP Rising Edge
SHD Rising Edge to SHP Falling Edge
Internal Clock Delay
tCONV
tADC
tSHP
22
9
ns
ns
ns
ns
Pixels
ns
ns
ns
ns
11
5.5
5.5
20
5.5
11
11
5.5
4
tSHD
2
tS3
tS1
tS2
tS4
tID
9
9
tCONV − tS2
tCONV − tS1
ns
DATA OUTPUTS
Output Delay
Pipeline Delay
tOD
15
15
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency (Must Not Exceed Pixel Rate)
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Rising Edge to SDATA Valid Hold
fSCLK
tLS
tLH
tDS
tDH
40
10
10
10
10
MHz
ns
ns
ns
ns
1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Timing Diagrams
CCD
SIGNAL
(CCDIN)
PIXEL N
PIXEL
N + 1
PIXEL
N + 2
PIXEL
N + 14
PIXEL
N + 15
tID
tID
SHP
tS4
tS2
tS3
tS1
tCONV
SHD
DATACLK
tOD
N – 15
OUTPUT
DATA
N – 14
N – 13
N – 1
N
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING (ACTIVE) EDGE IS NEAR THE SHP OR SHD RISING
(ACTIVE) EDGE. THE BEST LOCATION FOR LOWEST NOISE WILL BE SYSTEM DEPENDENT.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
Figure 3. CCD Sampling Timing (Default Polarity Settings)
Rev. C | Page 5 of 20
ADDI7100
HORIZONTAL
BLANKING
EFFECTIVE PIXELS
OPTICAL BLACK PIXELS
DUMMY PIXELS
EFFECTIVE PIXELS
CCD
SIGNAL
(CCDIN)
CLPOB
PBLK
ACTIVE
ACTIVE
OUTPUT
DATA
EFFECTIVE PIXEL DATA
OB PIXEL DATA
DUMMY BLACK
EFFECTIVE DATA
NOTES
1. CLPOB AND PBLK SHOULD BE ALIGNED WITH THE CCD SIGNAL INPUT (CCDIN).
CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.
2. PBLK SIGNAL IS OPTIONAL. KEEP THE PBLK PIN IN THE INACTIVE STATE IF NOT USED.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS FIFTEEN DATACLK CYCLES.
Figure 4. Typical Clamp Timing (Default Polarity Settings)
Rev. C | Page 6 of 20
ADDI7100
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
θJA is specified for a device with the exposed bottom pad
soldered to the circuit board ground.
Parameter
Rating
AVDD to AVSS
DVDD to DVSS
DRVDD to DRVSS
Digital Outputs to DRVSS
SHP, SHD, DATACLK to DVSS
CLPOB, PBLK to DVSS
SCK, SL, SDATA to DVSS
REFT, REFB, CCDIN to AVSS
Junction Temperature
Lead Temperature (10 sec)
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
150°C
Table 6. Thermal Resistance
Package Type
θJA
Unit
32-Lead LFCSP
27.7
°C/W
ESD CAUTION
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 7 of 20
ADDI7100
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D2
D3
D4
D5
D6
D7
D8
D9
1
2
3
4
5
6
7
8
24 REFB
23 REFT
22 CCDIN
21 AVSS
20 AVDD
19 SHD
PIN 1
INDICATOR
ADDI7100
TOP VIEW
(Not to Scale)
18 SHP
17 CLPOB
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED
PAD BE SOLDERED TO THE GROUND PLANE
OF THE PCB.
2. NC = NO CONNECT.
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1 to 10
11
Mnemonic
D2 to D11
DRVDD
DRVSS
DVDD
DATACLK
DVSS
Type1
DO
P
P
P
Description
Digital Data Outputs.
Digital Output Driver Supply.
Digital Output Driver Ground.
Digital Supply.
Digital Data Output Latch Clock.
Digital Supply Ground.
12
13
14
15
DI
P
16
17
18
19
20
21
PBLK
CLPOB
SHP
SHD
AVDD
AVSS
DI
DI
DI
DI
P
Preblanking Clock Input.
Black Level Clamp Clock Input.
CDS Sampling Clock for CCD Reference Level.
CDS Sampling Clock for CCD Data Level.
Analog Supply.
P
Analog Ground.
22
23
24
25
26
27
28
CCDIN
REFT
REFB
SL
SDATA
SCK
AI
AO
AO
DI
DI
DI
DI
Analog Input for CCD Signal.
ADC Top Reference Voltage Decoupling.
ADC Bottom Reference Voltage Decoupling.
Serial Digital Interface Load Pulse.
Serial Digital Interface Data Input.
Serial Digital Interface Clock Input.
VD
Vertical Sync Input. Controls the update time of VD-updated registers. If this pin is not
needed, it should be tied to GND.
29, 30
31, 32
NC
D0, D1
NC
DO
Not Internally Connected.
Digital Data Output.
1 AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
Rev. C | Page 8 of 20
ADDI7100
TYPICAL PERFORMANCE CHARACTERISTICS
3
2
200
180
160
1
3.6V
140
120
3.0V
0
–1
–2
–3
–4
–5
100
2.7V
80
60
40
20
0
1
523
1045
1567
2089
2611
3133
3655
10
22
36
45
262
784 1306
1828
2350
2872
3394
3916
SAMPLE RATE (MHz)
CODE
Figure 8. Typical INL Performance
Figure 6. Power vs. Sample Rate
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
1
539
1077
808 1346
1615
2153
2691
3229
3767
4036
270
1884
2422
2960
3498
CODE
Figure 7. Typical DNL Performance
Rev. C | Page 9 of 20
ADDI7100
EQUIVALENT INPUT CIRCUITS
DVDD
AVDD
330Ω
60Ω
INPUT
DVSS
AVSS
AVSS
Figure 11. CCDIN (Pin 22)
Figure 9. Digital Inputs
SHP, SHD, DATACLK, CLPOB, PBLK, SCK, SL, SDATA, and VD
DRVDD
DVDD
DATA
THREE-
STATE
D[0:11]
DVSS
DRVSS
Figure 10. Data Outputs
Rev. C | Page 10 of 20
ADDI7100
TERMINOLOGY
Differential Nonlinearity (DNL)
Power Supply Rejection (PSR)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Therefore,
every code must have a finite width. No missing codes guaranteed
to 12-bit resolution indicates that all 4096 codes, respectively,
must be present over all operating conditions.
PSR is measured with a step change applied to the supply pins.
This represents a very high frequency disturbance on the power
supply of the ADDI7100. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
Peak Nonlinearity
Internal Delay for SHP/SHD
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the ADDI7100 from a true
straight line. The point used as zero scale occurs 0.5 LSB before
the first code transition. Positive full scale is defined as a level
that is 1.5 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of
the 2 V ADC full-scale signal. The input signal is always gained
appropriately to fill the full-scale range of the ADC.
The internal delay (also called aperture delay) is the time delay
that occurs from the time a sampling edge is applied to the
ADDI7100 until the actual sample of the input signal is held.
Both SHP and SHD sample the input signal during the transi-
tion from low to high; therefore, the internal delay is measured
from the rising edge of each clock to the instant that the actual
internal sample is taken.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSBs and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
1 LSB = (ADC Full Scale/2N codes)
where N is the bit resolution of the ADC. For example, 1 LSB of
the ADDI7100 is 0.5 mV.
Rev. C | Page 11 of 20
ADDI7100
CIRCUIT DESCRIPTION AND OPERATION
DC RESTORE
DATACLK
SHP
INTERNAL
PBLK
DCBYP
V
REF
–3dB, 0dB,
+3dB, +6dB
6dB TO 42dB
VGA
2V FULL SCALE
0.1µF
12
CCDIN
DATA
OUTPUT
LATCH
DOUT
D0 TO D11
12-BIT
ADC
CDS
CLPOB
PBLK
OPTICAL BLACK
CLAMP
SHP
SHD
DAC
10
CLPOB
DIGITAL
FILTERING
BLANK TO
ZERO OR
CLAMP LEVEL
VGA GAIN
REGISTER
11
CLAMP LEVEL
REGISTER
Figure 12. CCD Mode Block Diagram
The ADDI7100 signal processing chain is shown in Figure 12.
Each processing step is essential for achieving a high quality
image from the raw CCD pixel data.
OPTICAL BLACK CLAMP
The optical black clamp loop removes residual offsets in the
signal chain and tracks low frequency variations in the CCD
black level. During the optical black (shielded) pixel interval
on each line, the ADC output is compared with the fixed black
level reference selected by the user in the clamp level register
(Address 0x04). The resulting error signal is filtered to reduce
noise, and the correction value is applied to the ADC input
through a DAC. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamping
is used during postprocessing, optical black clamping for the
ADDI7100 can be disabled using Address 0x00, Bit 2. When the
optical black clamp loop is disabled, the clamp level register can
still be used to provide programmable offset adjustment.
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This circuit restores the dc level of the CCD signal
to approximately 1.5 V, which is compatible with the 3 V supply
of the ADDI7100.
CORRELATED DOUBLE SAMPLER (CDS)
The CDS circuit samples each CCD pixel twice to extract video
information and to reject low frequency noise. The timing
shown in Figure 3 illustrates how the two CDS clocks, SHP and
SHD, are used to sample the reference level and the data level,
respectively, of the CCD signal. The CCD signal is sampled on
the rising edges of SHP and SHD. Placement of these two clock
signals is critical for achieving the best performance from the
CCD. An internal SHP/SHD delay (tID) of 4 ns is caused by
internal propagation delays.
Note that if the CLPOB is disabled, higher VGA gain settings
reduce the dynamic range because the uncorrected offset in the
signal path is amplified.
Horizontal timing is shown in Figure 4. Align the CLPOB pulse
with the optical black pixels of the CCD. It is recommended that
the CLPOB pulse be used during valid CCD dark pixels. It is
recommended that the CLPOB pulse should be 20 pixels wide
to minimize clamp noise. Shorter pulse widths can be used, but
the ability of the loop to track low frequency variations in the
black level is reduced.
Rev. C | Page 12 of 20
ADDI7100
ANALOG-TO-DIGITAL CONVERTER (ADC)
DIGITAL DATA OUTPUTS
The ADDI7100 uses a high performance ADC architecture
optimized for high speed and low power. Differential non-
linearity (DNL) performance is typically better than 0.5 LSB.
The ADC uses a 2 V full-scale input range.
By default, the digital output data is latched by the rising edge of
the DATACLK input. Output data timing is shown in Figure 3.
It is also possible to make the output data latch transparent,
immediately validating the data outputs from the ADC. Setting
the DOUTLATCH register (Address 0x01[5]) to 1 configures
the latch as transparent. The data outputs can also be disabled
by setting the DOUT_OFF register (Address 0x01[4]) to 1.
VARIABLE GAIN AMPLIFIER (VGA)
The VGA stage provides a gain range of 6 dB to 42 dB, pro-
grammable with 10-bit resolution through the serial digital
interface. The minimum gain of 6 dB is needed to match a 1 V
input signal with the ADC full-scale range of 2 V. A plot of the
VGA gain curve is shown in Figure 13.
VGA Gain (dB) = (VGA Code × 0.0358 dB) + 5.4 dB
where Code is in the range of 0 to 1023.
42
36
30
24
18
12
6
0
127
383
511
639
767
895
1023
255
VGA GAIN REGISTER MODE
Figure 13. VGA Gain Curve
Rev. C | Page 13 of 20
ADDI7100
APPLICATIONS INFORMATION
The ADDI7100 is a complete analog front-end (AFE) product
for digital still camera and camcorder applications. As shown in
Figure 14, the CCD image (pixel) data is buffered and sent to
the ADDI7100 analog input through a series input capacitor.
The ADDI7100 performs the dc restoration, CDS sampling,
gain adjustment, black level correction, and analog-to-digital
conversion. The digital output data of the ADDI7100 is then
processed by the image processing ASIC. The internal registers
of the ADDI7100—used to control gain, offset level, and other
functions—are programmed by the ASIC or by a microprocessor
through a 3-wire serial digital interface. A system timing generator
provides the clock signals for both the CCD and the AFE (see
Figure 14).
DIGITAL
OUTPUTS
ADDI7100
CCD
V
OUT
ADC
0.1µF
OUT
DIGITAL IMAGE
PROCESSING
ASIC
CCDIN
SERIAL
INTERFACE
REGISTER
DATA
BUFFER
CDS/CLAMP
TIMING
V-DRIVER
CCD
TIMING
TIMING
GENERATOR
Figure 14. System Applications Diagram
3
SERIAL
INTERFACE
VD OUTPUT FROM ASIC/DSP
(SHOULD BE GROUNDED IF NOT USED.)
D0
D1
32 31 30 29 28 27 26 25
1.0µF
1.0µF
24 REFB
23 REFT
22 CCDIN
D2
D3
D4
D5
D6
D7
D8
D9
1
2
3
4
5
6
7
8
PIN 1
IDENTIFIER
0.1µF
CCDIN
21 AVSS
20 AVDD
ADDI7100
TOP VIEW
(Not to Scale)
3V
ANALOG
SUPPLY
19 SHD
0.1µF
18 SHP
17 CLPOB
9
10 11 12 13 14 15 16
12
5
DATA
OUTPUTS
CLOCK
INPUTS
3V
3V
ANALOG
SUPPLY
DRIVER
SUPPLY
0.1µF
0.1µF
NC = NO CONNECT (NOT INTERNALLY CONNECTED, MAY BE TIED TO GROUND OR LEFT FLOATING).
Figure 15. Recommended Circuit Configuration for CCD Mode
Rev. C | Page 14 of 20
ADDI7100
A single clean power supply is recommended for the ADDI7100,
but a separate digital driver supply can be used for DRVDD
(Pin 11). Always decouple DRVDD to DRVSS (Pin 12), which
should be connected to the analog ground plane. The advantages
of using a separate digital driver supply include using a lower
voltage (2.7 V) to match levels with a 2.7 V ASIC, and reducing
digital power dissipation and potential noise coupling. If the
digital outputs must drive a load larger than 20 pF, buffering is
the recommended method to reduce digital code transition
noise. Alternatively, placing series resistors close to the digital
output pins may also help to reduce noise.
INITIAL POWER-ON SEQUENCE
After power-on, the ADDI7100 automatically resets all internal
registers to default values. Settling of the internal voltage refer-
ence takes approximately 1 ms to complete. During this time,
normal clock signals and serial write operations can take place,
but valid output data do not occur until the reference is fully
settled. When loading the desired register settings, the STARTUP
register (Address 0x05[1:0]) must be set to 0x3.
GROUNDING AND DECOUPLING
RECOMMENDATIONS
As shown in Figure 15, a single ground plane is recommended
for the ADDI7100. This ground plane should be as continuous
as possible to ensure that all analog decoupling capacitors
provide the lowest possible impedance path between the power
and bypass pins and their respective ground pins. Place all
decoupling capacitors as close as possible to the package pins.
Note that the exposed pad on the bottom of the package should
be soldered to the ground plane of the printed circuit board.
Rev. C | Page 15 of 20
ADDI7100
SERIAL INTERFACE TIMING
All ADDI7100 internal registers are accessed through a 3-wire
serial interface. Each register consists of an 8-bit address and
a 16-bit data-word. Both the address and the data-word are
written starting with the LSB. To write to each register, a 24-bit
operation is required, as shown in Figure 16. Although many
data-words are fewer than 16 bits wide, all 16 bits must be written
for each register. For example, if the data-word is only eight bits
wide, the upper eight bits are don’t care bits and must be filled
with zeros during the serial write operation. If fewer than 16 data
bits are written, the register is not updated with new data.
Figure 17 shows a more efficient way to write to the registers,
using the ADDI7100 address autoincrement capability. Using
this method, the lowest desired address is written first, followed
by multiple 16-bit data-words. Each data-word is automatically
written to the address of the next highest register. By eliminating
the need to write each address, faster register loading is achieved.
Continuous write operations can start with any register location.
8-BIT ADDRESS
16-BIT DATA
SDATA
SCK
A0
A1
A2
tDS
A4
A5
A6
A7
D0
D1
D2
D3
D13 D14 D15
A3
tDH
1
2
3
4
5
6
7
8
9
10
11
12
22
23
tLH
24
tLS
SL
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 24 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 16 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS LESS THAN 16 BITS, THEN ZEROS MUST BE USED TO COMPLETE THE 16-BIT
DATA LENGTH.
4. NEW DATA VALUES ARE UPDATED IN THE SPECIFIED REGISTER LOCATION AT DIFFERENT TIMES, DEPENDING ON
THE PARTICULAR REGISTER WRITTEN TO.
Figure 16. Serial Write Operation
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
SDATA
SCK
A0
A1
A2
A6
A7
D0
D1
D14 D15 D0
D1
D14 D15 D0
A3
D1
D2
42
43
1
2
3
4
7
8
9
10
23
24
25
26
39
40
41
SL
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
Figure 17. Continuous Serial Write Operation
Rev. C | Page 16 of 20
ADDI7100
COMPLETE REGISTER LISTING
Note that when an address contains fewer than 16 data bits, all remaining bits must be written as zeros.
Table 8. AFE
Data Default Update
Address Bits
Value
Type1
Name
Description
0x00
[1:0]
0
SCK
STANDBY
00: normal operation
01: reference standby
10: full standby
11: full standby
[2]
0x1
0
CLAMP_EN
FASTCLAMP
FASTUPDATE
PBLK_LVL
DCBYP
1: enable black clamp
0: disable black clamp
0: normal CLPOB settling
1: faster CLPOB settling
1: enable very fast clamping when CDS gain is changed
0: ignore CDS gain updates
0: blank to 0
[3]
[4]
0
[5]
0
1: blank to clamp level
0: normal dc restore operation
[6]
0
1: dc restore disabled during PBLK active
[8:7]
[10:9] 0x2
0x2
Test
Test
Test use only; must be set to 2
Test use only; must be set to 2
0x01
[0]
[1]
[2]
[3]
[4]
[5]
0
0
0
0
0
0
SCK
SHPD_POL
0: rising edge sample
1: falling edge sample
DATACLK_POL 0: rising edge triggered
1: falling edge triggered
CLP_POL
0: active low
1: active high
0: active low
1: active high
0: data outputs are driven
1: data outputs are disabled (high-Z)
0: retime data outputs with output latch (using DATACLK)
1: do not retime data outputs; output latch is transparent
1: gray encode ADC outputs
PBLK_POL
DOUT_OFF
DOUTLATCH
GRAY_EN
[6]
0
0x02
[2:0]
0x1
SCK/VD CDSGAIN
CDS gain setting:
0x0: −3 dB
0x1: 0 dB
0x2: +3 dB
0x3: +6 dB
0x03
0x04
0x05
[9:0]
0x0F
SCK/VD VGAGAIN
VGA gain, 6 dB to 42 dB (0.0358 dB per step)
Optical black clamp level, 0 LSB to 511 LSB (0.25 LSB per step)
Must be set to 0x3 after power-up
[10:0] 0x1EC
SCK/VD CLAMPLEVEL
[1:0]
[3:2]
[2:0]
[3]
0
0
SCK
STARTUP
Test
Test use only; must be set to 0
0x06
0x6
0
SCK
Test
Test use only; must be set to 6
Test use only; must be set to 0
Test
[5:4]
[0]
0
Test
Test use only; must be set to 0
0x07
0x08
0x09
0x0A
0x0B
0x0C
0
SCK
SCK
SCK
SCK
SCK
SCK
Test
Test use only; must be set to 0
[11:0] 0xFFF
[11:0] 0xFFF
Test
Test use only; must be set to 0xFFF
Test use only; must be set to 0xFFF
Test use only; must be set to 0
Test
[0]
[0]
[0]
0
Test
0
SW_RST
1: software reset; automatically resets to 0 after software reset
0x1
OUTCONTROL Data output control:
0: make all outputs dc inactive
1: enable data outputs
Rev. C | Page 17 of 20
ADDI7100
Data Default Update
Address Bits
Value
Type1
Name
Description
0x0D
[0]
0
SCK
VD_POL
0: falling edge triggered
1: rising edge triggered
0x0E
[6:0]
0
SCK
REG_UPDATE
Set the appropriate bits high to enable VD update of the selected registers:
[0]: CDSGAIN (Register 0x02)
[1]: VGAGAIN (Register 0x03)
[2]: CLAMPLEVEL (Register 0x04)
[3]: test use only; must be set to 0
[4]: test use only; must be set to 0
[5]: test use only; must be set to 0
[6]: test use only; must be set to 0
0xFF
[0]
0
SCK
Test
Test use only; do not access
1 SCK = register is immediately updated when the 16th data bit (D15) is written. VD = register is updated at the VD falling edge.
Rev. C | Page 18 of 20
ADDI7100
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
0.80 MAX
0.65 TYP
3.50 REF
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADDI7100BCPZ
ADDI7100BCPZRL
Temperature Range
−25°C to +85°C
−25°C to +85°C
Package Description
Package Option
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
CP-32-2
CP-32-2
1 Z = RoHS Compliant Part.
Rev. C | Page 19 of 20
ADDI7100
NOTES
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07608-0-6/10(C)
Rev. C | Page 20 of 20
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