ADE7761ARS_技术文档

Energy Metering IC with On-Chip

Fault and Missing Neutral Detection

ADE7761

FEATURES

GENERAL DESCRIPTION

High accuracy active energy measurement IC, supports

IEC 687/61036

Less than 0.1% error over a dynamic range of 500 to 1

Supplies active power on the frequency outputs F1 and F2

High frequency output CF is intended for calibration and

supplies instantaneous active power

Continuous monitoring of the phase and neutral current

allows fault detection in 2-wire distribution systems

Current channels input level best suited for current

transformer sensors

Uses the larger of the two currents (phase or neutral) to

bill—even during a fault condition

Continuous monitoring of the voltage and current inputs

allows missing neutral detection

Uses one current input (phase or neutral) to bill when

missing neutral is detected

The ADE7761 is a high accuracy, fault tolerant, electrical energy

measurement IC intended for use with 2-wire distribution

systems. The part specifications surpass the accuracy require-

ments as quoted in the IEC61036 standard.

The only analog circuitry used on the ADE7761 is in the ADCs

and reference circuit. All other signal processing (such as multi-

plication and filtering) is carried out in the digital domain. This

approach provides superior stability and accuracy over extremes

in environmental conditions and over time.

The ADE7761 incorporates a fault detection scheme similar to

the ADE7751 by continuously monitoring both the phase and

neutral currents. A fault is indicated when these currents differ

by more than 6.25%.

Two logic outputs (FAULT and REVP) can be used to indicate

a potential miswiring, fault, or missing neutral condition

(continued on Page 3)

Direct drive for electromechanical counters and 2-phase

stepper motors (F1 and F2)

Proprietary ADCs and DSP provide high accuracy over large

variations in environmental conditions and time

Reference 2.5 V 8% (drift 30 ppm/°C typical) with external

overdrive capability

Single 5 V supply, low power

FUNCTIONAL BLOCK DIAGRAM

V

AGND

8

FAULT

15

DD

1

POWER

SUPPLY MONITOR

V

2

4

1A

1N

ADE7761

SIGNAL PROCESSING

BLOCK

ADC

HPF

A>B

LPF

B>A

A<>B

3

7

ZERO CROSSING

DETECTION

1B

MISSING NEUTRAL

GAIN ADJUST

MISCAL

6

5

V

2P

MISSING NEUTRAL

DETECTION

2N

4kΩ

2.5V

REFERENCE

INTERNAL

OSCILLATOR

DIGITAL-TO-FREQUENCY CONVERTER

9

14

17

10

11

12

16

18

19

20

REF

RCLKIN

DGND

SCF S1 S0 REVP CF F2 F1

IN/OUT

Figure 1.

Rev. A

.

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

ADE7761

TABLE OF CONTENTS

General Description......................................................................... 3

Active Power Calculation.......................................................... 15

Digital-to-Frequency Conversion............................................ 18

Transfer Function....................................................................... 18

Fault Detection ........................................................................... 19

Missing Neutral Mode............................................................... 20

Applications..................................................................................... 23

Interfacing to a Microcontroller for Energy Measurement.. 23

Selecting a Frequency for an Energy Meter Application....... 23

Negative Power Information..................................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

Disclaimer........................................................................................ 26

Specifications..................................................................................... 4

Timing Characteristics..................................................................... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Terminology ...................................................................................... 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Operation......................................................................................... 13

Power Supply Monitor ............................................................... 13

Analog Inputs.............................................................................. 13

Internal Oscillator ...................................................................... 14

Analog-to-Digital Conversion.................................................. 14

REVISION HISTORY

2/04—Changed from Rev. 0 to Rev. A.

Changes to Ordering Guide .......................................................... 25

1/04—Revision 0: Initial Version

Rev. A | Page 2 of 28

ADE7761

GENERAL DESCRIPTION

(continued from Page 1)

The ADE7761 incorporates a missing neutral detection scheme

by continuously monitoring the input voltage. When a missing

neutral condition is detected—no voltage input—the ADE7761

continues billing based on the active current signal (see the

Missing Neutral Mode section). The missing neutral condition

is indicated when the FAULT pin goes high.

The ADE7761 includes a power supply monitoring circuit on

the V_DDsupply pin. Internal phase matching circuitry ensures

that the voltage and current channels are matched. An internal

no-load threshold ensures that the ADE7761 does not exhibit

any creep when there is no load.

The ADE7761 supplies average active power information on the

low frequency outputs F1 and F2. The CF logic output gives

instantaneous active power information.

Rev. A | Page 3 of 28

ADE7761

SPECIFICATIONS

V_DD= 5 V 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, T_MINto T_MAX= –40°C to +85°C.

Table 1.

Parameter

Value

Unit

Test Conditions/Comments

ACCURACY¹

Measurement Error²

0.1

% of reading, typ

Over a dynamic range of 500 to 1

Phase Error between Channels

(PF = 0.8 Capacitive)

(PF = 0.5 Inductive)

0.05

Degrees, max

Phase lead 37°

Phase lag 60°

AC Power Supply Rejection²

Output Frequency Variation

DC Power Supply Rejection²

Output Frequency Variation

FAULT DETECTION^{2, 3}

0.01

%, typ

V_1A= V_1B= V_2P= 100 mV rms

See the Fault Detection section

Fault Detection Threshold

Inactive Input <> Active Input

Input Swap Threshold

Inactive Input <> Active Input

Accuracy Fault Mode Operation

V_1AActive, V_1B= AGND

V_1BActive, V_1A= AGND

Fault Detection Delay

6.25

%, typ

(V_1Aor V_1Bactive)

% of larger, typ

0.1

3

% of reading, typ

Seconds, typ

Over a dynamic range of 500 to 1

Swap Delay

3

Seconds, typ

MISSING NEUTRAL MODE^{2, 4}

Missing Neutral Detection Threshold

V_2P− V_2N

See the Missing Neutral Detection section

59.4

mV peak, min

Accuracy Missing Neutral Mode

V_1AActive, V_1B= V_2P= AGND

V_1BActive, V_1A= V_2P= AGND

Missing Neutral Detection Delay

ANALOG INPUTS

0.1

3

% of reading, typ

Seconds, typ

Over a dynamic range of 500 to 1

V_1A− V_1N, V_1B− V_1N, V_2P− V_2N

Differential input

Differential input MISCAL − V_2N

Maximum Signal Levels

660

400

7

10

4

mV peak, max

kΩ, min

kHz, typ

mV, max

Input Impedance (DC)

Bandwidth (−3 dB)

ADC Offset Error²

Uncalibrated error, see the Terminology section for details

External 2.5 V reference

Gain Error

%, typ

REFERENCE INPUT

REF_IN/OUTInput Voltage Range

2.7

2.3

4

V, max

V, min

kΩ, min

pF, max

2.5 V + 8%

2.5 V − 8%

Input Impedance

Input Capacitance

10

ON-CHIP REFERENCE

Reference Error

Temperature Coefficient

Current Source

200

30

20

mV, max

ppm/°C, typ

µA, min

ON-CHIP OSCILLATOR

Oscillator Frequency

Oscillator Frequency Tolerance

450

12

30

kHz

% of reading, typ

ppm/°C, typ

Temperature Coefficient

See footnotes on next page.

Rev. A | Page 4 of 28

ADE7761

Parameter

LOGIC INPUTS⁵

Value

Unit

Test Conditions/Comments

SCF, S1, and S0

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.4

0.8

3

V, min

V_DD= 5 V 5%

Typical 10 nA, V_IN= 0 V to V_DD

V, max

µA, max

pF, max

Input Capacitance, C_IN

10

LOGIC OUTPUTS⁵

CF, REVP, and FAULT

Output High Voltage, V_OH

Output Low Voltage, V_OH

F1 and F2

4

1

V, min

V, max

V_DD= 5 V 5%

Output High Voltage, V_OH

Output Low Voltage, V_OH

POWER SUPPLY

4

1

V, min

V, max

V_DD= 5 V 5%, I_SOURCE= 10 mA

V_DD= 5 V 5%, I_SINK= 10 mA

For specified performance

5 V − 5%

V_DD

4.75

5.25

4

V, min

V, max

mA, max

5 V + 5%

V_DD

¹See plots in the Typical Performance Characteristics section.

²See the Terminology section for explanation of specifications.

³See the Fault Detection section for explanation of fault detection functionality.

⁴See the Missing Neutral Detection section for explanation of missing neutral detection functionality.

⁵Sample tested during initial release and after any redesign or process change that may affect this parameter.

Rev. A | Page 5 of 28

ADE7761

TIMING CHARACTERISTICS

V_DD= 5 V 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, T_MINto T_MAX= –40°C to +85°C.

Sample tested during initial release and after any redesign or process change that may affect this parameter.

See Figure 2.

Table 2.

Parameter

Value

Unit

Test Conditions/Comments

1

t₁

120

See Table 6

1/2 t₂

ms

s

ms

s

F1 and F2 Pulse Width (Logic High).

t₂

t₃

t₄

Output Pulse Period. See the Transfer Function section.

Time between F1 Falling Edge and F2 Falling Edge.

CF Pulse Width (Logic High).

CF Pulse Period. See the Transfer Function section.

Minimum Time between F1 and F2 Pulse.

1

90

t₅

t₆

See Table 7

CLKIN/4

¹The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Transfer Function section.

t₁

F1

t₆

t₂

t₃

F2

t₄

t₅

CF

Figure 2. Timing Diagram for Frequency Outputs

Rev. A | Page 6 of 28

ADE7761

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 3.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto AGND

Analog Input Voltage to AGND

V_1AP, V_1BP, V_1N, V_2N, V_2P, MISCAL

−0.3 V to +7 V

−6 V to +6 V

Reference Input Voltage to AGND

Digital Input Voltage to DGND

Digital Output Voltage to DGND

Operating Temperature Range

Industrial

−0.3 V to V_DD+ 0.3 V

−40°C to +85°C

−65°C to +150°C

150°C

Storage Temperature Range

Junction Temperature

20-Lead SSOP, Power Dissipation

θ_JAThermal Impedance

Lead Temperature, Soldering

Vapor Phase (60 s)

450 mW

112°C/W

215°C

220°C

Infrared (15 s)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page 7 of 28

ADE7761

TERMINOLOGY

Measurement Error

For the dc PSR measurement, a reading at nominal supplies

(5 V) is taken. A second reading is obtained with the same input

signal levels when the power supplies are varied 5%. Any error

introduced is again expressed as a percentage of reading.

The error associated with the energy measurement made by the

ADE7761 is defined by the following formula:

Percentage Error =

ADC Offset Error

⎛

⎜

⎝

⎞

⎟

⎠

Energyregisteredby ADE7761 −True Energy

This refers to the dc offset associated with the analog inputs to

the ADCs. It means that with the analog inputs connected to

AGND, the ADCs still see a dc analog input signal. The magni-

tude of the offset depends on the input range selection (see the

Typical Performance Characteristics section). However, when

HPFs are switched on, the offset is removed from the current

channels and the power calculation is not affected by this offset.

×100%

True Energy

Phase Error between Channels

The high-pass filter (HPF) in the current channel has a phase

lead response. To offset this phase response and equalize the

phase response between channels, a phase correction network is

also placed in the current channel. The phase correction net-

work ensures a phase match between the current channels and

voltage channels to within 0.1° over a range of 45 Hz to 65 Hz

and 0.2° over a range 40 Hz to 1 kHz.

Gain Error

The gain error in the ADE7761 ADCs is defined as the differ-

ence between the measured output frequency (minus the offset)

and the ideal output frequency. The difference is expressed as a

percentage of the ideal frequency, which is obtained from the

transfer function (see the Transfer Function section).

Power Supply Rejection

This quantifies the ADE7761 measurement error as a percent-

age of reading when the power supplies are varied. For the ac

PSR measurement, a reading at nominal supplies (5 V) is taken.

A second reading is obtained with the same input signal levels

when an ac (175 mV rms/100 Hz) signal is introduced onto the

supplies. Any error introduced by this ac signal is expressed as a

percentage of reading (see the Measurement Error definition

above).

Rev. A | Page 8 of 28

ADE7761

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

1

2

20 F1

F2

DD

V

19

1A

1B

1N

2N

V

3

18 CF

V

4

17 DGND

ADE7761

TOP VIEW

(Not to Scale)

5

REVP

16

V

6

15 FAULT

2P

14

13

MISCAL

AGND

7

RCLKIN

INT

8

REF

9

12 S0

IN/OUT

SCF

S1

11

10

Figure 3. Pin Configuration (SSOP)

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

V_DD

Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7761. The supply

voltage should be maintained at 5 V 5% for specified operation. This pin should be decoupled with a

10 µF capacitor in parallel with a ceramic 100 nF capacitor.

2, 3

V_1A, V_1B

Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with

maximum differential input signal levels of 660 mV with respect to V_1Nfor specified operation. The

maximum signal level at these pins is 1 V with respect to AGND. Both inputs have internal ESD

protection circuitry, and an overvoltage of 6 V can also be sustained on these inputs without risk of

permanent damage.

4

V_1N

Negative Input Pin for Differential Voltage Inputs V_1Aand V_1B. The maximum signal level at this pin is

1 V with respect to AGND. The input has internal ESD protection circuitry, and an overvoltage of 6 V

can also be sustained on these inputs without risk of permanent damage. The input should be directly

connected to the burden resistor and held at a fixed potential,that is, AGND. See the Analog Inputs

section.

5

6

V_2N

Negative Input Pin for Differential Voltage Inputs V_2Pand MISCAL. The maximum signal level at this pin is

1 V with respect to AGND. The input has internal ESD protection circuitry, and an overvoltage of 6 V

can also be sustained on these inputs without risk of permanent damage. The input should be held at a

fixed potential, that is, AGND. See the Analog Inputs section.

Analog Inputs for Channel 2 (Voltage Channel). This input is fully differential voltage input with

maximum differential input signal levels of 660 mV with respect to V_2Nfor specified operation. The

maximum signal level at these pins is 1 V with respect to AGND. This input has internal ESD protection

circuitry, and an overvoltage of 6 V can also be sustained on these inputs without risk of permanent

damage.

V_2P

7

8

9

MISCAL

AGND

Analog Input for Missing Neutral Calibration. This pin can be used to calibrate the CF-F1-F2 frequencies

in the missing neutral condition. This input is fully differential voltage input with maximum differential

input signal levels of +660 mV with respect to V_2Nfor specified operation. The maximum signal level at

this pin is 1 V with respect to AGND. This input has internal ESD protection circuitry, and an

overvoltage of 6 V can also be sustained on these inputs without risk of permanent damage.

This pin provides the ground reference for the analog circuitry in the ADE7761, that is, ADCs and

reference. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the

ground reference for all analog circuitry such as antialiasing filters, and current and voltage transducers.

For good noise suppression, the analog ground plane should be connected only to the digital ground

plane at the DGND pin.

REF_IN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

2.5 V 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be

connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic

capacitor and 100 nF ceramic capacitor.

10

SCF

Select Calibration Frequency. This logic input is used to select the frequency on the calibration output

CF. Table 6 shows how the calibration frequencies are selected.

11, 12

S1, S0

These logic inputs are used to select one of four possible frequencies for the digital-to-frequency

conversion. This offers the designer greater flexibility when designing the energy meter. See the

Selecting a Frequency for an Energy Meter Application section.

Rev. A | Page 9 of 28

ADE7761

Pin No.

Mnemonic

Description

13

14

INT

RCLKIN

This pin is internally used and should be connected to DGND.

To enable the internal oscillator as a clock source on the chip, a precise low temperature drift resistor at

nominal value of 6.2 kΩ must be connected from this pin to DGND.

15

FAULT

This logic output goes active high when a fault or missing neutral condition occurs. A fault is defined as

a condition under which the signals on V_1Aand V_1Bdiffer by more than 6.25%. A missing neutral

condition is defined when the chip is powered up with no voltage at the input. The logic output is reset

to zero when a fault or missing neutral condition is no longer detected. See the Fault Detection section

and the Missing Neutral Mode section.

16

17

REVP

This logic output goes logic high when negative power is detected, that is, when the phase angle

between the voltage and current signals is greater than 90°. This output is not latched and is reset when

positive power is once again detected. The output goes high or low at the same time as a pulse is issued

on CF.

This pin provides the ground reference for the digital circuitry in the ADE7761, that is, multiplier, filters,

and digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The

digital ground plane is the ground reference for all digital circuitry such as counters (mechanical and

digital), MCUs, and indicator LEDs. For good noise suppression, the analog ground plane should be

connected only to the digital ground plane at the DGND pin.

DGND

18

CF

Calibration Frequency Logic Output. The CF logic output, active high, gives instantaneous active power

information. This output is intended to be used for operational and calibration purposes. See the Digital-

to-Frequency Conversion section.

19, 20

F2, F1

Low Frequency Logic Outputs. F1 and F2 supply average active power information. The logic outputs

can be used to directly drive electromechanical counters and 2-phase stepper motors.

Rev. A | Page 10 of 28

ADE7761

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

PF = 1

ON-CHIP REFERENCE

0.8

–40°C

5.25V

0.6

0.4

+25°C

0.2

0

5.00V

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

+85°C

4.75V

0.1

1.0

10.0

100.0

0.1

1.0

10.0

100.0

CURRENT (% of Full Scale)

Figure 4. Active Power Error as a Percentage of Reading with

Internal Reference

Figure 6. Active Power Error as a Percentage of Reading

over Power Supply with Internal Reference

1.5

2.0

1.5

PF = 0.5

ON-CHIP REFERENCE

1.0

0.5

1.0

–40°C; PF = 0.5

+85°C

0.5

0

+25°C; PF = 1

+25°C

0

–0.5

–1.0

–1.5

–2.0

–40°C

+25°C; PF = 0.5

+85°C; PF = 0.5

–0.5

–1.0

0.1

1.0

10.0

100.0

0.1

1.0

10.0

100.0

CURRENT (% of Full Scale)

Figure 5. Active Power Error as a Percentage of Reading over

Power Factor with Internal Reference

Figure 7. Ampere Hour Error as a Percentage of Reading in

Missing Neutral Mode with Internal Reference

Rev. A | Page 11 of 28

ADE7761

V

DD

+

10µF

100nF

1

PS2501-1

40A TO 80mA

I

2kΩ

18

CF

DD

1kΩ

1

4

2

V

1A

TO FREQ.

COUNTER

RB

33nF

ADE7761

2

3

1kΩ

33nF

1kΩ

2kΩ

3

4

5

V

1B

15

14

FAULT

RB

6.2kΩ

RCLKIN

1N

2N

RB = 18Ω

33nF

10kΩ

1kΩ

12

11

10

S0

S1

33nF

SCF

1MΩ

1kΩ 33nF

REF

6

9

V

IN/OUT

2P

+

220V

100nF

10µF

560kΩ

MISCAL

INT AGND DGND

13 17

100kΩ 33nF

8

Figure 8. Test Circuit for Performances Curves

Rev. A | Page 12 of 28

ADE7761

OPERATION

POWER SUPPLY MONITOR

Channel V2 (Voltage Channel)

The output of the line voltage transducer is connected to the

ADE7761 at this analog input. Channel V2 is a single-ended

voltage input. The maximum peak differential signal on

Channel 2 is 660 mV with respect to V_2N. Figure 11 shows the

maximum signal levels that can be connected to Channel 2.

The ADE7761 contains an on-chip power supply monitor. The

power supply (V_DD) is continuously monitored by the ADE7761.

If the supply is less than 4 V 5%, the ADE7761 goes into an

inactive state, that is, no energy is accumulated and the CF, F1,

and F2 outputs are disabled. This is useful to ensure correct

device operation at power-up and during power-down. The

power supply monitor has built-in hysteresis and filtering. This

gives a high degree of immunity to false triggering due to noisy

supplies.

V2

V

2P

+660mV + V

CM

V2

DIFFERENTIAL INPUT

±660mV MAX PEAK

V

2N

CM

V

COMMON MODE

±100mV MAX

CM

The power supply and decoupling for the part should be such

that the ripple at V_DDdoes not exceed 5 V 5% as specified for

normal operation.

–660mV + V

CM

Figure 11. Maximum Signal Levels, Channel 2

V

DD

The differential voltage V_2P–V_2Nmust be referenced to a

common mode (usually AGND). The analog inputs of the

ADE7761 can be driven with common-mode voltages of up to

100 mV with respect to AGND. However, the best results are

achieved using a common mode equal to AGND.

5V

4V

0V

TIME

MISCAL Input

ADE7761

REVP - FAULT - CF -

F1 - F2 OUTPUTS

INACTIVE

ACTIVE

INACTIVE

The input for the power calibration in missing neutral mode is

connected to the ADE7761 at this analog input. MISCAL is a

single-ended voltage input. It is recommended to use a dc signal

derived from the voltage reference to drive this pin. The maxi-

mum peak differential signal on MISCAL is +660 mV with

respect to V_2N. Figure 12 shows the maximum signal levels that

can be connected to the MISCAL pin.

Figure 9. On-Chip Power Supply Monitoring

ANALOG INPUTS

Channel V1 (Current Channel)

The voltage outputs from the current transducers are connected

to the ADE7761 here. Channel V1 has two voltage inputs, V_1A

and V_1B. These inputs are fully differential with respect to V_1N.

However, at any one time, only one is selected to perform the

power calculation (see the Fault Detection section).

MISCAL

+660mV + V

CM

DIFFERENTIAL INPUT

±660mV MAX PEAK

V

2N

V

COMMON MODE

±100mV MAX

V

CM

The maximum peak differential signal on V_1A–V_1Nand V_1B–V_1N

is 660 mV.

AGND

Figure 10 shows the maximum signal levels on V_1A, V_1B, and V_1N.

The differential voltage signal on the inputs must be referenced

to a common mode (usually AGND).

Figure 12. Maximum Signal Levels, MISCAL

The differential voltage MISCAL–V_2Nmust be referenced to a

common mode (usually AGND). The analog inputs of the

ADE7761 can be driven with common-mode voltages of up to

100 mV with respect to AGND. However, best results are

achieved using a common mode equal to AGND.

V

1A

DIFFERENTIAL INPUT A

±660mV MAX PEAK

V

, V

1A 1B

V1

+660mV + V

CM

V

1N

COMMON MODE

±100mV MAX

V

CM

V

CM

Typical Connection Diagrams

V1

AGND

Figure 13 shows a typical connection diagram for Channel V1.

The analog inputs are being used to monitor both the phase

and neutral currents. Because of the large potential difference

between the phase and neutral, two current transformers (CTs)

must be used to provide the isolation. Note that both CTs are

referenced to analog ground (AGND); the common-mode

–660mV + V

DIFFERENTIAL INPUT B

±660mV MAX PEAK

CM

V

1B

Figure 10. Maximum Signal Levels, Channel 1

Rev. A | Page 13 of 28

ADE7761

voltage, therefore, is 0 V. The CT turns ratio and burden resistor

(RB) are selected to give a peak differential voltage of 660 mV.

INTERNAL OSCILLATOR

The nominal internal oscillator frequency is 450 kHz when

used with the recommended R_OSCresistor value of 6.2 kΩ

between RCLKIN and DGND (see Figure 16).

Figure 14 shows two typical connections for Channel V2. The

first option uses a potential transformer (PT) to provide

complete isolation from the main voltage. In the second option,

the ADE7761 is biased around the neutral wire, and a resistor

divider is used to provide a voltage signal that is proportional to

the line voltage. Adjusting the ratio of RA and RB + VR is a

convenient way of carrying out a gain calibration on the meter.

The internal oscillator frequency is inversely proportional to the

value of this resistor. Although the internal oscillator operates

when used with a R_OSCresistor value between 5 kΩ and 12 kΩ, it

is recommended to choose a value within the range of the

nominal value.

Figure 15 shows a typical connection for MISCAL input. The

voltage reference input (REF_IN/OUT) is used as a dc reference to

set the MISCAL voltage. Adjusting the level of MISCAL to

calibrate the meter in missing neutral mode can be done by

changing the ratio of RC and RD + VR₁. When the internal

reference is used, the values of RC, RD, and VR₁must be chosen

to limit the current sourced by the internal reference sourcing

current to below the specified 20 µA. Therefore, because V_REF

internal = 2.5 V, RC + RD + VR₁> 600 kΩ.

The output frequencies on CF, F1, and F2 are directly propor-

tional to the internal oscillator frequency; therefore, the resistor

R_OSCmust have a low tolerance and low temperature drift. A low

tolerance resistor limits the variation of the internal oscillator

frequency. Small variation of the clock frequency and conse-

quently of the output frequencies from meter to meter

contributes to a smaller calibration range of the meter. A low

temperature drift resistor directly limits the variation of the

internal clock frequency over temperature. The stability of the

meter to external variation is then better ensured by design.

V

R

F

1A

CT

ADE7761

RB

C

F

IP

IN

AGND

4k

Ω

2.5V

INTERNAL

OSCILLATOR

V

1N

1B

REFERENCE

9

14

17

CT

REF

RCLKIN

DGND

IN/OUT

R

F

R

OSC

Figure 13. Typical Connection for Channel 1

Figure 16. Internal Oscillator Connection

V

R

2P

F

C

±660mV

AGND

F

V

ANALOG-TO-DIGITAL CONVERSION

2N

F

The analog-to-digital conversion in the ADE7761 is carried out

using second-order Σ-Δ ADCs. Figure 17 shows a first-order

(for simplicity) Σ-Δ ADC. The converter is made up of two

parts: the Σ-Δ modulator and the digital low-pass filter.

RA*

RB*

VR*

C

F

V

2P

MCLK

ANALOG

LOW-PASS FILTER

V

R

2N

F

LATCHED

COMPAR-

ATOR

INTEGRATOR

DIGITAL

LOW-PASS FILTER

C

T

R

*RB + VR = RF

∫

V

REF

1

24

C

Figure 14. Typical Connection for Channel 2

....10100101....

REF

IN/OUT

1-BIT DAC

RC

C

F

RD

Figure 17. First-Order Σ-∆ ADC

MISCAL

VR1

V

A Σ-Δ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. In the ADE7761, the sampling clock is equal to CLKIN.

The 1-bit DAC in the feedback loop is driven by the serial data

stream. The DAC output is subtracted from the input signal. If

the loop gain is high enough, the average value of the DAC

R

2N

F

C

F

Figure 15. Typical Connection for MISCAL

Rev. A | Page 14 of 28

ADE7761

output (and, therefore, the bit stream) approaches that of the

input signal level. For any given input value in a single sampling

interval, the data from the 1-bit ADC is virtually meaningless.

Only when a large number of samples are averaged is a

meaningful result obtained. This averaging is carried out in the

second part of the ADC, the digital low-pass filter. By averaging

a large number of bits from the modulator, the low-pass filter

can produce 24-bit data words that are proportional to the input

signal level.

Antialias Filter

Figure 18 also shows an analog low-pass filter (RC) on input to

the modulator. This filter is present to prevent aliasing. Aliasing

is an artifact of all sampled systems, which means that fre-

quency components in the input signal to the ADC that are

higher than half the sampling rate of the ADC appear in the

sampled signal frequency below half the sampling rate.

Figure 19 illustrates the effect.

In Figure 19, frequency components (arrows shown in black)

above half the sampling frequency (also known as the Nyquist

frequency), that is, 225 kHz, are imaged or folded back down

below 225 kHz (arrows shown in gray). This happens with all

ADCs no matter what the architecture. In the example shown,

only frequencies near the sampling frequency (450 kHz) move

into the band of interest for metering (40 Hz to 1 kHz). This

fact allows the use of a very simple low-pass filter to attenuate

these frequencies (near 250 kHz) and thereby prevent distortion

in the band of interest. A simple RC filter (single pole) with a

corner frequency of 10 kHz produces an attenuation of

approximately 33 dB at 450 kHz (see Figure 19). This is

sufficient to eliminate the effects of aliasing.

The Σ-Δ converter uses two techniques to achieve high

resolution from what is essentially a 1-bit conversion technique.

The first is oversampling, which means that the signal is

sampled at a rate (frequency) that is many times higher than the

bandwidth of interest. For example, the sampling rate in the

ADE7761 is CLKIN (450 kHz) and the band of interest is 40 Hz

to 1 kHz. Oversampling has the effect of spreading the

quantization noise (noise due to sampling) over a wider

bandwidth. With the noise spread more thinly over a wider

bandwidth, the quantization noise in the band of interest is

lowered (see Figure 18).

However, oversampling alone is not an efficient enough method

to improve the signal-to-noise ratio (SNR) in the band of inter-

est. For example, an oversampling ratio of 4 is required just to

increase the SNR by only 6 dB (1 bit). To keep the oversampling

ratio at a reasonable level, it is possible to shape the quantization

noise so that the majority of the noise lies at the higher frequen-

cies. This is what happens in the Σ-Δ modulator; the noise is

shaped by the integrator, which has a high-pass type response

for the quantization noise. The result is that most of the noise is

at the higher frequencies where it can be removed by the digital

low-pass filter. This noise shaping is also shown in Figure 18.

ANTIALIASING EFFECTS

SAMPLING

FREQUENCY

IMAGE

FREQUENCIES

0

1kHz

225kHz

450kHz

FREQUENCY (Hz)

Figure 19. ADC and Signal Processing in Current Channel or Voltage Channel

ANTIALIAS FILTER (RC)

DIGITAL FILTER

SAMPLING FREQUENCY

SHAPED NOISE

ACTIVE POWER CALCULATION

SIGNAL

NOISE

The ADCs digitize the voltage signals from the current and

voltage transducers. A high-pass filter in the current channel

removes any dc component from the current signal. This

eliminates any inaccuracies in the active power calculation due

to offsets in the voltage or current signals (see the HPF and

Offset Effects section).

0

1kHz

225kHz

FREQUENCY (Hz)

450kHz

HIGH RESOLUTION

SIGNAL

NOISE

OUTPUT FROM

DIGITAL LFP

The active power calculation is derived from the instantaneous

power signal. The instantaneous power signal is generated by a

direct multiplication of the current and voltage signals. To

extract the active power component (dc component), the

instantaneous power signal is low-pass filtered. Figure 20

illustrates the instantaneous active power signal and shows how

the active power information can be extracted by low-pass

filtering the instantaneous power signal. This scheme correctly

calculates active power for nonsinusoidal current and voltage

waveforms at all power factors. All signal processing is carried

out in the digital domain for superior stability over temperature

and time.

0

1kHz

225kHz

FREQUENCY (Hz)

450kHz

Figure 18. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

Rev. A | Page 15 of 28

ADE7761

INSTANTANEOUS

POWER SIGNAL

INSTANTANEOUS

ACTIVE POWER SIGNAL

The low frequency output of the ADE7761 is generated by

accumulating this active power information. This low frequency

inherently means a long accumulation time between output

pulses. The output frequency is, therefore, proportional to the

average active power. This average active power information can

in turn be accumulated (for example, by a counter) to generate

active energy information. Because of its high output frequency

and therefore shorter integration time, the CF output is propor-

tional to the instantaneous active power. This is useful for

system calibration purposes that would take place under steady

load conditions.

V × I

2

0V

CURRENT

VOLTAGE

INSTANTANEOUS

POWER SIGNAL

INSTANTANEOUS

ACTIVE POWER SIGNAL

DIGITAL-TO-

FREQUENCY

V × I

2

F1

F2

× cos(60°)

0V

CH1

CH2

ADC

HPF

MULTIPLIER

DIGITAL-TO-

FREQUENCY

LPF

VOLTAGE

CURRENT

CF

60°

Figure 21. Active Power Calculation over PF

INSTANTANEOUS

POWER SIGNAL –p(t)

INSTANTANEOUS

ACTIVE POWER SIGNAL

Nonsinusoidal Voltage and Current

V × I

p(t) = i(t).v(t)

WHERE:

The active power calculation method also holds true for

nonsinusoidal current and voltage waveforms. All voltage and

current waveforms in practical applications have some

harmonic content. Using the Fourier transform, instantaneous

voltage and current waveforms can be expressed in terms of

their harmonic content:

V × I

2

v(t) = V × cos(ϖt)

i(t) = I × cos(ϖt)

V × I

p(t) =

{1 + cos (2ϖt)}

2

TIME

Figure 20. Signal Processing Block Diagram

v(t) =V + 2 × ^∞V ×sin(hωt + α )

(1)

Power Factor Considerations

∑

O

h

The method used to extract the active power information from

the instantaneous power signal (by low-pass filtering) is still

valid even when the voltage and current signals are not in

phase. Figure 21 displays the unity power factor condition and

a displacement power factor (DPF = 0.5), that is, current signal

lagging the voltage by 60°. If one assumes that the voltage and

current waveforms are sinusoidal, the active power component

of the instantaneous power signal (dc term) is given by

h ≠0

where:

v(t) is the instantaneous voltage.

V_Ois the average value.

V_his the rms value of voltage harmonic h.

α_his the phase angle of the voltage harmonic.

∞

i(t) = I_O+ 2 × I ×sin(hωt +β )

(2)

(V × I/2) × cos(60°)

∑

h

h ≠0

This is the correct active power calculation.

where:

i(t) is the instantaneous current.

I_Ois the dc component.

I_his the rms value of current harmonic h.

β_his the phase angle of the current harmonic.

Rev. A | Page 16 of 28

ADE7761

Using Equations 1 and 2, the active power P can be expressed in

terms of its fundamental active power (P₁) and harmonic active

power (P_H):

DC COMPONENT (INCLUDING ERROR TERM)

IS EXTRACTED BY THE LPF FOR ACTIVE

POWER CALCULATION

V

× I

1

2

P = P₁+ P_H

where:

V

× I

1

0

1

P₁= V₁× I₁cos(Φ₁)

(3)

Φ₁= α₁−β₁

2v

FREQUENCY (RAD/S)

0v

and

Figure 22. Effect of Channel Offsets on the Active Power Calculation

P_H

=

^∞V ×I ×cos(Φ )

∑

0.30

0.25

0.20

0.15

h

h =2

(4)

Φ_h= α_h−β_h

As can be seen from Equation 4, a harmonic active power

component is generated for every harmonic, provided that

harmonic is present in both the voltage and current waveforms.

The power factor calculation has previously been shown to be

accurate in the case of a pure sinusoid; the harmonic active

power must, therefore, also correctly account for power factor,

because it is made up of a series of pure sinusoids.

0.10

0.05

0

–0.05

–0.10

Note that the input bandwidth of the analog inputs is 7 kHz

with the internal oscillator frequency of 450 kHz.

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (Hz)

HPF and Offset Effects

Figure 23. Phase Error between Channels (0 Hz to 1 kHz)

Equation 5 shows the effect of offsets on the active power

calculation. Figure 22 shows the effect of offsets on the active

power calculation in the frequency domain.

0.30

0.25

0.20

0.15

0.10

V(t)× I(t) =

(V₀+V₁× cos(ωt))×(I₀+ I₁× cos(ωt)) =

V₁× I₁

(5)

V₀× I₁+

+V₀× I₁× cos(ωt) +V₁× I₀× cos(ωt)

2

0.05

0

As can be seen from Equation 5 and Figure 22, an offset on

Channel 1 and Channel 2 contributes a dc component after

multiplication. Because this dc component is extracted by the

LPF and used to generate the active power information, the

offsets contribute a constant error to the active power calcula-

tion. This problem is easily avoided in the ADE7761 with the

HPF in Channel 1. By removing the offset from at least one

channel, no error component can be generated at dc by the

multiplication. Error terms at cos(ωt) are removed by the LPF

and the digital-to-frequency conversion (see the Digital-to-

Frequency Conversion section).

–0.05

–0.10

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 24. Phase Error between Channels (40 Hz to 70 Hz)

The HPF in Channel 1 has an associated phase response that is

compensated for on-chip. Figure 23 and Figure 24 show the

phase error between channels with the compensation network

activated. The ADE7761 is phase compensated up to 1 kHz as

shown, which ensures correct active harmonic power

calculation even at low power factors.

Rev. A | Page 17 of 28

ADE7761

The output frequency on CF can be up to 2048 times higher

than the frequency on F1 and F2. This higher output frequency

is generated by accumulating the instantaneous active power

signal over a much shorter time while converting it to a

frequency. This shorter accumulation period means less

averaging of the cos(2ωt) component. As a consequence, some

of this instantaneous power signal passes through the digital-to-

frequency conversion. This is not a problem in the application.

DIGITAL-TO-FREQUENCY CONVERSION

As previously described, the digital output of the low-pass filter

after multiplication contains the active power information.

However, because this LPF is not an ideal “brick wall” filter

implementation, the output signal also contains attenuated

components at the line frequency and its harmonics, that is,

cos(hωt), where h = 1, 2, 3, …, and so on. The magnitude

response of the filter is given by

Where CF is used for calibration purposes, the frequency

should be averaged by the frequency counter, which removes

any ripple. If CF is being used to measure energy, such as in a

microprocessor-based application, the CF output should also be

averaged to calculate power. Because the outputs F1 and F2

operate at a much lower frequency, a lot more averaging of the

instantaneous active power signal is carried out. The result is a

greatly attenuated sinusoidal content and a virtually ripple-free

frequency output.

1

H( f ) =

(6)

1 = ( f / 4.5Hz)²

For a line frequency of 50 Hz, this gives an attenuation of the 2ω

(100 Hz) component of approximately –26.9 dB. The dominat-

ing harmonic is at twice the line frequency, cos(2ωt), due to the

instantaneous power signal.

Figure 25 shows the instantaneous active power signal output of

the LPF, which still contains a significant amount of instantane-

ous power information, cos(2ωt). This signal is then passed to

the digital-to-frequency converter, where it is integrated

(accumulated) over time to produce an output frequency. This

accumulation of the signal suppresses or averages out any non-

dc components in the instantaneous active power signal. The

average value of a sinusoidal signal is zero. Therefore, the

frequency generated by the ADE7761 is proportional to the

average active power.

TRANSFER FUNCTION

Frequency Outputs F1 and F2

The ADE7761 calculates the product of two voltage signals (on

Channel 1 and Channel 2) and then low-pass filters this product

to extract active power information. This active power infor-

mation is then converted to a frequency. The frequency

information is output on F1 and F2 in the form of active high

pulses. The pulse rate at these outputs is relatively low, for

example, 0.34 Hz maximum for ac signals with S0 = S1 = 0 (see

Table 7). This means that the frequency at these outputs is

generated from active power information accumulated over a

relatively long period of time. The result is an output frequency

that is proportional to the average active power. The averaging

of the active power signal is implicit to the digital-to-frequency

conversion. The output frequency or pulse rate is related to the

input voltage signals by the following equation:

Figure 25 also shows the digital-to-frequency conversion for

steady load conditions: constant voltage and current. As can be

seen in Figure 25, the frequency output CF varies over time,

even under steady load conditions. This frequency variation is

primarily due to the cos(2ωt) component in the instantaneous

active power signal.

F1

5.70 × V1_rms× V2_rms× F₁₋₄

F₁− F₂Frequency =

(7)

2

V_REF

DIGITAL-TO-

FREQUENCY

F1

where:

F2

V

TIME

F₁− F₂Frequency is the output frequency on F1 and F2 (Hz).

V1_rmsis the differential rms voltage signal on Channel 1 (V).

V2_rmsis the differential rms voltage signal on Channel 2 (V).

MULTIPLIER

FOUT

DIGITAL-TO-

FREQUENCY

LPF

I

CF

LPF TO EXTRACT

ACTIVE POWER

(DC TERM)

V

_REFis the reference voltage (2.5 V 8%) (V).

_1–4is one of four possible frequencies selected by using the

logic inputs S0 and S1 (see Table 5).

F

TIME

0

ϖ

2ϖ

FREQUENCY (Rad/s)

INSTANTANEOUS ACTIVE POWER SIGNAL (FREQUENCY DOMAIN)

Figure 25. Active Power to Frequency Conversion

Rev. A | Page 18 of 28

ADE7761

Table 5. F_1–4Frequency Selection

Note that if the on-chip reference is used, actual output

frequencies may vary from device to device due to a reference

tolerance of 8%.

S1

S0

F_1–4(Hz)¹

1.72

OSC/CLKIN²

OSC/2¹⁸

0

1

3.44

OSC/2¹⁷

1

0

6.86

OSC/2¹⁶

OSC/2¹⁵

5.70× 0.66 × 0.66 × 1.72 Hz

F₁− F₂Frequency =

= 0.34 Hz

2 × 2 ×2.5²

1

13.7

¹Values are generated using the nominal frequency of 450 kHz.

²F_1–4are a binary fraction of the master clock and, therefore, vary with the

internal oscillator frequency (OSC).

CF Frequency = F₁− F₂× 64 = 22.0 Hz

Frequency Output CF

As can be seen from these two example calculations, the

maximum output frequency for ac inputs is always half of that

for dc input signals. Table 7 shows a complete listing of all

maximum output frequencies for ac signals.

The pulse output calibration frequency (CF) is intended for use

during calibration. The output pulse rate on CF can be up to

2048 times the pulse rate on F1 and F2. The lower the F_1–4

frequency selected, the higher the CF scaling. Table 6 shows

how the two frequencies are related, depending on the states of

the logic inputs S0, S1, and SCF. Because of its relatively high

pulse rate, the frequency at this logic output is proportional to

the instantaneous active power. As with F1 and F2, the

frequency is derived from the output of the low-pass filter after

multiplication. However, because the output frequency is high,

this active power information is accumulated over a much

shorter time. Therefore, less averaging is carried out in the

digital-to-frequency conversion. With much less averaging of

the active power signal, the CF output is much more responsive

to power fluctuations (see Figure 20).

Table 7. Maximum Output Frequency on CF, F1, and F2 for

AC Inputs

CF to

F1, F2 Maximum

SCF S1 S0 Frequency (Hz)

CF Maximum

Frequency (Hz)

F1

Ratio

1

0

1

0

1

0

1

0

1

0

1

0

1

0.34

0.68

1.36

2.72

43.52

21.76

43.52

21.76

43.52

21.76

43.52

5570

128

64

32

16

2048

Table 6. Relationship between CF and F1, F2 Frequency

Outputs

FAULT DETECTION

The ADE7761 incorporates a novel fault detection scheme that

warns of fault conditions and allows the ADE7761 to continue

accurate billing during a fault event. The ADE7761 does this by

continuously monitoring both the phase and neutral (return)

currents. A fault is indicated when these currents differ by more

than 6.25%. However, even during a fault, the output pulse rate

on F1 and F2 is generated using the larger of the two currents.

Because the ADE7761 looks for a difference between the voltage

signals on V_1Aand V_1B, it is important that both current trans-

ducers be closely matched.

SCF

S1

S0

F_1–4(Hz)

CF Frequency Output

128 × F1, F2

64 × F1, F2

1

0

1.72

1

0

1

3.44

64 × F1, F2

0

1

3.44

32 × F1, F2

1

0

6.86

32 × F1, F2

0

1

0

6.86

16 × F1, F2

1

13.7

16 × F1, F2

0

1

13.7

2048 × F1, F2

Example

On power-up, the output pulse rate of the ADE7761 is pro-

portional to the product of the voltage signals on V_1Aand

Channel 2. If there is a difference of greater than 6.25% between

In this example, if ac voltages of 660 mV peak are applied to

V1 and V2, then the expected output frequency on CF, F1, and

F2 is calculated as follows:

V_1Aand V_1Bon power-up, the fault indicator (FAULT) becomes

active after about 1 s. In addition, if V_1Bis greater than V_1A, the

ADE7761 selects V_1Bas the input. The fault detection is

automatically disabled when the voltage signal on Channel 1 is

less than 0.3% of the full-scale input range. This eliminates false

detection of a fault due to noise at light loads.

F

_1–4= 1.7 Hz, SCF = S1 = S0 = 0

V1_rms= rms of 660 mV peak ac = 0.66/√ V

2

V2_rms= rms of 660 mV peak ac = 0.66/√ V

2

V

_REF= 2.5 V (nominal reference value)

Rev. A | Page 19 of 28

ADE7761

Fault with Active Input Greater than Inactive Input

Calibration Concerns

If V_1Ais the active current input (that is, being used for billing),

and the voltage signal on V_1B(inactive input) falls below 93.75%

of V_1A, the fault indicator becomes active. Both analog inputs are

filtered and averaged to prevent false triggering of this logic

output. As a consequence of the filtering, there is a time delay of

approximately 3 s on the logic output FAULT after the fault

event. The FAULT logic output is independent of any activity on

outputs F1 or F2. Figure 26 shows one condition under which

FAULT becomes active. Because V_1Ais the active input and it is

still greater than V_1B, billing is maintained on V_1A, that is, no

swap to the V_1Binput occurs. V_1Aremains the active input.

Typically, when a meter is being calibrated, the voltage and

current circuits are separated as shown in Figure 28. This means

that current passes through only the phase or neutral circuit.

Figure 28 shows current being passed through the phase circuit.

This is the preferred option, because the ADE7761 starts billing

on the input V_1Aon power-up. The phase circuit CT is con-

nected to V_1Ain the diagram. Since there is no current in the

neutral circuit, the FAULT indicator comes on under these

conditions. However, this does not affect the accuracy of the

calibration and can be used as a means to test the functionality

of the fault detection.

FAULT

FILTER

AND

V

R

F

1A

V

1A

IB

CT

COMPARE

V

A

B

1B

V

RB

TO

C

1A

1B

V

F

1A

MULTIPLIER

0V

AGND

V

1N

1B

V

1N

AGND

IB

0V

TEST

CURRENT

V

< 93.75% OF V

1A

1B

CT

FAULT

R

F

1B

RA*

RB*

VR*

C

F

<0

>0

ACTIVE POINT – INACTIVE INPUT

V

2P

6.25% OF ACTIVE INPUT

R

F

2N

V

Figure 26. Fault Conditions for Active Input Greater than Inactive Input

C

T

240V RMS

*RB + VR = RF

Fault with Inactive Input Greater than Active Input

Figure 28. Fault Conditions for Inactive Input Greater than Active Input

Figure 27 illustrates another fault condition. If the difference

between V_1B, the inactive input, and V_1A, the active input (that is,

being used for billing), becomes greater than 6.25% of V_1B, the

FAULT indicator goes active, and there is also a swap over to the

V_1Binput. The analog input V_1Bbecomes the active input. Again,

there is a time constant of about 3 s associated with this swap.

If the neutral circuit is chosen for the current circuit in the

arrangement shown in Figure 28, this may have implications for

the calibration accuracy. The ADE7761 powers up with the V_1A

input active as normal. However, because there is no current in

the phase circuit, the signal on V_1Ais zero. This causes a fault to

be flagged and the active input to be swapped to V_1B(neutral).

The meter can be calibrated in this mode, but the phase and

neutral CTs might differ slightly. Because under no-fault condi-

tions all billing is carried out using the phase CT, the meter

should be calibrated using the phase circuit. Of course, both

phase and neutral circuits can be calibrated.

V_1Adoes not swap back to being the active channel until V_1Ais

greater than V_1Band the difference between V_1Aand V_1B—in this

order—becomes greater than 6.25% of V_1A. However, the

FAULT indicator becomes inactive as soon as V_1Ais within

6.25% of V_1B. This threshold eliminates potential chatter

between V_1Aand V_1B.

FAULT

FILTER

AND

COMPARE

V

1A

MISSING NEUTRAL MODE

V

A

B

1B

The ADE7761 integrates a novel fault detection that warns and

allows the ADE7761 to continue to bill in case a meter is

connected to only one wire (see Figure 29). For correct

operation of the ADE7761 in this mode, the V_DDpin of the

ADE7761 must be maintained within the specified range (5 V

5%). The missing neutral detection algorithm is designed to

work over a line frequency of 45 Hz to 55 Hz.

V

TO

1A

1B

MULTIPLIER

0V

V

1N

1B

AGND

V

< 93.75% OF V

1B

1A

FAULT + SWAP

<0

>0

ACTIVE POINT – INACTIVE INPUT

6.25% OF INACTIVE INPUT

Figure 27. Fault Conditions for Inactive Input Greater than Active Input

Rev. A | Page 20 of 28

ADE7761

V

R

1A

F

Important Note for Billing of Active Energy

CT

IB

The ADE7761 provides pulse outputs—CF, F1, and F2—

intended to be used for the billing of active energy. Pulses are

generated at these outputs in two different situations.

RB

C

240V RMS

POWER

GENERATOR

F

V1A

0V

V

1N

Case 1: When the analog input V_2P– V_2Ncomplies with the

conditions described in Figure 32, CF, F1, and F2 frequencies

are proportional to active power and can be used to bill active

energy.

C

F

CT

RA*

R

V

1B

F

LOAD

C

F

RB*

VR*

Case 2: When the analog input V_2P– V_2Ndoes not comply with

the conditions described in Figure 32, the ADE7761 does not

measure active energy, but a quantity proportional to kAh. This

quantity is used to generate pulses on the same CF, F1, and F2.

This situation is indicated when the FAULT pin is high.

V

2P

R

2N

C

T

*RB + VR = RF

Figure 29. Missing Neutral System Diagram

Analog Devices Inc. cautions users of the ADE7761:

The ADE7761 detects a missing neutral condition by continu-

ously monitoring the voltage channel input (V_2P–V_2N). The

FAULT pin is held high when a missing neutral condition is

detected. In this mode, the ADE7761 continues to bill the

energy based on the signal level on the current channel (see

Figure 30). The billing rate or frequency outputs can be adjusted

by changing the dc level on the MISCAL pin.

•

Billing active energy in Case 1 is consistent with the

understanding of the quantity represented by pulses on

CF, F1, and F2 outputs (watt-hour).

Billing active energy while the ADE7761 is in Case 2 must

be decided knowing that the entity measured by the

ADE7761 in this case is ampere-hour and not watt-hour.

Users should be aware of this limitation and decide if the

ADE7761 is appropriate for their application.

V

1A

ADC

A > B

V

1N

1B

HPF

Missing Neutral Detection

ADC

ZERO

CROSSING

DETECTION

B > A

B <> A

The ADE7761 continuously monitors the voltage input and

detects a missing neutral condition when the voltage input peak

value is smaller than 9% of the analog full scale or when no zero

crossings are detected on this input (see Figure 31).

LPF

MISSING NEUTRAL

GAIN ADJUSMENT

MISCAL

DIGITAL-

TO-

FREQUENCY

CONVERTERS

V

MISSING

2P

NEUTRAL

FILTER AND

THRESHOLD

V2

ADC

F1 F2

CF

V

2N

AGND

Figure 30. Energy Calculation in Missing Neutral Mode

|V2|

PEAK

< 9% OF FULL SCALE

OR

NO ZERO-CROSSING ON V2

V

–V

2P 2N

V

–V

2P 2N

V

–V

2P 2N

FS

9% OF FS

0V

Figure 31. Missing Neutral Detection

Rev. A | Page 21 of 28

ADE7761

The ADE7761 leaves the missing neutral mode for normal

operation when both conditions are no longer valid—voltage

peak value greater than 9% of full scale and zero crossing on the

voltage channel detected (see Figure 32).

where:

F₁, F₂Frequency is the output frequency on F1 and F2 (Hz).

V1_rmsis the differential rms voltage signal on Channel 1 (V).

MISCAL_rmsis the differential rms voltage signal on the MISCAL

pin (V).

V

MISSING

2P

NEUTRAL

FILTER AND

THRESHOLD

V

_REFis the reference voltage (2.5 V 8%) (V).

V2

ADC

F

_1-4is one of four possible frequencies selected by using the

V

2N

AGND

logic inputs S0 and S1 (see Table 5).

Example

|V2|

PEAK

> 9% OF FULL SCALE

AND

ZERO-CROSSING ON V2

In normal mode, ac voltages of 330 mV peak are applied to V1

and V2, and then the expected output frequency on F1 and F2 is

calculated as follows:

V

–V

2P 2N

FS

F

_1–4= 1.7 Hz, SCF = S1 = S0 = 0

+9% OF FS

–9% OF FS

V1 = rms of 330 mV peak ac = 0.33/√ V

2

V2 = rms of 330 mV peak ac = 0.33/√ V

2

Figure 32. Return to Normal Mode after Missing Neutral Detection

V

_REF= 2.5 V (nominal reference value)

Missing Neutral Gain Calibration

5.70×0.33×0.33×1.7 Hz

When the ADE7761 is in missing neutral mode, the energy is

billed based on the active current input signal level. The

calibration of the frequency outputs in this mode can be done

with the MISCAL analog input pin. In this mode, applying a dc

voltage of 330 mV on MISCAL is equivalent to applying, in

normal mode, a pure sine wave on the voltage input with a peak

value of 330 mV. The MISCAL input can vary from 0 V to

660 mV (see the Analog Inputs section). When set to 0 V, the

frequency outputs are close to zero. When set to 660 mV dc, the

frequency outputs are twice that when MISCAL is at 330 mV

dc. In other words, Equation 7 can be used in missing neutral

F₁, F₂Frequency =

= 0.084 Hz

2 × 2 ×2.5²

CF Frequency = F₁− F₂frequency × 64 = 5.4 Hz

In missing neutral mode, ac voltage of 330 mV peak is applied

to V1, no signal is connected on V2, and 330 mV dc input is

applied to MISCAL. With the ADE7761 in the same configura-

tion as the previous example, the expected output frequencies

on CF, F1, and F2 are

5.70×0.33×0.33/ 2 ×1.7 Hz

F₁, F₂Frequency =

= 0.084 Hz

mode by replacing V2_rmsby MISCAL_rms√ :

2 × 2.5²

2

CF Frequency = F₁, F₂frequency × 64 = 5.4 Hz

5.70 × MISCAL_rms/ 2 × F₁₋₄

F₁, F₂Frequency =

(8)

2

V_REF

Rev. A | Page 22 of 28

ADE7761

APPLICATIONS

For the purpose of calibration, this integration time could be

INTERFACING TO A MICROCONTROLLER FOR

ENERGY MEASUREMENT

10 s to 20 s in order to accumulate enough pulses to ensure

correct averaging of the frequency. In normal operation, the

integration time could be reduced to 1 s or 2 s depending, for

example, on the required update rate of a display. With shorter

integration times on the MCU, the amount of energy in each

update may still have a small amount of ripple, even under

steady load conditions. However, over a minute or more, the

measured energy has no ripple.

The easiest way to interface the ADE7761 to a microcontroller

is to use the CF high frequency output with the output

frequency scaling set to 2048 × F1, F2. This is done by setting

SCF = 0 and S0 = S1 = 1 (see Table 7). With full-scale ac signals

on the analog inputs, the output frequency on CF is approxi-

mately 5.5 kHz. Figure 33 illustrates one scheme that could be

used to digitize the output frequency and carry out the

necessary averaging mentioned in the previous section.

SELECTING A FREQUENCY FOR AN ENERGY

METER APPLICATION

CF

FREQUENCY

RIPPLE

As shown in Table 5, the user can select one of four frequencies.

This frequency selection determines the maximum frequency

on F1 and F2. These outputs are intended to be used to drive the

energy register (electromechanical or other). Because only four

different output frequencies can be selected, the available

frequency selection has been optimized for a meter constant of

100 impulses/kWh with a maximum current of between 10 A

and 120 A. Table 8 shows the output frequency for several

maximum currents (I_MAX) with a line voltage of 240 V. In all

cases, the meter constant is 100 impulses/kWh.

AVERAGE

FREQUENCY

±10%

TIME

MCU

ADE7761

COUNTER

CF

Table 8. F1 and F2 Frequency at 100 Impulses/kWh

UP/DOWN

REVP*

I_MAX(A)

12.5

25

F1 and F2 (Hz)

0.083

FAULT**

LOGIC

0.166

40

0.266

*REVP MUST BE USED IF THE METER IS BIDIRECTIONAL OR

DIRECTION OF ENERGY FLOW IS NEEDED.

**FAULT MUST BE USED TO RECORD ENERGY IN FAULT CONDITION.

60

0.4

80

0.533

120

0.8

Figure 33. Interfacing the ADE7761 to an MCU

As shown, the frequency output CF is connected to an MCU

counter or port, which counts the number of pulses in a given

integration time, determined by an MCU internal timer. The

average power, proportional to the average frequency, is given

by

The F_1–4frequencies allow complete coverage of this range of

output frequencies on F1 and F2. When designing an energy

meter, the nominal design voltage on Channel 2 (voltage)

should be set to half-scale to allow for calibration of the meter

constant. The current channel should also be no more than half-

scale when the meter sees maximum load, which accommodates

overcurrent signals and signals with high crest factors. Table 9

shows the output frequency on F1 and F2 when both analog

inputs are half-scale. The frequencies listed in Table 9 align well

with those listed in Table 8 for maximum load.

Counter

AverageFrequency = Average ActivePower =

Timer

The energy consumed during an integration period is given by

Counter

Energy = Average Power ×Time =

×Time = Counter

Time

Rev. A | Page 23 of 28

ADE7761

Table 9. F1 and F2 Frequency with Half-Scale AC Inputs

No-Load Threshold

Frequency on F1 and F2,

Ch 1 and Ch 2,

Half-Scale AC Inputs (Hz)

The ADE7761 includes a no-load threshold and startup current

feature that eliminates creep effects in the meter. The ADE7761

is designed to issue a minimum output frequency. Any load

generating a frequency lower than this minimum frequency

does not cause a pulse to be issued on F1, F2, or CF. The mini-

mum output frequency is given as 0.0045% of the full-scale

output frequency. (See Table 7 for maximum output frequencies

for ac signals).

S0

0

1

S1

0

1

0

1

F_1–4

1.72

3.44

6.86

13.5

0.085

0.17

0.34

0.68

When selecting a suitable F_1–4frequency for a meter design, the

frequency output at I_MAX(maximum load) with a meter constant

of 100 impulses/kWh should be compared with Column 4 of

Table 9. The frequency that is closest in Table 9 determines the

best choice of frequency (F_1-4). For example, if a meter with a

maximum current of 40 A is being designed, the output

frequency on F1 and F2 with a meter constant of

For example, an energy meter with a meter constant of

100 impulses/kWh on F1, F2 using SCF = 1, S1 = 0, and S0 = 1,

the maximum output frequency at F1 or F2 is 0.68 Hz and 43.52

Hz on CF. The minimum output frequency at F1 or F2 is

0.0045% of 0.68 Hz or 3.06 × 10^–5Hz. This is 1.96 × 10^–3Hz at

CF (64 × F1 Hz).

100 impulses/kWh is 0.266 Hz at 40 A and 240 V (from

Table 8). Looking at Table 9, the closest frequency to 0.266 Hz

in Column 4 is 0.17 Hz. Therefore, F2 (3.4 Hz; see Table 5) is

selected for this design.

In this example, the no-load threshold is equivalent to 1.1 W of

load or a startup current of 4.6 mA at 240 V. Compare this value

to the IEC61036 specification, which states that the meter must

start up with a load equal to or less than 0.4% I_B. For a 5 A (I_B)

meter, 0.4% of I_Bis equivalent to 20 mA.

Frequency Outputs

Figure 2 shows a timing diagram for the various frequency

outputs. The high frequency CF output is intended to be used

for communications and calibration purposes. CF produces a

90 ms wide, active high pulse (t₄) at a frequency that is propor-

tional to active power. The CF output frequencies are given in

Table 7. As in the case of F1 and F2, if the period of CF (t₅) falls

below 180 ms, the CF pulse width is set to half the period. For

example, if the CF frequency is 20 Hz, the CF pulse width is

25 ms.

Note that the no-load threshold is not enabled when using the

high CF frequency mode: SCF = 0, S1 = S0 = 1.

NEGATIVE POWER INFORMATION

The ADE7761 detects when the current and voltage channels

have a phase shift greater than 90°. This mechanism can detect

wrong connection of the meter or generation of negative power.

The REVP pin output goes active high when negative power is

detected, and active low when positive power is detected. The

REVP pin output changes state as a pulse is issued on CF.

Rev. A | Page 24 of 28

ADE7761

OUTLINE DIMENSIONS

7.50

7.20

6.90

20

11

5.60

5.30

5.00

8.20

7.80

7.40

1

10

1.85

1.75

1.65

2.00 MAX

0.25

0.09

8°

4°

0°

0.65

BSC

0.95

0.75

0.55

0.38

0.22

0.05 MIN

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-150AE

Figure 34. 20-Lead Shrink Small Outline Package [SSOP]

(RS-20)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADE7761ARS

ADE7761ARSRL

ADE7761ARS-REF

–40°C to +85°C

Shrink Small Outline Package

Reference Board

RS-20

Rev. A | Page 25 of 28

ADE7761

DISCLAIMER

The ADE7761 provides pulse outputs—CF, F1, and F2—

intended to be used for the billing of active energy. Pulses are

generated at these outputs in two different situations.

Analog Devices Inc. cautions users of the ADE7761:

•

Billing active energy in Case 1 is consistent with the

understanding of the quantity represented by pulses on

CF, F1, and F2 outputs (watt-hour).

Case 1: When the analog input V_2P– V_2Ncomplies with the

conditions described in Figure 32, CF, F1, and F2 frequencies

are proportional to active power and can be used to bill active

energy.

•

Billing active energy while the ADE7761 is in Case 2 must

be decided knowing that the entity measured by the

ADE7761 in this case is ampere-hour and not watt-hour.

Users should be aware of this limitation and decide if the

ADE7761 is appropriate for their application.

Case 2: When the analog input V_2P– V_2Ndoes not comply with

the conditions described in Figure 32, the ADE7761 does not

measure active energy, but a quantity proportional to kAh. This

quantity is used to generate pulses on the same CF, F1, and F2.

This situation is indicated when the FAULT pin is high.

Rev. A | Page 26 of 28

ADE7761

NOTES

Rev. A | Page 27 of 28

ADE7761

NOTES

©

registered trademarks are the property of their respective owners.

D04407–0–2/04(A)

Rev. A | Page 28 of 28


型号：	ADE7761ARS
厂家：	ADI
描述：	Energy Metering IC with On-Chip Fault and Missing Neutral Detection 电能计量IC ，带有片上故障和中性丢失检测
文件：	总28页 (文件大小：321K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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