ADF4002SRUZ-EP [ADI]
Phase Detector / PLL Frequency Synthesizer;
| 型号： | ADF4002SRUZ-EP |
| 厂家： | 
ADI |
| 描述： | Phase Detector / PLL Frequency Synthesizer 信息通信管理 光电二极管 |
| 文件： | 总8页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Phase Detector/Frequency Synthesizer
ADF4002-EP
FEATURES
GENERAL DESCRIPTION
400 MHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended
tuning voltage in 3 V systems
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
104 MHz phase frequency detector
Supports defense and aerospace applications
(AQEC standard)
The ADF4002-EP frequency synthesizer is used to implement
local oscillators in the upconversion and downconversion sections
of wireless receivers and transmitters. It consists of a low noise
digital phase frequency detector (PFD), a precision charge pump,
a programmable reference divider, and a programmable N divider.
The 14-bit reference counter (R counter) allows selectable REFIN
frequencies at the PFD input. A complete phase-locked loop (PLL)
can be implemented if the synthesizer is used with an external
loop filter and voltage controlled oscillator (VCO). In addition,
by programming R and N to 1, the part can be used as a stand-
alone PFD and charge pump.
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
One assembly/test site
Additional application and technical information can be found
in the ADF4002 data sheet.
One fabrication site
Enhanced product change notification
Qualification data available on request
APPLICATIONS
Clock conditioning
Clock generation
IF LO generation
FUNCTIONAL BLOCK DIAGRAM
AV
DV
R
SET
V
CPGND
DD
DD
P
REFERENCE
14-BIT
R COUNTER
PHASE
FREQUENCY
DETECTOR
REF
CHARGE
PUMP
IN
CP
14
R COUNTER
LATCH
LOCK
DETECT
CURRENT
SETTING 2
CURRENT
SETTING 1
CLK
DATA
LE
24-BIT INPUT
REGISTER
FUNCTION
LATCH
CPI6 CPI5 CPI4
HIGH-Z
CPI3 CPI2 CPI1
22
N COUNTER
LATCH
SD
OUT
AV
DD
MUXOUT
MUX
SD
OUT
RF
RF
A
B
13-BIT
N COUNTER
IN
IN
M3 M2 M1
ADF4002-EP
CE
AGND DGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
ADF4002-EP
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................5
Thermal Characteristics...............................................................5
ESD Caution...................................................................................5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Outline Dimensions..........................................................................8
Ordering Guide .............................................................................8
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
REVISION HISTORY
11/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 8
ADF4002-EP
SPECIFICATIONS
AVDD = DVDD = 3 V 10ꢀ, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN
,
unless otherwise noted. Operating temperature range is −55°C to +125°C.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
RF CHARACTERISTICS
RF Input Sensitivity
RF Input Frequency (RFIN)
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity1
REFIN Input Capacitance
REFIN Input Current
PHASE FREQUENCY DETECTOR (PFD)
Phase Detector Frequency2
CHARGE PUMP
−10
5
0
400
dBm
MHz
For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/μs
20
0.8
300
AVDD
10
MHz
V p-p
pF
For REFIN < 20 MHz, ensure SR > 50 V/μs
Biased at AVDD/2 (ac coupling ensures AVDD/2 bias)
100
μA
104
MHz
ABP[2:1] = 00 (2.9 ns antibacklash pulse width)
Programmable
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
RSET Range
ICP Three-State Leakage
ICP vs. VCP
Sink and Source Current Matching
ICP vs. Temperature
LOGIC INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IINH, IINL
Input Capacitance, CIN
LOGIC OUTPUTS
5
625
2.5
mA
μA
%
kΩ
nA
%
RSET = 5.1 kΩ
RSET = 5.1 kΩ
3.0
1.4
11
1
1.5
2
TA = 25°C
0.5 V ≤ VCP ≤ (VP − 0.5 V)
0.5 V ≤ VCP ≤ (VP − 0.5 V)
VCP = VP/2
%
%
2
V
V
μA
pF
0.6
1
10
Output High Voltage, VOH
1.4
DVDD − 0.4
V
V
Open-drain output, 1 kΩ pull-up resistor to 1.8 V
CMOS output
Output High Current, IOH
Output Low Voltage, VOL
POWER SUPPLIES
AVDD
100
0.4
μA
V
IOL = 500 μA
2.7
3.3
V
DVDD
AVDD
AVDD
V
V
mA
mA
μA
VP
5.5
6.0
0.4
AVDD ≤ VP ≤ 5.5 V
3
IDD (AIDD + DIDD
)
5.0
1
IP
TA = 25°C
AIDD + DIDD
Power-Down Mode
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH
Normalized 1/f Noise (PN1_f
4, 5
)
−222
−119
dBc/Hz
dBc/Hz
PLL loop bandwidth = 500 kHz
Measured at 10 kHz offset; normalized to 1 GHz
4, 6
)
1 AVDD = DVDD = 3 V.
2 Guaranteed by design. Sample tested to ensure compliance.
3 TA = 25°C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF); RF frequency and REFIN
frequency in MHz.
4 All phase noise measurements were performed with a Rohde & Schwarz FSUP26 phase noise test system using the EVAL-ADF4002EBZ1 evaluation board and the
ultralow noise, 100 MHz OCXO from Wenzel (Part No. 501-16843) as the PLL reference.
5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value)
and 10logfPFD. PNSYNTH = PNTOT − 10logfPFD − 20logN.
6 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at a
frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and the flicker noise are modeled in ADIsimPLL.
Rev. 0 | Page 3 of 8
ADF4002-EP
TIMING CHARACTERISTICS
AVDD = DVDD = 3 V 10ꢀ, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN
,
unless otherwise noted. Operating temperature range is −55°C to +125°C.
Table 2.
Parameter
Limit1
10
10
25
25
10
20
Unit
Description
t1
t2
t3
t4
t5
t6
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
1 Guaranteed by design, but not production tested.
Timing Diagram
t3
t4
CLK
t1
t2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
DB2
DB23 (MSB)
DB22
DATA
t6
LE
LE
t5
Figure 2. Timing Diagram
Rev. 0 | Page 4 of 8
ADF4002-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
Table 3.
Parameter
AVDD to GND1
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to DVDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to AVDD + 0.3 V
THERMAL CHARACTERISTICS
AVDD to DVDD
VP to GND1
Table 4. Thermal Impedance
VP to AVDD
Package Type
θJA
Unit
Digital I/O Voltage to GND1
Analog I/O Voltage to GND1
REFIN, RFINA, RFINB to GND1
Operating Temperature Range
Industrial
TSSOP (RU-16)
150.4
°C/W
ESD CAUTION
−55°C to +125°C
−65°C to +125°C
150°C
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
215°C
220°C
Transistor Count
CMOS
Bipolar
6425
303
1 GND = AGND = DGND = CPGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 8
ADF4002-EP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
16
15
14
V
R
P
SET
CP
DV
DD
MUXOUT
LE
CPGND
AGND
ADF4002-EP 13
TOP VIEW
(Not to Scale)
12
RF
RF
B
DATA
CLK
IN
11
10
9
A
IN
CE
AV
DD
DGND
REF
IN
Figure 3. Pin Configuration (Top View)
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
25.5
ICP MAX
=
RSET
where RSET = 5.1 kΩ and ICP MAX = 5 mA.
2
CP
Charge Pump Output. When enabled, this output provides ICP to the external loop filter that, in turn, drives
the external VCO.
3
4
5
CPGND
AGND
RFINB
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the RF input.
Complementary Input to the RF Input. This pin must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
6
7
RFINA
AVDD
Input to the RF Input. This small-signal input is ac-coupled to the external VCO.
Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to the AVDD pin. AVDD must be the same value as DVDD.
8
REFIN
Reference Input. This CMOS input has a nominal threshold of AVDD/2 and a dc equivalent input resistance
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
9
10
DGND
CE
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking this pin high powers up the device, depending on the status of the Power-Down Bit PD1.
11
12
13
14
15
16
CLK
Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first; the two LSBs are the control bits. This input is a high
impedance CMOS input.
Load Enable. When LE goes high, the data stored in the shift registers is loaded into one of the four latches;
the latch is selected using the control bits. This input is a high impedance CMOS input.
Multiplexer Output. This output allows the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.
Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to the DVDD pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to AVDD. In systems where AVDD is 3 V,
VP can be set to 5.5 V and used to drive a VCO with a tuning voltage of up to 5 V.
DATA
LE
MUXOUT
DVDD
VP
Rev. 0 | Page 6 of 8
ADF4002-EP
TYPICAL PERFORMANCE CHARACTERISTICS
0
–130
–135
–140
–145
–150
–155
–160
–165
–170
–175
–180
–5
–55°C
+25°C
+125°C
–10
–15
–20
–25
–30
–35
–40
100k
1M
10M
100M
1G
0
100
200
300
400
500
600
PFD FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 4. RF Input Sensitivity
Figure 7. Phase Noise (Referred to CP Output) vs. PFD Frequency
–15
–20
–25
–30
–35
MKR1 1.000 MHz
–94.5dBc
REF –4dBm
ATTN 10dB
1R
SAMP LOG 10dB/
0
–10
–20
–30
–40
–50
–55°C
+25°C
+125°C
–60
–70
–94.5dBc
1
–80
–90
5
7
9
11
13
15
–100
CENTER 399.995MHz
RES BW 20kHz
SPAN 2.2MHz
SWEEP 21ms (601pts)
VBW 20kHz
FREQUENCY (MHz)
Figure 5. RF Input Sensitivity, Low Frequency
Figure 8. Reference Spurs (400 MHz, 1 MHz, 7 kHz)
–70
–80
rms NOISE = 0.07 DEGREES
–90
–100
–110
–120
–130
–140
–150
–160
1k
10k
100k
FREQUENCY OFFSET (Hz)
1M
10M
Figure 6. Integrated Phase Noise (400 MHz, 1 MHz, 50 kHz)
Rev. 0 | Page 7 of 8
ADF4002-EP
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 9. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADF4002SRU-EP
ADF4002SRU-EP-RL7
Temperature Range
−55°C to +125°C
−55°C to +125°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
Package Option
RU-16
RU-16
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09187-0-11/10(0)
Rev. 0 | Page 8 of 8
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