ADF4007BCPZ-REEL7 [ADI]
PLL FREQUENCY SYNTHESIZER, 7500MHz, QCC20, MO-220-VGGD-1, LFCSP-20;![ADF4007BCPZ-REEL7](http://pdffile.icpdf.com/pdf2/p00223/img/icpdf/ADF4007BCPZ-_1305406_icpdf.jpg)
型号: | ADF4007BCPZ-REEL7 |
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描述: | PLL FREQUENCY SYNTHESIZER, 7500MHz, QCC20, MO-220-VGGD-1, LFCSP-20 信息通信管理 |
文件: | 总16页 (文件大小:248K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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High Frequency Divider/PLL Synthesizer
Data Sheet
ADF4007
FEATURES
GENERAL DESCRIPTION
7.5 GHz bandwidth
The ADF4007 is a high frequency divider/PLL synthesizer that
can be used in a variety of communications applications. It can
operate to 7.5 GHz on the RF side and to 120 MHz at the PFD.
It consists of a low noise digital PFD (phase frequency detector), a
precision charge pump, and a divider/prescaler. The divider/
prescaler value can be set by two external control pins to one of
four values (8, 16, 32, or 64). The reference divider is permanently
set to 2, allowing an external REFIN frequency of up to 240 MHz.
Maximum PFD frequency of 120 MHz
Divide ratios of 8, 16, 32, or 64
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
RSET control of charge pump current
Hardware power-down mode
APPLICATIONS
A complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and a VCO (voltage
controlled oscillator). Its very high bandwidth means that
frequency doublers can be eliminated in many high frequency
systems, simplifying system architecture and reducing cost.
Satellite communications
Broadband wireless access
CATV
Instrumentation
Wireless LANs
FUNCTIONAL BLOCK DIAGRAM
V
V
CPGND
R
SET
P
DD
REFERENCE
ADF4007
PHASE
FREQUENCY
DETECTOR
REF
R COUNTER
÷ 2
CHARGE
PUMP
IN
CP
MUXOUT
MUX
N COUNTER
÷ 8, ÷ 16,
÷ 32, ÷ 64
RF
RF
A
B
IN
IN
N2
N1
GND
M2
M1
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
ADF4007
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
RF Input Stage................................................................................9
Prescaler P......................................................................................9
R Counter .......................................................................................9
Phase Frequency Detector (PFD) and Charge Pump...............9
MUXOUT ................................................................................... 10
Applications Information .............................................................. 11
Fixed High Frequency Local Oscillator................................... 11
Using the ADF4007 as a Divider.............................................. 12
PCB Design Guidelines for Chip Scale Package......................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Reference Input Section............................................................... 9
REVISION HISTORY
7/12—Rev. A to Rev. B
12/09—Rev. 0 to Rev. A
Changes to Figure 2.......................................................................... 5
Changed Applications Section to Applications Information
Section.............................................................................................. 11
Updated Outline Dimensions (Changed CP-20-1 to CP-20-6)......14
Changes to Ordering Guide .......................................................... 14
Added Exposed Pad Notation to Figure 2 and Table 3.................5
Changes to Table 5.............................................................................6
Changes to Ordering Guide.......................................................... 14
2/04—Revision 0: Initial Version
Rev. B | Page 2 of 16
Data Sheet
ADF4007
SPECIFICATIONS
AVDD = DVDD = 3 V 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω,
TA = TMAX to TMIN, unless otherwise noted.
Table 1.
Parameter
B Version1
Unit
Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RFIN)
RF Input Frequency
1.0/7.0
0.5/7.5
GHz min/max
GHz min/max
RF input level: +5 dBm to −10 dBm
RF input level: +5 dBm to −5 dBm, for lower frequencies,
ensure that slew rate (SR) > 560 V/µs
REFIN CHARACTERISTICS
REFIN Input Sensitivity
REFIN Input Frequency
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency3
MUXOUT
0.8/VDD
20/240
10
V p-p min/max
MHz min/max
pF max
Biased at AVDD/22
For f < 20 MHz, use square wave (slew rate > 50 V/µs)
100
µA max
120
200
MHz max
MHz max
MUXOUT Frequency3
CHARGE PUMP
CL = 15 pF
ICP Sink/Source
Absolute Accuracy
RSET Range
ICP Three-State Leakage
Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
5.0
2.5
3.0/11
10
2
1.5
2
mA typ
% typ
kΩ typ
nA max
% typ
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
TA = 85°C
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
% typ
% typ
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
1.4
0.6
1
V min
V max
µA max
pF max
TA = 25°C
10
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
AVDD
DVDD
VP
IDD4 (AIDD + DIDD)
VDD − 0.4
0.4
V min
V max
IOH = 100 µA
IOL = 500 µA
2.7/3.3
AVDD
AVDD/5.5
17
V min/max
V min/max
mA max
AVDD ≤ VP ≤ 5.5 V
15 mA typ
IP
2.0
mA max
TA = 25°C
NOISE CHARACTERISTICS
Normalized Phase Noise Floor5
−219
dBc/Hz typ
1 Operating temperature range (B version) is −40°C to +85°C.
2 AC coupling ensures AVDD/2 bias. See Figure 13 for typical circuit.
3 Guaranteed by design. Characterized to ensure compliance.
4 TA = 25°C; AVDD = DVDD = 3 V; N = 64; RFIN = 7.5 GHz.
5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PNTOT, and subtracting 20logN (where N is the N divider
value) and 10logFPFD. PNSYNTH = PNTOT − 10logFPFD − 20logN. The in-band phase noise (PNTOT) is measured using the HP8562E Spectrum Analyzer from Agilent.
Rev. B | Page 3 of 16
ADF4007
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
AVDD to GND1
AVDD to DVDD
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
CSP θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 s)
Infrared (15 s)
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to VDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
−40°C to +85°C
−65°C to +125°C
150°C
ESD CAUTION
122°C/W
215°C
220°C
Transistor Count
CMOS
Bipolar
6425
303
1 GND = AGND = DGND = 0 V.
Rev. B | Page 4 of 16
Data Sheet
ADF4007
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF4007
15 MUXOUT
14 M1
CPGND
AGND
AGND
1
2
3
4
5
TOP
VIEW
13 M2
12 N1
RF
RF
B
IN
A
11 N2
IN
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT
MUST BE CONNECTED TO GROUND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1
2, 3
4
CPGND
AGND
RFINB
Charge Pump Ground. The ground return path of the charge pump.
Analog Ground. The ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF.
5
6, 7
RFINA
AVDD
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8
REFIN
Reference Input. A CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 kΩ.
This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9, 10
11, 12
13, 14
15
DGND
N2, N1
M2, M1
MUXOUT
DVDD
Digital Ground.
These two bits set the N value. See Table 4.
These two bits set the status of MUXOUT and PFD polarity. See Table 5.
This multiplexer output allows either the N divider output or the R divider output to be accessed externally.
Digital Power Supply. This pin can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
16, 17
18
19
VP
Charge Pump Power Supply. This pin should be greater than or equal to VDD. In systems where VDD is 3 V, it can be
set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
RSET
voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
25.5
RSET
ICPMAX
=
Therefore, if RSET = 5.1 kΩ, then ICP = 5 mA.
20
21
CP
EP
Charge Pump Output. When enabled, this pin provides ICP to the external loop filter, which in turn drives the
external VCO.
Exposed Pad.
Rev. B | Page 5 of 16
ADF4007
Data Sheet
Table 4. N Truth Table
Table 5. M Truth Table
N2
N1
N Value
M2
M1
Operation
Description
Active
0
0
8
0
0
CP
0
1
1
1
0
1
16
32
64
MUXOUT
PFD polarity
CP
MUXOUT
PFD polarity
CP
MUXOUT
PFD polarity
CP
MUXOUT
PFD polarity:
VDD
+ve
0
1
1
1
0
1
Three-state
R divider output/2
+ve
Active
N divider output
+ve
Active
GND
−ve
Rev. B | Page 6 of 16
Data Sheet
ADF4007
TYPICAL PERFORMANCE CHARACTERISTICS
Table 6. S-Parameter Data for the RF Input
Frequency1
0.60000
0.70000
0.80000
0.90000
1.00000
1.10000
1.20000
1.30000
1.40000
1.50000
1.60000
1.70000
1.80000
1.90000
2.00000
2.10000
2.20000
2.30000
2.40000
2.50000
2.60000
2.70000
2.80000
2.90000
3.00000
3.10000
3.20000
3.30000
3.40000
3.50000
3.60000
3.70000
3.80000
3.90000
4.00000
4.10000
4.20000
MagS11
0.87693
0.85834
0.85044
0.83494
0.81718
0.80229
0.78917
0.77598
0.75578
0.74437
0.73821
0.72530
0.71365
0.70699
0.70380
0.69284
0.67717
0.67107
0.66556
0.65640
0.63330
0.61406
0.59770
0.56550
0.54280
0.51733
0.49909
0.47309
0.45694
0.44698
0.43589
0.42472
0.41175
0.41055
0.40983
0.40182
0.41036
AngS11
Frequency1
4.30000
4.40000
4.50000
4.60000
4.70000
4.80000
4.90000
5.00000
5.10000
5.20000
5.30000
5.40000
5.50000
5.60000
5.70000
5.80000
5.90000
6.00000
6.10000
6.20000
6.30000
6.40000
6.50000
6.60000
6.70000
6.80000
6.90000
7.00000
7.10000
7.20000
7.30000
7.40000
7.50000
MagS11
0.41731
0.43126
0.42959
0.42687
0.43450
0.42275
0.40662
0.39103
0.37761
0.34263
0.30124
0.27073
0.23590
0.17550
0.12739
0.09058
0.06824
0.04465
0.04376
0.06621
0.08498
0.10862
0.12161
0.12917
0.12716
0.11678
0.10533
0.09643
0.08919
0.08774
0.09289
0.10803
0.13956
AngS11
−19.9279
−23.5610
−26.9578
−30.8201
−34.9499
−39.0436
−42.3623
−46.3220
−50.3484
−54.3545
−57.3785
−60.6950
−63.9152
−66.4365
−68.4453
−70.7986
−73.7038
−75.8206
−77.6851
−80.3101
−82.5082
−85.5623
−87.3513
−89.7605
−93.0239
−95.9754
−99.1291
−102.208
−106.794
−111.659
−117.986
−125.620
−133.291
−140.585
−147.970
−155.978
−162.939
−168.232
−174.663
−179.797
174.379
171.537
167.201
163.534
159.829
157.633
152.815
147.632
144.304
138.324
131.087
124.568
119.823
114.960
84.4391
34.2210
4.70571
−12.6228
−26.6069
−38.5860
−47.1990
−55.8515
−63.0234
−66.9967
−75.4961
−89.2055
−103.786
−127.153
−150.582
−170.971
1Frequency unit: GHz; parameter type: s; data format: MA; keyword: R;
impedance: 50.
Rev. B | Page 7 of 16
ADF4007
Data Sheet
0
0
–10
–20
–30
–40
–50
–60
–70
–80
V
V
= 3V
= 3V
DD
REF LEVEL = –14.0dBm
V
= 3V, V = 5V
P
DD P
–5
I
= 5mA
CP
PFD FREQUENCY = 106MHz
LOOP BANDWIDTH = 1MHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5s
–10
–15
–20
AVERAGES = 30
TA = +85°C
= –40°C
–25
–30
T
A
T
= +25°C
A
–91.0dBc/Hz
–35
–40
–90
–100
–212
–106
6780
106
212
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
RF INPUT FREQUENCY (GHz)
FREQUENCY (MHz)
Figure 6. Reference Spurs (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop
Bandwidth)
Figure 3. Input Sensitivity
–120
0
–10
–20
–30
–40
–50
–60
–70
–80
V
V
= 3V
= 5V
P
REF LEVEL = –14.3dBm
DD
V
= 3V, V = 5V
= 5mA
DD
P
I
CP
–130
–140
–150
–160
–170
–180
PFD FREQUENCY = 106kHz
LOOP BANDWIDTH = 1MHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9s
AVERAGES = 10
–99dBc/Hz
–90
–100
10k
100k
1M
10M
–2k
–1k
6780M
1k
2k
120M
FREQUENCY (Hz)
PHASE DETECTOR FREQUENCY (Hz)
Figure 7. Phase Noise (Referred to CP Output) vs. PFD Frequency
Figure 4. Phase Noise (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz Loop
Bandwidth)
–40
–6
–5
10dB/DIV
–50
–60
R
= –40dBc/Hz
L
RMS NOISE = 4.2°
–4
–3
–2
–1
0
V
= 5V
P
I
= 5mA
CP
–70
–80
–90
1
–100
–110
–120
2
3
4
–130
–140
5
6
0
0.5
1.0
1.5
2.0
2.5
(V)
3.0
3.5
4.0
4.5 5.0
10k
100k
1M
10M
100M
V
CP
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 5. Integrated Phase Noise (6.78 GHz RFOUT, 106 MHz PFD, and 1 MHz
Loop Bandwidth)
Figure 8. Charge Pump Output Characteristics
Rev. B | Page 8 of 16
Data Sheet
ADF4007
THEORY OF OPERATION
REFERENCE INPUT SECTION
PRESCALER P
The prescaler, operating at CML levels, takes the clock from the
RF input stage and divides it down to a manageable frequency
for the PFD. The prescaler can be selected to be either 8, 16, 32,
or 64, and is effectively the N value in the PLL synthesizer. The
terms N and P are used interchangeably in this data sheet. N1
and N2 set the prescaler values. The prescaler value should be
chosen so that the prescaler output frequency is always less than
or equal to 120 MHz, the maximum specified PFD frequency.
Thus, with an RF frequency of 4 GHz, a prescaler value of 64 is
valid, but a value of 32 or less is not valid.
The reference input stage is shown in Figure 9. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
POWER-DOWN
CONTROL
100kΩ
NC
SW2
TO R COUNTER
REF
IN
fREFIN
2
NC
fVCO =[N]×
BUFFER
SW1
R COUNTER
SW3
NO
The R counter is permanently set to 2. It allows the input reference
frequency to be divided down by 2 to produce the reference clock
to the phase frequency detector (PFD).
Figure 9. Reference Input Stage
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
RF INPUT STAGE
The RF input stage is shown in Figure 10. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
The PFD takes inputs from the R counter and the N counter
(prescaler, P) and produces an output proportional to the phase
and frequency difference between them. Figure 11 is a simplified
schematic. The PFD includes a fixed, 3 ns delay element that
controls the width of the antibacklash pulse. This pulse ensures
that there is no dead zone in the PFD transfer function and
minimizes phase noise and reference spurs.
BIAS
GENERATOR
1.6V
AV
DD
500Ω
500Ω
V
P
RF
RF
A
B
IN
CHARGE
PUMP
UP
Q1
U1
D1
LOGIC HI
IN
R DIVIDER
CLR1
3ns
DELAY
AGND
U3
CP
Figure 10. RF Input Stage
CLR2
D2 Q2
DOWN
LOGIC HI
U2
N DIVIDER
CPGND
Figure 11. PFD Simplified Schematic and Timing (In Lock)
Rev. B | Page 9 of 16
ADF4007
Data Sheet
PFD Polarity
MUXOUT
The PFD polarity is set by the state of M2 and M1 pins as given
in the Table 5. The ability to set the polarity allows the use of VCOs
with either positive or negative tuning characteristics. For standard
VCOs with positive characteristics (output frequency increases
with increasing tuning voltage), the polarity should be set to
positive. This is accomplished by tying M2 and M1 to a logic
low state.
The output multiplexer on the ADF4007 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by the M2 and M1 pins. Figure 12
shows the MUXOUT section in block diagram form.
DV
DD
CP Output
DV
DD
The CP output state is also controlled by the state of M2 and M1. It
can be set either to active (so that the loop can be locked) or to
three-state (open the loop). The normal state is CP output active.
R COUNTER OUTPUT
N COUNTER OUTPUT
DGND
MUX
CONTROL
MUXOUT
DGND
Figure 12. MUXOUT Circuit
Rev. B | Page 10 of 16
Data Sheet
ADF4007
APPLICATIONS INFORMATION
Other PLL system specifications are as follows:
FIXED HIGH FREQUENCY LOCAL OSCILLATOR
KD = 5 mA
KV = 100 MHz/V
Loop Bandwidth = 300 kHz
FPFD = 106 MHz
N = 64
Figure 13 shows the ADF4007 being used with the HMC358MS8G
VCO from Hittite Microwave Corporation to produce a fixed-
frequency LO (local oscillator), which could be used in satellite
or CATV applications. In this case, the desired LO is 6.7 GHz.
The reference input signal is applied to the circuit at FREFIN
and, in this case, is terminated in 50 Ω. Many systems would
have either a TCXO or an OCXO driving the reference input
without any 50 Ω termination. To bias the REFIN pin at AVDD/2,
ac coupling is used. The value of the coupling capacitor used
depends on the input frequency. The equivalent impedance at
the input frequency should be less than 10 Ω. Given that the dc
input impedance at the REFIN pin is 100 kΩ, less than 0.1% of
the signal is lost.
All these specifications are needed and used with the ADIsimPLL
to derive the loop filter component values shown in Figure 13.
The circuit in Figure 13 gives a typical phase noise performance
of −100 dBc/Hz at 10 kHz offset from the carrier. Spurs are
heavily attenuated by the loop filter and are below −90 dBc.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output, and the RFIN
terminal of the synthesizer.
The charge pump output of the ADF4007 drives the loop filter.
In calculating the loop filter component values, a number of items
need to be considered. In this example, the loop filter was designed
so that the overall phase margin for the system is 45°.
AV
= 3.3V
V
= 3.3V
DD
CC
18kΩ
18Ω
18Ω
V
= 12V
CC
6
7
16
17
18
1kΩ
V
100pF
18Ω
100pF
AV
AV
DV
DV
P
DD
DD
1kΩ
DD
DD
HMC358MS8G
RF
5
4
OUT
RF
RF
A
IN
IN
20
10pF
CP
AD820
B
VCO
100MHz/V
22Ω
5.6nF
47nF
ADF4007
100pF
100pF
FREF
8
REF
IN
IN
51Ω
11
12
13
14
LOGIC HI
LOGIC HI
LOGIC LO
LOGIC LO
N2
N1
M2
M1
MUXOUT
15
10
19
R
SET
GND
9
R
SET
5.1kΩ
100pF
2
3
NOTE
DECOUPLING CAPACITORS (0.1mF/10pF) ON AV , DV , AND V OF THE ADF4007 AND ON
DD
DD
P
V
OF THE AD820 AND THE HMC358MS8G HAVE BEEN OMITTED FROM THE DIAGRAM
CC
TO AID CLARITY.
Figure 13. 6.78 GHz Local Oscillator Using the ADF4007
Rev. B | Page 11 of 16
ADF4007
Data Sheet
This part is an integrated synthesizer and VCO, in this case
USING THE ADF4007 AS A DIVIDER
operating over a range of 1200 MHz to 1500 MHz. With divide-
by-8 chosen in the ADF4007 (N2 = 0, N1 = 0), the output range
is 150 MHz to 187.50 MHz.
In addition to its use as a standard PLL synthesizer, the ADF4007
can also be used as a high frequency counter/divider with a value
of 8, 16, 32, or 64.This can prove useful in a wide variety of
applications where a higher frequency signal is readily available.
Figure 14 shows the ADF4007 used in this manner with the
ADF4360-7.
V
DD
V
LOCK
DETECT
V
DD
VCO
4.7kΩ
M2 M1
R
CP
V
AV
DV
DD
SET
P
DD
6
21
DV
2
20
23
10mF
V
V
7
AV
CE MUXOUT
TUNE
CP
VCO
DD
DD
14
16
C
N
13kΩ
CMOS OUTPUT
PHASE
MUXOUT
24
CHARGE
PUMP
1nF
1nF
FREQUENCY
DETECTOR
MUX
FREF
IN
REF
6.8nF
IN
470pF
VCO
220pF
51Ω
17
6.2kΩ
CLK
ADF4360-7
18
19
DATA
LE
V
REF
IN
R COUNTER
÷ 2
12
C
C
51Ω
51Ω
RF
A
IN
13
R
1nF
SET
4
5
RF
RF
A
OUT
N COUNTER
÷ 8, ÷ 16
÷ 32, ÷ 64
4.7kΩ
100pF
100pF
RF
B
IN
CPGND AGND
DGND
L1 L2
10
B
OUT
15
1
3
8
11
22
9
CPGND GND
N1
N2
ADF4007
2.2nH
2.2nH
Figure 14. Using the ADF4007 to Divide-Down the Output of the ADF4360-7
Rev. B | Page 12 of 16
Data Sheet
ADF4007
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the chip scale package (CP-20-6) are rectangular.
The printed circuit board pad for these should be 0.1 mm longer
than the package land length and 0.05 mm wider than the package
land width. Center the land on the pad to ensure that the solder
joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. The printed circuit board should have
a clearance of at least 0.25 mm between the thermal pad and the
inner edges of the pad pattern to ensure that shorting is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.30 mm and
0.33 mm, and the via barrel should be plated with 1 oz. copper
to plug the via.
Connect the printed circuit board thermal pad to AGND.
Rev. B | Page 13 of 16
ADF4007
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.30
2.10 SQ
2.00
11
5
6
10
0.65
0.60
0.55
0.20 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
Figure 15. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
ADF4007BCPZ
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-20-6
Evaluation Board
ADF4007BCPZ-RL
ADF4007BCPZ-RL7
EVAL-ADF4007EBZ1
1 Z = RoHS compliant part.
Rev. B | Page 14 of 16
Data Sheet
NOTES
ADF4007
Rev. B | Page 15 of 16
ADF4007
NOTES
Data Sheet
©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04537-0-7/12(B)
Rev. B | Page 16 of 16
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