ADF4106SRUZ-EP-R7 [ADI]
6 GHz integer-N PLL;
| 型号： | ADF4106SRUZ-EP-R7 |
| 厂家： | 
ADI |
| 描述： | 6 GHz integer-N PLL 信息通信管理 光电二极管 |
| 文件： | 总10页 (文件大小：316K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PLL Frequency Synthesizer
Enhanced Product
ADF4106-EP
FEATURES
GENERAL DESCRIPTION
6.0 GHz bandwidth
2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning
voltage in 3 V systems
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
The ADF4106-EP frequency synthesizer can be used to
implement local oscillators in the up-conversion and down-
conversion sections of wireless receivers and transmitters. It
consists of a low noise, digital phase frequency detector (PFD),
a precision charge pump, a programmable reference divider,
programmable A counter and B counter, and a dual-modulus
prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in
conjunction with the dual-modulus prescaler (P/P + 1), implement
an N divider (N = BP + A). In addition, the 14-bit reference
counter (R counter) allows selectable REFIN frequencies at the
PFD input. A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO). Its very high
bandwidth means that frequency doublers can be eliminated in
many high frequency systems, simplifying system architecture
and reducing cost.
Support defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available upon request
Additional application and technical information can be found
in the ADF4106 data sheet.
APPLICATIONS
Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios
FUNCTIONAL BLOCK DIAGRAM
AV
DV
R
SET
V
CPGND
DD
DD
P
REFERENCE
14-BIT
R COUNTER
PHASE
FREQUENCY
DETECTOR
REF
CHARGE
PUMP
IN
CP
14
R COUNTER
LATCH
LOCK
DETECT
CURRENT
SETTING 2
CURRENT
SETTING 1
CLK
DATA
LE
24-BIT INPUT
REGISTER
FUNCTION
LATCH
CPI6 CPI5 CPI4
HIGH Z
CPI3 CPI2 CPI1
22
A, B COUNTER
LATCH
FROM
SD
19
OUT
AV
FUNCTION
LATCH
DD
MUXOUT
MUX
13
13-BIT
N = BP + A
SD
OUT
B COUNTER
LOAD
RF
RF
A
B
PRESCALER
P/P + 1
IN
IN
LOAD
M3 M2 M1
6-BIT
A COUNTER
ADF4106-EP
6
CE
AGND DGND
Figure 1.
Rev. C
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Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADF4106-EP
Enhanced Product
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configurations and Function Descriptions............................6
Typical Performance Characteristics ..............................................7
PCB Design Guidelines for Chip Scale Package............................9
Outline Dimensions....................................................................... 10
Ordering Guide .......................................................................... 10
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characterisitics ............................................................... 4
REVISION HISTORY
11/14—Rev. B to Rev. C
Change to Table 1 ............................................................................. 3
Change to Table 2 ............................................................................. 4
Changes to Table 3............................................................................ 5
8/12—Rev. A to Rev. B
Changes to Table 3............................................................................ 5
Updated Outline Dimensions....................................................... 10
Changes to Ordering Guide .......................................................... 10
11/10—Rev. 0 to Rev. A
Changes to Figure 6.......................................................................... 7
Changes to Figure 11........................................................................ 8
Changes to Ordering Guide .......................................................... 10
8/10—Revision 0: Initial Version
Rev. C | Page 2 of 10
Enhanced Product
SPECIFICATIONS
ADF4106-EP
AVDD = DVDD = 3 V 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN
,
unless otherwise noted.
Table 1.
Parameter
SVersion1 Unit
Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RFIN)
RF Input Sensitivity
Maximum Allowable Prescaler Output Frequency2
0.5/6.0
−10/0
300
GHz min/max
For lower frequencies, ensure slew rate (SR) > 320 V/µs
dBm min/max
MHz max
MHz
P = 8
P = 16
325
REFIN CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity3
REFIN Input Capacitance
REFIN Input Current
PHASE DETECTOR
Phase Detector Frequency5
CHARGE PUMP
20/300
0.8/VDD
10
MHz min/max
For f < 20 MHz, ensure SR > 50 V/µs
V p-p min/max Biased at AVDD/24
pF max
µA max
100
104
MHz max
ABP = 0, 0 (2.9 ns antibacklash pulse width)
ICP Sink/Source
High Value
Low Value
5
mA typ
µA typ
% typ
kΩ typ
nA max
% typ
With RSET = 5.1 kΩ
With RSET = 5.1 kΩ
625
2.5
3.0/11
2
2
1.5
2
Absolute Accuracy
RSET Range
ICP Three-State Leakage
Sink and Source Current Matching
ICP vs. VCP
1 nA typical; TA = 25°C
0.5 V ≤ VCP ≤ VP − 0.5 V
0.5 V ≤ VCP ≤ VP − 0.5 V
VCP = VP/2
% typ
% typ
ICP vs. Temperature
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance
LOGIC OUTPUTS
1.4
0.6
1
V min
V max
µA max
pF max
10
VOH, Output High Voltage
1.4
VDD − 0.4
100
V min
Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V
CMOS output chosen
V min
µA max
V max
IOH
VOL, Output Low Voltage
0.4
IOL = 500 µA
POWER SUPPLIES
AVDD
DVDD
VP
IDD6 (AIDD + DIDD)
IDD7 (AIDD + DIDD)
IDD8 (AIDD + DIDD)
IP
2.7/3.3
AVDD
AVDD/5.5
11
11.5
13
V min/V max
V min/V max
mA max
mA max
mA max
mA max
µA typ
AVDD ≤ VP ≤ 5.5 V
9.0 mA typical
9.5 mA typical
10.5 mA typical
TA = 25°C
0.4
10
Power-Down Mode9 (AIDD + DIDD)
Rev. C | Page 3 of 10
ADF4106-EP
Enhanced Product
Parameter
SVersion1 Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PNSYNTH
Normalized 1/f Noise (PN1_f)11
Phase Noise Performance12
900 MHz13
10
)
−223
−122
dBc/Hz typ
dBc/Hz typ
PLL loop BW = 500 kHz
Measured at 10 kHz offset; normalized to 1 GHz
VCO output
1 kHz offset and 200 kHz PFD frequency
1 kHz offset and 200 kHz PFD frequency
1 kHz offset and 1 MHz PFD frequency
−92.5
−76.5
−83.5
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
5800 MHz14
5800 MHz15
Spurious Signals
900 MHz13
−90/−92
−65/−70
−70/−75
dBc typ
dBc typ
dBc typ
200 kHz/400 kHz and 200 kHz PFD frequency
200 kHz/400 kHz and 200 kHz PFD frequency
1 MHz/2 MHz and 1 MHz PFD frequency
5800 MHz14
5800 MHz15
1 Operating temperature range is −55°C to +125°C.
2 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3 AVDD = DVDD = 3 V.
4 AC coupling ensures AVDD/2 bias.
5 Guaranteed by design. Sample tested to ensure compliance.
6 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz.
7 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz.
8 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz.
9 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz.
10 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N.
11 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a
frequency offset, f, is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
12 The phase noise is measured with the EVAL-ADF4106-EB1 evaluation board and the Agilent E4440A spectrum analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm).
13
f
f
f
= 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz.
= 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 29,000; loop B/W = 20 kHz.
= 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 5800; loop B/W = 100 kHz.
REFIN
REFIN
REFIN
14
15
TIMING CHARACTERISITICS
AVDD = DVDD = 3 V 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN
,
unless otherwise noted.
Table 2.
Parameter
Limit1 (B Version)
Unit
Test Conditions/Comments
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
CLOCK to LE Setup Time
LE Pulse Width
1 Operating temperature range (S Version) is –55°C to +125°C.
Timing Diagram
t3
t4
CLOCK
t1
t2
DB0 (LSB)
(CONTROL BIT C1)
DB1 (CONTROL
BIT C2)
DB2
DB23 (MSB)
DATA
DB22
t6
LE
LE
t5
Figure 2. Timing Diagram
Rev. C | Page 4 of 10
Enhanced Product
ADF4106-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3.
Parameter
AVDD to GND1
AVDD to DVDD
VP to GND
VP to AVDD
Digital I/O Voltage to GND
Analog I/O Voltage to GND
REFIN, RFINA, RFINB to GND
RFINA to RFINB
Rating
−0.3 V to + 3.6 V
−0.3 V to + 0.3 V
−0.3 V to + 5.8 V
−0.3 V to + 5.8 V
−0.3 V to VDD + 0.3 V
−0.3 V to VP + 0.3 V
−0.3 V to VDD + 0.3 V
320 mV
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
Operating Temperature Range
Industrial (S Version)
Storage Temperature Range
Maximum Junction Temperature
θJA Thermal Impedance
16-Lead TSSOP
ESD CAUTION
−55°C to +125°C
−65°C to +125°C
150°C
112°C/W
30.4°C/W
20-Lead LFCSP (Paddle Soldered)
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Transistor Count
260°C
40 sec
CMOS
Bipolar
6425
303
1GND = AGND = DGND = 0 V.
Rev. C | Page 5 of 10
ADF4106-EP
Enhanced Product
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
R
P
SET
DV
CP
DD
MUXOUT
LE
CPGND
AGND
ADF4106-EP
PIN 1
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
CPGND 1
AGND 2
AGND 3
INDICATOR
TOP VIEW
(Not to Scale)
ADF4106-EP
DATA
CLK
RF
RF
B
IN
IN
RF B 4
IN
TOP VIEW
(Not to Scale)
RF A 5
IN
A
CE
AV
DD
DGND
REF
IN
NOTES:
NOTES
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
2. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
Figure 4. 20-Lead LFCSP Pin Configuration
Figure 3. 16-Lead TSSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Pin No.
TSSOP
LFCSP
Mnemonic Description
1
19
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
25.5
RSET
ICP MAX
=
So, with RSET = 5.1 kΩ, ICP MAX = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this provides ICP to the external loop filter, which in turn drives
the external VCO.
3
4
5
1
2, 3
4
CPGND
AGND
RFINB
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF.
6
7
5
6, 7
RFINA
AVDD
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input
resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
9
10
9, 10
11
DGND
CE
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high powers up the device, depending on the status of the power-
down bit, F2.
11
12
13
14
15
16
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input
is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches with the latch being selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.
Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
13
DATA
LE
14
15
MUXOUT
DVDD
VP
16, 17
18
EP
Exposed Pad. The exposed pad must be connected to AGND.
Rev. C | Page 6 of 10
Enhanced Product
ADF4106-EP
TYPICAL PERFORMANCE CHARACTERISTICS
–40
–50
FREQ UNIT
GHz KEYWORD
R
10dB/DIV
= –40dBc/Hz
PARAM TYPE
S
IMPEDANCE 50Ω
DATA FORMAT MA
R
L
RMS NOISE = 0.36°
–60
FREQ
0.500
0.600
0.700
0.800
0.900
1.000
1.100
1.200
1.300
1.400
1.500
1.600
1.700
1.800
1.900
2.000
2.100
2.200
2.300
2.400
2.500
2.600
2.700
2.800
2.900
3.000
3.100
3.200
MAGS11
0.89148
0.88133
0.87152
0.85855
0.84911
0.83512
0.82374
0.80871
0.79176
0.77205
0.75696
0.74234
0.72239
0.69419
0.67288
0.66227
0.64758
0.62454
0.59466
0.55932
0.52256
0.48754
0.46411
0.45776
0.44859
0.44588
0.43810
0.43269
ANGS11
FREQ MAGS11 ANGS11
–17.2820
– 20.6919
– 24.5386
–27.3228
–31.0698
– 34.8623
–38.5574
–41.9093
– 45.6990
–49.4185
–52.8898
–56.2923
–60.2584
–63.1446
–65.6464
–68.0742
–71.3530
–75.5658
–79.6404
–82.8246
–85.2795
–85.6298
–86.1854
–86.4997
–88.8080
–91.9737
–95.4087
–99.1282
3.300
3.400
3.500
3.600
3.700
3.800
3.900
4.000
4.100
4.200
4.300
4.400
4.500
4.600
4.700
4.800
4.900
5.000
5.100
5.200
5.300
5.400
5.500
5.600
5.700
5.800
5.900
6.000
0.42777
0.42859
0.43365
0.43849
0.44475
0.44800
0.45223
0.45555
0.45313
0.45622
0.45555
0.46108
0.45325
0.45054
0.45200
0.45043
0.45282
0.44287
0.44909
0.44294
0.44558
0.45417
0.46038
0.47128
0.47439
0.48604
0.50637
0.52172
–102.748
–107.167
–111.883
–117.548
–123.856
–130.399
–136.744
–142.766
–149.269
–154.884
–159.680
–164.916
–168.452
–173.462
–176.697
178.824
174.947
170.237
166.617
162.786
158.766
153.195
147.721
139.760
132.657
125.782
121.110
115.400
–70
–80
–90
–100
–110
–120
–130
–140
100Hz
1MHz
FREQUENCY OFFSET FROM 900MHz CARRIER
Figure 5. S-Parameter Data for the RF Input
Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, and 20 kHz)
5
0
0
–55°C
+25°C
+125°C
REF LEVEL = –14.0dBm
V
= 3V, V = 5V
P
DD
= 5mA
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
I
CP
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30
–5
–10
–15
–20
–25
–30
–35
–91.0dBc/Hz
–40
0
1
2
3
4
5
6
7
8
9
10
–400kHz
–200kHz
900MHz
200kHz
400kHz
FREQUENCY
FREQUENCY (GHz)
Figure 9. Reference Spurs (900 MHz, 200 kHz, and 20 kHz)
Figure 6. Input Sensitivity
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
REF LEVEL = –10dBm
V
I
= 3V, V = 5V
P
REF LEVEL = –14.3dBm
DD
= 5mA
V
= 3V, V = 5V
P
DD
= 5mA
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CP
I
CP
PFD FREQUENCY = 200kHz
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10
–93.0dBc/Hz
–83.5dBc/Hz
–2kHz
–1kHz
5800MHz
1kHz
2kHz
–2kHz
–1kHz
900MHz
1kHz
2kHz
FREQUENCY
FREQUENCY
Figure 10. Phase Noise (5.8 GHz,1 MHz, and 100 kHz)
Figure 7. Phase Noise (900 MHz, 200 kHz, and 20 kHz)
Rev. C | Page 7 of 10
ADF4106-EP
Enhanced Product
–70
–5
–15
–25
–35
–45
–55
–65
–75
–85
–95
–105
–55°C
+25°C
+125°C
V
V
= 3V
DD
= 5V
–80
P
–90
–100
–110
–120
–130
–140
–150
–160
–170
1k
10k
100k
1M
10M
100M
0
1
2
3
4
5
TUNNING VOLTAGE (V)
FREQUENCY OFFSET (Hz)
Figure 14. Reference Spurs vs. VTUNE (5.8 GHz,1 MHz, and 100 kHz)
Figure 11. Integrated Phase Noise (5.8 GHz,1 MHz, and 100 kHz)
–120
0
V
I
= 3V, V = 5V
P
DD
= 5mA
V
V
= 3V
REF LEVEL = –10dBm
DD
= 5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CP
P
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1
–130
–140
–150
–160
–170
–180
–65.0dBc
–66.0dBc
10k
100k
1M
10M
100M
–2M
–1M
5800
1M
2M
PHASE DETECTOR FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. Phase Noise (Referred to CP Output) vs. PFD Frequency
Figure 12. Reference Spurs (5.8 GHz,1 MHz, and 100 kHz)
–6
–5
–4
–60
V
V
= 3V
DD
= 3V
P
V
= 5V
PP
I
SETTLING = 5mA
CP
–3
–2
–1
0
–70
–80
1
2
3
–90
4
5
6
–100
0
0.5
1.0
1.5
2.0
2.5
(V)
3.0
3.5
4.0
4.5
5.0
–40
–20
0
20
40
60
80
100
V
TEMPERATURE (°C)
CP
Figure 13. Phase Noise (5.8 GHz,1 MHz, and 100 kHz) vs. Temperature
Figure 16. Charge Pump Output Characteristics
Rev. C | Page 8 of 10
Enhanced Product
ADF4106-EP
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the 20-lead LFCSP (CP-20) are rectangular. The
printed circuit board (PCB) pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized. The
bottom of the LFCSP has a central thermal pad.
Thermal vias may be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated in the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with 1 oz. copper to plug the via.
The user should connect the PCB thermal pad to AGND.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Rev. C | Page 9 of 10
ADF4106-EP
Enhanced Product
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 17. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
0.60 MAX
3.90
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.50
BSC
PIN 1
INDICATOR
2.25
2.10 SQ
1.95
EXPOSED
PAD
3.75
BCS SQ
10
6
11
0.75
0.60
0.50
0.25 MIN
BOTTOM VIEW
TOP VIEW
0.80 MAX
0.65 TYP
12° MAX
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
1.00
0.85
0.80
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 18. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−55°C to + 125°C
−55°C to + 125°C
−55°C to + 125°C
−55°C to + 125°C
Package Description
Package Option
RU-16
RU-16
CP-20-1
CP-20-1
ADF4106SRU-EP
ADF4106SRU-EP-R7
ADF4106SCPZ-EP
ADF4106SCPZ-EP-R7
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
1 Z = RoHS Compliant Part.
©2010–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09272-0-11/14(C)
Rev. C | Page 10 of 10
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