ADF4116BCPZ [ADI]
IC PLL FREQUENCY SYNTHESIZER, 550 MHz, CQCC20, CSP-20, PLL or Frequency Synthesis Circuit;
| 型号： | ADF4116BCPZ |
| 厂家： | 
ADI |
| 描述： | IC PLL FREQUENCY SYNTHESIZER, 550 MHz, CQCC20, CSP-20, PLL or Frequency Synthesis Circuit |
| 文件： | 总14页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
a
Preliminary Technical Data
PLLFrequencySynthesizer
ADF4116/ADF4117/ADF4118
FEATURES
G E NE R AL D E S C R IP T IO N
ADF4116:
ADF4117:
ADF4118:
550 MHz
1.2 GHz
2.8 GHz
T he ADF4116 family of frequency synthesizers can
be used to implement local oscillators in the up-con-
version and down-conversion sections of wireless
receivers and transmitters. T hey consist of a low-
noise digital PFD (Phase Frequency Detector), a
precision charge pump, a programmable reference
divider, programmable A and B counters and a dual-
modulus prescaler (P/P+1). T he A (5-bit) and B
(13-bit) counters, in conjunction with the dual modu-
lus prescaler (P/P+1), implement an N divider (N=
BP+A). In addition, the 14-bit reference counter (R
Counter), allows selectable REFIN frequencies at the
PFD input. A complete PLL (Phase-Locked Loop)
can be implemented if the synthesizer is used with an
external loop filter and VCO (Voltage Controlled
O scillator)
+2.7 V to +5.5 V Pow er Supply
Separate Vp Allow s Extended Tuning Voltage in
3V System s
Selectable Charge Pum p Currents
Dual Modulus Prescaler
ADF4116:
8/ 9
32/33
ADF4117/ ADF4118:
3-Wire Serial Interface
Digital Lock Detect
Pow er Dow n Mode
Fastlock Mode
APPLICATIONS
Control of all the on-chip registers is via a simple 3-
wire interface. T he devices operate with a power sup-
ply ranging from 2.7V to 5.5V and can be powered
down when not in use.
Base Stations for Wireless Radio (GSM, PCS, DCS,
WCDMA)
Wireless Handsets (GSM, PCS, DCS, WCDMA)
Wireless LANS
Com m unications Test Equipm ent
CATV Equipm ent
FUNCTIO NAL BLO CK D IAGRAM
AVDD
DVDD
VP
CPG N D
REF ERENCE
14-BIT
COUNT ER
REF IN
R
PHAS E
CHARGE
FRE QUENCY
C P
PUM P
DET ECTOR
14
R
COUNTER
LA TCH
LOCK DETECT
CLK
21-BIT
INPUT RE GISTE R
FUNCTION
LA TC H
DATA
LE
19
SDO
U T
A,
B
COUNTE
LATCH
High
Z
FROM
FUNCTION
LA TCH
AVDD
18
M UX
13
MU XOUT
N
= BP + A
13-BIT
COUNTER
SDO
U T
B
L OA D
+
-
RFIN
A
PR ESCA LER
P/P+1
RFINB
M3 M2 M1
L OA D
5-BIT
CO UNTER
A
FLo
FLo
Switch
5
ADF4116/ADF4117/ADF4118
REV.PrH 12/99
DG ND
CE
AG ND
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/ 329-470 0
Fa x: 781/ 326-8703
World Wide Web Site: http:/ / w w w.analog.com
Analog Devices, Inc., 1999
(AV = AV = +3V ± 10%, +5 V ± 10% V = AV +5
DD
DD
P
DD,
V ± 10%, ; AGND = DGND = 0 V; T = TMIN to TMAX un-
less otherwise noted)
A
1
ADF4116/7/8 – SPECIFICATIONS
P ar am eter
B Version
BChips2
Units
Test Conditions/Com m ents
(Typical)
RF C H ARAC T ERIST IC S
RF Input Frequency
AD F 4116
See Figure 3 for input circuit.
25/550
0.1/1.2
0.1/2.8
0/150
25/550
0.1/1.2
0.1/2.8
0/150
M H z min/max
G H z min/max
G H z min/max
M H z min/max
AD F 4117
AD F 4118
Reference Input Frequency
M aximum Allowable
Prescaler Output Frequency3
Phase Detector Frequency4
RF Input Sensitivity
200
55
-15/0
-10/0
-5
200
55
-15/0
-10/0
-5
M H z max
M H z max
dBm min/max AVDD = 3V
dBm min/max AVDD = 5V
Reference Input Sensitivity
dBm min
ac coupled. Max when dc
coupled: 0 to VDD (CMOS
C ompatible)
C H ARG E PU M P
IC P sink/source
H igh Value
1
250
2
1
250
2
mA typ
µA typ
%typ
Low Value
Absolute Accuracy
5
1
2
5
1
2
% m ax
nA max
% typ
IC P T hree State Current
Sink and Source Current Matching
IC P vs. VC P
See Figure 28
0.5V < VC P < VP - 0.5
0.5V < VC P < VP - 0.5
VC P = VP/2
2
2
2
2
% typ
% typ
IC P vs. T emperature
LO G IC IN PU T S
VINH, Input High Voltage
0.8*D VD D
0.2*D VD D
± 1
10
± 100
0.8*D VD D
0.2*D VD D
± 1
10
± 100
V min
V max
µA max
pF max
µA max
V
I
C
INL, Input Low Voltage
INH/IINL, Input Current
IN, Input Capacitance
Reference Input Current
LO G IC O U T P U T S
VOH, Output High Voltage
VOL, Output Low Voltage
DVDD - 0.4 DVDD - 0.4 V min
IOH = 1mA
IOL = 1mA
0.4
0.4
V max
PO WER SU PPLIES
AVDD
DVDD
2.7/5.5
AVDD
AVD D/6.0
2.7/5.5
AVDD
AVD D/6.0
V min/V max
V min/V max
VP
5
IDD (AIDD + DIDD
AD F 4116
)
See Figure 26 and 27
2.0
4.2
6.5
1
2.0
4.2
6.5
1
mA max
mA max
mA max
µA typ
AD F 4117
AD F 4118
Low Power Sleep Mode
NOTES
1. Operating temperature range is as follows: B Version: –40°C to +85°C.
2. T he BChip specifications are given as typical values.
3. T his is the maximum operating frequency of the CMOS counters. T he prescaler value should be chosen to ensure that the RF input is divided down to a frequency
which is less than this value.
4. Guaranteed by deign. Sample tested to ensure compliance.
5. AVDD = AVDD = 3V; RFIN for ADF4116 = 540MHz; RFIN for ADF4117, ADF4118 = 900MHz.
REV.PrH 12/99
–2–
(AV = AV = +3V ± 10%, +5 V ± 10% V = AV
DD,
DD
DD
P
+5 V ± 10%, ; AGND = DGND = 0 V; T = TMIN to T
unless otherwise noted)
1
A
MAX
ADF4116/7/8 – SPECIFICATIONS
P ar am eter
B Version
BChips
Units
Test Conditions/Com m ents
N O ISE C H ARAC T ERIST IC S
AD F4118 Phase N oise Floor2
-170
-162
-170
-162
dBc/H z typ
dBc/H z typ
@ 25kH z PFD Frequency
@ 200kH z PFD Frequency
@ VCO Output
Phase Noise Performance3
AD F 41164
-93
-89
-90
-82
-83
-68
-83
-93
-89
-90
-82
-83
-68
-83
dBc/H z typ
dBc/H z typ
dBc/H z typ
dBc/H z typ
dBc/H z typ
dBc/H z typ
dBc/H z typ
AD F 41175
AD F 41185
AD F 41176
AD F 41187
AD F 41188
AD F 41189
Spurious Signals
Measured at offset of fPFD/2fPFD
AD F 41164
-80/-84
-80/-84
-80/-84
-80/-84
-80/-84
-78/-82
-78/-82
-80/-84
-80/-84
-80/-84
-80/-84
-80/-84
-78/-82
-78/-82
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
dB typ
AD F 41175
AD F 41185
AD F 41176
AD F 41187
AD F 41188
AD F 41189
NOTES
1. Operating temperature range is as follows: B Version: –40°C to +85°C.
2. T he synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the divider value).
3. T he phase noise is measured with the EVAL-ADF411XEB Evaluation Board and the HP8562E Spectrum Analyzer. T he spectrum analyzer provides the REFIN for
the synthesizer. (fREFOUT = 10MHz @ 0dBm)
4. f REFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 540MHz; N = 2700; Loop B/W = 20kHz
5. f REFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900MHz; N = 4500; Loop B/W = 20kHz
6. f REFIN = 10 MHz; fPFD = 30kHz; Offset frequency = 300 Hz; fRF = 836MHz; N = 27867; Loop B/W = 3kHz
7. f REFIN = 10 MHz; fPFD = 200kHz; Offset frequency = 1 kHz; fRF = 1750MHz; N = 8750; Loop B/W = 20kHz
8. f REFIN = 10 MHz; fPFD = 10kHz; Offset frequency = 200 Hz; fRF = 1750MHz; N = 175000; Loop B/W = 1kHz
9. f REFIN = 10 MHz; fPFD = 200kHz; Offset frequency = 1 kHz; fRF = 1960MHz; N = 9800; Loop B/W = 20kHz
Specifications subject to change without notice.
O R D E R ING G U ID E
Model
Tem perature Range P ackage O ption*
AD F 4116BRU
AD F 4116BC P
AD F 4117BRU
AD F 4117BC P
AD F 4118BRU
AD F 4118BC P
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
RU -16
C P-24
RU -16
C P-24
RU -16
C P-24
*
RU = T hin Shrink Small Outline Package (T SSOP)
CP = Chip Scale Package
Contact the factoryfor chip availability
REV.PrH 12/99
–3–
ADF4116/ADF4117/ADF4118
Preliminary Technical Data
(V = +5 V 10%, +3 V ± 10%; AGND = DGND = 0 V, unless otherwise noted)
DD
TIMINGCHARACTERISTICS
Lim it at
TMIN to TMAX
P ar am eter
(B Version)
Units
Test Conditions/Com m ents
t1
t2
t3
t4
t5
t6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
DAT A to CLOCK Set Up T ime
DAT A to CLOCK H old T ime
C LOC K H igh D uration
C LOC K Low D uration
CLOCK to LE Set Up T ime
LE Pulse Width
NOTE
Guaranteed by Design but not Production T ested.
t3
t4
CLOCK
t1
t2
DB20
DATA
DB19
DB2
DB1
DB0 (LSB)
(CONTROL BIT C1)
(MSB)
(CONTROL BIT C2)
t6
LE
LE
t5
Figure 1. Tim ing Diagram
2
ABSO LUT E MAXIMUM RAT INGS1,
M aximum Junction T emperature . . . . . . . . . . . . . + 150°C
T SSOP θJA T hermal Impedance . . . . . . . . . . . 150.4°C /W
CSP θJA T hermal Impedance . . . . . . . . . . . . . . T BD °C /W
Lead T emperature, Soldering
(
T A = +25°C unless otherwise noted)
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
VP to GND . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +5.5 V
D igital I/O Voltage to GN D . . . . . –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND . . . . . . –0.3 V to Vp + 0.3 V
Operating T emperature Range
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . + 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . + 220°C
1. Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. Thisisa stressratingonlyand functionaloperation
of the device at these or any other conditions above those listed in the operational
sections ofthis specification is not implied. Exposure to absolute maximum rating
conditions for extended periods mayaffect device reliability.
2. T his device is a high-performance RF integrated circuit with an ESD rating of <
2kV and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.
Industrial (B Version) . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . –65°C to +150°C
3. AGND = DGND = GND = 0V.
C AUT IO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although this device features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges.
T herefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV.PrH 12/99
–4 –
Preliminary Technical Data
ADF4116/ADF4117/ADF4118
P IN D E S C R IP T IO N
Mnem onic
Function
F LO
Fast Lock Switch Output. T his can be used to switch an external resistor to change the loop filter band-
width. T his will speed up locking of the PLL.
C P
Charge Pump Output. T his is normally connected to a loop filter which drives the input to an external
VC O .
C P G N D
AG N D
RF IN B
Charge Pump Ground
Analog Ground
Complementary Input to the RF Prescaler. T his point should be decoupled to the ground plane with a
small bypass capacitor.
RF IN A
AVDD
Input to the RF Prescaler. T his small signal input is normally ac coupled from the VCO.
Analog Power Supply. T his may range from 2.7V to 5.5V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD
.
REF IN
Reference Input. T his is a CMOS input with a nominal threshold of AVDD /2 and an equivalent input
resistance of 100kΩ. See Figure 2. T he oscillator input can be driven from a T T L or CMOS crystal
oscillator or it can be ac coupled.
D G N D
C E
D igital G round.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. T aking the pin high will power up the device depending on the status of the power-
down bit F2.
C L K
Serial Clock Input. T his serial clock is used to clock in the serial data to the registers. T he data is
latched into the 21-bit shift register on the CLK rising edge. T his input is a high impedance CMOS
input.
D AT A
L E
Serial Data Input. T he serial data is loaded MSB first with the two LSBs being the control bits. T his
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches, the latch being selected using the control bits.
M U X O U T 1
DVDD
T his multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency
to be accessed externally.
Digital Power Supply. T his may range from 2.7V to 5.5V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD
.
VP
Charge Pump Power Supply. T his should be greater than or equal to VDD. In systems where VDD is 3V, it
can be set to 5V and used to drive a VCO with a tuning range of up to 5V
NOTES
1. MUXOUT is also used for T est Modes on the devices. T hese T est modes will be detailed in T NXXX available from Analog Devices Inc.
P IN C O NF IG U R AT IO N
T O P VIE W
T O P VIE W
CP FL
V
DV
DV
D D D D
o
P
VP
FLO
CP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
20 19 18
17 16
DVDD
TSSOP
CPGND
AGND
AGND
1
2
3
4
5
MUXOUT
LE
15
14
13
12
11
Chip Scale Package
CPGND
AGND
RFINB
MUXOUT
LE
ADF4116
ADF4117
ADF4118
DATA
CLK
ADF4116
ADF4117
ADF4118
DATA
CLK
RF
RF
B
A
IN
RFIN
A
CE
IN
AVDD
10 CE
6
7
8
9
10
DGND
REFIN
9
AV AV REF DGND DGND
D D
D D
IN
TRANSISTO R CO UNT:
6425 (CMOS) and 303 (Bi-
polar).
REV.PrH 12/99
–5 –
ADF4116/ADF4117/ADF4118
Preliminary Technical Data
C IR C U IT D E S C R IP T IO N
P R E S C ALE R
R E F E R E NC E INP U T SE C T IO N
T he Reference Input stage is shown below in Figure 2.
SW1 and SW2 are normally-closed switches. SW3 is
T he dual-modulus prescaler takes the CML clock from
the RF input stage and divides it down to a manageable
frequency for the CMOS A and B counters. T he
prescaler is set to 8/9 for the ADF4116, and set to 32/33
for the ADF4117 & ADF4118. It is based on a synchro-
nous 4/5 core.
Powerdown
Control
A AND B C O UNTE RS
T he A and B CMOS counters combine with the dual
modulus prescaler to allow a wide ranging division ratio
in the PLL feedback counter. T he counters are guaranteed
to work when the prescaler output is 200MHz or less.
T ypically, they will work with 250MHz output from the
prescaler.
100k
Ω
NC
SW2
REFIN
To R Counter
NC
SW1
Buffer
SW3
NO
P u lse Swallow F u n ction
T he A and B counters, in conjunction with the dual modu-
lus prescaler make it possible to generate output frequen-
cies which are spaced only by the Reference Frequency
divided by R . T he equation for the VCO frequency is as
follows:
Figure 2. Reference Input Stage
fVCO = [(P x B) + A] x fREFIN /R
normally-open. When Powerdown is initiated, SW3 is
closed and SW1 and SW2 are opened. T his ensures that
there is no loading of the REFIN pin on powerdown.
fVCO
:
Ouput Frequency of external voltage controlled
oscillator (VC O).
P :
Preset modulus of dual modulus prescaler.
RF INP UT STAGE
B :
Preset Divide Ratio of binary 13-bit counter (3 to
8191).
T he RF input stage is shown in Figure 3. It is followed
by a 2-stage limiting amplifier to generate the CML clock
levels needed for the prescaler.
A:
Preset Divide Ratio of binary 5-bit swallow
counter (0 to 31).
fREFIN: Ouput frequency of the external reference
frequency oscillator.
1.6V
Bias
Generator
R :
Preset divide ratio of binary 14-bit
programmable reference counter (1 to 16383)
AV
DD
500 Ω
500 Ω
R C O U N T ER
T he 14-bit R counter allows the input reference frequency
to be divided down to produce the input clock to the phase
frequency detector (PFD). Division ratios from 1 to
16,383 are allowed.
RF
RF
A
B
IN
IN
N = BP + A
13-BIT B
COUNTER
To PFD
From RF
Input Stage
LOAD
AGND
PRESCALER
P/P+1
LOAD
5-BIT A
COUNTER
Figure 3. RF Input Stage
Modulus
Control
Figure 4. A and B Counters
REV.PrH 12/99
–6 –
Preliminary Technical Data
ADF4116/ADF4117/ADF4118
P H ASE F RE Q UE NC Y D E T E C T O R (P F D ) AND
C H AR G E P U M P
DVDD
T he PFD takes inputs from the R counter and N counter
and produces an output proportional to the phase and
frequency difference between them. Figure 5 is a simpli-
fied schematic. T he PFD includes a fixed delay element
Analog Lock Detect
Digital Lock Detect
R
N
Counter Output
Counter Output
M UX
UP
CONTROL
MUXOUT
HI
D1
Q1
SDOUT
U1
+ IN
CLR1
DGND
CHARGE
PUMP
U3
CP
Figure 6. MUXOUT Circuit
INP UT SH IF T RE G IST E R
CLR2
U2
T he ADF4116 family digital section includes a 21-bit
input shift register, a 14-bit R counter and a 18-bit N
counter, comprising a 5-bit A counter and a 13-bit B
counter. Data is clocked into the 21-bit shift register on
each rising edge of CLK. T he data is clocked in MSB
first. Data is transferred from the shift register to one of
four latches on the rising edge of LE. T he destination
latch is determined by the state of the two control bits
(C2, C1) in the shift register. T hese are the two lsb's
DB1, DB0 as shown in the timing diagram of Figure 1.
T he truth table for these bits is shown in T able 6. T able 1
shows a summary of how the latches are programmed.
DOWN
HI
D2
Q2
- IN
Figure 5. PFD Sim plified Schem atic
which sets the width of the anti-backlash pulse. T his is
typically 3ns. T his pulse ensures that there is no deadzone
in the PFD transfer function and gives a consistent refer-
ence spur level.
M UXO UT AND LO C K D E T E C T
T he output multiplexer on the ADF4116 family allows
the user to access various internal points on the chip. T he
state of MUXOUT is controlled by M3, M2 and M1 in
the Function Latch. T able 5 shows the full truth table.
Figure 6 shows the MUXOUT section in block diagram
form.
Table 1. C2, C1 Tr uth Table
C on tr ol Bits
C 2
C 1
D a ta La tch
0
0
1
1
0
1
0
1
R Counter
N Counter (A and B)
Function Latch
Initialization Latch
Lock D etect
MUXOUT can be programmed for two types of lock
detect:
Digital Lock Detect and Analog Lock Detect
Digital Lock Detect is active high. It is set high when the
phase error on three consecutive Phase Detector cycles is
less than 15ns. It will stay set high until a phase error of
greater than 25ns is detected on any subsequent PD cycle.
T he N-channel open-drain analog lock detect should be
operated with an external pull-up resistor of 10k nominal.
When lock has been detected it is high with narrow low-
going pulses.
REV.PrH 12/99
–7 –
ADF4116/ADF4117/ADF4118
Preliminary Technical Data
Table 2. AD F4116 Fam ily Latch Sum m ar y
Reference Counter Latch
Test
Mode Bits
Control
Bits
14-Bit Reference Counter
DB20 DB19 DB18 DB17 DB16
DB15 DB14 DB13 DB12 DB11 DB10
R14 R13 R12 R11 R10 R9
DB9
R8
DB8
R7
DB7
R6
DB6
R5
DB5
R4
DB4
R3
DB3
R2
DB2
R1
DB1
DB0
LDP
T4
T3
T2
T1
C2 (0) C1 (0)
N Counter Latch
Control
Bits
13-Bit B Counter
5-Bit A Counter
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12
B13 B12 B11 B10 B9 B8 B7 B6
DB11 DB10 DB9
B5 B4 B3
DB8
B2
DB7
B1
DB6
A5
DB5
A4
DB4
A3
DB3
A2
DB2
A1
DB1
DB0
DB20
G1
C2 (0) C1 (1)
Function Latch
Timer Counter
Control
MUXOUT
Control
Control
Bits
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12
TC4
DB11 DB10 DB9
F6
DB8
F3
DB7
F2
DB6
M3
DB5
M2
DB4
M1
DB3
PD1
DB2
F1
DB1
DB0
F4
PD2
F5
TC3
TC2
TC1
C2 (1) C1 (0)
Initialization Latch
Timer Counter
Control
MUXOUT
Control
Control
Bits
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12
TC4
DB11 DB10 DB9
F6
DB8
F3
DB7
F2
DB6
M3
DB5
M2
DB4
M1
DB3
PD1
DB2
F1
DB1
DB0
PD2
TC3
TC2
TC1
F5
F4
C2 (1) C1 (1)
REV.PrH 12/99
–8 –
Preliminary Technical Data
ADF4116/ADF4117/ADF4118
R E F E R E NC E C O U NT E R LAT C H
Table 3. Refer ence Counter Latch Map
Test
Mode Bits
Control
Bits
14-Bit Reference Counter
DB20 DB19 DB18 DB17 DB16
LDP T4 T3 T2 T1
DB15 DB14 DB13 DB12 DB11 DB10
R14 R13 R12 R11 R10 R9
DB9
R8
DB8
R7
DB7
R6
DB6
R5
DB5
R4
DB4
R3
DB3
R2
DB2
R1
DB1
DB0
C2 (0) C1 (0)
R14
R13
R12
..........
R3
R2
0
1
1
0
.
R1
Divide Ratio
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
0
0
0
1
.
1
0
1
0
.
1
2
3
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
0
0
16380
1
1
1
1
1
1
1
1
1
..........
..........
..........
1
1
1
0
1
1
1
0
1
16381
16382
16383
Test M ode Bits should
be set to 0000 for
Normal Operation
LDP
0
Operation
3 consecutive cycles of phase delay less than
15ns must occur before lock detect is set.
5 consecutive cycles of phase delay less than
15ns must occur before lock detect is set.
1
REV.PrH 12/99
–9 –
ADF4116/ADF4117/ADF4118
Preliminary Technical Data
N C O U NT E R LAT C H
Table 4. N Counter Latch Map
Control
Bits
13-Bit B Counter
5-Bit A Counter
DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12
DB11 DB10 DB9
DB8
B2
DB7
B1
DB6
A5
DB5
A4
DB4
A3
DB3
A2
DB2
A1
DB1
DB0
DB20
G1
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
C2 (0) C1 (1)
A5
A4
A3
A2
A1
A Counter
Divide Ratio
X
X
.
X
X
.
0
0
.
0
0
.
0
1
.
0
1
.
ADF4116
.
.
.
.
.
.
X
X
X
X
1
1
1
1
0
1
6
7
A5
A4
A3
A2
A1
A Counter
Divide Ratio
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
0
1
2
.
ADF4117 / ADF4118
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
29
30
31
B13
B12
B11
B3
0
0
0
1
.
B2
0
1
1
0
.
B1
B Counter Divide Ratio
0
0
0
0
.
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
1
0
1
0
.
1
2
3
4
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
0
0
8188
1
1
1
1
1
1
1
1
1
..........
..........
..........
1
1
1
0
1
1
1
0
1
8189
8190
8191
G1
0
Current Setting
250uA
1
1mA
N = BP + A, P is prescaler value set in the Function Latch
B must be greater than or equal to A
For contiguous values of N, NM IN is (P2 - P)
REV.PrH 12/99
–1 0 –
Preliminary Technical Data
ADF4116/ADF4117/ADF4118
F U NC T IO N LAT C H
Table 5. Function Latch Map
Timer Counter
Control
MUXOUT
Control
Control
Bits
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
F3
DB7
F2
DB6
M3
DB5
M2
DB4
M1
DB3
PD1
DB2
F1
DB1
DB0
F6
TC4
PD2
TC3
TC2
TC1
F5
F4
C2 (1) C1 (0)
F1
Counter
Operation
Normal
0
1
R, A,
B Counter
Held in Reset
CE Pin
PD2
PD1
M ode
0
1
1
1
X
X
0
1
X
0
1
1
Asynchronous P ower-Down
Normal O peration
M 3
0
M 2
0
M 1
0
Output
3-State Outp ut
Digital Lock Detect
(Active High)
Asynchronous P ower-Down
Synchronous P ow er-Down
0
0
1
0
0
1
1
1
1
0
0
0
1
0
1
N
Divider Output
AVDD
R
Divider Output
N-Channel O pen-Drain
Lock Detect
Serial Data Output
DGN D
1
1
1
1
0
1
F3
PD Polarity
0
1
Negative
Positive
F3
Charge Pump
Output
0
1
Normal
3-State
F4
0
F6
X
Fastlock M ode
Fastlock Disabled
1
0
Fastlock M ode
Fastlock M ode
1
2
1
1
TC4
TC3
TC2
TC1
Tim eout
(P FD Cycles)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
REV.PrH 12/99
–1 1 –
ADF4116/ADF4117/ADF4118
Preliminary Technical Data
INIT IALIZAT IO N LAT C H
Table 6. Initialization Latch Map
Timer Counter
Control
M UXO UT
Control
Control
Bits
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
F3
DB7
F2
DB6
M3
DB5
M2
DB4
M1
DB3
PD1
DB2
F1
DB1
DB0
F6
TC4
F5
F4
PD2
TC3
TC2
TC1
C2 (1) C1 (1)
F1
Counter
Operation
Normal
0
1
R, A,
B Counters
Held in Reset
CE Pi
PD2
PD1
M ode
M 3
0
M 2
0
M 1
0
Output
0
1
1
1
X
X
0
1
X
0
1
1
Asynchronous Power-Down
Normal Operation
3-S tate Output
Digital Lock Detect
(Active High)
0
0
1
Asynchronous Power-Down
Synchronous Power-Down
0
0
1
1
0
1
N
Divider Output
AVDD
1
1
0
0
0
1
R
Divider Output
N-Channel Open-Drain
Lock Detect
Serial Data Output
DGN D
1
1
1
1
0
1
F3
PD Polarity
0
1
Negative
Positive
F3
Charge Pump
Output
0
1
Normal
3-S tate
F4
0
F6
X
Fastlock Mode
Fastlock Disabled
1
0
Fastlock Mode
Fastlock Mode
1
2
1
1
TC4
TC3
TC2
TC1
Timeout
(PFD Cycles)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
REV.PrH 12/99
–1 2 –
Preliminary Technical Data
ADF4116/ADF4117/ADF4118
F astlock E nable Bit
T H E F UNC T IO N LAT C H
DB9 of the Function Latch is the Fastlock Enable Bit.
Only when this is “1” is Fastlock enabled.
With C2, C1 set to 1,0, the on-chip function latch will be
programmed. T able 5 shows the input data format for
programming the Function Latch.
Fastlock Mode Bit
DB11 of the Function Latch is the Fastlock Mode bit.
When Fastlock is enabled, this bit determines which
Fastlock Mode is used. If the Fastlock Mode bit is “0”
then Fastlock Mode 1 is selected and if the Fastlock
Mode bit is “1”, then Fastlock Mode 2 is selected.
If Fastlock is not enabled (DB9 = “0”), then DB11
(ADF4116) determines the state of the FLO output. FLO
state will be the same as that programmed to DB11.
Counter Reset
DB2 (F1) is the counter reset bit. When this is “1”, the
R counter and the A,B counters are reset. For normal
operation this bit should be “0”. Upon powering up, the F1 bit
needs to be disabled, the N counter resumes counting in “close” align-
ment with the R counter. (The maximum error is one prescaler cycle).
P ower D own
DB3 (PD1) and DB19 (PD2) on the ADF4116, provide
programmable power-down modes. T hey are enabled by
the CE pin.
When the CE pin is low, the device is immediately dis-
abled regardless of the states of PD2, PD1.
Fa stlock Mode 1
In the ADF4116 family, the output level of FLO is pro-
grammed to a low state and the charge pump current is
switched to the high value (1mA). FLO is used to switch a
resistor in the loop filter and ensure stability while in
Fastlock by altering the loop bandwidth.
In the programmed asynchronous power-down, the device
powers down immediately after latching a “1” into bit
PD1, with the condition that PD2 has been loaded with a
“ 0” .
T he device enters Fastlock by having a “1” written to the
CP Gain bit in the N register. T he device exits Fastlock
by having a “0” written to the CP Gain bit in the N regis-
ter.
In the programmed synchronous power-down, the device
power down is gated by the charge pump to prevent un-
wanted frequency jumps. Once the power-down is enabled
by writing a “1” into bit PD1 (on condition that a “1” has
also been loaded to PD2), then the device will go into
power-down after the first successive charge pump event.
Fa stlock Mode 2
In the ADF4116 family, the output level of FLO is pro-
grammed to a low state and the charge pump current is
switched to the high value (1mA). FLO is used to switch a
resistor in the loop filter and ensure stability while in
Fastlock by altering the loop bandwidth.
When a power down is activated (either synchronous or
asynchronous mode including CE-pin-activated power
down), the following events occur:
T he device enters Fastlock by having a “1” written to the
CP Gain bit in the N register. T he device exits Fastlock
under the control of the T imer Counter. After the
timeout period determined by the value in T C4 - T C1,
the CP Gain bit in the N register is automatically reset to
“0” and the device reverts to normal mode instead of
F astlock.
All active DC current paths are removed.
T he R, N and timeout counters are forced to their load
state conditions.
T he charge pump is forced into three-state mode.
T he digital clock detect circuitry is reset.
T he RFIN input is debiased.
T he oscillator input buffer circuitry is disabled.
T he input register remains active and capable of loading
and latching data.
M U XO U T C on t r ol
T he on-chip multiplexer is controlled by M3, M2 and
M1 on the an ADF4116 family. T able 5 shows the truth
table.
P h a se D etector P ola r ity
DB7 (F2) of the function latch sets the Phase Detector
Polarity. When the VCO characteristics are positive this
should be set to “1”. When they are negative it should be
set to “0”.
C h a r ge P u m p T h r ee- Sta te
T his bit puts the charge pump into three-state mode when
programmed to a “1”. It should be set to “0” for normal
operation.
REV.PrH 12/99
–1 3 –
ADF4116/ADF4117/ADF4118
Preliminary Technical Data
In itia liza tion La tch Meth od .
Tim er Counter Contr ol
In the ADF4116 family, the user has the option of switch-
ing between two charge pump current values to speed up
locking to a new frequency.
Apply VDD
.
Program the Initialization Latch (“11” in 2 lsb’s of input
word). Make sure that F1bit is programmed to “0”.
T hen do an R load (“00” in 2 lsb’s).
T hen do an N load (“01” in 2 lsb’s).
When the Initialisation Latch is loaded, the following
occurs:
When using the Fastlock feature with the ADF4116 fam-
ily, the normal sequence of events is as follows:
T he user must make sure that Fastlock is enabled. Set
DB9 of the ADF4116 family to “1”. T he user must also
choose which Fastlock Mode to use. As discussed in the
previous section, Fastlock Mode 2 uses the values in the
T imer Counter to determine the timeout period before
reverting to normal mode operation after Fastlock.
Fastlock Mode 2 is chosen by setting DB11 of the
ADF4116 family to “1”.
1. T he function latch contents are loaded.
2. An internal pulse resets the R, N and timeout counters
to load state conditions and also tri-states the charge
pump. Note that the prescaler bandgpap reference and
the oscillator input buffer are unaffected by the internal
reset pulse, allowing close phase alignment when counting
resumes.
3. Latching the first N counter data after the initialisation
word will activate the same internal reset pulse. Succes-
sive N loads will not trigger the internal reset pulse unless
there is another initialisation.
T he user must also decide how long they want the high
current (1mA) to stay active before reverting to low cur-
rent (250uA). T his is controlled by the T imer Counter
Control Bits DB14 to DB11 (T C4 - T C1) in the Func-
tion Latch. T he truth table is given in T able 5.
The CE pin Method.
Now, when the user wishes to program a new output fre-
quency, they can simply program the A,B counter latch
with new values for A and B. At the same time they can
set the CP Gain bit to a “1” ,which sets the charge pump
1mA for a period of time determined by T C4 - T C1.
When this time is up, the charge pump current reverts to
250uA. At the same time the CP Gain Bit in the A, B
Counter latch is reset to 0 and is now ready for the next
time that the user wishes to change the frequency again.
Apply VDD
.
Bring CE low to put the device into power-down. T his is
an asychronous power-down in that it happens immedi-
ately.
Program the Function Latch (10).
Program the R Counter Latch (00).
Program the N Counter Latch (01).
Bring CE high to take the device out of power-down.
T he R and N counter will now resume counting in close
alignment.
Note that after CE goes high, a duration of 1us may be
required for the prescaler bandgap voltage and oscillator
input buffer bias to reach steady state.
CE can be used to power the device up and down in order
to check for channel activity. T he input register does not
need to be reprogrammed each time the device is disabled
and enabled as long as it has been programmed at least
once after Vcc was initially applied.
T h e In itia liza tion La tch
When C2, C1 = 1, 1 then the Initialization Latch is pro-
grammed. T his is essentially the same as the Function
Latch (programmed when C2, C1 = 1, 0).
H owever, when the Initialization Latch is programmed
there is a additional internal reset pulse applied to the R
and N counters. T his pulse ensures that the N counter is
at load point when the N counter data is latched and the
device will begin counting in close phase alignment.
The Cou n ter Reset Method
Apply VDD
.
If the Latch is programmed for synchronous powerdown
(CE pin is High; PD1 bit is High; PD2 bit is Low), the
internal pulse also triggers this powerdown. T he prescaler
reference and the oscillator input buffer are unaffected by
the internal reset pulse and so close phase alignment is
maintained when counting resumes.
Do a Function Latch Load (“10” in 2 lsb’s). As part of
this, load “1” to the F1 bit. T his enables the counter re-
set.
Do an R Counter Load (“00” in 2 lsb’s).
Do an N Counter Load (“01” in 2 lsb’s).
Do a Function Latch Load (“10” in 2 lsb’s). As part of
this, load “0” to the F1 bit. T his disables the counter
reset.
T his sequence provides the same close alignment as the
initialization method. It offers direct control over the
internal reset. Note that counter reset holds the counters at
load point and tri-states the charge pump, but does not
trigger synchronous power-down. T he counter reset
method requires an extra function latch load compared to
the initialization latch method.
When the first N counter data is latched after initializa-
tion, the internal reset pulse is again activated. However,
successive N counter loads after this will not trigger the
internal reset pulse.
D evice P r ogr am m in g After In itial P ower - Up.
After initially powering up the device, there are three ways
to program the device.
REV.PrH 12/99
–1 4 –
相关型号：
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