ADF4152HVBCPZ [ADI]
High Voltage, Fractional-N/Integer N PLL Synthesizer;
| 型号： | ADF4152HVBCPZ |
| 厂家： | 
ADI |
| 描述： | High Voltage, Fractional-N/Integer N PLL Synthesizer |
| 文件： | 总27页 (文件大小：634K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage, Fractional-N/
Integer N PLL Synthesizer
Data Sheet
ADF4152HV
FEATURES
GENERAL DESCRIPTION
Fractional-N synthesizer and integer N synthesizer
High voltage charge pump: VP = 6.0 V to 30 V
Radio frequency (RF) bandwidth to 5.0 GHz
Programmable output divider
Synthesizer power supply: 3.0 V to 3.6 V
Programmable dual-modulus prescaler
Programmable output power level
Programmable charge pump currents
RF output mute function
The ADF4152HV is a 5.0 GHz, fractional-N or integer N
frequency synthesizer with an integrated high voltage charge
pump. The synthesizer can drive external wideband voltage
controlled oscillators (VCOs) directly, eliminating the need for
operational amplifiers to achieve higher tuning voltages. The
integrated high voltage charge pump simplifies design and
reduces cost while improving phase noise, in contrast to active
filter topologies, which tend to degrade phase noise compared
to passive filter topologies.
3-wire serial interface
Analog and digital lock detect
The VCO frequency can be divided by 1, 2, 4, 8, or 16 to allow
the user to generate RF output frequencies as low as 31.25 MHz.
For applications that require isolation, the RF output stage can be
muted. The mute function is both pin and software controllable.
APPLICATIONS
Wireless infrastructure
Microwave point to point/point to multipoint radios
Very small aperture terminal (VSAT) radios
Test equipment
A simple 3-wire interface controls all on-chip registers. The
charge pump operates from a power supply ranging from 6.0 V
to 30 V, whereas the rest of the device operates from 3.0 V to
3.6 V. The ADF4152HV can be powered down when not in use.
Private land mobile radios
FUNCTIONAL BLOCK DIAGRAM
SDV
AV
DV
V
R
SET
DD
DD
DD
P
MULTIPLEXER
MUXOUT
LD
10-BIT R
COUNTER
÷2
DIVIDER
×2
REF
DOUBLER
IN
LOCK
DETECT
CLK
DATA
LE
DATA REGISTER
HIGH VOLTAGE
CHARGE
FUNCTION
LATCH
CP
OUT
PUMP
PHASE
COMPARATOR
BOOST
MODE
CURRENT
SETTING
RF
RF
+
–
OUT
OUTPUT
STAGE
÷1/÷2/
÷4/÷8/÷16
INTEGER
VALUE
FRACTION
VALUE
MODULUS
VALUE
OUT
PDB
RF
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
RF
+
–
RF
INPUT
IN
MULTIPLEXER
RF
IN
N COUNTER
ADF4152HV
CE
GND
CP
SD
GND
GND
Figure 1.
Rev. 0
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Tel: 781.329.4700
Technical Support
©2016 Analog Devices, Inc. All rights reserved.
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ADF4152HV
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 0 ..................................................................................... 14
Register 1 ..................................................................................... 15
Register 2 ..................................................................................... 16
Register 3 ..................................................................................... 18
Register 4 ..................................................................................... 19
Register 5 ..................................................................................... 20
Register Initialization Sequence ............................................... 20
RF Synthesizer—A Worked Example...................................... 20
Reference Doubler and Reference Divider ............................. 21
12-Bit Programmable Modulus................................................ 21
Spurious Optimization and Boost Mode ................................ 21
Spur Mechanisms ....................................................................... 21
Spur Consistency and Fractional Spur Optimization ........... 22
Phase Resync............................................................................... 22
Applications Information .............................................................. 23
Ultrawideband PLL.................................................................... 23
Microwave PLL........................................................................... 23
Generating the High Voltage Supply ....................................... 24
Interfacing to the ADuC702x and the ADSP-BF527 ............ 25
PCB Design Guidelines for a Chip Scale Package ................. 25
Output Matching........................................................................ 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 11
Reference Input Section............................................................. 11
RF N Divider............................................................................... 11
Phase Frequency Detector (PFD) and High Voltage Charge
Pump ............................................................................................ 11
MUXOUT and Lock Detect...................................................... 12
Input Shift Registers................................................................... 12
Program Modes .......................................................................... 12
Output Stage................................................................................ 12
Register Maps.................................................................................. 13
REVISION HISTORY
7/2016—Revision 0: Initial Version
Rev. 0 | Page 2 of 27
Data Sheet
ADF4152HV
SPECIFICATIONS
AVDD = DVDD = SDVDD = 3.3 V 10%; VP = 6.0 V to 30 V; GND = 0 V; operating temperature range is TA = −40°C to +85°C, unless
otherwise noted. VCP is the voltage at the CPOUT pin.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFIN CHARACTERISTICS
Input Frequency
10
10
300
30
MHz
MHz
For f < 10 MHz, ensure slew rate > 21 V/µs
Reference doubler enabled (DB25 bit in
Register 2 is set to 1)
Input Sensitivity
Input Capacitance
Input Current
0.7
AVDD
5.0
±±0
V p-p
pF
µA
Biased at AVDD/2; ac coupling ensures AVDD/2 bias
RF INPUT CHARACTERISTICS
For lower RFIN± frequencies, ensure slew
rate > 400 V/µs
RF Input Frequency (RFIN±)
RF Output Buffer Disabled
0.5
0.5
0.5
0.5
4.0
5.0
3.5
3.0
GHz
GHz
GHz
GHz
−10 dBm ≤ RF input power ≤ +5 dBm
−5 dBm ≤ RF input power ≤ +5 dBm
−10 dBm ≤ RF input power ≤ +5 dBm
−10 dBm ≤ RF input power ≤ +5 dBm
RF Output Buffer Enabled
RF Output Buffer and Dividers
Enabled
Prescaler Output Frequency
PHASE DETECTOR
750
MHz
Phase Detector Frequency
2±
20
2±
MHz
MHz
MHz
Low noise mode
Low spur mode
Integer N mode
HIGH VOLTAGE CHARGE PUMP
Charge Pump Current, ICP
Sink/Source
High Value
Low Value
High Value vs. RSET
384
48
µA
µA
µA
µA
kΩ
%
%
%
%
nA
RSET = 5.1 kΩ
RSET = 5.1 kΩ
RSET = 10 kΩ
RSET = 3.3 kΩ
19±
3.3
594
10
RSET Range
Sink and Source Current Matching
Absolute ICP Accuracy
ICP vs. VCP
ICP vs. Temperature
ICP Leakage
±
3
2.5
2.5
2.5
1.0 V ≤ VCP ≤ (VP − 1.0 V); VP = ± V to 30 V
1.0 V ≤ VCP ≤ (VP − 1.0 V)
VCP = VP/2
VCP = VP/2
LOGIC INPUTS
Input Voltage
High, VINH
2.0
V
Low, VINL
0.±
V
Input Current, IINH/IINL
Input Capacitance, CIN
LOGIC OUTPUTS
Output Voltage
High, VOH
±1
15.0
µA
pF
DVDD − 0.4
V
V
CMOS output selected
IOL = 500 µA
Low, VOL
0.4
Output High Current, IOH
500
µA
Rev. 0 | Page 3 of 27
ADF4152HV
Data Sheet
Parameter
POWER SUPPLIES
AVDD
DVDD, SDVDD
VP
Min
3.0
Typ
Max
3.±
Unit
Test Conditions/Comments
V
V
V
AVDD
±.0
30
Set the VP supply at least 1 V above the
maximum desired tuning voltage
IP
1
50
± to 24
2.5
±0
mA
mA
mA
VP = 30 V
1
IDVDD + ISDVDD + IAVDD
Current per Output Divider
Each output divide by 2 consumes ± mA
typical
RF output stage is programmable
2
IRFOUT
20
1
32
mA
µA
Low Power Sleep Mode
RF OUTPUT CHARACTERISTICS
Output Frequency Using RF Output
Dividers
31.25
MHz
500 MHz VCO input and divide by 1± selected
Second-Order Harmonic Distortion
−19
−20
−13
−10
−4
dBc
dBc
dBc
dBc
dBm
dBm
dB
Fundamental VCO output
Divided VCO output
Fundamental VCO output
Divided VCO output
Programmable in 3 dB steps
Programmable in 3 dB steps
Pull-up supply on Pin 18 and Pin 19 varied
from 3.0 V to 3.± V
Third-Order Harmonic Distortion
Minimum RF Output Power(RFOUT±)2
Maximum RF Output Power(RFOUT±)2
Output Power Variation vs. Supply
5
±1
Output Power Variation vs. Temperature
Level of Signal with RF Mute Enabled
NOISE CHARACTERISTICS
±1
−37
dB
dBm
From −40°C to +85°C
PDBRF pin brought low; RFOUT± = 2 GHz
Normalized In-Band Phase Noise Floor
−213
dBc/Hz
Low noise mode
3
(PNSYNTH
)
−203
−113
−108
−155
−70
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
Low spur mode
Low noise mode
Low spur mode
Measured at 10 MHz offset
At RFOUT+/RFOUT− pins
Normalized 1/f Phase Noise (PN1_f)4
RF Output Divider Noise Floor
Spurious Signals Due to Phase
Frequency Detector (PFD) Frequency
−85
dBc
At VCO output
1 TA = 25°C; AVDD = DVDD = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 25 MHz; fRF = 1.75 GHz.
2 Using 50 Ω resistors to AVDD, into a 50 Ω load.
3 This figure can be used to calculate phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
PNSYNTH = PNTOT − 10 log(fPFD) − 20 log N
where PNTOT is the measured in-band phase noise at the VCO output.
4 The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The flicker noise is specified at a 10 kHz offset and normalized to 1 GHz. The
formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at a frequency offset (f) is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both
the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
Rev. 0 | Page 4 of 27
Data Sheet
ADF4152HV
TIMING CHARACTERISTICS
AVDD = DVDD = SDVDD = 3.3 V ꢀ10% VP = 6.1 V to 31 V% GND = 1 V% operating temperature range is TA = −41°C to +85°C, unless
otherwise noted.
Table 2.
Parameter
Limit
20
10
10
25
25
10
20
Unit
Description
t1
t2
t3
t4
t5
t6
t7
ns min
ns min
ns min
ns min
ns min
ns min
ns min
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Timing Diagram
t4
t5
CLK
t2
t3
DB2
(CONTROL BIT C3)
DB1
DB0 (LSB)
(CONTROL BIT C1)
DB31 (MSB)
DB30
DATA
LE
(CONTROL BIT C2)
t7
t1
t6
LE
Figure 2. Timing Diagram
Rev. 0 | Page 5 of 27
ADF4152HV
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
TRANSISTOR COUNT
The transistor count for the ADF4152HV is 23,380 (CMOS)
and 809 (bipolar).
Table 3.
Parameter
AVDD to GND1
AVDD to DVDD
VP to GND1
Rating
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−0.3 V to +33 V
−0.3 V to AVDD + 0.3 V
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required. θJA is the natural convection
junction to ambient thermal resistance measured in a one cubic
foot sealed enclosure.
Digital Input/Output (I/O) Voltage to
GND1
Analog I/O Voltage to GND1
REFIN to GND1
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +85°C
−±5°C to +125°C
150°C
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Reflow Soldering
Table 4. Thermal Resistance
Package Type
θJA
Unit
CP-32-11
27.3
°C/W
Peak Temperature
Time at Peak Temperature
2±0°C
40 sec
ESD CAUTION
1 GND = CPGND = SDGND = 0 V.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page ± of 27
Data Sheet
ADF4152HV
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND 1
24 GND
23
2
CLK
GND
22 DV
DATA 3
LE 4
DD
ADF4152H
V
21 PDB
RF
TOP VIEW
(Not to Scale)
5
6
20
19
18 RF
CE
AV
RF
DD
V
+
–
P
OUT
OUT
GND 7
GND 8
17 GND
NOTES
1. THE LFCSP HAS AN EXPOSED PAD
THAT MUST BE CONNECTED TO GND.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
Ground. Tie all ground pins together.
1, 7, 8, 12, 1±, 17, GND
23, 24, 30, 32
2
3
4
5
±
CLK
DATA
LE
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a
high impedance CMOS input.
Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into the register
that is selected by the three control bits. This input is a high impedance CMOS input.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state
mode. A logic high on this pin powers up the device.
High Voltage Charge Pump Power Supply. Place decoupling capacitors to the ground plane as close to
this pin as possible. The decoupling capacitors must have the appropriate voltage rating (a value of
10 µF is recommended). Take care to ensure that VP does not exceed the absolute maximum ratings on
power-up (see Table 3). A 10 Ω series resistor can significantly reduce voltage overshoot with minimal
voltage drop.
CE
VP
9
CPOUT
High Voltage Charge Pump Output. When enabled, this output provides ±ICP to the external passive loop
filter. The output of the loop filter is connected to the voltage tuning port of the external VCO.
10
11, 13, 20
CPGND
AVDD
High Voltage Charge Pump Ground. Tie all ground pins together.
Analog Power Supply. This pin ranges from 3.0 V to 3.± V. Place decoupling capacitors to the ground
plane as close to this pin as possible. AVDD must have the same value as DVDD.
14
15
RFIN+
RFIN−
Positive RF Input. The output of the VCO or external prescaler must be ac-coupled to this pin.
Complementary RF Input. If a single-ended input is required, this pin can be tied to ground via a 100 pF
capacitor.
18
19
RFOUT
RFOUT
−
Divided Down Output of RFIN−. This pin can be left unconnected if the divider functionality is not
required.
Divided Down Output of RFIN+. This pin can be left unconnected if the divider functionality is not
required.
+
21
22
PDBRF
DVDD
RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
Digital Power Supply. Place decoupling capacitors to the ground plane as close to this pin as possible.
DVDD must have the same value as AVDD.
25
2±
REFIN
LD
Reference Input. This CMOS input has a nominal threshold of AVDD/2 and a dc equivalent input resistance
of 100 kΩ. This input can be driven from a thermally compensated crystal oscillator (TCXO) or other
reference.
Lock Detect Output. A logic high output on this pin indicates a phase-locked loop (PLL) lock. A logic low
output indicates loss of PLL lock.
Rev. 0 | Page 7 of 27
ADF4152HV
Data Sheet
Pin No.
Mnemonic
Description
27
MUXOUT
Multiplexer Output. The multiplexer output allows the lock detect, the N divider value, or the R counter
value to be accessed externally.
28
SDVDD
Digital Σ-Δ Modulator Power Supply. Place decoupling capacitors to the ground plane as close to this
pin as possible. SDVDD must have the same value as AVDD.
29
31
SDGND
RSET
Digital Σ-Δ Modulator Ground. Tie all ground pins together.
Bias Current Resistor. Connecting a resistor between this pin and GND sets the charge pump output
current. Place the resistor as close to this pin as possible. The nominal voltage bias at the RSET pin is 0.55 V.
The relationship between ICP and RSET is as follows:
ICP = 1.9±/RSET
where:
RSET = 5.1 kΩ.
ICP = 384 µA.
EP
Exposed Pad
Exposed Pad. The LFCSP has an exposed pad that must be connected to GND.
Rev. 0 | Page 8 of 27
Data Sheet
ADF4152HV
TYPICAL PERFORMANCE CHARACTERISTICS
0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
T
= 25°C
A
BOOST MODE ON
–5
–10
–15
–20
–25
–30
BOOST MODE OFF
0
50
100
150
200
250
300
500 1000 1500 2000 2500 3000 3500 4000 4500 5000
TIME (µs)
FREQUENCY (MHz)
Figure 7. PLL Lock Time with Boost Mode On and Off; Locking over Octave
Range Jump (1 GHz to 2 GHz) for PFD = 20 MHz, Loop Bandwidth = 100 kHz,
Figure 4. RF Input Sensitivity, RF Output Disabled
ICP = 300 µA, VP = 28 V, AVDD = DVDD = SDVDD = 3.3 V, REFIN = 100 MHz
600
550
500
450
400
350
300
250
200
150
100
50
0
16
V
V
V
V
V
V
V
V
= 6V MISMATCH (%)
= 9V MISMATCH (%)
= 12V MISMATCH (%)
= 15V MISMATCH (%)
= 18V MISMATCH (%)
= 21V MISMATCH (%)
= 24V MISMATCH (%)
= 28V MISMATCH (%)
P
P
P
P
P
P
P
P
14
12
10
8
I
I
I
I
I
I
I
= 400µA SOURCE
= 350µA SOURCE
= 300µA SOURCE
= 250µA SOURCE
= 200µA SOURCE
= 150µA SOURCE
= 100µA SOURCE
= 50µA SOURCE
CP
CP
CP
CP
CP
CP
CP
6
4
2
I
0
CP
–2
–4
–6
–8
–10
–12
–14
–16
I
I
= 50µA SINK
–50
CP
= 100µA SINK
= 150µA SINK
= 200µA SINK
= 250µA SINK
= 300µA SINK
= 350µA SINK
= 400µA SINK
–100
–150
–200
–250
–300
–350
–400
–450
–500
CP
I
I
I
I
I
I
CP
CP
CP
CP
CP
CP
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
(V)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28
(V)
V
V
CP
CP
Figure 5. Charge Pump Output Characteristics, VP = 28 V,
Figure 8. Charge Pump Output (ICP) Mismatch vs. VCP, ICP = 200 µA
I
CP Varied from 50 µA to 400 µA, RSET = 5.1 kΩ
–80
–85
–90
–40
ADF4152HV
200kHz
400kHz
600kHz
800kHz
RMS NOISE = 0.28°
–50
–60
ADF4156
RMS NOISE = 0.36°
–95
BEAT NOTE
SPUR
BEAT NOTE
SPUR
–100
–105
–110
–115
–120
–125
–130
–135
–140
–145
–150
–155
–160
–165
–170
–70
–80
–90
–100
–110
–120
–130
100
1k
10k
100k
1M
10M
100M
1500
1505
1510
1515
1520
1525
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 6. Active Filter Phase Noise, ADF4152HV vs. ADF4156;
Active Filter Implemented Using OP27 Op Amp; PFD = 20 MHz, Loop
Bandwidth = 10 kHz, ICP = 300 µA, Carrier Frequency = 1.7 GHz, VP = 28 V
Figure 9. Fractional Spur Levels vs. Frequency, Low Spur Mode;
Measured at VCO Output, PFD = 25 MHz, MOD = 125
Rev. 0 | Page 9 of 27
ADF4152HV
Data Sheet
–80
–85
–40
200kHz
400kHz
600kHz
800kHz
–50
–60
LOW SPUR MODE
–90
–70
–80
–95
–90
–100
–105
–110
–100
–110
–120
–130
LOW NOISE MODE
1000
1050
1100
1150
1200
1250
1300
1500
1505
1510
1515
1520
1525
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 10. Fractional Spur Levels vs. Frequency, Low Noise Mode;
Measured at VCO Output, PFD = 25 MHz, MOD = 125
Figure 13. In-Band Phase Noise Measured at 3 kHz Offset for Low Noise Mode
and Low Spur Mode, PFD = 25 MHz, PLL Loop Bandwidth = 40 kHz
–40
4
25MHz
50MHz
75MHz
100MHz
2
0
+5dBm
–50
–60
+2dBm
–1dBm
–4dBm
–2
–70
–4
–80
–6
–8
–90
–10
–12
–14
–16
–100
–110
–120
1000
1200
1400
1600
1800
2000
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 11. PFD and Reference Spur Levels vs. Frequency, Measured at VCO
Output, REFIN = 100 MHz, PFD = 25 MHz
Figure 14. Single-Ended RF Output Power Level vs. Frequency over Various
Power Settings, RF Output Pins Pulled Up to 3.3 V via 27 nH||50 Ω
–40
25MHz
50MHz
75MHz
100MHz
–50
–60
–70
–80
–90
–100
–110
–120
1000
1200
1400
1600
1800
2000
FREQUENCY (MHz)
Figure 12. PFD and Reference Spur Levels vs. Frequency, Measured at VCO
Output with ADL5541 Buffer Placed Between VCO Output and RF Input,
REFIN = 100 MHz, PFD = 25 MHz
Rev. 0 | Page 10 of 27
Data Sheet
ADF4152HV
THEORY OF OPERATION
The PFD frequency (fPFD) equation is
PFD = REFIN × ((1 + D)/(R × (1 + T)))
REFERENCE INPUT SECTION
f
(2)
The reference input stage is shown in Figure 15. The SW1 and
SW2 switches are normally closed. The SW3 switch is normally
open. When power-down is initiated, SW3 is closed, and SW1
and SW2 are opened. In this way, no loading of the REFIN pin
occurs during power-down.
where:
REFIN is the reference input frequency.
D is the reference doubler bit, DB25 in Register 2.
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023), DB14 to DB23 in Register 2.
T is the reference divide by 2 bit (0 or 1), DB24 in Register 2.
POWER-DOWN
CONTROL
100kΩ
SW2
NC
Integer N Mode
TO R COUNTER
REF
IN
If FRAC = 0 and the DB8 (LDF) bit in Register 2 is set to 1,
the synthesizer operates in integer-N mode. Set the DB8 bit in
Register 2 to 1 for integer N digital lock detect.
BUFFER
SW1
SW3
R Counter
Figure 15. Reference Input Stage
The 10-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 1023 are allowed.
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. This divider comprises the INT, FRAC, and MOD values,
which determine the division ratio (see Figure 16).
PFD AND HIGH VOLTAGE CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
RF N DIVIDER
N = INT + FRAC/MOD
produces an output proportional to the phase and frequency
difference between them. Figure 17 is a simplified schematic of
the PFD.
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
TO PFD
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
UP
HIGH
D1
Q1
U1
CLR1
+IN
INT
VALUE
MOD
VALUE
FRAC
VALUE
CHARGE
PUMP
CP
U3
DELAY
DOWN
OUT
Figure 16. RF N Divider
INT, FRAC, MOD, and R Counter Relationship
CLR2
D2 Q2
HIGH
The INT, FRAC, and MOD values, in conjunction with the
R counter, enable the user to generate output frequencies that
are spaced by fractions of the PFD frequency. For more informa-
tion, see the RF Synthesizer—A Worked Example section.
U2
–IN
Figure 17. PFD Simplified Schematic
The PFD includes a delay element that sets the width of the
antibacklash pulse to 4.2 ns. This pulse ensures that there is no
dead zone in the PFD transfer function and provides a
consistent reference spur level.
The RF VCO frequency (RFOUT) is calculated as follows:
RFOUT = (fPFD/RF Divider) × (INT + (FRAC/MOD))
where:
RFOUT is the output frequency of the external VCO.
PFD is the PFD frequency.
(1)
The high voltage charge pump is designed on an Analog
Devices, Inc., proprietary high voltage process and allows the
charge pump to output voltages as high as 29 V when powered
by a 30 V supply. The high voltage charge pump removes the
need for active filtering when interfacing to a high voltage VCO.
f
RF Divider is the output divider that divides down the VCO
frequency.
INT is the preset divide ratio of the binary 16-bit counter (23 to
32,767 for the 4/5 prescaler, 75 to 65,535 for the 8/9 prescaler).
FRAC is the numerator of the fractional division (0 to MOD − 1).
MOD is the preset fractional modulus (2 to 4095).
Rev. 0 | Page 11 of 27
ADF4152HV
Data Sheet
MUXOUT AND LOCK DETECT
PROGRAM MODES
The multiplexer output on the ADF4152HV allows the user to
access various internal points on the chip. The state of the
MUXOUT pin is controlled by the M3, M2, and M1 bits in
Register 2 (see Figure 23). Figure 18 shows the MUXOUT
section in block diagram form.
Table 6 and Figure 20 through Figure 26 show how the program
modes are set up in the ADF4152HV.
The following settings in the ADF4152HV are double buffered:
phase value, modulus value, reference doubler, reference divide
by 2, R counter value, and charge pump current setting. Before
the device uses a new value for any double-buffered setting, the
following two events must occur:
R COUNTER INPUT
DV
DD
THREE-STATE OUTPUT
DV
1. Write the appropriate register to latch the new value into
the device.
DD
GND
2. Perform a new write on Register 0 (R0).
R COUNTER OUTPUT
N COUNTER OUTPUT
ANALOG LOCK DETECT
MUXOUT
MUX
CONTROL
For example, to ensure that the modulus value is loaded correctly
any time that the modulus value is updated, Register 0 (R0)
must be written to. The divider select value in Register 4 (R4) is
also double buffered, but only when the DB13 bit of Register 2
(R2) is high.
DIGITAL LOCK DETECT
RESERVED
GND
Figure 18. MUXOUT Schematic
OUTPUT STAGE
The RFOUT+ and RFOUT− pins of the ADF4152HV are connected
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 19. To allow the user to
optimize the power dissipation vs. output power requirements,
the tail current of the differential pair is programmable using
Bits[DB4:DB3] in Register 4 (R4). Four current levels can be set.
These levels give output power levels of −4 dBm, −1 dBm, +2 dBm,
and +5 dBm, respective of RFOUT , using a 50 Ω resistor to
AVDD and ac coupling into a 50 Ω load. Alternatively, both
outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section). If the
outputs are used individually, the optimum output stage
INPUT SHIFT REGISTERS
The ADF4152HV digital section includes a 10-bit RF R counter,
a 16-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of six latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2, and C1) in the shift
register. As shown in Figure 2, the control bits are the three LSBs:
DB2, DB1, and DB0. The truth table for these bits is shown in
Table 6. Figure 20 summarizes how the latches are programmed.
consists of a shunt inductor to AVDD
.
Table 6. Truth Table for C3, C2, and C1 Control Bits
RF
+
RF
–
OUT
Control Bits
OUT
C3
0
0
0
0
C2
0
0
1
1
C1
0
1
0
1
Register
Register 0 (R0)
Register 1 (R1)
Register 2 (R2)
Register 3 (R3)
Register 4 (R4)
Register 5 (R5)
BUFFER/
VCO
÷1/÷2/÷4/÷8/÷16
1
1
0
0
0
1
Figure 19. Output Stage
Another feature of the ADF4152HV is that the supply current to
the RF output stage can be shut down until the device achieves
lock, as measured by the digital lock detect circuitry. This
feature is enabled by the mute till lock detect (MTLD) bit in
Register 4 (R4).
Rev. 0 | Page 12 of 27
Data Sheet
ADF4152HV
REGISTER MAPS
REGISTER 0
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
12-BIT FRACTIONAL VALUE (FRAC)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
N16 N15 N14 N13 N12 N11 N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
F12 F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1 C3(0) C2(0) C1(0)
REGISTER 1
CONTROL
BITS
1
1
RESERVED
12-BIT PHASE VALUE (PHASE)
12-BIT MODULUS VALUE (MOD)
DBR
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
PR1 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)
0
0
0
0
REGISTER 2
1
DBR
CHARGE
PUMP
CURRENT
SETTING
LOW
NOISE AND
LOW SPUR
MODES
1
CONTROL
BITS
MUXOUT
10-BIT R COUNTER
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
L2
L1
M3
M2
M1 RD2 RD1 R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D1
0
CP3 CP2 CP1 U6
U5
1
U3
U2
U1 C3(0) C2(1) C1(0)
REGISTER 3
CLOCK
DIVIDER
MODE
RESERVED
CONTROL
BITS
12-BIT CLOCK DIVIDER VALUE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
B1
0
C2
C1
D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1 C3(0) C2(1) C1(1)
REGISTER 4
2
DBB
DIVIDER
SELECT
OUTPUT
POWER
RESERVED
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
D13 D12 D11 D10
0
0
0
0
0
0
0
0
0
D8
0
0
0
0
D3
D2
D1 C3(1) C2(0) C1(0)
REGISTER 5
LD PIN
MODE
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ABP2 ABP1 CE1 D15 D14 C3(1) C2(0) C1(1)
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
DBR = DOUBLE-BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
2
DBB = DOUBLE-BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, ONLY WHEN DB13 OF REGISTER 2 IS HIGH.
Figure 20. Register Summary
Rev. 0 | Page 13 of 27
ADF4152HV
Data Sheet
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
12-BIT FRACTIONAL VALUE (FRAC)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
N16
N15 N14
N13
N12 N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1 C3(0) C2(0) C1(0)
F12
F11 ...
F2
F1
FRACTIONAL VALUE (FRAC)
N16
N15
0
...
...
...
...
...
...
...
...
...
...
...
...
N5
N4
N3
N2
N1
INTEGER VALUE (INT)
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
NOT ALLOWED
1
0
NOT ALLOWED
2
0
NOT ALLOWED
3
.
...
0
0
0
.
0
1
1
1
.
0
0
1
.
1
1
0
.
1
1
0
.
0
1
0
.
NOT ALLOWED
.
.
.
.
.
.
0
23
0
24
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
.
...
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
65,533
65,534
65,535
1
1
INTMIN = 75 WITH PRESCALER = 8/9
Figure 21. Register 0 (R0)
12-Bit Fractional Value (FRAC)
REGISTER 0
The 12 FRAC bits (Bits[DB14:DB3]) set the numerator of the
fraction that is input to the Σ-Δ modulator. This fraction, along
with the INT value, specifies the new frequency channel that
the synthesizer locks to, as shown in the RF Synthesizer—A
Worked Example section. FRAC values from 0 to (MOD − 1)
cover channels over a frequency range equal to the PFD
reference frequency.
Control Bits
When Bits[C3:C1] are set to 000, Register 0 is programmed.
Figure 21 shows the input data format for programming this
register.
16-Bit Integer Value (INT)
The 16 INT bits (Bits[DB30:DB15]) set the INT value, which
determines the integer part of the feedback division factor. The
INT value is used in Equation 1 (see the INT, FRAC, MOD, and
R Counter Relationship section). Integer values from 23 to
32,767 are allowed for the 4/5 prescaler; for the 8/9 prescaler,
the minimum integer value is 75 and the maximum value is
65,535.
Rev. 0 | Page 14 of 27
Data Sheet
ADF4152HV
CONTROL
BITS
RESERVED
12-BIT PHASE VALUE (PHASE)
DBR
12-BIT MODULUS VALUE (MOD)
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
PR1
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
M12 M11 M10
M9
M8
M7 M6
M5
M4
M3
M2
M1 C3(0) C2(0) C1(1)
PR1
PRESCALER
P12
P11
...
...
...
...
...
...
...
...
...
...
...
...
P2
0
0
1
1
.
P1
0
1
0
1
.
PHASE VALUE (PHASE)
M12
M11
...
M2
M1
INTERPOLATOR MODULUS (MOD)
0
1
4/5
8/9
0
0
0
0
.
0
0
0
0
.
0
0
0
.
0
0
.
...
...
...
...
...
...
...
...
...
1
1
.
0
1
.
2
3
1 (RECOMMENDED)
.
2
.
.
.
.
.
3
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
Figure 22. Register 1 (R1)
12-Bit Phase Value
REGISTER 1
Bits[DB26:DB15] control the phase value. The word must be
less than the MOD value programmed in Register 1. The phase
word programs the RF output phase from 0° to 360° with a
resolution of 360°/MOD. For more information, see the Phase
Resync section.
Control Bits
When Bits[C3:C1] are set to 001, Register 1 is programmed.
Figure 22 shows the input data format for programming this
register.
Prescaler Value
In most applications, the phase relationship between the RF
signal and the reference is not important. In such applications,
the phase value can be used to optimize the fractional and
subfractional spur levels. For more information, see the Spur
Consistency and Fractional Spur Optimization section.
The dual-modulus prescaler, along with the INT, FRAC, and
MOD values, determines the overall division ratio from the VCO
output to the PFD input. The PR1 bit (DB27) in Register 1 sets
the prescaler value.
Operating at CML levels, the prescaler takes the clock from the
VCO output and divides it down for the counters. The prescaler
is based on a synchronous 4/5 core. When the prescaler is set to
4/5, the maximum RF frequency allowed is 3 GHz. Therefore,
when operating the ADF4152HV above 3 GHz, the prescaler
must be set to 8/9. The prescaler limits the INT value as follows:
If neither the phase resync nor the spurious optimization function
is used, it is recommended that the phase word be set to 1.
12-Bit Modulus Value (MOD)
The 12 MOD bits (Bits[DB14:DB3]) set the fractional modulus.
The fractional modulus is the ratio of the PFD frequency to the
channel step resolution on the RF output. For more information,
see the 12-Bit Programmable Modulus section.
Prescaler = 4/5: NMIN = 23, where NMIN is the minimum
INT value
Prescaler = 8/9: NMIN = 75
Rev. 0 | Page 15 of 27
ADF4152HV
Data Sheet
DBR
CHARGE
PUMP
CURRENT
SETTING
LOW
NOISE AND
LOW SPUR
MODES
CONTROL
BITS
MUXOUT
10-BIT R COUNTER
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
L2
L1
M3
M2
M1 RD2 RD1 R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D1
0
CP3 CP2 CP1 U6
U5
1
U3
U2
U1 C3(0) C2(1) C1(0)
REFERENCE
RD2
COUNTER
RESET
DOUBLE BUFFER
R4[DB22:DB20]
U1
L2
0
L1
NOISE MODE
DOUBLER
D1
U6 LDF
0
1
DISABLED
ENABLED
0
1
0
1
LOW NOISE MODE
RESERVED
0
1
FRACTIONAL-N
INTEGER-N
0
1
DISABLED
ENABLED
0
1
DISABLED
ENABLED
0
1
RESERVED
RD1 REFERENCE DIVIDE BY 2
CP
I
(µA)
1
LOW SPUR MODE
CP
U2
U5
0
LDP
THREE-STATE
0
1
DISABLED
ENABLED
5.1kΩ
CP3
CP2
0
CP1
10ns
6ns
0
1
DISABLED
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
48
1
0
96
ENABLED
1
144
192
240
288
336
384
R10
R9
...
R2
R1
R COUNTER (R)
1
U3
POWER-DOWN
RESERVED
BIT
0
0
.
0
0
.
...
...
...
...
...
...
...
...
...
0
1
.
1
0
.
1
0
0
1
DISABLED
ENABLED
0
2
0
1
RESERVED
1
.
NORMAL
OPERATION
1
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1020
1021
1022
1023
M3
M2
0
M1
0
OUTPUT
0
0
0
0
1
1
1
1
THREE-STATE OUTPUT
DVDD
0
1
1
0
GND
1
1
R COUNTER OUTPUT
N DIVIDER OUTPUT
0
0
0
1
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
RESERVED
1
0
1
1
Figure 23. Register 2 (R2)
synthesizer ensures extremely low noise, and the filter attenuates
the spurs.
REGISTER 2
Control Bits
Figure 9 and Figure 10 show fractional spur levels when using
low spur mode and low noise mode, respectively. Figure 13 shows
the in-band phase noise when using low spur mode and low
noise mode.
When Bits[C3:C1] are set to 010, Register 2 is programmed.
Figure 23 shows the input data format for programming this
register.
Low Noise and Low Spur Modes
MUXOUT
The noise modes on the ADF4152HV are controlled by setting
Bits[DB30:DB29] in Register 2 (see Figure 23). The noise modes
allow the user to optimize a design either for improved spurious
performance or for improved phase noise performance.
The on-chip multiplexer is controlled by Bits[DB28:DB26] (see
Figure 23).
Reference Doubler
When the low spur mode is chosen, dither is enabled. Dither
randomizes the fractional quantization noise so that it resembles
white noise rather than spurious noise. As a result, the device is
optimized for improved spurious performance. Low spur mode
is normally used for fastlocking applications when the PLL closed-
loop bandwidth is wide. Wide loop bandwidth is a loop bandwidth
greater than 1/10 of the RF VCO frequency, RFOUT. A wide loop
filter does not attenuate the spurs to the same level as a narrow
loop bandwidth.
Setting the DB25 bit to 0 disables the doubler and feeds the
REFIN signal directly into the 10-bit R counter. Setting this bit to
1 multiplies the REFIN frequency by a factor of 2 before feeding
it into the 10-bit R counter. When the doubler is disabled, the
REFIN falling edge is the active edge at the PFD input to the
fractional synthesizer. When the doubler is enabled, both the
rising and falling edges of REFIN become active edges at the
PFD input.
When the doubler is enabled and the low spur mode is chosen,
the in-band phase noise performance is sensitive to the REFIN duty
cycle. The phase noise degradation can be as much as 5 dB for
REFIN duty cycles outside a 45% to 55% range. The phase noise
is insensitive to the REFIN duty cycle in the low noise mode and
when the doubler is disabled.
For the best noise performance, use the low noise mode option.
When the low noise mode is chosen, dither is disabled. This
mode ensures that the charge pump operates in an optimum
region for noise performance. Low noise mode is extremely
useful when a narrow loop filter bandwidth is available. The
Rev. 0 | Page 1± of 27
Data Sheet
ADF4152HV
The maximum allowable REFIN frequency when the doubler is
enabled is 30 MHz.
by the LDF bit (DB8). For example, with DB8 = 0 and DB7 = 0,
40 consecutive PFD cycles of 10 ns or less must occur before the
digital lock detect goes high. The recommended settings for
Bits[DB8:DB7] are listed in Table 7.
Reference Divide by 2 (RDIV2)
Setting the DB24 bit to 1 inserts a divide by 2 toggle flip flop
between the R counter and the PFD. This function allows a 50%
duty cycle signal to appear at the PFD input, which is necessary
when the charge pump boost mode is enabled (see the Boost
Enable section).
Table 7. Recommended LDF and LDP Bit Settings
Mode
DB8 (LDF)
DB7 (LDP)
Integer N
Fractional N, Low Noise Mode
Fractional N, Low Spur Mode
1
0
0
1
1
0
10-Bit R Counter
The 10-bit R counter (Bits[DB23:DB14]) allows the input
reference frequency (REFIN) to be divided down to produce the
reference clock to the PFD. Division ratios from 1 to 1023 are
allowed.
Power-Down (PD)
The DB5 bit provides the programmable power-down mode.
Setting this bit to 1 performs a power-down. Setting this bit to 0
returns the synthesizer to normal operation. In software power-
down mode, the device retains all information in its registers.
The register contents are lost only when the supply voltages are
removed.
Double Buffer
The DB13 bit enables or disables double buffering of
Bits[DB22:DB20] in Register 4. For information about how
double buffering works, see the Program Modes section.
When power-down is activated, the following events occur:
Charge Pump Current Setting
•
The synthesizer counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RFOUT buffers are disabled.
Bits[DB11:DB9] set the charge pump current. Set this value to
the charge pump current that the loop filter is designed with
(see Figure 23).
•
•
•
•
Lock Detect Function (LDF)
The input registers remain active and capable of loading
and latching data.
The DB8 bit configures the lock detect function (LDF). The LDF
controls the number of PFD cycles monitored by the lock detect
circuit to ascertain whether lock has been achieved. When DB8
is set to 0, the number of PFD cycles monitored is 40. When
DB8 is set to 1, the number of PFD cycles monitored is 5. It is
recommended that the DB8 bit be set to 0 for fractional-N mode
and 1 for integer N mode.
Charge Pump Three-State
Setting the DB4 bit to 1 sets the charge pump into three-state
mode. Set this bit to 0 for normal operation.
Counter Reset
The DB3 bit is the reset bit for the R counter and the N counter
of the ADF4152HV. When this bit is set to 1, the RF synthesizer
N counter and R counter are held in reset. For normal operation,
set this bit to 0.
Lock Detect Precision (LDP)
The lock detect precision bit (Bit DB7) sets the comparison
window in the lock detect circuit. When DB7 is set to 0, the
comparison window is 10 ns; when DB7 is set to 1, the window
is 6 ns. The lock detect circuit goes high when n consecutive
PFD cycles are less than the comparison window value; n is set
Rev. 0 | Page 17 of 27
ADF4152HV
Data Sheet
CLOCK
DIVIDER
MODE
CONTROL
BITS
RESERVED
12-BIT CLOCK DIVIDER VALUE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
0
0
B1
0
C2
C1
D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1 C3(0) C2(1) C1(1)
0
0
0
D12
D11 ...
D2
D1
CLOCK DIVIDER VALUE
BOOST
ENABLE
B1
0
0
0
0
.
0
0
0
0
.
...
...
...
...
...
...
...
...
...
...
...
0
0
1
1
.
0
1
0
1
.
0
0
1
DISABLED
ENABLED
1
2
3
.
.
.
.
.
.
C2
C1
0
CLOCK DIVIDER MODE
CLOCK DIVIDER OFF
RESERVED
.
.
.
.
.
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
4092
4093
4094
4095
1
0
RESYNC ENABLE
RESERVED
1
Figure 24. Register 3 (R3)
Loop stability is maintained because the current is constant and
is not pulsed, so there is no need to switch a compensating loop
filter resistor in and out, as in standard fast lock modes. Note that
the PFD requires a 45% to 55% duty cycle for the boost mode to
operate correctly. This duty cycle can be guaranteed by setting
the RDIV2 bit (DB24) in Register 2.
REGISTER 3
Control Bits
When Bits[C3:C1] are set to 011, Register 3 is programmed.
Figure 24 shows the input data format for programming this
register.
Boost Enable
Clock Divider Mode
Setting the DB18 bit to 1 enables the charge pump boost mode.
If boost mode is enabled, the narrow loop bandwidth is main-
tained for spur attenuation, but faster lock times are still possible.
Boost mode speeds up locking significantly for higher values of
PFD frequencies that normally have many cycle slips.
Bits[DB16:DB15] must be set to 10 to activate phase resync
(see the Phase Resync section). Setting Bits[DB16:DB15] to
00 disables the clock divider (see Figure 24).
12-Bit Clock Divider Value
Bits[DB14:DB3] set the 12-bit clock divider value. This value is
the timeout counter for activation of the phase resync. For more
information, see the Phase Resync section.
When boost mode is enabled, an extra charge pump current cell
is turned on. This cell outputs a constant current to the loop filter
or removes a constant current from the loop filter (depending on
whether the VCO tuning voltage (VTUNE) needs to increase or
decrease to acquire the new frequency) until VTUNE approaches
the lock voltage. The boost current is then disabled and the
charge pump current setting reverts to the user programmed
value.
Rev. 0 | Page 18 of 27
Data Sheet
ADF4152HV
DBB
DIVIDER
SELECT
OUTPUT
POWER
RESERVED
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
D13 D12 D11 D10
0
0
0
0
0
0
0
0
0
D8
0
0
0
0
D3
D2
D1 C3(1) C2(0) C1(0)
FEEDBACK
SELECT
D13
D2
D1
0
OUTPUT POWER (dBm)
0
0
1
1
–4
–1
+2
+5
0
1
DIVIDED
FUNDAMENTAL
1
0
MUTE TILL
LOCK DETECT
D12
D11
D10
RF DIVIDER SELECT
1
D8
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
÷1
÷2
÷4
÷8
÷16
MUTE DISABLED
D3
RF OUT
1
MUTE ENABLED
0
1
DISABLED
ENABLED
Figure 25. Register 4 (R4)
Divider Select
REGISTER 4
Bits[DB22:DB20] select the value of the output divider (see
Figure 25).
Control Bits
When Bits[C3:C1] are set to 100, Register 4 is programmed.
Figure 25 shows the input data format for programming this
register.
Mute Till Lock Detect (MTLD)
When the DB10 bit is set to 1, the supply current to the RF output
stage is shut down until the device achieves lock, as measured
by the digital lock detect circuitry.
Feedback Select
The DB23 bit selects the feedback from the VCO output to the
N counter. When this bit is set to 1, the signal is taken directly
from the VCO. When this bit is set to 0, the signal is taken from
the output of the output dividers. The dividers enable coverage
of the wide frequency band (31.25 MHz to 3.0 GHz). When the
dividers are enabled and the feedback signal is taken from the
divider output, the RF output signals of two separately config-
ured PLLs are in phase. Enabling the drivers is useful in some
applications where the positive interference of signals is required to
increase the power.
RF Output Enable
The DB5 bit enables or disables the primary RF output. If DB5
is set to 0, the primary RF output is disabled; if DB5 is set to 1,
the primary RF output is enabled.
Output Power
Bits[DB4:DB3] set the value of the primary RF output power
level (see Figure 25).
Rev. 0 | Page 19 of 27
ADF4152HV
Data Sheet
LD PIN
MODE
CONTROL
BITS
ABP
WIDTH
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
ABP2 ABP1 CE1
1
0
0
0
0
D15 D14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C3(1) C2(0) C1(1)
D15
0
D14
0
LOCK DETECT PIN OPERATION
OUTPUT LOW
0
1
DIGITAL LOCK DETECT
OUTPUT LOW
1
0
1
1
OUTPUT HIGH
CE1
0
CHARGE CANCELL ATION
DISABLED
1
ENABLED
ABP2 ABP1
ANTIBACKLASH PULSE WIDTH
0
0
1
1
0
1
0
1
4.2ns (RECOMMENDED)
RESERVED
RESERVED
RESERVED
1
MUXOUT IN REGISTER 2 MUST ALSO BE SET TO DIGITAL LOCK DETECT FOR THE LOCK DETECT PINTO OPERATE CORRECTLY.
Figure 26. Register 5 (R5)
REGISTER 5
RF SYNTHESIZER—A WORKED EXAMPLE
Control Bits
Use the following equations to program the ADF4152HV
synthesizer:
When Bits[C3:C1] are set to 101, Register 5 is programmed.
Figure 26 shows the input data format for programming this
register.
RFOUT = (INT + (FRAC/MOD)) × (fPFD/RF Divider)
(3)
where:
Antibacklash Pulse (ABP) Width
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC is the numerator of the fractional division (0 to MOD − 1).
MOD is the modulus.
RF Divider is the output divider that divides down the VCO
frequency.
Bits[DB31:DB30] set the PFD antibacklash pulse width.
The recommended value for all operating modes is 4.2 ns (set
Bits[DB31:DB30] to 00). Other antibacklash pulse width
settings are reserved and are not recommended.
Charge Cancellation (CC) Enable
f
PFD is the PFD frequency, calculated in Equation 4.
PFD = REFIN × ((1 + D)/(R × (1 + T)))
Setting the DB29 bit to 1 enables charge pump charge cancellation,
which has the effect of reducing PFD spurs in integer N mode.
In fractional-N mode, set this bit to 0.
f
(4)
where:
REFIN is the reference frequency input.
Lock Detect Pin Operation
D is the RF reference doubler bit (0 or 1), DB25 in Register R2.
R is the RF reference division factor (1 to 1023).
T is the reference divide by 2 bit (0 or 1).
Bits[DB23:DB22] set the operation of the lock detect (LD) pin
(see Figure 26).
REGISTER INITIALIZATION SEQUENCE
In this example, a 1.5 GHz RF frequency output (RFOUT) with a
500 kHz channel resolution at RFOUT (fRESOUT) required on the
RF output is programmed. The reference frequency input (REFIN)
is 25 MHz. The VCO options available to the user include the
following:
At initial power-up, after the correct application of voltages to
the supply pins, program the ADF4152HV registers in the
following sequence:
1. Register 5
2. Register 4
3. Register 3
4. Register 2
5. Register 1
6. Register 0
1.5 GHz VCO in fundamental mode
3 GHz VCO with the RF divider set to 2
When enabling the RF divider, the user must choose to either
close the PLL loop before the RF divider or after the RF divider.
In this example, the PLL loop is closed before the RF divider
(see Figure 27).
Rev. 0 | Page 20 of 27
Data Sheet
ADF4152HV
fPFD
For example, consider an application that requires a 1.75 GHz
RF frequency output with a 200 kHz channel step resolution.
The system has a 13 MHz reference signal.
RF
OUT
PFD
VCO
÷2
N
One possible setup is to feed the 13 MHz reference signal
directly into the PFD and to program the modulus to divide
by 65. This setup results in the required 200 kHz resolution.
DIVIDER
Figure 27. PLL Loop Closed Before Output Divider
To minimize VCO feedthrough, the 3 GHz VCO is selected. A
channel resolution (fRESOUT) of 500 kHz is required at the output
of the RF divider. Therefore, the channel resolution at the output
of the VCO (fRES) must be 2 × fRESOUT, that is, 1 MHz.
Another possible setup is to use the reference doubler to create
26 MHz from the 13 MHz input signal. The 26 MHz is then fed
into the PFD, and the modulus is programmed to divide by 130.
This setup also results in 200 kHz resolution but offers superior
phase noise performance over the first setup.
MOD = REFIN/fRES
MOD = 25 MHz/1 MHz = 25
The programmable modulus is also very useful for multistandard
applications with different channel spacing requirements.
From Equation 4,
f
PFD = (25 MHz × (1 + 0)/1) = 25 MHz
From Equation 3,
1500.5 MHz = 25 MHz × ((INT + (FRAC/25))/2)
(5)
(6)
It is important that the PFD frequency remain constant (in this
example, 13 MHz). The constant PFD frequency allows the user
to design one loop filter for both setups without encountering
stability issues. Note that the ratio of the RF frequency to the
PFD frequency principally affects the loop filter design, and not
the actual channel spacing.
where:
INT = 120.
FRAC = 1.
SPURIOUS OPTIMIZATION AND BOOST MODE
The RF divider value is fixed at 2.
Narrow loop bandwidths can filter unwanted spurious signals,
but these bandwidths usually have a long lock time. A wider
loop bandwidth achieves faster lock times, but may lead to
increased spurious signals inside the loop bandwidth.
Use the ADF4152HV evaluation software to determine integer
and fractional values for a given setup, as well as the actual
register settings to be programmed.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The boost mode feature can achieve the same fast lock time as
the wider bandwidth, but with the advantage of a narrow final
loop bandwidth to keep spurs low (see the Boost Enable section).
The on-chip reference doubler allows the input reference signal
to be doubled. Doubling the reference signal doubles the PFD
comparison frequency, which improves the noise performance
of the system. Doubling the PFD frequency usually improves
noise performance by 3 dB. Note that the PFD cannot operate
above 26 MHz due to a limitation in the speed of the Σ-Δ circuit
of the N divider.
SPUR MECHANISMS
This section describes the three different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4152HV.
Fractional Spurs
The reference divide by 2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency. The 50% duty
cycle PFD frequency is necessary for the correct operation of
the charge pump boost mode. For more information, see the
Boost Enable section.
The fractional interpolator in the ADF4152HV is a third-order,
Σ-Δ modulator with a modulus (MOD) that is programmable to
any integer value from 2 to 4095. In low spur mode (dither on),
the minimum allowable value of MOD is 50. The Σ-Δ modulator
is clocked at the PFD reference rate (fPFD), which allows PLL out-
put frequencies to be synthesized at a channel step resolution
of fPFD/MOD.
12-BIT PROGRAMMABLE MODULUS
The choice of modulus (MOD) depends on the reference signal
(REFIN) available and the channel resolution at RFOUT (fRESOUT
)
In low noise mode (dither off), the quantization noise from the
Σ-Δ modulator appears as fractional spurs. The interval between
spurs is fPFD/L, where L is the repeat length of the code sequence
in the digital Σ-Δ modulator. For the third-order Σ-Δ modulator
used in the ADF4152HV, the repeat length depends on the value
of MOD, as listed in Table 8.
required at the RF output. For example, a GSM system with
13 MHz REFIN sets the modulus to 65, which means that the RF
output resolution (fRESOUT) is the 200 kHz (13 MHz/65) neces-
sary for GSM. With dither off, the fractional spur interval
depends on the modulus values chosen (see Table 8).
Unlike most other fractional-N PLLs, the ADF4152HV allows
the user to program the modulus over a 12-bit range. When
combined with the reference doubler and the 10-bit R counter,
the 12-bit modulus allows the user to set up the device in many
different configurations for the application.
Rev. 0 | Page 21 of 27
ADF4152HV
Data Sheet
Table 8. Fractional Spurs with Dither Off (Low Noise Mode)
MOD is the fractional modulus. The phase resync feature of
the ADF4152HV produces a consistent output phase offset with
respect to the input reference. The consistent output phase offset
with respect to the input reference is necessary in applications
where the output phase and frequency are important, such as
digital beamforming. For information about how to program a
specific RF output phase when using phase resync, see the Phase
Programmability section.
Repeat
Length
MOD Value (Dither Off)
Divisible by 2, But Not by 3
Divisible by 3, But Not by 2
Divisible by ±
Spur Interval
2 × MOD Channel step/2
3 × MOD Channel step/3
± × MOD Channel step/±
Not Divisible by 2, 3, or ±
MOD
Channel step
In low spur mode (dither on), the repeat length is extended
to 221 cycles, regardless of the value of MOD, which makes the
quantization error spectrum appear as broadband noise. This
dither may degrade the in-band phase noise at the PLL output
by as much as 10 dB. For lowest noise, dither off is a better
choice, particularly when the final loop bandwidth is low
enough to attenuate even the lowest frequency fractional spur.
Phase resync is enabled by setting Bits[DB16:DB15] in
Register 3 to 10. When phase resync is enabled, an internal
timer generates sync signals at intervals of tSYNC given by the
following formula:
t
SYNC = CLK_DIV_VALUE × MOD × tPFD
where:
SYNC is the time interval between sync signals.
Integer Boundary Spurs
t
Another mechanism for fractional spur creation is the inter-
actions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related (the
purpose of a fractional-N synthesizer), spur sidebands appear
on the VCO output spectrum at an offset frequency that corre-
sponds to the beat note, or difference frequency, between an
integer multiple of the reference and the VCO frequency. These
spurs are attenuated by the loop filter and are more noticeable
on channels close to integer multiples of the reference where the
difference frequency can be inside the loop bandwidth (thus the
name integer boundary spurs).
CLK_DIV_VALUE is the decimal value programmed in
Bits[DB14:DB3] of Register 3 and can be any integer in the
range of 1 to 4095.
MOD is the modulus value programmed in Bits[DB14:DB3]
of Register 1.
tPFD is the PFD reference period.
When a new frequency is programmed, the second sync pulse
after the LE rising edge resynchronizes the output phase to the
reference. The tSYNC time must be programmed to a value that is
at least as long as the worst case lock time to guarantee that the
phase resync occurs after the last cycle slip in the PLL settling
transient.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism that
bypasses the loop may cause a problem. The PCB layout must
ensure adequate isolation between VCO traces and the input
reference to avoid a possible feedthrough path on the board.
In the example shown in Figure 28, the PFD reference is 25 MHz
and MOD is 125 for a 200 kHz channel spacing. tSYNC is set to
400 µs by programming CLK_DIV_VALUE = 80.
LE
tSYNC
SYNC
(INTERNAL)
LAST CYCLE SLIP
SPUR CONSISTENCY AND FRACTIONAL SPUR
OPTIMIZATION
FREQUENCY
With dither off, the fractional spur pattern due to the quantiza-
tion noise of the Σ-Δ modulator also depends on the particular
phase word with which the modulator is seeded.
PLL SETTLES TO
INCORRECT PHASE
PLL SETTLES TO
CORRECT PHASE
AFTER RESYNC
The phase word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Thus, a
lookup table of phase values corresponding to each frequency
can be constructed for use when programming the ADF4152HV.
PHASE
–100
0
100 200 300 400 500 600 700 800 900 1000
TIME (µs)
If a lookup table is not used, keep the phase word at a constant
value to ensure consistent spur levels on any particular frequency.
Figure 28. Phase Resync Example
Phase Programmability
PHASE RESYNC
The phase word in Register 1 controls the RF output phase. As
this word is swept from 0 to MOD, the RF output phase sweeps
over a 360° range in steps of 360°/MOD.
The output of a fractional-N PLL can settle to any one of the
MOD phase offsets with respect to the input reference, where
Rev. 0 | Page 22 of 27
Data Sheet
ADF4152HV
APPLICATIONS INFORMATION
ULTRAWIDEBAND PLL
MICROWAVE PLL
When paired with an octave tuning range VCO, the ADF4152HV
provides an ultrawideband PLL function using the on-board RF
dividers. With an octave tuning range at the fundamental
frequency, the RF dividers provide full frequency coverage with
no gaps down to much lower frequencies.
The ADF4152HV can be interfaced directly to a wide tuning
range microwave VCO without the need for an active filter.
Typically, most microwave VCOs have a maximum tuning range
of 15 V. In this case, set VP on the ADF4152HV to a value of
16 V or higher to ensure sufficient headroom in the charge
pump. An external prescaler, such as the ADF5001, is required
to divide down VCO frequencies that are above the maximum
RF input frequency of 5.0 GHz.
For example, using a 1 GHz to 2 GHz octave tuning range VCO
(such as the Synergy DCYS100200-12), the user can obtain
contiguous output frequencies from 62.5 MHz to 2 GHz at the
ADF4152HV RF outputs, as shown in Figure 29. A broadband
output match is achieved using a 27 nH inductor in parallel with
a 50 Ω resistor (for more information, see the Output Matching
section). With such a wide output range, the same PLL
hardware design can generate different frequencies for each of
the different hardware platforms in the system.
In the application circuit shown in Figure 30, the ADF5001
divides down the 16 GHz VCO signal to 4 GHz, which can then
be input directly into the ADF4152HV RF inputs. The ADF5001
can be connected either single-endedly or differentially to the
ADF4152HV. For best performance and to achieve maximum
power transfer, it is recommended that a differential connection
be used.
V
DD
Z
BIAS
RF
+
–
OUT
Z
=
RF
±
BIAS
OUT
ADF4152HV
50Ω||27nH
62.5MHz TO 2GHz
PLL
RF
RF
+
–
RF
IN
OUT
CP
IN
OUT
SYNERGY DCYS100200-12
OCTAVE RANGE VCO
37Ω
RFOUT
VTUNE
150Ω
150Ω
Figure 29. Ultrawideband PLL Using the ADF4152HV and an Octave Tuning Range VCO
Rev. 0 | Page 23 of 27
ADF4152HV
Data Sheet
10pF
0.1µF
AC COUPLING INTEGRATED
ON ADF5001 DEVICE
VDD1 VDD2
RFOUT
RF
RF
+
–
IN
ADF5001
PRESCALER
ADF4152HV
PLL
CP
RFIN
OUT
RFOUT
GND
IN
MICROWAVE
VCO
6dB PAD
37Ω
18Ω
18Ω
RFOUT
VTUNE
150Ω
150Ω
18Ω
16GHz OUT
Figure 30. 16 GHz Microwave PLL
GENERATING THE HIGH VOLTAGE SUPPLY
It is possible to use a boost converter such as the Analog Devices
ADP1613 to generate the high voltage charge pump supply
from a lower voltage rail without degrading PLL performance.
To minimize any switching noise feedthrough, ensure that
sufficient decoupling is placed close to the charge pump supply
pin (Pin 6). Take care to use capacitors with the appropriate
voltage rating; for example, if using a boost converter to generate
a 20 V VP supply, use capacitors with a rating of 20 V or higher.
The design of the boost converter is simplified using the Excel-
based boost regulator design tool. This tool is available from the
ADP1613 product page under tools and simulations. Figure 31
shows the user inputs for a 5 V input to 20 V output design. To
minimize voltage ripple at the output of the converter stage,
select the Noise Filter check box, and set the Vout Ripple box to
its minimum value. The high voltage charge pump current draw
is 2 mA maximum; therefore, a value of 0.01 A is entered in the
Iout box to provide a margin.
Figure 31. Designer Tool
Rev. 0 | Page 24 of 27
Data Sheet
ADF4152HV
Blackfin ADSP-BF527 Interface
INTERFACING THE ADF4152HVTO THE ADUC7024
OR THE ADSP-BF527
Figure 33 shows the interface between the ADF4152HV and
the Blackfin® ADSP-BF527 digital signal processor (DSP). The
ADF4152HV needs a 32-bit serial word for each latch write.
The easiest way to accomplish this using the Blackfin family
is to use the autobuffered transmit mode of operation with
alternate framing. This mode provides a means for transmitting
an entire block of serial data before an interrupt is generated.
The ADF4152HV has a simple SPI-compatible serial interface for
writing to the device. The CLK, DATA, and LE pins control the
data transfer. When LE goes high, the 32 bits that were clocked
into the appropriate register on each rising edge of CLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 6 for the register address truth table.
ADuC7024 Interface
ADF4152HV
CLK
SCKE
Figure 32 shows the interface between the ADF4152HV and the
ADuC7024 analog microcontroller. The ADuC7024 is based on
an ARM7 core, but the same interface can be used with any
8051-based microcontroller.
MOSI
GPIO
DATA
LE
CE
ADSP-BF527
I/O PORTS
MUXOUT
(LOCK DETECT)
The microcontroller is set up for SPI master mode with CPHA =
0. To initiate the operation, the I/O port driving LE is brought
low. Each latch of the ADF4152HV needs a 32-bit word, which
is accomplished by writing four 8-bit bytes from the microcontrol-
ler to the device. After the fourth byte is written, bring the LE
input high to complete the transfer.
Figure 33. ADSP-BF527 to ADF4152HV Interface
Set up the word length for eight bits and use four memory loca-
tions for each 32-bit word. To program each 32-bit latch, store
the 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer. If using a faster SPI clock, ensure that the
SPI timing requirements listed in Table 2 are adhered to.
ADF4152HV
SCLK
MOSI
CLK
DATA
ADuC7024
LE
CE
PCB DESIGN GUIDELINES FOR A CHIP SCALE
PACKAGE
I/O PORTS
MUXOUT
(LOCK DETECT)
The lands on the chip scale package (CP-32-11) are rectangular.
The PCB pad for these lands must be 0.1 mm longer than the
package land length and 0.05 mm wider than the package land
width. Each land must be centered on the pad to ensure that the
solder joint size is maximized.
Figure 32. ADuC7024 to ADF4152HV Interface
I/O port lines on the ADuC7024 also control the power-down
input (CE) and the lock detect (MUXOUT configured for lock
detect and polled by the port input). When operating in the SPI
master mode with CPHA = 0, the maximum SPI transfer rate of
the ADuC7024 is 20 Mbps. This transfer rate means that the
maximum rate at which the output frequency can be changed is
833 kHz. If using a faster SPI clock, ensure that the SPI timing
requirements listed in Table 2 are adhered to.
The bottom of the chip scale package has a central exposed
thermal pad. The thermal pad on the PCB must be at least as
large as the exposed pad. On the PCB, there must be a minimum
clearance of 0.25 mm between the thermal pad and the inner
edges of the pad pattern to ensure that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
must be incorporated into the thermal pad at 1.2 mm pitch grid.
The via diameter must be between 0.3 mm and 0.33 mm, and
the via barrel must be plated with 1 oz. of copper to plug the via.
Rev. 0 | Page 25 of 27
ADF4152HV
Data Sheet
The circuit shown in Figure 35 provides a good broadband
OUTPUT MATCHING
match to 50 Ω for frequencies from 250 MHz to 5.0 GHz. The
maximum output power in this case is approximately 5 dBm.
The inductor can be increased for operation below 250 MHz.
Both single-ended architectures can be examined using the
EVAL-ADF4152HVEB1Z evaluation board.
The output of the ADF4152HV can be matched in a number of
ways for optimum operation; the most basic is to connect a 50 Ω
resistor to AVDD. A dc bypass capacitor of 100 pF is connected
in series, as shown in Figure 34. Because the resistor is not
frequency dependent, this method provides a good broadband
match. When connected to a 50 Ω load, this circuit typically
gives a differential output power equal to the values chosen by
Bits[DB4:DB3] in Register 4.
AV
DD
22nH
1nF
50Ω
RF
RF
+
OUT
AV
DD
50Ω
50Ω
50Ω
100pF
100Ω
RF
OUT±
50Ω
50Ω
1nF
–
OUT
Figure 34. Simple ADF4152HV Output Stage
22nH
Another solution is to connect a shunt inductor (acting as an RF
choke) to AVDD. This solution can help provide a better narrow-
band match and, therefore, more output power. However, because
the output stage is open-collector, it is recommended that a
termination resistor be used in addition to the RF choke to give
a defined output impedance. The termination resistor can be
either 50 Ω in parallel with the RF choke or 100 Ω connected
across the RF output pins.
AV
DD
Figure 35. Optimum ADF4152HV Output Stage
If differential outputs are not needed, the unused output can be
terminated, or both outputs can be combined using a balun.
Rev. 0 | Page 2± of 27
Data Sheet
ADF4152HV
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
24
32
1
0.50
BSC
3.65
3.50 SQ
3.45
EXPOSED
PAD
8
9
17
16
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
3.50 REF
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.
Figure 36. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-11)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
CP-32-11
CP-32-11
ADF4152HVBCPZ
ADF4152HVBCPZ-RL7
EVAL-ADF4152HVEB1Z
−40°C to +85°C
−40°C to +85°C
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14382-0-7/16(0)
Rev. 0 | Page 27 of 27
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