ADF4212LBCP_技术文档

Dual Low Power PLL

Frequency Synthesizer

a

ADF4212L

GENERAL DESCRIPTION

FEATURES

The ADF4212L is a dual frequency synthesizer that can be used

to implement local oscillators (LO) in the up-conversion and

down-conversion sections of wireless receivers and transmitters.

It can provide the LO for both the RF and IF sections. It con-

sists of a low noise digital PFD (Phase Frequency Detector), a

precision charge pump, a programmable reference divider, pro-

grammable A and B counters, and a dual modulus prescaler

(P/P + 1). The A (6-bit) and B (12-bit) counters, in conjunction

with the dual modulus prescaler (P/P + 1), implement an N

divider (N = BP + A). In addition, the 14-bit reference counter

(R Counter), allows selectable REFIN frequencies at the PFD

input. A complete PLL (Phase-Locked Loop) can be imple-

mented if the synthesizer is used with external loop filters and

VCOs (Voltage Controlled Oscillators).

I_DDTotal, 7.5 mA

Bandwidth RF/IF, 2.4 GHz/1.0 GHz

2.7 V to 3.3 V Power Supply

Separate V_PAllows Extended Tuning Voltage

Programmable Dual Modulus Prescaler

RF and IF: 8/9, 16/17, 32/33, 64/65

Programmable Charge Pump Currents

3-Wire Serial Interface

Analog and Digital Lock Detect

Fastlock Mode

Power-Down Mode

20-Lead TSSOP and 20-Lead MLF Chip Scale Package

APPLICATIONS

Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)

Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)

Wireless LANS

Cable TV Tuners (CATV)

Control of all the on-chip registers is via a simple 3-wire interface

with 1.8 V compatibility. The devices operate with a power

supply ranging from 2.6 V to 3.3 V and can be powered down

when not in use.

Communications Test Equipment

FUNCTIONAL BLOCK DIAGRAM

V

1

V

2

V 1

V 2

P

R

SET

DD

P

ADF4212L

IF PHASE

FREQUENCY

DETECTOR

REFERENCE

12-BIT IF

B-COUNTER

CHARGE

PUMP

CP

IF

IN

IF

PRESCALER

6-BIT IF

A-COUNTER

IF CURRENT

SETTING

IF

LOCK

IFCP3 IFCP2 IFCP1

DETECT

REF

OSCILLATOR

IN

14-BIT IF

R-COUNTER

OUTPUT

MUX

MUXOUT

CLOCK

DATA

LE

22-BIT

DATA

REGISTER

SDOUT

RFCP3 RFCP2 RFCP1

REFERENCE

RF

14-BIT RF

R-COUNTER

LOCK

DETECT

12-BIT RF

B-COUNTER

CHARGE

PUMP

CP

RF

IN

RF

PRESCALER

RF PHASE

FREQUENCY

DETECTOR

REFERENCE

6-BIT RF

A-COUNTER

R

SET

FL SWITCH

FL

O

DGND

RF

AGND

RF

DGND

IF

AGND

IF

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

ADF4212L–SPECIFICATIONS¹^(V_DD^{1 = V}_DD^{2 = 2.7 V to 3.3 V; V}_P^{1, V}_P^{2 = V}_DDto 5.5 V; AGND_RF= DGND_RF=

AGND_IF= DGND_IF= 0 V; T_A= T_MINto T_MAX, unless otherwise noted; dBm referred to 50 ꢀ.)

B Chips²

B Version (Typical)

Parameter

Unit

Test Conditions/Comments

RF/IF CHARACTERISTICS

RF Input Frequency (RF_IN)

RF Input Sensitivity

IF Input Frequency (IF_IN)

IF Input Sensitivity

0.2/2.4

–10/0

100/1000

–10/0

0.2/2.4

–10/0

100/1000

–10/0

GHz min/max

dBm min/max

MHz min/max

dBm min/max

For Operation below F_MIN, Use a Square Wave

V_DD= 3 V

MAXIMUM ALLOWABLE

Prescaler Output Frequency³

200

MHz max

REFIN CHARACTERISTICS

REFIN Input Frequency

REFIN Input Sensitivity

See Figure 2 for Input Circuit.

10/150

–5

10/150

–5

MHz min/max

dBm min

AC-Coupled. When DC-Coupled,

0 to V_DDMax (CMOS-Compatible)

REFIN Input Capacitance

REFIN Input Current

10

100

10

100

pF max

µA max

PHASE DETECTOR

Phase Detector Frequency⁴

75

MHz max

CHARGE PUMP

I_CPSink/Source

High Value

Programmable: See Table V.

With R_SET= 2.7 kΩ

5

625

2

5

625

2

mA typ

µA typ

% typ

kΩ min/max

nA max

% typ

Low Value

Absolute Accuracy

With R_SET= 2.7 kΩ

R

_SETRange

_CPThree-State Leakage Current

Sink and Source Current Matching

_CPvs. V_CP

I_CPvs. Temperature

1.5/5.6

I

1

6

2

1

6

2

0.5 V < V_CP< V_P– 0.5 2% typ

0.5 V < V_CP< V_P– 0.5

V_CP= V_P/2

I

% typ

LOGIC INPUTS

V_INH, Input High Voltage

V_INL, Input Low Voltage

1.4

0.6

1

1.4

0.6

1

V min

V max

µA max

pF max

I

_INH/I_INL, Input Current

C_IN, Input Capacitance

10

LOGIC OUTPUTS

V_OH, Output High Voltage

V_OL, Output Low Voltage

1.4

0.4

1.4

0.4

V min

V max

Open Drain 1 kΩ Pull-Up to 1.8 V

I_OL= 500 µA

POWER SUPPLIES

V_DD

1

2.7/3.3

V_DD1

V_DD1/5.5

V min/V max

V

_DD2

V_DD

1

V_P1, V_P2

V_DD1/5.5

I_DD⁵(RF and IF)

RF Only

IF Only

I_P(I_P1 + I_P2)

Low Power Sleep Mode

10

6

4

0.6

1

10

6

4

0.6

1

mA max

mA typ

µA typ

7.5 mA Typical

5.0 mA Typical

2.5 mA Typical

NOTES

¹Operating temperature range is as follows: B Version: –40°C to +85°C.

²The B Chip specifications are given as typical values.

³This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency

that is less than this value.

⁴Guaranteed by design. Sample tested to ensure compliance.

⁵T_A= 25°C. RF = 1 GHz. Prescaler = 32/33. IF = 500 MHz. Prescaler = 16/17.

Specifications subject to change without notice.

–2–

REV. 0

ADF4212L

(V_DD1 = V_DD2 = 2.7 V to 3.3 V; V_P1, V_P2 = V_DDto 5.5 V ; AGND_RF= DGND_RF= AGND_IF= DGND_IF= 0 V;

T_A= T_MINto T_MAX, unless otherwise noted; dBm referred to 50 ꢀ.)

SPECIFICATIONS¹

Parameter

B Version B Chips²Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

RF Phase Noise Floor³

–170

–162

–170

–162

dBc/Hz typ

@ 25 kHz PFD Frequency

@ 200 kHz PFD Frequency

@ VCO Output

@ 1 kHz Offset and 200 kHz PFD Frequency

See Note 9

Phase Noise Performance⁴

IF: 540 MHz Output⁵

IF: 900 MHz Output⁶

RF: 900 MHz Output⁶

RF: 1750 MHz Output⁷

RF: 2400 MHz Output⁸

Spurious Signals

–89

–87

–89

–84

–87

–89

–87

–89

–84

–87

dBc/Hz typ

See Note 9

@ 1 kHz Offset and 1 MHz PFD Frequency

IF: 540 MHz Output⁵

IF: 900 MHz Output⁶

RF: 900 MHz Output⁶

RF: 1750 MHz Output⁷

RF: 2400 MHz Output⁸

–88/–90

–90/–94

–80/–82

–88/–90

–90/–94

–80/–82

dB typ

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

See Note 9

@ 200 kHz/400 kHz and 200 kHz PFD Frequency

NOTES

¹Operating temperature range is as follows: B Version: –40°C to +85°C

²The B Chip specifications are given as typical values.

³The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider

value). See TPC 14.

⁴The phase noise is measured with the EVAL-ADF4210/12/13EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides

the REFIN for the synthesizer. (f_REFOUT= 10 MHz @ 0 dBm)

⁵f_REFIN= 10 MHz; f_PFD= 200 kHz; Offset Frequency = 1 kHz; f_IF= 540 MHz; N = 2700; Loop B/W = 20 kHz

⁶f_REFIN= 10 MHz; f_PFD= 200 kHz; Offset Frequency = 1 kHz; f_RF= 900 MHz; N = 4500; Loop B/W = 20 kHz

⁷f_REFIN= 10 MHz; f_PFD= 200 kHz; Offset Frequency = 1 kHz; f_RF= 1750 MHz; N = 8750; Loop B/W = 20 kHz

⁸f_REFIN= 10 MHz; f_PFD= 1 MHz; Offset Frequency = 1 kHz; f_RF= 2400 MHz; N = 9800; Loop B/W = 20 kHz

⁹Same conditions as listed on the preceding line.

Specifications subject to change without notice.

(V_DD1 = V_DD2 = 2.6 V to 3.3 V; V_P1, V_P2 = V_DDto 5.5 V ; AGND_RF= DGND_RF= AGND_IF= DGND_IF= 0 V;

T_A= T_MINto T_MAX, unless otherwise noted; dBm referred to 50 ꢀ.)

TIMING CHARACTERISTICS

Limit at

T_MINto T_MAX

(B Version)

Parameter

Unit

Test Conditions/Comments

t₁

t₂

t₃

t₄

t₅

t₆

10

25

10

20

ns min

DATA to CLOCK Set-Up Time

DATA to CLOCK Hold Time

CLOCK High Duration

CLOCK Low Duration

CLOCK to LE Set-Up Time

LE Pulsewidth

Guaranteed by design but not production tested.

Specifications subject to change without notice.

t₃

t₄

CLOCK

t₁

t₂

DB1

DB0 (LSB)

(CONTROL BIT C1)

DATA DB20 (MSB)

DB19

DB2

(CONTROL BIT C2)

t₆

LE

t₅

Figure 1. Timing Diagram

–3–

REV. 0

ADF4212L

ABSOLUTE MAXIMUM RATINGS^{1, 2, 3}

(T_A= 25°C, unless otherwise noted.)

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device reliability.

²This device is a high performance RF integrated circuit with an ESD rating of

<2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and

assembly.

V_DD1 to GND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V

V

_DD1 to V_DD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

V_P1, V_P2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V

V_P1, V_P2 to V_DD1, V_DD2 . . . . . . . . . . . . . . . –0.3 V to +3.6 V

Digital I/O Voltage to GND . . . . . . –0.3 V to DV_DD+ 0.3 V

Analog I/O Voltage to GND . . . . . . . . –0.3 V to V_DD+ 0.3 V

REFIN, RFIN, IFIN to GND . . . . . . . –0.3 V to V_DD+ 0.3 V

Operating Temperature Range

³GND = AGND = DGND = 0 V

ORDERING GUIDE

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

TSSOP ␪_JAThermal Impedance . . . . . . . . . . . . . 150.4°C/W

CSP ␪_JAThermal Impedance (Paddle Soldered) . . . 122°C/W

CSP ␪_JAThermal Impedance (Paddle Not Soldered) 216°C/W

Lead Temperature, Soldering

Model

ADF4212LBRU –40°C to +85°C

ADF4212LBCP –40°C to +85°C

Temperature Range Package Option*

RU-20

CP-20

*RU = Thin Shrink Small Outline Package (TSSOP)

CP = Chip Scale Package

Contact the factory for chip availability.

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADF4212L features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN CONFIGURATION

TSSOP

LFCSP

1

2

20

V_DD

1

V_DD

2

19

V_P1

V_P2

20 19 18 17 16

1

2

3

4

5

15

14

13

12

11

CP_RF

DGND_RF

RF_IN

DGND_IF

3

18

17

CP_RF

CP_IF

IF_IN

4

DGND_IF

IF_IN

DGND_RF

RF_IN

ADF4212L

AGND_IF

R_SET

LE

5

ADF4212L 16

CHIP SCALE

PACKAGE

TOP VIEW

AGND_RF

FL_O

6

15

AGND_RF

FL_O

AGND_IF

R_SET

LE

(Not To Scale)

7

14

6

7

8

9

10

13

12

11

REF_IN

8

DGND_IF

9

DATA

CLK

10

MUXOUT

–4–

REV. 0

ADF4212L

PIN FUNCTION DESCRIPTION

Mnemonic

Description

CP_RF

RF Charge Pump Output. When enabled, this provides I_CPto the external RF loop filter, which in turn drives the

external RF VCO.

DGND_RF

RF_IN

AGND_RF

Digital Ground Pin for the RF Digital Circuitry

Input to the RF Prescaler. This small signal input is normally ac-coupled from the RF VCO.

Ground Pin for the RF Analog Circuitry

FL_O

REF_IN

Multiplexed Output of RF/IF Programmable or Reference Dividers, RF/IF Fastlock Mode. CMOS output.

Reference Input. This is a CMOS input with a nominal threshold of V_DD/2 and an equivalent input resistance of 100 kΩ.

See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

Digital Ground Pin for the IF Digital, Interface, and Control Circuitry

DGND_IF

MUXOUT

This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF, or the scaled Reference Frequency

to be accessed externally.

CLK

DATA

LE

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high

impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches, the latch being selected using the control bits.

R_SET

Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output current. The

nominal voltage potential at the R_SETpin is 0.66 V. The relationship between I_CPand R_SETis

13.5

R_SET

I_{CP MAX}

=

so, with R_SET= 2.7 kΩ, I_{CP MAX}= 5 mA for both the RF and IF Charge Pumps.

AGND_IF

IF_IN

CP_IF

Ground Pin for the IF Analog Circuitry

Input to the IF Prescaler. This small signal input is normally ac-coupled from the IF VCO.

Output from the IF Charge Pump. This is normally connected to a loop filter that drives the input to an external VCO.

Power Supply for the IF Charge Pump. This should be greater than or equal to V_DD2. In systems where V_DD2 is 3 V,

it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.

V_P2

V

_DD2

Power Supply for the IF, Digital, and Interface Section. Decoupling capacitors to the ground plane should be placed

as close as possible to this pin. V_DD2 should have a value of between 2.6 V and 3.3 V. V_DD2 must have the same

potential as V_DD1.

V

_DD1

Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as close as possible to

this pin. V_DD1 should have a value of between 2.6 V and 3.3 V. V_DD1 must have the same potential as V_DD2.

Power Supply for the RF Charge Pump. This should be greater than or equal to V_DD1. In systems where V_DD1 is 3 V,

it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.

V_P1

REV. 0

–5–

–Typical Performance Characteristics

ADF4212L

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

V

= 3V,V = 5V

= 5mA

REFERENCE

LEVEL = –3.0dBm

DD P

I

CP

–5

–10

–15

–20

–25

PFD FREQUENCY =

200kHz

LOOP BANDWIDTH =

20kHz

RES. BANDWIDTH = 1Hz

VIDEO BANDWIDTH = 1Hz

SWEEP = 2.5 SECONDS

AVERAGES = 20

V

= 3V

DD

V

= 5V

P

–85.9dB

–30

0

–400k

–200k

1.75G

FREQUENCY – Hz

200k

400k

500

1000

1500

2000

2500

3000

FREQUENCY – MHz

TPC 4. Reference Spurs, RF Side (1750 MHz, 200 kHz, 20 kHz)

TPC 1. Input Sensitivity (RF Input)

rms NOISE =

1.38 DEGREES

10dB/DIV

R

= –50dBc/Hz

L

0

–5

–50

–60

1.38” rms

V

= 3V

DD

= 5V

–70

P

–10

–80

–90

–15

–20

–25

–30

–35

–100

–110

–120

–130

–140

–150

0

500

1000

1500

100Hz

1MHz

FREQUENCY – MHz

FREQUENCY OFFSET

FROM 1.75GHz CARRIER

TPC 2. Input Sensitivity (IF Input)

TPC 5. Integrated Phase Noise (1750 MHz, 200 kHz/20 kHz)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

V

= 3V,V = 5V

P

= 5mA

DD

REFERENCE

LEVEL = –4.3dBm

REFERENCE

V

= 3V,V = 5V

P

= 5mA

DD

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

I

CP

LEVEL = –3.2dBm

I

CP

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 22

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 22

–84.2dBc/Hz

1k 2k

–88.8dBc/Hz

–2k

–1k

1.75G

FREQUENCY – Hz

–2k

–1k

540M

FREQUENCY – Hz

1k

2k

TPC 6. Phase Noise, IF Side (540 MHz, 200 kHz/20 kHz)

TPC 3. Phase Noise, RF Side (1750 MHz, 200 kHz, 20 kHz)

–6–

REV. 0

ADF4212L

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–130

–140

–150

V

= 3V,V = 5V

= 5mA

REFERENCE

DD P

V

= 3V

DD

= 5V

LEVEL = –7.0dBm

I

CP

V

P

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1Hz

VIDEO BANDWIDTH = 1Hz

SWEEP = 2.5 SECONDS

AVERAGES = 20

–160

–170

–180

–89.3dBc

–400k

–200k

200k

400k

540M

FREQUENCY – Hz

10

100

1000

10000

PHASE DETECTOR FREQUENCY – kHz

TPC 7. Reference Spurs, IF Side (540 MHz, 200 kHz, 20 kHz)

TPC 10. Phase Noise Referred to CP Output vs.

PFD Frequency, IF Side

rms NOISE =

0.83 DEGREES

10dB/DIV

R

= –50dBc/Hz

L

6

4

–50

–60

0.83” rms

–70

–80

2

–90

0

–100

–110

–120

–130

–140

–150

–2

–4

–6

0

1

2

3

4

5

100Hz

1MHz

V

–V

FREQUENCY OFFSET

FROM 540MHz CARRIER

CP

TPC 8. Integrated Phase Noise (540 MHz, 200 kHz/20 kHz)

TPC 11. RF Charge Pump Output Characteristics

–130

6

4

V

= 3V

= 5V

DD

V

P

–140

–150

V

P

= 3V

DD

V 2 = 5.5V

2

0

–160

–170

–180

–2

–4

–6

0

1

2

3

4

5

10

100

1000

10000

V

–V

PHASE DETECTOR FREQUENCY – kHz

CP

TPC 9. Phase Noise Referred to CP Output vs.

PFD Frequency, RF Side

TPC 12. IF Charge Pump Output Characteristics

REV. 0

–7–

ADF4212L

0

–10

–20

–30

–40

–50

–20

–40

–60

–80

–60

–70

–80

–90

–100

0

–100

2

1

3

4

5

–40

–20

0

20

40

60

80

100

TUNINGVOLTAGE –V

TEMPERATURE –

C

TPC 13. RF Reference Spurs (200 kHz) vs. V_TUNE

(1750 MHz, 200 kHz, 20 kHz)

TPC 16. IF Phase Noise vs. Temperature

(540 MHz, 200 kHz, 20 kHz)

0

–20

–40

–60

–80

0

–10

–20

–30

–40

–50

–60

–70

–80

–100

–120

–90

–100

0

1

2

3

4

5

0

1

2

3

4

5

TUNINGVOLTAGE –V

TPC 14. IF Reference Spurs (200 kHz) vs. V_TUNE

(1750 MHz, 200 kHz, 20 kHz)

TPC 17. RF Noise vs. V_TUNE

0

–10

–20

–30

–40

–10

–20

–30

–40

–50

–60

–70

–80

–50

–60

–70

–80

–90

–100

–40

–20

0

20

40

60

80

100

0

1

2

3

4

5

TEMPERATURE –

C

TUNINGVOLTAGE –V

TPC 15. RF Phase Noise vs. Temperature

(1750 MHz, 200 kHz, 20 kHz)

TPC 18. IF Noise vs. V_TUNE

–8–

REV. 0

ADF4212L

0

–20

–40

–60

–80

FREQ/

MHz

FREQ/

MHz

s11.IMAG

s11.REAL s11.IMAG

0.97692

s11.REAL

50

–0.021077 1550

0.561872

0.529742

0.514244

0.405754

0.379354

0.312959

0.322646

0.288881

0.199294

0.206914

0.168344

0.092764

0.036125

0.037007

–0.648879

–0.668172

–0.702192

–0.714541

–0.703593

–0.802878

–0.80397

150

250

350

450

550

650

750

850

950

1050

1150

1250

1350

1450

0.942115 –0.110459

0.961217 –0.085802

0.920667 –0.18583

0.897441 –0.245482

0.888164 –0.282399

0.850012 –0.305457

0.760189 –0.358884

0.767363 –0.541032

0.779511 –0.585687

0.761034 –0.482539

0.624825 –0.530108

0.635364 –0.590526

0.630242 –0.592498

0.634506 –0.655932

1650

1750

1850

1950

2050

2150

2250

2350

2450

2550

2650

2750

2850

2950

–0.807055

–0.758619

–0.725029

–0.770837

–0.778619

–0.706197

–0.716939

–100

–120

–0.053842 –0.736527

–40

–20

0

20

40

60

80

100

TPC 21. S Parameter Data for the RF Input

TEMPERATURE –

C

TPC 19. RF Spurs vs. Temperature

0

–20

–40

–60

–80

–100

–120

–40

–20

0

20

40

60

80

100

TEMPERATURE –

C

TPC 20. IF Spurs vs. Temperature

CIRCUIT DESCRIPTION

Reference Input Section

RF/IF Input Stage

The RF/IF Input Stage is shown in Figure 3. It is followed by a

two-stage limiting amplifier to generate the CML (Current Mode

Logic) clock levels needed for the prescaler.

The Reference Input Stage is shown in Figure 2. SW1 and SW2

are normally-closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2 are

opened. This ensures that there is no loading of the REF_INpin

on power-down.

1.6V

BIAS

GENERATOR

AV

DD

POWER-DOWN

CONTROL

2kꢀ

RF

A

B

IN

100kꢀ

NC

SW2

REF

IN

TO R COUNTER

IN

NC

BUFFER

SW1

SW3

AGND

NC = NO CONNECT

NO

Figure 3. RF/IF Input Stage

Figure 2. Reference Input Stage

REV. 0

–9–

ADF4212L

Prescaler (P/P + 1)

Phase Frequency Detector (PFD) and Charge Pump

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 5 is a simplified schematic.

The PFD includes a fixed delay element that sets the width

of the antibacklash pulse. This is typically 3 ns. This pulse ensures

that there is no dead zone in the PFD transfer function and gives a

consistent reference spur level.

The dual-modulus prescaler (P/P + 1), along with the A and B

counters, enables the large division ratio N, to be realized

(N = PB + A). The dual-modulus prescaler, operating at CML

levels, takes the clock from the RF/IF input stage and divides it

down to a manageable frequency for the CMOS A and B

counters in the RF and IF sections. The prescaler in both

sectionsis programmable. It can be set in software to 8/9, 16/17,

32/33, or 64/65. See Table IV and Table VI. It is based on a

synchronous 4/5 core.

UP

HI

D1

Q1

RF/IF A and B Counters

U1

The A and B CMOS counters combine with the dual modulus

prescaler to allow a wide ranging division ratio in the PLL feed-

back counter. The counters are specified to work when the

prescaler output is 200 MHz or less. Typically, they will work

with 250 MHz output from the prescaler. Thus, with an RF

input frequency of 2.5 GHz, a prescaler value of 16/17 is valid,

but a value of 8/9 is not valid.

+IN

CLR1

CHARGE

PUMP

CP

U3

DELAY

DOWN

CLR2

D2 Q2

HI

Pulse Swallow Function

The A and B counters, in conjunction with the dual modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the Reference Frequency divided by R. The

equation for the VCO frequency is as follows:

U2

–IN

Figure 5. RF/IF PFD Simplified Schematic

MUXOUT and Lock Detect

The output multiplexer on the ADF4212L allows the user to

access various internal points on the chip. The state of MUX-

OUT is controlled by P3, P4, P11, and P12. See Table III and

Table V. Figure 6 shows the MUXOUT section in block dia-

gram form.

f_VCO

=

P × B + A × f_REFIN/R

(

[

)

]

f_VCO

=

Output frequency of external voltage controlled

oscillator (VCO)

P

=

Preset modulus of dual modulus prescaler (8/9, 16/17, and so on)

Preset divide ratio of binary 13-bit counter (3 to 8191)

Preset divide ratio of binary 6-bit swallow counter (0 to 63)

External reference frequency oscillator

Lock Detect

B

MUXOUT can be programmed for two types of lock detect:

digital lock detect and analog lock detect. Digital Lock Detect is

active high. It is set high when the phase error on three con-

secutive Phase Detector cycles is less than 15 ns. It will stay set

high until a phase error of greater than 25 ns is detected on any

subsequent PD cycle.

A

f_REFIN

R

Preset divide ratio of binary 14-bit programmable

reference counter (1 to 16383)

The N-channel open-drain Analog Lock Detect should be oper-

ated with an external pull-up resistor of 10 kΩ nominal. When

lock has been detected, it is high with narrow low going pulses.

N = BP + A

12-BIT B

TO PFD

DV

DD

COUNTER

LOAD

FROM RF

INPUT STAGE

PRESCALER

P/P+1

6-BIT A

COUNTER

IF ANALOG LOCK DETECT

IF R COUNTER OUTPUT

MODULUS

CONTROL

IF N COUNTER OUTPUT

MUXOUT

MUX

CONTROL

IF/RF ANALOG LOCK DETECT

RF R COUNTER OUTPUT

RF N COUNTER OUTPUT

RF ANALOG LOCK DETECT

Figure 4. RF/IF A and B Counters

RF/IF R Counter

The 14-bit RF/IF R counter allows the input reference fre-

quency to be divided down to produce the input clock to the

phase frequency detector (PFD). Division ratios from 1 to

16,383 are allowed.

DGND

Figure 6. MUXOUT Schematic

–10–

REV. 0

ADF4212L

RF/IF Input Shift Register

Table I. C2, C1 Truth Table

The ADF4212L digital section includes a 24-bit input shift

register, a 14-bit IF R counter, and an 18-bit IF N counter (com-

prising a 6-bit IF A counter and a 12-bit IF B counter). Also

present is a 14-bit RF R counter and an 18-bit RF N counter

(comprising a 6-bit RF A counter and a 12-bit RF B counter).

Data is clocked into the 24-bit shift register on each rising edge of

CLK. The data is clocked in MSB first. Data is transferred

from the shift register to one of four latches on the rising edge of

LE. The destination latch is determined by the state of the two

control bits (C2, C1) in the shift register. These are the two

LSBs, DB1, and DB0, as shown in the timing diagram of Figure 1.

The truth table for these bits is shown in Table VI. Table I shows a

summary of how the latches are programmed.

Control Bits

C2

C1

Data Latch

0

1

0

1

0

1

IF R Counter

IF N Counter (A and B)

RF R Counter

RF N Counter (A and B)

Table II. Latch Summary

IF R COUNTER LATCH

IF CP CURRENT

SETTING

CONTROL

BITS

15-BIT REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

IFCP2 IFCP1 IFCP0

P4

P3

P2

P1

R15

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1 C2 (0) C1 (0)

IF N COUNTER LATCH

IF

PRESCALER

CONTROL

BITS

12-BIT B COUNTER

6-BIT A COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

P8

P7

P6

P5

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

A6

A5

A4

A3

A2

A1 C2 (0) C1 (1)

RF R COUNTER LATCH

RF CP CURRENT

SETTING

CONTROL

BITS

15-BIT RF REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

RFCP2 RFCP1 RFCP0 P12

P11

P10

P9

R15

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1 C2 (1) C1 (0)

RF N COUNTER LATCH

RF

CONTROL

BITS

12-BIT B COUNTER

6-BIT A COUNTER

PRESCALER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

P17

P16

P15

P14

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

A6

A5

A4

A3

A2

A1 C2 (1) C1 (1)

REV. 0

–11–

ADF4212L

IF R COUNTER LATCH

Table III. IF R Counter Latch Map

IF CP CURRENT

SETTING

CONTROL

BITS

15-BIT IF REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

IFCP2 IFCP1 IFCP0

P4

P3

P2

P1

R15

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1 C2 (0) C1 (0)

R15

R14

R13

..........

R3

R2

R1

DIVIDE RATIO

0

.

0

.

0

.

..........

0

1

.

0

1

0

.

1

0

1

0

.

1

2

3

4

.

..........

.

1

.

1

.

1

.

1

.

0

.

0

.

32764

1

..........

1

0

1

0

1

32765

32766

32767

P1

IF PD POLARITY

0

1

NEGATIVE

POSITIVE

CHARGE PUMP

P2

OUTPUT

0

1

NORMAL

THREE-STATE

P12

P11

P4

P3

MUXOUT

FROM RF R LATCH

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LOGIC LOW STATE

IF ANALOG LOCK DETECT

IF REFERENCE DIVIDER OUTPUT

IF N DIVIDER OUTPUT

RF ANALOG LOCK DETECT

RF/IF ANALOG LOCK DETECT

IF DIGITAL LOCK DETECT

LOGIC HIGH STATE

RF REFERENCE DIVIDER OUTPUT

RF N DIVIDER OUTPUT

THREE-STATE OUTPUT

IF COUNTER RESET

RF DIGITAL LOCK DETECT

RF/IF DIGITAL LOCK DETECT

RF COUNTER RESET

IF AND RF COUNTER RESET

I

(mA)

CP

IFCP2

IFCP1

IFCP0

1.5kꢀ

1.1250

2.2500

3.3750

4.5000

5.6250

6.7500

7.7875

9.0000

2.7kꢀ

5.6kꢀ

0.301

0.602

0.904

1.205

1.506

1.808

2.109

2.411

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.625

1.250

1.875

2.500

3.125

3.750

4.375

5.000

–12–

REV. 0

ADF4212L

IF N COUNTER LATCH

Table IV. IF N Counter Latch Map

IF

CONTROL

BITS

12-BIT B COUNTER

6-BIT A COUNTER

PRESCALER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

P8

P7

P6

P5

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

A6

A5

A4

A3

A2

A1 C2 (0) C1 (1)

A6

A5

..........

A2

A1

A COUNTER

DIVIDE RATIO

P6 P5 PRESCALERVALUE

0

.

0

.

..........

0

1

0

.

0

1

0

1

0

.

0

1

2

3

4

.

0

1

0

1

0

1

8/9

16/17

32/33

64/65

P7 IF POWER-DOWN

0

1

DISABLED

ENABLED

.

..........

.

1

.

1

.

0

.

0

.

60

1

..........

0

1

0

1

61

62

63

P8 IF CP GAIN

0

1

DISABLED

ENABLED

B12

B11

B10

B3

B2

B1

B COUNTER DIVIDE RATIO

0

.

0

.

0

.

..........

0

1

.

1

0

.

1

0

.

3

4

.

..........

.

1

.

1

.

1

.

1

.

0

.

0

.

4092

1

..........

1

0

1

0

1

4093

4094

4095

N = BP+A, P IS PRESCALERVALUE SET INTHE FUNCTION LATCH

B MUST BE GREATERTHAN OR EQUALTO A

2

FOR CONTIGUOUSVALUES OF N, N

IS (P – P)

MIN

REV. 0

–13–

ADF4212L

RF R COUNTER LATCH

Table V. RF R Counter Latch Map

RF CP CURRENT

SETTING

CONTROL

BITS

15-BIT RF REFERENCE COUNTER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

RFCP2 RFCP1 RFCP0 P12

P11

P10

P9

R15

R14

R13

R12

R11

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1 C2 (1) C1 (0)

R15

R14

R13

..........

R3

R2

R1

DIVIDE RATIO

0

.

0

.

0

.

..........

0

1

.

0

1

0

.

1

0

1

0

.

1

2

3

4

.

..........

.

1

.

1

.

1

.

1

.

0

.

0

.

32764

1

..........

1

0

1

0

1

32765

32766

32767

P9

RF PD POLARITY

0

1

NEGATIVE

POSITIVE

RF CHARGE

PUMP OUTPUT

P10

0

1

NORMAL

THREE-STATE

P12

P11

P4

P3

MUXOUT

FROM IF R LATCH

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LOGIC LOW STATE

IF ANALOG LOCK DETECT

IF REFERENCE DIVIDER OUTPUT

IF N DIVIDER OUTPUT

RF ANALOG LOCK DETECT

RF/IF ANALOG LOCK DETECT

IF DIGITAL LOCK DETECT

LOGIC HIGH STATE

RF REFERENCE DIVIDER OUTPUT

RF N DIVIDER OUTPUT

THREE-STATE OUTPUT

IF COUNTER RESET

RF DIGITAL LOCK DETECT

RF/IF DIGITAL LOCK DETECT

RF COUNTER RESET

IF AND RF COUNTER RESET

I

(mA)

CP

RFCP2 RFCP1 RFCP0

1.5kꢀ

2.7kꢀ

5.6kꢀ

0.301

0.602

0.904

1.205

1.506

1.808

2.109

2.411

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.1250

2.2500

3.3750

4.5000

5.6250

6.7500

7.7875

9.0000

0.625

1.250

1.875

2.500

3.125

3.750

4.375

5.000

–14–

REV. 0

ADF4212L

RF N COUNTER LATCH

Table VI. RF N Counter Latch Map

RF

CONTROL

BITS

12-BIT B COUNTER

6-BIT A COUNTER

PRESCALER

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

P17

P16

P15

P14

B12

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

A6

A5

A4

A3

A2

A1 C2 (1) C1 (1)

A6

A5

..........

A2

A1

A COUNTER

DIVIDE RATIO

P15 P14 PRESCALERVALUE

0

.

0

.

..........

0

1

0

.

0

1

0

1

0

.

0

1

2

3

4

.

0

1

0

1

0

1

8/9

16/17

32/33

64/65

P16 RF POWER-DOWN

0

1

DISABLED

ENABLED

.

..........

.

1

.

1

.

0

.

0

.

60

1

..........

0

1

0

1

61

62

63

P17 RF CP GAIN

B12

B11

B10

B3

B2

B1

B COUNTER DIVIDE RATIO

0

1

DISABLED

ENABLED

0

.

0

.

0

.

..........

0

1

.

1

0

.

1

0

.

3

4

.

..........

.

..........

.

1

.

1

.

1

.

1

.

0

.

0

.

4092

1

..........

1

0

1

0

1

4093

4094

4095

N = BP+A, P IS PRESCALERVALUE SET INTHE FUNCTION LATCH

B MUST BE GREATERTHAN OR EQUALTO A

2

FOR CONTIGUOUSVALUES OF N, N

IS (P – P)

MIN

REV. 0

–15–

ADF4212L

PROGRAM MODES

Table III and Table V show how to set up the Program Modes

in the ADF4212L. The following should be noted:

The REF_INoscillator circuit is only disabled if both the IF and

RF power-downs are set.

The input register and latches remain active and are capable of

loading and latching data during all power-down modes.

1. IF and RF Analog Lock Detect indicate when the PLL is in

lock. When the loop is locked and either IF or RF Analog

Lock Detect is selected, then the MUXOUT pin will show a

logic high with narrow low going pulses. When the IF/RF

Analog Lock Detect is chosen, then the locked condition is

indicated only when both IF and RF loops are locked.

The IF/RF section of the devices will return to normal powered-up

operation immediately upon LE latching a “0” to the appropriate

Power-Down Bit.

IF SECTION

2. The IF Counter Reset Mode resets the R and AB counters in

the IF section and also puts the IF charge pump into three-

state. The RF Counter Reset Mode resets the R and AB

counters in the RF section and also puts the RF charge pump

into three-state. The IF and RF Counter Reset Mode does

both of the above. Upon removal of the reset bits, the AB

counter resumes counting in close alignment with the R

counter. (Maximum error is one prescaler output cycle.)

PROGRAMMABLE IF REFERENCE (R) COUNTER

If control bits C2, C1 are 0, 0, the data is transferred from the input

shift register to the 14-bit IFR counter. Table III shows the input shift

register data format for the IFR counter and the divide ratios possible.

IF Phase Detector Polarity

P1 sets the IF Phase Detector Polarity. When the IF VCO char-

acteristics are positive, this should be set to “1.” When they are

negative, it should be set to “0.” See Table III.

3. The Fastlock Mode uses MUXOUT to switch a second loop

filter damping resistor to ground during Fastlock operation.

Activation of Fastlock occurs whenever RF CP Gain in the

RF Reference counter is set to “1.”

IF Charge Pump Three-State

P2 puts the IF charge pump into three-state mode when pro-

grammed to a “1.” It should be set to “0” for normal operation.

See Table III.

IF Power-Down

It is possible to program the ADF4210 family for either synchro-

nous or asynchronous power-down on either the IF or RF side.

IF PROGRAM MODES

Table III and Table V show how to set up the Program Modes

in the ADF4212L.

Synchronous IF Power-Down

Programming a “1” to P7 of the ADF4212L will initiate a power-

down. If P2 of the ADF4212L has been set to “0” (normal

operation), a synchronous power-down is conducted. The device

will automatically put the charge pump into three-state and com-

plete the power-down.

IF Charge Pump Currents

IFCP2, IFCP1, IFCP0 program Current Setting for the IF

charge pump. See Table III.

PROGRAMMABLE IF AB COUNTER

If control bits C2, C1 are 0, 1, the data in the input register is used

to program the IF AB counter. The N counter consists of a 6-bit

swallow counter (A counter) and 12-bit programmable counter (B

counter). Table IV shows the input register data format for pro-

gramming the IF AB counter and the divide ratios possible.

Asynchronous IF Power-Down

If P2 of the ADF4212L has been set to “1” (three-state the IF

charge pump) and P7 is subsequently set to “1,” an asynchronous

power-down is conducted. The device will go into power-down on

the rising edge of LE, which latches the “1” to the IF Power-

Down Bit (P7).

IF Prescaler Value

P5 and P6 in the IF A, B Counter Latch set the IF prescaler

values. See Table IV.

Synchronous RF Power-Down

Programming a “1” to P16 of the ADF4212L will initiate a

power-down. If P10 of the ADF4212L has been set to “0”

(normal operation), a synchronous power-down is conducted.

The device will automatically put the charge pump into three-

state and then complete the power-down.

IF Power-Down

Table III and Table V show the power-down bits in the ADF4212L.

IF Fastlock

The IF CP Gain Bit (P8) of the IF N Register in the ADF4212L

is the Fastlock Enable Bit. Only when this is “1” is IF Fastlock

enabled. When Fastlock is enabled, the IF CP current is set to

maximum value. Also an extra loop filter damping resistor to

ground is switched in using the FL_Opin, thus compensating for

the change in loop characteristics while in Fastlock. Since the IF

CP Gain Bit is contained in the IF N Counter, only one write is

needed to both program a new output frequency and initiate Fast-

lock. To come out of fastlock, the IF CP Gain bit on the IF N

Register must be set to “0.” See Table IV.

Asynchronous RF Power-Down

If P10 of the ADF4212L has been set to “1” (three-state the RF

charge pump) and P16 is subsequently set to “1,” an asynchronous

power-down is conducted. The device will go into power-down on

the rising edge of LE, which latches the “1” to the RF Power-

Down Bit (P16).

Activation of either synchronous or asynchronous power-down

forces the IF/RF loop’s R and AB dividers to their load state

conditions and the IF/RF input section is debiased to a high

impedance state.

–16–

REV. 0

ADF4212L

RF SECTION

RF Power-Down

Programmable RF Reference (R) Counter

If control bits C2, C1 are 1, 0, the data is transferred from

the input shift register to the 14-bit RFR counter. Table V

shows the input shift register data format for the RFR counter

and the divide ratios possible.

Table III and Table V show the power-down bits in the

ADF4210 family.

RF Fastlock

The RF CP Gain Bit (P17) of the RF N Register in the ADF4212L

is the Fastlock Enable Bit. Only when this is “1” is IF Fastlock

enabled. When Fastlock is enabled, the RF CP current is set to

maximum value. Also, an extra loop filter damping resistor to

ground is switched in using the FL_Opin, thus compensating for

the change in loop characteristics while in Fastlock. Since the

RF CP Gain Bit is contained in the RF N counter, only one

write is needed to both program a new output frequency and

initiate Fastlock. To come out of Fastlock, the RF CP Gain Bit

on the RF N Register must be set to “0.” See Table VI.

RF Phase Detector Polarity

P9 sets the IF Phase Detector Polarity. When the RF VCO charac-

teristics are positive, this should be set to “1.” When they are

negative, it should be set to “0.” See Table V.

RF Charge Pump Three-State

P10 puts the RF charge pump into three-state mode when pro-

grammed to a “1.” It should be set to “0” for normal operation.

See Table V.

RF Program Modes

Table III and Table V show how to set up the Program Modes

in the ADF4212L.

APPLICATION SECTION

Local Oscillator for GSM Handset Receiver

Figure 7 shows the ADF4212L being used with a VCO to produce

the required LOs for a GSM base station transmitter or receiver.

The reference input signal is applied to the circuit at FREF_IN

and, in this case, is terminated in 50 Ω. Typical GSM systems

would have a 13 MHz TCXO driving the Reference Input without

any 50 Ω termination. In order to have a channel spacing of

200 kHz (the GSM standard), the reference input must be divided

by 65, using the on-chip reference.

RF Charge Pump Currents

RFCP2, RFCP1, RFCP0 program Current Setting for the RF

charge pump. See Table V.

Programmable RF N Counter

If control bits C2, C1 are 1, 1, the data in the input register is used

to program the RF N (A + B) counter. The N counter consists

of a 6-bit swallow counter (A counter) and 12-bit programmable

counter (B counter). Table IV shows the input register data format

for programming the RF N counter and the divide ratios possible.

See Table VI.

The RF output frequency range is 880 MHz to 915 MHz. The

loop filter is designed to give a 20 kHz loop bandwidth. The

filter is set up for a 5 mA charge pump current, and the VCO

sensitivity is 12 MHz/V. The IF output is fixed at 540 MHz.

The filter is again designed to have a bandwidth of 20 kHz, and

the system is programmed to give channel steps of 200 kHz.

RF Prescaler Value

P14 and P15 in the RF A, B Counter Latch set the RF prescaler

values. See Table VI.

RF

IF

OUT

V

P

DD

100pF

18ꢀ

V 2

V

2

V 1

DD

V 1

P

100pF

P

DD

3.3kꢀ

18ꢀ

V

CC

CP

RF

IF

VCO190-540T

VCO190-902U

18ꢀ

1.3nF

620pF

2.7kꢀ

ADF4212L

13nF

R

SET

2.7kꢀ

LOCK

DETECT

MUXOUT

100pF

RF

IN

IF

IN

51ꢀ

CLK

DATA

LE

1000pF 1000pF

SPI COMPATIBLE SERIAL BUS

FREF

REF

IN

51ꢀ

DECOUPLING CAPACITORS (22ꢁF/10pF) ONV , V OFTHE ADF4212L AND ONV OFTHE VCOs

CC

DD

P

HAVE BEEN OMITTED FROMTHE DIAGRAMTO AID CLARITY.

Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4212L

REV. 0

–17–

ADF4212L

Wideband PLL

In narrow-band applications, there is generally a small variation

in output frequency (generally less than 10%) and also a small

variation in VCO sensitivity over the range (typically <10%).

However in wideband applications both of these parameters

have a much greater variation. Variations in these parameters will

change the loop bandwidth. This in turn can affect stability

and lock time. By changing the programmable I_CP, it is possible

to get compensation for these varying loop conditions and ensure

that the loop is always operating close to optimal conditions.

Many of the wireless applications for synthesizers and VCOs in

PLLs are narrow-band in nature. These applications include the

various wireless standards like GSM, DSC1800, CDMA, or

WCDMA. In each of these cases, the total tuning range for the

local oscillator is less than 100 MHz. However, there are also

wideband applications where the local oscillator could have up

to an octave tuning range. For example, cable television tuners

have a total range of about 400 MHz. Figure 8 shows an appli-

cation where the ADF4212L is used to control and program the

Micronetics M3500-1324. The loop filter was designed for an

RF output of 2100 MHz, a loop bandwidth of 40 kHz, a PFD

frequency of 1 MHz, I_CPof 10 mA (2.5 mA synthesizer I_CP

multiplied by the gain factor of 4), VCO K_Dof 80 MHz/V (sen-

sitivity of the M3500-1324 at an output of 2100 MHz) and a

phase margin of 45 degrees.

RF

OUT

V

20V

12V

P

DD

100pF

V

CC

3kꢀ

AD820

1kꢀ

100pF

18ꢀ

V

1

V

2

V 1 V 2

DD

P

V_TUNE

M3500-1324

GND

OUT

20kꢀ

CP

RF

1000pF 1000pF

FREF

REF

IN

3.9nF

27nF

130pF

R

SET

51ꢀ

2.7kꢀ

470ꢀ

ADF4212L

CLK

LOCK

DETECT

SPI COMPATIBLE SERIAL BUS DATA

LE

MUXOUT

100pF

RF

IN

51ꢀ

DECOUPLING CAPACITORS ONV , V OFTHE ADF4212L, ONV

DD

OFTHE AD820 AND ON

P

CC

V

OFTHE M3500-2250 HAVE BEEN OMITTED FROMTHE DIAGRAMTO AID CLARITY.

CC

THE IF SECTION OFTHE CIRCUIT HAS ALSO BEEN OMITTEDTO SIMPLIFYTHE SCHEMATIC.

Figure 8. Wideband PLL Circuit

–18–

REV. 0

ADF4212L

Interfacing

ADSP-2181 Interface

The ADF4212L has a simple SPI compatible serial interface for

writing to the device. SCLK, SDATA, and LE control the data

transfer. When LE (Latch Enable) goes high, the 22 bits that

have been clocked into the input register on each rising edge of

SCLK will get transferred to the appropriate latch. See Figure 1

for the Timing Diagram and Table I for the Latch Truth Table.

Figure 10 shows the interface between the ADF4212L and the

ADSP-21xx Digital Signal Processor. As previously discussed, the

ADF4212L needs a 24-bit serial word for each latch write. The

easiest way to accomplish this using the ADSP-21xx family is to

use the Autobuffered Transmit Mode of operation with Alter-

nate Framing. This provides a means for transmitting an

entire block of serial data before an interrupt is generated. Set

up the word length for eight bits and use three memory loca-

tions for each 24-bit word. To program each 24-bit latch, store

the three 8-bit bytes, enable the Autobuffered Mode, and

then write to the transmit register of the DSP. This last opera-

tion initiates the autobuffer transfer.

The maximum allowable serial clock rate is 20 MHz. This means that

the maximum update rate possible for the device is 909 kHz or one

update every 1.1 µs. This is certainly more than adequate for systems

that will have typical lock times in hundreds of microseconds.

ADuC812 Interface

Figure 9 shows the interface between the ADF4212L and the

ADuC812 microconverter. Since the ADuC812 is based on an

8051 core, this interface can be used with any 8051-based

microcontroller. The microconverter is set up for SPI Master

Mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4212L needs a

24-bit word. This is accomplished by writing three 8-bit bytes

from the microconverter to the device. When the third byte has

been written, the LE input should be brought high to complete

the transfer.

ADuC812

ADF4212L

SCLK

MOSI

SCLK

SDATA

LE

CE

I/O PORTS

MUXOUT

(LOCK DETECT)

Figure 9. ADuC812 to ADF4212L Interface

On first applying power to the ADF4212L, four writes (one each to

the R counter latch and the AB counter latch for both IF and

RF side) are required for the output to become active.

ADSP-21xx

ADF4212L

When operating in the mode described, the maximum SCLOCK rate

of the ADuC812 is 4 MHz. This means that the maximum rate

at which the output frequency can be changed will be 180 kHz.

SCLK

DT

SCLK

SDATA

TFS

LE

CE

I/O FLAGS

MUXOUT

(LOCK DETECT)

Figure 10. ADSP-21xx to ADF4212L Interface

REV. 0

–19–

ADF4212L

OUTLINE DIMENSIONS

20-Lead Thin Shrink Small Outline Package (TSSOP)

(RU-20)

Dimensions shown in millimeters

6.60

6.50

6.40

20

11

10

4.50

4.40

4.30

6.40 BSC

1

PIN 1

0.65

BSC

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8ꢂ

0ꢂ

0.30

0.19

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153AC

20-Lead Frame Chip Scale Package (LFCSP)

4x4 mm Body

(CP-20)

Dimensions shown in millimeters

0.60

MAX

4.0

BSC SQ

0.60

MAX

16

15

20

1

5

PIN 1

INDICATOR

2.25

2.10 SQ

1.95

3.75

BSC SQ

TOP

VIEW

BOTTOM

VIEW

11

10

0.75

0.55

0.35

6

0.70 MAX

0.65 NOM

0.30

0.23

0.18

12ꢂ MAX

1.00

0.90

0.80

0.05

0.02

0.00

SEATING

PLANE

COPLANARITY

0.08

0.50

BSC

0.25

REF

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

–20–

REV. 0


型号：	ADF4212LBCP
厂家：	ADI
描述：	Dual Low Power PLL Frequency Synthesizer 双路低功耗锁相环频率合成器
文件：	总20页 (文件大小：241K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADF4212LBCP [ADI]

相关型号：

ADF4212LBCP-REEL

ADF4212LBCP-REEL7

ADF4212LBCPZ-REEL

ADF4212LBCPZ-REEL7

ADF4212LBCPZ-RL7

ADF4212LBRU

ADF4212LBRU-REEL

ADF4212LBRU-REEL7

ADF4212LBRUZ

ADF4212LBRUZ-REEL

ADF4212LBRUZ-REEL7

ADF4212LBRUZ-RL