ADF5355 [ADI]
Microwave Wideband Synthesizer with Integrated VCO;![ADF5355](http://pdffile.icpdf.com/pdf2/p00333/img/icpdf/ADF5355_2050092_icpdf.jpg)
型号: | ADF5355 |
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描述: | Microwave Wideband Synthesizer with Integrated VCO |
文件: | 总38页 (文件大小:795K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Microwave Wideband Synthesizer
with Integrated VCO
Data Sheet
ADF5355
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 54 MHz to 13,600 MHz
Fractional-N synthesizer and integer-N synthesizer
High resolution 38-bit modulus
The ADF5355 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
when used with an external loop filter and an external reference
frequency. The wideband microwave VCO design permits
frequency operation from 6.8 GHz to 13.6 GHz at one radio
frequency (RF) output. A series of frequency dividers at another
frequency output permits operation from 54 MHz to 6800 MHz.
Phase frequency detector (PFD) operation to 125 MHz
Reference frequency operation to 600 MHz
Maintains frequency lock over −40°C to +85°C
Low phase noise, voltage controlled oscillator (VCO)
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Analog and digital power supplies: 3.3 V
Charge pump and VCO power supplies: 5.0 V, typical
Logic compatibility: 1.8 V
The ADF5355 has an integrated VCO with a fundamental
output frequency ranging from 3400 MHz to 6800 MHz. In
addition, the VCO frequency is connected to divide by 1, 2, 4, 8,
16, 32, or 64 circuits that allow the user to generate RF output
frequencies as low as 54 MHz. For applications that require
isolation, the RF output stage can be muted. The mute function
is both pin and software controllable.
Programmable dual modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
Analog and digital lock detect
Control of all on-chip registers is through a simple 3-wire interface.
The ADF5355 operates with analog and digital power supplies
ranging from 3.15 V to 3.45 V, with charge pump and VCO
supplies from 4.75 V to 5.25 V. The ADF5355 also contains
hardware and software power-down modes.
Supported in the ADIsimPLL design tool
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA,
WiMAX, GSM, PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
Clock generation
FUNCTIONAL BLOCK DIAGRAM
AV
DV
V
R
V
VCO
AV
V
RF
CE
DD
DD
P
SET
DD
MULTIPLEXER
MUXOUT
10-BIT R
COUNTER
÷2
DIVIDER
REF
A
B
IN
×2
DOUBLER
C
1
2
REG
REG
LOCK
DETECT
REF
IN
C
CLK
DATA
LE
CHARGE
PUMP
CP
OUT
DATA REGISTER
FUNCTION
LATCH
PHASE
COMPARATOR
V
V
TUNE
REF
V
VCO
CORE
BIAS
×2
INTEGER
REG
FRACTION
REG
MODULUS
REG
V
REGVCO
OUTPUT
STAGE
RF
B
THIRD-ORDER
FRACTIONAL INTERPOLATOR
OUT
PDB
RF
RF
÷ 1/2/4/8/
16/32/64
A+
A–
OUTPUT
STAGE
OUT
N COUNTER
RF
OUT
ADF5355
MULTIPLEXER
A
CP
SD
A
GNDVCO
A
GND
GND
GND
GNDRF
Figure 1.
4
Rev. D
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Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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ADF5355
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 4 ..................................................................................... 26
Register 5 ..................................................................................... 27
Register 6 ..................................................................................... 28
Register 7 ..................................................................................... 30
Register 8 ..................................................................................... 31
Register 9 ..................................................................................... 31
Register 10................................................................................... 32
Register 11................................................................................... 32
Register 12................................................................................... 33
Register Initialization Sequence ............................................... 33
Frequency Update Sequence..................................................... 33
RF Synthesizer—A Worked Example ...................................... 34
Reference Doubler and Reference Divider ............................. 34
Spurious Optimization and Fast Lock..................................... 34
Optimizing Jitter......................................................................... 35
Spur Mechanisms ....................................................................... 35
Lock Time.................................................................................... 35
Applications Information .............................................................. 36
Power Supplies............................................................................ 36
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings............................................................ 8
Transistor Count........................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Circuit Description......................................................................... 16
Reference Input........................................................................... 16
RF N Divider............................................................................... 16
Phase Frequency Detector (PFD) and Charge Pump............ 17
MUXOUT and Lock Detect...................................................... 17
Input Shift Registers................................................................... 17
Program Modes .......................................................................... 18
VCO.............................................................................................. 18
Output Stage................................................................................ 18
Register Maps.................................................................................. 20
Register 0 ..................................................................................... 22
Register 1 ..................................................................................... 23
Register 2 ..................................................................................... 24
Register 3 ..................................................................................... 25
Printed Circuit Board (PCB) Design Guidelines for a Chip-
Scale Package .............................................................................. 36
Output Matching........................................................................ 37
Outline Dimensions....................................................................... 38
Ordering Guide .......................................................................... 38
Rev. D | Page 2 of 38
Data Sheet
ADF5355
REVISION HISTORY
8/2017—Rev. C to Rev D
Changes to Table 4 ..........................................................................10
Changes to Figure 4 to Figure 6 ....................................................11
Added Figure 7 to Figure 9; Renumbered Sequentially.............11
Changes to Figure 10 to Figure 18 ................................................12
Changes to Figure 20 ......................................................................13
Changes to Figure 23 and Figure 27.............................................14
Changes to Figure 28 to Figure 30 and Figure 31 Caption........15
Changes to Reference Input Section and INT, FRAC, MOD,
and R Counter Relationship Section ............................................16
Changes to Phase Frequency Detector (PFD) and Charge Pump
Section ..............................................................................................17
Changes to VCO Section and Output Stage Section..................18
Changes to Automatic Calibration (AUTOCAL) Section.........22
Changes to Figure 43 ......................................................................24
Changes to MUXOUT Section......................................................26
Changes to Reference Mode Section and Counter Reset
Section ..............................................................................................27
Changes to Negative Bleed Section...............................................28
Changes to Charge Pump Bleed Current Section.......................29
Changes to Register 9 Section, VCO Band Division Section,
Timeout Section, Automatic Level Calibration Timeout Section,
and Synthesizer Lock Timeout Section........................................31
Changes to ADC Conversion Clock (ADC_CLK_DIV)
Changes to Frequency Update Sequence Section.......................34
Updated Outline Dimensions........................................................38
Changes to Ordering Guide...........................................................38
4/2017—Rev. B to Rev C
Changes to Figure 55 and Power Supplies Section .....................36
1/2017—Rev. A to Rev B
Change to Features Section..............................................................1
Changes to Doubler Enabled Parameter and Endnote 3, Table 1.....4
Changes to Table 2 ............................................................................7
Changes to Table 3 ............................................................................8
Changes to Table 4 ............................................................................9
Changes to Reference Input Section and Figure 32 Caption.....16
Changes to Table 6 ..........................................................................19
Changes to Phase Resync Section.................................................25
Change to Reference Doubler Section..........................................26
Changes to Power-Down Section..................................................27
Changes to Negative Bleed Section...............................................28
Changes to Loss of Lock (LOL) Mode Section............................30
Changes to Register Initialization Sequence Section and Frequency
Update Sequence Section .................................................................33
Changes to Power Supplies Section and Figure 55 .....................36
Section ..............................................................................................32
Changes to Phase Resync Clock Divider Value Section and
Frequency Update Sequence Section............................................33
Changes to RF Synthesizer—A Worked Example Section ........34
Changes to Lock Time Section and Automatic Level
2/2015—Rev. 0 to Rev. A
Changed Register 5, Bit DB5 Value from 0 to 1 ........ Throughout
Changed Register 5 Default Value from 0x00800005 to
0x00800025 .................................................................... Throughout
Changed Register 8 Default Value from 0x102D4028 to
0x102D0428 ................................................................... Throughout
Changes to Table 1 ............................................................................4
Changed Timing Diagram Section to Write Timing Diagram
Section ................................................................................................7
Calibration Timeout Section .........................................................35
Added Lock Time—A Worked Example Section .......................35
10/2014—Revision 0: Initial Version
Rev. D | Page 3 of 38
ADF5355
Data Sheet
SPECIFICATIONS
AVDD = DVDD = VRF = 3.3 V 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, R SET = 5.1 kΩ, dBm referred
to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
REFINA/REFINB CHARACTERISTICS
Input Frequency
For f < 10 MHz, ensure slew rate >
21 V/µs
Single-Ended Mode
Differential Mode
Doubler Enabled
Input Sensitivity
10
10
250
600
100
MHz
MHz
MHz
Doubler is set in Register 4, Bit DB26
Single-Ended Mode
0.4
0.4
AVDD
1.8
V p-p
V p-p
REFINA biased at AVDD/2;
ac coupling ensures AVDD/2 bias
LVDS and LVPECL compatible,
REFINA/REFINB biased at 2.1 V;
ac coupling ensures 2.1 V bias
Differential Mode
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
6.9
1.4
pF
pF
µA
µA
MHz
60
250
125
Single-ended reference programmed
Differential reference programmed
Phase Detector Frequency
CHARGE PUMP (CP)
Charge Pump Current, Sink/Source
High Value
Low Value
RSET Range
Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
ICP
RSET = 5.1 kΩ
4.8
0.3
5.1
3
3
1.5
mA
mA
kΩ
%
%
%
Fixed
0.5 V ≤ VCP1 ≤ VP − 0.5 V
0.5 V ≤ VCP1 ≤ VP − 0.5 V
VCP1 = 2.5 V
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance
LOGIC OUTPUTS
Output High Voltage
VINH
VINL
IINH/IINL
CIN
1.5
V
V
µA
pF
0.6
1
3.0
1.8
VOH
DVDD
0.4
1.5
−
V
V
1.8 V output selected
Output High Current
Output Low Voltage
IOH
VOL
500
0.4
µA
V
IOL2 = 500 µA
See Table 6
POWER SUPPLIES
Analog Power
AVDD
3.15
4.75
3.45
V
V
Digital Power and RF Supply Voltage
Charge Pump and VCO Supply Voltage
Charge Pump Supply Power Current
DVDD, VRF
VP, VVCO
IP
AVDD
5.0
8
62
6 to
36
Voltages must equal AVDD
VP must equal VVCO
5.25
9
69
3
DIDD + AIDD
mA
mA
Output Dividers
Supply Current
Each output divide by 2 consumes
6 mA
IVCO
70
85
mA
Rev. D | Page 4 of 38
Data Sheet
ADF5355
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
RFOUTA /RFOUTB Supply Current
IRF
OUTx
RFOUTA output stage is
programmable; enabling RFOUT
B
draws negligible extra current
16
30
42
55
500
1000
20
35
50
70
mA
mA
mA
mA
µA
−4 dBm setting
−1 dBm setting
2 dBm setting
5 dBm setting
Hardware power-down selected
Software power-down selected
Low Power Sleep Mode
µA
RF OUTPUT CHARACTERISTICS
VCO Frequency Range
RFOUTB Output Frequency
RFOUTA+/RFOUTA− Output Frequency
VCO Sensitivity
3400
6800
53.125
6800
13600
6800
MHz
MHz
MHz
MHz/V
MHz/V
MHz
Fundamental VCO range
2× VCO output (RFOUTB)
KV
15
15
0.5
Frequency Pushing (Open-Loop)
Frequency Pulling (Open-Loop)
Voltage standing wave ratio (VSWR) =
2:1 RFOUTA+/RFOUTA−
30
MHz
VSWR = 2:1 RFOUTB
Harmonic Content
Second
−27
−22
−20
−12
−8
dBc
dBc
dBc
dBc
dBm
dBc
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
RFOUTB = 10 GHz
RFOUTA+/RFOUTA− = 1 GHz;
VCO frequency = 4 GHz
RFOUTA+ = 1 GHz; 7.5 nH inductor to VRF
Third
Fundamental VCO Feedthrough
−55
RF Output Power4
+8
−3
dBm
dBm
RFOUTA+/RFOUTA− = 6.8 GHz;
7.5 nH inductor to VRF
1
−1
1
dBm
dBm
dB
RFOUTB = 6.8 GHz
RFOUTB = 13.6 GHz
RFOUTA+/RFOUTA− = 5 GHz
RFOUTB = 10 GHz
RF Output Power Variation
1
dB
RF Output Power Variation (over Frequency)
Level of Signal with RF Output Disabled
6
4
−60
−30
−15
−17
dB
dB
dBm
dBm
dBm
dBm
RFOUTA+/RFOUTA− = 1 GHz to 6.8 GHz
RFOUTB = 6.8 GHz to 13.6 GHz
RFOUTA+/RFOUTA− = 1 GHz
RFOUTA+/RFOUTA− = 6.8 GHz
RFOUTB = 6.8 GHz
RFOUTB = 13.6 GHz
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise Performance
VCO noise in open-loop conditions
100 kHz offset from 3.4 GHz carrier
800 kHz offset from 3.4 GHz carrier
1 MHz offset from 3.4 GHz carrier
10 MHz offset from 3.4 GHz carrier
100 kHz offset from 5.0 GHz carrier
800 kHz offset from 5.0 GHz carrier
1 MHz offset from 5.0 GHz carrier
10 MHz offset from 5.0 GHz carrier
100 kHz offset from 6.8 GHz carrier
800 kHz offset from 6.8 GHz carrier
1 MHz offset from 6.8 GHz carrier
10 MHz offset from 6.8 GHz carrier
−116
−136
−138
−155
−113
−133
−135
−153
−110
−130
−132
−150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. D | Page 5 of 38
ADF5355
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
VCO 2× Phase Noise Performance
VCO noise in open-loop conditions
100 kHz offset from 6.8 GHz carrier
800 kHz offset from 6.8 GHz carrier
1 MHz offset from 6.8 GHz carrier
10 MHz offset from 6.8 GHz carrier
100 kHz offset from 10 GHz carrier
800 kHz offset from 10 GHz carrier
1 MHz offset from 10 GHz carrier
10 MHz offset from 10 GHz carrier
100 kHz offset from 13.6 GHz carrier
800 kHz offset from 13.6 GHz carrier
1 MHz offset from 13.6 GHz carrier
10 MHz offset from 13.6 GHz carrier
−110
−130
−132
−149
−107
−127
−129
−147
−103
−124
−126
−144
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Normalized In-Band Phase Noise Floor
Fractional Channel5
−221
−223
−116
150
dBc/Hz
dBc/Hz
dBc/Hz
fs
Integer Channel6
7
Normalized 1/f Noise, PN1_f
10 kHz offset; normalized to 1 GHz
Integrated RMS Jitter
Spurious Signals due to PFD Frequency
−80
dBc
1 VCP is the voltage at the CPOUT pin.
2 IOL is the output low current.
3 TA = 25°C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5.0 V; prescaler = 4/5; fREF = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz. For the nominal DIDD + AIDD (62 mA):
IN
DIDD = 15 mA (typical), AIDD (Pin 5) = 24 mA (typical), AIDD (Pin 16) = 23 mA (typical).
4 RF output power using the EV-ADF5355SD1Z evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. Unused RF output pins
are terminated in 50 Ω.
5 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−221 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel.
6 Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−223 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel.
7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF
and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the
ADIsimPLL design tool.
)
Rev. D | Page 6 of 38
Data Sheet
ADF5355
TIMING CHARACTERISTICS
AVDD = DVDD =VRF = 3.3 V ꢀ%, 4.7ꢀ V ≤ VP = VVCO ≤ ꢀ.2ꢀ V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = ꢀ.1 kΩ, dBm referred
to ꢀ0 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Write Timing
Parameter
Limit
Unit
Description
fCLK
t1
t2
t3
t4
t5
t6
t7
50
10
5
5
10
10
5
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Serial peripheral interface CLK frequency
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
20 (or 2/fPFD, whichever is longer)
Write Timing Diagram
t4
t5
CLK
t2
t3
DB3
DB2
DB1
DB0 (LSB)
(CONTROL BIT C1)
DB31 (MSB)
DB30
DATA
LE
(CONTROL BIT C4)
(CONTROL BIT C3)
(CONTROL BIT C2)
t7
t1
t6
Figure 2. Write Timing Diagram
Rev. D | Page 7 of 38
ADF5355
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3.
Parameter
VRF, DVDD, AVDD to GND1, 2
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to VP + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
2.1 V
AVDD to DVDD
VP, VVCO to GND1
CPOUT to GND1
Digital Input/Output Voltage to GND1
Analog Input/Output Voltage to GND1
REFINA, REFINB to GND1
REFINA to REFINB
The ADF5355 is a high performance RF integrated circuit with
an ESD rating of 2.5 kV and is ESD sensitive. Take proper
precautions for handling and assembly.
TRANSISTOR COUNT
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
−40°C to +85°C
−65°C to +125°C
150°C
The transistor count for the ADF5355 is 103,665 (CMOS) and
3214 (bipolar).
ESD CAUTION
θJA, Thermal Impedance Paddle
Soldered to GND1
27.3°C/W
Reflow Soldering
Peak Temperature
260°C
40 sec
Time at Peak Temperature
Electrostatic Discharge (ESD)
Charged Device Model
Human Body Model
1000 V
2500 V
1 GND = AGND = SDGND = AGNDRF = AGNDVCO = CPGND = 0 V.
2 Do not connect VRF to DVDD
.
Rev. D | Page 8 of 38
Data Sheet
ADF5355
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK
DATA
LE
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
V
V
R
A
V
BIAS
REF
SET
ADF5355
TOP VIEW
(Not to Scale)
CE
GNDVCO
AV
DD
TUNE
V
A
V
V
P
REGVCO
CP
CP
GNDVCO
VCO
OUT
GND
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO A
.
GND
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLK
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
2
3
4
DATA
LE
Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits
(LSBs) as the control bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
that is selected by the four LSBs.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
A logic high (at levels equal to DVDD) on this pin powers up the device, depending on the status of the power-
down bits. Register contents are retained unless the supply voltages are removed.
CE
5, 16
AVDD
VP
Analog Power Supply. This pin ranges from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog
ground plane as close to this pin as possible. AVDD must have the same value as DVDD.
Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the
ground plane as close to this pin as possible.
Charge Pump Output. When enabled, this output provides ICP to the external loop filter. The output of the
loop filter is connected to VTUNE to drive the internal VCO.
6
7
CPOUT
8
9
10
CPGND
AGND
VRF
Charge Pump Ground. This output is the ground return pin for CPOUT.
Analog Ground. Ground return pin for AVDD.
Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this
pin as possible. VRF must have the same value as AVDD. Do not connect VRF to DVDD.
11
12
RFOUTA+
RFOUTA−
AGNDRF
VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is
available. This pin can be left floating if RFOUTA is disabled in Register 6 or by the PDBRF pin.
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided
down version is available. This pin can be left floating if RFOUTA is disabled in Register 6 or by the PDBRF pin.
RF Output Stage Ground. Ground return pins for the RF output stage.
Auxiliary VCO Output. The 2× VCO output is available at this pin.
Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Place decoupling capacitors to
the analog ground plane as close to this pin as possible. For best performance, this supply must be clean and
have low noise.
13, 15
14
17
RFOUT
VVCO
B
18, 21
19
AGNDVCO
VREGVCO
VCO Ground. Ground return path for the VCO.
VCO Compensation Node. Place decoupling capacitors to the ground plane as close to this pin as possible.
Connect this pin directly to VVCO
.
20
22
VTUNE
RSET
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage. The input capacitance of this pin is 9 pF.
No Connection. Charge pump bias resistance is internal.
Rev. D | Page 9 of 38
ADF5355
Data Sheet
Pin No.
Mnemonic
Description
23
VREF
Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the
ground plane as close to this pin as possible.
24
VBIAS
Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.
25, 32
CREG1, CREG
2
Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits. Nominal
voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.
26
27
PDBRF
DVDD
RFOUTA Power-Down. A logic low on this pin powers down the RFOUTA outputs only. This power-down function
is also software controllable. Do not leave this pin floating.
Digital Power Supply. This pin must be at the same voltage as AVDD. Do not connect to VRF. Place decoupling
capacitors to the ground plane as close to this pin as possible.
28
29
30
REFINB
REFINA
MUXOUT
Complementary Reference Input. If unused, ac couple this pin to AGND
Reference Input.
Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or
the scaled reference frequency to be externally accessible.
.
31
SDGND
EPAD
Digital Σ-Δ Modulator Ground. Pin 31 is the ground return path for the Σ-Δ modulator.
Exposed Pad. The exposed pad must be connected to AGND
.
Rev. D | Page 10 of 38
Data Sheet
ADF5355
TYPICAL PERFORMANCE CHARACTERISTICS
–50
–70
–50
–70
–90
–90
–110
–130
–150
–170
–110
–130
–150
–170
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 4. Open-Loop VCO Phase Noise, 3.4 GHz
Figure 7. Open-Loop VCO Phase Noise, 8.0 GHz
–50
–70
–50
–70
–90
–90
–110
–130
–150
–170
–110
–130
–150
–170
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 8. Open-Loop VCO Phase Noise, 10.0 GHz
Figure 5. Open-Loop VCO Phase Noise, 5.0 GHz
–50
–70
–50
–70
–90
–90
–110
–130
–150
–170
–110
–130
–150
–170
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 9. Open-Loop VCO Phase Noise, 13.6 GHz
Figure 6. Open-Loop VCO Phase Noise, 6.8 GHz
Rev. D | Page 11 of 38
ADF5355
Data Sheet
–50
–70
–50
÷1
÷2
÷1
÷2
÷4
÷8
–70
÷16
÷32
÷64
–90
–90
–110
–130
–150
–170
–110
–130
–150
–170
1k
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 10. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Dividers, VCO = 3.4 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 20 kHz
Figure 13. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 3.4 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 2 kHz
–50
–50
÷1
÷1
÷2
÷2
÷4
–70
–90
÷8
–70
÷16
÷32
÷64
–90
–110
–130
–150
–170
–110
–130
–150
–170
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 11. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Dividers, VCO = 5.0 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 20 kHz
Figure 14. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 5.0 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 2 kHz
–50
–50
÷1
÷1
÷2
÷2
÷4
–70
–90
÷8
–70
÷16
÷32
÷64
–90
–110
–130
–150
–170
–110
–130
–150
–170
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 12. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Dividers, VCO = 6.8 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 20 kHz
Figure 15. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and
Divide by 2, VCO = 6.8 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 2 kHz
Rev. D | Page 12 of 38
Data Sheet
ADF5355
10
9
8
–50
–40°C
+25°C
+85°C
7
–70
6
5
4
3
2
–90
1
0
–110
–130
–150
–170
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
1
2
3
4
5
6
7
1k
10k
100k
1M
10M
100M
FREQUENCY (GHz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 19. Output Power vs. Frequency, RFOUTA+/RFOUTA− (7.5 nH Inductors,
10 pF Bypass Capacitors, Board Losses De-Embedded)
Figure 16. Closed-Loop Phase Noise, RFOUTB = 6.8 GHz, 2× VCO,
VCO = 3.4 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 2 kHz
0
–50
SECOND HARMONIC (RF
A × 2)
OUT
THIRD HARMONIC (RF
A × 3)
OUT
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–70
–90
–110
–130
–150
–170
1
2
3
4
5
6
7
1k
10k
100k
1M
10M
100M
RF
A FREQUENCY (GHz)
FREQUENCY OFFSET FROM CARRIER (Hz)
OUT
Figure 20. RFOUTA+/RFOUTA− Harmonics vs. Frequency (7.5 nH Inductors,
10 pF Bypass Capacitors, Board Losses De-Embedded)
Figure 17. Closed-Loop Phase Noise, RFOUTB = 10 GHz, 2× VCO,
VCO = 5.0 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 2 kHz
10
8
–50
–70
–90
6
4
2
0
–110
–130
–150
–170
–2
–4
–6
–8
–10
0
1
2
3
4
5
6
7
1k
10k
100k
1M
10M
100M
FREQUENCY (GHz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 21. RFOUTA+/RFOUTA− Power vs. Frequency (100 nH Inductors,
100 pF Bypass Capacitors, Board Measurement)
Figure 18. Closed-Loop Phase Noise, RFOUTB = 13.6 GHz, 2× VCO,
VCO = 6.8 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 2 kHz
Rev. D | Page 13 of 38
ADF5355
Data Sheet
10
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–40°C
RMS JITTER (ps) 1kHz TO 20MHz
RMS JITTER (ps) 12kHz TO 20MHz
+25°C
+85°C
8
6
4
2
0
–2
–4
–6
–8
–10
6.7
7.7
8.7
9.7
10.7
11.7
12.7
13.7
0.8
1.8
2.8
3.8
4.8
5.8
6.8
FREQUENCY (GHz)
OUTPUT FREQUENCY (GHz)
Figure 22. Output Power vs. Frequency, RFOUTB (10 pF Bypass Capacitor
De-Embedded)
Figure 25. RMS Jitter vs. Output Frequency, fPFD = 61.44 MHz, Loop Filter = 20 kHz
0
–50
–40°C
PFD = 15.36MHz
PFD = 30.72MHz
PFD = 61.44MHz
–60
–1
+25°C
+85°C
–2
–3
–4
–5
–70
–80
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–90
–100
–110
3.4
3.9
4.4
4.9
5.4
5.9
6.4
6.9
0
1
2
3
4
5
6
7
FREQUENCY (GHz)
RF
A+/RF
A– OUTPUT FREQUENCY(GHz)
OUT
OUT
Figure 26. PFD Spur Amplitude vs. RFOUTA+/RFOUTA− Output Frequency;
PFD = 61.44 MHz, fPFD = 30.72 MHz, and fPFD = 15.36 MHz; Loop Filter = 20 kHz
Figure 23. VCO Feedthrough at RFOUTB (De-Embedded) vs. Fundamental VCO
Frequency
f
–70
–80
0
–10
–20
–30
–40
–50
–60
–90
–100
–110
–120
–130
–140
–150
–160
–170
1k
10k
100k
1M
10M
100M
5
10
15
20
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY (GHz)
Figure 24. Wideband Spectrum, RFOUTB, VCO = 6.8 GHz, RFOUTB Enabled,
RFOUTA+/RFOUTA− Disabled (Board Measurement)
Figure 27. Fractional-N Spur Performance, GSM1800 Band, RFOUTA+ =
1550.2 MHz, REFIN = 122.88 MHz, fPFD = 61.44 MHz, Output Divide by 4
Selected, Loop Filter Bandwidth = 2 kHz, Channel Spacing = 20 kHz
Rev. D | Page 14 of 38
Data Sheet
ADF5355
–70
–80
–70
–80
–90
–90
–100
–110
–120
–130
–140
–150
–160
–170
–100
–110
–120
–130
–140
–150
–160
–170
1k
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 28. Fractional-N Spur Performance, W-CDMA Band,
RFOUTA+ = 2113.5 MHz, REFIN = 122.88 MHz, fPFD = 61.44 MHz,
Output Divide by 2 Selected, Loop Filter Bandwidth = 2 kHz,
Channel Spacing = 20 kHz
Figure 30. Fractional-N Spur Performance, RFOUTA+ = 5.8 GHz,
REFIN = 122.88 MHz, fPFD = 61.44 MHz, Output Divide by 2 Selected,
Loop Filter Bandwidth = 2 kHz, Channel Spacing = 20 kHz
–70
4.65
4.60
–80
–90
4.55
4.50
4.45
–100
–110
–120
–130
–140
–150
–160
–170
1
4.40
4.35
4.30
4.25
4.20
4.15
1k
10k
100k
1M
10M
100M
–1
0
1
2
3
4
TIME (ms)
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 31. Lock Time for 250 MHz Jump from 4150 MHz to 4400 MHz,
Loop Bandwidth = 20 kHz
Figure 29. Fractional-N Spur Performance, RFOUTA+ = 2.591 GHz,
REFIN = 122.88 MHz, fPFD = 61.44 MHz, Output Divide by 2 Selected,
Loop Filter Bandwidth = 2 kHz, Channel Spacing = 20 kHz
Rev. D | Page 15 of 38
ADF5355
Data Sheet
CIRCUIT DESCRIPTION
INT, FRAC, MOD, and R Counter Relationship
REFERENCE INPUT
The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in
conjunction with the R counter, make it possible to generate
output frequencies that are spaced by fractions of the PFD
frequency (fPFD). For more information, see the RF Synthesizer—
A Worked Example section.
Figure 32 shows the reference input stage. The reference input
can accept both single-ended and differential signals. Use the
reference mode bit (Register 4, DB9) to select the signal. To use a
differential signal on the reference input, program this bit high.
In this case, SW1 and SW2 are open, SW3 and SW4 are closed,
and the current source that drives the differential pair of
transistors switches on (see Figure 32). The differential signal is
buffered, and it is provided to an emitter coupled logic (ECL) to
CMOS converter. When a single-ended signal is used as the
reference, connect the reference signal to REFINA and program
Bit DB9 in Register 4 to 0. In this case, SW1 and SW2 are
closed, SW3 and SW4 are open, and the current source that
drives the differential pair of transistors switches off. Single-
ended mode results in lower integer boundary spurs.
Calculate the VCO output frequency (VCOOUT) by
VCOOUT = fPFD × N
(1)
where:
VCOOUT is the output frequency of the external VCO voltage
controlled oscillator (without using the output divider).
fPFD is the frequency of the phase frequency detector.
N is the desired value of the feedback counter, N.
Calculate fPFD by
REFERENCE
INPUT MODE
fPFD = REFIN × [(1 + D)/(R × (1 + T))]
(2)
where:
85kΩ
REFIN is the reference input frequency.
D is the REFIN doubler bit.
SW2
BUFFER
SW1
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
SW3
TO
R COUNTER
MULTIPLEXER
T is the REFIN divide by 2 bit (0 or 1)
AV
DD
N comprises
ECL TO CMOS
BUFFER
FRAC2
MOD2
MOD1
FRAC1+
REF
REF
A
N = INT +
(3)
IN
where:
B
IN
INT is the 16-bit integer value (23 to 32,767 for 4/5 prescaler,
75 to 65,535 for 8/9 prescaler).
FRAC1 is the numerator of the primary modulus (0 to 16,777,215).
FRAC2 is the numerator of the 14-bit auxiliary modulus
(0 to 16,383).
2.5kΩ
2.5kΩ
SW4
BIAS
GENERATOR
Figure 32. Reference Input Stage
MOD2 is the programmable, 14-bit auxiliary fractional
modulus (2 to 16,383).
RF N DIVIDER
MOD1 is a 24-bit primary modulus with a fixed value of 224
=
The RF N divider allows a division ratio in the PLL feedback
path. Determine the division ratio by the INT, FRAC1, FRAC2,
and MOD2 values that this divider comprises.
16,777,216.
This calculation results in a very fine frequency resolution with
no residual frequency error. To apply this formula, take the
following steps:
FRAC2
MOD2
RF N COUNTER
N = INT +
FRAC1 +
MOD1
1. Calculate N by dividing VCOOUT/fPFD
.
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
TO PFD
N COUNTER
2. The integer value of this number forms INT.
3. Subtract this value from the full N value.
4. Multiply the remainder by 224.
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
5. The integer value of this number forms FRAC1.
6. Calculate MOD2 based on the channel spacing (fCHSP) by
INT
REG
FRAC1
REG
FRAC2
VALUE
MOD2
VALUE
MOD2 = fPFD/GCD(fPFD, fCHSP
where:
CHSP is the desired channel spacing frequency.
)
(4)
f
Figure 33. RF N Divider
GCD(fPFD, fCHSP) is the greatest common divisor of the PFD
frequency and the channel spacing frequency.
Rev. D | Page 16 of 38
Data Sheet
ADF5355
7. Calculate FRAC2 by the following equation:
MUXOUT AND LOCK DETECT
FRAC2 = [(N − INT) × 224 − FRAC1)] × MOD2
(5)
(6)
The output multiplexer on the ADF5355 allows the user to access
various internal points on the chip. The M3, M2, and M1 bits in
Register 4 control the state of MUXOUT. Figure 35 shows the
MUXOUT section in block diagram form.
The FRAC2 and MOD2 fraction result in outputs with zero
frequency error for channel spacings when
fPFD/GCD(fPFD, fCHSP) = MOD2 < 16,383
DV
DD
where:
f
PFD is the frequency of the phase frequency detector.
CHSP is the desired channel spacing.
THREE-STATE OUTPUT
DV
f
DD
GCD is a greatest common divisor function.
DGND
If zero frequency error is not required, the MOD1 and MOD2
denominators operate together to create a 38-bit resolution
modulus.
R DIVIDER OUTPUT
N DIVIDER OUTPUT
MUX
CONTROL
MUXOUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
RESERVED
INT N Mode
When FRAC1 and FRAC2 are 0, the synthesizer operates in
integer-N mode.
DGND
R Counter
Figure 35. MUXOUT Schematic
The 10-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 1023 are allowed.
INPUT SHIFT REGISTERS
The ADF5355 digital section includes a 10-bit R counter, a
16-bit RF integer-N counter, a 24-bit FRAC1 counter, a 14-bit
auxiliary fractional counter, and a 14-bit auxiliary modulus
counter. Data clocks into the 32-bit shift register on each rising
edge of CLK. The data clocks in MSB first. Data transfers from
the shift register to one of 13 latches on the rising edge of LE.
The state of the four control bits (C4, C3, C2, and C1) in the
shift register determines the destination latch. As shown in
Figure 2, the four LSBs are DB3, DB2, DB1, and DB0. The truth
table for these bits is shown in Table 5. Figure 39 and Figure 40
summarize the programming of the latches.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 34 is a simplified schematic of
the phase frequency detector. The PFD includes a fixed delay
element (INT = 1.6 ns, FRAC = 2.6 ns) that sets the width of the
anti-backlash pulse. This pulse ensures that there is no dead
zone in the PFD transfer function and provides a consistent
reference spur level. Set the phase detector polarity to positive
on this device because of the positive tuning of the VCO.
Table 5. Truth Table for the C4, C3, C2, and C1 Control Bits
Control Bits
UP
HIGH
D1
Q1
C4
0
0
0
0
0
0
0
0
1
1
1
1
1
C3
0
0
0
0
1
1
1
1
0
0
0
0
1
C2
0
0
1
1
0
0
1
1
0
0
1
1
0
C1
0
1
0
1
0
1
0
1
0
1
0
1
0
Register
U1
CLR1
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
+IN
CHARGE
PUMP
CP
U3
DELAY
DOWN
CLR2
D2 Q2
HIGH
U2
–IN
Figure 34. PFD Simplified Schematic
Rev. D | Page 17 of 38
ADF5355
Data Sheet
50
45
40
35
30
25
20
15
10
5
PROGRAM MODES
Table 5 and Figure 39 through Figure 53 show how the program
modes must be set up in the ADF5355.
The following settings in the ADF5355 are double buffered: main
fractional value (FRAC1), auxiliary modulus value (MOD2),
auxiliary fractional value (FRAC2), reference doubler, reference
divide by 2 (RDIV2), R counter value, and charge pump current
setting. Two events must occur before the ADF5355 uses a new
value for any of the double buffered settings. First, the new value
must latch into the device by writing to the appropriate register,
and second, a new write to Register 0 must be performed.
LINEAR
TREND LINE
AVERAGE
VCO SENSITIVITY
0
3.3
3.8
4.3
4.8
5.3
5.8
6.3
6.8
For example, to ensure that the modulus value loads correctly,
every time that the modulus value updates, Register 0 must be
written to. The RF divider select in Register 6 is also double
buffered, but only if DB14 of Register 4 is high.
FREQUENCY (GHz)
Figure 36. VCO Sensitivity, KV vs. Frequency
OUTPUT STAGE
VCO
The RFOUTA+ and RFOUTA− pins of the ADF5355 connect to
the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 37. In this scheme,
the ADF5355 contains internal 50 Ω resistors connected to
the VRF pin. To optimize the power dissipation vs. the output
power requirements, the tail current of the differential pair is
programmable using Bits[D2:D1] in Register 6. Four current
levels can be set. These levels give approximate output power
levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively.
Levels of −4 dBm, −1 dBm, +2 dBm can be achieved using a
50 Ω resistor to VRF and ac coupling into a 50 Ω load. A +5 dBm
level requires an external shunt inductor to VRF. Note that an
inductor has a narrower operating frequency than a 50 Ω
resistor. For accurate power levels, refer to the Typical
The VCO core in the ADF5355 consists of four separate VCOs,
each of which uses 256 overlapping bands, which allows the
device to cover a wide frequency range without large VCO
sensitivity (KV) and without resultant poor phase noise and
spurious performance.
The correct VCO and band are chosen automatically by the
VCO and band select logic whenever Register 0 is updated and
automatic calibration is enabled. The VCO VTUNE is disconnected
from the output of the loop filter and is connected to an internal
reference voltage.
The R counter output is used as the clock for the band select
logic. After band selection, normal PLL action resumes. The
nominal value of KV is 15 MHz/V when the N divider is driven
from the VCO output, or the KV value is divided by D. D is
the output divider value if the N divider is driven from the
RF output divider (chosen by programming Bits[D23:D21] in
Register 6).
Performance Characteristics section. Add an external shunt
inductor to provide higher power levels; however, this is less
wideband than the internal bias only. Terminate the unused
complementary output with a circuit similar to the used output.
V
V
RF
RF
The VCO shows variation of KV as the tuning voltage, VTUNE
,
50Ω
A+
50Ω
RF
RF
A–
varies within the band and from band to band. For wideband
applications covering a wide frequency range (and changing
output dividers), a value of 15 MHz/V provides the most accurate
KV, because this value is closest to the average value. Figure 36
shows how KV varies with fundamental VCO frequency along with
an average value for the frequency band. Users may prefer this
figure when using narrow-band designs.
OUT
OUT
BUFFER/
DIVIDE BY
1/2/4/8/
VCO
16/32/64
Figure 37. Output Stage
The doubled VCO output (6.8 GHz to 13.6 GHz) is available on
the RFOUTB pin, which can be ac-coupled to the next circuit.
2× VCO
MUX
RF
B
OUT
Figure 38. Output Stage
Rev. D | Page 18 of 38
Data Sheet
ADF5355
Another feature of the ADF5355 is that the supply current to
the RFOUTA+/RFOUTA− output stage can shut down until the
ADF5355 achieves lock as measured by the digital lock detect
circuitry. The mute till lock detect (MTLD) bit (Bit DB11) in
Register 6 enables this function.
RFOUTB directly connects to the VCO, and it can be muted but
only by using the RFOUTB bit (Bit DB10) in Register 6.
Table 6. Total IDD (RFOUTA Refers to RFOUTA+/RFOUTA−)
Divide By
RFOUTA
Off
RFOUTA
= −4 dBm
RFOUTA
= −1 dBm
RFOUTA
= +2 dBm
RFOUTA = +5 dBm
5.0 V Supply (IVCO and IP)
78 mA
78 mA
78 mA
78 mA
78 mA
3.3 V Supply (AIDD, DIDD, IRF)1
1
2
4
8
16
32
64
79.8 mA
87.8 mA
97.1 mA
104.9 mA
109.8 mA
113.6 mA
115.9 mA
101.3 mA
110.1 mA
119.3 mA
127.1 mA
131.8 mA
135.5 mA
137.8 mA
111.9 mA
120.6 mA
130.1 mA
137.8 mA
142.7 mA
146.5 mA
148.9 mA
122.7 mA
131.9 mA
141.6 mA
149.2 mA
154.1 mA
157.8 mA
160.1 mA
132.8 mA
141.9 mA
152.1 mA
159.7 mA
164.6 mA
168.4 mA
170.8 mA
1 For DIDD + AIDD (nominal 62 mA): DIDD = 15 mA (typical), AIDD (Pin 5) = 24 mA (typical), AIDD (Pin 16) = 23 mA (typical).
Rev. D | Page 19 of 38
ADF5355
Data Sheet
REGISTER MAPS
REGISTER 0
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2
DB1
DB0
N15 N14 N13 N12 N11 N10
N9
N8
N7
N6
N5
N4
N3
N2
N1 C4(0) C3(0) C2(0) C1(0)
0
0
0
0
0
0
0
0
0
0
AC1
PR1
N16
REGISTER 1
CONTROL
BITS
1
RESERVED
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
F24
F23
F22
F21
F20
F19
F18
F17
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
0
0
0
C3(0) C2(0) C1(1)
C4(0)
0
REGISTER 2
CONTROL
BITS
1
1
DBR
14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2)
DBR
14-BIT AUXILIARY MODULUS VALUE (MOD2)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M14 M13 M12 M11 M10 M9
M8
M7
M6
M5
M4
M3
M2
M1
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
C3(0) C2(1) C1(0)
C4(0)
REGISTER 3
CONTROL
BITS
1
24-BIT PHASE VALUE (PHASE)
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3(0) C2(1) C1(1)
P1 C4(0)
0
SD1
PR1 PA1 P24
P23 P22
P21
P20
P19
P18
P17
P16 P15
P14 P13
P12
P11 P10
P9
P8
P7
P6
P5
P4
P3
P2
REGISTER 4
CONTROL
BITS
CURRENT
SETTING
1
DBR
1
RESERVED
MUXOUT
10-BIT R COUNTER
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3(1) C2(0) C1(0)
U1 C4(0)
0
0
M3
M2
M1
RD2 RD1
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D1
CP4
CP3 CP2 CP1 U6
U5
U4
U3
U2
REGISTER 5
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
C4(0) C3(1) C2(0)
C1(1)
REGISTER 6
RF
OUTPUT
POWER
RF
DIVIDER SELECT
CONTROL
BITS
2
RESERVED
CHARGE PUMP BLEED CURRENT
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
BL10 BL9 D2 D1 C4(0) C3(1) C2(1) C1(0)
0
1
0
1
0
D13
D12
D11
D10 BL8 BL7 BL6 BL5 BL4 BL3 BL2 BL1
0
D8
D7
0
0
0
D3
1
2
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
DBB = DOUBLE BUFFERED BITS—BUFFERED BY A WRITE TO REGISTER 0 WHEN BIT DB14 OF REGISTER 4 IS HIGH.
Figure 39. Register Summary (Register 0 to Register 6)
Rev. D | Page 20 of 38
Data Sheet
ADF5355
REGISTER 7
LD
CYCLE
COUNT
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LD4
LD3 LD2 LD1 C4(0) C3(1) C2(1) C1(1)
0
0
0
1
0
0
LE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LD5
LOL
REGISTER 8
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
0
1
0
0
0
1
0
0
0
1
0
0
0
C4(1) C3(0) C2(0) C1(0)
REGISTER 9
SYNTHESIZER
LOCK TIMEOUT
CONTROL
BITS
VCO BAND DIVISION
TIMEOUT
AUTOMATIC LEVEL TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VC8 VC7 VC6 VC5 VC4 VC3 VC2 VC1 TL10 TL9 TL8 TL7 TL6 TL5 TL4 TL3 TL2 TL1 AL5 AL4 AL3 AL2 AL1 SL5 SL4 SL3 SL2 SL1 C4(1) C3(0) C2(0) C1(1)
REGISTER 10
ADC
CLOCK DIVIDER
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
AD8 AD7 AD6
AD5 AD4 AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)
REGISTER 11
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
C4(1) C3(0) C2(1) C1(1)
0
REGISTER 12
CONTROL
BITS
RESERVED
RESYNC CLOCK
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P13 P12
P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1
0
0
0
0
0
1
0
0
0
0
0
1
P16 P15
C4(1) C3(1) C2(0) C1(0)
P14
Figure 40. Register Summary (Register 7 to Register 12)
Rev. D | Page 21 of 38
ADF5355
Data Sheet
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22
DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
N15 N14 N13 N12 N11 N10
N9
N8
N7
N6
N5
N4
N3
N2
N1 C4(0) C3(0) C2(0) C1(0)
0
0
0
0
0
0
0
0
0
0
AC1
PR1
N16
N16
0
N15
0
...
...
...
...
...
...
...
...
...
...
...
...
N5
N4
N3
N2
N1
0
1
0
.
INTEGER VALUE (INT)
PR1 PRESCALER
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
NOT ALLOWED
0
1
4/5
8/9
0
0
NOT ALLOWED
0
0
NOT ALLOWED
.
.
...
0
0
1
1
1
.
0
0
1
.
1
1
0
.
1
1
0
.
0
1
0
.
NOT ALLOWED
0
0
23
0
0
24
VCO
AUTOCAL
AC1
.
.
...
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
65533
65534
65535
0
1
DISABLED
ENABLED
1
1
1
1
INT
= 75 WITH PRESCALER = 8/9
MIN
Figure 41. Register 0
Prescaler Value
REGISTER 0
The dual modulus prescaler (P/P + 1), along with the INT,
FRACx, and MODx counters, determines the overall division
ratio from the VCO output to the PFD input. The PR1 bit
(Bit DB20) in Register 0 sets the prescaler value.
Control Bits
With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 41
shows the input data format for programming this register.
Reserved
Operating at CML levels, the prescaler takes the clock from the
VCO output and divides it down for the counters. It is based on
a synchronous 4/5 core. When the prescaler is set to 4/5, the
maximum RF frequency allowed is 7 GHz. The prescaler limits
the INT value; therefore, if P is 4/5, NMIN is 23, and if P is 8/9,
Bits[DB31:DB22] are reserved and must be set to 0.
Automatic Calibration (AUTOCAL)
Write to Register 0 to enact (by default) the VCO automatic
calibration, and to choose the appropriate VCO and VCO
subband. Write 1 to the AC1 bit (Bit DB21) to enable the
automatic calibration, which is the recommended mode of
operation.
N
MIN is 75.
16-Bit Integer Value
The 16 INT bits (Bits[DB19:DB4]) set the INT value, which
determines the integer part of the feedback division factor. The
INT value is used in Equation 3 (see the INT, FRAC, MOD, and
R Counter Relationship section). All integer values from 23 to
32,767 are allowed for the 4/5 prescaler. For the 8/9 prescaler,
the minimum integer value is 75, and the maximum value is
65,535.
Set the AC1 bit (Bit DB21) to 0 to disable the automatic
calibration, which leaves the ADF5355 in the same band it was
already in when Register 0 is updated.
Disable the automatic calibration only for fixed frequency
applications, phase adjust applications, or very small (<10 kHz)
frequency jumps.
Toggling automatic calibration (AUTOCAL) is also required
when changing frequency. See the Frequency Update Sequence
section for more information.
Rev. D | Page 22 of 38
Data Sheet
ADF5355
CONTROL
BITS
1
RESERVED
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1
0
0
0
C3(0) C2(0) C1(1)
C4(0)
0
F24
F23
.......... F2
F1
MAIN FRACTIONAL VALUE (FRAC1)
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
0
0
1
1
.
0
1
0
1
.
0
1
2
3
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16777212
16777213
16777214
16777215
1
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 42. Register 1
24-Bit Main Fractional Value
REGISTER 1
The 24 FRAC1 bits (Bits[DB27:DB4]) set the numerator of the
fraction that is input to the Σ-Δ modulator. This fraction, along
with the INT value, specifies the new frequency channel that
the synthesizer locks to, as shown in the RF Synthesizer—A
Worked Example section. FRAC1 values from 0 to (MOD1 − 1)
cover channels over a frequency range equal to the PFD
reference frequency.
Control Bits
With Bits[C4:C1] set to 0001, Register 1 is programmed. Figure 42
shows the input data format for programming this register.
Reserved
Bits[DB31:DB28] are reserved and must be set to 0.
Rev. D | Page 23 of 38
ADF5355
Data Sheet
CONTROL
BITS
1
1
14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2) DBR
14-BIT AUXILIARY MODULUS VALUE (MOD2) DBR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M14 M13 M12 M11 M10 M9
M8
M7
M6
M5
M4
M3
M2
M1
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
C3(0) C2(1) C1(0)
C4(0)
M14 M13 .......... M2
M1
0
1
0
1
.
MODULUS VALUE (MOD2)
F14
F13
.......... F2
F1
0
1
0
1
.
FRAC2 WORD
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
0
0
1
1
.
NOT ALLOWED
0
0
0
0
.
0
0
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
0
0
1
1
.
0
NOT ALLOWED
1
2
2
3
3
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16380
16381
16382
16383
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16381
16382
16382
16383
1
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 43. Register 2
14-Bit Auxiliary Modulus Value (MOD2)
REGISTER 2
The 14-bit auxiliary modulus value (Bits[DB17:DB4]) sets the
auxiliary fractional modulus. Use MOD2 to correct any residual
error due to the main fractional modulus.
Control Bits
With Bits[C4:C1] set to 0010, Register 2 is programmed. Figure 43
shows the input data format for programming this register.
14-Bit Auxiliary Fractional Value (FRAC2)
The 14-bit auxiliary fractional value (Bits[DB31:DB18]) controls
the auxiliary fractional word. FRAC2 must be less than the
MOD2 value programmed in Register 2.
Rev. D | Page 24 of 38
Data Sheet
ADF5355
CONTROL
BITS
24-BIT PHASE VALUE (PHASE)
DBR1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3(0) C2(1) C1(1)
0
SD1
PR1 PA1 P24
P23 P22
P21
P20
P19
P18
P17
P16 P15
P14 P13
P12
P11 P10
P9
P8
P7
P6
P5
P4
P3
P2
P1 C4(0)
PHASE
ADJUST
PA1
P24
P23
0
0
0
0
.
.......... P2
P1
PHASE VALUE (PHASE)
0
1
DISABLED
ENABLED
0
0
0
0
.
..........
0
0
1
1
.
0
1
0
1
.
0
..........
..........
..........
..........
..........
..........
..........
..........
..........
.........
1
2
3
PHASE
PR1
.
RESYNC
.
.
.
.
.
0
1
DISABLED
ENABLED
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
16777212
16777213
16777214
16777215
SD LOAD
RESET
SD1
0
1
ON REGISTER0 UPDATE
DISABLED
1
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 44. Register 3
This is achieved by programming the D13 bit (Bit DB24) in
Register 6 to 0, which ensures divided feedback to the N divider.
REGISTER 3
Control Bits
Phase resynchronization operates only when FRAC2 = 0.
With Bits[C4:C1] set to 0011, Register 3 is programmed. Figure 44
shows the input data format for programming this register.
For resync applications, enable the SD load reset in Register 3
by setting DB30 to 0.
Reserved
Phase Adjust
Bit DB31 is reserved and must be set to 0.
SD Load Reset
To adjust the relative output phase of the ADF5355 on each
Register 0 update, set the PA1 bit (Bit DB28) to 1. This feature
differs from the resynchronization feature in that it is useful
when adjustments to phase are made continually in an
application. For this function, disable the VCO automatic
calibration by setting the AC1 bit (Bit DB21) in Register 0 to 0,
and disable the SD load reset by setting the SD1 bit (Bit DB30)
in Register 3 to 1. Note that phase resync and phase adjust
cannot be used simultaneously.
When writing to Register 0, the Σ-Δ modulator resets. For
applications in which the phase is continually adjusted, this may
not be desirable; therefore, in these cases, the Σ-Δ reset can be
disabled by writing a 1 to the SD1 bit (Bit DB30).
Phase Resync
To use the phase resynchronization feature, the PR1 bit (Bit DB29)
must be set to 1. If unused, the bit can be programmed to 0. The
phase resync timer must also be used in Register 12 to ensure
that the resynchronization feature is applied after PLL has settled to
the final frequency. If the PLL has not settled to the final frequency,
phase resync may not function correctly. Resynchronization is
useful in phased array and beam forming applications. It ensures
repeatability of output phase when programming the same
frequency. In phase critical applications that use frequencies
requiring the output divider (<3400 MHz), it is necessary to
feed the N divider with the divided VCO frequency as distinct
from the fundamental VCO frequency.
24-Bit Phase Value
The phase of the RF output frequency can adjust in 24-bit steps,
from 0° (0) to 360° (224 − 1). For phase adjust applications, the
phase is set by
(Phase Value/16,777,216) × 360°
When the phase value is programmed to Register 3, each
subsequent adjustment of Register 0 increments the phase by
the value in this equation.
Rev. D | Page 25 of 38
ADF5355
Data Sheet
CURRENT
SETTING
CONTROL
BITS
1
1
DBR
MUXOUT
10-BIT R COUNTER
DBR
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1
DB0
0
0
M3
M2
M1 RD2 RD1 R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
D1
CP4 CP3 CP2 CP1 U6
U5
U4
U3
U2
U1
C3(1) C2(0) C1(0)
C4(0)
REFERENCE
RD2
COUNTER
RESET
DOUBLE BUFFERED
REGISTER 6, BITS[DB23:DB21]
U1
DOUBLER
D1
U6
0
REFIN
SINGLE
DIFF
0
1
DISABLED
ENABLED
0
1
DISABLED
ENABLED
0
1
DISABLED
1
ENABLED
RD1 REFERENCE DIVIDE BY 2
CP
I
(mA)
CP
U2
U5
LDP
1.8V
3.3V
THREE-STATE
CP4
CP3
CP2
CP1
5.1kΩ
0
1
DISABLED
ENABLED
0
1
0
1
DISABLED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.31
0.63
0.94
1.25
1.56
1.88
2.19
2.50
2.81
3.13
3.44
3.75
4.06
4.38
4.69
5.00
ENABLED
R10
R9
..........
R2
R1
R DIVIDER (R)
U4
0
PD POLARITY
NEGATIVE
POSITIVE
U3
POWER DOWN
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
0
1
DISABLED
ENABLED
2
1
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1020
1021
1022
1023
M3
0
M2
0
M1
0
OUTPUT
THREE-STATE OUTPUT
0
0
1
DV
DD
0
1
0
DGND
0
1
1
R DIVIDER OUTPUT
N DIVIDER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
RESERVED
1
0
0
1
0
1
1
1
0
1
1
1
1
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
Figure 45. Register 4
The maximum allowable reference frequency when the doubler
is enabled is 100 MHz.
REGISTER 4
Control Bits
RDIV2
With Bits[C4:C1] set to 0100, Register 4 is programmed. Figure 45
shows the input data format for programming this register.
Setting the RDIV2 bit (Bit DB25) to 1 inserts a divide by 2,
toggle flip-flop between the R counter and PFD, which extends
the maximum reference frequency input rate. This function
provides a 50% duty cycle signal at the PFD input.
Reserved
Bits[DB31:DB30] are reserved and must be set to 0.
MUXOUT
10-Bit R Counter
The on-chip multiplexer (MUXOUT) is controlled by
Bits[DB29:DB27]. For additional details, see Figure 45.
The 10-bit R counter divides the input reference frequency
(REFIN) to produce the reference clock to the PFD. Division
ratios range from 1 to 1023.
When changing frequency, that is, writing Register 0, MUXOUT
must not be set to N divider output or R divider output. If needed,
enable these functions after locking to the new frequency.
Double Buffer
The D1 bit (Bit DB14) enables or disables double buffering of
the RF divider select bits (Bits[DB23:DB21]) in Register 6. The
Program Modes section explains how double buffering works.
Reference Doubler
Setting the RD2 bit (Bit DB26) to 0 feeds the reference frequency
signal directly to the 10-bit R counter, disabling the doubler.
Setting this bit to 1 multiplies the reference frequency by a factor
of 2 before feeding it into the 10-bit R counter. When the doubler
is disabled, the REFIN falling edge is the active edge at the PFD
input to the fractional synthesizer. When the doubler is enabled,
both the rising and falling edges of the reference frequency become
active edges at the PFD input.
Charge Pump Current Setting
The CP4 to CP1 bits (Bits[DB13:DB10]) set the charge pump
current. Set this value to the charge pump current that the loop
filter is designed with (see Figure 45). For the lowest spurs, the
0.9 mA setting is recommended.
Rev. D | Page 26 of 38
Data Sheet
ADF5355
Reference Mode
When power-down activates, the following events occur:
The ADF5355 permits use of either differential or single-ended
reference sources.
•
The synthesizer counters are forced to their load state
conditions.
•
•
•
•
The VCO powers down.
For optimum integer boundary spur performance, it is
recommended to use the single-ended setting for all references
up to 250 MHz (even if using a differential reference signal). Use
the differential setting for reference frequencies above 250 MHz.
The charge pump is forced into three-state mode.
The digital lock detect circuitry resets.
The RFOUTA+/RFOUTA− and RFOUTB output stages are
disabled.
The input registers remain active and capable of loading
and latching data.
Level Select
•
To assist with logic compatibility, MUXOUT is programmable to
two logic levels. Set the U5 bit (Bit DB8) to 0 to select 1.8 V
logic, and set it to 1 to select 3.3 V logic.
Charge Pump Three-State
Setting the U2 bit (Bit DB5) to 1 puts the charge pump into
three-state mode. Set DB5 to 0 for normal operation.
Phase Detector Polarity
The U4 bit (Bit DB7) sets the phase detector polarity. When a
passive loop filter or a noninverting active loop filter is used, set
DB7 to 1 (positive). If an active filter with an inverting
characteristic is used, set this bit to 0 (negative).
Counter Reset
The U1 bit (Bit DB4) resets the R counter, N counter, and VCO
band select of the ADF5355. When DB4 is set to 1, the RF
synthesizer N counter, R counter, and VCO band select are reset.
For normal operation, set DB4 to 0.
Power-Down
The U3 bit (Bit DB6) sets the programmable power-down mode.
Setting DB6 to 1 performs a power-down. Setting DB6 to 0 returns
the synthesizer to normal operation. In software or hardware
power-down mode, the ADF5355 retains all information in its
registers. The register contents are only lost if the supply voltages
are removed.
Toggling counter reset is also required when changing frequency.
See the Frequency Update Sequence section for more information.
REGISTER 5
The bits in Register 5 are reserved and must be programmed as
described in Figure 46, using a hexadecimal word of 0x00800025.
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C4(0) C3(1) C2(0)
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
C1(1)
Figure 46. Register 5 (0x00800025)
Rev. D | Page 27 of 38
ADF5355
Data Sheet
RF
OUTPUT
POWER
RF DIVIDER
CONTROL
BITS
1
RESERVED
SELECT
CHARGE PUMP BLEED CURRENT
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
BL10 BL9
1
0
1
0
D2
D1 C4(0) C3(1) C2(1) C1(0)
D13 D12 D11 D10 BL8 BL7 BL6 BL5 BL4 BL3 BL2 BL1
0
D8
D7
0
0
0
D3
FEEDBACK
SELECT
D13
D2
D1
0
OUTPUT POWER
–4dBm
0
0
1
1
0
1
DIVIDED
1
–1dBm
FUNDAMENTAL
0
+2dBm
1
+5dBm
NEGATIVE BLEED
BL9
D12
D11
D10 RF DIVIDER SELECT
RFOUTA+/RFOUTA–
DISABLED
D3
0
0
1
DISABLED
ENABLED
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
÷1
÷2
MUTE TILL
LOCK DETECT
1
ENABLED
D8
0
÷4
MUTE DISABLED
÷8
GATED BLEED
BL10
1
MUTE ENABLED
÷16
÷32
÷64
0
1
DISABLED
ENABLED
RFOUT
B
D7
0
ON
1
OFF
BL8
BL7
..........
BL2
BL1 BLEED CURRENT
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
2
.
(3.75µA)
(7.5µA)
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
252 (945µA)
253 (948.75µA)
254 (952.5µA)
255 (956.25µA)
1
BITS[DB23:DB21] ARE BUFFERED BY A WRITE TO REGISTER 0 WHEN THE DOUBLE BUFFER BIT, BIT DB14 OF REGISTER 4, IS ENABLED.
Figure 47. Register 6
Do not use negative bleed when operating in integer-N mode,
that is, when FRAC1 = FRAC2 = 0, or when fPFD is greater than
100 MHz.
REGISTER 6
Control Bits
With Bits[C4:C1] set to 0110, Register 6 is programmed. Figure 47
shows the input data format for programming this register.
Reserved
Bit DB28 is reserved and must be set to 1. Bits[DB27:DB25] are
reserved and must be set to 010.
Reserved
Bit DB31 is reserved and must be set to 0.
Gated Bleed
Feedback Select
D13 (Bit DB24) selects the feedback from the output of the
VCO to the N counter. When D13 is set to 1, the signal is taken
directly from the VCO. When this bit is set to 0, the signal is
taken from the output of the output dividers. The dividers
enable coverage of the wide frequency band (3.4 GHz to 6.8 GHz).
When the divider is enabled and the feedback signal is taken
from the output, the RF output signals of two separately
configured PLLs are in phase. Divided feedback is useful in
some applications where the positive interference of signals is
required to increase the power.
Bleed currents can be used for improving phase noise and spurs;
however, due to a potential impact on lock time, the gated bleed
bit, BL10 (Bit DB30), if set to 1, ensures bleed currents are not
switched on until the digital lock detect asserts logic high. Note
that this function requires digital lock detect to be enabled.
Negative Bleed
Use of constant negative bleed is recommended for most
fractional-N applications because it improves the linearity of
the charge pump, leading to lower noise and spurious signals than
leaving it off. To enable negative bleed, write 1 to BL9 (Bit DB29),
and to disable negative bleed, write 0 to BL9 (Bit DB29).
Rev. D | Page 28 of 38
Data Sheet
ADF5355
Divider Select
Mute Till Lock Detect
D12 to D10 (Bits[DB23:DB21]) select the value of the RF output
divider (see Figure 47).
When D8 (Bit DB11) is set to 1, the supply current to the RF
output stage is shut down until the device achieves lock, as
determined by the digital lock detect circuitry.
Charge Pump Bleed Current
RF Output B Enable
BL8 to BL1 (Bits[DB20:DB13]) control the level of the bleed
current added to the charge pump output. This current
optimizes the phase noise and spurious levels from the device.
D7 (Bit DB10) enables or disables the high frequency RF output
(RFOUTB). If DB10 is set to 0, the auxiliary high frequency RF
output is enabled. If DB10 is set to 1, the auxiliary RF output is
disabled.
Tests have shown that the optimal bleed set is the following:
4/N < IBLEED/ICP < 10/N
Reserved
where:
Bits[DB9:DB7] are reserved and must be set to 000.
RF Output A Enable
N is the value of the feedback counter from the VCO to the PFD.
I
BLEED is the value of constant negative bleed applied to the
charge pump, which is set by the contents of Bits[DB20:DB13].
CP is the value of charge pump current setting, Bits[DB13:DB10] of
D3 (Bit DB6) enables or disables the primary RF output
(RFOUTA+/RFOUTA−). If DB6 is set to 0, the primary RF output
is disabled. If DB6 is set to 1, the primary RF output is enabled.
I
Register 4.
Reserved
Output Power
Bit DB12 is reserved and must be set to 0.
D2 and D1 (Bits[DB5:DB4]) set the value of the primary RF
output power level (see Figure 47).
Rev. D | Page 29 of 38
ADF5355
Data Sheet
LD
CYCLE
COUNT
CONTROL
BITS
RESERVED
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
LD4
LD3 LD2 LD1 C4(0) C3(1) C2(1) C1(1)
0
0
0
1
0
0
LE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LD5
LOL
LOCK DETECT MODE
LD1
0
1
FRACTIONAL-N
INTEGER-N (2.9ns)
LD3
0
LD2
0
FRACTIONAL-N LD PRECISION
5.0ns
6.0ns
8.0ns
12.0ns
0
1
1
0
1
1
LE SYNCHRONIZATION
LOSS OF LOCK MODE
LOL
LE
0
1
DISABLED
0
1
DISABLED
ENABLED
LE SYNCED TO REFIN
LD5
0
LD4
LOCK DETECT CYCLE COUNT
0
1
0
1
1024
2048
4096
8192
0
1
1
Figure 48. Register 7
Loss of Lock (LOL) Mode
REGISTER 7
Set the LOL mode bit (Bit DB7) to 1 when the application is a
fixed frequency application in which the reference (REFIN) is
likely to be removed, such as a clocking application. The standard
lock detect circuit assumes that REFIN is always present; however,
this may not be the case with clocking applications. To enable this
functionality, set DB7 to 1. LOL mode does not function reliably
when using differential REFIN mode.
Control Bits
With Bits[C4:C1] set to 0111, Register 7 is programmed. Figure 48
shows the input data format for programming this register.
Reserved
Bits[DB31:DB29] are reserved and must be set to 0. Bit DB28 is
reserved and must be set to 1. Bits[DB27:DB26] are reserved
and must be set to 0.
Fractional-N Lock Detect Precision (LDP)
LE Sync
LD3 and LD2 (Bits[DB6:DB5]) set the precision of the lock detect
circuitry in fractional-N mode. LDP is available at 5 ns, 6 ns, 8 ns,
or 12 ns. If bleed currents are used, use 12 ns.
When set to 1, Bit DB25 ensures that the load enable (LE) edge
is synchronized internally with the rising edge of reference
input frequency. This synchronization prevents the rare event of
reference and RF dividers loading at the same time as a falling edge
of the reference frequency, which can lead to longer lock times.
Lock Detect Mode (LDM)
If LD1 (Bit DB4) is set to 0, each reference cycle is set by
fractional-N lock detect precision as described in the
Fractional-N Lock Detect Count (LDC) section. If DB4 is
set to 1, each reference cycle is 2.9 ns long, which is more
appropriate for integer-N applications.
Reserved
Bits[DB24:DB10] are reserved and must be set to 0.
Fractional-N Lock Detect Count (LDC)
LD5 and LD4 (Bits[DB9:DB8]) set the number of consecutive
cycles counted by the lock detect circuitry before asserting lock
detect high. See Figure 48 for details.
Rev. D | Page 30 of 38
Data Sheet
ADF5355
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
0
1
0
0
0
0
1
0
0
0
1
0
0
0
C4(1) C3(0) C2(0) C1(0)
Figure 49. Register 8 (0x102D0428)
SYNTHESIZER
LOCK TIMEOUT
CONTROL
BITS
VCO BAND DIVISION
TIMEOUT
AUTOMATIC LEVEL TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VC8 VC7 VC6
VC5 VC4 VC3 VC2 VC1 TL10 TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
TL1 AL5 AL4
AL3 AL2 AL1 SL5 SL4 SL3 SL2 SL1 C4(1) C3(0) C2(0) C1(1)
SL5
SL4
..........
SL2
SL1 SLC WAIT
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
TL10
TL9
..........
TL2
TL1 TIMEOUT
2
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
.
2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
28
29
30
31
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
1020
1021
1022
1023
AL5
AL4
..........
AL2
AL1 ALC WAIT
VC8
VC7
..........
VC2
VC1 VCO BAND DIV
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
2
2
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
28
29
30
31
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
252
253
254
255
Figure 50. Register 9
Timeout
REGISTER 8
TL10 to TL1 (Bits[DB23:DB14]) set the timeout value for the
VCO band select.
The bits in this register are reserved and must be programmed as
shown in Figure 49, using a hexadecimal word of 0x102D0428.
Automatic Level Calibration (ALC) Timeout
REGISTER 9
AL5 to AL1 (Bits[DB13:DB9]) set the timer value used for the
automatic level calibration of the VCO. This function combines
the PFD frequency, the timeout variable, and ALC wait variable.
Choose the ALC such that the following equation is always
greater than 50 µs.
For a worked example and more information, see the Lock
Time section.
Control Bits
With Bits[C4:C1] set to 1001, Register 9 is programmed. Figure 50
shows the input data format for programming this register.
ALC Wait > (50 µs × fPFD)/Timeout
VCO Band Division
Synthesizer Lock Timeout
VC8 to VC1 (Bits[DB31:DB24]) set the value of the VCO band
division clock. Determine the value of this clock by
SL5 to SL1 (Bits[DB8:DB4]) set the synthesizer lock timeout
value. This value allows the VTUNE force to settle on the VTUNE
pin. The value must be 20 µs. Calculate the value using the
following equation:
VCO Band Div = Ceiling(fPFD/2,400,000)
Synthesizer Lock Timeout > (20 µs × fPFD)/Timeout
Rev. D | Page 31 of 38
ADF5355
Data Sheet
ADC
CLOCK DIVIDER
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
AE1 ADC
0
1
DISABLED
ENABLED
AE2 ADC CONVERSION
0
1
DISABLED
ENABLED
AD8
AD7
..........
AD2 AD1 ADC CLK DIV
0
0
.
0
0
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
0
1
.
1
0
.
1
2
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
252
253
254
255
Figure 51. Register 10
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
C4(1) C3(0) C2(1) C1(1)
0
Figure 52. Register 11
Choose the value such that
REGISTER 10
Control Bits
ADC_CLK_DIV = Ceiling(((fPFD/100,000) − 2)/4)
With Bits[C4:C1] set to 1010, Register 10 is programmed.
Figure 51 shows the input data format for programming this
register.
where Ceiling() rounds up to the nearest integer.
For example, for fPFD = 61.44 MHz, set ALC_CLK_DIV = 154
so that the ADC clock frequency is 99.417 kHz.
Reserved
If ADC_CLK_DIV is greater than 255, set it to 255.
Bits[DB31:DB14] are reserved. Bits[DB23:DB22] must be set to
11, and all other bits in this range must be set to 0.
ADC Conversion Enable
AE2 (Bit DB5) ensures that the ADC performs a conversion
when a write to Register 10 is performed. It is recommended to
enable this mode.
ADC Conversion Clock (ADC_CLK_DIV)
An on-board analog-to-digital converter (ADC) determines the
V
TUNE setpoint relative to the ambient temperature of the
ADC Enable
ADF5355 environment. The ADC ensures that the initial tuning
voltage in any application is chosen correctly to avoid any
temperature drift issues.
AE1 (Bit DB4), when set to 1, powers up the ADC for the
temperature dependent VTUNE calibration. It is recommended to
always use this function.
The ADC uses a clock that is equal to the output of the R
counter (or the PFD frequency) divided by ADC_CLK_DIV.
REGISTER 11
The bits in this register are reserved and must be programmed
as described in Figure 52, using a hexadecimal word of
0x0061300B.
AD8 to AD1 (Bits[DB13:DB6]) set the value of this divider. On
power-up, the R counter is not programmed; however, in these
power-up cases, it defaults to R = 1.
Rev. D | Page 32 of 38
Data Sheet
ADF5355
CONTROL
BITS
RESERVED
PHASE RESYNC CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
P13 P12
P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1
0
0
0
0
0
1
0
0
0
0
0
1
P16 P15
C4(1) C3(1) C2(0) C1(0)
P14
P16
0
0
0
.
P15
...
...
...
...
...
...
...
...
...
...
...
...
P5
P4
P3
P2
P1
PHASE RESYNC CLOCK DIVIDER
0
0
0
.
0
0
0
.
0
0
0
.
0
0
0
.
0
0
1
.
0
1
0
.
NOT ALLOWED
1/NORMAL OPERATION
2
...
0
0
0
.
0
0
0
.
1
1
1
.
0
0
1
.
1
1
0
.
1
1
0
.
0
1
0
.
22
23
24
...
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
65533
65534
65535
Figure 53. Register 12
12. Register 1.
REGISTER 12
13. Wait >16 ADC clock cycles. For example, if the ADC clock =
99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10
section for more information.
Control Bits
With Bits[C4:C1] set to 1100, Register 12 is programmed.
Figure 53 shows the input data format for programming this
register.
14. Register 0.
For fPFD > 75 MHz (initially locked with half fPFD), use the
following sequence:
Phase Resync Clock Divider Value
P16 to P1 (Bits[DB31:DB16]) set the timeout counter for
activation of phase resync. This value must be set such that
a resync happens immediately after (and not before) the PLL
has achieved lock after reprogramming.
1. Register 12.
2. Register 11.
3. Register 10.
4. Register 9.
Calculate the timeout value using the following equation:
5. Register 8.
Time Out Value = Phase Resync Clock Divider/fPFD
6. Register 7.
7. Register 6.
8. Register 5.
When not using phase resync, set these bits to 1 for normal
operation.
9. Register 4 (with the R divider doubled to output half fPFD).
10. Register 3.
11. Register 2 (for halved fPFD).
12. Register 1 (for halved fPFD).
13. Wait >16 ADC clock cycles. For example, if the ADC clock =
99.417 kHz, wait 16/99417 sec = 161 μs. See the Register 10
section for more information.
14. Register 0 (for halved fPFD; autocalibration enabled).
15. Register 4 (with the R divider set for desired fPFD).
16. Register 2 (for desired fPFD).
17. Register 1 (for desired fPFD).
18. Register 0 (for desired fPFD; autocalibration disabled).
Reserved
Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB4 must be set
to 1, and all other bits in this range must be set to 0.
REGISTER INITIALIZATION SEQUENCE
At initial power-up, after the correct application of voltages to
the supply pins, the registers must be programmed in sequence.
For fPFD ≤ 75 MHz, use the following sequence:
1. Register 12.
2. Register 11.
3. Register 10.
4. Register 9.
5. Register 8.
6. Register 7.
7. Register 6.
8. Register 5.
9. Register 4.
10. Register 3.
11. Register 2.
FREQUENCY UPDATE SEQUENCE
Frequency updates require updating the auxiliary modulator
(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,
and the integer value (INT) in Register 0. It is recommended to
perform a temperature dependent VTUNE calibration by updating
Register 10 first. Toggling the counter reset bit (Register 4) is also
required. Therefore, for fPFD ≤ 75 MHz, use the following sequence:
Rev. D | Page 33 of 38
ADF5355
Data Sheet
1. Register 10.
required, a 122.88 MHz reference frequency input (REFIN)
2. Register 4 (counter reset enabled, DB4 = 1).
3. Register 2 (new FRAC2 and MOD2).
is available. Note that the ADF5355 VCO operates in the
frequency range of 3.4 GHz to 6.8 GHz. Therefore, the RF divider
4. Register 1 (new FRAC1).
of 2 must be used (VCO frequency = 4225.6 MHz, RFOUT =
5. Register 0 (new INT and AUTOCAL disabled, DB21 = 0).
6. Register 4 (counter reset disabled, DB4 = 0).
7. Wait >16 ADC clock cycles. For example, if the ADC clock =
99.417 kHz, wait 16/99417 sec = 161 µs. See the Register 10
section for more information.
VCO frequency/RF divider = 4225.6 MHz/2 = 2112.8 MHz).
The feedback path is also important. In this example, the VCO
output is fed back before the output divider (see Figure 54).
In this example, the 122.88 MHz reference signal is divided by 2
to generate fPFD of 61.44 MHz. The desired channel spacing is
200 kHz.
8. Register 0 (new INT and AUTOCAL enabled, DB21 = 1).
The frequency change occurs on the second write to Register 0.
fPFD
RF
OUT
PFD
VCO
÷2
For fPFD > 75 MHz (initially locked with half fPFD), use the
following sequence:
N
1. Register 10.
DIVIDER
2. Register 4 (counter reset enabled, DB4 = 1).
3. Register 2 (for halved fPFD).
Figure 54. Loop Closed Before Output Divider
4. Register 1 (for halved fPFD).
The worked example follows:
5. Register 0 (for halved fPFD; autocalibration disabled)
6. Register 4 (counter reset disabled [DB4 = 0], with the R
divider doubled to output half fPFD).
7. Wait >16 ADC clock cycles. For example, if the ADC clock =
99.417 kHz, wait 16/99417 sec = 161 μs. See the Register 10
section for more information.
•
N = VCOOUT/fPFD = 4225.6 MHz/61.44 MHz =
68.7760416666666667
INT = int(VCO frequency/fPFD) = 68
FRAC = 0.7760416666666667
•
•
•
•
•
•
MOD1 = 16,777,216
FRAC1 = int(MOD1 × FRAC) = 13019818
Remainder = 0.6666666667 or 2/3
MOD2 = fPFD/GCD(fPFD, fCHSP) =
61.44 MHz/GCD(61.44 MHz, 200 kHz) = 1536
FRAC2 = Remainder × 1536 = 1024
8. Register 0 (for halved fPFD; autocalibration enabled).
9. Register 4 (with the R divider set for desired fPFD
10. Register 2 (for desired fPFD).
.
11. Register 1 (for desired fPFD).
12. Register 0 (for desired fPFD; autocalibration disabled).
•
From Equation 8,
The frequency change only occurs when writing to Register 0.
f
PFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz
(x)
(9)
RF SYNTHESIZER—A WORKED EXAMPLE
2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +
FRAC2/MOD2)/224))/2
Use the following equations to program the ADF5355 synthesizer:
FRAC2
MOD2
MOD1
FRAC1+
where:
INT = 68
FRAC1 = 13,019,817
MOD2 = 1536
FRAC2 = 1024
RF Divider = 2
RFOUT = INT +
where:
×
(
fPFD /RF Divider (7)
)
RFOUT is the RF output frequency.
INT is the integer division factor.
FRAC1 is the fractionality.
FRAC2 is the auxiliary fractionality.
MOD1 is the fixed 24-bit modulus.
MOD2 is the auxiliary modulus.
RF Divider is the output divider that divides down the VCO
frequency.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The on-chip reference doubler allows the input reference signal
to be doubled. The doubler is useful for increasing the PFD
comparison frequency. To improve the noise performance of
the system, increase the PFD frequency. Doubling the PFD
frequency typically improves noise performance by 3 dB.
f
PFD = REFIN × ((1 + D)/(R × (1 + T)))
(8)
The reference divide by 2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency.
where:
REFIN is the reference frequency input.
D is the REFIN doubler bit.
R is the REF reference division factor.
SPURIOUS OPTIMIZATION AND FAST LOCK
Narrow loop bandwidths can filter unwanted spurious signals;
however, these bandwidths typically have a long lock time.
T is the reference divide by 2 bit (0 or 1).
For example, in a universal mobile telecommunication system
(UMTS) where a 2112.8 MHz RF frequency output (RFOUT) is
Rev. D | Page 34 of 38
Data Sheet
ADF5355
A wider loop bandwidth achieves faster lock times but may lead
to increased spurious signals inside the loop bandwidth.
It is found that
ALC Wait = 2.5 × Synthesizer Lock Timeout
OPTIMIZING JITTER
The ALC wait and synthesizer lock timeout values must be set
to fulfill this equation. Both values are 5 bits wide; therefore, the
maximum value for either is 31. There are several suitable values.
For lowest jitter applications, use the highest possible PFD
frequency to minimize the contribution of in-band noise from
the PLL. Set the PLL filter bandwidth such that the in-band noise
of the PLL intersects with the open-loop noise of the VCO,
minimizing the contribution of both to the overall noise.
The following values meet the criteria:
ALC Wait = 30
Synthesizer Lock Timeout = 12
Use the ADIsimPLL design tool for this task.
Finally, ALC Wait > (50 µs × fPFD)/Timeout, is rearranged for
Timeout = Ceiling((fPFD × 50 µs)/ALC Wait)
Timeout = Ceiling((61.44 MHz × 50 µs)/30) = 103
Synthesizer Lock Timeout
SPUR MECHANISMS
This section describes the two different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF5355.
Integer Boundary Spurs
The synthesizer lock timeout ensures that the VCO calibration
DAC, which forces VTUNE, has settled to a steady value for the
band select circuitry.
One mechanism for fractional spur creation is the interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (the purpose of a
fractional-N synthesizer), spur sidebands appear on the VCO
output spectrum at an offset frequency that corresponds to the
beat note or the difference in frequency between an integer
multiple of the reference and the VCO frequency. These spurs
are attenuated by the loop filter and are more noticeable on
channels close to integer multiples of the reference where the
difference frequency can be inside the loop bandwidth (thus
the name, integer boundary spurs).
The timeout and synthesizer lock timeout variables programmed
in Register 9 select the length of time the DAC is allowed to
settle to the final voltage, before the VCO calibration process
continues to the next phase, which is VCO band selection. The
PFD frequency is the clock for this logic, and the duration is set by
Timeout ×Synthesizer Lock Timeout
fPFD
The calculated time must be equal to or greater than 20 µs.
Reference Spurs
VCO Band Selection
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. Feedthrough of low
levels of on-chip reference switching noise, through the
prescaler back to the VCO, can result in reference spur levels
as high as −80 dBc.
Use the PFD frequency again as the clock for the band selection
process. Calculate this value by
fPFD/(VCO Band Selection × 16) < 150 kHz
The band selection takes 11 cycles of the previously calculated
value. Calculate the duration by
11 × (VCO Band Selection × 16)/fPFD
LOCK TIME
Automatic Level Calibration Timeout
The PLL lock time divides into a number of settings. All of
these settings are modeled in the ADIsimPLL design tool.
Use the automatic level calibration (ALC) function to choose
the correct bias current in the ADF5355 VCO core. Calculate
the time taken by
Much faster lock times than those detailed in this data sheet
are possible; contact Analog Devices for more information.
55 × ALC Wait × Timeout/fPFD
Lock Time—A Worked Example
Assume that fPFD = 61.44 MHz,
PLL Low-Pass Filter Settling Time
The time taken for the loop to settle is inversely proportional to
the low-pass filter bandwidth. The settling time is also modeled
in the ADIsimPLL design tool.
VCO Band Div = Ceiling(fPFD/2,400,000) = 26
where Ceiling() rounds up to the nearest integer.
By combining
The total lock time for changing frequencies is the sum of the
four separate times (synthesizer lock, VCO band selection, ALC
timeout, and PLL settling time) and is all modeled in the
ADIsimPLL design tool.
ALC Wait > (50 µs × fPFD)/Timeout
Synthesizer Lock Timeout > (20 µs × fPFD)/Timeout
Rev. D | Page 35 of 38
ADF5355
Data Sheet
APPLICATIONS INFORMATION
On the PCB, there must be a minimum clearance of 0.25 mm
between the thermal pad and the inner edges of the pad pattern.
This clearance ensures the avoidance of shorting.
POWER SUPPLIES
The ADF5355 contains four multiband VCOs that together cover
an octave range of frequencies. To ensure best performance, it is
vital to connect a low noise regulator, such as the ADM7150, to
the VVCO pin. Connect the same regulator to VVCO, VREGVCO, and VP.
To improve the thermal performance of the package, use thermal
vias on the PCB thermal pad. If vias are used, incorporate them
into the thermal pad at the 1.2 mm pitch grid. The via diameter
must be between 0.3 mm and 0.33 mm, and the via barrel must
be plated with 1 oz. of copper to plug the via.
For the 3.3 V supply pins, use an ADM7150 regulator. Figure 55
shows the recommended connections.
PRINTED CIRCUIT BOARD (PCB) DESIGN
GUIDELINES FOR A CHIP-SCALE PACKAGE
For a microwave PLL and VCO synthesizer, such as the ADF5355,
take care with the board stack-up and layout. Do not consider
using FR4 material because it is too lossy above 3 GHz. Instead,
Rogers 4350, Rogers 4003, or Rogers 3003 dielectric material is
suitable.
The lands on the 32-lead lead frame chip-scale package are
rectangular. The PCB pad for these lands must be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. Center each land on the pad to
maximize the solder joint size.
Take care with the RF output traces to minimize discontinuities
and ensure the best signal integrity. Via placement and grounding
are critical.
The bottom of the chip-scale package has a central exposed
thermal pad. The thermal pad on the PCB must be at least as
large as the exposed pad.
1
V
= 6.0V
FB
IN
V
OUT
= 3.3V
100nF
100nF
VIN
EN
VOUT
C
IN
10µF
C
10µF
OUT
ON
LOCK
DETECT
ADM7150
OFF
BYP
REF
17
6
27
5
16
4
26
10
32
REG2 CREG1
MUXOUT
25
30
C
10µF
BYP
VVCO
DVDD AVDD AV
VRF
C
DD CE PDBRF
VREG REF_SENSE
GND
VP
1nF
1nF
1nF
C
REG
10µF
10pF
FREFIN
FREFIN
29
REFIN
A
RFOUT
B
14
100Ω
VOUT
REFINB
28
1nF
7.5nH
7.5nH
1
2
3
CLK
DATA
LE
1nF
1nF
11
12
RFOUTA+
RFOUTA–
ADF5355
V
= 6.0V
IN
V
OUT
= 5.0V
VIN
EN
VOUT
VTUNE 20
C
IN
10µF
C
OUT
10µF
430Ω
ON
CPOUT
7
RSET
22
ADM7150
OFF
4.7kΩ
1µF
68Ω
33nF
6800pF
BYP
REF
C
BYP
10µF
VREG REF_SENSE
GND
CPGND SDGND
AGNDVCO AGNDRF VREGVCO VREF VBIAS
AGND
9
C
REG
10µF
15
8
31
18 21
13
19
23
24
10pF
0.1µF 10pF
0.1µF 10pF
0.1µF
1
MURATA PART NUMBER BLM15AX100SN1D HAS BEEN USED WITH GOOD RESULTS.
Figure 55. ADF5355 Power Supplies
Rev. D | Page 36 of 38
Data Sheet
ADF5355
For lower frequencies below 2 GHz, it is recommended to use a
100 nH inductor on the RFOUTA+/RFOUTA− pins.
OUTPUT MATCHING
The low frequency output can simply be ac-coupled to the next
circuit, if desired; however, if higher output power is required,
use a pull-up inductor to increase the output power level.
The RFOUTA+/RFOUTA− pins are a differential circuit. Provide
each output with the same (or similar) components where
possible, such as same shunt inductor value, bypass capacitor,
and termination.
V
RF
7.5nH
100pF
AC couple the higher frequency output, RFOUTB, directly to the
next appropriate circuit stage.
RF
A+
OUT
50Ω
RFOUTB is matched internally to a 50 Ω impedance and requires
no additional matching components.
Figure 56. Optimum Output Stage
When differential outputs are not needed, terminate the unused
output or combine it with both outputs using a balun.
Rev. D | Page 37 of 38
ADF5355
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00 SQ
4.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
25
32
24
1
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
8
16
9
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
Package Option
ADF5355BCPZ
ADF5355BCPZ-RL7
EV-ADF5355SD1Z
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
CP-32-12
CP-32-12
1 Z = RoHS Compliant Part.
©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12714-0-8/17(D)
Rev. D | Page 38 of 38
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