ADF5356BCPZ-RL7_技术文档

Microwave Wideband Synthesizer

with Integrated VCO

Data Sheet

ADF5356

FEATURES

GENERAL DESCRIPTION

RF output frequency range: 53.125 MHz to 13,600 MHz

Noise floor integer channel: −227 dBc/Hz

Noise floor fractional channel: −225 dBc/Hz

Integrated rms jitter (1 kHz to 20 MHz): 97 fs for 6 GHz output

Fractional-N synthesizer and integer N synthesizer

Pin compatible to the ADF5355

The ADF5356 allows implementation of fractional-N or integer N

phase-locked loop (PLL) frequency synthesizers when used with

an external loop filter and an external reference frequency. The

wideband microwave VCO design permits frequency operation

from 6.8 GHz to 13.6 GHz at one radio frequency (RF) output. A

series of frequency dividers at another frequency output permits

operation from 53.125 MHz to 6800 MHz.

High resolution, 52-bit modulus

Phase frequency detector (PFD) operation to 125 MHz

Reference input frequency operation to 600 MHz

Maintains frequency lock over −40°C to +85°C

Low phase noise, voltage controlled oscillator (VCO)

Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output

Analog and digital power supplies: 3.3 V

Charge pump and VCO power supplies: 5.0 V typical

Logic compatibility: 1.8 V

The ADF5356 has an integrated VCO with a fundamental

output frequency ranging from 3400 MHz to 6800 MHz. In

addition, the VCO frequency is connected to divide by 1, 2, 4, 8,

16, 32, or 64 circuits that allow the user to generate RF output

frequencies as low as 53.125 MHz. For applications that require

isolation, the RF output stage can be muted. The mute function

is both pin- and software-controllable.

Control of all on-chip registers is through a simple 3-wire interface.

The ADF5356 operates with analog and digital power supplies

ranging from 3.15 V to 3.45 V, with charge pump and VCO

supplies from 4.75 V to 5.25 V. The ADF5356 also contains

hardware and software power-down modes.

Programmable output power level

RF output mute function

Supported by the ADIsimPLL design tool

APPLICATIONS

Wireless infrastructure (LTE, W-CDMA, TD-SCDMA,

WiMAX, GSM, PCS, DCS)

Point to point and point to multipoint microwave links

Satellites and very small aperture terminals (VSATs)

Test equipment and instrumentation

Clock generation

FUNCTIONAL BLOCK DIAGRAM

V

VCO

AV

DV

V

R

AV

V

RF

CE

DD

P

SET

DD

MULTIPLEXER

MUXOUT

10-BIT R

COUNTER

÷2

DIVIDER

REF

A

B

IN

×2

DOUBLER

C

1

2

REG

LOCK

DETECT

REF

IN

CHARGE

PUMP

CLK

DATA

LE

CP

OUT

DATA REGISTER

FUNCTION

LATCH

PHASE

COMPARATOR

V

TUNE

REF

V

VCO

CORE

BIAS

×2

INTEGER

REG

FRACTION

REG

MODULUS

REG

V

REGVCO

OUTPUT

STAGE

RF

B

OUT

THIRD-ORDER

FRACTIONAL INTERPOLATOR

PDB

RF

÷ 1/2/4/8/

16/32/64

A+

A–

OUTPUT

STAGE

OUT

N COUNTER

RF

OUT

ADF5356

MULTIPLEXER

A

CP

SD

GND

A

GNDVCO

A

GND

GNDRF

Figure 1.

Rev. 0

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Tel: 781.329.4700

Technical Support

www.analog.com

ADF5356

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Register 3 ..................................................................................... 23

Register 4 ..................................................................................... 24

Register 5 ..................................................................................... 25

Register 6 ..................................................................................... 26

Register 7 ..................................................................................... 28

Register 8 ..................................................................................... 29

Register 9 ..................................................................................... 29

Register 10................................................................................... 30

Register 11................................................................................... 31

Register 12................................................................................... 31

Register 13................................................................................... 32

Register Initialization Sequence ............................................... 32

Frequency Update Sequence..................................................... 33

RF Synthesizer—A Worked Example...................................... 33

Reference Doubler and Reference Divider ............................. 34

Spurious Optimization and Fast Lock..................................... 34

Optimizing Jitter......................................................................... 34

Spur Mechanisms ....................................................................... 34

PLL Lock Time ........................................................................... 34

Applications Information.............................................................. 36

Power Supplies............................................................................ 36

PCB Design Guidelines for a Chip Scale Package ................. 36

Output Matching........................................................................ 37

Outline Dimensions....................................................................... 38

Ordering Guide .......................................................................... 38

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

Transistor Count........................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 15

Reference Input Section............................................................. 15

RF N Divider............................................................................... 15

Phase Frequency Detector (PFD) and Charge Pump............ 16

MUXOUT and Lock Detect...................................................... 16

Input Shift Registers................................................................... 16

Program Modes .......................................................................... 17

VCO.............................................................................................. 17

Output Stage................................................................................ 17

Register Maps.................................................................................. 19

Register 0 ..................................................................................... 21

Register 1 ..................................................................................... 22

Register 2 ..................................................................................... 22

REVISION HISTORY

8/2017—Revision 0: Initial Version

Rev. 0 | Page 2 of 38

Data Sheet

ADF5356

SPECIFICATIONS

AV_DD= DV_DD= V_RF= 3.3 V 5%, 4.75 V ≤ V_P= V_VCO≤ 5.25 V, A_GND= CP_GND= A_GNDVCO= SD_GND= A_GNDRF= 0 V, R_SET= 5.1 kΩ, dBm referred

to 50 Ω, T_A= T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

REF_INA/REF_INB CHARACTERISTICS

Input Frequency Range

Single-Ended Mode

Differential Mode

For f < 10 MHz, ensure slew rate > 21 V/μs

10

250

600

MHz

Input Sensitivity

Single-Ended Mode

0.4

AV_DD

1.8

V p-p

REF_INA biased at AV_DD/2; ac coupling ensures

AV_DD/2 bias

Low voltage differential signaling (LVDS) and

Low voltage positive emitter-coupled logic

(LVPECL) compatible, REF_INA/REF_INB biased at

2.1 V; ac coupling ensures 2.1 V bias

Differential Mode

Input Capacitance

Single-Ended Mode

Differential Mode

Input Current

6.9

1.4

pF

μA

MHz

100

250

125

Single-ended reference programmed

Differential reference programmed

PFD

CHARGE PUMP (CP)

CP Current, Sink/Source

I_CP

R_SET= 5.1 kΩ, this resistor is internal in the

ADF5356

High Value

Low Value

R_SETRange

Current Matching

I_CPvs. V_CP

4.8

0.3

5.1

3

mA

kΩ

%

Fixed

0.5 V ≤ V_CP¹≤ V_P− 0.5 V

V_CP¹= 2.5 V

3

%

I_CPvs. Temperature

LOGIC INPUTS

Input Voltage

High

1.5

%

V_INH

V_INL

I_INH/I_INL

C_IN

1.5

DV_DD

0.6

1

V

μA

pF

Low

Input Current, High/Low

Input Capacitance

LOGIC OUTPUTS

Output High Voltage

3.0

1.8

V_OH

DV_DD− 0.4

1.5

V

3.3 V output selected

1.8 V output selected

Output High Current

Output Low Voltage

POWER SUPPLIES

Analog Power

Digital Power and RF Supply

Voltage

I_OH

V_OL

500

0.4

μA

V

I_OL²= 500 μA

See Table 7

AV_DD

DV_DD

V_RF

V_P, V_VCO

3.15

4.75

3.3

AV_DD

3.45

V

,

Voltages must equal AV_DD

V_Pmust equal V_VCO

CP and VCO Supply Voltage

5.0

82

5.25

92

V

mA

Total Digital and Analog Current,

3

DI_DD+ AI_DD

Output Dividers

CP Supply Power Current

Supply Current

6 to 36

8

70

mA

Each output divide by 2 consumes 6 mA

For maximum I_CP= 4.8 mA

I_P

I_VCO

9

90

Rev. 0 | Page 3 of 38

ADF5356

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

RF_OUTA+/RF_OUTA− and RF_OUTB Supply

Current

I_RFOUTx

RF Output A and RF Output B enabled;

RF Output A is programmable; enabling RF

Output B draws negligible extra current

12

24

35

46

5

15

29

42

56

mA

−4 dBm setting

−1 dBm setting

2 dBm setting

5 dBm setting

Hardware power-down selected

Software power-down selected

Low Power Sleep Mode

20

RF OUTPUT CHARACTERISTICS

VCO Frequency Range

3400

6800

53.125

6800

13600 MHz

12000 MHz

MHz

Fundamental VCO range

RF_OUTB Output Frequency

2× VCO output (RF_OUTB), prescaler = 8/9

2× VCO output (RF_OUTB), prescaler = 4/5

Prescaler = 8/9

RF_OUTA+/RF_OUTA− Output

Frequency

6800

MHz

53.125

6000

MHz

Prescaler = 4/5

VCO Sensitivity

Frequency Pushing (Open Loop)

Frequency Pulling (Open Loop)

K_V

25

12

0.5

MHz/V

MHz

Voltage standing wave ratio (VSWR) = 2:1

RF_OUTA/RF_OUTA−

30

MHz

VSWR = 2:1 RF_OUTB

Harmonic Content

Second

−26

−29

−32

−14

−10

8

−1

0

2

dBc

dBm

dB

Fundamental VCO output (RF_OUTA+)

Divided VCO output (RF_OUTA+)

Fundamental VCO output (RF_OUTA+)

Divided VCO output (RF_OUTA+)

RF_OUTB = 10 GHz

RF_OUTA+ = 1 GHz; 7.4 nH inductor to V_RF

RF_OUTA+ = 6.8 GHz; 7.4 nH inductor to V_RF

RF_OUTB = 6.8 GHz

Third

Fundamental VCO Feedthrough

RF Output Power⁴

RF_OUTB = 13.6 GHz

RF_OUTA+ = 5 GHz

Variation

1

dB

RF_OUTB = 10 GHz

Variation over Frequency

5

3

−53

dB

dBm

RF_OUTA+ = 1 GHz to 6.8 GHz

RF_OUTB = 6.8 GHz to 13.6 GHz

RF_OUTA+ = 1 GHz

Level of Signal with RF Output

Disabled

−20

−16

−12

dBm

RF_OUTA+ = 6.8 GHz

RF_OUTB = 6.8 GHz

RF_OUTB = 13.6 GHz

NOISE CHARACTERISTICS

Fundamental VCO Phase Noise

Performance

VCO noise in open-loop conditions

−115

−135

−137

−155

−113

−133

−135

−153

−110

−130

−132

−150

dBc/Hz

100 kHz offset from 3.4 GHz carrier

800 kHz offset from 3.4 GHz carrier

1 MHz offset from 3.4 GHz carrier

10 MHz offset from 3.4 GHz carrier

100 kHz offset from 5.0 GHz carrier

800 kHz offset from 5.0 GHz carrier

1 MHz offset from 5.0 GHz carrier

10 MHz offset from 5.0 GHz carrier

100 kHz offset from 6.8 GHz carrier

800 kHz offset from 6.8 GHz carrier

1 MHz offset from 6.8 GHz carrier

10 MHz offset from 6.8 GHz carrier

Rev. 0 | Page 4 of 38

Data Sheet

ADF5356

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

VCO 2× Phase Noise Performance

VCO noise in open-loop conditions

100 kHz offset from 6.8 GHz carrier

800 kHz offset from 6.8 GHz carrier

1 MHz offset from 6.8 GHz carrier

10 MHz offset from 6.8 GHz carrier

100 kHz offset from 10 GHz carrier

800 kHz offset from 10 GHz carrier

1 MHz offset from 10 GHz carrier

10 MHz offset from 10 GHz carrier

100 kHz offset from 13.6 GHz carrier

800 kHz offset from 13.6 GHz carrier

1 MHz offset from 13.6 GHz carrier

10 MHz offset from 13.6 GHz carrier

−110

−130

−132

−149

−107

−127

−129

−147

−103

−124

−126

−144

dBc/Hz

Normalized In-Band Phase Noise

Floor

Fractional Channel⁵

Integer Channel⁶

Normalized 1/f Noise, PN_{1_f}

Integrated RMS Jitter (1 kHz to

20 MHz)⁸

−225

−227

−121

97

dBc/Hz

fs

7

10 kHz offset; normalized to 1 GHz

Spurious Signals Due to PFD

Frequency

−85

dBc

¹V_CPis the voltage at the CP_OUTpin.

²I_OLis the output low current.

³T_A= 25°C; AV_DD= DV_DD= V_RF= 3.3 V; V_VCO= V_P= 5.0 V; prescaler = 8/9; f_REFIN= 122.88 MHz; f_PFD= 61.44 MHz; and f_RF= 1650 MHz.

⁴RF output power using the EV-ADF5356SD1Z evaluation board is measured by a spectrum analyzer, with board and cable losses de-embedded. Unused RF output pins

are terminated into 50 Ω.

⁵Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

−225 + 10log(f_PFD) + 20logN. The value given is the lowest noise mode for the fractional channel.

⁶Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

−227 + 10log(f_PFD) + 20logN. The value given is the lowest noise mode for the integer channel.

⁷The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (f_RF)

and at a frequency offset (f) is given by PN = P_{1_f}+ 10log(10 kHz/f) + 20log(f_RF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the

ADIsimPLL design tool.

⁸Integrated rms jitter using the EV-ADF5356SD1Z evaluation board is measured by a spectrum analyzer. The EV-ADF5356SD1Z evaluation board is configured to accept

a single-ended REF_INsignal (SMA 100) = 160 MHz, VCO frequency = 6 GHz, f_PFD= 80 MHz, charge pump current = 0.9 mA, with bleed current off. The loop filter is

configured for an 80 kHz loop filter bandwidth. Unused RF output pins are terminated into 50 Ω.

Rev. 0 | Page 5 of 38

ADF5356

Data Sheet

TIMING CHARACTERISTICS

AV_DD= DV_DD=V_RF= 3.3 V 5%, 4.75 V ≤ V_P= V_VCO≤ 5.25 V, A_GND= CP_GND= A_GNDVCO= SD_GND= A_GNDRF= 0 V, R_SET= 5.1 kΩ, dBm referred

to 50 Ω, T_A= T_MINto T_MAX, unless otherwise noted.

Table 2. Write Timing

Parameter

Limit

Unit

Description

f_CLK

t₁

t₂

t₃

t₄

t₅

t₆

t₇

50

10

5

10

MHz max

ns min

Serial peripheral interface (SPI) CLK frequency

LE setup time

DATA to CLK setup time

DATA to CLK hold time

CLK high duration

CLK low duration

CLK to LE setup time

LE pulse width

20 or (2/f_PFD), whichever is longer

Write Timing Diagram

t₄

t₅

CLK

t₂

t₃

DB3

DB2

(CONTROL BIT C3)

DB1

DB0 (LSB)

(CONTROL BIT C1)

DB31 (MSB)

DB30

DATA

LE

(CONTROL BIT C4)

(CONTROL BIT C2)

t₇

t₁

t₆

Figure 2. Write Timing Diagram

Rev. 0 | Page 6 of 38

Data Sheet

ADF5356

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Careful attention to

PCB thermal design is required. θ_JAis the natural convection

junction to ambient thermal resistance measured in a one cubic

foot sealed enclosure.

Table 3.

Parameter

V_RF, DV_DD, AV_DDto GND¹

AV_DDto DV_DD

V_P, V_VCOto GND¹

CP_OUTto GND¹

Digital Input/Output Voltage to GND¹−0.3 V to DV_DD+ 0.3 V

Analog Input/Output Voltage to GND¹−0.3 V to AV_DD+ 0.3 V

REF_INA, REF_INB to GND¹

Rating

−0.3 V to +3.6 V

−0.3 V to +0.3 V

−0.3 V to +5.8 V

−0.3 V to V_P+ 0.3 V

Table 4. Thermal Resistance

Package Type

CP-32-12¹

θ_JA

Unit

27.3

°C/W

−0.3 V to AV_DD+ 0.3 V

2.1 V

−40°C to +85°C

−65°C to +125°C

150°C

¹Thermal impedance simulated values are based on use of a PCB with the

REF_INA to REF_INB

thermal impedance pad soldered to GND (GND = A_GND= SD_GND= A_GNDRF

A_GNDVCO= CP_GND= 0 V).

=

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

Reflow Soldering

TRANSISTOR COUNT

The transistor count for the ADF5356 is 134,486 (CMOS) and

3874 (bipolar).

Peak Temperature

260°C

40 sec

Time at Peak Temperature

Electrostatic Discharge (ESD)

Charged Device Model

Human Body Model

ESD CAUTION

500 V

2000 V

¹GND = A_GND= SD_GND= A_GNDRF= A_GNDVCO= CP_GND= 0 V.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

The ADF5356 is a high performance RF integrated circuit with

an ESD rating of 2 kV and is ESD sensitive. Take proper

precautions for handling and assembly.

Rev. 0 | Page 7 of 38

ADF5356

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CLK

DATA

LE

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

V

NIC

A

BIAS

REF

ADF5356

TOP VIEW

(Not to Scale)

CE

GNDVCO

AV

V

DD

TUNE

V

P

REGVCO

A

V

CP

GNDVCO

OUT

GND

VCO

NOTES

1. NIC = NO INTERNAL CONNECTION. FOR EXISTING DESIGNS THAT CURRENTLY USE THE ADF5355,

TO UPGRADE TO THE ADF5356, THE R RESISTOR CAN BE LEFT CONNECTED TO THIS PIN.

SET

2. THE EXPOSED PAD MUST BE CONNECTED TO A

.

GND

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

CLK

DATA

LE

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four LSBs as the control bits. This

input is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is

selected by the four LSBs.

2

3

4

CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A

logic high on this pin powers up the device, depending on the status of the power-down bits.

5, 16

AV_DD

V_P

Analog Power Supplies. These pins range from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog

ground plane as close to these pins as possible. AV_DDmust have the same value as DV_DD.

Charge Pump Power Supply. V_Pmust have the same value as V_VCO. Connect decoupling capacitors to the ground

plane as close to this pin as possible.

Charge Pump Output. When enabled, this output provides I_CPto the external loop filter. The output of the loop

filter is connected to V_TUNEto drive the internal VCO.

6

7

CP_OUT

8

9

10

CP_GND

A_GND

V_RF

Charge Pump Ground. This output is the ground return pin for CP_OUT

Analog Ground. This pin is the ground return pin for AV_DD.

Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin as

possible. V_RFmust have the same value as AV_DD.

.

11

12

RF_OUTA+

RF_OUTA−

A_GNDRF

VCO Output. The output level is programmable. The VCO fundamental output, or a divided down version, is

available.

Complementary VCO Output. The output level is programmable. The VCO fundamental output, or a divided down

version, is available.

RF Output Stage Ground. This pin is the ground return pin for the RF output stage.

Auxiliary VCO Output. The 2× VCO output is available at this pin.

Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Place decoupling capacitors to the

analog ground plane as close to this pin as possible.

13, 15

14

17

RF_OUT

V_VCO

B

18, 21

19

A_GNDVCO

V_REGVCO

VCO Ground. This pin is the ground return path for the VCO.

VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.

Connect V_REGVCOdirectly to V_VCO

.

Rev. 0 | Page 8 of 38

Data Sheet

ADF5356

Pin No. Mnemonic Description

20

22

23

V_TUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP_OUT

output voltage. The capacitance at this pin (V_TUNEinput capacitance) is 9 pF.

No Internal Connection. For existing designs that currently use the ADF5355, to upgrade to the ADF5356, the R_SET

resistor can be left connected to this pin.

Internal Compensation Node. This pin is dc biased at half the tuning range. Connect decoupling capacitors to the

ground plane as close to this pin as possible.

NIC

V_REF

24

V_BIAS

Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.

25, 32

C_REG1, C_REG

2

Outputs from the LDO Regulator. C_REG1 and C_REG2 are the supply voltages to the digital circuits. These pins have a

nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to A_GNDare required for these pins.

26

27

PDB_RF

DV_DD

RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software controllable. Do

not leave this pin floating.

Digital Power Supply. This pin must be at the same voltage as AV_DD. Place decoupling capacitors to the ground

plane as close to this pin as possible.

28

29

30

REF_INB

REF_INA

MUXOUT

Complementary Reference Input. If unused, ac couple this pin to A_GND

Reference Input.

Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the

scaled reference frequency to be externally accessible.

.

31

SD_GND

EP

Digital Σ-Δ Modulator Ground. SD_GNDis the ground return path for the Σ-Δ modulator.

Exposed Pad. The exposed pad must be connected to A_GND

.

Rev. 0 | Page 9 of 38

ADF5356

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

–50

–80

–90

DIV1

DIV2

DIV4

DIV8

–70

DIV16

DIV32

DIV64

–100

–110

–120

–130

–140

–150

–160

–170

–90

–110

–130

–150

–170

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET FROM CARRIER (Hz)

FREQUENCY (Hz)

Figure 4. Open-Loop VCO Phase Noise, 3.4 GHz

Figure 7. Closed-Loop Phase Noise, RF_OUTA+ (100 nH Inductors),

Fundamental VCO and Dividers, VCO = 3.4 GHz, PFD = 61.44 MHz, Loop

Bandwidth = 40 kHz

–50

–70

–50

DIV1

DIV2

DIV4

DIV8

–70

–90

DIV16

DIV32

DIV64

–90

–110

–130

–150

–170

–110

–130

–150

–170

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET FROM CARRIER (Hz)

FREQUENCY (Hz)

Figure 5. Open-Loop VCO Phase Noise, 5.0 GHz

Figure 8. Closed-Loop Phase Noise, RF_OUTA+ (100 nH Inductors),

Fundamental VCO and Dividers, VCO = 5.0 GHz, PFD = 61.44 MHz, Loop

Bandwidth = 40 kHz

–50

–70

–50

DIV1

DIV2

DIV4

DIV8

–70

–90

DIV16

DIV32

DIV64

–90

–110

–130

–150

–170

–110

–130

–150

–170

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET FROM CARRIER (Hz)

FREQUENCY (Hz)

Figure 6. Open-Loop VCO Phase Noise, 6.8 GHz

Figure 9. Closed-Loop Phase Noise, RF_OUTA+ (100 nH Inductors),

Fundamental VCO and Dividers, VCO = 6.8 GHz, PFD = 61.44 MHz, Loop

Bandwidth = 40 kHz

Rev. 0 | Page 10 of 38

Data Sheet

ADF5356

–60

–80

DIV1

–100

–120

–140

–160

–100

–120

–140

–160

–180

DIV2

–180

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET FROM CARRIER (Hz)

Figure 13. Closed-Loop Phase Noise, RF_OUTB = 6.8 GHz, 2× VCO,

VCO = 3.4 GHz, f_PFD= 61.44 MHz, Loop Bandwidth = 10 kHz,

Figure 10. Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and

Divide by 2, VCO = 3.4 GHz, f_PFD= 61.44 MHz, Loop Bandwidth = 10 kHz

–60

–80

DIV1

–100

DIV2

–120

–140

–160

–180

–120

–140

–160

–180

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET FROM CARRIER (Hz)

Figure 14. Closed-Loop Phase Noise, RF_OUTB = 10 GHz, 2× VCO,

VCO = 5.0 GHz, f_PFD= 61.44 MHz, Loop Bandwidth = 10 kHz

Figure 11. Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and

Divide by 2, VCO = 5.0 GHz, f_PFD= 61.44 MHz, Loop Bandwidth = 10 kHz

–60

–70

–80

–90

–60

–80

DIV1

–100

DIV2

–100

–110

–120

–130

–140

–150

–160

–120

–140

–160

–180

1k

10k

100k

1M

10M

100M

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET FROM CARRIER (Hz)

Figure 15. Closed-Loop Phase Noise, RF_OUTB = 13.6 GHz, 2× VCO,

VCO = 6.8 GHz, f_PFD= 61.44 MHz, Loop Bandwidth = 10 kHz

Figure 12 Closed-Loop Phase Noise, RF_OUTA+, Fundamental VCO and

Divide by 2, VCO = 6.8 GHz, f_PFD= 61.44 MHz, Loop Bandwidth = 10 kHz

Rev. 0 | Page 11 of 38

ADF5356

Data Sheet

15

10

5

0

–1

–2

–3

–4

–5

–6

–7

–8

T

= +85°C

= +25°C

= –40°C

A

–9

–10

–11

–12

–13

–14

–15

–16

–17

–18

–19

0

–5

–10

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

OUTPUT FREQUENCY (GHz)

VCO FREQUENCY (MHz)

Figure 19. VCO Feedthrough at RF_OUTB (Board and Cable Losses De-

Embedded) vs. VCO Frequency

Figure 16. RF_OUTA+/RF_OUTA− Output Power vs. Output Frequency, (7.4 nH

Inductors, 10 pF AC Coupling Capacitors, Board and Cable Losses De-

Embedded)

10

0

10

0

CARRIER (dBm)

SECOND HARMONIC (dBc)

THIRD HARMONIC (dBc)

FOURTH HARMONIC (dBc)

FIFTH HARMONIC (dBc)

CARRIER (dBm)

–10

–20

–30

–40

–50

–60

–70

–80

–10

–20

–30

–40

–50

–60

–70

–80

SECOND HARMONIC (dBc)

THIRD HARMONIC (dBc)

FOURTH HARMONIC (dBc)

FIFTH HARMONIC (dBc)

–10

–20

–30

–40

–50

–60

–10

–20

–30

–40

–50

–60

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

OUTPUT FREQUENCY (GHz)

Figure 20. Harmonics and RF_OUTB Output Power of Carrier vs. Output

Frequency (10 pF AC Coupling Capacitors, Board and Cable Losses De-

Embedded)

Figure 17. Harmonics and RF_OUTA+/RF_OUTA− Output Power of Carrier vs.

Output Frequency (7.4 nH Inductors, 10 pF AC Coupling Capacitors, Board

and Cable Losses De-Embedded)

0

–10

–20

–30

–40

–50

–60

3

2

1

0

–1

–2

T

= +85°C

= +25°C

= –40°C

–3

–4

–5

–6

–7

–8

A

5

7

9

11

13

15

17

19

21

23

25

FREQUENCY (GHz)

OUTPUT FREQUENCY (GHz)

Figure 21. Wideband Spectrum, RF_OUTB, VCO = 6.8 GHz, RF_OUTB Enabled,

RF_OUTA+/RF_OUTA− Disabled (Board Measurement)

Figure 18. RF_OUTB Output Power vs. Output Frequency (10 pF AC Coupling

Capacitors, Board and Cable Losses De-Embedded)

Rev. 0 | Page 12 of 38

Data Sheet

ADF5356

250

200

150

100

50

–40

–50

PFD = 122.88MHz

PFD = 61.44MHz

PFD = 30.72MHz

1kHz TO 20MHz

12kHz TO 20MHz

–60

–70

–80

–90

–100

–110

0

1000

2000

3000

4000

5000

6000

7000

OUTPUT FREQUENCY (MHz)

Figure 24. Worst Case PFD/Reference Spur vs. Output Frequency (RF_OUTB),

f_PFD= 30.72 MHz, 61.44 MHz, and 122.88 MHz, Loop Filter = 3 kHz

Figure 22. RMS Jitter/Noise vs. Output Frequency,

PFD Frequency = 61.44 MHz, Loop Filter = 40 kHz

–60

–40

PFD = 122.88MHz

PFD = 61.44MHz

PFD = 30.72MHz

–50

–60

–80

–100

–120

–140

–160

–180

–70

–80

–90

–100

–110

1k

10k

100k

1M

10M

100M

0

1000

2000

3000

4000

5000

6000

7000

FREQUENCY (Hz)

OUTPUT FREQUENCY (MHz)

Figure 25. Fractional-N Spur Performance, GSM1800 Band, RF_OUTA+ =

1550.2 MHz, f_REFIN= 122.88 MHz, f_PFD= 61.44 MHz, Output Divide by 4

Selected, Loop Filter Bandwidth = 10 kHz, Channel Spacing = 20 kHz

Figure 23. Worst Case PFD/Reference Spur vs. Output Frequency

(RF_OUTA+/RF_OUTA−), f_PFD= 30.72 MHz, 61.44 MHz, and 122.88 MHz,

Loop Filter = 3 kHz

Rev. 0 | Page 13 of 38

ADF5356

Data Sheet

–60

4650

4600

4550

4500

4450

4400

4350

4300

4250

4200

4150

–80

–100

–120

–140

–160

1

–180

1k

10k

100k

1M

10M

100M

–1

0

1

2

3

4

FREQUENCY (Hz)

TIME (ms)

Figure 26. Fractional-N Spur Performance, W-CDMA Band, RF_OUTA+ =

2113.5 MHz, f_REFIN= 122.88 MHz, f_PFD= 61.44 MHz, Output Divide by 2

Selected, Loop Filter Bandwidth = 10 kHz, Channel Spacing = 20 kHz

Figure 28. Lock Time for 250 MHz Jump from 4150 MHz to 4400 MHz,

Loop Bandwidth = 23 kHz

–60

–80

–100

–120

–140

–160

–180

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 27. Fractional-N Spur Performance, RF_OUTA+ = 2.591 GHz,

f

_REFIN= 122.88 MHz, f_PFD= 61.44 MHz, Output Divide by 2 Selected,

Loop Filter Bandwidth = 10 kHz, Channel Spacing = 20 kHz

Rev. 0 | Page 14 of 38

Data Sheet

ADF5356

THEORY OF OPERATION

INT, FRACx, MODx, and R Counter Relationship

REFERENCE INPUT SECTION

The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in

conjunction with the R counter, make it possible to generate

output frequencies spaced by fractions of the PFD frequency

(f_PFD). For more information, see the RF Synthesizer—A Worked

Example section.

Figure 29 shows the reference input stage. The reference input

can accept both single-ended and differential signals. Use the

reference mode bit (Register 4, Bit DB9) to select the signal. To

use a differential signal on the reference input, program this bit

high. In this case, SW1 and SW2 are open, SW3 and SW4 are

closed, and the current source that drives the differential pair of

transistors switches on. The differential signal buffers and provides

an emitter coupled logic (ECL) to the CMOS converter. When a

single-ended signal is used as the reference, program Bit DB9

in Register 4 to 0. Connect the single-ended reference signal to

REF_INA. In this case, SW1 and SW2 are closed, SW3 and SW4

are open, and the current source that drives the differential pair

of transistors switches off.

Calculate the RF VCO frequency (VCO_OUT) as follows:

VCO_OUT= f_PFD× N

(1)

where:

VCO_OUTis the output frequency of the VCO (without using the

output divider).

f

_PFDis the frequency of the phase frequency detector.

N is the desired value of the feedback counter, N.

Calculate f_PFDas follows:

REFERENCE

INPUT MODE

f

_PFD= f_REFIN× ((1 + D)/(R × (1 + T)))

where:

_REFINis the reference input frequency.

(2)

85kꢀ

f

SW2

BUFFER

SW1

D is the f_REFINdoubler bit.

R is the preset divide ratio of the binary 10-bit programmable

reference counter (1 to 1023).

SW3

TO

R COUNTER

MULTIPLEXER

T is the f_REFINdivide by 2 bit (0 or 1).

N comprises

AV

DD

ECL TO CMOS

BUFFER

FRAC2

MOD2

MOD1

FRAC1 

N  INT 

(3)

REF

A

B

IN

where:

INT is the 16-bit integer value (23 to 32,767 for the 4/5

prescaler, and 75 to 65,535 for the 8/9 prescaler).

IN

2.5kΩ

FRAC1 is the numerator of the primary modulus (0 to 16,777,215).

FRAC2 is the numerator of the 28-bit auxiliary modulus

(0 to 268,435,455).

SW4

BIAS

GENERATOR

Figure 29. Reference Input Stage

MOD2 is the programmable, 28-bit auxiliary fractional

modulus (2 to 268,435,455).

RF N DIVIDER

MOD1 is a 24-bit primary modulus with a fixed value of 2²⁴

=

The RF N divider allows a division ratio in the PLL feedback

path. Determine the division ratio by the INT, FRAC1, FRAC2,

and MOD2 values that this divider comprises.

16,777,216.

Equation 3 results in a very fine frequency resolution with no

residual frequency error. To apply this formula, take the

following steps:

1. Calculate N by dividing VCO_OUT/f_PFD. The integer value of

this number forms INT.

2. Subtract the INT value from the full N value.

3. Multiply the remainder by 2²⁴. The integer value of this

number forms FRAC1.

FRAC2

MOD2

RF N COUNTER

N = INT +

FRAC1 +

MOD1

FROM

VCO OUTPUT/

OUTPUT DIVIDERS

TO PFD

N COUNTER

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

4. Calculate MOD2 based on the channel spacing (f_CHSP) as

follows:

INT

REG

FRAC1

REG

FRAC2

VALUE

MOD2

VALUE

MOD2 = f_PFD/GCD(f_PFD, f_CHSP

)

(4)

where:

Figure 30. RF N Divider

GCD(f_PFD, f_CHSP) is the greatest common divider of the PFD

frequency and the desired channel spacing frequency.

f

_CHSPis the desired channel spacing frequency.

Rev. 0 | Page 15 of 38

ADF5356

Data Sheet

5. Calculate FRAC2 as follows:

MUXOUT AND LOCK DETECT

FRAC2 = ((N − INT) × 2²⁴− FRAC1)) × MOD2

(5)

(6)

The output multiplexer on the ADF5356 allows the user to access

various internal points on the chip. The M3, M2, and M1 bits in

Register 4 control the state of MUXOUT. Figure 32 shows the

MUXOUT section in block diagram form.

The FRAC2 and MOD2 fraction results in outputs with zero

frequency error for channel spacings when

f

_PFD/GCD(f_PFD/f_CHSP) < 268,435,455

where:

_PFDis the frequency of the phase frequency detector.

GCD is a greatest common denominator function.

_CHSPis the desired channel spacing frequency.

DV

DD

f

THREE-STATE OUTPUT

DV

DD

f

SD

GND

If zero frequency error is not required, the MOD1 and MOD2

denominators operate together to create a 52-bit resolution

modulus.

R DIVIDER OUTPUT

N DIVIDER OUTPUT

MUX

CONTROL

MUXOUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

RESERVED

Integer N Mode

When FRAC1 and FRAC2 are 0, the synthesizer operates in

integer N mode.

SD

GND

R Counter

Figure 32. MUXOUT Schematic

The 10-bit R counter allows the input reference frequency

(f_REFIN) to be divided down to produce the reference clock to the

PFD. Division ratios from 1 to 1023 are allowed.

INPUT SHIFT REGISTERS

The ADF5356 digital section includes a 10-bit R counter, a

16-bit RF integer N counter, a 24-bit FRAC1 counter, a 28-bit

auxiliary fractional counter, and a 28-bit auxiliary modulus

counter. Data clocks into the 32-bit shift register on each rising

edge of CLK. The data clocks in MSB first. Data transfers from

the shift register to one of 13 latches on the rising edge of LE.

The state of the four control bits (C4, C3, C2, and C1) in the

shift register determines the destination latch. As shown in

Figure 2, the four least significant bits (LSBs) are DB3, DB2,

DB1, and DB0. The truth table for these bits is shown in Table 6.

Figure 36 and Figure 37 summarize the programming of the

latches.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 31 is a simplified schematic of

the phase frequency detector. The PFD includes a fixed delay

element that sets the width of the antibacklash pulse. This pulse

ensures that there is no dead zone in the PFD transfer function

and provides a consistent reference spur level. Set the phase

detector polarity to positive on this device because of the

positive tuning of the VCO.

Table 6. Truth Table for the C4, C3, C2, and C1 Control Bits

UP

HIGH

D1

Q1

Control Bits

U1

CLR1

C4

0

1

C3

0

1

0

1

C2

0

1

0

1

0

1

0

C1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Register

+IN

Register 0

Register 1

Register 2

Register 3

Register 4

Register 5

Register 6

Register 7

Register 8

Register 9

Register 10

Register 11

Register 12

Register 13

CHARGE

PUMP

CP

U3

DELAY

DOWN

CLR2

D2 Q2

HIGH

U2

–IN

Figure 31. PFD Simplified Schematic

Rev. 0 | Page 16 of 38

Data Sheet

ADF5356

50

40

30

20

10

0

PROGRAM MODES

Table 6 and Figure 38 through Figure 51 show how the program

modes must be set up for the ADF5356.

AVERAGE

LINEAR

VCO SENSITIVITY

TREND LINE

The following settings in the ADF5356 are double-buffered: main

fractional value (FRAC1), auxiliary modulus value (MOD2),

auxiliary fractional value (FRAC2), reference doubler, reference

divide by 2 (RDIV2), R counter value, and charge pump current

setting. Two events must occur before the ADF5356 uses a new

value for any of the double-buffered settings. First, the new value

must latch into the device by writing to the appropriate register,

and second, a new write to Register 0 must be performed.

For example, to ensure that the modulus value loads correctly,

every time that the modulus value updates, Register 0 must be

written to. The RF divider select in Register 6 is also double

buffered, but only if DB14 of Register 4 is high.

3.4

3.8

4.2

4.6

5.0

5.4

5.8

6.2

6.6

FREQUENCY (GHz)

Figure 33. VCO Sensitivity, K_Vvs. Frequency

OUTPUT STAGE

VCO

The RF_OUTA+ and RF_OUTA− pins of the ADF5356 connect to

the collectors of a negative/positive/negative (NPN) differential

pair driven by buffered outputs of the VCO, as shown in Figure 34.

In this scheme, the ADF5356 contains internal 50 Ω resistors

connected to the V_RFpin. To optimize the power dissipation vs.

the output power requirements, the tail current of the differential

pair is programmable using Bits[DB5:DB4] in Register 6. Four

current levels can be set. These levels give approximate output

power levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm,

respectively. Levels of −4 dBm, −1 dBm, and +2 dBm can be

achieved using a 50 Ω resistor connected to V_RFand ac coupling

into a 50 Ω load. For accurate power levels, refer to the Typical

Performance Characteristics section. An output power of 5 dBm

requires an external shunt inductor to provide higher power levels;

however, this addition results in less wideband performance

using the internal bias only. Terminate the unused complementary

output with a similar circuit to the used output.

The VCO core in the ADF5356 consists of four separate VCOs,

each of which uses 256 overlapping bands, which allows the

device to cover a wide frequency range without large VCO

sensitivity (K_V) and without resulting in poor phase noise and

spurious performance.

The correct VCO and band are chosen automatically by the

VCO and band select logic when Register 0 is updated and

autocalibration is enabled.

The R counter output is the clock for the band select logic. After

band selection, normal PLL action resumes. The nominal value of

K_Vis 25 MHz/V when the N divider is driven from the VCO

output, or the K_Vvalue is divided by D. D is the output divider

value if the N divider is driven from the RF output divider (chosen

by programming Bits[DB23:DB21] in Register 6).

The VCO shows variations of K_Vas the tuning voltage, V_TUNE, varies

within the band and from band to band. For wideband applications

covering a wide frequency range (and changing output dividers), a

value of 25 MHz/V provides the most accurate K_V, because this

value is closest to the average value. Figure 33 shows how K_Vvaries

with the fundamental VCO frequency along with an average value

for the frequency band. Users may prefer this K_Vvalue shown in

Figure 33 when using narrow-band designs.

V

RF

50ꢀ

A+

50ꢀ

RF

A–

OUT

BUFFER/

DIVIDE BY

1/2/4/8/

VCO

16/32/64

Figure 34. Output Stage

The doubled VCO output (6.8 GHz to 13.6 GHz) is available on

the RF_OUTB pin, which can be ac-coupled to the next circuit.

2× VCO

MUX

RF

B

OUT

Figure 35. Output Stage

Rev. 0 | Page 17 of 38

ADF5356

Data Sheet

Another feature of the ADF5356 is that the supply current to

the RF_OUTA+/RF_OUTA− output stage can shut down until the

ADF5356 achieves lock as measured by the digital lock detect

circuitry. The mute till lock detect (MTLD) bit (Bit DB11) in

Register 6 enables this function.

RF_OUTB directly connects to the VCO, and it can be muted but

only by using the RF Output B enable bit (Bit DB10) in Register 6.

Table 7. Total I_DD¹(RF Output A Enabled)²

RF_OUTA Off

(mA)

RF_OUT

(mA)

A

= −4 dBm

RF_OUT

(mA)

A

= −1 dBm

RF_OUT

(mA)

A

= +2 dBm

RF_OUT

(mA)

A = +5 dBm

Supply

5 V Supply (I_VCOand I_CP)

74

3.3 V Supply (AI_DD, DI_DD, and

I_RFOUTx

)

Divide by 1

Divide by 2

Divide by 4

Divide by 8

Divide by 16

Divide by 32

Divide by 64

82.6

91.9

103.9

112.6

122.6

130.6

135.7

139.7

142.1

115.1

123.5

134.0

142.1

147.3

151.4

153.8

126.1

134.3

145.2

153.5

158.6

162.7

165.2

136.9

144.5

156.0

164.8

169.8

174.1

176.4

101.7

109.7

114.7

118.7

121.1

¹I_DDis the total current of I_VCO, I_CP, AI_DD, DI_DD, and I_RFOUTx

²RF_OUT

refers to RF_OUTA+/RF_OUTA−.

.

A

Rev. 0 | Page 18 of 38

Data Sheet

ADF5356

REGISTER MAPS

REGISTER 0

CONTROL

BITS

RESERVED

16-BIT INTEGER VALUE (INT)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2

DB1

DB0

0

AC1

PR1

N16 N15 N14 N13 N12 N11 N10

N9

N8

N7

N6

N5

N4

N3

N2

N1 C4(0) C3(0) C2(0) C1(0)

REGISTER 1

CONTROL

BITS

1

DBR

RESERVED

24-BIT MAIN FRACTIONAL VALUE (FRAC1)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

F24

F23

F22

F21

F20

F19

F18

F17

F16

F15

F14 F13 F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1 C4(0) C3(0) C2(0) C1(1)

REGISTER 2

CONTROL

BITS

1

14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_LSB) DBR

14-BIT AUXILIARY FRACTIONAL LSB VALUE (FRAC2_LSB) DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

F14

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

M14 M13 M12 M11 M10 M9

M8

M7

M6

M5

M4

M3

M2

M1 C4(0) C3(0) C2(1) C1(0)

REGISTER 3

CONTROL

BITS

1

24-BIT PHASE VALUE (PHASE)

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

SD1 PR1 PA1 P24

P23

P22

P21

P20

P19

P18

P17

P16

P15

P14 P13

P12

P11

P10

P9

P8

P7

P6

P5

P4

P3

P2

P1 C4(0) C3(0) C2(1) C1(1)

REGISTER 4

CURRENT

SETTING

CONTROL

BITS

1

DBR

1

RESERVED

MUXOUT

10-BIT R COUNTER

DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

M3

M2

M1

RD2 RD1 R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4 CP3 CP2 CP1

U6

U5

U4

U3

U2

U1 C4(0) C3(1) C2(0) C1(0)

REGISTER 5

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

C4(0) C3(1) C2(0) C1(1)

REGISTER 6

RF

OUTPUT A

POWER

RESERVED

RF DIVIDER

SELECT

CONTROL

BITS

1

RESERVED

CHARGE PUMP BLEED CURRENT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

BP1 BL10 BL9 D2 D1 C4(0) C3(1) C2(1) C1(0)

1

0

1

0

D9

D8

D7

D6

BL8 BL7 BL6 BL5 BL4 BL3 BL2 BL1

0

D5

D4

0

D3

1

2

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY A WRITE TO REGISTER 0.

DBB = DOUBLE BUFFERED BITS—BUFFERED BY A WRITE TO REGISTER 0 WHEN BIT DB14 OF REGISTER 4 IS HIGH.

Figure 36. Register Summary (Register 0 to Register 6)

Rev. 0 | Page 19 of 38

ADF5356

Data Sheet

REGISTER 7

LD

CYCLE

COUNT

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LD4

LD3 LD2 LD1 C4(0) C3(1) C2(1) C1(1)

LOL

0

LD5

LE2

1

LE1

REGISTER 8

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

1

0

1

0

C4(1)

C1(0)

C3(0) C2(0)

1

0

1

0

1

0

1

0

REGISTER 9

AUTOMATIC

LEVEL CALIBRATION

TIMEOUT

SYNTHESIZER

LOCK TIMEOUT

CONTROL

BITS

VCO BAND DIVISION

TIMEOUT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

VC8 VC7 VC6 VC5 VC4 VC3 VC2 VC1 TL10 TL9 TL8 TL7 TL6 TL5 TL4 TL3 TL2 TL1 AL5 AL4 AL3 AL2 AL1 SL5 SL4 SL3 SL2 SL1 C4(1) C3(0) C2(0) C1(1)

REGISTER 10

ADC

CLOCK DIVIDER

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)

0

1

0

REGISTER 11

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

C4(1) C3(0) C2(1) C1(1)

0

VH

0

1

0

1

0

REGISTER 12

CONTROL

BITS

PHASE RESYNC CLOCK VALUE

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

0

1

0

1

C4(1) C3(1) C2(0) C1(0)

REGISTER 13

CONTROL

BITS

1

14-BIT AUXILIARY FRACTIONAL MSB VALUE (FRAC2_MSB) DBR

14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_MSB) DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C4(1) C3(1) C2(0) C1(1)

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY A WRITE TO REGISTER 0.

1

Figure 37. Register Summary (Register 7 to Register 13)

Rev. 0 | Page 20 of 38

Data Sheet

ADF5356

CONTROL

BITS

RESERVED

16-BIT INTEGER VALUE (INT)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3

DB2

DB1

DB0

0

AC1

PR1

N16 N15 N14 N13 N12 N11 N10

N9

N8

N7

N6

N5

N1

N4

N3

N2

N1 C4(0) C3(0) C2(0) C1(0)

PRESCALER

N16 N15

....

N5

N4

N3

N2

INTEGER VALUE (INT)

0

1

4/5

8/9

0

.

0

.

0

.

0

.

....

0

.

1

.

0

.

0

1

.

0

.

1

0

.

0

1

.

1

0

.

0

1

0

.

0

1

0

.

NOT ALLOWED

....

NOT ALLOWED

23

24

....

VCO

AUTOCAL

AC1

1

0

1

0

1

65533

65534

65535

0

1

DISABLED

INT

= 75 WITH PRESCALER = 8/9

MIN

Figure 38. Register 0 Details

Prescaler Value

REGISTER 0

The dual modulus prescaler (P/P + 1), together with the INT,

FRACx, and MODx counters, determines the overall division

ratio from the VCO output to the PFD input. The PR1 bit

(Bit DB20) in Register 0 sets the prescaler value.

Control Bits

With C4 to C1 (Bits[DB3:DB0]) set to 0000, Register 0 is

programmed. Figure 38 shows the input data format for

programming this register.

Operating at CML levels, the prescaler takes the clock from the

VCO output and divides it down for the counters. It is based on

a synchronous 4/5 core. When the prescaler is set to 4/5, the

maximum RF frequency allowed is 6.0 GHz. Therefore, when

operating the ADF5356 above 6.0 GHz, the prescaler must be

set to 8/9. The prescaler limits the INT value; therefore, if P is

4/5, N_MINis 23, and if P is 8/9, N_MINis 75.

Reserved

Bits[DB31:DB22] are reserved and must be set to 0.

Automatic Calibration (AUTOCAL)

Write to Register 0 to enact (by default) the VCO automatic

calibration, and to choose the appropriate VCO and VCO subband.

Write 1 to the AC1 bit (Bit DB21) to enable the automatic

calibration, which is the recommended mode of operation.

16-Bit Integer Value

Set the AC1 bit (Bit DB21) to 0 to disable the automatic calibration,

which leaves the ADF5356 in the same band it is in when

Register 0 updates.

The 16 INT bits (Bits[DB19:DB4]) set the INT value, which

determines the integer part of the feedback division factor. The

INT value is used in Equation 3 (see the INT, FRACx, MODx,

and R Counter Relationship section). All integer values from 23

to 32,767 are allowed for the 4/5 prescaler. For the 8/9 prescaler,

the minimum integer value is 75, and the maximum value is

65,535

Disable the automatic calibration only for fixed frequency

applications, phase adjust applications, or very small (<10 kHz)

frequency jumps.

Toggling AUTOCAL is also required when changing frequency.

See the Frequency Update Sequence section for more information.

Rev. 0 | Page 21 of 38

ADF5356

Data Sheet

CONTROL

BITS

1

DBR

RESERVED

24-BIT MAIN FRACTIONAL VALUE (FRAC1)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

F24

F23

F22

F21

F20

F19

F18

F17

F16

F15

F14 F13 F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1 C4(0) C3(0) C2(0) C1(1)

F24 F23

....

F12

F1

MAIN FRACTIONAL VALUE (FRAC1)

0

.

1

0

.

1

....

0

1

.

0

1

0

1

0

1

.

0

1

0

1

2

3

.

16777212

16777213

16777214

16777215

1

DBR = DOUBLE BUFFERED REGISTER–BUFFERED BY A WRITE TO REGISTER 0.

Figure 39. Register 1 Details

CONTROL

BITS

1

14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_LSB) DBR

14-BIT AUXILIARY FRACTIONAL LSB VALUE (FRAC2_LSB) DBR

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

F14

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

M14 M13 M12 M11 M10 M9

M8

M7

M6

M5

M4

M3

M2

M1 C4(0) C3(0) C2(1) C1(0)

F14 F13

....

F2

F1

FRAC2_LSB WORD

M14 M13

....

M2

M1

MOD2_LSB VALUE

0

.

1

0

.

1

....

0

1

.

0

1

0

1

0

1

.

0

1

0

1

0

1

2

3

.

0

.

1

0

.

1

....

0

1

.

0

1

0

1

0

1

.

0

1

0

1

NOT ALLOWED

2

3

.

16380

16381

16382

16383

16381

16382

16383

1

DBR = DOUBLE BUFFERED REGISTER–BUFFERED BY A WRITE TO REGISTER 0.

Figure 40. Register 2 Details

REGISTER 1

REGISTER 2

Control Bits

With C4 to C1 (Bits[DB3:DB0]) set to 0001, Register 1 is

programmed. Figure 39 shows the input data format for

programming this register.

With C4 to C1 (Bits[DB3:DB0]) set to 0010, Register 2 is pro-

grammed. Figure 40 shows the input data format for programming

this register.

Reserved

14-Bit Auxiliary Fractional LSB Value (FRAC2_LSB)

Bits[DB31:DB28] are reserved and must be set to 0.

24-Bit Main Fractional Value

Use this value with the auxiliary fractional MSB value (Register 13,

Bits[DB31:DB18]) to generate the total auxiliary fractional value.

FRAC2 = (FRAC2_MSB × 2¹⁴) + FRAC2_LSB

The 24 FRAC1 bits (Bits[DB27:DB4]) set the numerator of the

fraction that is input to the Σ-Δ modulator. This fraction, together

with the INT value, specifies the new frequency channel that

the synthesizer locks to, as shown in the RF Synthesizer—A

Worked Example section. FRAC1 values from 0 to (MOD1 − 1)

cover channels over a frequency range equal to the PFD reference

frequency.

FRAC2 must be less than the MOD2 value programmed in

Register 2 and Register 13.

14-Bit Auxiliary Modulus LSB Value (MOD2_LSB)

Use this value with the auxiliary modulus MSB value (Register 13,

Bits[DB17:DB4]) to generate the total auxiliary modulus value.

MOD2 = (MOD2_MSB) × 2¹⁴+ MOD2_LSB

Use MOD2 to correct any residual error due to the main

fractional modulus.

Rev. 0 | Page 22 of 38

Data Sheet

ADF5356

CONTROL

BITS

1

DBR

24-BIT PHASE VALUE (PHASE)

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

SD1 PR1 PA1 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 C4(0) C3(0) C2(1) C1(1)

0

PHASE

ADJUST

PA1

P24 P23

....

P2

P1

PHASE VALUE (PHASE)

0

1

DISABLED

ENABLED

0

.

1

0

.

1

....

0

1

.

0

1

0

1

0

1

.

0

1

0

1

0

1

2

3

.

PHASE

RESYNC

PR1

16777212

16777213

16777214

16777215

0

1

DISABLED

ENABLED

SD LOAD

RESET

SD1

0

1

ON REGISTER0 UPDATE

DISABLED

1

DBR = DOUBLE BUFFERED REGISTER–BUFFERED BY A WRITE TO REGISTER 0.

Figure 41. Register 3

REGISTER 3

Control Bits

For resynchronization applications, enable the Σ-Δ modulator

load reset (SD load reset) in Register 3 by setting the SD1 bit (Bit

DB30) to 0.

With C4 to C1 (Bits[DB3:DB0]) set to 0011, Register 3 is

programmed. Figure 41 shows the input data format for

programming this register.

The phase of the RF output frequency can be adjusted in 24-bit

steps from 0° (0) to 360° (2²⁴− 1) relative to the resynchronization

phase. For phase adjustment applications, the phase is set by

P24 to P1 (Bits[DB27:DB1]).

Reserved

Bit DB31 is reserved and must be set to 0.

SD Load Reset

(Phase Value/16,777,216) × 360°

Practically, this setting means that repeatable adjustable phase

values can be achieved by using the resynchronization feature with

different phase values.

When writing to Register 0, the Σ-Δ modulator resets. For

applications in which the phase is continually adjusted, this

reset may not be desirable; therefore, in these cases, disable the

Σ-Δ reset by writing a 1 to the SD1 bit (Bit DB30).

Phase Adjustment

To adjust the relative output phase of the ADF5356 on each

Register 0 update, set the PA1 bit (Bit DB28) to 1. This feature

differs from the resynchronization feature in that it is useful when

adjustments to phase are made continually in an application.

For this function, disable the VCO automatic calibration by

setting the AC1 bit (Bit DB21) in Register 0 to 1, and disable the

Σ-Δ load reset by setting the SD1 bit (Bit DB30) in Register 3 to 1.

Phase Resynchronization

To use the phase resynchronization feature, the PR1 bit (Bit DB29)

must be set to 1. If unused, the bit can be programmed to 0.

The phase resynchronization clock value must also be used in

Register 12 to ensure that the resynchronization feature is applied

after the PLL settles to the final frequency. If the PLL has not

settled to the final frequency, phase resynchronization may not

function correctly. Resynchronization is useful in phased array

and beamforming applications. It ensures repeatability of the

output phase when programming the same frequency. In phase

critical applications that use frequencies requiring the output

divider (<3400 MHz), it is necessary to feed the N divider with

the divided VCO frequency as distinct from the fundamental

VCO frequency, which is achieved by programming the D9 bit

(Bit DB24) in Register 6 to 0, which ensures divided feedback to

the N divider.

24-Bit Phase Value

The phase of the RF output frequency can adjust in 24-bit steps,

from 0° (0) to 360° (2²⁴− 1). For phase adjust applications, the

phase is set by

(Phase Value/16,777,216) × 360°

When the phase value is programmed to Register 3, each

subsequent adjustment of Register 0 increments the phase by

the value in this equation.

Rev. 0 | Page 23 of 38

ADF5356

Data Sheet

CURRENT

SETTING

CONTROL

BITS

MUXOUT

10-BIT R COUNTER

DBR¹

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

0

M3

M2

M1 RD2 RD1 R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4 CP3 CP2 CP1 U6

U5

U4

U3

U2

U1

C3(1) C2(0) C1(0)

C4(0)

REFERENCE

RD2

COUNTER

RESET

DOUBLE BUFFERED

REGISTER 6, BITS[DB23:DB21]

U1

DOUBLER

D1

U6

0

REFIN

SINGLE

DIFF

0

1

DISABLED

ENABLED

0

1

DISABLED

ENABLED

0

1

DISABLED

1

ENABLED

RD1 REFERENCE DIVIDE BY 2

CP

I

(mA)

CP

U2

U5

LDP

1.8V

3.3V

THREE-STATE

CP4

0

CP3

0

CP2

0

CP1

0

5.1kꢀ

0.30

0.60

0.90

1.20

1.50

1.80

2.10

2.40

2.70

3.00

3.30

3.60

3.90

4.20

4.50

4.80

0

1

DISABLED

ENABLED

0

1

0

1

DISABLED

0

1

ENABLED

0

1

0

R10

R9

..........

R2

R1

R DIVIDER (R)

0

1

U4

0

PD POLARITY

NEGATIVE

POSITIVE

U3

POWER DOWN

0

.

0

.

..........

0

1

.

1

0

.

1

0

1

0

1

DISABLED

ENABLED

0

1

0

1

2

1

0

1

0

.

0

1

.

1

0

.

1

0

1

0

1

0

1

0

1

1020

1021

1022

1023

1

0

1

0

1

0

1

0

1

0

1

0

1

M3

0

M2

0

M1

0

OUTPUT

THREE-STATE OUTPUT

0

1

DV

DD

0

1

0

SD

GND

0

1

R DIVIDER OUTPUT

N DIVIDER OUTPUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

RESERVED

1

0

1

0

1

0

1

¹DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY A WRITE TO REGISTER 0.

Figure 42. Register 4 Details

both the rising and falling edges of the reference frequency become

active edges at the PFD input.

REGISTER 4

Control Bits

The maximum allowable reference frequency when the doubler

is enabled is 80 MHz.

With C4 to C1 (Bits[DB3:DB0]) set to 0100, Register 4 is

programmed. Figure 42 shows the input data format for

programming this register.

RDIV2

Reserved

Setting the RD1 bit (Bit DB25) to 1 inserts a divide by 2, toggle

flip flop between the R counter and PFD, which extends the

maximum reference frequency input rate. This function

provides a 50% duty cycle signal at the PFD input.

Bits[DB31:DB30] are reserved and must be set to 0.

MUXOUT

The on-chip multiplexer (MUXOUT) is controlled by

Bits[DB29:DB27]. For additional details, see Figure 42.

10-Bit R Counter

The 10-bit R counter divides the reference frequency input,

f_REFIN, to produce the reference clock to the PFD. Division ratios

range from 1 to 1023.

When changing the frequency, that is, writing Register 0,

MUXOUT must not be set to the N divider output or R divider

output. If needed, enable these functions after locking to the new

frequency.

Double Buffer

The D1 bit (Bit DB14) enables or disables double buffering of

the RF divider select bits (Bits[DB23:DB21]) in Register 6. The

Program Modes section explains how double buffering works.

Reference Doubler

Setting the RD2 bit (Bit DB26) to 0 feeds the reference frequency

signal directly to the 10-bit R counter, disabling the doubler.

Setting this bit to 1 multiplies the reference frequency by a factor

of 2 before feeding it into the 10-bit R counter. When the doubler

is disabled, the f_REFINfalling edge is the active edge at the PFD

input to the fractional synthesizer. When the doubler is enabled,

Charge Pump Current Setting

The CP4 to CP1 bits (Bits[DB13:DB10]) set the charge pump

current. Set this value to the charge pump current that the loop

filter is designed with (see Figure 42). For the lowest spurs, the

0.90 mA setting is recommended.

Rev. 0 | Page 24 of 38

Data Sheet

ADF5356

When power-down activates, the following events occur:

Reference Mode

The ADF5356 permits use of either differential or single-ended

reference sources.



The synthesizer counters are forced to their load state

conditions.



The VCO powers down.

For optimum integer boundary spur performance, it is recom-

mended to use the single-ended setting for all references up to

250 MHz (even if using a differential reference signal). Use the

differential setting for reference frequencies above 250 MHz.

The charge pump is forced into three-state mode.

The digital lock detect circuitry resets.

The RF_OUTA+/RF_OUTA− and RF_OUTB output stages are

disabled.

The input registers remain active and capable of loading

and latching data.

Mux Logic



To assist with logic compatibility, MUXOUT is programmable to

two logic levels. Set the U5 bit (Bit DB8) to 0 to select 1.8 V

logic, and set it to 1 to select 3.3 V logic.

Charge Pump Three-State

Setting the U2 bit (Bit DB5) to 1 puts the charge pump into

three-state mode. Set DB5 to 0 for normal operation.

Phase Detector Polarity

The U4 bit (Bit DB7) sets the phase detector polarity. When a

passive loop filter or a noninverting active loop filter is used, set

DB7 to 1 (positive). If an active filter with an inverting characteris-

tic is used, set this bit to 0 (negative).

Counter Reset

The U1 bit (Bit DB4) resets the R counter, N counter, and VCO

band select of the ADF5356. When DB4 is set to 1, the RF

synthesizer N counter, R counter, and VCO band select are reset.

For normal operation, set DB4 to 0.

Power-Down

The U3 bit (Bit DB6) sets the programmable power-down mode.

Setting DB6 to 1 performs a power-down. Setting DB6 to 0 returns

the synthesizer to normal operation. In software power-down

mode, the ADF5356 retains all information in its registers. The

register contents are lost only when the supply voltages are

removed.

REGISTER 5

The bits in Register 5 are reserved and must be programmed as

described in Figure 43, using a hexadecimal word of 0x00800025.

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C4(0) C3(1) C2(0) C1(1)

0

1

0

1

0

Figure 43. Register 5 Details (0x00800025)

Rev. 0 | Page 25 of 38

ADF5356

Data Sheet

RF

OUTPUT A

POWER

RESERVED

RF DIVIDER

CONTROL

BITS

1

RESERVED

SELECT

CHARGE PUMP BLEED CURRENT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

BP1 BL10 BL9

1

0

1

0

D2

D1 C4(0) C3(1) C2(1) C1(0)

D9

D8

D7

D6

BL8 BL7 BL6 BL5 BL4 BL3 BL2 BL1

0

D5 D4

0

D3

RF OUTPUT A

POWER

D2

D1

0

1

0

1

0

1

–4dBm

–1dBm

+2dBm

+5dBm

FEEDBACK

SELECT

D9

RF OUTPUT A

ENABLE

0

1

DIVIDED

D3

MUTE TILL

LOCK DETECT

D5

FUNDAMENTAL

0

1

DISABLED

ENABLED

0

1

MUTE DISABLED

MUTE ENABLED

NEGATIVE BLEED

BL9

D8

D7

D6

RF DIVIDER SELECT

0

1

DISABLED

ENABLED

0

1

0

1

0

1

0

1

0

1

0

1

0

÷1

÷2

÷4

÷8

GATED BLEED

BL10

÷16

÷32

÷64

0

1

DISABLED

ENABLED

RF OUTPUT B

ENABLE

D4

BLEED POLARITY

BP1

0

1

ENABLED

DISABLED

BL8

BL7

..........

BL2

BL1 BLEED CURRENT

0

1

NEGATIVE

POSITIVE

0

.

0

.

..........

0

1

.

1

0

.

1

2

.

(3.75µA)

(7.5µA)

.

1

0

1

0

1

0

1

252 (945µA)

253 (948.75µA)

254 (952.5µA)

255 (956.25µA)

1

BITS[DB23:DB21] ARE BUFFERED BY A WRITE TO REGISTER 0 WHEN THE DOUBLE BUFFER BIT, BIT DB14 OF REGISTER 4, IS ENABLED.

Figure 44. Register 6 Details

Do not use negative bleed when operating in integer N mode,

that is, FRAC1 = FRAC2 = 0. Do not use negative bleed for f_PFD

values greater than 100 MHz.

REGISTER 6

Control Bits

With C4 to C1 (Bits[DB3:DB0]) set to 0110, Register 6 is

programmed. Figure 44 shows the input data format for

programming this register.

Reserved

Bits[DB28:DB25] are reserved and must be set to 1010.

Bit DB12 is reserved and must be set to 0. Bits[DB9:DB7] are

reserved and must be set to 0.

Bleed Polarity

BP1 (Bit DB31) sets the polarity of the charge pump bleed current.

Feedback Select

Gated Bleed

D9 (Bit DB24) selects the feedback from the output of the VCO

to the N counter. When D9 is set to 1, the signal is taken

directly from the VCO. When this bit is set to 0, the signal is

taken from the output of the output dividers. The dividers

enable coverage of the wide frequency band (53.125 MHz to

6800 MHz). When the divider is enabled and the feedback

signal is taken from the output, the RF output signals of two

separately configured PLLs are in phase. Divided feedback is

useful in some applications where the positive interference of

signals is required to increase the power.

Bleed currents can be used for improving phase noise and spurs;

however, due to a potential impact on lock time, the gated bleed

bit, BL10 (Bit DB30), if set to 1, ensures bleed currents are not

switched on until the digital lock detect asserts logic high. Note

that this function requires the digital lock detect to be enabled

in Register 4.

Negative Bleed

Use of constant negative bleed is recommended for most

fractional-N applications because it improves the linearity of

the charge pump, leading to lower noise and spurious signals than

leaving it off. To enable negative bleed, write 1 to BL9 (Bit DB29),

and to disable negative bleed, write 0 to BL9.

RF Divider Select

D8 to D6 (Bits[DB23:DB21]) select the value of the RF output

divider (see Figure 44).

Rev. 0 | Page 26 of 38

Data Sheet

ADF5356

Charge Pump Bleed Current

Mute Till Lock Detect

BL8 to BL1 (Bits[DB20:DB13]) control the level of the bleed

current added to the charge pump output. This current

optimizes the phase noise and spurious levels from the device.

When D5 (Bit DB11) is set to 1, the supply current to the RF

output stage is shut down until the device achieves lock, as

determined by the digital lock detect circuitry.

Calculate the optimal bleed setting using the following

equation:

RF Output B Enable

D4 (Bit DB10) enables or disables RF Output B (RF_OUTB). If

DB10 is set to 0, RF Output B is enabled. If DB10 is set to 1,

RF Output B is disabled.

Bleed Value = floor(24 × (f_PFD/61.44 MHz) × (I_CP/0.9 mA))

where:

RF Output A Enable

Bleed Value is the value programmed to Bits[DB20:DB13].

floor() is a function to round down to the nearest integer value.

D3 (Bit DB6) enables or disables RF Output A (RF_OUTA+/RF_OUTA−).

If DB3 is set to 0, RF Output A is disabled. If DB6 is set to 1, RF

Output A is enabled.

f

I

_PFDis the PFD frequency.

_CPis the value of charge pump current setting, Bits[DB13:DB10] of

Register 4.

RF Output A Power

If f_PFD> 100 MHz, disable the bleed current using Bit DB29.

D2 and D1 (Bits[DB5:DB4]) set the value of the RF Output A

(RF_OUTA+/RF_OUTA−) power level (see Figure 44).

Rev. 0 | Page 27 of 38

ADF5356

Data Sheet

LD

CYCLE

COUNT

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LD4

LD3 LD2 LD1 C4(0) C3(1) C2(1) C1(1)

LOL

0

LD5

LE2

1

LE1

LD1 LOCK DETECT MODE

LE1 LE SYNCHRONIZATION

0

1

FRACTIONAL-N

DISABLED

0

1

INTEGER-N (2.9ns)

LE SYNCED TO REF

IN

LD3

0

LD2

0

FRACTIONAL-N LD PRECISION

LE SEL SYNC EDGE

5.0ns

6.0ns

8.0ns

12.0ns

LE2

0

1

0

1

LE SYNC TO REFERENCE FALLING EDGE

LE SYNC TO REFERENCE RISING EDGE

1

0

1

LOL LOSS OF LOCK MODE

DISABLED

ENABLED

0

1

LD5

0

LD4

LOCK DETECT CYCLE COUNT

0

1

0

1

1024

2048

4096

8192

0

1

Figure 45. Register 7 Details

Fractional-N Lock Detect (LD) Cycle Count

REGISTER 7

LD5 and LD4 (Bits[DB9:DB8]) set the number of consecutive

cycles counted by the lock detect circuitry before asserting lock

detect high (see Figure 45 for details).

Control Bits

With C4 to C1 (Bits[DB3:DB0]) set to 0111, Register 7 is

programmed. Figure 45 shows the input data format for

programming this register.

Loss of Lock (LOL) Mode

Set the LOL mode bit (Bit DB7) to 1 when the application is a fixed

frequency application in which the reference (REF_INsignal) is likely

to be removed, such as a clocking application. The standard lock

detect circuit assumes that the REF_INsignal is always present;

however, this may not be the case with clocking applications. To

enable this functionality, set Bit DB7 to 1.

Reserved

Bits[DB31:DB28] are reserved and must be set to 0. Bit DB26 is

reserved and must be set to 1. Bits[DB24:DB10] are reserved

and must be set to 0.

LE Select Synchronization Edge

LE2 (Bit DB27) allows selection of the synchronization load

enable (LE) edge to the falling or rising edge of the reference

clock, which is useful for applications that require synchronization

to a common reference edge (see Figure 45). To use this bit, LE

synchronization (Bit DB25) must be set to 1.

Fractional-N Lock Detect (LD) Precision

LD3 and LD2 (Bits[DB6:DB5]) set the precision of the lock detect

circuitry in fractional-N mode. LD precision is available at 5.0 ns,

6.0 ns, 8.0 ns, or 12.0 ns. If bleed currents are used, use 12.0 ns.

Lock Detect (LD) Mode

LE Synchronization

When LD1 (Bit DB4) is set to 0, lock detect precision is set by

fractional-N lock detect precision as described in the Fractional-N

Lock Detect (LD) Precision section. If LD1 (Bit DB4) is set to 1,

lock detect precision is 2.9 ns long, which is more appropriate

for integer N applications.

When set to 1, Bit DB25 ensures that the LE edge is synchronized

internally with the rising edge of reference input frequency.

This synchronization prevents the rare event of the reference

and RF dividers loading at the same time as a falling edge of the

reference frequency, which can lead to longer lock times.

Rev. 0 | Page 28 of 38

Data Sheet

ADF5356

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

1

0

1

0

1

0

1

0

C4(1)

C1(0)

C3(0) C2(0)

1

0

1

0

1

0

1

0

Figure 46. Register 8 Details (0x15596568)

AUTOMATIC

LEVEL CALIBRATION

TIMEOUT

SYNTHESIZER

LOCK TIMEOUT

CONTROL

BITS

VCO BAND DIVISION

TIMEOUT

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

VC8 VC7 VC6

VC5 VC4 VC3 VC2 VC1 TL10 TL9

TL8

TL7

TL6

TL5

TL4

TL3

TL2

TL1 AL5 AL4

AL3 AL2 AL1 SL5 SL4 SL3 SL2 SL1 C4(1) C3(0) C2(0) C1(1)

SL5

SL4

..........

SL2

SL1 SLC WAIT

0

.

0

.

..........

0

1

.

1

0

.

1

TL10

TL9

..........

TL2

TL1 TIMEOUT

2

0

.

0

.

..........

0

1

.

1

0

.

1

.

2

.

1

0

1

0

1

0

1

28

29

30

31

.

1

0

1

0

1

0

1

1020

1021

1022

1023

AL5

AL4

..........

AL2

AL1 ALC WAIT

VC8

VC7

..........

VC2

VC1 VCO BAND DIV

0

.

0

.

..........

0

1

.

1

0

.

1

0

.

0

.

..........

0

1

.

1

0

.

1

2

.

1

0

1

0

1

0

1

28

29

30

31

1

0

1

0

1

0

1

252

253

254

255

Figure 47. Register 9 Details

REGISTER 8

Timeout

The bits in this register are reserved and must be programmed as

shown in Figure 46, using a hexadecimal word of 0x15596568.

TL10 to TL1 (Bits[DB23:DB14]) set the timeout value for the

VCO band select.

REGISTER 9

Automatic Level Calibration (ALC) Timeout

For a worked example and more information, see the PLL Lock

Time section.

AL5 to AL1 (Bits[DB13:DB9]) set the timer value used for the

automatic level calibration of the VCO. This function combines

the PFD frequency, the timeout variable, and the ALC wait

variable. Choose the ALC such that the following equation is

always greater than 50 μs:

Control Bits

With C4 to C1 (Bits[DB3:DB0]) set to 1001, Register 9 is

programmed. Figure 47 shows the input data format for

programming this register.

ALC Wait > (50 μs × f_PFD)/Timeout

VCO Band Division

Synthesizer Lock Timeout

VC8 to VC1 (Bits[DB31:DB24]) set the value of the VCO band

division clock. Determine the value of this clock by

SL5 to SL1 (Bits[DB8:DB4]) set the synthesizer lock timeout

value. This value allows the V_TUNEforce to settle on the V_TUNEpin.

The value must be 20 μs. Calculate the value using the following

equation:

VCO Band Division = ceiling(f_PFD/1,600,000)

where ceiling() is a function that rounds up to the nearest

integer.

Synthesizer Lock Timeout > (20 μs × f_PFD)/Timeout

Rev. 0 | Page 29 of 38

ADF5356

Data Sheet

ADC

CLOCK DIVIDER

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)

0

1

0

AE1 ADC

0

1

DISABLED

ENABLED

AE2 ADC CONVERSION

0

1

DISABLED

ENABLED

AD8

AD7

..........

AD2 AD1 ADC CLK DIV

0

.

0

.

..........

0

1

.

1

0

.

1

2

.

1

0

1

0

1

0

1

252

253

254

255

Figure 48. Register 10 Details

AD8 to AD1 (Bits[DB13:DB6]) set the value of this divider. On

power-up, the R counter is not programmed; however, in these

power-up cases, it defaults to R = 1.

REGISTER 10

Control Bits

With C4 to C1 (Bits[DB3:DB0]) set to 1010, Register 10 is

programmed. Figure 48 shows the input data format for

programming this register.

Choose the value such that

ADC_CLK_DIV = ceiling(((f_PFD/100,000) − 2)/4)

Reserved

For example, for f_PFD= 61.44 MHz, set ALC_CLK_DIV = 154

so that the ADC clock frequency is 99.417 kHz.

Bits[DB31:DB14] are reserved. Bits[DB23:DB22] must be set to

11, and all other bits in this range must be set to 0.

If ADC_CLK_DIV is greater than 255, set it to 255.

ADC Clock Divider (ADC_CLK_DIV)

ADC Conversion Enable

An on-board analog-to-digital converter (ADC) determines the

V_TUNEsetpoint relative to the ambient temperature of the

ADF5356 environment. The ADC ensures that the initial tuning

voltage in any application is chosen correctly to avoid any

temperature drift issues.

AE2 (Bit DB5) ensures that the ADC performs a conversion

when a write to Register 10 is performed. It is recommended to

enable this mode.

ADC Enable

AE1 (Bit DB4), when set to 1, powers up the ADC for the

temperature dependent V_TUNEcalibration. It is recommended to

always use this function.

The ADC uses a clock that is equal to the output of the R counter

(or the PFD frequency) divided by ADC_CLK_DIV.

Rev. 0 | Page 30 of 38

Data Sheet

ADF5356

CONTROL

BITS

RESERVED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0

1

0

C4(1) C3(0) C2(1) C1(1)

0

VH

0

1

0

1

0

VCO BAND HOLD

VH

0

1

NORMAL OPERATION

VCO BAND HOLD

Figure 49. Register 11 Details

CONTROL

BITS

RESERVED

PHASE RESYNC CLOCK VALUE

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P13 P12

P11 P10

P9

P8

P7

P6

P5

P4

P3

P2

P1

0

1

0

1

P20 P19 P18 P17 P16

C4(1) C3(1) C2(0) C1(0)

P15

P14

P20

0

.

P19

...

P5

0

.

P4

0

.

P3

P2

0

1

.

P1

RESYNC CLOCK

0

.

0

.

0

1

0

.

NOT ALLOWED

1

2

...

0

.

0

.

1

.

0

1

.

1

0

.

1

0

.

0

1

0

.

22

23

24

...

1

0

1

0

1

65533

65534

1048575

Figure 50. Register 12 Details

REGISTER 11

Control Bits

REGISTER 12

Control Bits

With C4 to C1 (Bits[DB3:DB0]) set to 1011, Register 11 is

programmed. Figure 49 shows the input data format for

programming this register.

With C4 to C1 (Bits[DB3:DB0]) set to 1100, Register 12 is

programmed. Figure 50 shows the input data format for

programming this register.

Reserved

Phase Resynchronization Clock Value

Bits[DB31:DB25] are reserved and must be set to 0. Bit DB22,

Bit DB21, Bit DB16, and Bit DB13 must be set to 1, and all other

bits in this range (Bits[DB23:DB4]) must be set to 0.

P20 to P1 (Bits[DB31:DB12]) set the timeout counter for

activation of the phase resynchronization. This value must be

set such that a resynchronization occurs immediately after (and

not before) the PLL has achieved lock, after reprogramming.

VCO Band Hold

Calculate the timeout value using the following equation:

VH (Bit DB24), when set to 1, prevents a reset of the VCO core,

band, and bias during a counter reset. VCO band hold is

required for applications that use external PLLs.

Timeout Value = Phase Resynchronization Clock Value/f_PFD

When not using phase resynchronization, set these bits to 1 for

normal operation.

Reserved

Bits [DB11:DB4] are reserved. Bit DB11 and Bit DB9 must be

set to 0, and all other bits in this range must be set to 1.

Rev. 0 | Page 31 of 38

ADF5356

Data Sheet

CONTROL

BITS

14-BIT AUXILIARY FRACTIONAL MSB VALUE (FRAC2_MSB) DBR ¹

14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_MSB) DBR¹

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

M14 M13 M12 M11 M10 M9

M8

M7

M6

M5

M4

M3

M2

M1

F14

F13

F12

F11

F10

F9

F8

F7

F6

F5

F4

F3

F2

F1

C3(1) C2(0) C1(1)

C4(1)

M14 M13 .......... M2

M1

0

1

0

1

.

MOD2_MSB VALUE

0

F14

F13

.......... F2

F1

0

1

0

1

.

FRAC2_MSB WORD

0

.

0

.

..........

.........

0

1

.

0

.

0

.

..........

.........

0

1

.

0

1

2

3

.

1

0

1

0

1

0

1

16380

16381

16382

16383

1

0

1

0

1

0

1

16381

16382

16383

1

DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY A WRITE TO REGISTER 0.

Figure 51. Register 13 Details

11. Register 3.

12. Register 2.

13. Register 1.

REGISTER 13

Control Bits

With C4 to C1 (Bits[DB3:DB0]) set to 1101, Register 13 is

programmed. Figure 51 shows the input data format for

programming this register.

14. Ensure that >16 ADC clock cycles elapse between the write

of Register 10 and Register 0. For example, if ADC clock =

99.417 kHz, wait 16/99,417 sec = 161 ꢀs. See the Register 10

section for more information.

14-Bit Auxiliary Fractional MSB Value (FRAC2_MSB)

15. Register 0.

This value is used with the auxiliary fractional LSB value

(Register 2, Bits[DB31:DB18]) to generate the total auxiliary

fractional FRAC2 value.

For f_PFD> 75 MHz (initially lock with halved f_PFD), use the

following sequence:

FRAC2 = (FRAC2_MSB × 2¹⁴) + FRAC2_LSB

1. Register 13 (for halved f_PFD).

These bits can be set to all zeros to ensure software

compatibility with the ADF5355.

2. Register 12.

3. Register 11.

4. Register 10.

5. Register 9.

6. Register 8.

7. Register 7.

8. Register 6 (bleed current setting using the desired f_PFD).

9. Register 5.

14-Bit Auxiliary Modulus MSB Value (MOD2_MSB)

This value is used with the auxiliary fractional MSB value

(Register 2, Bits[DB17:DB4]) to generate the total auxiliary

modulus MOD2 value.

MOD2 = (MOD2_MSB × 2¹⁴) + MOD2_LSB

10. Register 4 (with the R divider doubled to halve f_PFD).

11. Register 3.

12. Register 2 (for halved f_PFD).

REGISTER INITIALIZATION SEQUENCE

At initial power-up, after the correct application of voltages to

the supply pins, the ADF5356 registers must be programmed in

sequence. For f ≤ 75 MHz, use the following sequence:

13. Register 1 (for halved f_PFD).

14. Ensure that >16 ADC clock cycles elapse between the write

of Register 10 and Register 0. For example, if ADC clock =

99.417 kHz, wait 16/99,417 sec = 161 ꢀs. See the Register 10

section for more information.

15. Register 0 (for halved f_PFD; autocalibration enabled).

16. Register 13 (for the desired f_PFD).

17. Register 4 (with the R divider set for the desired f_PFD).

18. Register 2 (for the desired f_PFD).

19. Register 1 (for the desired f_PFD).

20. Register 0 (for the desired f_PFD; autocalibration disabled).

1. Register 13.

2. Register 12.

3. Register 11.

4. Register 10.

5. Register 9.

6. Register 8.

7. Register 7.

8. Register 6.

9. Register 5.

10. Register 4.

Rev. 0 | Page 32 of 38

Data Sheet

ADF5356

FREQUENCY UPDATE SEQUENCE

f

_PFD= f_REFIN× ((1 + D)/(R × (1 + T)))

where:

_REFINis the reference input frequency.

(8)

Frequency updates require updating the auxiliary modulator

(FRAC2/MOD2) in Register 2 and Register 13, the fractional value

(FRAC1) in Register 1, and the integer value (INT) in Register 0.

It is recommended to perform a temperature dependent V_TUNE

f

D is the reference doubler bit.

R is the f_REFINreference division factor.

T is the reference divide by 2 bit (0 or 1).

calibration by updating Register 10 first. Therefore, for f_PFD

75 MHz, the sequence must be as follows:

≤

1. Register 13.

2. Register 10.

3. Register 2.

4. Register 1.

5. Ensure that >16 ADC clock cycles elapse between the write

of Register 10 and Register 0. For example, if ADC clock =

99.417 kHz, wait 16/99,417 sec = 161 ꢀs. See the Register 10

section for more information.

For example, in a universal mobile telecommunication system

(UMTS) where a 2112.8 MHz RF output frequency (f_RFOUT) is

required, a 122.88 MHz reference frequency input (f_REFIN) is availa-

ble. Note that the ADF5356 VCO operates in the frequency range

of 3400 MHz to 6800 MHz. Therefore, the RF divider of 2 must be

used (VCO frequency = 4225.6 MHz, RF_OUT= VCO frequency/RF

divider = 4225.6 MHz/2 = 2112.8 MHz).

The feedback path is also important. In this example, the VCO

output is fed back before the output divider (see Figure 52). In

this example, the 122.88 MHz reference signal is divided by 2 to

generate an f_PFDof 61.44 MHz. The desired channel spacing is

200 kHz.

6. Register 0.

For f_PFD> 75 MHz (initially lock with halved f_PFD), the sequence

must be as follows:

1. Register 13 (for halved f_PFD).

2. Register 10.

3. Register 4 (with the R divider doubled to halve f_PFD).

4. Register 2 (for halved f_PFD).

f_PFD

RF

OUT

PFD

VCO

÷2

5. Register 1 (for halved f_PFD).

N

6. Ensure that >16 ADC clock cycles elapse between the write

of Register 10 and Register 0. For example, if ADC clock =

99.417 kHz, wait 16/99,417 sec = 161 ꢀs. See the Register 10

section for more information.

DIVIDER

Figure 52. Loop Closed Before Output Divider

The worked example is as follows:

7. Register 0 (for halved f_PFD; autocalibration enabled).

8. Register 13 (for the desired f_PFD).

N = VCO_OUT/f_PFD= 4225.6 MHz/61.44 MHz =

68.7760416666666667

9. Register 4 (with the R divider doubled to halve f_PFD

10. Register 2 (for the desired f_PFD).

11. Register 1 (for the desired f_PFD).

12. Register 0 (for desired f_PFD; autocalibration disabled).

)

INT = int(VCO frequency/f_PFD) = 68

where int() is a function indicating the integer result.

FRAC = 0.7760416666666667

MOD1 = 16,777,216

The frequency change occurs on the write to Register 0.

FRAC1 = int(MOD1 × FRAC) = 13,019,818

Remainder = 0.6666666667 or 2/3

RF SYNTHESIZER—A WORKED EXAMPLE

Use the following equations to program the ADF5356 synthesizer:

MOD2 = f_PFD/GCD(f_PFD, f_CHSP) =

61.44 MHz/GCD(61.44 MHz, 200 kHz) = 1536

FRAC2

MOD2

MOD1

FRAC1 

 INT 





f_PFD



/RF Divider

(7)

RFOUT

FRAC2 = Remainder × 1536 = 1024

where:

From Equation 8,

f

_RFOUTis the RF output frequency.

f

_PFD= (122.88 MHz × (1 + 0)/2) = 61.44 MHz

(9)

INT is the integer division factor.

2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +

FRAC2/MOD2)/2²⁴))/2

FRAC1 is the fractionality.

(10)

FRAC2 is the auxiliary fractionality (FRAC2 = (FRAC2_MSB ×

2¹⁴) + FRAC2_LSB).

where:

INT = 68.

FRAC1 = 13,019,818.

FRAC2 = 1024.

MOD2 = 1536.

RF Divider = 2.

MOD2 is the auxiliary modulus (MOD2 = (MOD2_MSB × 2¹⁴) +

MOD2_LSB).

MOD1 is the fixed 24-bit modulus.

RF Divider is the output divider that divides down the VCO

frequency.

Rev. 0 | Page 33 of 38

ADF5356

Data Sheet

Lock Time—A Worked Example

REFERENCE DOUBLER AND REFERENCE DIVIDER

Assume that f_PFD= 61.44 MHz,

The on-chip reference doubler allows the input reference signal

to be doubled. The doubler is useful for increasing the PFD

comparison frequency. To improve the noise performance of

the system, increase the PFD frequency. Doubling the PFD

frequency typically improves noise performance by 3 dB.

VCO Band Div = ceiling(f_PFD/1,600,000) = 39

By combining

ALC Wait > (50 μs × f_PFD)/Timeout

Synthesizer Lock Timeout > (20 μs × f_PFD)/Timeout

The reference divide by 2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency.

It is found that

SPURIOUS OPTIMIZATION AND FAST LOCK

ALC Wait = 2.5 × Synthesizer Lock Timeout

Narrow loop bandwidths can filter unwanted spurious signals;

however, these bandwidths typically have a long lock time. A

wider loop bandwidth achieves faster lock times but may lead

to increased spurious signals inside the loop bandwidth.

The ALC wait and synthesizer lock timeout values must be set

to fulfill this equation. Both values are five bits wide; therefore,

the maximum value for either is 31. There are several suitable

values.

OPTIMIZING JITTER

The following values meet the criteria:

ALC Wait = 30

For the lowest jitter applications, use the highest possible PFD

frequency to minimize the contribution of in-band noise from

the PLL. Set the PLL filter bandwidth such that the in-band noise

of the PLL intersects with the open-loop noise of the VCO,

minimizing the contribution of both to the overall noise.

Synthesizer Lock Timeout = 12

Finally, rearrange as follows:

ALC wait > (50 μs × f_PFD)/Timeout

Timeout = ceiling((f_PFD× 50 μs)/ALC Wait)

Timeout = ceiling((61.44 MHz × 50 μs)/30) = 103

Synthesizer Lock Timeout

Use the ADIsimPLL design tool for this task.

SPUR MECHANISMS

This section describes the two different spur mechanisms that

arise with a fractional-N synthesizer and methods to minimize

them in the ADF5356.

The synthesizer lock timeout ensures that the VCO calibration

digital-to-analog (DAC), which forces V_TUNE, settles to a steady

value for the band select circuitry.

Integer Boundary Spurs

One mechanism for fractional spur creation is the interactions

between the RF VCO frequency and the reference frequency.

When these frequencies are not integer related (the purpose of a

fractional-N synthesizer), spur sidebands appear on the VCO

output spectrum at an offset frequency that corresponds to the

beat note or the difference in frequency between an integer

multiple of the reference and the VCO frequency. These spurs

are attenuated by the loop filter and are more noticeable on

channels close to integer multiples of the reference where the

difference frequency can be inside the loop bandwidth (thus

the name, integer boundary spurs).

The timeout and synthesizer lock timeout variables programmed

in Register 9 select the length of time the DAC is allowed to

settle to the final voltage, before the VCO calibration process

continues to the next phase, which is VCO band selection. The

PFD frequency is the clock for this logic, and the duration is set by

Timeout  Synthesize r Lock Timeout

f_PFD

The calculated time must be equal to or greater than 20 μs.

VCO Band Selection

Use the PFD frequency again as the clock for the band selection

process. Calculate this value by

Reference Spurs

Reference spurs are generally not a problem in fractional-N

synthesizers because the reference offset is far outside the loop

bandwidth. However, any reference feedthrough mechanism

that bypasses the loop can cause a problem. Feedthrough of low

levels of on-chip reference switching noise, through the

prescaler back to the VCO, can result in reference spur levels

as high as −85 dBc.

f

_PFD/(VCO Band Selection × 16) < 100 kHz

The band selection takes 11 cycles of the previously calculated

value. Calculate the duration by

11 × (VCO Band Selection × 16)/f_PFD

Automatic Level Calibration Timeout

Use the automatic level calibration (ALC) function to choose

the correct bias current in the ADF5356 VCO core. Calculate

the time taken by

PLL LOCK TIME

The PLL lock time divides into a number of settings. All of

these settings are modeled in the ADIsimPLL design tool.

30 × ALC Wait × Timeout/f_PFD

Much faster lock times than those detailed in this data sheet are

possible; contact Analog Devices, Inc., for more information.

Rev. 0 | Page 34 of 38

Data Sheet

ADF5356

PLL Low-Pass Filter Settling Time

The total lock time for changing frequencies is the sum of the

four separate times (synthesizer lock, VCO band selection, ALC

timeout, and PLL settling time) and is modeled in the ADIsimPLL

design tool.

The time taken for the loop to settle is inversely proportional to

the low-pass filter bandwidth. The settling time is also modeled

in the ADIsimPLL design tool.

Rev. 0 | Page 35 of 38

ADF5356

Data Sheet

APPLICATIONS INFORMATION

large as the exposed pad. On the PCB, there must be a minimum

clearance of 0.25 mm between the thermal pad and the inner

edges of the pad pattern. This clearance ensures the avoidance

of shorting.

POWER SUPPLIES

The ADF5356 contains four multiband VCOs that cover an

octave range of frequencies. To ensure the best performance, it is

vital to connect a low noise regulator, such as the ADM7150.

Connect the same regulator to the V_VCO, V_REGVCO, and V_Ppins.

To improve the thermal performance of the package, use thermal

vias on the PCB thermal pad. If vias are used, incorporate them

into the thermal pad at the 1.2 mm pitch grid. The via diameter

must be between 0.3 mm and 0.33 mm, and the via barrel must

be plated with 1 oz. of copper to plug the via.

For the 3.3 V supply pins, use one or two ADM7150 regulators,

one for the DV_DDand AV_DDsupplies and one for V_RF. Figure 53

shows the recommended connections.

PCB DESIGN GUIDELINES FOR A CHIP SCALE

PACKAGE

For a microwave PLL and VCO synthesizer, such as the ADF5356,

take care with the board stackup and layout. Do not consider

using FR4 material because it is too lossy above 3 GHz. Instead,

Rogers 4350, Rogers 4003, or Rogers 3003 dielectric material is

suitable.

The lands on the 32-lead, lead frame chip scale package are

rectangular. The PCB pad for these lands must be 0.1 mm

longer than the package land length and 0.05 mm wider than

the package land width. Center each land on the pad to

maximize the solder joint size.

Take care with the RF output traces to minimize discontinuities

and ensure the best signal integrity. Via placement and grounding

are critical.

The bottom of the chip scale package has a central exposed

thermal pad. The thermal pad on the PCB must be at least as

V

IN

= 6.0V

V

= 3.3V

OUT

100nF

VIN

EN

VOUT

ADM7150

C

IN

1µF

C

ON

1µF

LOCK

DETECT

OFF

C

REF

BYP

17

6

27

5

16

4

26

10

32

_REG2 C_REG1

MUXOUT

25

30

C

BYP

1µF

VREG

REF_SENSE

V_VCO

DV_DDAV_DDAV

V_RF

C

_DDCE PDB_RF

V_P

1nF

10pF

REG

10µF

FREF_IN

GND

29

REF_IN

A

RF_OUT

B

14

100ꢀ

V_OUT

REF_INB

28

1nF

7.5nH

1

2

3

CLK

DATA

LE

1nF

11

12

RF_OUTA+

RF_OUTA–

ADF5356

V

IN

= 6.0V

V

= 5.0V

OUT

VIN

VOUT

REF

V_TUNE20

CP_OUT

C

IN

1µF

C

OUT

1µF

430ꢀ

ADM7150

ON

22 NIC

7

OFF

EN

1µF

68ꢀ

33nF

6800pF

BYP

VREG

C

BYP

1µF

CP_GNDSD_GND

A_GNDVCOA_GNDRFV_REGVCOV_REFV_BIAS

13 18 21 15 19 23 24

REF_SENSE

GND

A_GND

9

C

REG

10µF

8

31

10pF

0.1µF 10pF

0.1µF

Figure 53. Power Supplies

Rev. 0 | Page 36 of 38

Data Sheet

ADF5356

For frequencies below 2 GHz, it is recommended to use a

100 nH inductor on the RF_OUTA+/RF_OUTA− pins and a 100 pF

ac coupling capacitor.

OUTPUT MATCHING

The low frequency output can simply be ac-coupled to the next

circuit, if desired; however, if a higher output power is required,

use a pull-up inductor to increase the output power level.

The RF_OUTA+/RF_OUTA− pins form a differential circuit. Provide

each output with the same (or similar) components where

possible, such as the same shunt inductor value, bypass

capacitor, and termination.

V

RF

7.5nH

100pF

RF

A+

OUT

50ꢀ

AC couple the higher frequency output, RF_OUTB, directly to the

next appropriate circuit stage.

Figure 54. Optimum Output Stage

RF_OUTB is matched internally to a 50 Ω impedance and requires

no additional matching components.

When differential outputs are not required, terminate the

unused output or combine it with both outputs using a balun.

Rev. 0 | Page 37 of 38

ADF5356

Data Sheet

OUTLINE DIMENSIONS

5.10

5.00 SQ

4.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

25

32

24

1

0.50

BSC

3.75

3.60 SQ

3.55

EXPOSED

PAD

17

8

16

9

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.

Figure 55. 32-Lead Lead Frame Chip Scale Package [LFCSP]

5 mm × 5 mm Body and 0.75 mm Package Height

(CP-32-12)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

ADF5356BCPZ

ADF5356BCPZ-RL7

EV-ADF5356SD1Z

Temperature Range

−40°C to +85°C

Package Description

Package Option

32-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

CP-32-12

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D15360-0-8/17(0)

Rev. 0 | Page 38 of 38


型号：	ADF5356BCPZ-RL7
厂家：	ADI
描述：	Microwave Wideband Synthesizer
文件：	总38页 (文件大小：726K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADF5356BCPZ-RL7 [ADI]

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