ADF7030-1BSTZN-RL_技术文档

High Performance, Sub GHz

Radio Transceiver IC

ADF7030-1

Data Sheet

On-chip ARM Cortex-M0 processor for

Radio control and calibration

Packet management

Clear channel assessment (CCA)

IEEE802.15.4g support

Frame format

Data whitening

Dual-sync word detection

FEATURES

Radio frequency (RF) ranges

169.4 MHz to 169.6 MHz

426 MHz to 470 MHz

863 MHz to 960 MHz

Data rates

2FSK/2GFSK: 0.1 kbps to 300 kbps

4FSK/4GFSK: 1 kbps to 360 kbps (transmit only)

Dual power amplifiers (PAs)

Programmable receiver channel bandwidth (BW) from

2.6 kHz to 738 kHz

Forward error correction (FEC) and interleaving

Suitable for systems targeting compliance with

ETSI EN 300 220-1

EN 54-25, EN 13757-4

Receiver (Rx) performance

FCC Part 15, Part 22, Part 24, Part 90, and Part 101

ARIB STD-T30, STD-T67, STD-T108, STD-T96

Packages

6 mm × 6 mm, 40-lead LFCSP

7 mm × 7 mm, 48-lead LQFP

Up to 102 dB blocking at 20 MHz offset

Up to 66 dB adjacent channel rejection

−134.3 dBm sensitivity at 0.1 kbps

−121.2 dBm sensitivity at 2.4 kbps

Transmitter (Tx) performance

−20 dBm to +17 dBm range with 0.1 dB step resolution

Very low output power variation vs. temperature and supply

Low active current

50 mA Tx current at 17 dBm

21.2 mA Rx current at12.5 kbps

Ultralow sleep current

10 nA with memory retained

Autonomous smart wake modes

Host microprocessor interface

APPLICATIONS

IEEE 802.15.4g (MR-FSK PHY)

Wireless M-Bus (EN 13757-4)

Smart metering

Security and building automation

Active tag asset tracking

Industrial control

Wireless sensor networks (WSNs)

Easy to use programming serial peripheral interface (SPI)

Configurable 8-bit general-purpose input/output (GPIO) bus

FUNCTIONAL BLOCK DIAGRAM

HFXTALN HFXTALP

CREGx

LDOx

GPIO6 GPIO7

ADF7030-1

TCXO

BUFFER

26MHz

OSC

32kHz

OSC

26kHz

RC OSC

INTERRUPT

CONTROLLER

®

ARM

LNAIN1

LNAIN2

®

CORTEX -M0

LNA

RECEIVER

SYNTHESIZER

TRANSMITTER

SPI

SLAVE

SPI

DIGITAL

BASEBAND

CONFIGURABLE

GPIOx

PA

PAOUT1

GPIOs

ROM

TEMPERATURE

RAM

SENSOR

PAOUT2

NOTES

1. CREGx, GPIOx, AND SPI CONTAIN MULTIPLE PINS.

Figure 1.

Rev. 0

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ADF7030-1

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

460 MHz—Transmit .................................................................. 34

868 MHz—Receive..................................................................... 36

868 MHz—Transmit .................................................................. 38

915 MHz—Receive..................................................................... 40

915 MHz—Transmit .................................................................. 42

Theory of Operation ...................................................................... 44

State Machine.............................................................................. 44

Radio Timing.............................................................................. 45

Host Interface.............................................................................. 46

Receiver........................................................................................ 46

Transmitter.................................................................................. 48

Calibration................................................................................... 49

Packet Handling ......................................................................... 50

Applications Information.............................................................. 51

Typical Application Circuit....................................................... 51

Silicon Anomaly ............................................................................. 52

ADF7030-1 Functionality Issues.............................................. 52

Functionality Issues.................................................................... 52

Development Support.................................................................... 53

Design Package........................................................................... 53

Reference Manuals ..................................................................... 53

Evaluation Kits............................................................................ 53

Evaluation Software ................................................................... 53

Outline Dimensions....................................................................... 54

Ordering Guide .......................................................................... 55

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

Temperature and Voltage............................................................. 4

General RF..................................................................................... 4

Receive ........................................................................................... 5

Transmit......................................................................................... 6

Current Consumption ................................................................. 8

Band Specific Receive and Transmit.......................................... 9

External 26 MHz Oscillator ...................................................... 19

Low Frequency Oscillator ......................................................... 19

Temperature Sensor ................................................................... 19

Digital Input/Output.................................................................. 20

Digital Timing............................................................................. 20

Absolute Maximum Ratings.......................................................... 22

ESD Caution................................................................................ 22

Pin Configurations and Function Descriptions ......................... 23

Typical Performance Characteristics ........................................... 27

169 MHz—Receive..................................................................... 27

169 MHz—Transmit .................................................................. 28

433 MHz—Receive..................................................................... 30

433 MHz—Transmit .................................................................. 31

460 MHz—Receive..................................................................... 33

REVISION HISTORY

6/2016—Revision 0: Initial Version

Rev. 0 | Page 2 of 55

Data Sheet

ADF7030-1

GENERAL DESCRIPTION

The ADF7030-1 is a fully integrated, radio transceiver achieving

high performance at very low power. The ADF7030-1 is ideally

suited for applications that require long range, network

robustness, and long battery life. It is suitable for applications

that operate in the ISM, SRD, and licensed frequency bands at

169.4 MHz to 169.6 MHz, 426 MHz to 470 MHz, and 863 MHz

to 960 MHz. It provides extensive support for standards-based

protocols like IEEE802.15.4g while also providing flexibility to

support a wide range of proprietary protocols.

ultralow power deep sleep mode achieves a typical current of

10 nA with the configuration memory retained.

The ADF7030-1 supports smart wake mode (SWM) where the

ADF7030-1 can wake up autonomously from sleep using an

internal real-time clock (RTC) without intervention from the

host processor. After wake-up, the ADF7030-1 operates

autonomously. This functionality allows carrier sense, packet

sniffing, and packet reception while the host processor is in

sleep mode, thereby reducing overall system current consump-

tion. The ADF7030-1 autonomous operation can also be

triggered by the host processor using the interrupt input of the

ADF7030-1.

The highly configurable low intermediate frequency (IF) receiver

supports a large range of receiver channel bandwidths from

2.6 kHz to 738 kHz. This range of receiver channel bandwidths

allows the ADF7030-1 to support ultranarrow-band, narrow-

band, and wideband channel spacing.

A complete wireless solution can be built using a small number of

external discrete components and a host processor (typically a

microcontroller). The host processor can configure the ADF7030-1

using a simple command-based protocol over a standard 4-wire

SPI interface. A single-byte command transitions the radio

between states or performs a radio function.

The ADF7030-1 features two independent PAs supporting

output power ranges of −20 dBm to +13 dBm and −20 dBm to

+17 dBm. The PAs support ultrafine adjustment of the power

with a step resolution of 0.1 dB. The PA output power is

exceptionally robust over temperature and voltage. The PAs

have an automatic power ramp control to limit spectral splatter

to meet regulatory standards.

The ADF7030-1 is available in two package types: a 6 mm ×

6 mm, 40-lead LFCSP and a 7 mm × 7 mm, 48-lead LQFP. Both

package types use NiPdAu plating to mitigate against silver

migration in high humidity applications. The ADF7030-1

operating temperature range is −40°C to +85°C.

The ADF7030-1 features an on-chip ARM® Cortex®-M0

processor that performs radio control, radio calibration, and

packet management. Cortex-M0 eases the processing burden of

the host processor because the ADF7030-1 integrates the lower

layers of a typical communication protocol stack. This internal

processor also permits the download and execution of Analog

Devices, Inc., provided firmware modules that can extend the

functionality of the ADF7030-1.

For Figure 13 to Figure 19, Figure 30, Figure 42, Figure 60,

Figure 61, and Figure 77 in the Typical Performance Characteristics

section, PA_COARSE is a programmable value that provides a

coarse adjustment of the PA output power. This value can be

programmed in the range of 1 to 6 for PA1, and from 1 to 10 for

PA2. PA_FINE is a programmable value that provides a fine adjust-

ment of the PA output power. This value can be programmed in

the range of 3 to 127 for both PA1 and PA2. PA_MICRO is a

programmable value that provides a microadjustment (typically

<0.1 dB) of the PA output power. This value can be programmed in

the range of 1 to 31 for both PA1 and PA2. PAOLDO_VOUT_

CON is a programmable value that configures the internal LDO

voltage that provides bias for the PA. For additional information

on these bit settings, see the ADF7030-1 Software Reference

Manual, which is the detailed programming guide for the device.

The ADF7030-1 has two packet modes: generic packet mode

and IEEE802.15.4g mode. In generic packet mode, the packet

format is highly flexible and fully programmable, thereby

ensuring its compatibility with proprietary packet formats. In

IEEE802.15.4g packet mode, the packet format conforms to the

IEEE802.15.4g standard. FEC, as per the IEEE802.15.4g standard,

is also supported.

The ADF7030-1 operates with a power supply range of 2.2 V to

3.6 V and has very low power consumption in both Tx and Rx

modes, enabling long lifetimes in battery-operated systems. An

Rev. 0 | Page 3 of 55

ADF7030-1

Data Sheet

SPECIFICATIONS

V_DD= VBAT1 = VBAT2 = VBAT3 = VBAT4 = VBAT5 = VBAT6 = 2.2 V to 3.6 V, exposed pad (EPAD) = 0 V (ground), T_A= T_MINto T_MAX

unless otherwise noted. Typical specifications are at V_DD= 3 V, T _A= 25°C, unless otherwise noted. All VBATx pins must be tied together.

A one-time radio calibration is required, unless otherwise noted.

,

TEMPERATURE AND VOLTAGE

Table 1.

Parameter

Min

Typ Max

Unit Test Conditions/Comments

TEMPERATURE RANGE, T_A−40

VOLTAGE SUPPLY

+85

°C

VBATx Pin Voltage

2.2

2.85

3.6

V

Transmit power ≤ 13 dBm

Transmit power ≥ 17 dBm, PA LDO voltage = 2.65 V

Transmit power >13 dBm and < 17 dBm; the PA LDO

voltage is configurable

PA LDO voltage + 0.2 V

GENERAL RF

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

RF FREQUENCY

Frequency Range

169.4

426

863

169.6

470

960

MHz

Hz

Channel Frequency Resolution

DATA RATE

1.5

IEEE802.15.4g Packet Mode

2FSK, 2GFSK Modulation

Generic Packet Mode

kbps

2.4

150

2FSK, 2GFSK Modulation

4FSK, 4GFSK Modulation

On/Off Keying (OOK) Modulation

0.1

1

300

360

kbps

Tx only, generic packet mode only

Tx only, Manchester encoded,

generic packet mode only

16.384

1

Resolution

bps

FREQUENCY DEVIATION

Range

2FSK, 2GFSK Modulation

4FSK, 4GFSK Modulation

Resolution

1

250

kHz

Hz

Tx only, generic packet mode only

Programmable

100

GAUSSIAN FILTER BANDWIDTH TIME (BT) PRODUCT

0.3, 0.35, 0.4, 0.5

Rev. 0 | Page 4 of 55

Data Sheet

ADF7030-1

RECEIVE

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

MAXIMUM DATA RATE ERROR TOLERANCE

RECEIVER CHANNEL FILTER BANDWIDTH

0.1

%

Programmable; see Table 27 and Table 28 for a list of all

supported values

Narrow-Band Mode

Maximum

Minimum

20.0

2.6

kHz

Wideband Mode

Maximum

Minimum

738

77

kHz

dBm

MAXIMUM RF INPUT LEVEL

RECEIVER LINEARITY

Input Third-Order Intercept (IIP3)

10

Measured at maximum receiver gain

Receiver channel frequency = 169.43125 MHz,

f_SOURCE1= 171.35 MHz, f_SOURCE2= 173.26875 MHz

Receiver channel frequency = 169.53125 MHz,

f_SOURCE1= 171.55 MHz, f_SOURCE2= 171.63125 MHz

Receiver channel frequency = 169.43125 MHz,

f_SOURCE1= 171.43125 MHz

−8.5

53

dBm

Input Second-Order Intercept (IIP2)

1 dB Compression (P1dB)

−18.7

RECEIVED SIGNAL STRENGTH INDICATOR

(RSSI)

Refer to the Typical Performance Characteristics section

for further detail; sensitivity defined as bit error rate

(BER) = 0.1%

Resolution

Calibrated Absolute Accuracy

0.25

2

dB

−40 dBm to sensitivity + 6 dB; one-point offset calibration

DIFFERENTIAL LOW NOISE AMPLIFIER

(LNA) INPUT IMPEDANCE, 40-LEAD

LFCSP PACKAGE

LNA in Rx Mode

f = 169 MHz

f = 433 MHz

f = 460 MHz

f = 868 MHz

f = 915 MHz

LNA in Tx Mode

f = 169 MHz

f = 433 MHz

f = 460 MHz

f = 868 MHz

f = 915 MHz

78 − j20

69 − j25

68 − j25

56 − j29

55 − j30

Ω

Combined match enabled

7 + j2

7 + j4

8 + j8

Ω

DIFFERENTIAL LNA INPUT IMPEDANCE,

48-LEAD LQFP PACKAGE

LNA in Rx Mode

f = 169 MHz

f = 433 MHz

f = 460 MHz

f = 868 MHz

f = 915 MHz

LNA in Tx Mode

f = 169 MHz

f = 433 MHz

f = 460 MHz

f = 868 MHz

f = 915 MHz

78 − j16

71 − j18

73 − j22

58 − j20

57 − j20

Ω

Combined match enabled

7 + j3

8 + j9

9 + j18

9 + j19

Ω

Rev. 0 | Page 5 of 55

ADF7030-1

Data Sheet

TRANSMIT

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER AMPLIFIER (PA)

Power Amplifier 1 (PA1)

Transmit Power Maximum

Transmit Power Minimum

Transmit Power Step Resolution

13

−20

0.1

dBm

dB

Transmit Power Variation vs.

Temperature

0.15

From −40°C to +85°C, transmit power = 13 dBm, RF

frequency = 169 MHz

Transmit Power Variation vs. V_DD

0.1

0.3

From V_DD= 2.2 V to V_DD= 3.6 V, transmit power =

13 dBm, RF frequency = 169 MHz

transmit power = 13 dBm, RF frequency = 169 MHz

Transmit Power Accuracy

Power Amplifier 2 (PA2)

Transmit Power Maximum

The maximum output power level achievable on PA2

depends on the programmable PA CREG3 LDO voltage

setting; refer to the ADF7030-1 Software Reference

Manual for further details

17

13

−20

0.1

dBm

dB

2.85 V ≤ V_DD≤ 3.6 V

2.2 V ≤ V_DD≤ 3.6 V

Transmit Power Minimum

Transmit Power Step Resolution

Transmit Power Variation vs.

Temperature

dB

From −40°C to +85°C, transmit power = 17 dBm,

RF frequency = 169 MHz

Transmit Power Variation vs. V_DD

0.1

dB

From V_DD= 3.0 V to V_DD= 3.6 V, transmit power = 17 dBm,

RF frequency = 169 MHz

Transmit power = 17 dBm, RF frequency = 169 MHz

Transmit Power Accuracy

0.25

PA IMPEDANCE, 40-LEAD LFCSP

PACKAGE

For guidance on impedance matching, refer to the

ADF7030-1 Hardware Reference Manual

Optimum PA Load While in Transmit

PA1

f = 169 MHz

50 + j0

45 + j30

50 + j20

Ω

f = 433 MHz, f = 460 MHz

f = 868 MHz, f = 915 MHz

PA2

f = 169 MHz

38 + j0

38 + j25

38 + j18.5

Ω

f = 433 MHz, f = 460 MHz

f = 868 MHz, f = 915 MHz

PA Input Impedance While in Rx

PA1

f = 169 MHz

f = 433 MHz

f = 460 MHz

f = 868 MHz

7 − j232

5 − j102

5 − j96

4 − j49

4 − j46

Ω

f = 915 MHz

PA2

f = 169 MHz

f = 433 MHz

f = 460 MHz

f = 868 MHz

5 − j177

3 − j69

3 − j65

3 − j33

3 − j31

Ω

f = 915 MHz

Rev. 0 | Page 6 of 55

Data Sheet

ADF7030-1

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PA IMPEDANCE, 48-LEAD LQFP

PACKAGE

For guidance on impedance matching, refer to the

ADF7030-1 Hardware Reference Manual

Optimum PA Load While in Transmit

PA1

f = 169 MHz

f = 433 MHz, f = 460 MHz

f = 868 MHz

45 + j 8

40 + j20

Ω

f = 915 MHz

PA2

f = 169 MHz

37 + j 9

30 + j25

30 + j15

Ω

f = 433 MHz, f = 460 MHz

f = 868 MHz, f = 915 MHz

PA Input Impedance While in Rx

PA1

f = 169 MHz

f = 433 MHz, f = 460 MHz

f = 868 MHz

6 − j236

6 − j87

5 − j37

5 − j34

Ω

f = 915 MHz

PA2

f = 169 MHz

f = 433 MHz, f = 460 MHz

f = 868 MHz

5 − j169

4 − j58

3 − j22

3 − j19

Ω

f = 915 MHz

Rev. 0 | Page 7 of 55

ADF7030-1

Data Sheet

CURRENT CONSUMPTION

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TRANSMIT CURRENT CONSUMPTION

f = 169.4 MHz

In the PHY_TX state transmitting a carrier

Tx Power = 0 dBm, PA1

Tx Power = 10 dBm, PA1

Tx Power = 13 dBm, PA1

Tx Power = 17 dBm, PA2

f = 433 MHz

18

31

39

65

mA

Tx Power = 0 dBm, PA1

Tx Power = 10 dBm, PA1

Tx Power = 13 dBm, PA1

f = 460 MHz

19

31

39

mA

Tx Power = 17 dBm, PA2

f = 868 MHz, f = 915 MHz

Tx Power = 0 dBm, PA1

Tx Power = 10 dBm, PA1

Tx Power = 13 dBm, PA1

Tx Power = 17 dBm, PA2

RECEIVE CURRENT CONSUMPTION

f = 169.4 MHz

Data Rate = 4.8 kbps

f = 433 MHz, f = 460 MHz

Data Rate = 4.8 kbps

Data Rate = 50 kbps

f = 868 MHz, f = 915 MHz

Data Rate = 5 kbps

Data Rate = 12.5 kbps

Data Rate = 50 kbps

Data Rate = 100 kbps

Data Rate = 150 kbps

Data Rate = 300 kbps

RADIO STATE CURRENT CONSUMPTION

PHY_SLEEP State

50

mA

20

34

43

65

mA

In the PHY_RX state, waiting for preamble

Narrow-band receive path

24.8

mA

24.5

24

mA

Narrow-band receive path

Wideband receive path

23.2

21.2

21.4

23.7

24

mA

Narrow-band receive path

Wideband receive path

25.4

2

nA

Memory not retained, no wakeup oscillator enabled,

RTC disabled

10

1

nA

Memory retained, no wakeup oscillator enabled, RTC

disabled

Memory retained, internal 26 kHz RC oscillator

enabled, RTC enabled

µA

1

µA

Memory retained, external 32 kHz oscillator enabled,

RTC enabled

PHY_OFF State

PHY_ON State

1.9

3.7

mA

First entry to PHY_OFF after wake from PHY_SLEEP

or after reset event

Second and subsequent entries to PHY_OFF after

wake from PHY_SLEEP or after reset event

Rev. 0 | Page 8 of 55

Data Sheet

ADF7030-1

BAND SPECIFIC RECEIVE AND TRANSMIT

169.4 MHz to 169.6 MHz

Unless otherwise noted, the configurations detailed in Table 6 are used to specify the performance of the ADF7030-1 in Table 7. All

measurements are performed on the EV-ADF70301-169BZ evaluation board, unless otherwise noted. The EV-ADF70301-169BZ uses a

separate transmit/receive match design and a 26 MHz thermally compensated crystal oscillator (TCXO) reference. N/A means not applicable.

Table 6. Configurations in the 169.4 MHz to 169.6 MHz Frequency Band

RF

Data

Rate

(kbps)

Frequency Channel IF

Deviation Spacing Frequency Receiver

Modulation (kHz)

Configuration

Name

Frequency

(MHz)

Packet Setup for Packet-

Based Testing

(kHz)

BW (kHz)

169.41875 MHz/ 169.41875

0.1 kbps

0.1

2GFSK

0.5

N/A

81.25

2.6

Preamble = 0xAAAA, sync

word = 0xF672, payload

length = 23 bytes, cyclic

redundancy check (CRC) =

2 bytes

169.43125 MHz/ 169.43125

2.4 kbps

2.4

4.8

6.4

2GFSK

4GFSK

2.4

12.5

81.25

8.7

Preamble = 0x5555, sync

word = 0xF672, payload

length = 23 bytes, CRC =

2 bytes

Preamble = 0x5555, sync

word = 0xF672, payload

length = 23 bytes, CRC =

2 bytes

169.41875 MHz/ 169.41875

4.8 kbps

10.6

169.46875 MHz/ 169.46875

6.4 kbps

3.2 (outer

deviation)

N/A

(Tx only)

N/A

(Tx only)

N/A

Table 7. Specifications in the 169.4 MHz to 169.6 MHz Frequency Band

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SENSITIVITY, PACKET ERROR RATE (PER)

Configuration 169.41875 MHz/0.1 kbps

Configuration 169.43125 MHz/2.4 kbps

−134.3

−121.2

dBm

At PER = 5%, automatic frequency control (AFC) disabled

At PER = 5%, AFC enabled, RF frequency error range =

11.5 ppm

Configuration 169.41875 MHz/4.8 kbps

−119.4

dBm

At PER = 5%, AFC enabled, RF frequency error range =

11.5 ppm

CHANNEL SELECTIVITY AND BLOCKING—

BER-BASED TEST METHOD

Desired signal 3 dB above the input sensitivity level (BER

= 0.1%), carrier wave (CW) interferer power level

increased until BER = 0.1%; AFC disabled, image calibrated

Configuration 169.43125 MHz/2.4 kbps

Adjacent Channel ( 12.5 kHz)

Alternate Channel ( 25 kHz)

2 MHz

66

94

92

102

dB

10 MHz

20 MHz

Configuration 169.41875 MHz/4.8 kbps

Adjacent Channel ( 12.5 kHz)

Alternate Channel ( 25 kHz)

2 MHz

55

63

92

90

dB

10 MHz

CHANNEL SELECTIVITY AND BLOCKING—

PER-BASED TEST METHOD

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%,

AFC enabled, image calibrated

Configuration 169.43125 MHz/2.4 kbps

Adjacent Channel ( 12.5 kHz)

Alternate Channel ( 25 kHz)

2 MHz

62

70

94

96

dB

10 MHz

Configuration 169.41875 MHz/4.8 kbps

Adjacent Channel ( 12.5 kHz)

55

dB

Rev. 0 | Page 9 of 55

ADF7030-1

Data Sheet

Parameter

Min

Typ

69

Max

Unit

dB

Test Conditions/Comments

Alternate Channel ( 25 kHz)

2 MHz

91

dB

10 MHz

95

dB

CHANNEL SELECTIVITY AND BLOCKING—

ETSI EN 300 220-1 TEST METHOD

Measured as per EN 300 220-1 V2.4.1, AFC disabled

Configuration 169.43125 MHz/2.4 kbps

Desired signal level = −106.7 dBm (3 dB above the

reference sensitivity level)

2 MHz

10 MHz

−15

−12

dBm

Configuration 169.41875 MHz/4.8 kbps

Desired signal level = −105.8 dBm (3 dB above the

reference sensitivity level)

2 MHz

10 MHz

−16

−13

dBm

COCHANNEL REJECTION

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%,

AFC enabled

Configuration 169.43125 MHz/2.4 kbps

Configuration 169.41875 MHz/4.8 kbps

CALIBRATED IMAGE REJECTION

−10

dB

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%,

AFC enabled, image calibrated

Configuration 169.43125 MHz/2.4 kbps

ADJACENT CHANNEL POWER (ACP)

55

dB

Spectrum analyzer settings: resolution bandwidth (RBW) =

100 Hz, video bandwidth (VBW) = 300 Hz

Configuration 169.43125 MHz/2.4 kbps

Adjacent Channel

Alternate Channel

Configuration 169.41875 MHz/4.8 kbps

Adjacent Channel

Alternate Channel

Configuration 169.46875 MHz/6.4 kbps

Adjacent Channel

Alternate Channel

PA1, output power = 13 dBm

PA2, output power = 17 dBm

PA1, output power = 13 dBm

−83

−82

dBc

−59

−81

dBc

−68

−81

dBc

OCCUPIED BANDWIDTH (OBW)

Occupied bandwidth is the bandwidth containing 99% of

the total integrated power; spectrum analyzer settings:

RBW = 100 Hz, VBW = 300 Hz

Configuration 169.43125 MHz/2.4 kbps

Configuration 169.41875 MHz/4.8 kbps

Configuration 169.46875 MHz/6.4 kbps

6.3

7.8

8.2

kHz

PA1, output power = 13 dBm

PA2, output power = 17 dBm

PA1, output power = 13 dBm

SPURIOUS EMISSIONS (EXCLUDING

HARMONICS)

Measured conductively at antenna input; RF frequency =

169.43125 MHz

Receive

<1 GHz

1 GHz to 4 GHz

−58

−49

dBm

Transmit

PA2, output power = 17 dBm, transmitting continuous

carrier wave

<1 GHz

1 GHz to 4 GHz

−75

−78

dBc

HARMONIC EMISSIONS

Measured conductively at antenna input, transmitting

continuous carrier wave; RF frequency = 169.43125 MHz

17 dBm Output Power

Second Harmonic

Third Harmonic

PA2

−81

−90

<−90

dBc

All Other Harmonics

Rev. 0 | Page 10 of 55

Data Sheet

ADF7030-1

433 MHz

Unless otherwise noted, the configuration detailed in Table 8 is used to specify the performance of the ADF7030-1 in Table 9. All

measurements are performed on the EV-ADF70301-460BZ evaluation board, unless otherwise noted. The EV-ADF70301-460BZ uses a

separate transmit/receive match design and a 26 MHz TCXO reference.

Table 8. 433 MHz Configurations

RF

Frequency Rate

Data

Frequency Channel IF

Deviation

Modulation (kHz)

Receiver

Spacing Frequency BW

Configuration

Name

Packet Setup for

Packet Based Testing

(MHz)

(kbps)

(kHz)

433 MHz/50 kbps

433

50

2GFSK

25

200

154

127

Preamble = 0xAAAA,

sync word = 0xF672,

payload length =

16 bytes, CRC = 2 bytes

Table 9. 433 MHz Specifications

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

SENSITIVITY, PER

Configuration 433 MHz/50 kbps

−108.2

dBm

At PER = 5%, AFC enabled, RF frequency error range =

25 ppm

CHANNEL SELECTIVITY AND BLOCKING—

BER-BASED TEST METHOD

Desired signal 3 dB above the input sensitivity level (BER =

0.1%), CW interferer power level increased until BER = 0.1%,

image calibrated, AFC disabled

Configuration 433 MHz/50 kbps

Adjacent Channel ( 200 kHz)

Alternate Channel ( 400 kHz)

2 MHz

48

58

74

83

91

dB

10 MHz

20 MHz

CHANNEL SELECTIVITY AND BLOCKING—

PER BASED TEST METHOD

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%,

image calibrated, AFC enabled

Configuration 433 MHz/50 kbps

Adjacent Channel ( 200 kHz)

Alternate Channel ( 400 kHz)

2 MHz

46

55

71.5

77

dB

10 MHz

COCHANNEL REJECTION

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%,

AFC enabled

Configuration 433 MHz/50 kbps

CALIBRATED IMAGE REJECTION

−10

dB

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%,

AFC enabled, image calibrated

Configuration 433 MHz/50 kbps

ACP

54

dB

Spectrum analyzer settings: RBW = 100 Hz, VBW = 300 Hz

Configuration 433 MHz/50 kbps

OCCUPIED BANDWIDTH (OBW)

−59

dBc

Occupied bandwidth is the bandwidth containing 99% of

the total integrated power; spectrum analyzer settings:

RBW = 100 Hz, VBW = 300 Hz

Configuration 433 MHz/50 kbps

86

kHz

Rev. 0 | Page 11 of 55

ADF7030-1

Data Sheet

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

SPURIOUS EMISSIONS (EXCLUDING

HARMONICS)

Measured conductively at antenna port; RF frequency =

433 MHz

Receive

<1 GHz

1 GHz to 4 GHz

Transmit

−82

−47

dBm

PA1, output power = 10 dBm, transmitting continuous

carrier wave

<1 GHz

1 GHz to 4 GHz

−53

−76

dBc

HARMONIC EMISSIONS

Measured conductively at antenna input, transmitting

continuous carrier wave; RF frequency = 433 MHz, PA1,

output power = 10 dBm

Second Harmonic

All Other Harmonics

−64

<−90

dBc

Rev. 0 | Page 12 of 55

Data Sheet

ADF7030-1

450 MHz to 470 MHz

Unless otherwise noted, the configuration detailed in Table 10 is used to specify the performance of the ADF7030-1 in Table 11. All

measurements are performed on the EV-ADF70301-460BZ evaluation board, unless otherwise noted. The EV-ADF70301-460BZ uses a

separate transmit/receive match design and a 26 MHz TCXO reference.

Table 10. Configurations in the 450 MHz to 470 MHz Frequency Band

RF

Data

Frequency Channel IF

Receiver

Configuration

Name

Frequency Rate

(MHz)

Deviation

Modulation (kHz)

2GFSK 2.0

Spacing

(kHz)

Frequency BW

(kHz)

Packet Setup for Packet

Based Testing

(kbps)

7.2

(kHz)

460 MHz/7.2 kbps

460

12.5

81.25

11.7

Preamble = 0xAAAA, sync

word = 0xF672, payload

length = 23 bytes, CRC =

2 bytes

Table 11. Specifications in the 450 MHz to 470 MHz Frequency Band

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

SENSITIVITY, PER

Configuration 460 MHz/7.2 kbps

−116

dBm

At PER = 5%, AFC enabled, RF frequency error range =

3.9 ppm

CHANNEL SELECTIVITY AND BLOCKING—

BER-BASED TEST METHOD

Desired signal 3 dB above the input sensitivity level (BER =

0.1%), CW interferer power level increased until BER = 0.1%,

image calibrated, AFC disabled

Configuration 460 MHz/7.2 kbps

Adjacent Channel ( 12.5 kHz)

Alternate Channel ( 25 kHz)

2 MHz

54

61

84

92

98

dB

10 MHz

20 MHz

CHANNEL SELECTIVITY AND BLOCKING—

PER-BASED TEST METHOD

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%,

image calibrated, AFC enabled

Configuration 460 MHz/7.2 kbps

Adjacent Channel ( 12.5 kHz)

Alternate Channel ( 25 kHz)

2 MHz

38

57

80

85

dB

10 MHz

COCHANNEL REJECTION

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%, AFC

enabled

Configuration 460 MHz/7.2 kbps

CALIBRATED IMAGE REJECTION

10

dB

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%, AFC

enabled, image calibrated

Configuration 460 MHz/7.2 kbps

51

dB

ACP

Spectrum analyzer settings: RBW = 100 Hz, VBW = 300 Hz

Configuration 460 MHz/7.2 kbps

OBW

−45

dBc

Occupied bandwidth is the bandwidth containing 99% of the

total integrated power; spectrum analyzer settings: RBW =

100 Hz, VBW = 300 Hz

Configuration 460 MHz/7.2 kbps

7.7

kHz

Rev. 0 | Page 13 of 55

ADF7030-1

Data Sheet

Parameter

Min Typ

Max

Unit

Test Conditions/Comments

SPURIOUS EMISSIONS (EXCLUDING

HARMONICS)

Measured conductively at antenna port; RF frequency =

460 MHz

Receive

<960 MHz

960 MHz to 12.7 GHz

Transmit

−57

−66

dBm

PA2, output power = 17 dBm, transmitting continuous carrier

wave

<960 MHz

960 MHz to 12.7 GHz

HARMONIC EMISSIONS

−59

−76

dBc

Measured conductively at antenna port, transmitting

continuous carrier wave; RF frequency = 460 MHz, output

power = 17 dBm, PA2

Second Harmonic

All Other Harmonics

−60

< −90

dBc

Rev. 0 | Page 14 of 55

Data Sheet

ADF7030-1

863 MHz to 876 MHz

Unless otherwise noted, the configurations detailed in Table 12 are used to specify the performance of the ADF7030-1 in Table 13. All

measurements are performed on the EV-ADF70301-868BZ evaluation board, unless otherwise noted. The EV-ADF70301-868BZ uses a

separate transmit/receive match design and a 26 MHz TCXO reference.

Table 12. Configurations in the 863 MHz to 876 MHz Frequency Band

RF

Frequency Rate

Data

Frequency Channel IF

Receiver

Configuration

Name

Deviation

Spacing Frequency BW

Packet Setup for

Packet Based Testing

(MHz)

(kbps) Modulation (kHz)

(kHz)

868 MHz/4.8 kbps

868

4.8

2GFSK

2.4

12.5

81.25

10.6

Preamble = 0xAAAA,

sync word = 0xF672,

payload length =

23 bytes, CRC = 2 bytes

868 MHz/100 kbps

868

100

2FSK

50

500

241

231

Preamble =

0xAAAAAAAA, sync

word = 0x543D54CD,

payload length =

20 bytes, CRC = 2 bytes

Table 13. Specifications in the 863 MHz to 876 MHz Frequency Band

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SENSITIVITY, PER

Configuration 868 MHz/4.8 kbps

Configuration 868 MHz/100 kbps

−118.5

−106

dBm

At PER = 5%, AFC enabled, RF frequency error range = 3 ppm

At PER = 5%, AFC enabled, RF frequency error range =

25 ppm, data rate error range = 100 ppm, frequency

deviation error range = 25%

CHANNEL SELECTIVITY AND BLOCKING—

BER-BASED TEST METHOD

Desired signal 3 dB above the input sensitivity level (BER =

0.1%), CW interferer power level increased until BER = 0.1%,

image calibrated, AFC disabled

Configuration 868 MHz/4.8 kbps

Adjacent Channel ( 12.5 kHz)

Alternate Channel ( 25 kHz)

2 MHz

56

78

87

98

dB

10 MHz

20 MHz

CHANNEL SELECTIVITY AND BLOCKING—

PER-BASED TEST METHOD

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%,

image calibrated, AFC enabled

Configuration 868 MHz/4.8 kbps

Adjacent Channel ( 12.5 kHz)

Alternate Channel ( 25 kHz)

2 MHz

47

55

79

90

dB

10 MHz

Configuration 868 MHz/100 kbps

Adjacent Channel ( 500 kHz)

Alternate Channel ( 1000 kHz)

2 MHz

44

59

65

76

dB

10 MHz

COCHANNEL REJECTION

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%,

AFC enabled

Configuration 868 MHz/4.8 kbps

Configuration 868 MHz/100 kbps

−10

dB

Rev. 0 | Page 15 of 55

ADF7030-1

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

UNCALIBRATED IMAGE REJECTION

Desired signal 3 dB above the input sensitivity level (PER =

5%), CW interferer power level increased until PER = 5%,

AFC enabled

Configuration 868 MHz/4.8 kbps

Configuration 868 MHz/100 kbps

ACP

35

dB

Spectrum analyzer settings: RBW = 100 Hz, VBW = 300 Hz

Configuration 868 MHz/4.8 kbps

Configuration 868 MHz/100 kbps

OBW

−65

−41

dBc

Occupied bandwidth is the bandwidth containing 99% of the

total integrated power; spectrum analyzer settings: RBW =

100 Hz, VBW = 300 Hz

Configuration 868 MHz/4.8 kbps

Configuration 868 MHz/100 kbps

7.8

226

kHz

SPURIOUS EMISSIONS (EXCLUDING

HARMONICS)

Measured conductively at antenna input; RF Frequency =

868 MHz

Receive

<1 GHz

1 GHz to 4 GHz

Transmit

−58

−46

dBm

PA2, 17dBm output power, transmitting continuous carrier

wave

<1 GHz

1 GHz to 4 GHz

−74

−77

dBc

HARMONIC EMISSIONS

Measured conductively at antenna input, transmitting

continuous carrier wave; RF frequency = 868 MHz

13 dBm Output Power

Second Harmonic

Third Harmonic

Seventh Harmonic

All Other Harmonics

17 dBm Output Power

Second Harmonic

Third Harmonic

PA1

PA2

−50

−78

−88

<−90

dBc

−55

−73

<−90

dBc

All Other Harmonics

Rev. 0 | Page 16 of 55

Data Sheet

ADF7030-1

902 MHz to 928 MHz

Unless otherwise noted, the configurations detailed in Table 14 are used to specify the performance of the ADF7030-1 in Table 15. All

measurements are performed on the EV-ADF70301-868BZ evaluation board, unless otherwise noted. The EV-ADF70301-868BZ uses a

separate transmit/receive match design and a 26 MHz TCXO reference.

Table 14. Configurations in the 902 MHz to 928 MHz Frequency Band

RF

Data

Rate

Frequency

Deviation

(kHz)

Channel

Spacing

(kHz)

IF

Configuration

Name

Frequency

(MHz)

Frequency

(kHz)

Receiver

BW (kHz)

Packet Setup for Packet Based

Testing

(kbps) Modulation

915 MHz/

50 kbps

915

50

2GFSK

25

200

154

127

Preamble = 0xAAAAAAAA, sync word =

0x904E, payload length = 100 bytes,

CRC = 2 bytes

915 MHz/

150 kbps

915

150

2GFSK

37.5

400

336

250

Preamble =

0xAAAAAAAAAAAAAAAAAAAAAAAA ,

sync word = 0xFF7D7F5D, payload

length = 100 bytes, CRC = 2 bytes

915 MHz/

300 kbps

915

300

2GFSK

120

600

540

530

Preamble = 0xAAAAAAAA, sync word =

0xF672, payload length = 23 bytes,

CRC = 2 bytes

Table 15. 902 MHz to 928 MHz Specifications

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

2GFSK SENSITIVITY, PER

Configuration 915 MHz/50 kbps

−108.2

−100.5

−102

dBm

At PER = 5%, FEC disabled, AFC enabled, RF frequency

error range = 40 ppm

At PER = 5%, FEC disabled, AFC enabled, RF frequency

error range = 40 ppm

Configuration 915 MHz/150 kbps

Configuration 915 MHz/300 kbps

At PER = 5%, AFC disabled, RF frequency error range

=

11.5 ppm

CHANNEL SELECTIVITY AND BLOCKING—

BER-BASED TEST METHOD

Desired signal 3 dB above the input sensitivity level

(BER = 0.1%), CW interferer power level increased

until BER = 0.1%, AFC disabled

Configuration 915 MHz/150 kbps

Adjacent Channel ( 400 kHz)

Alternate Channel ( 800 kHz)

2 MHz

46

56

66

77

83

dB

10 MHz

20 MHz

CHANNEL SELECTIVITY AND BLOCKING—

PER-BASED TEST METHOD

Desired signal 3 dB above the input sensitivity level

(PER = 5%), CW interferer power level increased until

PER = 5%, image calibrated

Configuration 915 MHz/50 kbps

Adjacent Channel ( 200 kHz)

Alternate Channel ( 400 kHz)

2 MHz

FEC disabled, AFC enabled

AFC disabled

44.5

52

67

dB

10 MHz

77

Configuration 915 MHz/150 kbps

Adjacent Channel ( 400 kHz)

Alternate Channel ( 800 kHz)

2 MHz

43.5

44

60.5

70

dB

10 MHz

Configuration 915 MHz/300 kbps

Adjacent Channel ( 600 kHz)

Alternate Channel ( 1200 kHz)

2 MHz

28

33

62

72

dB

10 MHz

Rev. 0 | Page 17 of 55

ADF7030-1

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

COCHANNEL REJECTION

Desired signal 3 dB above the input sensitivity level

(PER = 5%), CW interferer power level increased until

PER = 5%

Configuration 915 MHz/50 kbps

Configuration 915 MHz/150 kbps

Configuration 915 MHz/300 kbps

UNCALIBRATED IMAGE REJECTION

−10

dB

Desired signal 3 dB above the input sensitivity level

(PER = 5%), CW interferer power level increased until

PER = 5%

Configuration 915 MHz/50 kbps

Configuration 915 MHz/150 kbps

Configuration 915 MHz/300 kbps

ACP

35

dB

Configuration 915 MHz/50 kbps

Adjacent Channel ( 200 kHz)

Alternate Channel ( 400 kHz)

Configuration 915 MHz/150 kbps

Adjacent Channel ( 400 kHz)

Alternate Channel ( 800 kHz)

Configuration 915 MHz/300 kbps

Adjacent Channel ( 600 kHz)

Alternate Channel ( 1200 kHz)

OCCUPIED BANDWIDTH

Spectrum analyzer settings: RBW = 300 Hz, VBW = 1 kHz

−55

−62

dBc

−53

−66

dBc

−30.5

−66

dBc

Occupied bandwidth is the bandwidth containing 99%

of the total integrated power

Configuration 915 MHz/50 kbps

Configuration 915 MHz/150 kbps

Configuration 915 MHz/300 kbps

85

167

475

kHz

Spectrum analyzer settings: RBW = 300 Hz, VBW = 1 kHz

SPURIOUS EMISSIONS (EXCLUDING

HARMONICS)

Measured conductively at antenna input;

RF frequency = 915 MHz

Receive

<960 MHz

960 MHz to 12.7 GHz

Transmit

−82

−47

dBm

PA2, output power = 17 dBm, transmitting

continuous carrier wave

<960 MHz

960 MHz to 12.7 GHz

HARMONIC EMISSIONS

−71

−73

dBc

Measured conductively at antenna input,

transmitting continuous carrier wave; RF frequency =

915 MHz

13 dBm Output Power

Second Harmonic

Third Harmonic

Seventh Harmonic

All Other Harmonics

17 dBm Output Power

Second Harmonic

Third Harmonic

PA1

−53

−83

−88

<−90

dBc

PA2

−54

−66

<−90

dBc

All Other Harmonics

Rev. 0 | Page 18 of 55

Data Sheet

ADF7030-1

EXTERNAL 26 MHz OSCILLATOR

The ADF7030-1 requires a 26 MHz reference clock. This reference can be a 26 MHz crystal oscillator operating in parallel mode and

connected between the HFXTALP and HFXTALN pins. Alternatively, a 26 MHz TCXO can be dc-coupled to the HFXTALN input. A

TCXO is typically used in narrow-band applications where the transmit and receive RF frequency must meet accuracies not supported by

a crystal oscillator.

Table 16.

Parameter

Min Typ Max Unit Test Conditions/Comments

DC-COUPLED TCXO

HFXTALN pin, clipped sine wave

TCXO Frequency

26

MHz

V

Peak-to-Peak Voltage Level

Voltage Level with Respect to Ground

Duty Cycle

0.8

−0.1

40

1.8

+1.9

60

%

CRYSTAL OSCILLATOR

Parallel resonant crystal

Crystal Frequency

Maximum Crystal ESR

26

MHz

Ω

50

Crystal Oscillator Load Capacitance

HFXTALN, HFXTALP Pin Capacitance in Parallel with Crystal Oscillator

12

5

pF

LOW FREQUENCY OSCILLATOR

Table 17.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

26 kHz INTERNAL RC OSCIALLATOR

Frequency

Frequency Accuracy

Frequency Drift

26

0.2

kHz

%

After calibration

After calibration at 25°C

Temperature Coefficient

Voltage Coefficient

Calibration Time

0.3

0.5

30

%/°C

%/V

ms

32 kHz EXTERNAL OSCILLATOR

Frequency

Start-Up Time

32.768

1.45

kHz

sec

TEMPERATURE SENSOR

Table 18.

Parameter

Min

Typ

Max

+85

Unit

Test Conditions/Comments

TEMPERATURE SENSOR

Range

Accuracy

−40

°C

5

T_A= −40°C to +85°C; calibrated at 25°C

Rev. 0 | Page 19 of 55

ADF7030-1

Data Sheet

DIGITAL INPUT/OUTPUT

Table 19.

Parameter

Symbol

Min

Typ Max

Unit

Test Conditions/Comments

LOGIC INPUTS

Input Voltage

High

Low

Input Capacitance

V_INH

V_INL

C_IN

0.7 × V_DD

V

pF

0.2 × V_DD

3.6

LOGIC OUTPUTS

Output Voltage

High

Low

V_OH

V_OL

V_DD− 0.4

V

I_OH= 500 μA

I_OL= 500 μA

0.4

Maximum GPIO Drive Strength for V_OH

Maximum GPIO Drive Strength for V_OL

2

mA

DIGITAL TIMING

Table 20. SPI Interface Timing

Parameter

Description

Min

Typ

Max

Unit

ns

μs

t₁

t₂

Falling edge to MISO setup time

CS low to SCLK setup time

SCLK high time

SCLK low time

SCLK period

15

40

80

t₃

t₄

t₅

t₆

t₇

t₈

t₉

SCLK falling edge to MISO delay

10

MOSI to SCLK rising edge setup time

MOSI to SCLK rising edge hold time

SCLK falling edge to CS hold time

CS high time

5

40

80

t₁₀

t₁₁

t₁₂

t₁₃

CS low to MISO high wake-up time

MISO high to SCLK setup time

RST low time

92

SCLK low time¹

2

¹The minimum for t₁₂changes with the SCLK frequency.

Rev. 0 | Page 20 of 55

Data Sheet

ADF7030-1

Timing Diagrams

CS

10

2

3

4

5

9

SCLK

1

6

MISO

MOSI

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

BIT 7

BIT 0

X

BIT 7

8

7

6

5

4

3

2

1

0

7

Figure 2. SPI Interface Timing

CS

9

12

SCLK

7

6

5

4

3

2

1

0

11

6

MISO

X

SPI STATE

SLEEP

WAKE UP

SPI READY

Figure 3. PHY_SLEEP to SPI Ready State Timing

t₁₃

RST

Figure 4. Reset Pin ( ) Timing

Rev. 0 | Page 21 of 55

ADF7030-1

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted. All VBATx pins must be tied

together. The LNAIN1 and LNAIN2 inputs must be ac-coupled.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 21.

Parameter

Rating

Supply Pins

VBAT1, VBAT2, VBAT3, VBAT4, VBAT5,

VBAT6 to Ground

−0.3 V to +3.9 V

Connect the exposed pad of the 40-lead LFCSP device to

ground.

LNAIN1, LNAIN2

PAOUT1, PAOUT2

HFXTALP, HFXTALN

CLF

CREG1, CREG2, CREG4, CREG5, CREG6,

CREG7

−0.3 V to +1.98 V

−0.3 V to +3.9 V

−0.3 V to +1.98 V

This device is a high performance, RF integrated circuit with an

ESD rating as indicated in Table 21; it is ESD sensitive. Take proper

precautions for handling and assembly.

ESD CAUTION

CREG3

−0.3 V to +3.9 V

−40°C to +85°C

−65°C to +125°C

150°C

Digital Inputs/Outputs, GPIOx

MOSI, MISO, SCLK, CS, RST

Industrial Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

θ_JAThermal Impedance

26°C/W

ESD Rating, Human Body Model (HBM)

40-Lead LFCSP Package

LNAIN1, LNAIN2, PAOUT1, PAOUT2

All Other Pins

250 V

2 kV

48-Lead LQFP Package

LNAIN1, LNAIN2, PAOUT1, PAOUT2

All Other Pins

250 V

2 kV

ESD Rating, Field Induced Charged

Device Model (FICDM)

40-Lead LFCSP Package

LNAIN1, LNAIN2, PAOUT1, PAOUT2

All Other Pins

1250 V

48-Lead LQFP Package

LNAIN1, LNAIN2, PAOUT1, PAOUT2

All Other Pins

1250 V

Reflow Soldering

Peak Temperature

Time at Peak Temperature

260°C

40 sec

Rev. 0 | Page 22 of 55

Data Sheet

ADF7030-1

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

30 DNC

29 GPIO6

28 CS

RST

VBAT1

CREG1

VBAT2

CREG2

LNAIN1

LNAIN2

DNC

1

2

3

4

5

6

7

8

9

27 SCLK

26 MISO

25 MOSI

24 VBAT5

23 VBAT4

22 GPIO5

21 GPIO4

ADF7030-1

TOP VIEW

(Not to Scale)

CREG3

DNC 10

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

2. CONNECT THE EXPOSED PAD TO GROUND.

Figure 5. 40-Lead LFCSP Pin Configuration

Table 22. 40-Lead LFCSP Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

RST

External Reset, Active Low.

VBAT1

CREG1

Power Supply Pin 1 to the Internal Regulators.

Regulator Output 1. Place a 220 nF capacitor between this pin and ground for regulator stability and noise

rejection. Also, place a 1.2 nF capacitor between this pin and the CLF pin.

4

5

6

7

8

9

VBAT2

CREG2

LNAIN1

LNAIN2

DNC

Power Supply Pin 2 to the Internal Regulators.

Regulator Output 2. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

LNA Input 1.

LNA Input 2.

Do Not Connect. Do not connect to this pin.

Regulator Output 3. Connect this pin to the PA choke inductor to provide bias to the PA. Place a 220 nF capacitor

between this pin and ground for regulator stability and noise rejection.

CREG3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DNC

Do Not Connect. Do not connect to this pin.

Single-Ended PA1 Output.

PAOUT1

PAOUT2

VBAT3

CREG4

GPIO0

GPIO1

GPIO2

GPIO3

DNC

GPIO4

GPIO5

VBAT4

VBAT5

MOSI

Single-Ended PA2 Output.

Power Supply Pin 3 to the Internal Regulators.

Regulator Output 4. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

Digital GPIO Pin 0.

Digital GPIO Pin 1.

Digital GPIO Pin 2.

Digital GPIO Pin 3.

Do Not Connect. Do not connect to this pin.

Digital GPIO Pin 4.

Digital GPIO Pin 5.

Power Supply Pin 4 to the Internal Regulators.

Power Supply Pin 5 to the Internal Regulators.

Serial Port Master Output/Slave Input.

Serial Port Master Input/Slave Output.

Serial Port Clock.

MISO

SCLK

CS

Chip Select (Active Low). A pull-up resistor of 100 kΩ to V_DDis recommended to prevent the host processor from

inadvertently waking the ADF7030-1 from sleep.

Rev. 0 | Page 23 of 55

ADF7030-1

Data Sheet

Pin No. Mnemonic Description

29

30

31

32

33

34

35

GPIO6

DNC

GPIO7

DNC

CREG5

HFXTALP

Digital GPIO Pin 6.

Do Not Connect. Do not connect to this pin.

Digital GPIO Pin 7.

Do Not Connect. Do not connect to this pin.

Regulator Output 5. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

Positive Reference Input. If a 26 MHz TCXO is used as the external reference, do not connect this pin. If a 26 MHz

XTAL is used as the reference, connect this pin to the XTAL.

36

HFXTALN

Negative Reference Input. If a 26 MHz TCXO is used as the external reference, connect this pin to the TCXO output.

If a 26 MHz XTAL is used as the reference, connect this pin to the XTAL.

37

38

39

40

CREG6

CREG7

CLF

VBAT6

EPAD

Regulator Output 6. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

Regulator Output 7. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

External Loop Filter Capacitor. Place a 1.2 nF capacitor between this pin and the CREG1 pin.

Power Supply Pin 6 to the Internal Regulators.

Exposed Pad. Connect the exposed pad to ground.

Rev. 0 | Page 24 of 55

Data Sheet

ADF7030-1

48 47 46 45 44 43 42 41 40 39 38 37

1

2

36

35

34

GND

RST

GND

CS

3

VBAT1

CREG1

DNC

4

33 SCLK

32 MISO

31 MOSI

30 VBAT5

29 VBAT4

28 GPIO5

5

ADF7030-1

6

VBAT2

CREG2

GND

TOP VIEW

7

(Not to Scale)

8

9

LNAIN1

LNAIN2

GND

27

10

11

12

GPIO4

26 GND

25

GPIO3

CREG3

13 14 15 16

18

20 21 22 23 24

19

17

NOTES

1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.

Figure 6. 48-Lead LQFP Pin Configuration

Table 23. 48-Lead LQFP Pin Function Descriptions

Pin No. Mnemonic Description

1

2

3

4

GND

RST

Connection to Ground.

External Reset, Active Low.

VBAT1

CREG1

Power Supply Pin 1 to the Internal Regulators.

Regulator Output 1. Place a 220 nF capacitor between this pin and ground for regulator stability and noise

rejection. Also, place a 1.2 nF capacitor between this pin and the CLF pin.

5

DNC

Do Not Connect. Do not connect to this pin.

6

7

8

9

10

11

12

VBAT2

CREG2

GND

LNAIN1

LNAIN2

GND

Power Supply Pin 2 to the Internal Regulators.

Regulator Output 2. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

Connection to Ground.

LNA Input 1.

LNA Input 2.

Connection to Ground.

CREG3

Regulator Output 3. Connect this pin to the PA choke inductor to provide bias to the PA. Place a 220 nF capacitor

between this pin and ground for regulator stability and noise rejection.

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

GND

PAOUT1

GND

PAOUT2

GND

DNC

VBAT3

CREG4

GND

GPIO0

GPIO1

GPIO2

GPIO3

GND

GPIO4

GPIO5

VBAT4

VBAT5

Connection to Ground.

Single-Ended PA1 Output.

Connection to Ground.

Single-Ended PA2 Output.

Connection to Ground.

Do Not Connect. Do not connect to this pin.

Power Supply Pin 3 to the Internal Regulators.

Regulator Output 4. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

Connection to Ground.

Digital GPIO Pin 0.

Digital GPIO Pin 1.

Digital GPIO Pin 2.

Digital GPIO Pin 3.

Connection to Ground.

Digital GPIO Pin 4.

Digital GPIO Pin 5.

Power Supply Pin 4 to the Internal Regulators.

Power Supply Pin 5 to the Internal Regulators.

Rev. 0 | Page 25 of 55

ADF7030-1

Data Sheet

Pin No. Mnemonic Description

31

32

33

34

MOSI

MISO

SCLK

CS

Serial Port Master Output/Slave Input.

Serial Port Master Input/Slave Output.

Serial Port Clock.

Chip Select (Active Low). A pull-up resistor of 100 kΩ to V_DDis recommended to prevent the host processor from

inadvertently waking the ADF7030-1 from sleep.

35

36

37

38

39

40

41

42

GND

Connection to Ground.

Digital GPIO Pin 6.

Digital GPIO Pin 7.

GPIO6

GPIO7

GND

CREG5

GND

Connection to Ground.

Regulator Output 5. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

Connection to Ground.

Positive Reference Input. If a 26 MHz TCXO is used as the external reference, do not connect this pin. If a 26 MHz

XTAL is used as the reference, connect this pin to the XTAL.

HFXTALP

43

HFXTALN

Negative Reference Input. If a 26 MHz TCXO is used as the external reference, connect this pin to the TCXO output.

If a 26 MHz XTAL is used as the reference, connect this pin to the XTAL.

44

45

46

47

48

CREG6

CREG7

GND

CLF

VBAT6

Regulator Output 6. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

Regulator Output 7. Place a 220 nF capacitor between this pin and ground for regulator stability and noise rejection.

Connection to Ground.

External Loop Filter Capacitor. Place a 1.2 nF capacitor between this pin and the CREG1 pin.

Power Supply Pin 6 to the Internal Regulators.

Rev. 0 | Page 26 of 55

Data Sheet

ADF7030-1

TYPICAL PERFORMANCE CHARACTERISTICS

169 MHZ—RECEIVE

100

80

70

60

50

40

30

20

10

0

–120.6dBm

–117.6dBm

–110.6dBm

–50dBm

90

80

70

60

50

40

30

20

10

0

0dBm

IMAGE

FREQUENCY

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.2V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.2V

–10

–3

–2

–1

0

1

2

3

–200 –175 –150 –125 –100 –75 –50 –25

0

25 50 75 100

RF FREQUENCY ERROR (kHz)

INTERFERER FREQUENCY OFFSET (kHz)

Figure 7. Packet Error Rate vs. RF Frequency Error and RF Input Power,

Configuration 169.43125 MHz/2.4 kbps; AFC Enabled; V_DD= 3.0 V;

T_A= 25°C

Figure 10. Receiver Close-In Blocking vs. Interferer Frequency Offset, Temperature,

and V_DD; Configuration 169.43125 MHz/2.4 kbps; Unmodulated Interferer;

Desired Signal 3 dB Above the Sensitivity Level of BER = 0.1%; BER-Based Test

110

100

90

100

–119dBm

–116dBm

–109dBm

–50dBm

0dBm

90

80

70

60

50

40

30

20

10

0

80

70

+85°C, 3.6V

+85°C, 3.0V

60

+85°C, 2.2V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.2V

50

40

30

20

10

0

–10

–3

–2

–1

0

1

2

3

RF FREQUENCY ERROR (kHz)

INTERFERER FREQUENCY OFFSET (kHz)

Figure 8. Packet Error Rate vs. RF Frequency Error and RF Input Power,

Configuration 169.43125 MHz/4.8 kbps; AFC Enabled; V_DD= 3.0 V;

T_A= 25°C

Figure 11. Receiver Wideband Blocking vs. Interfer Frequency Offset,

Temperature, and V_DD; Configuration 169.43125 MHz/2.4 kbps;

Unmodulated Interferer; Desired Signal 3 dB Above the Sensitivity Level of

BER = 0.1%; BER-Based Test

2.0

100

+85°C, 3.6V

ERROR

+85°C, 2.2V

+25°C, 3.6V

+25°C, 2.2V

–40°C, 3.6V

STANDARD DEVIATION

90

80

70

1.5

1.0

0.5

–40°C, 2.2V

60

50

40

30

20

10

0

–0.5

–1.0

–1.5

–2.0

0

–125 –124 –123 –122 –121 –120 –119 –118 –117 –116

RECEIVE INPUT POWER (dBm)

RECEIVE POWER (dBm)

Figure 12. Packet RSSI Error vs. Rx Input Power with One-Point Calibration

at −50 dBm, V_DD= 3.0 V, T_A= 25°C, Configuration 169.43125 MHz/2.4 kbps

(Error is Based on the Mean RSSI of 100 Packets)

Figure 9. Packet Error Rate vs. RF Input Power, Temperature and VDD

Configuration 169.43125 MHz/2.4 kbps

Rev. 0 | Page 27 of 55

ADF7030-1

Data Sheet

169 MHZ—TRANSMIT

–110

16

13

–115

10

–120

–125

–130

–135

–140

–145

–150

–155

–160

–165

–170

7

4

1

–2

–5

–8

–11

–14

–17

–20

–23

–26

–29

–32

PA_COARSE = 1

PA_COARSE = 2

PA_COARSE = 3

PA_COARSE = 4

PA_COARSE = 5

PA_COARSE = 6

2

20

200

1k

10k

100k

1M

10M

100M

PA_FINE SETTING

FREQUENCY OFFSET (Hz)

Figure 13. Phase Noise vs. Frequency Offset, RF Frequency = 169.43125 MHz,

PA2 Output Power = 17 dBm, V_DD= 3.0 V, T_A= 25°C

Figure 16. PA1 Output Power vs. PA_FINE Setting and PA_COARSE Setting with

PA_FINE on a Log Scale, RF Frequency = 169.43125 MHz, V_DD= 3.0 V, T_A= 25°C

0.5

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.85V

+25°C, 3.6V

+25°C, 2.85V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.85V

T = 25°C

VBATx = 3V

+85°C, 3.6V

0.4

0.3

+85°C, 3.0V

+85°C, 2.85V

+25°C, 3.6V

+25°C, 2.85V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.85V

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.1

–0.2

–0.3

–0.4

–0.5

–13 –11 –9 –7 –5 –3 –1

1

3

5

7

9

11 13 15 17 19

PA2 OUTPUT POWER (dBm) AT T = 25°C, VBAT = 3.0V

PA1 OUTPUT POWER (dBm)

Figure 17. Change in PA2 Output Power vs. Temperature, and V_DDwith

PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = 169.43125 MHz

Figure 14. Change in PA1 Output Power vs. Temperature, and V_DDwith

PA_COARSE = 6, RF Frequency = 169.43125 MHz; Variation Above 11 dBm Can

Be Improved by Matching the PA for Higher Output Power

45

80

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.85V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.85V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.85V

70

60

50

40

30

20

10

0

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.2V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.2V

40

35

30

25

20

15

10

5

0

–13 –11 –9 –7 –5 –3 –1

1

3

5

7

9

11 13 15 17 19

PA2 OUTPUT POWER (dBm)

PA1 OUTPUT POWER (dBm)

Figure 15. VBATx Supply Current vs. PA1 Output Power, Temperature, and

V_DDwith PA_COARSE = 6, RF Frequency = 169.43125 MHz

Figure 18. VBATx Supply Current vs. PA2 Output Power, Temperature, and V_DD

PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = 169.43125 MHz

,

Rev. 0 | Page 28 of 55

Data Sheet

ADF7030-1

18

3.0

2.5

14

2.0

10

1.5

6

1.0

2

0.5

–2

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–6

–10

–14

–18

PA_COARSE = 5

PA_COARSE = 6

PA_COARSE = 7

PA_COARSE = 8

PA_COARSE = 9

PA_COARSE = 10

–22

2

20

200

0

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

PA_FINE SETTING

TRANSMIT SYMBOL (Bits)

Figure 19. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting

with PA_FINE on a Logarithmic Scale, V_DD= 3.0 V, T_A= 25°C,

RF Frequency = 169 MHz

Figure 21. Transmit Eye Diagram, PA2 Output Power = 17 dBm,

Configuration 169.43125 MHz/2.4 kbps, V_DD= 3.0 V, T_A= 25°C

0

–10

20

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.85V

+25°C, 3.6V

–20

0

+25°C, 3.0V

+25°C, 2.85V

–30

–40

–20

–40

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.85V

–50

–60

–70

–80

–60

–90

–100

–110

–120

–80

–100

ND

RD

TH

10

2

3

4

5

6

7

8

9

–20

–15

–10

–5

0

5

10

15

20

HARMONIC

FREQUENCY OFFSET (kHz)

Figure 22. Transmit Spectrum, PA2 Output Power = 17 dBm,

Configuration 169.43125 MHz/2.4 kbps, V_DD= 3.0 V, T_A= 25°C

Figure 20. Conductive Harmonic Emission Level, PA2 Output Power =

17 dBm, Carrier Unmodulated, RF Frequency = 169.43125 MHz, V_DD= 3.0 V,

T_A= 25°C

Rev. 0 | Page 29 of 55

ADF7030-1

Data Sheet

433 MHZ—RECEIVE

100

90

80

70

60

50

40

30

20

10

0

–108.1dBm

–105.1dBm

–98.1dBm

–50dBm

90

80

70

60

50

40

30

20

10

0

0dBm

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.2V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.2V

–10

–27

–21

–15

–9

–3

3

9

15

21

27

–20

–15

–10

–5

0

5

10

15

20

RF FREQUENCY ERROR (kHz)

INTERFERER FREQUENCY OFFSET (MHz)

Figure 25. Receiver Wideband Blocking vs. Interferer Frequency Offset,

Temperature, and V_DD; Configuration 433 MHz/50 kbps; Unmodulated

Interferer; Desired Signal 3 dB Above the Sensitivity Level of BER = 0.1%;

BER-Based Test

Figure 23. Packet Error Rate vs. RF Frequency Error and RF Input Power;

Configuration 433 MHz/50 kbps, AFC Enabled; V_DD= 3.0 V; T_A= 25°C

100

3

+85°C, 3.6V

+85°C, 2.2V

+25°C, 3.6V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 2.2V

90

80

70

60

50

40

30

20

10

0

AVERAGE ERROR

STANDARD DEVIATION

2

1

0

–1

–2

–3

–115 –114 –113 –112 –111 –110 –109 –108 –107 –106 –105

–113 –103 –93

–83

–73

–63

–53

–43

–33

–23

RECEIVE POWER (dBm)

RECEIVE INPUT POWER (dBm)

Figure 26. Packet RSSI Error vs. RX Input Power with One-Point Calibration at

−77 dBm; Configuration 433 MHz/50 kbps; V_DD= 3.0 V; T_A= 25°C (Error is

Based on the Mean RSSI of 100 Packets)

Figure 24. Packet Error Rate vs. RF Input Power, Temperature, and V_DD

Configuration 433 MHz/50 kbps

;

Rev. 0 | Page 30 of 55

Data Sheet

ADF7030-1

433 MHZ—TRANSMIT

–100

16

13

–105

10

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

7

4

1

–2

–5

–8

–11

–14

–17

–20

–23

–26

–29

–32

PA_COARSE = 1

PA_COARSE = 2

PA_COARSE = 3

PA_COARSE = 4

PA_COARSE = 5

PA_COARSE = 6

2

20

200

1k

10k

100k

1M

10M

100M

PA_FINE SETTING

FREQUENCY OFFSET (Hz)

Figure 27. Phase Noise vs. Frequency Offset, RF Frequency = 433 MHz, PA1 Output

Power = 10 dBm, V_DD= 3.0 V, T_A= 25°C

Figure 30. PA1 Output Power vs. PA_FINE Setting and PA_COARSE Setting with

PA_FINE on a Logarithmic Scale, RF Frequency = 433 MHz, V_DD= 3.0 V, T_A= 25°C

0.5

0

–10

T = 25°C

VBATx = 3V

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.85V

+25°C, 3.6V

+25°C, 2.85V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.85V

0.4

0.3

–20

–30

0.2

–40

0.1

–50

0

–60

–70

–0.1

–0.2

–0.3

–0.4

–0.5

–80

–90

–100

–110

–120

ND

RD

TH

10

2

3

4

5

6

7

8

9

HARMONIC

PA1 OUTPUT POWER (dBm)

Figure 28. Change in PA1 Output Power vs. Temperature, and V_DDwith

PA_COARSE = 6, RF Frequency = 433 MHz

Figure 31. Conductive Harmonic Emission Level, PA1 Output Power =

10 dBm, RF Frequency = 433.92 MHz, V_DD= 3.0 V, T_A= 25°C

50

30

25

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.2V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.2V

45

40

35

30

25

20

15

10

5

20

15

10

5

0

–5

–10

–15

–20

–25

–30

0

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

TRANSMIT SYMBOL (Bits)

PA1 OUTPUT POWER (dBm)

Figure 29. VBATx Supply Current vs. PA1 Output Power, Temperature, and

_DDwith PA_COARSE = 6, RF Frequency = 433 MHz

Figure 32. Transmit Eye Diagram, PA2 Output Power = 17 dBm,

Configuration 433 MHz/50 kbps, V_DD= 3.0 V, T_A= 25°C

V

Rev. 0 | Page 31 of 55

ADF7030-1

Data Sheet

10

0

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.85V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.85V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.85V

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–300

–200

–100

0

100

200

300

FREQUENCY OFFSET (kHz)

Figure 33. Transmit Spectrum, PA1 Output Power = 10 dBm, Configuration

433 MHz/50 kbps, V_DD= 3.0 V, T_A= 25°C

Rev. 0 | Page 32 of 55

Data Sheet

ADF7030-1

460 MHZ—RECEIVE

100

110

100

90

80

70

60

50

40

30

20

10

0

–116.7dBm

–113.7dBm

–106.7dBm

–50dBm

90

80

70

60

50

40

30

20

10

0

0dBm

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.2V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.2V

–10

–3

–2

–1

0

1

2

3

RF FREQUENCY ERROR (kHz)

INTERFERER FREQUENCY OFFSET (kHz)

Figure 34. Packet Error Rate vs. RF Frequency Error and RF Input Power;

Configuration 460 MHz/7.2 kbps; AFC Enabled; V_DD= 3.0 V; T_A= 25°C

Figure 37. Receiver Wideband Blocking vs. Inteferer Frequency Offset,

Temperature, and V_DD; Configuration 460 MHz/7.2 kbps; Unmodulated

Interferer; Desired Signal 3 dB Above the Sensitivity Level of BER = 0.1%;

BER-Based Test

100

3

+85°C, V

+25°C, V

–40°C, V

3.6V

2.2V

3.6V

2.2V

3.6V

2.2V

DD

90

80

70

60

50

40

30

20

10

0

AVERAGE ERROR

2

STANDARD DEVIATION

1

0

–1

–2

–3

–123 –122 –121 –120 –119 –118 –117 –116 –115 –114 –113

–122 –123 –102 –92 –82 –72 –62 –52 –42 –32 –22 –12

RECEIVE POWER (dBm)

RECEIVE INPUT POWER (dBm)

Figure 38. Packet RSSI Error vs. RF Input Power with One-Point Calibration at

−77 dBm; Configuration 460 MHz/7.2 kbps, 7.2 kbps; V_DD= 3.0 V; T_A= 25°C

(Error is Based on the Mean RSSI of 100 Packets)

Figure 35. Packet Error Rate vs. RF Input Power, Temperature, and V_DD

Configuration 460 MHz/7.2 kbps

;

75

65

55

45

35

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.2V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.2V

25

15

5

–5

–15

–100 –80 –60 –40 –20

0

20

40

60

80

100

INTERFERER FREQUENCY OFFSET (kHz)

Figure 36. Receiver Close-In Blocking vs. Interferer Frequency Offset and

Temperature and V_DD; Configuration 460 MHz/7.2 kbps; Unmodulated

Interferer; Desired Signal 3 dB Above the Sensitivity Level of BER = 0.1%;

BER-Based Test

Rev. 0 | Page 33 of 55

ADF7030-1

Data Sheet

460 MHZ—TRANSMIT

–100

18

14

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

10

6

2

–2

–6

PA_COARSE = 5

PA_COARSE = 6

PA_COARSE = 7

PA_COARSE = 8

PA_COARSE = 9

PA_COARSE = 10

–10

–14

–18

2

20

200

1k

10k

100k

1M

10M

100M

PA_FINE SETTING

FREQUENCY OFFSET (Hz)

Figure 39. Phase Noise vs. Frequency Offset, RF Frequency = 460 MHz, PA2 Output

Power = 17 dBm, V_DD= 3.0 V, T_A= 25°C

Figure 42. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting

with PA_FINE on a Logarithmic Scale, PAOLDO_VOUT_CON=15,

RF Frequency = 460 MHz, V_DD= 3.0 V, T_A= 25°C

0

0.5

FUNDAMENTAL = 450.0125MHz

T = 25°C

VBATx = 3V

FUNDAMENTAL = 460MHz

–10

–20

0.4

FUNDAMENTAL = 469.9875MHz

0.3

0.2

0.1

0

–30

–40

–50

–60

–70

–0.1

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.85V

+25°C, 3.6V

–80

–0.2

–90

–0.3

–0.4

–0.5

+25°C, 2.85V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.85V

–100

–110

–120

ND

RD

TH

10

2

3

4

5

6

7

8

9

–11 –9 –7 –5 –3 –1

1

3

5

7

9

11 13 15 17 19

HARMONIC

PA2 OUTPUT POWER (dBm)

Figure 40. Change in PA2 Output Power vs. Temperature, and V_DDwith

PA_COARSE = 10, PAOLDO_VOUT_CON=15, RF Frequency = 460 MHz; Variation

Above 15 dBm Can Be Improved by Matching the PA for Higher Output Power

Figure 43. Conductive Harmonic Emission Level, PA2 Output Power =

17 dBm, RF Frequency = 460 MHz, V_DD= 3.0 V, T_A= 25°C

30

25

60

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.85V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.85V

50

40

30

20

10

0

20

15

10

0

–10

–15

–20

–25

–30

0

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

–11 –9 –7 –5 –3 –1

1

3

5

7

9

11 13 15 17 19

TRANSMIT SYMBOL (Bits)

PA2 OUTPUT POWER (dBm)

Figure 41. VBATx Supply Current vs. PA2 Output Power, Temperature, and

V_DDwith PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = 460 MHz

Figure 44. Transmit Eye Diagram; PA2 Output Power = 17 dBm; Configuration

460 MHz/7.2 kbps; BT = 0.5; V_DD= 3.0 V; T_A= 25°C

Rev. 0 | Page 34 of 55

Data Sheet

ADF7030-1

20

10

0

–10

–20

–30

–40

–50

–60

–70

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.85V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.85V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.85V

FCC 90 MASK D

–50 –40 –30 –20 –10

0

10

20

30

40

50

FREQUENCY OFFSET (kHz)

Figure 45. Transmit Spectrum, PA2 Output Power = 17 dBm, Configuration

460 MHz/7.2 kbps, BT = 0.5, V_DD= 3.0 V, T_A= 25°C; Margin to the Mask Can Be

Improved by Reducing the BT or By Reducing the Data Rate

Rev. 0 | Page 35 of 55

ADF7030-1

Data Sheet

868 MHZ—RECEIVE

100

90

80

70

60

50

40

30

20

10

0

+85°C, 3.6V

+85°C, 2.2V

+25°C, 3.6V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 2.2V

–119.3dBm

–116.3dBm

–109.3dBm

–50dBm

90

80

70

60

50

40

30

20

10

0

0dBm

–4

–3

–2

–1

0

1

2

3

4

–113 –112 –111 –110 –109 –108 –107 –106 –105 –104 –103

RF FREQUENCY ERROR (kHz)

RECEIVE POWER (dBm)

Figure 46. Packet Error Rate vs. RF Frequency Error and RF Input Power,

Configuration 868 MHz/4.8 kbps, AFC Enabled, V_DD= 3.0 V, T_A= 25°C

Figure 49. Packet Error Rate vs. Rx Input Power, Temperature, and V_DD

Configuration 868 MHz/100 kbps

;

100

60

50

–108.1dBm

–105.1dBm

–98.1dBm

–50dBm

0dBm

90

80

70

60

50

40

30

20

10

0

40

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.2V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.2V

30

20

10

0

–10

–20

–50 –40 –30 –20 –10

0

10

20

30

40

50

RF FREQUENCY ERROR (kHz)

INTERFERER FREQUENCY OFFSET (kHz)

Figure 47. Packet Error Rate vs. RF Frequency Error and RF Input Power,

Configuration 868 MHz/100 kbps, AFC Enabled, V_DD= 3.0 V, T_A= 25°C

Figure 50. Receiver Close-In Blocking vs. Interferer Frequency Offset, Temperature,

and V_DD; Configuration 868 MHz/4.8 kbps, Unmodulated Interferer; Desired

Signal 3 dB Above the Sensitivity Level of BER = 0.1%, BER-Based Test

100

105

95

85

75

65

55

+85°C, 3.6V

+85°C, 2.2V

+25°C, 3.6V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 2.2V

90

80

70

60

50

40

30

20

10

0

+85°C, 3.6V

+85°C, 3.0V

45

35

25

15

5

+85°C, 2.2V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.2V

–5

–15

–125 –124 –123 –122 –121 –120 –119 –118 –117 –116 –115

RECEIVE POWER (dBm)

INTERFERER FREQUENCY OFFSET (MHz)

Figure 48. Packet Error Rate vs. RF Input Power, Temperature, and V_DD

Configuration 868 MHz/4.8 kbps

;

Figure 51. Receiver Wideband Blocking vs. Interferer Frequency Offset,

Temperature, and V_DD; Configuration 868 MHz/4.8 kbps, Unmodulated

Interferer; Desired Signal 3 dB Above the Sensitivity Level of BER = 0.1%;

BER-Based Test

Rev. 0 | Page 36 of 55

Data Sheet

ADF7030-1

95

85

75

65

55

45

35

25

15

5

3

2

AVERAGE ERROR

STANDARD DEVIATION

1

+85°C, 3.6V

+85°C, 3.0V

+85°C, 2.2V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.2V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.2V

0

–1

–2

–3

–5

–15

–110 –100 –90

–80

–70

–60

–50

–40

–30

–20

RECEIVE INPUT POWER (dBm)

INTERFERER FREQUENCY OFFSET (MHz)

Figure 54. Packet RSSI Error vs. Rx Input Power with One-Point Calibration at

−70 dBm; Configuration 868 MHz/100 kbps; V_DD= 3.0 V; T_A= 25°C (Error is

Based on the Mean RSSI of 100 Packets)

Figure 52. Receiver Wideband Blocking vs. Interferer Frequency Offset,

Temperature, V_DD; Configuration 868 MHz/100 kbps; Unmodulated

Interferer; Desired Signal 3 dB Above the Sensitivity Level of BER = 0.1%;

BER-Based Test

3

AVERAGE ERROR

STANDARD DEVIATION

2

1

0

–1

–2

–3

–122 –112 –102 –92 –82 –72 –62 –52 –42 –32 –22 –12

RECEIVE INPUT POWER (dBm)

Figure 53. Packet RSSI Error vs. Rx Input Power with One-Point Calibration at

−77 dBm; Configuration 868 MHz/4.8 kbps; V_DD= 3.0 V; T_A= 25°C (Error is

Based on the Mean RSSI of 100 Packets)

Rev. 0 | Page 37 of 55

ADF7030-1

Data Sheet

868 MHZ—TRANSMIT

–100

60

50

40

30

20

10

0

–40°C, 2.2V

–40°C, 3.0V

–40°C, 3.6V

+25°C, 2.2V

+25°C, 3.0V

+25°C, 3.6V

+85°C, 2.2V

+85°C, 3.0V

+85°C, 3.6V

–110

–120

–130

–140

–150

–160

1k

10k

100k

1M

10M

100M

–17 –15 –13 –11 –9 –7 –5 –3 –1

1

3

5

7

9

11 13 15

FREQUENCY OFFSET (Hz)

PA1 OUTPUT POWER (dBm)

Figure 55. Phase Noise vs. Frequency Offset, RF Frequency = 868 MHz, PA2

Output Power = 17 dBm, V_DD= 3.0 V, T_A= 25°C

Figure 58. VBATx Supply Current vs. PA1 Output Power, Temperature, and

V_DDwith PA_COARSE = 6, RF Frequency = 868 MHz

0.5

80

T = 25°C

VBATx = 3V

–40°C, 2.85V

–40°C, 3.0V

+85°C, 3.6V

+85°C, 3.0V

0.4

–40°C, 3.6V

+25°C, 2.85V

+25°C, 3.0V

+25°C, 3.6V

+85°C, 2.85V

+85°C, 3.0V

+85°C, 3.6V

70

60

50

40

30

20

10

0

+85°C, 2.85V

+25°C, 3.6V

0.3

+25°C, 2.85V

–40°C, 3.6V

0.2

–40°C, 3.0V

–40°C, 2.85V

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

13 11

9

7

5

3

1

3

5

7

9

11 13 15 17 19

PA1 OUTPUT POWER (dBm)

PA2 OUTPUT POWER (dBm)

Figure 59. VBATx Supply Current vs. PA2 Output Power, Temperature, and

V_DDwith PA_COARSE = 10, RF Frequency = 868 MHz

Figure 56. Change in PA1 Output Power vs. Temperature, and V_DDwith

PA_COARSE = 10, RF Frequency = 868 MHz

17

0.5

PA_COARSE = 1

–40°C, 2.85V

–40°C, 3.0V

–40°C, 3.6V

+25°C, 2.85V

+25°C, 3.6V

+85°C, 2.85V

+85°C, 3.0V

+85°C, 3.6V

T = 25°C

VBATx = 3V

PA_COARSE = 2

PA_COARSE = 3

PA_COARSE = 4

PA_COARSE = 5

PA_COARSE = 6

13

9

0.4

0.3

5

0.2

1

0.1

–3

–7

0

–11

–15

–19

–23

–27

–31

–0.1

–0.2

–0.3

–0.4

–0.5

2

20

200

13 11

9

7

5

3

1

3

5

7

9

11 13 15 17 19

PA_FINE SETTING

PA2 OUTPUT POWER (dBm)

Figure 60. PA1 Output Power vs. PA_FINE Setting and PA_COARSE Setting

with PA_FINE on a Logarithmic Scale, RF Frequency = 868 MHz, V_DD= 3.0 V,

T_A= 25°C

Figure 57. Change in PA2 Output Power vs. Temperature, and V_DDwith

PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = 868 MHz

Rev. 0 | Page 38 of 55

Data Sheet

ADF7030-1

19

17

15

13

11

9

3.0

2.5

2.0

1.5

7

5

1.0

0.5

3

1

0

–1

–3

–5

–7

–9

–11

–13

–15

–17

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

PA_COARSE = 5

PA_COARSE = 6

PA_COARSE = 7

PA_COARSE = 8

PA_COARSE = 9

PA_COARSE = 10

–19

2

20

200

0

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

PA_FINE SETTING

TRANSMIT SYMBOL (Bits)

Figure 61. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting

with PA_FINE on a Logarithmic Scale, PAOLDO_VOUT_CON = 15, RF Frequency =

868 MHz, V_DD= 3.0 V, T_A= 25°C

Figure 63. Transmit Eye Diagram, PA2 Output Power = 17 dBm,

Configuration 868 MHz/4.8 kbps; V_DD= 3.0 V; T_A= 25°C

0

20

FUNDAMENTAL = 863MHz

+85°C, 3.6V

FUNDAMENTAL = 868MHz

FUNDAMENTAL = 876MHz

–10

–20

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

+85°C, 3.0V

+85°C, 2.85V

+25°C, 3.6V

+25°C, 3.0V

+25°C, 2.85V

–40°C, 3.6V

–40°C, 3.0V

–40°C, 2.85V

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

ND

RD

TH

10

2

3

4

5

6

7

8

9

–40

–30

–20

–10

0

10

20

30

40

HARMONIC

FREQUENCY OFFSET (kHz)

Figure 62. Conductive Harmonic Emission Level, PA2 Output Power =

17 dBm, RF Frequency = 868 MHz, V_DD= 3.0 V, T_A= 25°C

Figure 64. Transmit Spectrum vs. Temperature, and V_DDwith PA2 Output

Power = 17 dBm, Configuration 868 MHz/4.8 kbps, V_DD= 3.0 V; T_A= 25°C

Rev. 0 | Page 39 of 55

ADF7030-1

Data Sheet

915 MHZ—RECEIVE

100

90

80

70

60

50

40

30

20

10

0

100

–108.6dBm

–105.6dBm

–98.6dBm

–50dBm

90

80

70

60

50

40

30

20

10

0dBm

–40°C, 2.2V

–40°C, 3.6V

+25°C, 2.2V

+25°C, 3.6V

+85°C, 2.2V

+85°C, 3.6V

0

–50 –40 –30 –20 –10

0

10

20

30

40

50

–107 –106 –105 –104 –103 –102 –101 –100 –99 –98 –97

RF FREQUENCY ERROR (kHz)

RECEIVE POWER (dBm)

Figure 65. Packet Error Rate vs. RF Frequency Error and RF Input Power;

Configuration 915 MHz/50 kbps; AFC Enabled; V_DD= 3.0 V; T_A= 25°C

Figure 68. Packet Error Rate vs. Rx Input Power, Temperature, and V_DD

Configuration 915 MHz/150 kbps; FEC Disabled; AFC Enabled

;

100

–101.2dBm

–40°C, 2.2V

–98.2dBm

–40°C, 3.6V

90

–91.2dBm

+25°C, 2.2V

–50dBm

+25°C, 3.6V

80

70

60

50

40

30

20

10

0

0dBm

80

70

60

50

40

30

20

10

0

+85°C, 2.2V

+85°C, 3.6V

–60

–40

–20

0

20

40

60

–108 –107 –106 –105 –104 –103 –102 –101 –100 –99 –98

RF FREQUENCY ERROR (kHz)

RECEIVE POWER (dBm)

Figure 66. Packet Error Rate vs. RF Frequency Error and RF Input Power;

Configuration 915 MHz/150 kbps; AFC Enabled; V_DD= 3.0 V; T_A= 25°C

Figure 69. Packet Error Rate vs. Rx Power, Temperature, and V_DD

Configuration 915 MHz/300 kbps; AFC Disabled

;

100

90

80

70

60

50

40

–101.9dBm

–98.9dBm

90

–91.9dBm

–50dBm

0dBm

80

70

60

50

40

30

20

10

0

30

+25°C, 2.2V

+25°C, 3.0V

20

10

+25°C, 3.6V

–40°C, 2.2V

–40°C, 3.0V

–40°C, 3.6V

+85°C, 2.2V

+85°C, 3.0V

+85°C, 3.6V

0

–10

–27

–60

–40

–20

0

20

40

60

–21

–15

–9

–3

3

9

15

21

27

RF FREQUENCY ERROR (kHz)

INTERFERER FREQUENCY OFFSET (MHz)

Figure 70. Receiver Wideband Blocking vs. Interferer Frequency Offset,

Temperature, and V_DD; Configuration 915 MHz/150 kbps; Unmodulated

Interferer; Desired Signal 3 dB Above the Sensitivity Level of BER = 0.1%;

BER-Based Test

Figure 67. Packet Error Rate vs. RF Frequency Error and RF Input Power;

Configuration 915 MHz/300 kbps; AFC Disabled; V_DD= 3.0 V; T_A= 25°C

Rev. 0 | Page 40 of 55

Data Sheet

ADF7030-1

3

2

–40°C, 2.2V

–40°C, 3.6V

+25°C, 2.2V

+25°C, 3.6V

+85°C, 2.2V

+85°C, 3.6V

AVERAGE ERROR

STANDARD DEVIATION

2

1

0

–1

–2

–3

–1

–2

–3

–105

–95

–85

–75

–65

–55

–45

–35

–25

–105

–95

–85

–75

–65

–55

–45

–35

–25

RECEIVE INPUT POWER (dBm)

Figure 71. Packet RSSI Error vs. Rx Input Power with One-Point Calibration at

−70 dBm; Configuration 915 MHz/150 kbps; V_DD= 3.0 V; T_A= 25°C (Error is

Based on the Mean RSSI of 100 Packets)

Figure 73. CCA (RSSI) Standard Deviation vs. Rx Input Power, Temperature

and VDD, with One-Point Calibration at −70 dBm (VDD = 2.2 V, T_A= 25°C);

Unmodulated RF Signal; Configuration 915 MHz/150 kbps (Standard

Deviation is Based on 100 CCA Operations)

3

–40°C, 2.2V

–40°C, 3.6V

+25°C, 2.2V

+25°C, 3.6V

+85°C, 2.2V

+85°C, 3.6V

2

1

0

–1

–2

–3

–105

–95

–85

–75

–65

–55

–45

–35

–25

RECEIVE INPUT POWER (dBm)

Figure 72. CCA (RSSI) Error vs. Rx Input Power, Temperature, and V_DDwith

One-Point Calibration at −70 dBm (VDD = 2.2 V, T_A= 25°C); Unmodulated RF

Signal; Configuration 915 MHz/150 kbps (Error is Based on the Mean of

100 CCA Operations)

Rev. 0 | Page 41 of 55

ADF7030-1

Data Sheet

915 MHZ—TRANSMIT

–100

19

17

15

13

11

9

7

5

3

1

–1

–3

–5

–7

–9

–11

–13

–15

–17

–19

PA_COARSE = 5

PA_COARSE = 6

PA_COARSE = 7

PA_COARSE = 8

PA_COARSE = 9

PA_COARSE = 10

–110

–120

–130

–140

–150

–160

2

20

200

1k

10k

100k

1M

10M

100M

PA_FINE SETTING

FREQUENCY OFFSET (Hz)

Figure 74. Phase Noise vs. Frequency Offset, RF Frequency = 915 MHz, PA2

Output Power = 17 dBm, V_DD= 3.0 V, T_A= 25°C

Figure 77. PA2 Output Power vs. PA_FINE Setting and PA_COARSE Setting

with PA_FINE on a Logarithmic Scale, PAOLDO_VOUT_CON = 15, RF

Frequency = 915 MHz, V_DD= 3.0 V, T_A= 25°C

0

0.5

FUNDAMENTAL = 902.2MHz

FUNDAMENTAL = 915MHz

FUNDAMENTAL = 927.8MHz

–40°C, 2.85V

–40°C, 3.0V

–40°C, 3.6V

+25°C, 2.85V

+25°C, 3.6V

+85°C, 2.85V

+85°C, 3.0V

+85°C, 3.6V

T = 25°C

VBATx = 3V

–10

–20

0.4

0.3

–30

0.2

–40

0.1

–50

–60

0

–70

–0.1

–0.2

–0.3

–0.4

–0.5

–80

–90

–100

–110

–120

ND

RD

TH

10

2

3

4

5

6

7

8

9

–12

–9

–6

–3

0

3

6

9

12

15

18

HARMONIC

PA2 OUTPUT POWER (dBm)

Figure 78. Conductive Harmonic Emission Level, PA2 Output Power =

17 dBm, RF Frequency = 915 MHz, V_DD= 3.0 V, T_A= 25°C

Figure 75. Change in PA2 Output Power vs. Temperature, and V_DDwith

PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = 915 MHz

60

50

80

–40°C, 2.85V

–40°C, 3.0V

–40°C, 3.6V

+25°C, 2.85V

+25°C, 3.0V

+25°C, 3.6V

+85°C, 2.85V

+85°C, 3.0V

+85°C, 3.6V

70

60

50

40

30

20

10

0

40

30

20

10

0

–10

–20

–30

–40

–50

–60

0

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

–13 –11 –9 –7 –5 –3 –1

1

3

5

7

9

11 13 15 17 19

TRANSMIT SYMBOL (Bits)

PA2 OUTPUT POWER (dBm)

Figure 79. Transmit Eye Diagram, PA2 Output Power = 17 dBm,

Configuration 915 MHz/150 kbps, V_DD= 3.0 V, T_A= 25°C

Figure 76. VBATx Supply Current vs. PA2 Output Power, Temperature, and

_DDwith PA_COARSE = 10, PAOLDO_VOUT_CON = 15, RF Frequency = 915 MHz

V

Rev. 0 | Page 42 of 55

Data Sheet

ADF7030-1

200

150

100

50

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+25°C, 2.2V

+25°C, 3.0V

+25°C, 3.6V

–40°C, 2.2V

–40°C, 3.0V

–40°C, 3.6V

+85°C, 2.2V

+85°C, 3.0V

+85°C, 3.6V

0

–50

–100

–150

–200

–900 –700 –500 –300 –100 100

300

500

700

900

0

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

FREQUENCY OFFSET (kHz)

TRANSMIT SYMBOL (Bits)

Figure 80. Transmit Eye Diagram, PA2 Output Power = 17 dBm,

Configuration 915 MHz/300 kbps, V_DD= 3.0 V, T_A= 25°C

Figure 82. Transmit Spectrum vs. Temperature, and VDDPA2 Output Power =

17 dBm, Configuration 915 MHz/300 kbps; V_DD= 3.0 V; T_A= 25°C

0

+25°C, 2.2V

+25°C, 3.0V

–10

+25°C, 3.6V

–40°C, 2.2V

–40°C, 3.0V

–40°C, 3.6V

+85°C, 2.2V

+85°C, 3.0V

+85°C, 3.6V

–20

–30

–40

–50

–60

–70

–80

–90

–600

–400

–200

0

200

400

600

FREQEUNCY OFFSET (kHz)

Figure 81. Transmit Spectrum, PA2 Output Power = 17 dBm,

Configuration: 915 MHz/150 kbps, V_DD= 3.0 V, T_A= 25°C

Rev. 0 | Page 43 of 55

ADF7030-1

Data Sheet

THEORY OF OPERATION

The ADF7030-1 processor handles the sequencing of various

radio circuits and critical timing functions, thereby simplifying

radio operation and easing the burden on the host processor.

STATE MACHINE

The ADF7030-1 operates as a simple state machine as

illustrated in Figure 83. The host processor can transition the

ADF7030-1 between states by issuing single-byte commands

over the SPI interface.

The ADF7030-1 states are described in Table 24.

RTC ALARM

COLD START

(BATTERY APPLIED)

GPIO WAKEUP/CS LOW

CMD_CFG_DEV (0x85)

CMD_PHY_SLEEP (0x80)

PHY_SLEEP

PHY_OFF

(0x01)

CONFIGURING (0x05)

MONITORING

(0x0A)

NOTE THAT THE CALIBRATION FIRMWARE

MODULE MUST BE DOWNLOADED BEFORE

THE CMD_DO_CAL COMMAND IS SUPPORTED

CALIBRATING

(0x09)

CMD_CCA (0x86)

PHY_ON

(0x02)

CMD_PHY_ON (0x82)

CCA

(0x06)

BUSY CHANNEL

TX_EOF

RX_EOF

CMD_PHY_TX (0x84)

PHY_RX

PHY_TX

(0x04)

(0x03)

CMD_PHY_RX (0x83)

CMD_PHY_TX (0x84)

RX_TO_TX_AUTO_TURNAROUND

CMD_PHY_RX (0x83)

TX_TO_RX_AUTO_TURNAROUND

KEY

TRANSITION TRIGGERED BY A RADIO COMMAND

TRANSITION TRIGGERED BY ADF7030-1

META STATE (FOR EXAMPLE, RETURN FROM THIS STATE TO THE PREVIOUS

STATE IS TRIGGERED BY THE ADF7030-1)

STATES REQUIRING A FIRMWARE MODULE DOWNLOAD

RADIO STATE

Figure 83. Radio State Machine Diagram

Table 24. Radio States

State

Description

Typical Current

10 nA

PHY_SLEEP In this state, the ADF7030-1 is in sleep. Memory can be optionally retained.

PHY_OFF

PHY_ON

PHY_RX

PHY_TX

CCA

In this state, the ADF7030-1 executes using its own internal oscillator clock. The host

configures the radio from this state.

In this state, the external reference clock source is enabled. After entering this state,

the ADF7030-1 is ready for the transmission and reception of packets.

In this state, the ADF7030-1 can receive and process an incoming packet.

In this state, the ADF7030-1 transmits the programmed packet data.

In this state, the ADF7030-1 performs clear channel assessment.

3.7 mA

21 mA to 25.4 mA (RF frequency

and data rate dependent)

16 mA to 65 mA (RF frequency and

Tx power dependent)

21 mA to 25.4 mA (frequency and

data rate dependent)

Rev. 0 | Page 44 of 55

Data Sheet

ADF7030-1

RADIO TIMING

Table 25. Radio Timing Specifications

Transition Time

(μs), Typical at

Data Rate =

2.4 kbps

Transition Time

(μs), Typical at

Data Rate =

300 kbps

Present

State

Command

Initiated By

Next State Command/Bit

Condition

PHY_SLEEP PHY_OFF

Wakeup from

Automatic

101

None

PHY_SLEEP (RTC

timeout event)

PHY_SLEEP PHY_OFF

Wakeup from

PHY_SLEEP (CS low)

Host

101

95

101

95

From CS low to PHY_OFF

PHY_OFF

PHY_SLEEP CMD_PHY_SLEEP

From CS low to

PHY_SLEEP, memory

retention enabled

First transition after cold

start or wake from

PHY_SLEEP, subsequent

transitions; 26 MHz TCXO

reference

First transition after cold

start or wake from

PHY_SLEEP, subsequent

transitions; 26 MHz XTAL

reference

RTC not enabled

None

PHY_ON

PHY_OFF

CMD_PHY_ON

CMD_CFG_DEV

Host

206, 188

490, 188

206, 188

490, 188

PHY_OFF

PHY_ON

CCA

Host

36

30

19

30000

230

245

223

46

36

30

19

30000

230

245

225

46

PHY_SLEEP CMD_PHY_SLEEP

PHY_OFF

PHY_ON

CCA

PHY_TX

PHY_RX

PHY_ON

PHY_TX

CMD_PHY_OFF

CMD_LFRC_CAL

CMD_CCA

CMD_PHY_TX

CMD_PHY_RX

CMD_PHY_ON

Channel busy

Clear channel

None

To receiver enabled

To start of PA ramp

To receiver enabled

None

From receiver disabled

From receiver disabled to

start of PA ramp

CCA

Automatic

16

208

16

203

CCA

PHY_TX

PHY_ON

PHY_TX

CMD_PHY_TX

CMD_PHY_ON

TX_EOF

Host

239

36

239

36

From receiver disabled to

start of PA ramp

From PA ramp finished to

PHY_ON

From PA ramp finished to

PHY_ON

From start of PA ramp

down (at fastest PA ramp

rate) to start of PA ramp

up on new channel

PHY_TX

Host

Automatic

Host

26

CMD_PHY_TX

258

231

PHY_TX

PHY_RX

CMD_PHY_RX

Host

204

208

From PA ramp finished to

receiver enabled

From PA ramp finished to

receiver enabled

Autoturnaround

Automatic

PHY_RX

PHY_ON

CMD_PHY_ON

RX_EOF

Host

Automatic

46

32

46

32

None

From end of frame IRQ to

PHY_ON

PHY_RX

PHY_TX

CMD_PHY_RX

Autoturnaround

CMD_PHY_TX

Host

216

220

203

220

203

From CS high to receiver

enabled on new channel

From end of frame IRQ to

start of PA ramp

From CS high to start of

PA ramp

Automatic

Host

Rev. 0 | Page 45 of 55

ADF7030-1

Data Sheet

Status Byte

HOST INTERFACE

Physical Interface

The ADF7030-1 reports the status via a status byte. The

ADF7030-1 returns this byte on the SPI MISO in response

to a no operation command (NOP) (0xFF) on the SPI MOSI.

The ADF7030-1 provides a simple host interface (HIF) that

consists of a 4-wire standard SPI, a hardware reset pin (

RST

)

and GPIOs. The ADF7030-1 always acts as a slave to the host

processor. The host uses the SPI to read and write ADF7030-1

memory and registers, to issue commands, to track the status of

the state machine, and to wake up the ADF7030-1 from

PHY_SLEEP.

RECEIVER

The ADF7030-1 features a fully integrated, highly configurable

receiver that enables exceptionally high performance reception

of narrow-band and wideband 2FSK/2GFSK signals. The receiver

is based on a low IF architecture. Figure 84 shows a simplified

block diagram of the receiver.

Host Interface Protocol

The ADF7030-1 implements a very simple protocol over the SPI

interface. Using this protocol, the host processor can perform a

number of operations, as described in the Memory Access section,

the Radio Commands section, and the Status Byte section.

RF Front End

The receive signal is amplified by a differential LNA. The LNA

is followed by a quadrature downconversion mixer that converts

the RF signal to the IF frequency. The automatic gain control

(AGC) circuit automatically controls the gain of the RF front

end. The fully integrated, fractional-N frequency synthesizer

generates the LO for the mixer. When the ADF7030-1 enters the

PHY_RX state, the bandwidth of the synthesizer is set automati-

cally to ensure optimum interference rejection performance.

Memory Access

The memory access commands allow the host processor to read

from and write to the internal memory of the ADF7030-1.

Typically, the host uses these commands to update the configura-

tion of the ADF7030-1 and to write packets for transmission or

to read received packets.

IF Processing

The quadrature IF signal is band-pass filtered using a high

performance, configurable analog filter. The filter is followed by

a programmable gain array (PGA) that is controlled by the

AGC circuit.

Radio Commands

A state machine command triggers a change of radio state as

described in Table 26.

Table 26. State Machine Radio Commands

The ADF7030-1 features a narrow-band and wideband IF

processing path. In the narrow-band path, the IF signal is

digitized by a high performance, high dynamic range analog-to-

digital converter (ADC). RSSI, decimation, and offset

correction are performed before the digitized IF is filtered using

a configurable narrow-band digital channel filter.

Command

Description

CMD_PHY_SLEEP

Performs a transition of the device into the

PHY_SLEEP state

CMD_PHY_OFF

CMD_PHY_ON

CMD_PHY_RX

CMD_PHY_TX

CMD_CFG_DEV

CMD_CCA

Performs a transition of the device into the

PHY_OFF state

Performs a transition of the device into the

PHY_ON state

Performs a transition of the device into the

PHY_RX state

Performs a transition of the device into the

PHY_TX state

Configures the ADF7030-1 based on the

radio profile

Performs a transition of the device into the

CCA state

In the wideband path, a limiter converts the IF signal to digital

levels for the demodulator. The limiter also provides offset

correction and RSSI, which is digitized using the ADC.

CMD_DO_CAL

Executes selected calibration routines;

requires the OffLineCalibrations.cfg

firmware module

CMD_MON

Measures and reports the ADF7030-1

temperature

CMD_LFRC_CAL

Performs a frequency calibration of the

internal 26kHz RC oscillator; requires the

OffLineCalibrations.cfg firmware module

Rev. 0 | Page 46 of 55

Data Sheet

ADF7030-1

AGC

NARROW-BAND Rx PATH

I

ADC

QEC

LNAIN1

LNAIN2

LNA

OCL

RSSI

Q

ADC

2FSK/2GFSK

DEMOD

PGA

CDR

SERDES

Rx DATA

TO Cortex-M0

PROCESSOR

RF

SYNTHESIZER

AFC

LIMITER,

OCL

RSSI

WIDEBAND Rx PATH

Figure 84. Receiver Block Diagram

Table 27 and Table 28 list the supported channel bandwidths and

IF frequencies. The ADF7030-1 graphic user interface (GUI)

automatically chooses the correct receive path, channel bandwidth,

and IF frequency based on the data rate and modulation settings.

Table 28. Wideband Rx Path Channel Bandwidths and IFs

Channel BW (kHz)

IF (kHz)

155

110

184

135

222

162

154

271

196

325

240

406

295

241

336

360

432

540

588

77

83

92

Table 27. Narrow-Band Rx Path Channel Bandwidths and IFs

Channel BW (kHz)

IF (kHz)

81.25

102

111

122

127

135

148

163

181

203

222

231

250

271

325

530

738

2.6

3.0

3.2

3.4

3.7

3.9

4.2

4.4

4.7

5.1

5.4

5.8

6.2

6.6

7.0

7.5

AGC

8.1

8.5

8.7

9.1

AGC is enabled by default and keeps the receiver gain at the

correct level by selecting the LNA, mixer, and filter gain settings

based on the measured RSSI level.

AFC

9.7

10.4

10.6

11.1

11.7

11.9

12.7

13.5

14.4

15.4

16.4

17.6

18.7

20.0

The ADF7030-1 features an internal real-time automatic

frequency control loop. In receive mode, the control loop

automatically monitors the frequency error during the packet

preamble sequence and adjusts the receiver synthesizer local

oscillator. AFC is supported without the need for any additional

preamble bits in the received packet.

Baseband Processing

The demodulator is based on a digital frequency correlator

that performs filtering and frequency discrimination of the

2FSK/2GFSK spectrum. Following the demodulator is an

oversampled digital clock and data recovery (CDR) phase-

locked loop (PLL) that resynchronizes the received bit stream to

a local clock in all modulation modes. A serializer/deserializer

Rev. 0 | Page 47 of 55

ADF7030-1

Data Sheet

(SERDES) block processes the received bit stream, carries out

pattern matching, and produces the byte sized data for the ARM

Cortex-M0 processor.

Power Amplifiers

The ADF7030-1 has two integrated power amplifiers. PA1 and

PA2 are designed for optimum power consumption performance

at 13 dBm and 17 dBm, respectively. The PAs cannot be operated

simultaneously. The user selects the appropriate PA for their

specific system. The power amplifiers are implemented as Class F

type amplifiers.

The ARM Cortex-M0 processor performs all of the byte level

packet processing and packet management.

Received Signal Strength Indicator (RSSI)

The ADF7030-1 supports accurate measurement of the received

signal strength. To achieve the calibrated absolute accuracy

specification, a one-point factory calibration is required (see the

Radio System Calibration section). The ADF7030-1 measures

the RSSI during packet reception and the value is stored in a

register for access by the host processor. The RSSI measurement

is also used during CCA, where the RSSI measurement is evalu-

ated against a user set threshold. The RSSI is reported in dBm.

For systems where very fine power control is required, a PA

microsetting can be used to achieve 0.1 dB of resolution across

the power range. To reduce spectral splatter when the PA is

turning on and off, a programmable PA ramp is provided.

Transmit Modulation Schemes

The ADF7030-1 supports 2FSK/2GFSK and 4FSK/4GFSK

modulation in transmit mode. In 2FSK/2GFSK mode, a binary

zero value generates a frequency deviation tone, –f_DEV. A binary

one generates a +f_DEVtone. In 4FSK/4GFSK, the symbol mapping

is configurable.

TRANSMITTER

The ADF7030-1 transmitter supports 2FSK/2GFSK, 4FSK/4GFSK,

and OOK modulation. It comprises a high performance PLL

synthesizer and power efficient dual PAs. A block diagram of the

ADF7030-1 transmitter architecture is shown in Figure 85. All

blocks are fully integrated.

OOK modulation is also supported in transmit mode at a data

rate of 16.384 kbps.

Transmit Filtering

Synthesizer and VCO

The ADF7030-1 supports Gaussian filtering in both 2FSK and

4FSK mode. Gaussian filtering reduces the occupied bandwidth

of the signal by digitally prefiltering the transmit data. The BT

factors are configurable with the following options: 0.5, 0.4,

0.35, or 0.3. Reducing BT increases the roll-off factor of the filter

resulting in a narrower signal bandwidth. As BT is reduced,

intersymbol interference is introduced, which affects the

receiver sensitivity performance.

An integrated, low noise PLL synthesizer and VCO generate

both the transmit signal and the receiver LO signal.

The synthesizer loop filter has a programmable bandwidth.

Upon entering the PHY_RX state, the ADF7030-1 sets a narrow

bandwidth to ensure optimum receiver rejection. In the PHY_TX

state, the bandwidth is chosen to ensure optimum modulation

quality.

A high speed, fully automatic calibration scheme ensures that

the VCO performance is maintained over temperature, supply

voltage, and process variations. The calibration is automatically

performed when the CMD_PHY_RX or CMD_PHY_TX

command is issued.

OOK

PA RAMP

PAOUT2

PAOUT1

RF

FREQ

PA2

PA1

26MHz

REFERENCE

(TCXO OR XTAL)

CHARGE

PUMP

DIVIDER

Rx LO

PFD

VCO

LOOP

FILTER

N

DIVIDER

Tx DATA

(FROM Cortex-M0

PROCESSOR)

Σ-Δ

BIT

MAPPER

GAUSSIAN

FILTER

MODULATOR

AFC

FSK

FREQUECY

DEVIATION

Figure 85. Transmitter Block Diagram

Rev. 0 | Page 48 of 55

Data Sheet

ADF7030-1

is present on the RF input of the ADF7030-1 during calibration,

this signal can degrade the calibration performance. The conse-

quence of a degraded calibration is a reduction in the image

rejection performance of the receiver.

CALIBRATION

Table 28 provides an overview of the calibrations associated

with the ADF7030-1 and when to run calibrations.

Radio System Calibration

If the application uses an external switch, the switch can be used

to provide extra isolation between the antenna and the RF input

of the ADF7030-1 during calibration.

To ensure that the ADF7030-1 radio performance meets the

data sheet specifications, it is necessary to perform a one-time

radio system calibration at 25°C 10°C.

26 kHz RC Oscillator Calibration

The radio system calibration routine is provided as a firmware

module, OffLineCalibrations.cfg, that the host processor must

download to the ADF7030-1 memory. The firmware module is

available as part of the ADF7030-1 design package. The calibration

is fully autonomous when initiated by the CMD_DO_CAL

command.

To ensure that the 26 kHz RC oscillator meets the calibrated

frequency accuracy specification, it is necessary to perform a

calibration. During calibration, the OffLineCalibrations.cfg

firmware module must be downloaded to the ADF7030-1. The

calibration is fully autonomous when initiated by the CMD_LFRC_

CAL command.

The radio system calibration firmware module can be downloaded

to the ADF7030-1 and run as part of a factory calibration proce-

dure and the calibration data stored on the host processor as part of

the configuration settings for the ADF7030-1. Calibration data is

maintained in PHY_SLEEP if memory retention is enabled. If

the memory is not retained, the host processor must replay the

calibration data to the ADF7030-1. Refer to the ADF7030-1

Software Reference Manual for further details on downloading

and using firmware modules with the ADF7030-1.

Refer to the ADF7030-1 Software Reference Manual for further

details.

RSSI Offset Calibration

To ensure that the ADF7030-1 RSSI performance meets the

calibrated RSSI data sheet specifications, it is necessary to perform

a measurement of the ADF7030-1 RSSI measurement offset.

The offset can be measured as part of a factory calibration

procedure where an RF signal source applies a signal to the

receiver input while the ADF7030-1 is in the continuous CCA

state. The offset between the applied signal power and the

ADF7030-1 RSSI result is stored on the host processor as part of

the configuration settings for the ADF7030-1. The ADF7030-1

has allocated registers for the RSSI offset, and the ADF7030-1

automatically applies these offsets to the RSSI measurement

result returned over the SPI. Refer to the ADF7030-1 Software

Reference Manual for further details on the RSSI offset

calibration procedure and the RSSI offset registers.

In the Field Radio System Calibration

The only receiver performance metric that benefits appreciably

from a recalibration over temperature, is the image rejection. In

applications where image rejection performance is critical over

temperature, it may be necessary to perform a recalibration as

the temperature changes.

If the application requires the calibration to be performed in the

field (in addition to the one-time factory calibration), it is

important to consider interferer signals during calibration, because

the calibration uses internally generated RF signals to perform

certain aspects of the receiver calibration. If an interferer signal

Table 29. ADF7030-1 Calibrations

Typical

Calibration

Time (ms)

Radio

Command

Calibration

Description

When to Run this Calibration

Firmware Module Required

Radio System

Calibration of

the radio

system

A one-time calibration is required to

meet the data sheet specifications. This

calibration can be performed as part of a downloaded to the ADF7030-1.

factory calibration of the end product.

The OffLineCalibrations.cfg

firmware module must be

CMD_DO_CAL

660

26 kHz RC

Oscillator

Frequency

calibration of

the internal

26 kHz RC

oscillator

A frequency calibration of the 26 kHz RC The OffLineCalibrations.cfg

CMD_LFRC_CAL 30

oscillator is required to meet the typical

frequency accuracy specification.

Depending on the frequency accuracy

requirements of the application, it may

also be necessary to calibrate as the

temperature changes. Refer to Table 17

for specifications.

firmware module must be

downloaded to the ADF7030-1.

RSSI Offset

A single point, A single-point, one-time, RSSI offset

None required.

Not applicable

Not

applicable

one-time,

offset

calibration is required to meet the RSSI

accuracy specification of Table 3. This

calibration can be performed as part of a

factory calibration of the end product.

calibration of

the RSSI

Rev. 0 | Page 49 of 55

ADF7030-1

Data Sheet

Transmitting and Receiving packets

PACKET HANDLING

The ADF7030-1 can be programmed to transmit and receive

variable and fixed length payloads. The packet data to be

transmitted must be written by the host into the ADF7030-1

internal memory. 511 bytes of dedicated RAM are available to

store, transmit, and receive packets. For payload lengths greater

than 511 bytes, the ADF7030-1 provides a rolling buffer mode.

The ADF7030-1 includes comprehensive transmit and receive

packet management capabilities and can be configured for use

with a wide variety of packet-based radio protocols.

IEEE 802.15.4g Packet Mode

The ADF7030-1 supports the multirate frequency shift keying

(MR-FSK) PHY 802.15.4g specified packet format in the IEEE

802.15.4g-2012 standard with FEC, whitening, and interleaving

at data rates of up to 150 kbps.

To transmit or receive a packet, the host processor must first

configure the ADF7030-1. Then, the host processor issues the

commands to place the ADF7030-1 into the PHY_RX state or

the PHY_TX state. After either state is entered, the ADF7030-1

automatically starts transmitting or receiving a packet.

Generic Packet Mode

The ADF7030-1 supports a wide variety of packet formats via

its fully flexible generic packet format. In generic packet

transmit mode, the ADF7030-1 can be configured to add the

preamble, sync word, and cyclic redundancy check (CRC) to the

payload data stored in the packet memory. The number of

preamble bits and sync bits is programmable, and an optional

length field can be added to allow packet length decoding at the

receiver. The CRC polynomial and length are fully

In transmit mode, a preamble, sync word, and CRC can be added

by the ADF7030-1 to the payload data stored in the RAM. In

receive mode, the ADF7030-1 can qualify received packets

based on preamble detection, sync word detection, or CRC

validation. When the ADF7030-1 receives a valid packet, the

received payload data is loaded to packet memory.

The host can track the progress of the transmission or reception

of a packet by monitoring the interrupt signals coming from the

ADF7030-1. There are two independent logical interrupts from

the ADF7030-1, and events can be configured to trigger one or

both of these logical interrupts.

programmable in generic packet mode.

Rev. 0 | Page 50 of 55

Data Sheet

ADF7030-1

APPLICATIONS INFORMATION

guide on application circuits, external hardware requirements,

and RF matching for the ADF7030-1.

TYPICAL APPLICATION CIRCUIT

A typical application circuit is shown in Figure 86. Refer to the

ADF7030-1 Hardware Reference Manual for a comprehensive

26MHz

TCXO

220nF

OPTIONAL

WAKE-UP

220nF

CRYSTAL

1.2nF

32.768kHz

100nF

100kΩ

RST

DNC

GPIO6

CS

SCLK

MISO

MOSI

VBAT5

VBAT4

GPIO5

GPIO4

GPIO

CS

VBAT1

CREG1

VBAT2

CREG2

LNAIN1

LNAIN2

DNC

220nF

SCLK

MISO

MOSI

100nF

220nF

ADF7030-1

TOP VIEW

(Not to Scale)

220nF

INT1

INT2

CREG3

DNC

100nF

Rx MATCH

100nF

220nF

100nF

HARMONIC

FILTER

OPTIONAL

GPIO CONNECTION

FROM ADF7030-1

PA2 MATCH

Figure 86. Typical Application Circuit with External Switch and TCXO Reference

Rev. 0 | Page 51 of 55

ADF7030-1

Data Sheet

SILICON ANOMALY

This anomaly list describes the known bugs, anomalies, and workarounds for the ADF7030-1.

Analog Devices, Inc., is committed, through future silicon revisions and/or firmware module revisions, to continuously improve

functionality. Analog Devices tries to ensure that these future revisions of the ADF7030-1 silicon or firmware modules remain compatible

with your present software/systems by implementing the recommended workarounds outlined here.

The silicon revision information can be electronically determined by reading the PART_ID and ROM_ID fields from the ADF7030-1

memory locations described in Table 30.

Table 30. Silicon Revision ID

IF Field

PART_ID

ROM_ID

Length (Bytes)

Memory Address

0x00007FF6

0x00007FF9

2

1

ADF7030-1 FUNCTIONALITY ISSUES

Silicon Revision ID

Chip Marking

Silicon Status

Release

No. of Reported Anomalies

PART_ID = 0x0602, ROM_ID = 0x02

ADF7030-1BCPZN or ADF7030-1BSTZN

2

FUNCTIONALITY ISSUES

Table 31. Short Transmit Pulse Preceding Packet preamble on OOK Transmit [er001]

Background

In OOK transmit, a preamble sequence with the length controlled by PREAMBLE_LEN in the GENERIC_PKT_FRAME_CFG0

register is transmitted at the start of a packet.

Issue

The first OOK transmit packet after a reset event or cold start has the correct preamble sequence. Subsequent OOK

transmit packets prepend a short transmit pulse with a duration of less than one bit, before the preamble sequence. The

output power of the pulse is at the configured output power.

None.

Workaround

Table 32. CCA After Aborting PHY_TX During Packet Transmission for Data Rates < 3.064 kbps [er002]

The host processor can abort a transmission by issuing any radio command while the ADF7030-1 is in the PHY_TX state.

Background

For data rates < 3.064 kbps, the first CCA operation is inoperative after aborting a transmission.

Issue

Workaround

After aborting a transmission, enter the CCA state twice. On the first CCA entry, CCA is inoperative. On the second and

subsequent entries to the CCA state, CCA is fully operational.

None.

Section 1. ADF7030-1 Functionality Issues

Reference Number

Description

Status

Open

er001

er002

Short transmit pulse preceding packet preamble on OOK transmit

CCA after aborting PHY_TX during packet transmission for data rates < 3.064 kbps

This completes the Silicon Anomaly section.

Rev. 0 | Page 52 of 55

Data Sheet

ADF7030-1

DEVELOPMENT SUPPORT

DESIGN PACKAGE

EVALUATION KITS

The ADF7030-1 design resource package is a complete

documentation and resource package for the ADF7030-1. It is

recommended to download this package as a starting point for

evaluation and development from the ADF7030-1 product page. It

contains manuals, application notes, hardware information, and

firmware modules.

Evaluation and development kits are available that include the

ADF7030-1 radio daughter boards. The ADF7030-1 EZ-KIT® is

an evaluation and development system for the ADF7030-1 high

performance, sub GHz, RF transceiver, and includes four

models. These kits are listed in Table 33.

Table 33. ADF7030-1 EZ-KIT Models

REFERENCE MANUALS

ADF7030-1 Software Reference Manual (UG-1002)

Model

Frequency (MHz)

902 to 928

863 to 876

433 to 434

169

ADF70301-915EZKIT

ADF70301-868EZKIT

ADF70301-433EZKIT

ADF70301-169EZKIT

The ADF7030-1 Software Reference Manual is the detailed

programming guide for the device. The ADF7030-1 hardware

reference manual provides a description of the ADF7030-1

hardware features and application circuit requirements.

A selection of individual daughter boards are also available

covering various frequency bands and matching topologies.

ADF7030-1 Hardware Reference Manual (UG-957)

The ADF7030-1 Hardware Reference Manual provides a

description of the ADF7030-1 radio functionality, hardware

features, and application circuit requirements. It is intended as a

resource for a hardware engineer designing a printed circuit

board (PCB) that includes the ADF7030-1.

EVALUATION SOFTWARE

The ADF7030-1 design center is a graphical user interface

(GUI) that can be used for configuring the ADF7030-1,

evaluating transmit and receive operation, and transmitting and

receiving packets. This ADF7030-1 design center allows the

user to rapidly prototype different configurations with the

ADF7030-1 and simplifies the migration to host code

development.

Rev. 0 | Page 53 of 55

ADF7030-1

Data Sheet

OUTLINE DIMENSIONS

6.10

6.00 SQ

5.90

0.30

0.25

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

31

40

1

30

0.50

BSC

4.60

4.50 SQ

4.40

EXPOSED

PAD

10

21

11

20

0.45

0.40

0.35

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.

Figure 87. 40-Lead Lead Frame Chip Scale Package [LFCSP]

6 mm × 6 mm Body and 0.75 Package Height

(CP-40-17)

Dimensions shown in millimeters

9.20

9.00 SQ

8.80

0.75

0.60

0.45

1.60

MAX

37

48

36

1

PIN 1

7.20

TOP VIEW

(PINS DOWN)

7.00 SQ

6.80

1.45

1.40

1.35

0.20

0.09

7°

3.5°

0°

25

12

0.15

0.05

13

24

SEATING

PLANE

0.08

0.27

0.22

0.17

VIEW A

0.50

BSC

LEAD PITCH

COPLANARITY

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

Figure 88. 48-Lead Low Profile Quad Flat Package [LQFP]

7 mm × 7 mm Body

(ST-48)

Dimensions shown in millimeters

Rev. 0 | Page 54 of 55

Data Sheet

ADF7030-1

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +85°C

Package Description

Package Option

CP-40-17

ST-48

ADF7030-1BCPZN

ADF7030-1BCPZN-RL

ADF7030-1BSTZN

ADF7030-1BSTZN-RL

EV-ADF70301-169BZ

40-Lead Lead Frame Chip Scale Package [LFCSP]

48-Lead Low Profile Quad Flat Package [LQFP]

Evaluation Daughter Board (169 MHz, Separate PA and LNA Match,

26 MHz XTAL)

ST-48

EV-ADF70301-433AZ

EV-ADF70301-460BZ

EV-ADF70301-868BZ

EV-ADF70301-915AZ

Evaluation Daughter Board (433 MHz, Separate PA and LNA Match,

26 MHz XTAL)

Evaluation Daughter Board (450MHz to 470MHz, Separate PA and

LNA match, 26 MHz TCXO)

Evaluation Daughter Board (863 MHz to 876 MHz, Separate PA and

LNA match, 26 MHz TCXO)

Evaluation Daughter Board (902 MHz to 928 MHz, Separate PA and

LNA match, 26 MHz XTAL)

ADF70301-169EZKIT

ADF70301-433EZKIT

ADF70301-868EZKIT

ADF70301-915EZKIT

Evaluation and Development Kit (169 MHz)

Evaluation and Development Kit (433 MHz to 434 MHz)

Evaluation and Development Kit (863 MHz to 876 MHz)

Evaluation and Development Kit (902 MHz to 928 MHz)

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D14373-0-6/16(0)

Rev. 0 | Page 55 of 55


型号：	ADF7030-1BSTZN-RL
厂家：	ADI
描述：	High Performance, Sub GHz Radio Transceiver IC 电信电信集成电路
文件：	总56页 (文件大小：1712K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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