ADG1207YRUZ-REEL7 [ADI]
Low Capacitance, 16- and 8-Channel +-15 V/+12 V iCMOS Multiplexers; 低电容，16位和8通道±15 V / + 12 V的iCMOS多路复用器
| 型号： | ADG1207YRUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Low Capacitance, 16- and 8-Channel +-15 V/+12 V iCMOS Multiplexers |
| 文件： | 总20页 (文件大小：478K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Capacitance, 16- and 8-Channel
1ꢀ ꢁV/1ꢂ ꢁ iCMOS™ Multiplexers
ADG1ꢂ06VADG1ꢂ07
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
<1 pC charge injection over full signal range
1.5 pF off capacitance
33 V supply range
ADG1206
ADG1207
S1
S1A
S8A
DA
DB
120 Ω on resistance
Fully specified at 15 V/+12 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
28-lead TSSOP and 32-lead, 5 mm × 5 mm LFCSP_VQ
D
S1B
S8B
S16
1-OF-16
DECODER
1-OF-8
DECODER
APPLICATIONS
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
A0 A1 A2 A3 EN
A0 A1 A2 EN
Figure 1.
GENERAL DESCRIPTION
The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data
acquisition and sample-and-hold applications, where low glitch
and fast settling are required. Figure 2 shows that there is
minimum charge injection over the entire signal range of the
device. iCMOS construction also ensures ultralow power
dissipation, making the parts ideally suited for portable and
battery-powered instruments.
The ADG1206 and ADG1207 are monolithic iCMOS analog
multiplexers comprising sixteen single channels and eight
differential channels, respectively. The ADG1206 switches one
of sixteen inputs to a common output, as determined by the 4-
bit binary address lines A0, A1, A2, and A3. The ADG1207
switches one of eight differential inputs to a common
differential output, as determined by the 3-bit binary address
lines A0, A1, and A2. An EN input on both devices is used to
enable or disable the device. When disabled, all channels are
switched off. When on, each channel conducts equally well in
both directions and has an input signal range that extends to the
supplies.
1.0
MUX (SOURCE TO DRAIN)
T
= 25°C
A
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
V
V
= +15V
= –15V
DD
SS
The iCMOS (industrial CMOS) modular manufacturing
process combines high voltage CMOS (complementary metal-
oxide semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased perfor-
mance, dramatically lower power consumption, and reduced
package size.
V
V
= +12V
= 0V
DD
SS
0.1
0
V
V
= +5V
= –5V
DD
SS
–15
–10
–5
0
5
10
15
V
(V)
S
Figure 2. Source-to-Drain Charge Injection vs. Source Voltage
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADG1ꢂ06VADG1ꢂ07
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................7
ESD Caution...................................................................................7
Pin Configurations and Function Descriptions............................8
Typical Performance Characteristics ........................................... 12
Terminology.................................................................................... 16
Test Circuits..................................................................................... 17
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply................................................................................... 3
Single Supply................................................................................. 5
REVISION HISTORY
7/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG1ꢂ06VADG1ꢂ07
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V 10%, VSS = –15 V 10%, GND = 0 V, unless otherwise noted.1
Table 1.
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VSS to VDD
270
V
120
200
3.5
Ω typ
Ω max
Ω typ
VS = 10 V, IS = −1 mA; see Figure 28
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
240
On Resistance Match Between
Channels, ∆RON
6
20
64
10
76
12
83
Ω max
Ω typ
Ω max
On Resistance Flatness, RFLAT (On)
VS = −5 V, 0 V, +5 V; IS = −1 mA
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.03
nA typ
VD = 10 V, VS = ∓10 V; see Figure 29
VS = 1 V, 10 V; VD = 10 V, 1 V; see Figure 29
VS = VD = 10 V; see Figure 30
0.2
0.05
0.2
0.08
0.2
0.6
0.6
0.6
1
2
2
nA max
nA typ
nA max
nA typ
nA max
Drain Off Leakage, ID (Off)
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.005
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
2
80
130
75
95
85
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 32
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 37
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz;
see Figure 38
165
105
125
185
115
140
10
tON (EN)
tOFF (EN)
100
20
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
0.5
−85
−85
0.15
−3 dB Bandwidth ADG1206
−3 dB Bandwidth ADG1207
CS (Off)
280
490
1.5
2
11
12
7
MHz typ
MHz typ
pF typ
pF max
pF typ
RL = 50 Ω, CL = 5 pF; see Figure 36
RL = 50 Ω, CL = 5 pF; see Figure 36
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
CD (Off) ADG1206
CD (Off) ADG1207
pF max
pF typ
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
9
pF max
f = 1 MHz, VS = 0 V
Rev. 0 | Page 3 of 20
ADG1ꢂ06VADG1ꢂ07
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
CD, CS (On) ADG1206
13
15
8
pF typ
pF max
pF typ
pF max
CD, CS (On) ADG1207
10
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
0.002
260
μA typ
μA max
μA typ
μA max
μA typ
μA max
1.0
IDD
Digital inputs = 5 V
420
ISS
0.002
Digital inputs = 0 V, 5 V, or VDD
1.0
VDD/VSS
5/ 16.5
V min/max GND = 0V
1 Temperature range for Y version is −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 20
ADG1ꢂ06VADG1ꢂ07
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.1
Table 2.
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 to VDD
625
V
300
475
5
Ω typ
Ω max
Ω typ
VS = 0 V to10 V, IS = −1 mA; see Figure 28
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
567
26
On Resistance Match Between
Channels, ∆RON
16
60
27
Ω max
Ω typ
On Resistance Flatness, RFLAT (On)
LEAKAGE CURRENTS
VS = 3 V, 6 V, 9 V; IS = −1 mA
VDD = 13.2 V
Source Off Leakage, IS (Off)
0.02
0.2
0.05
0.2
0.08
0.2
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29
0.6
0.6
0.6
1
2
2
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29
VS = VD = 1 V or 10 V; see Figure 30
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.001
0.1
VIN = VINL or VINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANSITION
3
100
140
80
100
90
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 31
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 33
RL = 300 Ω, CL = 35 pF
175
120
130
200
130
155
15
tON (EN)
tOFF (EN)
110
25
Break-Before-Make Time Delay, tBBM
ns min
pC typ
dB typ
dB typ
MHz typ
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
pF typ
pF max
pF typ
pF max
VS1 = VS2 = 8 V; see Figure 32
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 37
RL = 50 Ω, CL = 5 pF; see Figure 36
RL = 50 Ω, CL = 5 pF; see Figure 36
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth ADG1206
−3 dB Bandwidth ADG1207
CS (Off)
0.2
−85
−85
185
300
1.5
2
13
15
9
11
CD (Off) ADG1206
CD (Off) ADG1207
CD, CS (On) ADG1206
CD, CS (On) ADG1207
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
f = 1 MHz, VS = 6 V
15
17
10
12
f = 1 MHz, VS = 6 V
Rev. 0 | Page 5 of 20
ADG1ꢂ06VADG1ꢂ07
−40°C to
+25°C +85°C
−40°C to
+125°C
Parameter
Unit
Test Conditions/Comments
VDD = 13.2 V
Digital inputs = 0 V or VDD
POWER REQUIREMENTS
IDD
0.002
260
μA typ
μA max
μA typ
μA max
1.0
IDD
Digital inputs = 5
420
VDD
5/16.5
V min/max VSS = 0 V, GND = 0 V
1 Temperature range for Y version is −40°C to +125°C.
2 Guaranteed by design, not subject to production test.
Rev. 0 | Page 6 of 20
ADG1ꢂ06VADG1ꢂ07
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to VSS
35 V
VDD to GND
VSS to GND
Analog, Digital Inputs1
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V
or 30 mA, whichever
occurs first
Continuous Current, S or D
Peak Current, S or D (Pulsed at 1 ms,
10% Duty Cycle Maximum)
30 mA
100 mA
Only one absolute maximum rating may be applied at any
one time.
Operating Temperature Ranges
Industrial (Y Version)
Storage
Junction Temperature
28-Lead TSSOP
–40°C to +125°C
–65°C to +150°C
150°C
θJA, Thermal Impedance
θJC, Thermal Impedance
32-Lead LFCSP_VQ
θJA, Thermal Impedance
97.9°C/W
14°C/W
27.27°C/W
Reflow Soldering Peak Temperature
(Pb-Free)
260(+0/−5)°C
1 Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 20
ADG1ꢂ06VADG1ꢂ07
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
D
DD
2
NC
NC
V
SS
3
S8
S7
S6
S5
S4
S3
S2
S1
EN
A0
A1
A2
4
S16
S15
S14
S13
S12
S11
S10
S9
5
6
ADG1206
TOP VIEW
(Not to Scale)
7
S16
S15
S14
S13
S12
S11
S10
S9
1
2
3
4
5
6
7
8
24 S8
23 S7
22 S6
21 S5
20 S4
19 S3
18 S2
17 S1
PIN 1
INDICATOR
8
9
ADG1206
TOP VIEW
(Not to Scale)
10
11
12
13
14
GND
NC
NC = NO CONNECT
A3
NC = NO CONNECT
Figure 3. ADG1206 Pin Configuration—TSSOP
Figure 4. ADG1206 Pin Configuration—5 mm × 5 mm LFCSP_VQ,
Exposed Pad Tied to Substrate, VSS
Table 4. ADG1206 Pin Function Descriptions
Pin Number
TSSOP
LFCSP_VQ
31
12, 13
26, 27, 28,
30, 32
Mnemonic
Description
1
2
3
VDD
NC
NC
Most Positive Power Supply Potential.
No Connect.
No Connect.
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
S16
S15
S14
S13
S12
S11
S10
S9
GND
NC
A3
A2
A1
Source Terminal 16. Can be an input or an output.
Source Terminal 15. Can be an input or an output.
Source Terminal 14. Can be an input or an output.
Source Terminal 13. Can be an input or an output.
Source Terminal 12. Can be an input or an output.
Source Terminal 11. Can be an input or an output.
Source Terminal 10. Can be an input or an output.
Source Terminal 9. Can be an input or an output.
Ground (0 V) Reference.
No Connect.
Logic Control Input.
Logic Control Input.
Logic Control Input.
9
–
10
11
14
15
16
A0
EN
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1
S2
S3
S4
S5
S6
S7
S8
VSS
Source Terminal 1. Can be an input or an output.
Source Terminal 2. Can be an input or an output.
Source Terminal 3. Can be an input or an output.
Source Terminal 4. Can be an input or an output.
Source Terminal 5. Can be an input or an output.
Source Terminal 6. Can be an input or an output.
Source Terminal 7. Can be an input or an output.
Source Terminal 8. Can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be
connected to ground.
28
29
D
Drain Terminal. Can be an input or an output.
Rev. 0 | Page 8 of 20
ADG1ꢂ06VADG1ꢂ07
Table 5. ADG1206 Truth Table
A3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
EN
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
On Switch
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Rev. 0 | Page 9 of 20
ADG1ꢂ06VADG1ꢂ07
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DA
DD
DB
NC
V
SS
3
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
EN
4
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
NC
5
6
ADG1207
TOP VIEW
(Not to Scale)
7
8
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
1
2
3
4
5
6
7
8
24 S8A
23 S7A
22 S6A
21 S5A
20 S4A
19 S3A
18 S2A
17 S1A
PIN 1
INDICATOR
9
10
11
12
13
14
ADG1207
TOP VIEW
(Not to Scale)
A0
A1
NC
A2
NC = NO CONNECT
NC = NO CONNECT
Figure 5. ADG1207 Pin Configuration—TSSOP
Figure 6. ADG1207 Pin Configuration—5 mm × 5 mm LFCSP_VQ
Exposed Pad Tied to Substrate, VSS
Table 6. ADG1207 Pin Function Descriptions
Pin Number
TSSOP
LFCSP_VQ
Mnemonic
VDD
DB
Description
1
2
3
29
31
11, 12, 13
Most Positive Power Supply Potential.
Drain Terminal B. Can be an input or an output.
No Connect.
NC
4
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
9
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
Source Terminal 8B. Can be an input or an output.
Source Terminal 7B. Can be an input or an output.
Source Terminal 6B. Can be an input or an output.
Source Terminal 5B. Can be an input or an output.
Source Terminal 4B. Can be an input or an output.
Source Terminal 3B. Can be an input or an output.
Source Terminal 2B. Can be an input or an output.
Source Terminal 1B. Can be an input or an output.
Ground (0 V) Reference.
GND
NC
26, 28,
30, 32
No Connect.
14
15
16
17
18
–
NC
A2
A1
A0
EN
No Connect.
10
14
15
16
Logic Control Input.
Logic Control Input.
Logic Control Input.
Active High Digital Input. When this pin is low, the device is disabled and all switches are
turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
19
20
21
22
23
24
25
26
27
17
18
19
20
21
22
23
24
25
S1A
S2A
S3A
S4A
S5A
S6A
S7A
S8A
VSS
Source Terminal 1A. Can be an input or an output.
Source Terminal 2A. Can be an input or an output.
Source Terminal 3A. Can be an input or an output.
Source Terminal 4A. Can be an input or an output.
Source Terminal 5A. Can be an input or an output.
Source Terminal 6A. Can be an input or an output.
Source Terminal 7A. Can be an input or an output.
Source Terminal 8A. Can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin can be
connected to ground.
28
27
DA
Drain Terminal A. Can be an input or an output.
Rev. 0 | Page 10 of 20
ADG1ꢂ06VADG1ꢂ07
Table 7. ADG1207 Truth Table
A2
X
0
0
0
0
1
1
1
A1
X
0
0
1
1
0
0
1
A0
X
0
1
0
1
0
1
0
EN
0
1
1
1
1
1
1
1
On Switch Pair
None
1
2
3
4
5
6
7
8
1
1
1
1
Rev. 0 | Page 11 of 20
ADG1ꢂ06VADG1ꢂ07
TYPICAL PERFORMANCE CHARACTERISTICS
200
250
V
V
= +15V
= –15V
DD
SS
T
= 25°C
A
V
V
= +15V
= –15V
DD
SS
180
160
140
120
100
80
V
V
= +13.5V
= –13.5V
DD
SS
200
150
T
T
= +125°C
= +85°C
A
A
T
= +25°C
= –40°C
A
A
V
V
= +16.5V
= –16.5V
DD
SS
100
T
60
40
50
0
20
0
–18 –15 –12 –9 –6 –3
0
3
6
9
12 15 18
–15
–10
–5
0
5
10
15
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 7. On Resistance as a Function of VD (VS) for Dual Supply
Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
600
600
V
V
= 12V
= 0V
DD
SS
T
= 25°C
V
V
= +4.5V
= –4.5V
A
DD
SS
T
= +125°C
A
500
500
400
300
200
V
V
= +5V
= –5V
DD
SS
T
= +85°C
A
400
300
T
= +25°C
A
V
V
= +5.5V
= –5.5V
DD
SS
T
= –40°C
A
200
100
0
100
0
–6
–4
–2
0
2
4
6
0
2
4
6
8
10
12
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 8. On Resistance as a Function of VD (VS) for Dual Supply
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
450
1200
V
V
V
= +15V
= –15V
DD
SS
T
= 25°C
V
V
= 10.8V
= 0V
A
DD
SS
1000
800
400
350
300
250
200
150
100
50
I
(OFF) – +
D
= +10V/–10V
BIAS
I
, I (ON) + +
S
D
V
V
= 12V
= 0V
DD
SS
600
I
(OFF) + –
S
400
200
V
V
= 13.2V
= 0V
DD
SS
0
–200
–400
–600
–800
–1000
–1200
I
(OFF) – +
S
I
(OFF) + –
D
I
, I (ON) – –
S
D
0
0
2
4
6
8
10
12
14
0
20
40
60
80
100
120
SOURCE OR DRAIN VOLTAGE (V)
TEMPERATURE (°C)
Figure 9. On Resistance as a Function of VD (VS) for Single Supply
Figure 12. ADG1206 Leakage Currents as a Function of Temperature,
Dual Supply
Rev. 0 | Page 12 of 20
ADG1ꢂ06VADG1ꢂ07
6
4
400
300
DEMUX (DRAIN TO SOURCE)
= 25°C
V
V
V
= 12V
= 0V
I (OFF) – +
D
DD
SS
T
A
= 1V/10V
BIAS
V
V
= +5V
= –5V
I
(OFF) + –
DD
S
200
SS
I
, I (ON )+ +
S
D
2
100
0
V
V
= +12V
= 0V
0
DD
SS
–100
–200
–300
–400
V
V
= +15V
= –15V
DD
SS
–2
I
(OFF) – +
S
I
(OFF) + –
D
–4
–6
I
, I (ON) – –
S
D
–15
–10
–5
0
(V)
5
10
15
0
20
40
60
80
100
120
V
TEMPERATURE (°C)
S
Figure 13. ADG1206 Leakage Currents as a Function of Temperature,
Single Supply
Figure 16. Drain-to-Source Charge Injection vs. Source Voltage
350
300
200
I
T
PER CHANNEL
= 25°C
DD
180
160
140
120
100
80
A
V
V
= +5V
= –5V
DD
SS
V
V
= +15V
= –15V
DD
250
200
150
100
50
SS
V
V
= +12V
= 0V
DD
SS
60
V
V
= +15V
= –15V
DD
SS
40
V
V
= +12V
= 0V
DD
SS
20
0
0
–40
–20
0
20
40
60
80
100
120
0
2
4
6
8
10
12
14
16
LOGIC, IN (V)
TEMPERATURE (°C)
X
Figure 14. IDD vs. Logic Level
Figure 17. Transition Time vs. Temperature
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
MUX (SOURCE TO DRAIN)
= 25°C
V
V
= +15V
= –15V
= 25°C
DD
SS
T
A
T
A
V
V
= +15V
= –15V
DD
SS
V
V
= +12V
= 0V
DD
SS
0.1
0
V
V
= +5V
= –5V
DD
SS
–15
–10
–5
0
5
10
15
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
V
(V)
S
Figure 15. Source-to-Drain Charge Injection vs. Source Voltage
Figure 18. Off Isolation vs. Frequency
Rev. 0 | Page 13 of 20
ADG1ꢂ06VADG1ꢂ07
0
10
T
A
= 25°C
LOAD = 10kΩ
= 25°C
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
T
A
1
V
V
= +5V, V = –5V, V = +3.5V rms
SS S
DD
DD
ADJACENT
CHANNELS
= +15V, V = –15V, V = +5V rms
SS
S
0.1
NON ADJACENT
CHANNELS
0.01
10k
100k
1M
10M
100M
1G
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 22. THD + N vs. Frequency
Figure 19. ADG1206 Crosstalk vs. Frequency
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
20
T
A
= 25°C
V
V
= +15V
= –15V
DD
SS
18
16
14
12
10
8
T
= 25°C
A
SOURCE/DRAIN ON
DRAIN OFF
ADJACENT
CHANNELS
6
4
NON ADJACENT
2
SOURCE OFF
CHANNELS
0
–15
–10
–5
0
5
10
15
10k
100k
1M
10M
100M
1G
V
(V)
FREQUENCY (Hz)
BIAS
Figure 20. ADG1207 Crosstalk vs. Frequency
Figure 23. ADG1206 Capacitance vs. Source Voltage,
15 V Dual Supply
–4
–6
20
18
16
14
12
10
8
ADG1207
SOURCE/DRAIN ON
DRAIN OFF
–8
–10
–12
–14
–16
–18
–20
ADG1206
6
V
V
= 12V
= 0V
= 25°C
DD
SS
4
T
A
V
V
= +15V
= –15V
= 25°C
DD
SS
SOURCE OFF
6
2
T
A
0
0
2
4
8
10
12
10k
100k
1M
10M
100M
1G
V
(V)
FREQUENCY (Hz)
BIAS
Figure 21. On Response vs. Frequency
Figure 24. ADG1206 Capacitance vs. Source Voltage, 12 V Single Supply
Rev. 0 | Page 14 of 20
ADG1ꢂ06VADG1ꢂ07
12
10
8
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
V
= +15V
= –15V
= 25°C
DD
SS
T
= 25°C
A
NO DECOUPLING CAPACITORS
V
V
T
A
= +15V
= –15V
DD
SS
V p-p = 0.63V
SOURCE/DRAIN ON
DRAIN OFF
6
4
2
SOURCE OFF
0
–15
–10
–5
0
5
10
15
100
1k
10k
100k
1M
10M
V
(V)
BIAS
FREQUENCY (Hz)
Figure 25. ADG1207 Capacitance vs. Source Voltage, 15 V Dual Supply
Figure 27. AC PSRR vs. Frequency
14
V
V
= 12V
= 0V
DD
SS
12
10
8
T = 25°C
A
SOURCE/DRAIN ON
DRAIN OFF
6
4
2
SOURCE OFF
0
0
2
4
6
8
10
12
V
(V)
BIAS
Figure 26. ADG1207 Capacitance vs. Source Voltage, 12 V Single Supply
Rev. 0 | Page 15 of 20
ADG1ꢂ06VADG1ꢂ07
TERMINOLOGY
RON
TBBM
Ohmic resistance between D and S.
Off time measured between the 80% points of the switches
when switching from one address state to another.
ΔRON
Difference between the RON of any two channels.
VINL
Maximum input voltage for Logic 0.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.
VINH
Minimum input voltage for Logic 1.
IS (Off)
IINL (IINH)
Source leakage current when the switch is off.
Input current of the digital input.
ID (Off)
IDD
Drain leakage current when the switch is off.
Positive supply current.
ID, IS (On)
ISS
Channel leakage current when the switch is on.
Negative supply current.
VD (VS)
Off Isolation
Analog voltage on Terminals D and S.
A measure of unwanted signal coupling through an off channel.
CS (Off)
Charge Injection
Channel input capacitance for the off condition.
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CD (Off)
Channel output capacitance for the off condition.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
CD, CS (On)
On switch capacitance.
On Response
The frequency response of the on switch.
CIN
Digital input capacitance.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and the switch on condition.
ACPSRR (AC Power Supply Rejection Ratio)
Measures the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of
signal on the output to the amplitude of the modulation is the
ACPSRR.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and the switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
Rev. 0 | Page 16 of 20
ADG1ꢂ06VADG1ꢂ07
TEST CIRCUITS
V
I
(ON)
A
I
(OFF)
A
I
(OFF)
A
D
S
D
S
D
S
D
S
D
NC
I
DS
V
V
V
D
V
D
S
S
NC = NO CONNECT
Figure 28. On Resistance
Figure 29. Off Leakage
Figure 30. On Leakage
V
V
V
V
DD
SS
3V
t
t
< 20ns
< 20ns
r
f
DD
SS
ADDRESS
DRIVE (V
50%
50%
)
A0
A1
A2
A3
IN
S1
V
V
S1
0V
V
IN
50Ω
S2 TO S15
tTRANSITION
tTRANSITION
90%
S16
S16
ADG12061
OUTPUT
D
2.4V
EN
OUTPUT
GND
300Ω
35pF
90%
1
SIMILAR CONNECTION FOR ADG1207.
Figure 31. Address to Output Switching Times, tTRANSITION
V
V
V
DD
SS
SS
3V
V
DD
ADDRESS
A0
A1
A2
A3
DRIVE (V
)
IN
S1
V
S
V
IN
50Ω
0V
S2 TO S15
S16
ADG12061
80%
80%
OUTPUT
OUTPUT
D
2.4V
EN
GND
300Ω
35pF
tBBM
1
SIMILAR CONNECTION FOR ADG1207.
Figure 32. Break-Before-Make Delay, tBBM
V
V
V
V
DD
DD
SS
SS
3V
ENABLE
A0
A1
A2
A3
50%
50%
DRIVE (V
)
S1
S2 TO S16
V
IN
S
0V
ADG12061
tON (EN)
tOFF (EN)
OUTPUT
0.9V
0.9V
O
D
EN
O
OUTPUT
GND
V
IN
300Ω
50Ω
35pF
1
SIMILAR CONNECTION FOR ADG1207.
Figure 33. Enable Delay, tON (EN), tOFF (EN)
Rev. 0 | Page 17 of 20
ADG1ꢂ06VADG1ꢂ07
V
V
V
V
DD
SS
SS
DD
A0
A1
A2
A3
3V
V
V
IN
ADG12061
R
V
S
S
D
V
OUT
OUT
ΔV
EN
OUT
C
L
S
1nF
GND
Q
= C × ΔV
L OUT
INJ
V
IN
1
SIMILAR CONNECTION FOR ADG1207.
Figure 34. Charge Injection
V
V
DD
V
V
DD
SS
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
V
V
SS
DD
DD
SS
V
OUT
S1
R
L
S
50Ω
50Ω
50Ω
D
R
V
S
50Ω
S2
D
V
OUT
R
V
L
S
50Ω
GND
GND
V
OUT
V
OUT
OFF ISOLATION = 20 log
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
V
S
Figure 35. Off Isolation
Figure 37. Channel-to-Channel Crosstalk
V
V
V
DD
V
DD
SS
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
AUDIO PRECISION
V
V
V
DD
V
DD
SS
SS
R
S
S
S
50Ω
IN
V
S
V
S
V p-p
D
D
V
V
OUT
OUT
V
R
IN
R
L
L
50Ω
10kΩ
GND
GND
V
WITH SWITCH
OUT
WITHOUT SWITCH
INSERTION LOSS = 20 log
V
OUT
Figure 38. THD + Noise
Figure 36. Bandwidth
Rev. 0 | Page 18 of 20
ADG1ꢂ06VADG1ꢂ07
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 39. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
0.60
0.60
0.42
0.24
5.00
BSC SQ
0.42
0.24
0.45
BSC
25
32
1
24
4.75
BSC SQ
0.50
BSC
*
EXPOSED
PAD
2.85
2.70 SQ
2.55
PIN 1
INDICATOR
BOTTOM
VIEW
(TOP VIEW)
0.50
0.40
0.30
17
16
8
9
0.20
MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00 MAX
0.85 NOM
0.30
0.23
0.18
COPLANARITY
0.05
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220
WITH EXCEPTION TO PADDLE ORIENTATION.
Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Description
Package Option
RU-28
RU-28
CP-32-2
RU-28
RU-28
ADG1206YRUZ1
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
28-Lead Thin Shrink Small Outline Package [TSSOP]
28-Lead Thin Shrink Small Outline Package [TSSOP]
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
ADG1206YRUZ-REEL71
ADG1206YCPZ-REEL71
ADG1207YRUZ1
ADG1207YRUZ-REEL71
ADG1207YCPZ-REEL71
CP-32-2
1 Z = Pb-free part.
Rev. 0 | Page 19 of 20
ADG1ꢂ06VADG1ꢂ07
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06119-0-7/06(0)
Rev. 0 | Page 20 of 20
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