ADG1234YRUZ [ADI]

Low Capacitance, Triple/Quad SPDT +-15 V/+12 V i CMOS Switches; 低电容,三/四路SPDT ±15 V / + 12 V I CMOS开关
ADG1234YRUZ
型号: ADG1234YRUZ
厂家: ADI    ADI
描述:

Low Capacitance, Triple/Quad SPDT +-15 V/+12 V i CMOS Switches
低电容,三/四路SPDT ±15 V / + 12 V I CMOS开关

开关 光电二极管
文件: 总16页 (文件大小:469K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Low Capacitance, Triple/Quad SPDT  
± ±1 ꢀ/ꢁ±ꢂ ꢀ i CMOS™ Switches  
ADG±ꢂ33/ADG±ꢂ34  
FUNCTIONAL BLOCK DIAGRAMS  
FEATURES  
1.5 pF off capacitance  
0.5 pC charge injection  
33 V supply range  
120 Ω on resistance  
ADG1233  
S1A  
D1  
S3B  
D3  
S1B  
Fully specified at 15 V/+12 V  
3 V logic-compatible inputs  
Rail-to-rail operation  
S3A  
S2B  
D2  
Break-before-make switching action  
16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP  
Typical power consumption (<0.03 μW)  
S2A  
LOGIC  
APPLICATIONS  
IN1 IN2 IN3 EN  
SWITCHES SHOWN FOR A LOGIC 1 INPUT  
Audio and video routing  
Automatic test equipment  
Data acquisition systems  
Battery-powered systems  
Sample-and-hold systems  
Communication systems  
Figure 1.  
ADG1234  
S1A  
D1  
S4A  
D4  
S1B  
S4B  
GENERAL DESCRIPTION  
S2B  
D2  
S3B  
D3  
The ADG1233 and ADG1234 are monolithic iCMOS analog  
switches comprising three independently selectable single-pole,  
double throw SPDT switches and four independently selectable  
SPDT switches, respectively.  
S2A  
S3A  
LOGIC  
All channels exhibit break-before-make switching action  
preventing momentary shorting when switching channels.  
IN1 IN2 IN3 IN4 EN  
SWITCHES SHOWN FOR A LOGIC 1 INPUT  
EN  
An  
input on the ADG1233 and ADG1234 is used to  
Figure 2.  
enable or disable the device. When disabled, all channels are  
switched off.  
The iCMOS (industrial-CMOS) modular manufacturing process  
combines a high voltage complementary metal-oxide semi-  
conductor (CMOS) and bipolar technologies. It enables the  
development of a wide range of high performance analog ICs  
capable of 33 V operation in a footprint that no other generation of  
high voltage parts has been able to achieve. Unlike analog ICs  
using conventional CMOS processes, iCMOS components can  
tolerate high supply voltages while providing increased perfor-  
mance, dramatically lowered power consumption, and reduced  
package size.  
Fast switching speed coupled with high signal bandwidth make the  
parts suitable for video signal switching. iCMOS construction  
ensures ultralow power dissipation, making the parts ideally  
suited for portable and battery-powered instruments.  
PRODUCT HIGHLIGHTS  
1. 1.5 pF off capacitance ( 15 V supply).  
2. 0.5 pC charge injection.  
3. 3 V logic-compatible digital input, VIH = 2.0 V, VIL = 0.8 V.  
4. 16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP.  
The ultralow capacitance and charge injection of these multiplexers  
make them ideal solutions for data acquisition and sample-and-  
hold applications, where low glitch and fast settling are required.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2006 Analog Devices, Inc. All rights reserved.  
 
ADG±ꢂ33/ADG±ꢂ34  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Absolute Maximum Ratings ............................................................7  
ESD Caution...................................................................................7  
Pin Configurations and Function Descriptions............................8  
Terminology.......................................................................................9  
Typical Performance Characteristics ........................................... 10  
Test Circuits..................................................................................... 13  
Outline Dimensions....................................................................... 15  
Ordering Guide .......................................................................... 16  
Applications....................................................................................... 1  
General Description......................................................................... 1  
Functional Block Diagrams............................................................. 1  
Product Highlights ........................................................................... 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
Dual Supply................................................................................... 3  
Single Supply................................................................................. 5  
REVISION HISTORY  
8/06—Rev. 0 to Rev. A  
Updated Format…………………………….….…………Universal  
Changes to Table 1…………………………………………….…...3  
Changes to Table 2………………………………………………....4  
Changes to Figure 11……………………..………………………10  
Changes to Figure 12……………………………………………..11  
1/06—Revision 0: Initial Version  
Rev. A | Page 2 of 16  
 
ADG1233/ADG1234  
SPECIFICATIONS  
DUAL SUPPLY  
VDD = +15 V 10%, VSS = −15 V 10%, ꢀND = 0 V, unless otherwise noted.  
Table 1.  
Y Version1  
Parameter  
Unit  
Test Conditions/Comments  
+25°C −40°C to +85°C −40°C to +125°C  
ANALOG SWITCH  
Analog Signal Range  
On Resistance (RON)  
VSS to VDD  
V
120  
190  
3.5  
Ω typ  
Ω max  
Ω typ  
VS = 10 V, IS = −1 mA; see Figure 24  
VDD = +13.5 V, VSS = −13.5 V  
VS = 10 V, IS = −1 mA  
230  
260  
On Resistance Match Between  
Channels (∆RON)  
6
20  
60  
10  
72  
12  
79  
Ω max  
Ω typ  
Ω max  
On Resistance Flatness (RFLAT (ON)  
)
VS = −5 V, 0 V, +5 V; IS = −1 mA  
LEAKAGE CURRENTS  
VDD = +16.5 V, VSS = −16.5 V  
Source Off Leakage IS (Off)  
0.02  
0.1  
0.02  
nA typ  
nA max  
nA typ  
VD = 10 V, VS = −10 V; see Figure 25  
0.6  
1
Drain Off Leakage ID (Off)  
VS = 1 V/10 V, VD = 10 V/1 V;  
see Figure 25  
0.1  
0.02  
0.2  
0.6  
0.6  
1
1
nA max  
nA typ  
nA max  
Channel On Leakage ID, IS (On)  
VS = VD = 10 V; see Figure 26  
DIGITAL INPUTS  
Input High Voltage, VINH  
Input Low Voltage, VINL  
Input Current  
2.0  
0.8  
V min  
V max  
IINL or IINH  
0.005  
μA typ  
μA max  
pF typ  
VIN = VINL or VINH  
0.1  
Digital Input Capacitance, CIN  
DYNAMIC CHARACTERISTICS2  
tTRANSITION  
3
110  
130  
25  
ns typ  
ns max  
ns typ  
ns min  
ns typ  
ns max  
ns typ  
ns max  
pC typ  
RL = 300 Ω, CL = 35 pF  
VS = 10 V; see Figure 27  
RL = 300 Ω, CL = 35 pF  
VS1 = VS2 = +10 V; see Figure 28  
RL = 300 Ω, CL = 35 pF  
VS = 10 V; see Figure 29  
RL = 300 Ω, CL = 35 pF  
VS = 10 V; see Figure 29  
150  
170  
10  
tBBM  
tON (EN)  
tOFF (EN)  
120  
140  
40  
170  
55  
195  
60  
45  
0.5  
Charge Injection  
VS = 0 V, RS = 0 Ω, CL = 1 nF;  
see Figure 30  
Off Isolation  
−80  
−85  
0.14  
dB typ  
dB typ  
% typ  
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see  
Figure 31  
RL = 50 Ω, CL = 5 pF, f = 1 MHz;  
see Figure 33  
RL = 10 kΩ, 5 V rms, f = 20 Hz to  
20 kHz; see Figure 34  
Channel-to-Channel Crosstalk  
Total Harmonic Distortion, THD + N  
−3 dB Bandwidth  
CS (Off)  
900  
1.5  
1.7  
1.6  
1.8  
3.5  
4
MHz typ  
pF typ  
pF max  
pF typ  
pF max  
pF typ  
pF max  
RL = 50 Ω, CL = 5 pF; see Figure 32  
f = 1 MHz; VS = 0 V  
f = 1 MHz; VS = 0 V  
f = 1 MHz; VS = 0 V  
f = 1 MHz; VS = 0 V  
CD (Off)  
CD, CS (On)  
f = 1 MHz; VS = 0 V  
f = 1 MHz; VS = 0 V  
Rev. A | Page 3 of 16  
 
ADG±ꢂ33/ADG±ꢂ34  
Y Version1  
Parameter  
Unit  
Test Conditions/Comments  
VDD = +16.5 V, VSS = −16.5 V  
Digital inputs = 0 V or VDD  
+25°C −40°C to +85°C −40°C to +125°C  
POWER REQUIREMENTS  
IDD  
0.002  
μA typ  
1.0  
μA max  
μA typ  
IDD  
260  
Digital inputs = 5 V  
Digital inputs = 0 V or VDD  
Digital inputs = 5 V  
GND = 0 V  
420  
μA max  
μA typ  
μA max  
μA typ  
μA max  
V min/max  
ISS  
0.002  
0.002  
1.0  
1.0  
ISS  
VDD/VSS  
5/ 16.5  
1 Temperature range for the Y version: −40°C to +125°C.  
2 Guaranteed by design, not subject to production test.  
Rev. A | Page 4 of 16  
 
 
 
ADG1233/ADG1234  
SINGLE SUPPLY  
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.  
Table 2.  
Y Version1  
Parameter  
+25°C −40°C to +85°C −40°C to +125°C Unit  
Test Conditions/Comments  
ANALOG SWITCH  
Analog Signal Range  
On Resistance (RON)  
0 to VDD  
625  
V
300  
Ω typ  
VS = 0 V to10 V, IS = −1 mA;  
see Figure 24  
VDD = 10.8 V, VSS = 0 V  
475  
5
567  
26  
Ω max  
Ω typ  
On Resistance Match Between  
Channels (∆RON)  
VS = 0 V to10 V, IS = −1 mA  
16  
60  
27  
Ω max  
Ω typ  
On Resistance Flatness (RFLAT (ON)  
LEAKAGE CURRENTS  
)
VS = 3 V, 6 V, 9 V, IS = −1 mA  
VDD = 13.2 V  
Source Off Leakage IS (Off)  
0.02  
nA typ  
VS = 1 V/10 V, VD = 10 V/1 V;  
see Figure 25  
0.1  
0.02  
0.6  
1
nA max  
nA typ  
Drain Off Leakage ID (Off)  
VS = 1 V/10 V, VD = 10 V/1 V;  
see Figure 25  
0.1  
0.02  
0.2  
0.6  
0.6  
1
1
nA max  
nA typ  
nA max  
Channel On Leakage ID, IS (On)  
VS = VD = 1 V or 10 V, see Figure 26  
DIGITAL INPUTS  
Input High Voltage, VINH  
Input Low Voltage, VINL  
Input Current, IINL or IINH  
2.0  
0.8  
V min  
V max  
μA typ  
μA max  
pF typ  
0.001  
0.1  
VIN = VINL or VINH  
Digital Input Capacitance, CIN  
DYNAMIC CHARACTERISTICS2  
tTRANSITION  
2
135  
170  
45  
ns typ  
RL = 300 Ω, CL = 35 pF  
VS = 8 V; see Figure 27  
RL = 300 Ω, CL = 35 pF  
VS1 = VS2 = 8 V; see Figure 28  
RL = 300 Ω, CL = 35 pF  
VS = 8 V; see Figure 29  
RL = 300 Ω, CL = 35 pF  
VS = 8 V; see Figure 29  
200  
230  
10  
tBBM  
ns typ  
ns min  
ns typ  
tON (EN)  
tOFF (EN)  
150  
195  
45  
230  
70  
265  
75  
ns typ  
60  
Charge Injection  
−0.3  
pC typ  
dB typ  
dB typ  
VS = 6 V, RS = 0 Ω, CL = 1 nF; see  
Figure 30  
RL = 50 Ω, CL = 5 pF, f = 1 MHz;  
see Figure 31  
RL = 50 Ω, CL = 5 pF, f = 1 MHz;  
see Figure 33  
Off Isolation  
−80  
−85  
Channel-to-Channel Crosstalk  
−3 dB Bandwidth  
CS (Off)  
600  
1.5  
1.7  
2
MHz typ  
pF typ  
pF max  
pF typ  
RL = 50 Ω, CL = 5 pF; see Figure 32  
f = 1 MHz; VS = 6 V  
f = 1 MHz; VS = 6 V  
CD (Off)  
f = 1 MHz; VS = 6 V  
2.2  
4
pF max  
pF typ  
f = 1 MHz; VS = 6 V  
f = 1 MHz; VS = 6 V  
CD, CS (On)  
4.5  
pF max  
f = 1 MHz; VS = 6 V  
Rev. A | Page 5 of 16  
 
ADG±ꢂ33/ADG±ꢂ34  
Y Version1  
Parameter  
POWER REQUIREMENTS  
IDD  
+25°C −40°C to +85°C −40°C to +125°C Unit  
Test Conditions/Comments  
VDD = 13.2 V  
Digital inputs = 0 V or VDD  
0.002  
260  
μA typ  
μA max  
μA typ  
1.0  
IDD  
Digital inputs = 5 V  
VSS = 0 V, GND = 0 V  
440  
5/16.5  
μA max  
V min/max  
VDD  
1 Temperature range for the Y version: −40°C to +125°C  
2 Guaranteed by design, not subject to production test.  
Rev. A | Page 6 of 16  
 
 
 
ADG1233/ADG1234  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C, unless otherwise noted.  
Table 3.  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Parameter  
Rating  
VDD to VSS  
35 V  
VDD to GND  
VSS to GND  
Analog, Digital Inputs1  
−0.3 V to +25 V  
+0.3 V to −25 V  
VSS − 0.3 V to VDD + 0.3 V or  
30 mA, whichever  
occurs first  
Only one absolute maximum rating is applied at any one time.  
Continuous Current, S or D  
24 mA  
Peak Current, S or D (Pulsed at  
1 ms, 10% Duty Cycle Mximum)  
100 mA  
Operating Temperature Range  
Automotive Temperature Range  
(Y Version)  
–40°C to +125°C  
Storage Temperature Range  
Junction Temperature  
–65°C to +150°C  
150°C  
TSSOP, θJA, Thermal Impedance  
LFCSP, θJA, Thermal Impedance  
112°C/W  
30.4°C/W  
Reflow Soldering Peak Temperature, 260°C  
Pb-Fee  
1
EN  
Overvoltages at A, , S, or D are clamped by internal diodes. Current should  
be limited to the maximum ratings given.  
ESD CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on  
the human body and test equipment and can discharge without detection. Although this product features  
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy  
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance  
degradation or loss of functionality.  
Rev. A | Page 7 of 16  
 
 
ADG±ꢂ33/ADG±ꢂ34  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
GND  
DD  
S1A  
D1  
IN1  
EN  
ADG1233  
TOP VIEW  
(Not to Scale)  
PIN 1  
INDICATOR  
12 EN  
11 V  
D1  
S1B  
S2B  
D2  
1
2
3
4
S1B  
S2B  
D2  
V
SS  
SS  
S3B  
D3  
ADG1233  
TOP VIEW  
(Not to Scale)  
10 S3B  
D3  
9
S2A  
IN2  
S3A  
IN3  
Figure 3. 16-Lead TSSOP Pin Configuration  
Figure 5. 16-Lead, 4 mm × 4 mm LFCSP Pin Configuration,  
Exposed Pad Tied to Substrate, VSS  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
IN1  
S1A  
D1  
IN4  
S4A  
D4  
3
ADG1234  
TOP VIEW  
(Not to Scale)  
4
S1B  
S4B  
PIN 1  
INDICATOR  
5
V
V
D1  
S1B  
1
2
3
4
5
15 D4  
14 S4B  
SS  
DD  
6
GND  
S2B  
D2  
EN  
ADG1234  
TOP VIEW  
(Not to Scale)  
V
13 V  
SS  
DD  
7
GND  
S2B  
12 S3B  
11 D3  
S3B  
D3  
8
9
S2A  
IN2  
S3A  
IN3  
10  
Figure 4. 20-Lead TSSOP Pin Configuration  
Figure 6. 20-Lead, 4 mm × 4 mm LFCSP Pin Configuration  
Exposed Pad Tied to Substrate, VSS  
Table 4. 16-Lead TSSOP/20-Lead TSSOP Pin Configurations  
Table 5. 16-Lead LFCSP/20-Lead LFCSP Pin Configurations  
Pin No. ADG1233  
16-Lead TSSOP  
1
2
3
4
5
6
Pin No. ADG1234  
20-Lead TSSOP  
16  
2
3
4
Pin No. ADG1233  
16-Lead LFCSP  
1
2
3
4
5
6
Pin No. ADG1234  
20-Lead LFCSP  
1
2
5
6
7
8
Mnemonic  
VDD  
S1A  
D1  
S1B  
S2B  
D2  
Mnemonic  
D1  
S1B  
S2B  
D2  
7
8
S2A  
IN2  
7
8
9
9
S2A  
IN2  
IN3  
S3A  
D3  
S3B  
VSS  
7
8
9
9
IN3  
S3A  
D3  
S3B  
VSS  
EN  
10  
11  
12  
13  
14  
5
15  
1
6
17  
18  
19  
20  
10  
11  
12  
3
18  
19  
4
13  
20  
14  
15  
16  
17  
10  
11  
12  
13  
14  
15  
16  
N/A  
N/A  
N/A  
N/A  
10  
11  
12  
13  
14  
15  
16  
N/A  
N/A  
N/A  
N/A  
IN1  
GND  
VDD  
S1A  
S4B  
D4  
S4A  
IN4  
EN  
IN1  
GND  
S4B  
D4  
S4A  
IN4  
Table 6. ADG1233/ADG1234 Truth Table  
EN  
INx  
X
0
Switch xA  
Switch xB  
1
0
0
Off  
Off  
On  
Off  
On  
Off  
1
Rev. A | Page 8 of 16  
 
ADG±ꢂ33/ADG±ꢂ34  
TERMINOLOGY  
VDD  
EN  
( )  
tOFF  
Most positive supply potential.  
Delay time between the 50% and 90% points of the digital input  
and switch off condition.  
VSS  
Most negative power supply potential in dual supplies. In  
single-supply applications, it can be connected to ground.  
tTRANSITION  
Delay time between the 50% and 90% points of the digital  
inputs and the switch on condition when switching from one  
address state to another.  
GND  
Ground (0 V) reference.  
tBBM  
RON  
Off time measured between the 80% point of both switches  
when switching from one address state to another.  
Ohmic resistance between D and S.  
ΔRON  
VINL  
Difference between the RON of any two channels.  
Maximum input voltage for Logic 0.  
IS (Off)  
VINH  
Source leakage current when switch is off.  
Minimum input voltage for Logic 1.  
ID (Off)  
IINL, IINH  
Drain leakage current when switch is off.  
Input current of the digital input.  
ID, IS (On)  
IDD  
Channel leakage current when switch is on.  
Positive supply current.  
VD, VS  
ISS  
Analog voltage on Terminal D, Terminal S.  
Negative supply current.  
CS (Off)  
Off Isolation  
Channel input capacitance for off condition.  
A measure of an unwanted signal coupling through an off channel.  
CD (Off)  
Charge Injection  
A measure of the glitch impulse transferred from the digital  
input to the analog output during switching.  
Channel output capacitance for off condition.  
CD, CS (On)  
On switch capacitance.  
Bandwidth  
Frequency at which the output is attenuated by 3 dB.  
CIN  
Digital input capacitance.  
On Response  
Frequency response of the on switch.  
EN  
)
tON  
(
Delay time between the 50% and 90% points of the digital input  
and switch on condition.  
THD + N  
Ratio of the harmonic amplitude plus noise of the signal to the  
fundamental.  
Rev. A | Page 9 of 16  
 
ADG±ꢂ33/ADG±ꢂ34  
TYPICAL PERFORMANCE CHARACTERISTICS  
200  
250  
V
V
= +15V  
= –15V  
DD  
SS  
T
= 25°C  
A
V
V
= +15V  
= –15V  
DD  
SS  
180  
160  
140  
120  
100  
80  
V
V
= +13.5V  
= –13.5V  
DD  
SS  
200  
150  
T
T
= +125°C  
= +85°C  
A
A
T
= +25°C  
= –40°C  
A
A
V
V
= +16.5V  
= –16.5V  
DD  
SS  
100  
T
60  
40  
50  
0
20  
0
–18 –15 –12 –9 –6 –3  
0
3
6
9
12 15 18  
–15  
–10  
–5  
0
5
10  
15  
SOURCE OR DRAIN VOLTAGE (V)  
TEMPERATURE (°C)  
Figure 7. On Resistance as a Function of VD (VS ) for Dual Supply  
Figure 10. On Resistance as a Function of VD (VS ) for Different  
Temperatures, Dual Supply  
450  
600  
V
V
= 12V  
= 0V  
DD  
SS  
T
= 25°C  
V
V
= 10.8V  
= 0V  
A
DD  
SS  
T
= +125°C  
400  
350  
300  
250  
200  
150  
100  
A
500  
400  
300  
200  
V
V
= 12V  
= 0V  
DD  
SS  
T
= +85°C  
A
T
= +25°C  
A
V
V
= 13.2V  
= 0V  
DD  
SS  
T
= –40°C  
A
100  
0
50  
0
0
2
4
6
8
10  
12  
14  
0
2
4
6
8
10  
12  
SOURCE OR DRAIN VOLTAGE (V)  
TEMPERATURE (°C)  
Figure 11. On Resistance as a Function of VD (VS ) for Different  
Temperatures, Single Supply  
Figure 8. On Resistance as a Function of VD (VS ) for Dual Supply  
450  
250  
T
= 25°C  
V
V
V
= +15V  
= –15V  
V
V
= 10.8V  
= 0V  
A
DD  
SS  
DD  
SS  
200  
150  
100  
50  
400  
350  
300  
250  
200  
150  
100  
= +10V/–10V  
BIAS  
V
V
= 12V  
= 0V  
DD  
SS  
V
V
= 13.2V  
= 0V  
DD  
SS  
0
–50  
I
(OFF) + –  
(OFF) + –  
(OFF) – +  
(OFF) – +  
–100  
–150  
S
I
I
I
I
I
D
S
D
D
D
50  
0
, I (ON) – –  
S
–200  
–250  
, I (ON) + +  
S
0
2
4
6
8
10  
12  
14  
0
20  
40  
60  
80  
100  
120  
SOURCE OR DRAIN VOLTAGE (V)  
TEMPERATURE (°C)  
Figure 9. On Resistance as a Function of VD (VS ) for Single Supply  
Figure 12. Leakage Currents as a Function of Temperature, Dual Supply  
Rev. A | Page 10 of 16  
 
ADG±ꢂ33/ADG±ꢂ34  
130  
80  
220  
200  
180  
160  
140  
120  
100  
80  
V
V
V
= 12V  
= 0V  
DD  
SS  
A
B
12V DS  
OFF ON  
= 1V/10V  
BIAS  
A
B
15V DS  
OFF ON  
30  
–20  
I
I
I
I
I
I
(OFF) + –  
(OFF) + –  
(OFF) – +  
(OFF) – +  
S
D
S
D
D
D
60  
B
A
15V DS  
OFF ON  
–70  
B
A
12V DS  
40  
40  
OFF ON  
, I (ON) – –  
S
20  
0
, I (ON) + +  
S
–120  
0
20  
40  
60  
80  
100  
120  
–40  
–20  
0
20  
60  
80  
100  
120  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 13. Leakage Currents as a Function of Temperature, Single Supply  
Figure 16. tTRANSITION vs. Temperature  
0
V
V
= +15V  
= –15V  
= 25°C  
200  
DD  
SS  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
I
T
PER CHANNEL  
= 25°C  
DD  
T
A
180  
160  
140  
120  
100  
80  
A
V
V
= +15V  
= –15V  
DD  
SS  
60  
40  
–100  
–110  
V
V
= 12V  
= 0V  
DD  
SS  
20  
0
10k  
100k  
1M  
10M  
100M  
1G  
FREQUENCY (Hz)  
0
2
4
6
8
10  
12  
14  
16  
LOGIC, IN (V)  
X
Figure 14. IDD vs. Logic Level  
Figure 17. Off Isolation vs. Frequency  
6
4
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
T
= 25°C  
V
= +15V  
= –15V  
= 25°C  
V
V
= +15V  
= –15V  
A
DD  
SS  
DD  
SS  
V
T
A
V
V
= +5V  
= –5V  
DD  
SS  
2
0
SxA – SxB  
V
= 12V  
DD  
SS  
V
= 0V  
–2  
S1x – S2x  
–4  
–6  
–90  
–100  
–15  
–10  
–5  
0
5
10  
15  
10k  
100k  
1M  
10M  
100M  
1G  
V
(V)  
FREQUENCY (Hz)  
S
Figure 18. Crosstalk vs. Frequency  
Figure 15. Charge Injection vs. Source Voltage  
Rev. A | Page 11 of 16  
ADG±ꢂ33/ADG±ꢂ34  
0
5.0  
V
V
= +15V  
= –15V  
= 25°C  
V
V
= 12V  
= 0V  
DD  
DD  
SS  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
SS  
T
T = 25°C  
A
A
–5  
SOURCE/DRAIN ON  
–10  
–15  
DRAIN OFF  
SOURCE OFF  
–20  
–25  
0.5  
0
0
2
4
6
8
10  
12  
10k  
100k  
1M  
10M  
100M  
1G  
10G  
V
(V)  
FREQUENCY (Hz)  
BIAS  
Figure 19. On Response vs. Frequency  
Figure 22. Capacitance vs. Source Voltage for Single Supply  
10  
5.0  
V
V
= +5V  
= –5V  
= 25°C  
LOAD = 10k  
= 25°C  
DD  
SS  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
T
A
T
A
SOURCE/DRAIN ON  
1
V
= +5V, V = –5V, V = +3.5V rms  
SS  
DD  
S
DRAIN OFF  
V
= +15V, V = –15V, V = +5V rms  
SS  
DD  
S
0.10  
0.01  
SOURCE OFF  
0.5  
0
–5  
–4  
–3  
–2  
–1  
0
1
2
3
4
5
10  
100  
1k  
FREQUENCY (Hz)  
10k  
100k  
V
(V)  
BIAS  
Figure 20. THD + N vs. Frequency  
Figure 23. Capacitance vs. Source Voltage for Dual Supply  
5.0  
V
V
= +15V  
= –15V  
= 25°C  
DD  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
SS  
T
A
SOURCE/DRAIN ON  
DRAIN OFF  
SOURCE OFF  
0.5  
0
–15  
–10  
–5  
0
5
10  
15  
V
(V)  
BIAS  
Figure 21. Capacitance vs. Source Voltage for Dual Supply  
Rev. A | Page 12 of 16  
ADG±ꢂ33/ADG±ꢂ34  
TEST CIRCUITS  
V
S
D
I
DS  
V
S
Figure 24. On Resistance  
I
(OFF)  
A
I (OFF)  
D
S
S
D
A
V
V
S
D
Figure 25. Off Leakage  
I
(ON)  
D
S
D
NC  
A
V
D
NC = NO CONNECT  
Figure 26. On Leakage  
V
V
DD  
SS  
0.1µF  
0.1µF  
V
V
IN  
50%  
50%  
50%  
V
V
SS  
DD  
SxB  
SxA  
V
IN  
S
50%  
D
V
OUT  
R
300  
C
35pF  
L
L
90%  
90%  
INx  
V
OUT  
V
IN  
GND  
tON  
tOFF  
Figure 27. Switching Timing  
V
DD  
V
SS  
0.1µF  
0.1µF  
V
IN  
V
V
SS  
DD  
SxB  
V
S
D
V
OUT  
SxA  
INx  
80%  
V
R
300  
C
35pF  
OUT  
L
L
tBBM  
tBBM  
V
IN  
GND  
Figure 28. Break-Before-Make Delay  
Rev. A | Page 13 of 16  
 
 
 
 
 
 
ADG±ꢂ33/ADG±ꢂ34  
V
V
V
DD  
SS  
0.1µF  
0.1µF  
3V  
V
ENABLE  
DRIVE (V  
DD  
SS  
50%  
50%  
)
IN  
IN3  
IN2  
IN1  
V
S1A  
S1B  
S
0V  
tOFF (EN)  
0.9V  
ADG1233  
V
O
0.9V  
V
EN  
D1  
O
O
O
R
C
L
35pF  
V
L
300Ω  
IN  
OUTPUT  
0V  
50Ω  
GND  
tON (EN)  
EN  
), tOFF  
EN  
)
Figure 29. Enable Delay, tON  
(
(
V
V
DD  
SS  
0.1µF  
0.1µF  
V
(NORMALLY  
IN  
CLOSED SWITCH)  
V
V
SS  
DD  
ON  
OFF  
SxB  
SxA  
NC  
V
D
V
S
V
(NORMALLY  
IN  
OPEN SWITCH)  
OUT  
C
1nF  
L
INx  
V
ΔV  
OUT  
OUT  
V
IN  
Q
= C × ΔV  
L
OUT  
GND  
INJ  
Figure 30. Charge Injection  
V
V
DD  
V
V
SS  
DD  
SS  
0.1µF  
0.1µF  
0.1µF  
0.1µF  
NETWORK  
ANALYZER  
NETWORK  
ANALYZER  
V
V
DD  
V
V
SS  
DD  
SS  
NC  
SxA  
50  
V
OUT  
R
L
SxA  
SxB  
50Ω  
50  
INx  
V
S
SxB  
D
R
D
50Ω  
V
OUT  
V
INx  
IN  
R
L
50Ω  
V
S
GND  
GND  
V
V
OUT  
OFF ISOLATION = 20 log  
V
OUT  
S
CHANNEL-TO-CHANNEL CROSSTALK = 20 log  
V
S
Figure 31. Off Isolation  
Figure 33. Channel-to-Channel Crosstalk  
V
V
V
DD  
V
SS  
DD  
SS  
0.1µF  
0.1µF  
0.1µF  
0.1µF  
NETWORK  
ANALYZER  
AUDIO PRECISION  
V
V
DD  
V
V
SS  
SS  
DD  
NC  
50Ω  
R
S
S
SxA  
SxB  
INx  
INx  
V
S
V
S
V p-p  
D
D
V
OUT  
V
OUT  
V
IN  
R
50Ω  
V
L
IN  
R
L
10  
GND  
GND  
V
WITH SWITCH  
OUT  
INSERTION LOSS = 20 log  
V
WITHOUT SWITCH  
OUT  
Figure 32. Bandwidth  
Figure 34. THD + Noise  
Rev. A | Page 14 of 16  
 
 
 
 
 
ADG1233/ADG1234  
OUTLINE DIMENSIONS  
5.10  
5.00  
4.90  
16  
9
8
4.50  
4.40  
4.30  
6.40  
BSC  
1
PIN 1  
1.20  
MAX  
0.15  
0.05  
0.20  
0.09  
0.75  
0.60  
0.45  
8°  
0°  
0.30  
0.19  
0.65  
BSC  
SEATING  
PLANE  
COPLANARITY  
0.10  
COMPLIANT TO JEDEC STANDARDS MO-153-AB  
Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]  
(RU-16)  
Dimensions shown in millimeters  
6.60  
6.50  
6.40  
20  
11  
10  
4.50  
4.40  
4.30  
6.40 BSC  
1
PIN 1  
0.65  
BSC  
1.20 MAX  
0.15  
0.05  
0.20  
0.09  
0.75  
0.60  
0.45  
8°  
0°  
0.30  
0.19  
COPLANARITY  
0.10  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-153-AC  
Figure 36. 20-Lead Thin Shrink Small Outline Package [TSSOP]  
(RU-20)  
Dimensions shown in millimeters  
Rev. A | Page 15 of 17  
 
ADG1233/ADG1234  
4.00  
0.60 MAX  
(BOTTOM VIEW)  
BSC SQ  
0.60 MAX  
0.65 BSC  
PIN 1  
INDICATOR  
13  
16  
1
12  
PIN 1  
INDICATOR  
2.25  
2.10 SQ  
1.95  
TOP  
VIEW  
3.75  
BSC SQ  
EXPOSED  
PAD  
0.75  
0.60  
0.50  
9
4
8
5
0.25 MIN  
1.95 BSC  
0.80 MAX  
0.65 TYP  
12° MAX  
0.05 MAX  
0.02 NOM  
1.00  
0.85  
0.80  
0.35  
0.30  
0.25  
0.20 REF  
COPLANARITY  
0.08  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC  
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]  
4 mm × 4 mm Body, Very Thin Quad  
(CP-16-4)  
Dimensions shown in millimeters  
0.60  
MAX  
4.00  
BSC SQ  
PIN 1  
INDICATOR  
0.60  
MAX  
20  
16  
15  
1
PIN 1  
INDICATOR  
2.25  
2.10 SQ  
1.95  
TOP  
VIEW  
3.75  
BCS SQ  
11  
10  
5
0.75  
0.55  
0.35  
6
0.25 MIN  
0.80 MAX  
0.65 TYP  
0.30  
0.23  
0.18  
12° MAX  
1.00  
0.85  
0.80  
0.05 MAX  
0.02 NOM  
0.20  
REF  
COPLANARITY  
0.08  
SEATING  
PLANE  
0.50  
BSC  
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1  
Figure 38. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]  
4 mm × 4 mm Body, Very Thin Quad  
(CP-20-1)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model  
Temperature Range  
−40°C to +125°C  
−40°C to +125°C  
−40°C to +125°C  
−40°C to +125°C  
−40°C to +125°C  
−40°C to +125°C  
−40°C to +125°C  
−40°C to +125°C  
Package Description  
Package Option  
RU-16  
RU-16  
CP-16-4  
CP-16-4  
RU-20  
RU-20  
CP-20-1  
CP-20-1  
ADG1233YRUZ1  
16-Lead Thin Shrink Small Outline Package (TSSOP)  
16-Lead Thin Shrink Small Outline Package (TSSOP)  
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)  
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)  
20-Lead Thin Shrink Small Outline Package (TSSOP)  
20-Lead Thin Shrink Small Outline Package (TSSOP)  
20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)  
20-Lead Lead Frame Chip Scale Package (LFCSP_VQ)  
ADG1233YRUZ-REEL71  
ADG1233YCPZ-REEL1  
ADG1233YCPZ-REEL71  
ADG1234YRUZ1  
ADG1234YRUZ-REEL71  
ADG1234YCPZ-REEL1  
ADG1234YCPZ-REEL71  
1 Z = Pb-free part.  
©2006 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D05743-0-8/06(A)  
Rev. A | Page 16 of 16  
 
 
 
 
 
 
 

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