ADG1236YCPZ-500RL7 [ADI]
Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS, Dual SPDT Switch;
| 型号： | ADG1236YCPZ-500RL7 |
| 厂家： | 
ADI |
| 描述： | Low Capacitance, Low Charge Injection, ±15 V/12 V iCMOS, Dual SPDT Switch 光电二极管 输出元件 |
| 文件： | 总17页 (文件大小：394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Capacitance, Low Charge Injection,
15 V/12 V iCMOS, Dual SPDT Switch
Data Sheet
ADG1236
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.3 pF off capacitance
3.5 pF on capacitance
ADG1236
S1A
D1
1 pC charge injection
33 V supply range
S1B
120 Ω on resistance
Fully specified at +12 V, 15 V
No VL supply required
IN1
IN2
3 V logic-compatible inputs
Rail-to-rail operation
S2A
D2
16-lead TSSOP and 12-lead LFCSP packages
Typical power consumption: <0.03 µW
S2B
APPLICATIONS
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio/video signal routing
Communication systems
Figure 1.
GENERAL DESCRIPTION
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use in
multiplexer applications.
The ADG1236 is a monolithic CMOS device containing two
independently selectable SPDT switches. It is designed on an
iCMOS® process. iCMOS (industrial CMOS) is a modular
manufacturing process combining high voltage complementary
metal-oxide semiconductor (CMOS) and bipolar technologies.
It enables the development of a wide range of high performance
analog ICs capable of 33 V operation in a footprint that no
previous generation of high voltage devices has been able to
achieve. Unlike analog ICs using conventional CMOS processes,
iCMOS components can tolerate high supply voltages while
providing increased performance, dramatically lower power
consumption, and reduced package size.
PRODUCT HIGHLIGHTS
1. 1.3 pF off capacitance ( 15 V supply).
2. 1 pC charge injection.
3. 3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
4. No VL logic power supply required.
5. Ultralow power dissipation: <0.03 µW.
6. 16-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP packages.
The ultralow capacitance and charge injection of the device
make it an ideal solution for data acquisition and sample-and-
hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth makes
the device suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the device ideally
suited for portable and battery-powered instruments.
Rev. A
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ADG1236* PRODUCT PAGE QUICK LINKS
Last Content Update: 11/29/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Product Selection Guide
• Switches and Multiplexers Product Selection Guide
Technical Articles
EVALUATION KITS
• Evaluation Board for 16 lead TSSOP Devices in the Switch/
Mux Portfolio
• CMOS Switches Offer High Performance in Low Power,
Wideband Applications
• Data-acquisition system uses fault protection
DOCUMENTATION
Application Notes
DESIGN RESOURCES
• ADG1236 Material Declaration
• PCN-PDN Information
• AN-874: Operating the ADG12xx Series of Parts with 5 V
Supplies and the Impact on Performance
Data Sheet
• Quality And Reliability
• Symbols and Footprints
• ADG1236: Low Capacitance, Low Charge Injection, ±15 V/
12 V iCMOS, Dual SPDT Switch Data Sheet
User Guides
DISCUSSIONS
View all ADG1236 EngineerZone Discussions.
• UG-945: Evaluation Board for 16-Lead TSSOP Devices in
the Switches and Multiplexers Portfolio
SAMPLE AND BUY
Visit the product page to see pricing options.
TOOLS AND SIMULATIONS
• ADG1236 SPICE Macro Model
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
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ADG1236
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Truth Table for Switches...............................................................6
Pin Configurations and Function Descriptions............................7
Terminology.......................................................................................8
Typical Performance Characteristics ..............................................9
Test Circuits..................................................................................... 12
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply................................................................................... 3
Single Supply................................................................................. 5
REVISION HISTORY
3/16—Rev. 0 to Rev. A
Changes to Figure 2 and Figure 3................................................... 7
Updated Outline Dimensions....................................................... 14
Changes to Ordering Guide .......................................................... 14
9/05—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
ADG1236
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V 10%, VSS = −15 V 10%, ꢀGD = 0 V, unless otherwise noted.
Table 1.
Y Version1
Parameters
25°C
−40°C to +85°C −40°C to +125°C
Unit
Test Conditions/Comments1
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
VDD to VSS
V
120
190
3.5
Ω typ
Ω max
Ω typ
VS = 10 V, IS = −1 mA; Figure 20
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −1 mA
230
260
On Resistance Match Between
Channels (∆RON)
6
20
57
10
72
12
79
Ω max
Ω typ
Ω max
On Resistance Flatness (RFLAT(ON)
)
VS = −5 V, 0 V, +5 V; IS = −1 mA
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.02
nA typ
VS = 10 V, VS = ∓10 V; Figure 21
0.1
0.02
0.6
1
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 10 V, VS = ∓10 V; Figure 21
0.1
0.02
0.2
0.6
0.6
1
1
nA max
nA typ
nA max
Channel On Leakage, ID, IS (On)
VS = VD = 10 V; Figure 22
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
μA typ
μA max
pF typ
0.005
2
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANS AOFF BON
125
150
70
90
25
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS = 10 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; Figure 24
VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 26
200
115
10
Transition Time, tTRANS BOFF AON
Break-Before-Make Time Delay, tD
Charge Injection
Off Isolation
−1
80
Channel-to-Channel Crosstalk
85
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 27
RL = 10 kΩ, 5 V rms, f = 20 Hz to
20 kHz
Total Harmonic Distortion + Noise
0.15
−3 dB Bandwidth
CS (Off)
1000
1.3
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF; Figure 28
f = 1 MHz; VS = 0 V
1.6
3.5
pF max
pF typ
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
CD, CS (On)
4.3
pF max
f = 1 MHz; VS = 0 V
Rev. A | Page 3 of 16
ADG1236
Data Sheet
Y Version1
−40°C to +85°C −40°C to +125°C
Parameters
25°C
0.001
170
Unit
Test Conditions/Comments1
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
1.0
230
1.0
1.0
IDD
ISS
ISS
Digital inputs = 5 V
0.001
0.001
Digital inputs = 0 V or VDD
Digital inputs = 5 V
1 Temperature range for Y version is −40°C to +125°C.
2 Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 16
Data Sheet
ADG1236
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Y Version1
Parameters
25°C −40°C to +85°C −40°C to +125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
0 V to VDD
625
V
300
475
4.5
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −1 mA; Figure 20
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
567
26
On Resistance Match Between
Channels (∆RON)
16
60
27
Ω max
Ω typ
On Resistance Flatness (RFLAT(ON)
LEAKAGE CURRENTS
)
VS = 3 V, 6 V, 9 V, IS = −1 mA
VDD = 13.2 V
Source Off Leakage, IS (Off)
0.02
0.1
0.02
0.1
0.02
0.2
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 1 V/10 V, VD = 10 V/1 V; Figure 21
0.6
0.6
0.6
1
1
1
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V; Figure 21
VS = VD = 1 V or 10 V, Figure 22
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.001
3
VIN = VINL or VINH
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS2
Transition Time, tTRANS BOFF AON
105
140
155
190
50
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; Figure 24
VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 26;
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
175
255
10
Transition Time, tTRANS AOFF BON
Break-Before-Make Time Delay, tD
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off)
−0.8
75
85
800
1.6
1.9
4
MHz typ RL = 50 Ω, CL = 5 pF; Figure 28
pF typ
pF max
pF typ
pF max
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
VDD = 13.2 V
CD, CS (On)
4.9
POWER REQUIREMENTS
IDD
0.001
170
µA typ
µA max
µA typ
µA max
Digital inputs = 0 V or VDD
1.0
IDD
Digital inputs = 5 V
230
1 Temperature range for Y version is −40°C to +125°C.
2 Guaranteed by design; not subject to production test.
Rev. A | Page 5 of 16
ADG1236
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Parameter
Rating
VDD to VSS
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
ESD CAUTION
Peak Current, S or D
100 mA (pulsed at 1 ms,
10% duty cycle max)
Continuous Current per
Channel, S or D
25 mA
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
−40°C to +125°C
−65°C to +150°C
150°C
TRUTH TABLE FOR SWITCHES
Table 4.
IN
16-Lead TSSOP, θJA Thermal
Impedance
112°C/W
Switch A
Off
On
Switch B
On
Off
0
1
12-Lead LFCSP, θJA Thermal
Impedance
Reflow Soldering Peak
Temperature, Pb Free
80°C/W
260°C
1 Over voltages at IN, S, or D are clamped by internal diodes. Current must be
limited to the maximum ratings given.
Rev. A | Page 6 of 16
Data Sheet
ADG1236
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN1
S1A
D1
NC
NC
NC
D1
1
9
V
DD
ADG1236
S1B 2
8 S2B
TOP VIEW
(Not to Scale)
S1B
ADG1236
V
DD
3
7
D2
V
SS
TOP VIEW
V
S2B
D2
(Not to Scale)
SS
GND
NC
S2A
IN2
NOTES
NC
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MUST BE TIED
NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
TO SUBSTRATE, V
.
SS
Figure 2. TSSOP Pin Configuration
Figure 3. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
LFCSP
TSSOP
Mnemonic
IN1
Description
1
2
3
4
5
6
11
12
1
2
3
Logic Control Input.
S1A
D1
S1B
VSS
GND
NC
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
4
7, 8, 14 to 16 10
No Connect.
9
5
6
7
8
9
IN2
S2A
D2
S2B
VDD
Logic Control Input.
10
11
12
13
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Positive Power Supply Potential.
Rev. A | Page 7 of 16
ADG1236
Data Sheet
TERMINOLOGY
IDD
CD (Off)
The positive supply current.
The off switch drain capacitance, measured with reference to
ground.
ISS
The negative supply current.
CD, CS (On)
VD (VS)
The on switch capacitance, measured with reference to ground.
The analog voltage on Terminals D and S.
CIN
RON
The digital input capacitance.
The ohmic resistance between D and S.
tTRANS
RFLAT(ON)
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
Charge Injection
IS (Off)
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
The source leakage current with the switch off.
ID (Off)
Off Isolation
The drain leakage current with the switch off.
A measure of unwanted signal coupling through an off switch.
ID, IS (On)
Crosstalk
The channel leakage current with the switch on.
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
VINL
The maximum input voltage for Logic 0.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
VINH
The minimum input voltage for Logic 1.
On Response
The frequency response of the on switch.
I
INL (IINH)
The input current of the digital input.
Insertion Loss
The loss due to the on resistance of the switch.
CS (Off)
The off switch source capacitance, measured with reference to
ground.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
Rev. A | Page 8 of 16
Data Sheet
ADG1236
TYPICAL PERFORMANCE CHARACTERISTICS
250
200
V
V
= 15V
= –15V
DD
SS
T
= 25°C
A
V
V
= 15V
DD
SS
180
160
140
120
100
80
= –15V
V
V
= 13.5V
= –13.5V
200
150
DD
SS
T
T
= +125°C
= +85°C
A
A
T
= +25°C
= –40°C
A
A
V
V
= 16.5V
= –16.5V
DD
SS
100
T
60
50
0
40
20
0
–15
–10
–5
0
5
10
15
–18 –15 –12 –9 –6 –3
0
3
6
9
12 15 18
TEMPERATURE (°C)
SOURCE OR DRAIN VOLTAGE (V)
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
600
600
V
V
= 12V
= 0V
DD
SS
T
= 25°C
V
V
= 4.5V
= –4.5V
A
DD
SS
T
= +125°C
A
500
400
300
200
500
V
V
= 5V
= –5V
DD
SS
T
= +85°C
A
400
300
T
= +25°C
A
V
V
= 5.5V
= –5.5V
DD
SS
T
= –40°C
A
200
100
0
100
0
0
2
4
6
8
10
12
–6
–4
–2
0
2
4
6
TEMPERATURE (°C)
SOURCE OR DRAIN VOLTAGE (V)
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
0.20
450
V
V
V
= 15V
= –15V
DD
SS
T
= 25°C
V
V
= 10.8V
= 0V
A
DD
SS
400
350
300
250
200
150
100
0.15
0.10
0.05
0
= +10V/–10V
BIAS
V
V
= 12V
= 0V
DD
SS
I
(OFF)
S
V
V
= 13.2V
= 0V
DD
SS
–0.05
–0.10
I
, I (ON)
S
D
–0.15
–0.20
50
0
0
20
40
60
80
100
120
0
2
4
6
8
10
12
14
TEMPERATURE (°C)
SOURCE OR DRAIN VOLTAGE (V)
Figure 6. On Resistance as a Function of VD (VS) for Single Supply
Figure 9. Leakage Currents as a Function of Temperature, Dual Supply
Rev. A | Page 9 of 16
ADG1236
Data Sheet
0.35
220
V
V
V
= 12V
= 0V
DD
SS
0.30
0.25
200
180
160
= 1V/10V
BIAS
A
B
12V SS
OFF ON
A
B
15V DS
OFF ON
0.20
140
120
100
0.15
0.10
0.05
I
, I (ON)
S
D
B
A
12V SS
OFF ON
80
60
I
(OFF)
B
A
15V DS
S
OFF ON
0
–0.05
–0.10
40
20
0
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. tTRANSITION Times vs. Temperature
Figure 10. Leakage Currents as a Function of Temperature, Single Supply
60
0
–10
–20
–30
–40
–50
–60
–70
–80
I
T
PER CHANNEL
= 25°C
V
V
T
= 15V
DD
DD
= –15V
A
SS
= 25°C
50
40
30
20
A
V
V
= 15V
= –15V
DD
SS
V
V
= 12V
DD
10
0
= 0V
SS
–90
–100
0
2
4
6
8
10
12
14
10k
100k
1M
10M
100M
1G
LOGIC, IN (V)
X
FREQUENCY (Hz)
Figure 14. Off Isolation vs. Frequency
Figure 11. IDD vs. Logic Level
6
4
0
–10
–20
–30
–40
–50
–60
–70
–80
T
= 25°C
V
V
T
= 15V
= –15V
= 25°C
A
DD
SS
A
2
V
V
= 15V
= –15V
0
DD
SS
V
V
= 12V
= 0V
DD
SS
BETWEEN
SA AND SB
–2
–4
–6
BETWEEN
S1 AND S2
–90
–100
–15
–10
–5
0
5
10
15
10k
100k
1M
10M
100M
1G
V
(V)
BIAS
FREQUENCY (Hz)
Figure 15. Crosstalk vs. Frequency
Figure 12. Charge Injection vs. Source Voltage
Rev. A | Page 10 of 16
Data Sheet
ADG1236
5
4
0
V
V
= 15V
= –15V
= 25°C
DD
SS
V
V
= 15V
= –15V
= 25°C
DD
SS
T
A
T
A
–5
SOURCE/DRAIN ON
–10
–15
3
2
SOURCE OFF
–20
–25
–30
1
0
–15
–10
–5
0
5
10
15
10k
100k
1M
10M
100M
1G
10G
V
(V)
BIAS
FREQUENCY (Hz)
Figure 16. On Response vs. Frequency
Figure 18. Capacitance vs. Source Voltage for Dual Supply
5
10.00
1.00
LOAD = 10kΩ
SOURCE/DRAIN ON
T
= 25°C
A
4
V
V
= 12V
= 0V
DD
SS
T
= 25°C
A
3
2
V
= 5V, V = –5V, V = 3.5Vrms
SS
DD
S
V
= 15V, V = –15V, V = 5Vrms
SS
DD
S
SOURCE OFF
0.10
0.01
1
0
0
2
4
6
8
10
12
10
100
1k
FREQUENCY (Hz)
10k
100k
V
(V)
BIAS
Figure 17. THD + N vs. Frequency
Figure 19. Capacitance vs. Source Voltage for Single Supply
Rev. A | Page 11 of 16
ADG1236
Data Sheet
TEST CIRCUITS
V
S
D
I
DS
V
S
Figure 20. Test Circuit 1—On Resistance
I
(OFF)
A
I
(OFF)
A
S
D
S
D
V
V
D
S
Figure 21. Test Circuit 2—Off Resistance
I
(ON)
A
D
S
D
NC
V
D
NC = NO CONNECT
Figure 22. Test Circuit 3—On Leakage
V
V
V
DD
SS
0.1F
0.1F
V
IN
50%
50%
50%
50%
V
DD
SS
SB
V
V
IN
S
D
V
OUT
SA
R
300
C
35pF
L
L
90%
90%
IN
V
OUT
V
IN
GND
tON
tOFF
Figure 23. Test Circuit 4—Switching Times
V
V
DD
SS
0.1F
0.1F
V
IN
V
V
SS
DD
SB
V
S
D
V
OUT
SA
80%
V
R
C
OUT
L
L
35pF
300
IN
tBBM
tBBM
V
IN
GND
Figure 24. Test Circuit 5—Break-Before-Make Time Delay
V
V
V
DD
SS
0.1F
0.1F
V
(NORMALLY
IN
CLOSED SWITCH)
V
DD
SS
ON
OFF
SB
NC
V
D
V
S
V
(NORMALLY
IN
OUT
SA
OPEN SWITCH)
C
L
IN
1nF
V
V
OUT
OUT
V
IN
Q
= C V
L
GND
INJ
OUT
Figure 25. Test Circuit 6—Charge Injection
Rev. A | Page 12 of 16
Data Sheet
ADG1236
V
V
V
V
DD
SS
DD
SS
0.1F
0.1F
0.1F
0.1F
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
V
DD
V
DD
SS
SS
NC
50
SA
V
OUT
R
L
SA
SB
50
50
IN
V
S
SB
D
R
D
50
V
OUT
V
IN
R
50
IN
L
V
S
GND
GND
V
V
OUT
OFF ISOLATION = 20 log
V
OUT
S
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
S
Figure 26. Test Circuit 7—Off Isolation
Figure 28. Test Circuit 9—Bandwidth
SS
V
V
V
V
DD
DD
SS
0.1F
0.1F
0.1F
0.1F
AUDIO PRECISION
NETWORK
ANALYZER
V
V
V
DD
V
SS
DD
SS
R
S
NC
50
S
SA
SB
50
IN
IN
V
S
V
S
V p-p
D
D
V
OUT
V
OUT
V
IN
R
L
10k
V
IN
R
L
50
GND
GND
Figure 29. Test Circuit 10—THD + Noise
V
WITH SWITCH
OUT
INSERTION LOSS = 20 log
V
WITHOUT SWITCH
OUT
Figure 27. Test Circuit 8—Channel-to-Channel Crosstalk
Rev. A | Page 13 of 16
ADG1236
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
3.10
3.00 SQ
2.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
10
12
0.50
BSC
1
3
9
7
EXPOSED
PAD
1.45
1.30 SQ
1.15
0.25 MIN
6
4
0.70
0.60
0.50
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
Figure 31. 12-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-12-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
RU-16
RU-16
RU-16
CP-12-4
CP-12-4
ADG1236YRUZ
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
12-Lead Lead Frame Chip Scale Package [LFCSP]
12-Lead Lead Frame Chip Scale Package [LFCSP]
ADG1236YRUZ-REEL
ADG1236YRUZ-REEL7
ADG1236YCPZ-500RL7
ADG1236YCPZ-REEL7
1 Z = RoHS Compliant Part.
Rev. A | Page 14 of 16
Data Sheet
NOTES
ADG1236
Rev. A | Page 15 of 16
ADG1236
NOTES
Data Sheet
©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04776-0-3/16(A)
Rev. A | Page 16 of 16
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