ADG3242_06 [ADI]
2.5 V/3.3 V, 2-Bit Common Control Level Translator Bus Switch; 2.5 V / 3.3 V ， 2位共同控制电平转换器总线开关
| 型号： | ADG3242_06 |
| 厂家： | 
ADI |
| 描述： | 2.5 V/3.3 V, 2-Bit Common Control Level Translator Bus Switch |
| 文件： | 总16页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V/3.3 V, 2-Bit Common Control
Level Translator Bus Switch
ADG3242
FUNCTIONAL BLOCK DIAGRAM
FEATURES
B0
A0
225 ps propagation delay through the switch
4.5 Ω switch connection between ports
Data rate 1.5 Gbps
A1
BE
B1
2.5 V/3.3 V supply operation
Selectable level shifting/translation
Level translation
3.3 V to 2.5 V
Figure 1.
3.3 V to 1.8 V
2.5 V to 1.8 V
Small signal bandwidth 710 MHz
8-lead SOT-23 package
APPLICATIONS
3.3 V to 2.5 V voltage translation
3.3 V to 1.8 V voltage translation
2.5 V to 1.8 V voltage translation
Bus switching
Bus isolation
Hot swap
Hot plug
Analog switch applications
GENERAL DESCRIPTION
internally, allowing for level translation between 3.3 V inputs
and 1.8 V outputs. This makes the device suitable for applications
requiring level translation between different supplies, such as
converter to DSP/microcontroller interfacing.
The ADG3242 is a 2.5 V or 3.3 V, 2-bit, 2-port, common control
digital switch. It is designed on a low voltage CMOS process, and
provides low power dissipation, yet gives high switching speed
and very low on resistance. This allows the inputs to be connected
to the outputs without additional propagation delay or generating
additional ground bounce noise.
PRODUCT HIGHLIGHTS
1. 3.3 V or 2.5 V supply operation.
These switches are enabled by means of a common bus enable
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Level/voltage translation.
BE
(
) input signal. This digital switch allows a bidirectional signal
to be switched when on. In the off condition, signal levels up
to the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is oper-
ated from a 2.5 V supply and 2.5 V inputs are applied, the device
translates the outputs to 1.8 V. In addition, a level translating
5. Tiny SOT-23 package.
SEL
SEL
select pin (
) is included. When
is low, VCC is reduced
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights ofthird parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADG3242
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing Measurement Information.............................................. 11
Bus Switch Applications ................................................................ 12
Mixed Voltage Operation, Level Translation.......................... 12
3.3 V to 2.5 V Translation ......................................................... 12
2.5 V to 1.8 V Translation ......................................................... 12
3.3 V to 1.8 V Translation ......................................................... 12
Bus Isolation................................................................................ 13
Hot Plug and Hot Swap Isolation............................................. 13
Analog Switching ....................................................................... 13
High Impedance during Power-Up/Power-Down................. 13
Outline Dimensions....................................................................... 14
Ordering Guide............................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 6
Terminology .................................................................................... 10
REVISION HISTORY
9/06—Rev. 0 to Rev. A
Updated Format..................................................................Universal
Added Table 4.................................................................................... 5
Changes to the Ordering Guide.................................................... 14
8/03—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADG3242
SPECIFICATIONS
VCC = 2.3 V to 3.6 V, GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
B Version1
Typ2
Parameter
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
Symbol
VINH
Conditions
Min
Max
Unit
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
V
V
Input Low Voltage
VINL
0.8
0.7
1
1
1
2.9
2.1
2.1
V
V
μA
μA
μA
V
Input Leakage Current
Off State Leakage Current
On State Leakage Current
Maximum Pass Voltage
II
IOZ
0.01
0.01
0.01
2.5
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
VP
SEL
SEL
2.0
1.5
1.5
VA/VB = VCC
VA/VB = VCC
=
=
= 3.3 V, IO = −5 μA
= 2.5 V, IO = −5 μA
1.8
V
SEL
1.8
V
VA/VB = VCC = 3.3 V,
= 0 V, IO = −5 μA
CAPACITANCE3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
SWITCHING CHARACTERISTICS3
Propagation Delay A to B or B to A, tPD
CA OFF
CB OFF
CA, CB ON
CIN
f = 1 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
3.5
3.5
7
pF
pF
pF
pF
4
4
tPHL, tPLH
SEL
= 3 V
0.225
5
4.6
4
ns
CL = 50 pF, VCC
=
Propagation Delay Matching5
BE
Bus Enable Time to A or B
ps
ns
6
tPZH, tPZL
SEL
SEL
SEL
SEL
SEL
SEL
1
1
1
1
1
1
3.2
3
VCC = 3.0 V to 3.6 V;
VCC = 3.0 V to 3.6 V;
VCC = 2.3 V to 2.7 V;
VCC = 3.0 V to 3.6 V;
VCC = 3.0 V to 3.6 V;
VCC = 2.3 V to 2.7 V;
= VCC
= 0 V
= VCC
= VCC
= 0 V
= VCC
ns
3
4
ns
6
BE
t
PHZ, tPLZ
3
4
ns
Bus Disable Time to A or B
2.5
2.5
1.5
45
3.8
3.4
ns
ns
Maximum Data Rate
Channel Jitter
SEL
SEL
Gbps
ps p-p
VCC
VCC
=
=
= 3.3 V; VA/VB = 2 V
= 3.3 V; VA/VB = 2 V
DIGITAL SWITCH
On Resistance
RON
SEL
SEL
4.5
12
5
8
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
VCC = 3 V,
VCC = 3 V,
= VCC, VA = 0 V, IBA = 8 mA
= VCC, VA = 1.7 V, IBA = 8 mA
28
9
SEL
VCC = 2.3 V,
VCC = 2.3 V,
= VCC, VA = 0 V, IBA = 8 mA
= VCC, VA = 1 V, IBA = 8 mA
SEL
9
18
8
SEL
5
VCC = 3 V,
VCC = 3 V,
VCC = 3 V,
VCC = 3 V,
= 0 V, VA = 0 V, IBA = 8 mA
= 0 V, VA = 1 V, IBA = 8 mA
= VCC, VA = 0 V, IA = 8 mA
= 0 V, VA = 0 V, IA = 8 mA
SEL
SEL
SEL
12
0.1
0.1
On Resistance Matching
∆RON
0.5
0.5
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
2.3
3.6
1
V
ICC
SEL
SEL
0.01
0.1
μA
mA
μA
Digital inputs = 0 V or VCC;
Digital inputs = 0 V or VCC
= VCC
0.2
8
;
= 0 V
Increase in ICC per Input7
∆ICC
BE
VCC = 3.6 V, = 3.0 V;
SEL
0.15
= VCC
1 Temperature range is as follows: B version: −40°C to +85°C.
2 Typical values are at 25°C, unless otherwise stated.
3 Guaranteed by design, not subject to production test.
4 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation
delay of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5 Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6 See Timing Measurement Information section.
7
BE
This current applies to the Control Pin only. The A and B ports contribute no significant ac or dc currents as they transition.
Rev. A | Page 3 of 16
ADG3242
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
Rating
VCC to GND
Digital Inputs to GND
DC Input Voltage
−0.5 V to +4.6 V
−0.5 V to +4.6 V
−0.5 V to +4.6 V
25 mA per channel
DC Output Current
Only one absolute maximum rating can be applied at any
one time.
Operating Temperature Range
Industrial (B Version)
−40°C to +85°C
−65°C to +150°C
150°C
206°C/W
300°C
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
ESD CAUTION
235°C
Rev. A | Page 4 of 16
ADG3242
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SEL
V
BE
CC
ADI DIE MARK
A0
BE
A0
1
2
3
4
8
7
6
5
V
CC
ADG3242
SEL
B0
ADG3242
TOP VIEW
A1
TOP VIEW
(Not to Scale)
(Not to Scale)
GND
B1
B0
B1
A1
GND
Figure 2. Pin Configuration
Figure 3. Die Pad Configuration (Die size: 550 μm × 820 μm)
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
3
4
5
6
7
8
BE
Bus Enable (Active Low).
Port A0, Input or Output.
Port A1, Input or Output.
Ground (0 V) Reference.
Port B1, Input or Output.
Port B0, Input or Output.
Level Translation Select.
Positive Power Supply Voltage.
A0
A1
GND
B1
B0
SEL
VCC
Table 4. Die Pad Coordinates (Measured from the Center of the Die)
Mnemonic
X(μm)
Y(μm)
+303
+150
−139
−266
−247
+121
+279
+303
BE
+93
A0
A1
GND
B1
B0
+102
+168
+126
−88
−168
−111
−7
SEL
VCC
Table 5. Truth Table
BE
SEL1
Function
L
L
H
L
H
X
A0 = B0, A1 = B1, 3.3 V to 1.8 V Level Shifting.
A0 = B0, A1 = B1, 3.3 V to 2.5 V/2.5 V to 1.8 V Level Shifting.
Disconnect.
1 SEL
= 0 V only when VDD = 3.3 V 10ꢀ.
Rev. A | Page 5 of 16
ADG3242
TYPICAL PERFORMANCE CHARACTERISTICS
40
20
15
10
5
T
= 25°C
A
V
= 3.3V
CC
V
= 3V
CC
SEL = V
CC
SEL = V
CC
35
30
25
20
15
10
5
V
= 3.3V
CC
CC
+85°C
+25°C
V
= 3.6V
3.0
–40°C
0
0
0
0
0
0.5
1.0
1.5
2.0
/V (V)
2.5
3.5
3.0
3.5
0
0.5
1.0
V /V (V)
A
1.5
2.0
V
A
B
B
Figure 4. On Resistance vs. Input Voltage
Figure 7. On Resistance vs. Input Voltage for Different Temperatures
40
35
30
25
20
15
10
5
15
T
= 25°C
V
= 2.5V
A
CC
V
= 2.3V
CC
SEL = V
SEL = V
CC
CC
10
V
= 2.5V
= 2.7V
CC
CC
+85°C
–40°C
5
V
+25°C
0
0
0.5
1.0
1.5
/V (V)
2.0
2.5
0
0.5
1.0
1.2
V
V /V (V)
A B
A
B
Figure 5. On Resistance vs. Input Voltage
Figure 8. On Resistance vs. Input Voltage for Different Temperatures
40
35
30
25
20
15
10
5
3.0
T
= 25°C
A
V
= 3.6V
T
= 25°C
SEL = 0V
CC
A
V
= 3V
CC
SEL = V
= –5µA
O
CC
I
2.5
2.0
1.5
1.0
0.5
0
V
= 3.3V
CC
V
= 3.3V
= 3.6V
CC
V
= 3V
CC
V
CC
0
0.5
1.0
1.5
2.0
/V (V)
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
V /V (V)
A B
A
B
Figure 6. On Resistance vs. Input Voltage
Figure 9. Pass Voltage vs. VCC
Rev. A | Page 6 of 16
ADG3242
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
T
V
= 25°C
= 0V
A
A
V
= 2.7V
CC
SEL = V
CC
= –5µA
A
I
BE = 0
O
V
= 2.5V
CC
V
= 3.3V; SEL = 0V
CC
V
= 2.3V
CC
V
= SEL = 3.3V
CC
V
= SEL = 2.5V
CC
0
0
0
0.5
1.0
1.5
/V (V)
2.0
2.5
3.0
3.5
50
0
0.02
0.04
0.06
0.08
0.10
V
I (A)
O
A
B
Figure 10. Pass Voltage vs. VCC
Figure 13. Output Low Characteristic
3.0
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
T
= 25°C
T
V
= 25°C
A
A
V
= 3.6V
CC
SEL = 0V
= V
CC
A
I
= –5µA
BE = 0
O
V
= SEL = 3.3V
CC
V
= 3.3V
CC
V
= 3V
CC
V
= SEL = 2.5V
CC
V
= 3.3V; SEL = 0V
CC
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.5
1.0
1.5
V
2.0
/V (V)
2.5
3.0
I
(A)
O
A
B
Figure 14. Output High Characteristic
Figure 11. Pass Voltage vs. VCC
0
500
450
400
350
300
250
200
150
100
50
T
= 25°C
T
= 25°C
A
A
SEL = V
CC
–0.2 ON→OFF
= 1nF
C
L
V
= 2.5V
= 3.3V
CC
–0.4
–0.6
–0.8
–1.0
–1.2
V
= SEL = 3.3V
CC
V
CC
V
= 3.3V;
CC
SEL = 0V
V
= SEL = 2.5V
CC
0
0
0.5
1.0
1.5
2.0
2.5
3.0
5
10
15
20
25
30
35
40
45
V
/V (V)
B
ENABLE FREQUENCY (MHz)
A
Figure 12. ICC vs. Enable Frequency
Figure 15. Charge Injection vs. Source Voltage
Rev. A | Page 7 of 16
ADG3242
2
1
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
ENABLE
V
= SEL = 3.3V
CC
0
–1
–2
–3
–4
DISABLE
V
= 3.3V; SEL = 0V
CC
T
= 25°C
= 3.3V/2.5V
A
–5
–6
–7
–8
V
CC
SEL = V
CC
= 0dBm
V
IN
N/W ANALYZER:
= R = 50Ω
R
L
S
0.03 0.1
1
10
100
1000
1000
1000
–40
–20
0
20
40
60
80
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 19. Enable/Disable Time vs. Temperature
Figure 16. Bandwidth vs. Frequency
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
T
V
= 25°C
A
= 3.3V/2.5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CC
SEL = V
CC
= 0dBm
V
IN
N/W ANALYZER:
= R = 50Ω
ENABLE
V
= SEL = 2.5V
CC
R
L
S
DISABLE
–40
–20
0
20
40
60
80
0.03 0.1
1
10
100
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 20. Enable/Disable Time vs. Temperature
Figure 17. Crosstalk vs. Frequency
100
90
80
70
60
50
40
30
20
10
0
0
T
= 25°C
A
V
V
= SEL = 3.3V
CC
= 1.5V p-p
V
= 3.3V/2.5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CC
IN
20dB ATTENUATION
SEL = V
CC
= 0dBm
V
IN
N/W ANALYZER:
R
= R = 50Ω
L
S
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
0.1
1
10
100
DATA RATE (Gbps)
FREQUENCY (MHz)
Figure 21. Jitter vs. Data Rate; PRBS 31
Figure 18. Off Isolation vs. Frequency
Rev. A | Page 8 of 16
ADG3242
100
95
90
85
80
75
70
65
60
55
50
V
V
= SEL = 3.3V
CC
= 1.5V p-p
IN
20dB ATTENUATION
V
= 2.5V
CC
SEL = 2.5V
= 1.5V p-p
20dB
ATTENUATION
T = 25°C
A
20mV/DIV
200ps/DIV
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD) × 100%
V
IN
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
DATA RATE (Gbps)
Figure 22. Eye Width vs. Data Rate; PRBS 31
Figure 24. Eye Pattern; 1.244 Gbps, VCC = 2.5 V; PRBS 31
V
= 3.3V
CC
SEL = 3.3V
= 1.5V p-p
20dB
ATTENUATION
T = 25°C
A
50mV/DIV
200ps/DIV
V
IN
Figure 23. Eye Pattern; 1.5 Gbps, VCC = 3.3 V; PRBS 31
Rev. A | Page 9 of 16
ADG3242
TERMINOLOGY
VCC
CIN
Positive power supply voltage.
BE
SEL
and .
Control input capacitance. This consists of
GND
ICC
Ground (0 V) reference.
Quiescent power supply current. This current represents the
leakage current between the VCC and ground pins. It is measured
when all control inputs are at logic high or low level and the
switches are off.
VINH
Minimum input voltage for Logic 1.
VINL
ΔICC
Maximum input voltage for Logic 0.
EN
Extra power supply current component for the
when the input is not driven at the supplies.
control input
II
Input leakage current at the control inputs.
tPLH, tPHL
Data propagation delay through the switch in the on state. Propaga-
tion delay is related to the RC time constant RON × CL, where CL
is the load capacitance.
IOZ
Off state leakage current. It is the maximum leakage current at
the switch pin in the off state.
tPZH, tPZL
IOL
Bus enable times. These are the times taken to cross the VT in
On state leakage current. It is the maximum leakage current at
the switch pin in the on state.
BE
response to the control signal,
.
tPHZ, tPLZ
VP
Bus disable times. These are the times taken to place the switch
in the high impedance off state in response to the control signal.
They are measured as the time taken for the output voltage to
change by VΔ from the original quiescent level, with reference
to the logic level transition at the control input. (See Figure 27
for enable and disable times.)
Maximum pass voltage. The maximum pass voltage relates to
the clamped output voltage of an NMOS device when the switch
input voltage is equal to the supply voltage.
RON
Ohmic resistance offered by a switch in the on state. It is measured
at a given voltage by forcing a specified amount of current through
the switch.
Max Data Rate
Maximum rate at which data can be passed through the switch.
ΔRON
Channel Jitter
On resistance match between any two channels, that is, RON max
to RON min.
Peak-to-peak value of the sum of the deterministic and random
jitter of the switch channel.
CX OFF
Off switch capacitance.
CX ON
On switch capacitance.
Rev. A | Page 10 of 16
ADG3242
TIMING MEASUREMENT INFORMATION
DISABLE
ENABLE
For the following load circuit and waveforms, the notation that
V
V
INH
T
is used is VIN and VOUT where:
CONTROL INPUT BE
0V
V
IN = VA and VOUT = VB, or VIN = VB and VOUT = VA
tPZL
tPLZ
V
CC
V
2 × V
CC
CC
V
CC
V
SW1
OUT
V
V
V
= 0V
= V
T
IN
SW1 @ 2V
V
V
+ V
CC
L
L
Δ
GND
R
tPZH
tPHZ
L
V
V
OUT
IN
V
V
H
H
PULSE
GENERATOR
V
DUT
OUT
SW1 @ GND
–V
V
IN
CC
Δ
T
0V
0V
R
R
C
L
L
T
Figure 27. Enable and Disable Times
NOTES
Table 6. Switch Position
Test
1. PULSE GENERATOR FOR ALL PULSES: tR ≤ 2.5ns, tF ≤ 2.5ns,
FREQUENCY ≤ 10MHz.
S1
2. C INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
L
3. R IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO Z
OF THE PULSE GENERATOR.
T
OUT
tPLZ, tPZL
tPHZ, tPZH
2 × VCC
GND
Figure 25. Load Circuit
V
V
IH
CONTROL
INPUT BE
T
0V
tPLH
tPLH
V
V
H
V
T
OUT
V
L
Figure 26. Propagation Delay
Table 7. Test Conditions
VCC = 3.3 V 0.3 V (SEL = VCC
)
VCC = 2.5 V 0.2 V (SEL = VCC
)
VCC = 3.3 V 0.3 V (SEL = 0 V)
Symbol
Unit
Ω
mV
pF
V
RL
VΔ
CL
VT
500
300
50
500
150
30
500
150
30
1.5
0.9
0.9
Rev. A | Page 11 of 16
ADG3242
BUS SWITCH APPLICATIONS
MIXED VOLTAGE OPERATION, LEVEL
TRANSLATION
2.5 V TO 1.8 V TRANSLATION
SEL
When VCC is 2.5 V (
= 2.5 V) and the input signal range is
Bus switches provide an ideal solution for interfacing between
mixed voltage systems. The ADG3242 is suitable for applications
where voltage translation from 3.3 V technology to a lower voltage
technology is needed. This device translates from 3.3 V to 1.8 V,
from 2.5 V to 1.8 V, or from a bidirectional 3.3 V directly to 2.5 V.
0 V to VCC, the maximum output signal is also clamped within
a voltage threshold below the VCC supply. In this case, the output
is limited to approximately 1.8 V, as shown in Figure 32.
2.5V
Figure 28 shows a block diagram of a typical application in which a
user needs to interface between a 3.3 V ADC and a 2.5 V micro-
processor. The microprocessor does not have 3.3 V tolerant inputs,
therefore, placing the ADG3242 between the two devices allows
the devices to communicate easily. The bus switch directly connects
the two blocks, therefore introducing minimal propagation delay,
2.5V
ADG3242
1.8V
SEL
Figure 31. 2.5 V to 1.8 V Voltage Translation,
= 2.5 VCC
V
timing skew, or noise.
OUT
2.5V SUPPLY
SEL = 2.5V
3.3V
3.3V
2.5V
1.8V
2.5V
3.3V ADC
MICROPROCESSOR
Figure 28. Level Translation Between a 3.3 V ADC and a 2.5 V Microprocessor
V
IN
SWITCH
INPUT
0V
2.5V
3.3 V TO 2.5 V TRANSLATION
SEL
Figure 32. 2.5 V to 1.8 V Voltage Translation,
= VCC
SEL
When VCC is 3.3 V (
= 3.3 V) and the input signal range is
3.3 V TO 1.8 V TRANSLATION
0 V to VCC, the maximum output signal is clamped to within a
voltage threshold below the VCC supply. In this case, the output
is limited to 2.5 V, as shown in Figure 30. This device can be used
for translation from 2.5 V to 3.3 V devices and also between two
The ADG3242 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the
pin is an active low control pin.
nal circuitry in the ADG3242 that allows voltage translation
between 3.3 V devices and 1.8 V devices.
SEL
SEL
SEL
activates inter-
pin. The
3.3 V devices.
3.3V
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal is clamped to 1.8 V, as shown in Figure 34.
3.3V
2.5V
2.5V
2.5V
ADG3242
SEL
SEL
To do this, the
pin must be tied to Logic 0. If
is unused,
it can be tied directly to VCC.
3.3V
SEL
Figure 29. 3.3 V to 2.5 V Voltage Translation,
= VCC
V
OUT
3.3V SUPPLY
SEL = 3.3V
3.3V
ADG3242
1.8V
2.5V
SEL
Figure 33. 3.3 V to 1.8 V Voltage Translation,
= 0 V
V
V
OUT
IN
3.3V SUPPLY
SEL = 0V
SWITCH
INPUT
0V
3.3V
1.8V
SEL
Figure 30. 3.3 V to 2.5 V Voltage Translation,
= VCC
V
IN
SWITCH
INPUT
0V
3.3V
SEL
Figure 34. 3.3 V to 1.8 V Voltage Translation,
= 0 V
Rev. A | Page 12 of 16
ADG3242
BUS ISOLATION
PLUG-IN
CARD (1)
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the spec-
ifications. Because the ADG3242 is designed specifically for
applications that do not need drive, yet require simple logic func-
tions, it solves this requirement. The device isolates access to
the bus, thus minimizing capacitance loading.
CARD I/O
CPU
RAM
PLUG-IN
CARD (2)
CARD I/O
BUS
Figure 36. ADG3242 in a Hot Plug Application
LOAD A
LOAD C
There are many systems, such as docking stations, PCI boards for
servers, and line cards for telecommunications switches, that
require the ability to handle hot swapping. If the bus can be isolated
prior to insertion or removal, there is more control over the hot
swap event. This isolation can be achieved using bus switches. The
bus switches are positioned on the hot swap card between the con-
nector and the devices. During hot swap, the ground pin of the
hot swap card must connect to the ground pin of the backplane
before connecting to any other signal or power pins.
BUS/
BACKPLANE
LOAD B
LOAD D
BUS SWITCH
LOCATION
Figure 35. Location of Bus Switched in a Bus Isolation Application
HOT PLUG AND HOT SWAP ISOLATION
The ADG3242 is suitable for hot swap and hot plug applications.
The output signal of the ADG3242 is limited to a voltage that
is below the VCC supply, as shown in Figure 30, Figure 32, and
Figure 34. Thus, the switch acts like a buffer to take the impact
from the hot insertion, protecting vital and expensive chipsets
from damage.
ANALOG SWITCHING
Bus switches are used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller on and off channel capacitance, and better
frequency performance than their analog counterparts. The
bus switch channel itself, consisting solely of an NMOS switch,
limits the operating voltage (see Figure 4 for a typical plot), but
in many cases, this does not present an issue.
In hot plug applications, the system cannot be shut down when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 36 shows a typical example of this type of application.
HIGH IMPEDANCE DURING POWER-UP/POWER-
DOWN
To ensure the high impedance state during power-up or power-
BE
down,
must be tied to VCC through a pull-up resistor. The
minimum value of the resistor is determined by the current sink-
ing capability of the driver.
Rev. A | Page 13 of 16
ADG3242
OUTLINE DIMENSIONS
2.90 BSC
8
1
7
2
6
3
5
4
1.60 BSC
2.80 BSC
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8°
4°
0°
0.38
0.22
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 37. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Branding
SCA
SCA
SCA
SOU
ADG3242BRJ-R2
ADG3242BRJ-REEL
ADG3242BRJ-REEL7
ADG3242BRJZ-REEL71
ADG3242BCZ-SF31
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
8-Lead Small Outline Transistor [SOT-23] RJ-8
8-Lead Small Outline Transistor [SOT-23] RJ-8
8-Lead Small Outline Transistor [SOT-23] RJ-8
8-Lead Small Outline Transistor [SOT-23] RJ-8
Die
Chip
1 Z = Pb-free part.
Rev. A | Page 14 of 16
ADG3242
NOTES
Rev. A | Page 15 of 16
ADG3242
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04309-0-9/06(A)
Rev. A | Page 16 of 16
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