ADG3257BRQZ-REEL [ADI]
High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux (4-Bit, 1 of 2) Bus Switch; 高速， 3.3 V / 5 V四路2 ： 1复用器/解复用器（ 4位， 1 2 ）总线开关
| 型号： | ADG3257BRQZ-REEL |
| 厂家： | 
ADI |
| 描述： | High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux (4-Bit, 1 of 2) Bus Switch |
| 文件： | 总12页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux
(4-Bit, 1 of 2) Bus Switch
ADG3257
FUNCTIONAL BLOCK DIAGRAM
FEATURES
1B
1
1A
2A
3A
4A
100 ps propagation delay through the switch
2 Ω switches connect inputs to outputs
Data rates up to 933 Mbps
Single 3.3 V/5 V supply operation
Level translation operation
1B
2B
2
1
2B
3B
3B
4B
2
1
2
1
Ultralow quiescent supply current (1 nA typical)
3.5 ns switching
4B
2
Switches remain in the off state when power is off
Standard 3257 type pinout
APPLICATIONS
LOGIC
Bus switching
Bus isolation
Level translation
Memory switching/interleaving
S
BE
Figure 1.
GENERAL DESCRIPTION
The ADG3257 is a CMOS bus switch comprised of four 2:1
multiplexers/demultiplexers with high impedance outputs. The
device is manufactured on a CMOS process. This provides low
power dissipation yet high switching speed and very low on
resistance, allowing the inputs to be connected to the outputs
without adding propagation delay or generating additional
ground bounce noise.
PRODUCT HIGHLIGHTS
1. 0.1 ns propagation delay through switch.
2. 2 Ω switches connect inputs to outputs.
3. Bidirectional operation.
4. Ultralow power dissipation.
5. 16-lead QSOP package.
The ADG3257 operates from a single 3.3 V/5 V supply. The
control logic for each switch is shown in Table 1. These switches
are bidirectional when on. In the off state, signal levels are blocked
up to the supplies. When the power supply is off, the switches
remain in the off state, isolating Port A and Port B.
This bus switch is suited to both switching and level translation
applications. It can be used in applications requiring level trans-
lation from 3.3 V to 2.5 V when powered from 3.3 V. Additionally,
with a diode connected in series with 5 V VDD, the ADG3257
may also be used in applications requiring 5 V to 3.3 V level
translation.
Table 1. Truth Table
BE
S
Function
H
L
L
X
L
H
Disable
A = B1
A = B2
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no re-
sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.
ADG3257
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Test Circuits........................................................................................9
Applications Information.............................................................. 10
Mixed Voltage Operation, Level Translation.......................... 10
Memory Switching..................................................................... 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
03/08—Rev. D to Rev. E
Updated Format.................................................................... Universal
Changes to Features.............................................................................1
Changes to General Description .......................................................1
Changes to Absolute Maximum Ratings..........................................5
Changes to Pin Configuration and Function Descriptions ...........6
Changes to Test Circuits .....................................................................9
Changes to Ordering Guide ...............................................................11
11/04—Rev. C to Rev. D
Changes to Specifications...................................................................2
Changes to Ordering Guide ...............................................................4
04/03—Rev. A to Rev. B
Updated Outline Dimensions............................................................8
06/02—Rev. 0 to Rev. A
Edits to Features...................................................................................1
Rev. E | Page 2 of 12
ADG3257
SPECIFICATIONS
VCC = 5.0 V 10ꢀ, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
B Version
Typ3
Parameter1
Symbol
Conditions2
Min
Max Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Leakage Current
Off State Leakage Current
On State Leakage Current
Maximum Pass Voltage4
CAPACITANCE4
VINH
VINL
II
IOZ
IOZ
VP
2.4
−0.3
V
V
μA
μA
μA
V
+0.8
1
1
1
4.4
0 ≤ VIN ≤ 5.5 V
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
VIN = VCC = 5 V, IO = −5 μA
0.01
0.01
0.01
4.2
3.9
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
SWITCHING CHARACTERISTICS4
Propagation Delay A to B or B to A, tPD tPHL, tPLH
Propagation Delay Matching6
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B
Bus Select Time S to A or B
Enable
CA OFF
CB OFF
CA, CB ON f = 1 MHz
f = 1 MHz
f = 1 MHz
7
5
11
4
pF
pF
pF
pF
CIN
f = 1 MHz
5
VA = 0 V, CL = 50 pF
VA = 0 V, CL = 50 pF
CL = 50 pF, RL = 500 Ω
CL = 50 pF, RL = 500 Ω
0.10
ns
0.0075 0.035 ns
5
t
t
PZH, tPZL
PHZ, tPLZ
1
1
7.5
7
ns
ns
3.5
tSEL_EN
tSEL_DIS
CL = 50 pF, RL = 500 Ω
CL = 50 pF, RL = 500 Ω
VA = 2 V p-p
8
5
933
12
8
ns
ns
Mbps
Disable
Maximum Data Rate
DIGITAL SWITCH
On Resistance
RON
VA = 0 V
IO = 48 mA, 15 mA, 8 mA, TA = 25°C
IO = 48 mA, 15 mA, 8 mA
VA = 2.4 V
2
4
5
Ω
Ω
IO = 48 mA, 15 mA, 8 mA, TA = 25°C
IO = 48 mA, 15 mA, 8 mA
VA = 0 V, IO = 48 mA, 15 mA, 8 mA
3
6
7
Ω
Ω
Ω
On-Resistance Matching
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
Increase in ICC per Input4, 7
ΔRON
0.15
3.0
5.5
1
200
V
μA
μA
ICC
ΔICC
Digital inputs = 0 V or VCC
VCC = 5.5 V, one input at 3.0 V; others at VCC or GND
0.001
1 Temperature range is: Version B: –40°C to +85°C.
2 See Test Circuits section.
3 All typical values are at TA = 25°C, unless otherwise noted.
4 Guaranteed by design, not subject to production test.
5 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation
delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6 Propagation delay matching between channels is calculated from on-resistance matching of worst-case channel combinations and load capacitance.
7 This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute
no significant ac or dc currents as they transition.
Rev. E | Page 3 of 12
ADG3257
VCC = 3.3 V 10ꢀ, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Version
Min Typ3 Max Unit
Parameter1
Symbol
Conditions2
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Leakage Current
Off State Leakage Current
On State Leakage Current
Maximum Pass Voltage4
CAPACITANCE4
VINH
VINL
II
IOZ
IOZ
VP
2.0
−0.3
V
V
μA
μA
μA
V
+0.8
1
1
1
2.8
0 ≤ VIN ≤ 3.6 V
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
VIN = VCC = 3.3 V, IO = −5 μA
0.01
0.01
0.01
2.3
2.6
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
SWITCHING CHARACTERISTICS4
Propagation Delay A to B or B to A, tPD
Propagation Delay Matching6
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B
Bus Select Time S to A or B
Enable
CA OFF
CB OFF
CA, CB ON f = 1 MHz
f = 1 MHz
f = 1 MHz
7
5
11
4
pF
pF
pF
pF
CIN
f = 1 MHz
5
tPHL, tPLH
VA = 0 V, CL = 50 pF
VA = 0 V, CL = 50 pF
CL = 50 pF, RL = 500 Ω
CL = 50 pF, RL = 500 Ω
0.10 ns
0.04 ns
0.01
5.5
t
t
PZH, tPZL
PHZ, tPLZ
1
1
9
ns
ns
4.5
8.5
tSEL_EN
tSEL_DIS
CL = 50 pF, RL = 500 Ω
CL = 50 pF, RL = 500 Ω
VA = 2 V p-p
8
6
933
12
9
ns
ns
Mbps
Disable
Maximum Data Rate
DIGITAL SWITCH
On Resistance
RON
VA = 0 V, IO = 15 mA, 8 mA, TA = 25°C
VA= 0 V, Io = 15 mA, 8 mA
VA = 1 V, IO = 15 mA, 8 mA, TA = 25°C
VA= 1 V, Io = 15 mA, 8 mA
2
4
5
7
8
Ω
Ω
Ω
Ω
Ω
4
On-Resistance Matching
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
Increase in ICC per Input4, 7
ΔRON
VA = 0 V, IO = 15 mA, 8 mA
0.2
3.0
5.5
1
200
V
μA
μA
ICC
ΔICC
Digital inputs = 0 V or VCC
VCC = 3.3 V, one input at 3.0 V; others at VCC or GND
0.001
1 Temperature range is: Version B: −40°C to +85°C.
2 See Test Circuits section.
3 All typical values are at TA = 25°C, unless otherwise noted.
4 Guaranteed by design, not subject to production test.
5 The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Because the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation
delay of the digital switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6 Propagation delay matching between channels is calculated from on-resistance matching of worst-case channel combinations and load capacitance.
7 This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports contribute
no significant ac or dc currents as they transition.
Rev. E | Page 4 of 12
ADG3257
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tion of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
VCC to GND
Digital Inputs to GND
DC Input Voltage
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
100 mA
DC Output Current
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
QSOP Package
−40°C to +85°C
−65°C to +150°C
150°C
ESD CAUTION
θJA Thermal Impedance
Lead Soldering
149.97°C/W
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature (<20 sec)
Soldering (Pb-Free)
300°C
220°C
Reflow, Peak Temperature
Time at Peak Temperature
260(+0/−5)°C
20 sec to 40 sec
Rev. E | Page 5 of 12
ADG3257
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
V
CC
1B
BE
4B
1
2
1B
ADG3257
1
TOP VIEW
1A
4B
4A
3B
3B
3A
(Not to Scale)
2
2B
1
2
2B
1
2
2A
GND
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
S
Port Select.
2, 3, 5, 6, 10, 11, 13, 14
4, 7, 9, 12
8
15
16
1B1, 1B2, 2B1, 2B2, 3B2, 3B1, 4B2, 4B1
1A, 2A, 3A, 4A
GND
BE
Port B, Inputs or Outputs.
Port A, Inputs or Outputs.
Negative Power Supply.
Output Enable (Active Low).
Positive Power Supply.
VCC
Rev. E | Page 6 of 12
ADG3257
TYPICAL PERFORMANCE CHARACTERISTICS
20
15
10
5
20
V
= 3V
T
= 25°C
CC
A
16
12
8
V
= 5.0V
CC
+85°C
V
= 4.5V
+25°C
CC
4
–40°C
V
= 5.5V
CC
4
0
0
0
0.5
1.0
1.5
/V (V)
2.0
2.5
3.0
0
1
2
3
5
V
A
B
V
/V (V)
B
A
Figure 6. On Resistance vs. Input Voltage for Different Temperatures
Figure 3. On Resistance vs. Input Voltage
20
16
12
8
10m
T
= 25°C
A
T
= 25°C
A
1m
100µ
10µ
V
= 3.0V
CC
V
V
= 5V
= 3V
CC
CC
V
= 2.7V
CC
1µ
4
V
= 3.3V
100n
CC
0
10n
0.1
0
0.5
1.0
1.5
/V (V)
2.0
2.5
3.0
1
10
100
1k
10k
V
A
B
FREQUENCY (kHz)
Figure 4. On Resistance vs. Input Voltage
Figure 7. ICC vs. Enable Frequency
20
15
10
5
5
4
3
2
1
0
V
= 5V
T
= 25°C
CC
A
V
= 5.5V
CC
V
= 5.0V
CC
V
= 4.5V
CC
+85°C
+25°C
–40°C
0
0
1
2
3
4
5
0
1
2
3
4
5
V
/V (V)
B
INPUT VOLTAGE (V)
A
Figure 8. Maximum Pass Voltage
Figure 5. On Resistance vs. Input Voltage for Different Temperatures
Rev. E | Page 7 of 12
ADG3257
3.6
T
= 25°C
A
V
= 3.6V
CC
3.0
2.0
1.0
0
V
= 3.3V
CC
V
= 3.0V
CC
40mV/DIV
180ps/DIV
V
V
= 5V
= 2V p-p
933MBPS
20dB ATTENUATION
T = 25°C
A
CC
IN
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
INPUT VOLTAGE (V)
Figure 9. Maximum Pass Voltage
Figure 11. 933 Mbps Eye Diagram
40mV/DIV
267ps/DIV
V
V
= 5V
= 2V p-p
622MBPS
20dB ATTENUATION
T = 25°C
A
CC
IN
Figure 10. 622 Mbps Eye Diagram
Rev. E | Page 8 of 12
ADG3257
TEST CIRCUITS
V
Table 6. Switch S1 Condition
Test
CC
2 × V
CC
S1
S1
OPEN
GND
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
tSEL
Open
2 × VCC
GND
Open
R
R
L
V
V
OUT
IN
PULSE
DUT
1
GENERATOR
2
C
3
L
R
L
T
Table 7. Test Conditions
1
2
3
PULSE GENERATOR FOR ALL PULSES: tF < 2.5ns, tR < 2.5ns.
C
= INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
Symbol
VCC = 5 V 10%
VCC = 3.3 V 10%
Unit
Ω
mV
pF
L
R
ISTHETERMINATION RESISTOR; SHOULD BE EQUALTO Z
OF THE
T
OUT
RL
ΔV
CL
500
300
50
500
300
50
PULSE GENERATOR.
Figure 12. Load Circuit
V
V
IH
T
SWITCH INPUT
OUTPUT
0V
tPLH
tPHL
V
V
V
OH
T
OL
Figure 13. Propagation Delay
DISABLE
ENABLE
V
V
IH
T
CONTROL INPUTS
OUTPUT
0V
tPZL
tPLZ
V
V
CC
T
V
V
V
CC
+ ΔV
S1 @ 2V
CC
OL
OL
LOW
tPHZ
tPZH
V
V
OUTPUT
OH
OH
V
– ΔV
T
S1 @ 2V
CC
0V
0V
Figure 14. Select, Enable, and Disable Times
Rev. E | Page 9 of 12
ADG3257
APPLICATIONS INFORMATION
MIXED VOLTAGE OPERATION, LEVEL TRANSLATION
Similarly, the device could be used to translate bidirectionally
between 3.3 V to 2.5 V systems. In this case, there is no need for
an external diode. The internal VTH drop is 1 V, so with a
Bus switches can be used to provide a solution for mixed voltage
systems where interfacing bidirectionally between 5 V and 3.3 V
devices is required. To interface between 5 V and 3.3 V buses,
an external diode is placed in series with the 5 V power supply
as shown in Figure 15.
VCC = 3.3 V the bus switch limits the output voltage to
V
CC − 1 V = 2.3 V
V
= 5V
CC
V
OUT
3.3V
3.3V SUPPLY
2.5V
3.3V
2.5V
2.5V
2.5V
BE
ADG3257
3.3V CPU/DSP/
MICROPROCESSOR/
MEMORY
5V MEMORY
5V I/O
V
IN
SWITCH
INPUT
3.3V
0V
Figure 17. 3.3 V to 2.5 V Level Translation Using the ADG3257 Bus Switch
3.3V
5V
3.3V
3.3V
MEMORY SWITCHING
Figure 15. Level Translation Between 5 V and 3.3 V Devices
This quad bus switch may be used to allow switching between
different memory banks, thus allowing additional memory and
decreasing capacitive loading. Figure 18 illustrates the
ADG3257 in such an application.
The diode drops the internal gate voltage down to 4.3 V. The
bus switch limits the voltage present on the output to
V
CC − External Diode Drop = VTH
Therefore, assuming a diode drop of 0.7 V and a VTH of 1 V, the
output voltage is limited to 3.3 V with a logic high.
SDRAM NO. 1
SDRAM NO. 2
V
OUT
5V SUPPLY
3.3V
SDRAM NO. 7
SDRAM NO. 8
LOGIC
V
IN
SWITCH
INPUT
5V
0V
Figure 16. Input Voltage to Output Voltage
S
BE
Figure 18. Allows Additional Memory Modules Without Added Drive or Delay
Rev. E | Page 10 of 12
ADG3257
OUTLINE DIMENSIONS
0.197
0.193
0.189
16
1
9
8
0.158
0.154
0.150
0.244
0.236
0.228
PIN 1
0.069
0.053
0.065
0.049
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
0.050
0.016
SEATING
PLANE
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137-AB
Figure 19. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
ORDERING GUIDE
Model
ADG3257BRQ
ADG3257BRQ-REEL
ADG3257BRQ-REEL7
ADG3257BRQZ1
ADG3257BRQZ-REEL1
ADG3257BRQZ-REEL71
Temperature Range
–40°C to +85°C
Package Description
Package Option
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
16-Lead Shrink Small Outline Package [QSOP]
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
1 Z = RoHS Compliant Part.
Rev. E | Page 11 of 12
ADG3257
NOTES
©2002–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02914-0-3/08(E)
Rev. E | Page 12 of 12
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